From bb94121a4071139c80ee3d97bec6da931395c7b8 Mon Sep 17 00:00:00 2001 From: munailwaqar Date: Thu, 5 Dec 2024 15:10:20 +0500 Subject: [PATCH] documentation --- .../cv32a65x/isa/isa.adoc | 13 ++ .../cv32a65x/isa/isa.rst | 21 +++ core/alu.sv | 27 +-- .../RISCV_Instructions_RVZbkb.rst | 169 ++++++++++++++++++ 4 files changed, 217 insertions(+), 13 deletions(-) create mode 100644 docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc index c187bcbbb6..ec9951a720 100644 --- a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc +++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc @@ -22,6 +22,7 @@ |Zbc | RVZbc Carry-less multiplication | Carry-less multiplication is the multiplication in the polynomial ring over GF(2).clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product.clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product. |Zbs | RVZbs Single bit Instructions | The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. |Zicntr | Zicntr | No info found yet for extension Zicntr +|Zbkb | RVZbkb Bitmanip instructions for Cryptography | The Zbkb extension is a part of the RISC-V Bit-Manipulation (bitmanip) extensions, specifically targeting cryptographic applications. It introduces a set of instructions designed to facilitate operations commonly used in cryptographic algorithms, such as interleaving, packing, and reordering of bits. |=== ==== RV32I Base Integer Instructions @@ -221,3 +222,15 @@ | BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations |=== +==== RVZbkb Bitmanip instructions for Cryptography + +|=== +| Name | Format | Pseudocode|Invalid_values | Exception_raised | Description| Op Name + +| PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions +| PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions +| PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions +| ZIP | zip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions +| UNZIP | unzip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions +| BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse +|=== diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst index 2d02548c4e..864f3b49ff 100644 --- a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst +++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst @@ -47,6 +47,8 @@ Instructions +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Zicntr | Zicntr_ | No info found yet for extension Zicntr | +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Zbkb | RVZbkb Bitmanip instructions for Cryptography_ | The Zbkb extension is a part of the RISC-V Bit-Manipulation (bitmanip) extensions, specifically targeting cryptographic applications. It introduces a set of instructions designed to facilitate operations commonly used in cryptographic algorithms, such as interleaving, packing, and reordering of bits. | ++---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ RV32I Base Integer Instructions ------------------------------- @@ -394,3 +396,22 @@ RVZbs Single bit Instructions | BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) | (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations | +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+ +RVZbkb Bitmanip instructions for Cryptography +------------------------------------- + + ++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ +| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name | ++===========+========================+==========================================+==================+====================+===========================================================================================================================================================================================================================+==========================================================================================================================+ +| PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions | ++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ +| PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions | ++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ +| PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions | ++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ +| ZIP | zip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions | ++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ +| UNZIP | unzip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions | ++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ +| BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse | ++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ diff --git a/core/alu.sv b/core/alu.sv index 4c2e7ebdf9..2cd5de7624 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -52,10 +52,8 @@ module alu logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result; logic [CVA6Cfg.XLEN-1:0] brev8_reversed; - logic [ 15:0] unzip_gen_hi; - logic [ 15:0] unzip_gen_lo; - logic [ 31:0] zip_gen_even; - logic [ 31:0] zip_gen_odd; + logic [ 31:0] unzip_gen; + logic [ 31:0] zip_gen; // bit reverse operand_a for left shifts and bit counting generate genvar k; @@ -279,13 +277,15 @@ module alu end end // Generate zip and unzip results - for (n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen - // Assigning lower and upper half of operand into the even and odd positions of result - assign zip_gen_even[n<<1] = fu_data_i.operand_a[n]; - assign zip_gen_odd[(n<<1)+1] = fu_data_i.operand_a[n+CVA6Cfg.XLEN/2]; - // Assigning even and odd bits of operand into lower and upper halves of result - assign unzip_gen_lo[n] = fu_data_i.operand_a[n<<1]; - assign unzip_gen_hi[n+CVA6Cfg.XLEN/2] = fu_data_i.operand_a[(n<<1)+1]; + if (CVA6Cfg.IS_XLEN32) begin + for (n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen + // Assigning lower and upper half of operand into the even and odd positions of result + assign zip_gen[n<<1] = fu_data_i.operand_a[n]; + assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+CVA6Cfg.XLEN/2]; + // Assigning even and odd bits of operand into lower and upper halves of result + assign unzip_gen[n] = fu_data_i.operand_a[n<<1]; + assign unzip_gen[n+CVA6Cfg.XLEN/2] = fu_data_i.operand_a[(n<<1)+1]; + end end end @@ -390,10 +390,11 @@ module alu PACK: result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]}); PACK_H: result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}); BREV8: result_o = brev8_reversed; - UNZIP: result_o = {{unzip_gen_hi}, {unzip_gen_lo}}; - ZIP: result_o = {zip_gen_even} | {zip_gen_odd}; + default: ; endcase if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) result_o = {{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}}; + if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen; + if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen; end end endmodule diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst new file mode 100644 index 0000000000..77b13f91ef --- /dev/null +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst @@ -0,0 +1,169 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zbkb: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV32A60X", "Implemented extension" + "CV64A6_MMU", "Implemented extension" + +============================= +RVZbkb: Bitmanip instructions for Cryptography +============================= + +The following instructions comprise the Zbkb extension: + +Pack instructions +-------------------- +The Pack instructions can be implemented by packing the lower halves of both source operands into the destination register for pack and packw instructions and by packing the lower bytes of the source operands into the destination register for packh. + ++-----------+-----------+-----------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+=======================+ +| ✔ | ✔ | pack rd, rs1, rs2 | ++-----------+-----------+-----------------------+ +| ✔ | ✔ | packh rd, rs1, rs2 | ++-----------+-----------+-----------------------+ +| | ✔ | packw rd, rs1, rs2 | ++-----------+-----------+-----------------------+ + +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + + +- **PACK**: Pack low halves of registers + + **Format**: pack rd, rs1, rs2 + + **Description**: This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. + + **Pseudocode**: X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0]; + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **PACKH**: Pack low bytes of registers + + **Format**: packh rd, rs1, rs2 + + **Description**: This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. + + **Pseudocode**: X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]); + + **Invalid values**: NONE + + **Exception raised**: NONE + +RV64 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **PACKW**: Pack low 16-bits of registers + + **Format**: packw rd, rs1, rs2 + + **Description**: This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. + + **Pseudocode**: X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]); + + **Invalid values**: NONE + + **Exception raised**: NONE + + +Zip instructions +-------------------------------- +These instructions are used to extract bits from the source registers and interleave them into the destination register. + ++-----------+-----------+-----------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+=======================+ +| ✔ | | zip rd, rs | ++-----------+-----------+-----------------------+ +| ✔ | | unzip rd, rs | ++-----------+-----------+-----------------------+ + +RV32 specific Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **ZIP**: Zip + + **Format**: zip rd, rs + + **Description**: This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. + + **Pseudocode**: foreach (i from 0 to xlen/2-1) { + X(rd)[i << 1] = X(rs1)[i] + X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2] + } + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **UNZIP**: Unzip + + **Format**: unzip rd, rs + + **Description**: This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. + + **Pseudocode**: foreach (i from 0 to xlen/2-1) { + X(rd)[i] = X(rs1)[i << 1] + X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1] + } + + **Invalid values**: NONE + + **Exception raised**: NONE + + +Bits-in-Byte-reverse +------------ +brev8 reverses the bits in each byte of the source register. + ++-----------+-----------+-----------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+=======================+ +| ✔ | ✔ | brev8 rd, rs | ++-----------+-----------+-----------------------+ + +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **BREV8**: Reverse bits in bytes + + **Format**: brev8 rd, rs + + **Description**: This instruction reverses the order of the bits in every byte of a register. + + **Pseudocode**: foreach (i from 0 to xlen by 8) { + foreach (j from 0 to 7) { + X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)]; + } + } + + **Invalid values**: NONE + + **Exception raised**: NONE