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CPU.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="pc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="regfile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="cpu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
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<file xil_pn:name="if_id.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="defines.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="id.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="ex.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="ex_mem.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="mem.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="inst_rom.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="sopc.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="addiu3_test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="209"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="209"/>
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<file xil_pn:name="ctrl.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="ram.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="flash_io.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="vga/vga.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="ipcore_dir/my_dcm.xaw" xil_pn:type="FILE_XAW">
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<file xil_pn:name="ipcore_dir/screen_mem.xco" xil_pn:type="FILE_COREGEN">
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<file xil_pn:name="ps2.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="keyboard.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="ipcore_dir/screen_mem.xise" xil_pn:type="FILE_COREGENISE">
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<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/addiu3_test/uut/cpu_component/if_id_component" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
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<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="CPU" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-15T11:25:15" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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<bindings/>
<libraries/>
<autoManagedFiles>
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<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>