From 53b75ed19db50cf33e1443060d9f0f1a8120662a Mon Sep 17 00:00:00 2001 From: Vladimir Marchenko Date: Mon, 27 Nov 2023 17:17:51 +0100 Subject: [PATCH 1/5] Doc: cleaned CMSIS-Core(A) from removed __L1C_CleanInvalidateCache --- CMSIS/Core/Include/core_ca.h | 1 - .../Documentation/Doxygen/Core_A/src/ref_cache.txt | 14 ++------------ 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/CMSIS/Core/Include/core_ca.h b/CMSIS/Core/Include/core_ca.h index 9f73df666..cbd0791ec 100644 --- a/CMSIS/Core/Include/core_ca.h +++ b/CMSIS/Core/Include/core_ca.h @@ -1317,7 +1317,6 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma } /** \brief Clean and Invalidate the entire data or unified cache -* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean */ __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { diff --git a/CMSIS/Documentation/Doxygen/Core_A/src/ref_cache.txt b/CMSIS/Documentation/Doxygen/Core_A/src/ref_cache.txt index efc3f6b68..a953700ee 100644 --- a/CMSIS/Documentation/Doxygen/Core_A/src/ref_cache.txt +++ b/CMSIS/Documentation/Doxygen/Core_A/src/ref_cache.txt @@ -15,21 +15,11 @@ \fn __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) \fn __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) -\fn __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) -\details -Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. - +\fn __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) +\details Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. \fn __STATIC_INLINE void L1C_InvalidateDCacheAll(void) \fn __STATIC_INLINE void L1C_CleanDCacheAll(void) \fn __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) -\fn __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) -\details -Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. - -The parameter \b op defines which cleaning/invalidation strategy should be used: - - 0 - Cache is invalidated using DCISW register. - - 1 - Cache is cleaned using DCCSW register. - - other - Cache is invalidated and cleaned using DCCISW register. @} */ From 68fc2a63f99bde23885f8e2a653cb9985174a045 Mon Sep 17 00:00:00 2001 From: Vladimir Marchenko Date: Mon, 27 Nov 2023 17:19:29 +0100 Subject: [PATCH 2/5] Docs CMSIS-Core: References to anchor require text --- .../Doxygen/Core/src/ref_cm_instr.txt | 2 +- .../Doxygen/Core/src/ref_core_reg.txt | 42 +++++++++---------- .../Doxygen/Core/src/ref_nvic.txt | 32 +++++++------- 3 files changed, 38 insertions(+), 38 deletions(-) diff --git a/CMSIS/Documentation/Doxygen/Core/src/ref_cm_instr.txt b/CMSIS/Documentation/Doxygen/Core/src/ref_cm_instr.txt index 44341d73f..fa2f24cb7 100644 --- a/CMSIS/Documentation/Doxygen/Core/src/ref_cm_instr.txt +++ b/CMSIS/Documentation/Doxygen/Core/src/ref_cm_instr.txt @@ -4,7 +4,7 @@ \brief Functions that generate specific Cortex-M CPU Instructions. \details The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. -Refer to the \ref ref_man_sec for detailed information about these Cortex-M instructions. +Refer to the \ref ref_man_sec "Cortex-M Generic User Guides" for detailed information about these Cortex-M instructions. \note When using the Arm Compiler Version 5 Toolchain the following \ref intrinsic_CPU_gr are implemented using the Embedded Assembler. diff --git a/CMSIS/Documentation/Doxygen/Core/src/ref_core_reg.txt b/CMSIS/Documentation/Doxygen/Core/src/ref_core_reg.txt index 71fba569c..c566f0b85 100644 --- a/CMSIS/Documentation/Doxygen/Core/src/ref_core_reg.txt +++ b/CMSIS/Documentation/Doxygen/Core/src/ref_core_reg.txt @@ -39,7 +39,7 @@ \sa - \ref __set_CONTROL; CONTROL_Type - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t __get_CONTROL(void); @@ -81,7 +81,7 @@ uint32_t __get_CONTROL(void); \sa - \ref __get_CONTROL; __set_PSP; __set_MSP; CONTROL_Type - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void __set_CONTROL(uint32_t control); @@ -121,7 +121,7 @@ void __set_CONTROL(uint32_t control); \sa - \ref __get_xPSR; IPSR_Type - \ref NVIC_gr - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t __get_IPSR(void); @@ -169,7 +169,7 @@ uint32_t __get_IPSR(void); \sa - \ref __get_xPSR; APSR_Type - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t __get_APSR(void); @@ -207,7 +207,7 @@ uint32_t __get_APSR(void); \sa - \ref __get_APSR; __get_IPSR; xPSR_Type - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t __get_xPSR(void); @@ -238,7 +238,7 @@ uint32_t __get_xPSR(void); \sa - \ref __set_PSP; __get_MSP; __get_CONTROL - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ @@ -270,7 +270,7 @@ uint32_t __get_PSP(void); \sa - \ref __get_PSP; __set_MSP; __set_CONTROL - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void __set_PSP(uint32_t topOfProcStack); @@ -300,7 +300,7 @@ void __set_PSP(uint32_t topOfProcStack); \sa - \ref __set_MSP; __get_PSP; __get_CONTROL - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t __get_MSP(void); @@ -331,7 +331,7 @@ uint32_t __get_MSP(void); \sa - \ref __get_MSP; __set_PSP; __set_CONTROL - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void __set_MSP(uint32_t topOfMainStack); @@ -352,8 +352,8 @@ void __set_MSP(uint32_t topOfMainStack); \sa - \ref __set_PRIMASK; __get_BASEPRI; __get_FAULTMASK - - \ref ref_man_sec - + - \ref ref_man_sec "Cortex-M Generic User Guides" + */ uint32_t __get_PRIMASK(void); @@ -380,7 +380,7 @@ uint32_t __get_PRIMASK(void); \sa - \ref __get_PRIMASK; __set_BASEPRI; __set_FAULTMASK - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void __set_PRIMASK(uint32_t priMask); @@ -402,7 +402,7 @@ void __set_PRIMASK(uint32_t priMask); \sa - \ref __set_BASEPRI; __set_BASEPRI_MAX; __get_FAULTMASK; __get_PRIMASK - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t __get_BASEPRI(void); @@ -426,7 +426,7 @@ uint32_t __get_BASEPRI(void); \sa - \ref __get_BASEPRI; __set_BASEPRI_MAX; __set_FAULTMASK; __set_PRIMASK - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void __set_BASEPRI(uint32_t basePri); @@ -451,8 +451,8 @@ void __set_BASEPRI(uint32_t basePri); \sa - \ref __set_BASEPRI; __get_BASEPRI; __set_FAULTMASK; __set_PRIMASK - - \ref ref_man_sec - + - \ref ref_man_sec "Cortex-M Generic User Guides" + */ void __set_BASEPRI_MAX(uint32_t basePri); @@ -473,7 +473,7 @@ void __set_BASEPRI_MAX(uint32_t basePri); \sa - \ref __set_FAULTMASK; __get_BASEPRI; __get_PRIMASK - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t __get_FAULTMASK(void); @@ -507,7 +507,7 @@ uint32_t __get_FAULTMASK(void); \sa - \ref __get_FAULTMASK; __set_BASEPRI; __set_PRIMASK - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void __set_FAULTMASK(uint32_t faultMask); @@ -528,8 +528,8 @@ void __set_FAULTMASK(uint32_t faultMask); \sa - \ref __set_FPSCR - - \ref ref_man_sec - + - \ref ref_man_sec "Cortex-M Generic User Guides" + */ uint32_t __get_FPSCR(void); @@ -612,7 +612,7 @@ uint32_t __get_FPSCR(void); \sa - \ref __get_FPSCR - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void __set_FPSCR(uint32_t fpscr); diff --git a/CMSIS/Documentation/Doxygen/Core/src/ref_nvic.txt b/CMSIS/Documentation/Doxygen/Core/src/ref_nvic.txt index 32229cc40..b1ba140f4 100644 --- a/CMSIS/Documentation/Doxygen/Core/src/ref_nvic.txt +++ b/CMSIS/Documentation/Doxygen/Core/src/ref_nvic.txt @@ -419,7 +419,7 @@ typedef enum IRQn \sa - \ref NVIC_GetPriorityGrouping; NVIC_SetPriority; SCB_Type - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_SetPriorityGrouping(uint32_t PriorityGroup); @@ -438,7 +438,7 @@ void NVIC_SetPriorityGrouping(uint32_t PriorityGroup); \sa - \ref NVIC_SetPriorityGrouping; NVIC_GetPriority; SCB_Type - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t NVIC_GetPriorityGrouping(void); @@ -466,7 +466,7 @@ uint32_t NVIC_GetPriorityGrouping(void); \sa - \ref NVIC_DisableIRQ; SCnSCB_Type; - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_EnableIRQ(IRQn_Type IRQn); @@ -490,7 +490,7 @@ void NVIC_EnableIRQ(IRQn_Type IRQn); \sa - \ref NVIC_EnableIRQ; NVIC_DisableIRQ; - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn); @@ -511,7 +511,7 @@ uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn); \sa - \ref NVIC_EnableIRQ - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_DisableIRQ(IRQn_Type IRQn); @@ -534,7 +534,7 @@ void NVIC_DisableIRQ(IRQn_Type IRQn); \sa - \ref NVIC_SetPendingIRQ; NVIC_ClearPendingIRQ - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn); @@ -554,7 +554,7 @@ uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn); \sa - \ref NVIC_GetPendingIRQ; NVIC_ClearPendingIRQ - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_SetPendingIRQ(IRQn_Type IRQn); @@ -575,7 +575,7 @@ void NVIC_SetPendingIRQ(IRQn_Type IRQn); \sa - \ref NVIC_SetPendingIRQ; NVIC_GetPendingIRQ - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_ClearPendingIRQ(IRQn_Type IRQn); @@ -602,7 +602,7 @@ void NVIC_ClearPendingIRQ(IRQn_Type IRQn); previous interrupt is still defined as active. \sa - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t NVIC_GetActive(IRQn_Type IRQn); @@ -643,7 +643,7 @@ uint32_t NVIC_GetActive(IRQn_Type IRQn); \sa - \ref NVIC_GetPriority; NVIC_SetPriorityGrouping; __set_BASEPRI; - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); @@ -668,7 +668,7 @@ void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); \sa - \ref NVIC_SetPriority; NVIC_GetPriorityGrouping; __get_BASEPRI; - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t NVIC_GetPriority(IRQn_Type IRQn); @@ -694,7 +694,7 @@ uint32_t NVIC_GetPriority(IRQn_Type IRQn); \sa - \ref NVIC_DecodePriority; NVIC_SetPriority; - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority); @@ -719,7 +719,7 @@ uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, \sa - \ref NVIC_EncodePriority; NVIC_GetPriority; NVIC_GetPriorityGrouping; - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); @@ -739,7 +739,7 @@ void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* p \sa - \ref NVIC_SetVector - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ uint32_t NVIC_GetVector(IRQn_Type IRQn); @@ -759,7 +759,7 @@ uint32_t NVIC_GetVector(IRQn_Type IRQn); \sa - \ref NVIC_GetVector - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); @@ -775,7 +775,7 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); most parts of the system, but should not affect the debug system. \sa - - \ref ref_man_sec + - \ref ref_man_sec "Cortex-M Generic User Guides" */ void NVIC_SystemReset (void); From 6ef3c9c47e98c17ac95b64587ec90cea8a225c12 Mon Sep 17 00:00:00 2001 From: Vladimir Marchenko Date: Mon, 27 Nov 2023 17:20:13 +0100 Subject: [PATCH 3/5] Doc, CMSIS-Core: removed doc of deprecated __UNALIGNED_UINT32 --- .../Doxygen/Core/src/ref_compiler_ctrl.txt | 24 ------------------- .../Doxygen/Core_A/src/ref_compiler_ctrl.txt | 24 ------------------- 2 files changed, 48 deletions(-) diff --git a/CMSIS/Documentation/Doxygen/Core/src/ref_compiler_ctrl.txt b/CMSIS/Documentation/Doxygen/Core/src/ref_compiler_ctrl.txt index 43b9f7fb2..d79534b91 100644 --- a/CMSIS/Documentation/Doxygen/Core/src/ref_compiler_ctrl.txt +++ b/CMSIS/Documentation/Doxygen/Core/src/ref_compiler_ctrl.txt @@ -278,30 +278,6 @@ __PACKED_STRUCT foo { */ #define __PACKED_STRUCT -/**************************************************************************************************/ -/** -\def __UNALIGNED_UINT32 -\brief Pointer for unaligned access of a uint32_t variable. -\deprecated -Do not use this macro. -It has been superseded by \ref __UNALIGNED_UINT32_READ, \ref __UNALIGNED_UINT32_WRITE and will be removed in the future. -\details -Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write -operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm -processor core and compiler settings. - -Code Example: -\code -uint32_t val32; - -void test (uint8_t *ptr) { - __UNALIGNED_UINT32(ptr) = val32; -} -\endcode - -*/ -#define __UNALIGNED_UINT32 - /**************************************************************************************************/ /** \def __UNALIGNED_UINT16_READ diff --git a/CMSIS/Documentation/Doxygen/Core_A/src/ref_compiler_ctrl.txt b/CMSIS/Documentation/Doxygen/Core_A/src/ref_compiler_ctrl.txt index a25e8ebf4..7f6358c7d 100644 --- a/CMSIS/Documentation/Doxygen/Core_A/src/ref_compiler_ctrl.txt +++ b/CMSIS/Documentation/Doxygen/Core_A/src/ref_compiler_ctrl.txt @@ -199,30 +199,6 @@ __PACKED_STRUCT foo { */ #define __PACKED_STRUCT -/**************************************************************************************************/ -/** -\def __UNALIGNED_UINT32 -\brief Pointer for unaligned access of a uint32_t variable. -\deprecated -Do not use this macro. -It has been superseded by \ref __UNALIGNED_UINT32_READ, \ref __UNALIGNED_UINT32_WRITE and will be removed in the future. -\details -Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write -operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm -processor core and compiler settings. - - Code Example: -\code -uint32_t val32; - -void test (uint8_t *ptr) { - __UNALIGNED_UINT32(ptr) = val32; -} -\endcode - -*/ -#define __UNALIGNED_UINT32 - /**************************************************************************************************/ /** \def __UNALIGNED_UINT16_READ From 98c1eae914f1c1c417fc7588f71bffac0837d5b9 Mon Sep 17 00:00:00 2001 From: Vladimir Marchenko Date: Mon, 27 Nov 2023 17:21:36 +0100 Subject: [PATCH 4/5] Doc, CMSIS-Core: resolved warnings about __CA_CMSIS_VERSION, minor text improvement --- .../Doxygen/Core/src/ref_version_ctrl.txt | 29 +++++---- .../Doxygen/Core_A/src/ref_core_ca.txt | 61 +++++++------------ 2 files changed, 39 insertions(+), 51 deletions(-) diff --git a/CMSIS/Documentation/Doxygen/Core/src/ref_version_ctrl.txt b/CMSIS/Documentation/Doxygen/Core/src/ref_version_ctrl.txt index 2852739ac..fe9a61931 100644 --- a/CMSIS/Documentation/Doxygen/Core/src/ref_version_ctrl.txt +++ b/CMSIS/Documentation/Doxygen/Core/src/ref_version_ctrl.txt @@ -3,20 +3,31 @@ \defgroup version_control_gr Version Control \brief Version \#define symbols for CMSIS release specific C/C++ source code \details -The header file cmsis_version.h is included by each core header so that these definitions are available. + +\ref cmsis_processor_files contain macros \ref __CORTEX_M , \ref __CORTEX_SC or \ref __STAR_MC that identify the processor core variant described in the file. + +Additionally each processor header file includes the cmsis_version.h file with \ref __CM_CMSIS_VERSION define that identifies the CMSIS version used. + +This allows application code and middleware components to verify the target processor and the CMSIS version that CMSIS-Core component implies. + +@{ +*/ + +/** +\brief Contains the CMSIS version +\details The CMSIS version is a combination of the \ref __CM_CMSIS_VERSION_MAIN (bits 31..16) and \ref __CM_CMSIS_VERSION_SUB (bits 15..0). Code Example: \code #if defined(__CM_CMSIS_VERSION) && \ - (__CM_CMSIS_VERSION >= 0x00050001) -#error Yes, we have CMSIS 5.1 or later + (__CM_CMSIS_VERSION >= 0x00060000) +#error Yes, we have CMSIS 6.0 or later #else -#error We need CMSIS 5.1 or later! +#error We need CMSIS 6.0 or later! #endif \endcode - -@{ */ +#define __CM_CMSIS_VERSION /** \brief Contains the CMSIS major version @@ -30,12 +41,6 @@ The header file cmsis_version.h is included by each core header so that t */ #define __CM_CMSIS_VERSION_SUB -/** -\brief Contains the CMSIS version -\details The CMSIS version is a combination of the \ref __CM_CMSIS_VERSION_MAIN (bits 31..15) and \ref __CM_CMSIS_VERSION_SUB (bits 14..0). -*/ -#define __CM_CMSIS_VERSION - /** \brief Contains the core version for a Cortex-M class controller. \details This define can be used to differentiate between the various available Cortex-M controllers. diff --git a/CMSIS/Documentation/Doxygen/Core_A/src/ref_core_ca.txt b/CMSIS/Documentation/Doxygen/Core_A/src/ref_core_ca.txt index f719bee3d..cce3be645 100644 --- a/CMSIS/Documentation/Doxygen/Core_A/src/ref_core_ca.txt +++ b/CMSIS/Documentation/Doxygen/Core_A/src/ref_core_ca.txt @@ -230,57 +230,40 @@ The macro \ref _FLD2VAL uses the \#define's _Pos and _Msk of the r * CMSIS definitions ******************************************************************************/ /** -\defgroup version_ctrl Version Control -\brief Version symbols for CMSIS release specific C/C++ source code. - +\defgroup version_control_gr Version Control +\brief Version \#define symbols for CMSIS release specific C/C++ source code +\details + @{ */ -/* CMSIS CA definitions */ /** -\def __CA_CMSIS_VERSION_MAIN -\details -Use this define to query the major version of CMSIS-Core(A) component. - -\b Example: -\code -#if __CA_CMSIS_VERSION_MAIN < 5 -#error This code needs at least CMSIS-Core(A) version 5! -#endif -\endcode +\brief Contains the CMSIS version +\details The CMSIS version is a combination of the \ref __CA_CMSIS_VERSION_MAIN (bits 31..16) and \ref __CA_CMSIS_VERSION_SUB (bits 15..0). -\def __CA_CMSIS_VERSION_SUB -\details -Use this define to query the minor version of CMSIS-Core(A) component. - -\b Example: +Code Example: \code -#if __CA_CMSIS_VERSION_MAIN < 5 -#error This code needs at least CMSIS-Core(A) version 5! +#if defined(__CA_CMSIS_VERSION) && \ + (__CA_CMSIS_VERSION >= 0x00060000) +#error Yes, we have CMSIS 6.0 or later #else -#if __CA_CMSIS_VERSION_SUB < 1 -#warning Using CMSIS-Core(A) version 5.0 compatibility functions. -#endif +#error We need CMSIS 6.0 or later! #endif \endcode +*/ +#define __CA_CMSIS_VERSION -\def __CA_CMSIS_VERSION -\details -Use this define to query the full version of CMSIS-Core(A) component. - -| Bits | Name | Function | -| :------ | :------------ | :-----------------------| -| [31:16] | MAIN | __CA_CMSIS_VERSION_MAIN | -| [15:0] | SUB | __CA_CMSIS_VERSION_SUB | - +/** +\brief Contains the CMSIS major version +\details The CMSIS major version can be used to differentiate between CMSIS major releases. +*/ +#define __CA_CMSIS_VERSION_MAIN -\b Example: -\code -#if __CA_CMSIS_VERSION < 0x00050001 -#error This code needs at least CMSIS-Core(A) version 5.1! -#endif -\endcode +/** +\brief Contains the CMSIS minor version +\details The CMSIS minor version can be used to query a CMSIS release update level. */ +#define __CA_CMSIS_VERSION_SUB /** \brief Contains the core revision for a Cortex-A class device. From d1a46a009403be89e0ca7400f7da625bac06cb9d Mon Sep 17 00:00:00 2001 From: Vladimir Marchenko Date: Mon, 27 Nov 2023 17:22:20 +0100 Subject: [PATCH 5/5] Doc, CMSIS-Core: Added references for some macros. --- CMSIS/Documentation/Doxygen/Core/src/history.md | 8 ++++---- CMSIS/Documentation/Doxygen/Core_A/src/history.md | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/CMSIS/Documentation/Doxygen/Core/src/history.md b/CMSIS/Documentation/Doxygen/Core/src/history.md index 1d82d7e7f..2e527f1d4 100644 --- a/CMSIS/Documentation/Doxygen/Core/src/history.md +++ b/CMSIS/Documentation/Doxygen/Core/src/history.md @@ -13,7 +13,7 @@ The table below provides information about the changes delivered with specific v V5.7.0
    -
  • Added: Added new compiler macros __ALIAS and __NO_INIT
    • +
  • Added: Added new compiler macros \ref __ALIAS and \ref __NO_INIT
@@ -48,7 +48,7 @@ The table below provides information about the changes delivered with specific v
  • Added: Cortex-M55 cpu support
  • Enhanced: MVE support for Armv8.1-MML
  • Fixed: Device config define checks
    • -
  • Added: L1 Cache functions for Armv7-M and later
    • +
  • Added: \ref cache_functions_m7 for Armv7-M and later
    • @@ -84,7 +84,7 @@ The table below provides information about the changes delivered with specific v
    • Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.
      • -
    • Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.
      • +
    • Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.
    • Added support for Cortex-M1 (beta).
    • Removed usage of register keyword.
    • Added defines for EXC_RETURN, FNC_RETURN and integrity signature values.
      • @@ -116,7 +116,7 @@ The table below provides information about the changes delivered with specific v
      • Added macros \ref \__UNALIGNED_UINT16_READ, \ref \__UNALIGNED_UINT16_WRITE.
      • Added macros \ref \__UNALIGNED_UINT32_READ, \ref \__UNALIGNED_UINT32_WRITE.
        • -
      • Deprecated macro \ref \__UNALIGNED_UINT32.
        • +
      • Deprecated macro __UNALIGNED_UINT32.
      • Changed \ref version_control_gr macros to be core agnostic.
      • Added \ref mpu_functions for Cortex-M0+/M3/M4/M7.
      diff --git a/CMSIS/Documentation/Doxygen/Core_A/src/history.md b/CMSIS/Documentation/Doxygen/Core_A/src/history.md index 4e73e4eb3..5b0a11e3d 100644 --- a/CMSIS/Documentation/Doxygen/Core_A/src/history.md +++ b/CMSIS/Documentation/Doxygen/Core_A/src/history.md @@ -1,4 +1,4 @@ -# Revision History of CMSIS-Core (Cortex-A) {#rev_histCoreA} +# Revision History {#rev_histCoreA} CMSIS-Core (A) component is maintaned with own versioning that gets incremented together with the [CMSIS Software Pack](../General/cmsis_pack.html) releases. @@ -21,7 +21,7 @@ The table below provides information about the changes delivered with specific v V1.2.0
        -
      • Fixed GIC_SetPendingIRQ to use GICD_SGIR instead of GICD_SPENDSGIR +
      • Fixed \ref GIC_SetPendingIRQ to use GICD_SGIR instead of GICD_SPENDSGIR for compliance with all GIC specification versions.
      • Added missing DSP intrinsics.
      • Reworked assembly intrinsics: volatile, barriers and clobbers.
        • @@ -40,7 +40,7 @@ The table below provides information about the changes delivered with specific v V1.1.3
          -
        • Fixed __get_SP_usr()/__set_SP_usr() for ArmClang.
          • +
        • Fixed __get_SP_usr() / __set_SP_usr() for ArmClang.
        • Fixed zero argument handling in __CLZ() .