From 6093d109ec9d263f2952d4fe8b4cfa0652ec3f3d Mon Sep 17 00:00:00 2001
From: AUDIY <96096729+AUDIY@users.noreply.github.com>
Date: Tue, 12 Dec 2023 00:59:39 +0900
Subject: [PATCH] Update README.md

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 1bb50d6..4292320 100644
--- a/README.md
+++ b/README.md
@@ -7,7 +7,7 @@ FPGA based PCM oversampling FIR filter (oversample ratio: 2).
 2. Start Simulation.
    
 ### Real Machine
-1. Add all modules (except <module_name>_tb.v) and memory initialization file into your project.
+1. Add all modules (except <module_name>_tb.v other than test bench for DUT) and memory initialization file into your project.
 2. Change parameters depending on your audio data settings (ex. MCLK frequency, BCK frequency).
 3. Synthesize, place & route to your FPGA.
 4. Confirm actual operation.