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msm-arm-smmu-sdm845.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/msm/msm-bus-ids.h>
&soc {
kgsl_smmu: arm,smmu-kgsl@5040000 {
status = "ok";
compatible = "qcom,smmu-v2";
reg = <0x5040000 0x10000>;
#iommu-cells = <1>;
qcom,dynamic;
qcom,use-3-lvl-tables;
qcom,disable-atos;
#global-interrupts = <2>;
qcom,regulator-names = "vdd";
vdd-supply = <&gpu_cx_gdsc>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "gcc_gpu_memnoc_gfx_clk";
clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
attach-impl-defs =
<0x6000 0x2378>,
<0x6060 0x1055>,
<0x678c 0x8>,
<0x6794 0x28>,
<0x6800 0x6>,
<0x6900 0x3ff>,
<0x6924 0x204>,
<0x6928 0x11000>,
<0x6930 0x800>,
<0x6960 0xffffffff>,
<0x6b64 0x1a5551>,
<0x6b68 0x9a82a382>;
};
apps_smmu: apps-smmu@0x15000000 {
compatible = "qcom,qsmmu-v500";
reg = <0x15000000 0x80000>,
<0x150c2000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
qcom,no-asid-retention;
qcom,disable-atos;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 0>,
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 1000>;
anoc_1_tbu: anoc_1_tbu@0x150c5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150c5000 0x1000>,
<0x150c2200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 0>,
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 1000>;
};
anoc_2_tbu: anoc_2_tbu@0x150c9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150c9000 0x1000>,
<0x150c2208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 0>,
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 1000>;
};
mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150cd000 0x1000>,
<0x150c2210 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x800 0x400>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
qcom,msm-bus,name = "mnoc_hf_0_tbu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_MDP_PORT0>,
<MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
<0 0>,
<MSM_BUS_MASTER_MDP_PORT0>,
<MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
<0 1000>;
};
mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x150d1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150d1000 0x1000>,
<0x150c2218 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0xc00 0x400>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
qcom,msm-bus,name = "mnoc_hf_1_tbu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_MDP_PORT0>,
<MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
<0 0>,
<MSM_BUS_MASTER_MDP_PORT0>,
<MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
<0 1000>;
};
mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150d5000 0x1000>,
<0x150c2220 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1000 0x400>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
qcom,msm-bus,name = "mnoc_sf_0_tbu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_CAMNOC_SF>,
<MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
<0 0>,
<MSM_BUS_MASTER_CAMNOC_SF>,
<MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
<0 1000>;
};
compute_dsp_tbu: compute_dsp_tbu@0x150d9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150d9000 0x1000>,
<0x150c2228 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1400 0x400>;
/* No GDSC */
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 0>,
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 1000>;
};
adsp_tbu: adsp_tbu@0x150dd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150dd000 0x1000>,
<0x150c2230 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1800 0x400>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 0>,
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 1000>;
};
anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x150e1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150e1000 0x1000>,
<0x150c2238 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1c00 0x400>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>;
clock-names = "gcc_aggre_noc_pcie_tbu_clk";
clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 0>,
<MSM_BUS_MASTER_GNOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 1000>;
};
};
kgsl_iommu_test_device {
status = "disabled";
compatible = "iommu-debug-test";
/*
* 0x7 isn't a valid sid, but should pass the sid sanity check.
* We just need _something_ here to get this node recognized by
* the SMMU driver. Our test uses ATOS, which doesn't use SIDs
* anyways, so using a dummy value is ok.
*/
iommus = <&kgsl_smmu 0x7>;
qcom,iommu-dma = "disabled";
};
apps_iommu_test_device {
compatible = "iommu-debug-test";
/*
* This SID belongs to TSIF. We can't use a fake SID for
* the apps_smmu device.
*/
iommus = <&apps_smmu 0x20 0>;
qcom,iommu-dma = "disabled";
};
apps_iommu_coherent_test_device {
compatible = "iommu-debug-test";
/*
* This SID belongs to TSIF. We can't use a fake SID for
* the apps_smmu device.
*/
iommus = <&apps_smmu 0x20 0>;
qcom,iommu-dma = "disabled";
dma-coherent;
};
};
&apps_smmu {
qcom,actlr = <0x0880 0x8 0x103>,
<0x0881 0x8 0x103>,
<0x0c80 0x8 0x103>,
<0x0c81 0x8 0x103>,
<0x1090 0x0 0x103>,
<0x1091 0x0 0x103>,
<0x10a0 0x8 0x103>,
<0x10b0 0x0 0x103>,
<0x10a1 0x8 0x103>,
<0x10a3 0x8 0x103>,
<0x10a4 0x8 0x103>,
<0x10b4 0x0 0x103>,
<0x10a5 0x8 0x103>;
qcom,mmu500-errata-1 = <0x800 0x3ff>,
<0xc00 0x3ff>;
hwlocks = <&tcsr_mutex 6>;
};