diff --git a/AUTHORS b/AUTHORS index dbfd904..de0c9c7 100644 --- a/AUTHORS +++ b/AUTHORS @@ -1,7 +1,8 @@ -Julian Seward was the original founder, designer and author of Valgrind, -created the dynamic translation frameworks, wrote Memcheck and 3.3.X -Helgrind, and did lots of other things. +Julian Seward was the original founder, designer and author of +Valgrind, created the dynamic translation frameworks, wrote Memcheck, +the 3.X versions of Helgrind, Ptrcheck, DHAT, and did lots of other +things. Nicholas Nethercote did the core/tool generalisation, wrote Cachegrind and Massif, and tons of other stuff. @@ -33,8 +34,12 @@ other tweakage. Bart Van Assche wrote and maintains DRD. -Cerion Armour-Brown worked on PowerPC instruction set support in -the Vex dynamic-translation framework. +Cerion Armour-Brown worked on PowerPC instruction set support in the +Vex dynamic-translation framework. Maynard Johnson improved the +Power6 support. + +Kirill Batuzov and Dmitry Zhurikhin did the NEON instruction set +support for ARM. Donna Robinson did the v6 media instruction support. Donna Robinson created and maintains the very excellent http://www.valgrind.org. diff --git a/Makefile.all.am b/Makefile.all.am index b126e6b..6994d75 100644 --- a/Makefile.all.am +++ b/Makefile.all.am @@ -96,7 +96,8 @@ AM_CFLAGS_BASE = \ # stack traces, since users often see stack traces extending # into (and through) the preloads. if VGCONF_OS_IS_DARWIN -AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic +AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ + -mno-dynamic-no-pic -fpic -fPIC else AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing endif @@ -116,16 +117,16 @@ endif # automake, but this does not really matter and seems hard to avoid. AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \ - -I$(top_srcdir) \ - -I$(top_srcdir)/include \ + -I$(top_srcdir) \ + -I$(top_srcdir)/include \ -I$(top_srcdir)/VEX/pub \ -DVGA_@VGCONF_ARCH_PRI@=1 \ -DVGO_@VGCONF_OS@=1 \ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 if VGCONF_HAVE_PLATFORM_SEC AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \ - -I$(top_srcdir) \ - -I$(top_srcdir)/include \ + -I$(top_srcdir) \ + -I$(top_srcdir)/include \ -I$(top_srcdir)/VEX/pub \ -DVGA_@VGCONF_ARCH_SEC@=1 \ -DVGO_@VGCONF_OS@=1 \ @@ -155,6 +156,11 @@ AM_CFLAGS_X86_FREEBSD = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \ $(AM_CFLAGS_BASE) AM_CCASFLAGS_X86_FREEBSD = $(AM_CPPFLAGS_X86_FREEBSD) @FLAG_M32@ -g +AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@ +AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \ + $(AM_CFLAGS_BASE) -marm +AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -marm -g + AM_FLAG_M3264_AMD64_FREEBSD = @FLAG_M64@ AM_CFLAGS_AMD64_FREEBSD = @FLAG_M64@ -fomit-frame-pointer \ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE) @@ -172,8 +178,9 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \ AM_FLAG_M3264_X86_DARWIN = -arch i386 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \ - -mmacosx-version-min=10.5 -fno-stack-protector \ - -mdynamic-no-pic + -mmacosx-version-min=10.5 \ + -fno-stack-protector -fno-pic -fno-PIC + AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64 @@ -210,6 +217,7 @@ PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_FREEBSD = $(PRELOAD_LDFLAGS_COMMON_FREEBSD) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_FREEBSD= $(PRELOAD_LDFLAGS_COMMON_FREEBSD) @FLAG_M64@ +PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_PPC32_AIX5 = $(PRELOAD_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@ PRELOAD_LDFLAGS_PPC64_AIX5 = $(PRELOAD_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386 diff --git a/Makefile.am b/Makefile.am index 89e76fe..da79ec7 100644 --- a/Makefile.am +++ b/Makefile.am @@ -13,7 +13,8 @@ TOOLS = memcheck \ drd EXP_TOOLS = exp-ptrcheck \ - exp-bbv + exp-bbv \ + exp-dhat # DDD: once all tools work on Darwin, TEST_TOOLS and TEST_EXP_TOOLS can be # replaced with TOOLS and EXP_TOOLS. @@ -49,7 +50,8 @@ SUPP_FILES = \ glibc-2.X-drd.supp \ exp-ptrcheck.supp \ darwin9.supp darwin9-drd.supp \ - freebsd.supp + freebsd.supp \ + darwin10.supp darwin10-drd.supp DEFAULT_SUPP_FILES = @DEFAULT_SUPP@ # We include all the base .supp files in the distribution, but not diff --git a/Makefile.tool.am b/Makefile.tool.am index 0b8737f..857729a 100644 --- a/Makefile.tool.am +++ b/Makefile.tool.am @@ -26,39 +26,41 @@ TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \ endif -TOOL_LDFLAGS_COMMON_LINUX = -static \ - -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \ - -nodefaultlibs -nostartfiles -u _start +# -Wl,--build-id=none is needed when linking tools on Linux. Without this +# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the +# default text segment address, which of course means the resulting executable +# is unusable. So we have to tell ld not to generate that, with --build-id=none. +TOOL_LDFLAGS_COMMON_LINUX = \ + -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@ +TOOL_LDFLAGS_COMMON_AIX5 = \ + -static -Wl,-e_start_valgrind +TOOL_LDFLAGS_COMMON_DARWIN = \ + -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start TOOL_LDFLAGS_COMMON_FREEBSD = -static \ - -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \ - -nodefaultlibs -nostartfiles -u _start -TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind -TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \ - -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld + -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@ TOOL_LDFLAGS_X86_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \ - -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds + $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ TOOL_LDFLAGS_X86_FREEBSD = \ $(TOOL_LDFLAGS_COMMON_FREEBSD) @FLAG_M32@ \ -Wl,-T,$(top_builddir)/valt_load_address_x86_freebsd.lds TOOL_LDFLAGS_AMD64_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \ - -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds + $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ TOOL_LDFLAGS_AMD64_FREEBSD = \ $(TOOL_LDFLAGS_COMMON_FREEBSD) @FLAG_M64@ \ -Wl,-T,$(top_builddir)/valt_load_address_amd64_freebsd.lds TOOL_LDFLAGS_PPC32_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \ - -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds + $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ TOOL_LDFLAGS_PPC64_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \ - -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds + $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ + +TOOL_LDFLAGS_ARM_LINUX = \ + $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ TOOL_LDFLAGS_PPC32_AIX5 = \ $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@ @@ -67,120 +69,19 @@ TOOL_LDFLAGS_PPC64_AIX5 = \ $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc TOOL_LDFLAGS_X86_DARWIN = \ - $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \ - -Wl,-seg1addr,0xf0080000 \ - -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \ - -Wl,-pagezero_size,0xf0000000 + $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 -# pagezero can't be unmapped and remapped. Use stack instead. -# GrP fixme no stack guard TOOL_LDFLAGS_AMD64_DARWIN = \ - $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \ - -Wl,-seg1addr,0x7fff55000000 \ - -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \ - -Wl,-pagezero_size,0x100000000 - + $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 -BUILT_SOURCES = -CLEANFILES = -if VGCONF_PLATFORMS_INCLUDE_X86_LINUX -BUILT_SOURCES += $(top_builddir)/valt_load_address_x86_linux.lds -CLEANFILES += $(top_builddir)/valt_load_address_x86_linux.lds -endif -if VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX -BUILT_SOURCES += $(top_builddir)/valt_load_address_amd64_linux.lds -CLEANFILES += $(top_builddir)/valt_load_address_amd64_linux.lds -endif -if VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX -BUILT_SOURCES += $(top_builddir)/valt_load_address_ppc32_linux.lds -CLEANFILES += $(top_builddir)/valt_load_address_ppc32_linux.lds -endif -if VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX -BUILT_SOURCES += $(top_builddir)/valt_load_address_ppc64_linux.lds -CLEANFILES += $(top_builddir)/valt_load_address_ppc64_linux.lds -endif -if VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD -BUILT_SOURCES += $(top_builddir)/valt_load_address_x86_freebsd.lds -CLEANFILES += $(top_builddir)/valt_load_address_x86_freebsd.lds -endif -if VGCONF_PLATFORMS_INCLUDE_AMD64_FREEBSD -BUILT_SOURCES += $(top_builddir)/valt_load_address_amd64_freebsd.lds -CLEANFILES += $(top_builddir)/valt_load_address_amd64_freebsd.lds -endif -if VGCONF_PLATFORMS_INCLUDE_PPC32_AIX5 -# No need to generate $(top_builddir)/valt_load_address*.lds; the final -# executables can be linked to be at any address. They will be relocated by -# AIX kernel when they are loaded. -endif -if VGCONF_PLATFORMS_INCLUDE_PPC64_AIX5 -# Ditto -endif -if VGCONF_OS_IS_DARWIN -# GrP untested, possibly hopeless -endif - - -# Generate a linker script for linking the binaries. This is the -# standard gcc linker script, except hacked so that an alternative -# load address can be specified by (1) asking gcc to use this script -# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol -# valt_load_address to the required value -# (-Wl,-defsym,valt_load_address=0x70000000). -# -# Extract ld's default linker script and hack it to our needs. -# First we cut everything above and below the "=====..." lines at the top -# and bottom. -# Then we have to replace the load address with "valt_load_address". -# The line to replace in has one of the following two forms: -# -# . = 0x08048000 + SIZEOF_HEADERS; -# -# or -# PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS; +# NB for 64-bit darwin. We may want to set -Wl,-pagezero_size to +# something smaller than the default of 4G, so as to facilitate +# loading clients who are also linked thusly (currently m_ume.c +# will fail to load them). Although such setting is probably +# better done in link_tool_exe.c. # -# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace -# all the hex values in that line with "valt_load_address". -$(top_builddir)/valt_load_address_x86_linux.lds: Makefile - $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \ - -e '1,/^=====\+$$/d' \ - -e '/^=====\+$$/,/.\*/d' \ - -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) \+ SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \ - || rm -f $@ - -$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile - $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \ - -e '1,/^=====\+$$/d' \ - -e '/^=====\+$$/,/.\*/d' \ - -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) \+ SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \ - || rm -f $@ - -$(top_builddir)/valt_load_address_x86_freebsd.lds: Makefile - $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed -E \ - -e '1,/^=====+$$/d' \ - -e '/^=====+$$/,/.*/d' \ - -e '/. = (0x[0-9A-Fa-f]+|SEGMENT_START\("[^"]+", 0x[0-9A-Fa-f]+\)) \+ SIZEOF_HEADERS/s/0x[0-9A-Fa-f]+/valt_load_address/g' > $@ \ - || rm -f $@ - -$(top_builddir)/valt_load_address_amd64_freebsd.lds: Makefile - $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed -E \ - -e '1,/^=====+$$/d' \ - -e '/^=====+$$/,/.*/d' \ - -e '/\. = (0x[0-9A-Fa-f]+|SEGMENT_START\("[^"]+", 0x[0-9A-Fa-f]+\)) \+ SIZEOF_HEADERS/s/0x[0-9A-Fa-f]+/valt_load_address/g' > $@ \ - || rm -f $@ - -$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile - $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \ - -e '1,/^=====\+$$/d' \ - -e '/^=====\+$$/,/.\*/d' \ - -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) \+ SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \ - || rm -f $@ - -$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile - $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \ - -e '1,/^=====\+$$/d' \ - -e '/^=====\+$$/,/.\*/d' \ - -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) \+ SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \ - || rm -f $@ +# -Wl,-pagezero_size,0x100000000 + #---------------------------------------------------------------------------- # vgpreload_-.a stuff @@ -201,6 +102,9 @@ LIBREPLACEMALLOC_PPC64_LINUX = \ LIBREPLACEMALLOC_X86_FREEBSD = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-freebsd.a +LIBREPLACEMALLOC_ARM_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a + LIBREPLACEMALLOC_AMD64_FREEBSD = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-freebsd.a @@ -237,6 +141,11 @@ LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \ $(LIBREPLACEMALLOC_PPC64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_ARM_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_FREEBSD = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_FREEBSD) \ diff --git a/Makefile.vex.am b/Makefile.vex.am index 2ad2f75..b84ba4e 100644 --- a/Makefile.vex.am +++ b/Makefile.vex.am @@ -40,6 +40,7 @@ noinst_HEADERS = \ priv/guest_arm_defs.h \ priv/host_generic_regs.h \ priv/host_generic_simd64.h \ + priv/host_generic_simd128.h \ priv/host_x86_defs.h \ priv/host_amd64_defs.h \ priv/host_ppc_defs.h \ @@ -51,12 +52,22 @@ CLEANFILES = pub/libvex_guest_offsets.h # This is very uggerly. Need to sed out both "xyzzyN" and # "xyzzy$N" since gcc on different targets emits the constants # differently -- with a leading $ on x86/amd64 but none on ppc32/64. -pub/libvex_guest_offsets.h: +pub/libvex_guest_offsets.h: auxprogs/genoffsets.c \ + pub/libvex_basictypes.h \ + pub/libvex_guest_x86.h \ + pub/libvex_guest_amd64.h \ + pub/libvex_guest_ppc32.h \ + pub/libvex_guest_ppc64.h \ + pub/libvex_guest_arm.h rm -f auxprogs/genoffsets.s - $(CC) $(LIBVEX_CFLAGS) -O -S -o auxprogs/genoffsets.s \ - auxprogs/genoffsets.c + $(CC) $(LIBVEX_CFLAGS) \ + $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ + -O -S -o auxprogs/genoffsets.s \ + auxprogs/genoffsets.c grep xyzzy auxprogs/genoffsets.s | grep define \ - | sed "s/xyzzy\\$$//g" | sed "s/xyzzy//g" \ + | sed "s/xyzzy\\$$//g" \ + | sed "s/xyzzy#//g" \ + | sed "s/xyzzy//g" \ > pub/libvex_guest_offsets.h rm -f auxprogs/genoffsets.s @@ -88,6 +99,7 @@ LIBVEX_SOURCES_COMMON = \ priv/guest_arm_toIR.c \ priv/host_generic_regs.c \ priv/host_generic_simd64.c \ + priv/host_generic_simd128.c \ priv/host_generic_reg_alloc2.c \ priv/host_x86_defs.c \ priv/host_x86_isel.c \ diff --git a/NEWS b/NEWS index efac5dd..d5b42dd 100644 --- a/NEWS +++ b/NEWS @@ -1,4 +1,323 @@ +Release 3.6.0 (21 October 2010) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +3.6.0 is a feature release with many significant improvements and the +usual collection of bug fixes. + +This release supports X86/Linux, AMD64/Linux, ARM/Linux, PPC32/Linux, +PPC64/Linux, X86/Darwin and AMD64/Darwin. Support for recent distros +and toolchain components (glibc 2.12, gcc 4.5, OSX 10.6) has been added. + + ------------------------- + +Here are some highlights. Details are shown further down: + +* Support for ARM/Linux. + +* Support for recent Linux distros: Ubuntu 10.10 and Fedora 14. + +* Support for Mac OS X 10.6, both 32- and 64-bit executables. + +* Support for the SSE4.2 instruction set. + +* Enhancements to the Callgrind profiler, including the ability to + handle CPUs with three levels of cache. + +* A new experimental heap profiler, DHAT. + +* A huge number of bug fixes and small enhancements. + + ------------------------- + +Here are details of the above changes, together with descriptions of +many other changes, and a list of fixed bugs. + +* ================== PLATFORM CHANGES ================= + +* Support for ARM/Linux. Valgrind now runs on ARMv7 capable CPUs + running Linux. It is known to work on Ubuntu 10.04, Ubuntu 10.10, + and Maemo 5, so you can run Valgrind on your Nokia N900 if you want. + + This requires a CPU capable of running the ARMv7-A instruction set + (Cortex A5, A8 and A9). Valgrind provides fairly complete coverage + of the user space instruction set, including ARM and Thumb integer + code, VFPv3, NEON and V6 media instructions. The Memcheck, + Cachegrind and Massif tools work properly; other tools work to + varying degrees. + +* Support for recent Linux distros (Ubuntu 10.10 and Fedora 14), along + with support for recent releases of the underlying toolchain + components, notably gcc-4.5 and glibc-2.12. + +* Support for Mac OS X 10.6, both 32- and 64-bit executables. 64-bit + support also works much better on OS X 10.5, and is as solid as + 32-bit support now. + +* Support for the SSE4.2 instruction set. SSE4.2 is supported in + 64-bit mode. In 32-bit mode, support is only available up to and + including SSSE3. Some exceptions: SSE4.2 AES instructions are not + supported in 64-bit mode, and 32-bit mode does in fact support the + bare minimum SSE4 instructions to needed to run programs on Mac OS X + 10.6 on 32-bit targets. + +* Support for IBM POWER6 cpus has been improved. The Power ISA up to + and including version 2.05 is supported. + +* ==================== TOOL CHANGES ==================== + +* Cachegrind has a new processing script, cg_diff, which finds the + difference between two profiles. It's very useful for evaluating + the performance effects of a change in a program. + + Related to this change, the meaning of cg_annotate's (rarely-used) + --threshold option has changed; this is unlikely to affect many + people, if you do use it please see the user manual for details. + +* Callgrind now can do branch prediction simulation, similar to + Cachegrind. In addition, it optionally can count the number of + executed global bus events. Both can be used for a better + approximation of a "Cycle Estimation" as derived event (you need to + update the event formula in KCachegrind yourself). + +* Cachegrind and Callgrind now refer to the LL (last-level) cache + rather than the L2 cache. This is to accommodate machines with + three levels of caches -- if Cachegrind/Callgrind auto-detects the + cache configuration of such a machine it will run the simulation as + if the L2 cache isn't present. This means the results are less + likely to match the true result for the machine, but + Cachegrind/Callgrind's results are already only approximate, and + should not be considered authoritative. The results are still + useful for giving a general idea about a program's locality. + +* Massif has a new option, --pages-as-heap, which is disabled by + default. When enabled, instead of tracking allocations at the level + of heap blocks (as allocated with malloc/new/new[]), it instead + tracks memory allocations at the level of memory pages (as mapped by + mmap, brk, etc). Each mapped page is treated as its own block. + Interpreting the page-level output is harder than the heap-level + output, but this option is useful if you want to account for every + byte of memory used by a program. + +* DRD has two new command-line options: --free-is-write and + --trace-alloc. The former allows to detect reading from already freed + memory, and the latter allows tracing of all memory allocations and + deallocations. + +* DRD has several new annotations. Custom barrier implementations can + now be annotated, as well as benign races on static variables. + +* DRD's happens before / happens after annotations have been made more + powerful, so that they can now also be used to annotate e.g. a smart + pointer implementation. + +* Helgrind's annotation set has also been drastically improved, so as + to provide to users a general set of annotations to describe locks, + semaphores, barriers and condition variables. Annotations to + describe thread-safe reference counted heap objects have also been + added. + +* Memcheck has a new command-line option, --show-possibly-lost, which + is enabled by default. When disabled, the leak detector will not + show possibly-lost blocks. + +* A new experimental heap profiler, DHAT (Dynamic Heap Analysis Tool), + has been added. DHAT keeps track of allocated heap blocks, and also + inspects every memory reference to see which block (if any) is being + accessed. This gives a lot of insight into block lifetimes, + utilisation, turnover, liveness, and the location of hot and cold + fields. You can use DHAT to do hot-field profiling. + +* ==================== OTHER CHANGES ==================== + +* Improved support for unfriendly self-modifying code: the extra + overhead incurred by --smc-check=all has been reduced by + approximately a factor of 5 as compared with 3.5.0. + +* Ability to show directory names for source files in error messages. + This is combined with a flexible mechanism for specifying which + parts of the paths should be shown. This is enabled by the new flag + --fullpath-after. + +* A new flag, --require-text-symbol, which will stop the run if a + specified symbol is not found it a given shared object when it is + loaded into the process. This makes advanced working with function + intercepting and wrapping safer and more reliable. + +* Improved support for the Valkyrie GUI, version 2.0.0. GUI output + and control of Valgrind is now available for the tools Memcheck and + Helgrind. XML output from Valgrind is available for Memcheck, + Helgrind and exp-Ptrcheck. + +* More reliable stack unwinding on amd64-linux, particularly in the + presence of function wrappers, and with gcc-4.5 compiled code. + +* Modest scalability (performance improvements) for massive + long-running applications, particularly for those with huge amounts + of code. + +* Support for analyzing programs running under Wine with has been + improved. The header files , + and can now be used in + Windows-programs compiled with MinGW or one of the Microsoft Visual + Studio compilers. + +* A rare but serious error in the 64-bit x86 CPU simulation was fixed. + The 32-bit simulator was not affected. This did not occur often, + but when it did would usually crash the program under test. + Bug 245925. + +* A large number of bugs were fixed. These are shown below. + +* A number of bugs were investigated, and were candidates for fixing, + but are not fixed in 3.6.0, due to lack of developer time. They may + get fixed in later releases. They are: + + 194402 vex amd64->IR: 0x48 0xF 0xAE 0x4 0x24 0x49 (FXSAVE64) + 212419 false positive "lock order violated" (A+B vs A) + 213685 Undefined value propagates past dependency breaking instruction + 216837 Incorrect instrumentation of NSOperationQueue on Darwin + 237920 valgrind segfault on fork failure + 242137 support for code compiled by LLVM-2.8 + 242423 Another unknown Intel cache config value + 243232 Inconsistent Lock Orderings report with trylock + 243483 ppc: callgrind triggers VEX assertion failure + 243935 Helgrind: implementation of ANNOTATE_HAPPENS_BEFORE() is wrong + 244677 Helgrind crash hg_main.c:616 (map_threads_lookup): Assertion + 'thr' failed. + 246152 callgrind internal error after pthread_cancel on 32 Bit Linux + 249435 Analyzing wine programs with callgrind triggers a crash + 250038 ppc64: Altivec lvsr and lvsl instructions fail their regtest + 250065 Handling large allocations + 250101 huge "free" memory usage due to m_mallocfree.c + "superblocks fragmentation" + 251569 vex amd64->IR: 0xF 0x1 0xF9 0x8B 0x4C 0x24 (RDTSCP) + 252091 Callgrind on ARM does not detect function returns correctly + 252600 [PATCH] Allow lhs to be a pointer for shl/shr + 254420 memory pool tracking broken + n-i-bz support for adding symbols for JIT generated code + + +The following bugs have been fixed or resolved. Note that "n-i-bz" +stands for "not in bugzilla" -- that is, a bug that was reported to us +but never got a bugzilla entry. We encourage you to file bugs in +bugzilla (http://bugs.kde.org/enter_valgrind_bug.cgi) rather than +mailing the developers (or mailing lists) directly -- bugs that are +not entered into bugzilla tend to get forgotten about or ignored. + +To see details of a given bug, visit +https://bugs.kde.org/show_bug.cgi?id=XXXXXX +where XXXXXX is the bug number as listed below. + +135264 dcbzl instruction missing +142688 == 250799 +153699 Valgrind should report unaligned reads with movdqa +180217 == 212335 +190429 Valgrind reports lost of errors in ld.so + with x86_64 2.9.90 glibc +197266 valgrind appears to choke on the xmms instruction + "roundsd" on x86_64 +197988 Crash when demangling very large symbol names +202315 unhandled syscall: 332 (inotify_init1) +203256 Add page-level profiling to Massif +205093 dsymutil=yes needs quotes, locking (partial fix) +205241 Snow Leopard 10.6 support (partial fix) +206600 Leak checker fails to upgrade indirect blocks when their + parent becomes reachable +210935 port valgrind.h (not valgrind) to win32 so apps run under + wine can make client requests +211410 vex amd64->IR: 0x15 0xFF 0xFF 0x0 0x0 0x89 + within Linux ip-stack checksum functions +212335 unhandled instruction bytes: 0xF3 0xF 0xBD 0xC0 + (lzcnt %eax,%eax) +213685 Undefined value propagates past dependency breaking instruction + (partial fix) +215914 Valgrind inserts bogus empty environment variable +217863 == 197988 +219538 adjtimex syscall wrapper wrong in readonly adjtime mode +222545 shmat fails under valgind on some arm targets +222560 ARM NEON support +230407 == 202315 +231076 == 202315 +232509 Docs build fails with formatting inside elements +232793 == 202315 +235642 [PATCH] syswrap-linux.c: support evdev EVIOCG* ioctls +236546 vex x86->IR: 0x66 0xF 0x3A 0xA +237202 vex amd64->IR: 0xF3 0xF 0xB8 0xC0 0x49 0x3B +237371 better support for VALGRIND_MALLOCLIKE_BLOCK +237485 symlink (syscall 57) is not supported on Mac OS +237723 sysno == 101 exp-ptrcheck: the 'impossible' happened: + unhandled syscall +238208 is_just_below_ESP doesn't take into account red-zone +238345 valgrind passes wrong $0 when executing a shell script +238679 mq_timedreceive syscall doesn't flag the reception buffer + as "defined" +238696 fcntl command F_DUPFD_CLOEXEC not supported +238713 unhandled instruction bytes: 0x66 0xF 0x29 0xC6 +238713 unhandled instruction bytes: 0x66 0xF 0x29 0xC6 +238745 3.5.0 Make fails on PPC Altivec opcodes, though configure + says "Altivec off" +239992 vex amd64->IR: 0x48 0xF 0xC4 0xC1 0x0 0x48 +240488 == 197988 +240639 == 212335 +241377 == 236546 +241903 == 202315 +241920 == 212335 +242606 unhandled syscall: setegid (in Ptrcheck) +242814 Helgrind "Impossible has happened" during + QApplication::initInstance(); +243064 Valgrind attempting to read debug information from iso +243270 Make stack unwinding in Valgrind wrappers more reliable +243884 exp-ptrcheck: the 'impossible happened: unhandled syscall + sysno = 277 (mq_open) +244009 exp-ptrcheck unknown syscalls in analyzing lighttpd +244493 ARM VFP d16-d31 registers support +244670 add support for audit_session_self syscall on Mac OS 10.6 +244921 The xml report of helgrind tool is not well format +244923 In the xml report file, the not escape the + xml char, eg '<','&','>' +245535 print full path names in plain text reports +245925 x86-64 red zone handling problem +246258 Valgrind not catching integer underruns + new [] s +246311 reg/reg cmpxchg doesn't work on amd64 +246549 unhandled syscall unix:277 while testing 32-bit Darwin app +246888 Improve Makefile.vex.am +247510 [OS X 10.6] Memcheck reports unaddressable bytes passed + to [f]chmod_extended +247526 IBM POWER6 (ISA 2.05) support is incomplete +247561 Some leak testcases fails due to reachable addresses in + caller save regs +247875 sizeofIRType to handle Ity_I128 +247894 [PATCH] unhandled syscall sys_readahead +247980 Doesn't honor CFLAGS passed to configure +248373 darwin10.supp is empty in the trunk +248822 Linux FIBMAP ioctl has int parameter instead of long +248893 [PATCH] make readdwarf.c big endianess safe to enable + unwinding on big endian systems +249224 Syscall 336 not supported (SYS_proc_info) +249359 == 245535 +249775 Incorrect scheme for detecting NEON capabilities of host CPU +249943 jni JVM init fails when using valgrind +249991 Valgrind incorrectly declares AESKEYGENASSIST support + since VEX r2011 +249996 linux/arm: unhandled syscall: 181 (__NR_pwrite64) +250799 frexp$fenv_access_off function generates SIGILL +250998 vex x86->IR: unhandled instruction bytes: 0x66 0x66 0x66 0x2E +251251 support pclmulqdq insn +251362 valgrind: ARM: attach to debugger either fails or provokes + kernel oops +251674 Unhandled syscall 294 +251818 == 254550 + +254257 Add support for debugfiles found by build-id +254550 [PATCH] Implement DW_ATE_UTF (DWARF4) +254646 Wrapped functions cause stack misalignment on OS X + (and possibly Linux) +254556 ARM: valgrinding anything fails with SIGSEGV for 0xFFFF0FA0 + +(3.6.0: 21 October 2010, vex r2068, valgrind r11471). + + + Release 3.5.0 (19 August 2009) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3.5.0 is a feature release with many significant improvements and the @@ -123,7 +442,7 @@ many other minor changes, and a list of fixed bugs. changes above for more details). This was also necessary to fix a longstanding bug in which uses of suppressions against leaks were not "counted", leading to difficulties in maintaining suppression - files (XXXX bug number). + files (see https://bugs.kde.org/show_bug.cgi?id=186790). - Behavior of -v has changed. In previous versions, -v printed out a mixture of marginally-user-useful information, and tool/core @@ -502,7 +821,6 @@ where XXXXXX is the bug number as listed below. 190391 dup of 181394; see above 190429 Valgrind reports lots of errors in ld.so with x86_64 2.9.90 glibc 190820 No debug information on powerpc-linux -190820 No debug information on powerpc-linux 191095 PATCH: Improve usbdevfs ioctl handling 191182 memcheck: VALGRIND_LEAK_CHECK quadratic when big nr of chunks or big nr of errors @@ -561,7 +879,7 @@ n-i-bz drd: fixed a bug that caused incorrect messages to be printed about memory allocation events with memory access tracing enabled n-i-bz drd: fixed a memory leak triggered by vector clock deallocation -(3.5.0: 20 Aug 2009, vex r1913, valgrind r10846). +(3.5.0: 19 Aug 2009, vex r1913, valgrind r10846). @@ -1879,6 +2197,13 @@ BUGS FIXED: +Stable release 2.4.1 (1 August 2005) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +(The notes for this release have been lost. Sorry! It would have +contained various bug fixes but no new features.) + + + Stable release 2.4.0 (March 2005) -- CHANGES RELATIVE TO 2.2.0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2.4.0 brings many significant changes and bug fixes. The most diff --git a/README b/README index 71c525f..2811aee 100644 --- a/README +++ b/README @@ -14,16 +14,17 @@ If you have problems, consult the FAQ to see if there are workarounds. Executive Summary ~~~~~~~~~~~~~~~~~ -Valgrind is an award-winning instrumentation framework for building -dynamic analysis tools. There are Valgrind tools that can automatically -detect many memory management and threading bugs, and profile your -programs in detail. You can also use Valgrind to build new tools. +Valgrind is a framework for building dynamic analysis tools. There are +Valgrind tools that can automatically detect many memory management +and threading bugs, and profile your programs in detail. You can also +use Valgrind to build new tools. The Valgrind distribution currently includes six production-quality -tools: a memory error detector, two thread error detectors, a cache and -branch-prediction profiler, a call-graph generating cache profiler, and -a heap profiler. It also includes two experimental tools: a -heap/stack/global array overrun detector, and a SimPoint basic block vector +tools: a memory error detector, two thread error detectors, a cache +and branch-prediction profiler, a call-graph generating cache abd +branch-prediction profiler, and a heap profiler. It also includes +three experimental tools: a heap/stack/global array overrun detector, +a different kind of heap profiler, and a SimPoint basic block vector generator. Valgrind is closely tied to details of the CPU, operating system and to @@ -35,6 +36,7 @@ platforms: - AMD64/Linux - PPC32/Linux - PPC64/Linux +- ARM/Linux - x86/MacOSX - AMD64/MacOSX @@ -45,6 +47,9 @@ on Intel processors. Also note that the core of MacOSX is called Valgrind is licensed under the GNU General Public License, version 2. Read the file COPYING in the source distribution for details. +However: if you contribute code, you need to make it available as GPL +version 2 or later, and not 2-only. + Documentation ~~~~~~~~~~~~~ diff --git a/README_DEVELOPERS b/README_DEVELOPERS index e08d872..9d523db 100644 --- a/README_DEVELOPERS +++ b/README_DEVELOPERS @@ -101,6 +101,21 @@ without too much problem by following these steps: Steps (1)--(3) can be put in a .gdbinit file, but any directory names must be fully expanded (ie. not an environment variable). +A different and possibly easier way is as follows: + +(1) Run Valgrind as normal, but add the flag --wait-for-gdb=yes. This + puts the tool executable into a wait loop soon after it gains + control. This delays startup for a few seconds. + +(2) In a different shell, do "gdb /proc//exe ", where + you read from the output printed by (1). This attaches + GDB to the tool executable, which should be in the abovementioned + wait loop. + +(3) Do "cont" to continue. After the loop finishes spinning, startup + will continue as normal. Note that comment (3) above re passing + signals applies here too. + Self-hosting ~~~~~~~~~~~~ diff --git a/README_MISSING_SYSCALL_OR_IOCTL b/README_MISSING_SYSCALL_OR_IOCTL index 2f4e81d..27d1ab0 100644 --- a/README_MISSING_SYSCALL_OR_IOCTL +++ b/README_MISSING_SYSCALL_OR_IOCTL @@ -107,7 +107,7 @@ following: 1. Find out the name of the system call: - grep NNN /usr/include/asm/unistd.h + grep NNN /usr/include/asm/unistd*.h This should tell you something like __NR_mysyscallname. Copy this entry to include/vki/vki-scnums-$(VG_PLATFORM).h. diff --git a/VEX/HACKING.README b/VEX/HACKING.README index ab57565..195a67e 100644 --- a/VEX/HACKING.README +++ b/VEX/HACKING.README @@ -1,17 +1,5 @@ This directory and its children contain LibVEX, a library for dynamic -binary instrumentation and translation. +binary instrumentation and translation. See LICENSE.README for +licensing and contribution information. -Changes: if you wish to contribute a change which is a significant one -in terms of the amount of code changes, please be aware that OpenWorks -LLP wishes to retain copyright of the Vex library. Therefore you will -have to sign over copyright ownership of your code to OpenWorks LLP -before we can include your changes in the main source tree. - -Before you start modifying anything for real, you should probably join -the valgrind-developers mailing list and send it mail describing what -you want to do and how you want to do it so you don't waste time -working on something we can't integrate. This also allows us to keep -track of what's being worked on so efforts aren't duplicated. - -Please also read the information in the file LICENSE.README. diff --git a/VEX/LICENSE.README b/VEX/LICENSE.README index 4c62b6c..339b33d 100644 --- a/VEX/LICENSE.README +++ b/VEX/LICENSE.README @@ -2,37 +2,22 @@ This directory and its children contain LibVEX, a library for dynamic binary instrumentation and translation. -Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. -This library is made available under a dual licensing scheme. + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. -If you link LibVEX against other code all of which is itself licensed -under the GNU General Public License, version 2 dated June 1991 ("GPL -v2"), then you may use LibVEX under the terms of the GPL v2, as -appearing in the file LICENSE.GPL. If the file LICENSE.GPL is -missing, you can obtain a copy of the GPL v2 from the Free Software -Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, -USA. + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. -For any other uses of LibVEX, you must first obtain a commercial -license from OpenWorks LLP. Please contact info@open-works.co.uk for -information about commercial licensing. + The GNU General Public License is contained in the file LICENSE.GPL. -This software is provided by OpenWorks LLP "as is" and any express or -implied warranties, including, but not limited to, the implied -warranties of merchantability and fitness for a particular purpose are -disclaimed. In no event shall OpenWorks LLP be liable for any direct, -indirect, incidental, special, exemplary, or consequential damages -(including, but not limited to, procurement of substitute goods or -services; loss of use, data, or profits; or business interruption) -however caused and on any theory of liability, whether in contract, -strict liability, or tort (including negligence or otherwise) arising -in any way out of the use of this software, even if advised of the -possibility of such damage. - -Neither the names of the U.S. Department of Energy nor the University -of California nor the names of its contributors may be used to endorse -or promote products derived from this software without prior written -permission. - -Please also read the information in the file HACKING.README. +If you want to contribute code to LibVEX, please ensure it is licensed +as "GPL v2 or later". diff --git a/VEX/Makefile-gcc b/VEX/Makefile-gcc index efa7af4..d1e1df4 100644 --- a/VEX/Makefile-gcc +++ b/VEX/Makefile-gcc @@ -17,6 +17,7 @@ PRIV_HEADERS = priv/host_x86_defs.h \ priv/host_ppc_defs.h \ priv/host_generic_regs.h \ priv/host_generic_simd64.h \ + priv/host_generic_simd128.h \ priv/main_globals.h \ priv/main_util.h \ priv/guest_generic_x87.h \ @@ -44,6 +45,7 @@ LIB_OBJS = priv/ir_defs.o \ priv/host_ppc_isel.o \ priv/host_generic_regs.o \ priv/host_generic_simd64.o \ + priv/host_generic_simd128.o \ priv/host_generic_reg_alloc2.o \ priv/guest_generic_x87.o \ priv/guest_generic_bb_to_IR.o \ @@ -98,7 +100,7 @@ all: vex # Empty, needed for Valgrind install: -scratch: clean version all +scratch: clean all vex: libvex.a test_main.o $(CC) $(CCFLAGS) -o vex test_main.o libvex.a @@ -162,33 +164,20 @@ TAG-amd64-darwin: touch TAG-amd64-darwin -# This doesn't get rid of priv/main/vex_svnversion.h, because -# that can't be regenerated in the final Valgrind tarball, and -# so if 'make clean' did get rid of it, then in the tarball, -# doing 'make ; make clean ; make' (or distclean) would fail. clean: rm -f $(LIB_OBJS) *.a vex test_main.o TAG-* \ pub/libvex_guest_offsets.h \ auxprogs/genoffsets.s -version: - rm -f priv/main/vex_svnversion.h - cat quote.txt >> priv/main/vex_svnversion.h - svnversion -n . >> priv/main/vex_svnversion.h - cat quote.txt >> priv/main/vex_svnversion.h - cat newline.txt >> priv/main/vex_svnversion.h - -minidist: version +minidist: rm -f vex--minidist-2005MMDD.tar tar cf vex--minidist-2005MMDD.tar $(PUB_HEADERS) $(PRIV_HEADERS) \ - priv/main/vex_svnversion.h \ test_main.c test_main.h \ Makefile \ `echo $(LIB_OBJS) | sed "s/\.o/\.c/g"` @echo - @echo minidist done, size and svnversion follow: + @echo minidist done, size follows: @ls -l vex--minidist-2005MMDD.tar - @cat priv/main/vex_svnversion.h @echo # This is very uggerly. Need to sed out both "xyzzyN" and @@ -223,8 +212,7 @@ priv/ir_opt.o: $(ALL_HEADERS) priv/ir_opt.c $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/ir_opt.o \ -c priv/ir_opt.c -priv/main_main.o: $(ALL_HEADERS) priv/main_main.c \ - priv/main/vex_svnversion.h +priv/main_main.o: $(ALL_HEADERS) priv/main_main.c $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/main_main.o \ -c priv/main_main.c @@ -276,6 +264,10 @@ priv/host_generic_simd64.o: $(ALL_HEADERS) priv/host_generic_simd64.c $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_simd64.o \ -c priv/host_generic_simd64.c +priv/host_generic_simd128.o: $(ALL_HEADERS) priv/host_generic_simd128.c + $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_simd128.o \ + -c priv/host_generic_simd128.c + priv/host_generic_reg_alloc2.o: $(ALL_HEADERS) priv/host_generic_reg_alloc2.c $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_reg_alloc2.o \ -c priv/host_generic_reg_alloc2.c diff --git a/VEX/auxprogs/genoffsets.c b/VEX/auxprogs/genoffsets.c index 4bb16b4..b379691 100644 --- a/VEX/auxprogs/genoffsets.c +++ b/VEX/auxprogs/genoffsets.c @@ -1,42 +1,31 @@ /*--------------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (auxprogs/genoffsets.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin genoffsets.c ---*/ /*--------------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -61,6 +50,7 @@ #include "../pub/libvex_guest_amd64.h" #include "../pub/libvex_guest_ppc32.h" #include "../pub/libvex_guest_ppc64.h" +#include "../pub/libvex_guest_arm.h" #define VG_STRINGIFZ(__str) #__str #define VG_STRINGIFY(__str) VG_STRINGIFZ(__str) @@ -126,6 +116,7 @@ void foo ( void ) // ppc32 GENOFFSET(PPC32,ppc32,GPR0); + GENOFFSET(PPC32,ppc32,GPR1); GENOFFSET(PPC32,ppc32,GPR2); GENOFFSET(PPC32,ppc32,GPR3); GENOFFSET(PPC32,ppc32,GPR4); @@ -140,6 +131,7 @@ void foo ( void ) // ppc64 GENOFFSET(PPC64,ppc64,GPR0); + GENOFFSET(PPC64,ppc64,GPR1); GENOFFSET(PPC64,ppc64,GPR2); GENOFFSET(PPC64,ppc64,GPR3); GENOFFSET(PPC64,ppc64,GPR4); @@ -151,4 +143,20 @@ void foo ( void ) GENOFFSET(PPC64,ppc64,GPR10); GENOFFSET(PPC64,ppc64,CIA); GENOFFSET(PPC64,ppc64,CR0_0); + + // arm + GENOFFSET(ARM,arm,R0); + GENOFFSET(ARM,arm,R1); + GENOFFSET(ARM,arm,R2); + GENOFFSET(ARM,arm,R3); + GENOFFSET(ARM,arm,R4); + GENOFFSET(ARM,arm,R5); + GENOFFSET(ARM,arm,R7); + GENOFFSET(ARM,arm,R13); + GENOFFSET(ARM,arm,R14); + GENOFFSET(ARM,arm,R15T); } + +/*--------------------------------------------------------------------*/ +/*--- end genoffsets.c ---*/ +/*--------------------------------------------------------------------*/ diff --git a/VEX/priv/guest_amd64_defs.h b/VEX/priv/guest_amd64_defs.h index 6fc52e4..42451fa 100644 --- a/VEX/priv/guest_amd64_defs.h +++ b/VEX/priv/guest_amd64_defs.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_amd64_defs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_amd64_defs.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -60,6 +49,7 @@ extern DisResult disInstr_AMD64 ( IRSB* irbb, Bool put_IP, Bool (*resteerOkFn) ( void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, UChar* guest_code, Long delta, @@ -71,8 +61,10 @@ DisResult disInstr_AMD64 ( IRSB* irbb, /* Used by the optimiser to specialise calls to helpers. */ extern -IRExpr* guest_amd64_spechelper ( HChar* function_name, - IRExpr** args ); +IRExpr* guest_amd64_spechelper ( HChar* function_name, + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ); /* Describes to the optimiser which part of the guest state require precise memory exceptions. This is logically part of the guest @@ -116,6 +108,8 @@ extern ULong amd64g_calculate_RCL ( ULong arg, ULong rot_amt, ULong rflags_in, Long sz ); +extern ULong amd64g_calculate_pclmul(ULong s1, ULong s2, ULong which); + extern ULong amd64g_check_fldcw ( ULong fpucw ); extern ULong amd64g_create_fpucw ( ULong fpround ); @@ -152,6 +146,7 @@ extern void amd64g_dirtyhelper_storeF80le ( ULong/*addr*/, ULong/*data*/ ); extern void amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st ); extern void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st ); +extern void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st ); extern void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* ); @@ -163,6 +158,55 @@ extern ULong amd64g_dirtyhelper_IN ( ULong portno, ULong sz/*1,2 or 4*/ ); extern void amd64g_dirtyhelper_OUT ( ULong portno, ULong data, ULong sz/*1,2 or 4*/ ); +extern void amd64g_dirtyhelper_SxDT ( void* address, + ULong op /* 0 or 1 */ ); + +/* Helps with PCMP{I,E}STR{I,M}. + + CALLED FROM GENERATED CODE: DIRTY HELPER(s). (But not really, + actually it could be a clean helper, but for the fact that we can't + pass by value 2 x V128 to a clean helper, nor have one returned.) + Reads guest state, writes to guest state for the xSTRM cases, no + accesses of memory, is a pure function. + + opc_and_imm contains (4th byte of opcode << 8) | the-imm8-byte so + the callee knows which I/E and I/M variant it is dealing with and + what the specific operation is. 4th byte of opcode is in the range + 0x60 to 0x63: + istri 66 0F 3A 63 + istrm 66 0F 3A 62 + estri 66 0F 3A 61 + estrm 66 0F 3A 60 + + gstOffL and gstOffR are the guest state offsets for the two XMM + register inputs. We never have to deal with the memory case since + that is handled by pre-loading the relevant value into the fake + XMM16 register. + + For ESTRx variants, edxIN and eaxIN hold the values of those two + registers. + + In all cases, the bottom 16 bits of the result contain the new + OSZACP %rflags values. For xSTRI variants, bits[31:16] of the + result hold the new %ecx value. For xSTRM variants, the helper + writes the result directly to the guest XMM0. + + Declarable side effects: in all cases, reads guest state at + [gstOffL, +16) and [gstOffR, +16). For xSTRM variants, also writes + guest_XMM0. + + Is expected to be called with opc_and_imm combinations which have + actually been validated, and will assert if otherwise. The front + end should ensure we're only called with verified values. +*/ +extern ULong amd64g_dirtyhelper_PCMPxSTRx ( + VexGuestAMD64State*, + HWord opc4_and_imm, + HWord gstOffL, HWord gstOffR, + HWord edxIN, HWord eaxIN + ); + + //extern void amd64g_dirtyhelper_CPUID_sse0 ( VexGuestAMD64State* ); //extern void amd64g_dirtyhelper_CPUID_sse1 ( VexGuestAMD64State* ); //extern void amd64g_dirtyhelper_CPUID_sse2 ( VexGuestAMD64State* ); diff --git a/VEX/priv/guest_amd64_helpers.c b/VEX/priv/guest_amd64_helpers.c index 24c206e..a920ecd 100644 --- a/VEX/priv/guest_amd64_helpers.c +++ b/VEX/priv/guest_amd64_helpers.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_amd64_helpers.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_amd64_helpers.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -835,6 +824,9 @@ ULong LibVEX_GuestAMD64_get_rflags ( /*IN*/VexGuestAMD64State* vex_state ) rflags |= (1<<10); if (vex_state->guest_IDFLAG == 1) rflags |= (1<<21); + if (vex_state->guest_ACFLAG == 1) + rflags |= (1<<18); + return rflags; } @@ -878,7 +870,9 @@ static Bool isU64 ( IRExpr* e, ULong n ) } IRExpr* guest_amd64_spechelper ( HChar* function_name, - IRExpr** args ) + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ) { # define unop(_op,_a1) IRExpr_Unop((_op),(_a1)) # define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2)) @@ -994,6 +988,17 @@ IRExpr* guest_amd64_spechelper ( HChar* function_name, binop(Iop_Shl64,cc_dep1,mkU8(32)), binop(Iop_Shl64,cc_dep2,mkU8(32)))); + } + if (isU64(cc_op, AMD64G_CC_OP_SUBL) && isU64(cond, AMD64CondNLE)) { + /* long sub/cmp, then NLE (signed greater than) + --> test !(dst <=s src) + --> test (dst >s src) + --> test (src test (dst-src test dst!=0 */ + return unop(Iop_1Uto64, + binop(Iop_CmpNE64, binop(Iop_And64,cc_dep1,mkU64(255)), + mkU64(0))); + } if (isU64(cc_op, AMD64G_CC_OP_LOGICB) && isU64(cond, AMD64CondS)) { /* this is an idiom gcc sometimes uses to find out if the top @@ -1162,11 +1183,12 @@ IRExpr* guest_amd64_spechelper ( HChar* function_name, /*---------------- INCB ----------------*/ if (isU64(cc_op, AMD64G_CC_OP_INCB) && isU64(cond, AMD64CondLE)) { - /* 8-bit inc, then LE --> test result <=s 0 */ - return unop(Iop_1Uto64, - binop(Iop_CmpLE64S, - binop(Iop_Shl64,cc_dep1,mkU8(56)), - mkU64(0))); + /* 8-bit inc, then LE --> sign bit of the arg */ + return binop(Iop_And64, + binop(Iop_Shr64, + binop(Iop_Sub64, cc_dep1, mkU64(1)), + mkU8(7)), + mkU64(1)); } /*---------------- INCW ----------------*/ @@ -1992,6 +2014,162 @@ void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st ) } +/* Claim to be the following CPU (4 x ...), which is sse4.2 and cx16 + capable. + + vendor_id : GenuineIntel + cpu family : 6 + model : 37 + model name : Intel(R) Core(TM) i5 CPU 670 @ 3.47GHz + stepping : 2 + cpu MHz : 3334.000 + cache size : 4096 KB + physical id : 0 + siblings : 4 + core id : 0 + cpu cores : 2 + apicid : 0 + initial apicid : 0 + fpu : yes + fpu_exception : yes + cpuid level : 11 + wp : yes + flags : fpu vme de pse tsc msr pae mce cx8 apic sep + mtrr pge mca cmov pat pse36 clflush dts acpi + mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp + lm constant_tsc arch_perfmon pebs bts rep_good + xtopology nonstop_tsc aperfmperf pni pclmulqdq + dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 + xtpr pdcm sse4_1 sse4_2 popcnt aes lahf_lm ida + arat tpr_shadow vnmi flexpriority ept vpid + MINUS aes (see below) + bogomips : 6957.57 + clflush size : 64 + cache_alignment : 64 + address sizes : 36 bits physical, 48 bits virtual + power management: +*/ +void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st ) +{ +# define SET_ABCD(_a,_b,_c,_d) \ + do { st->guest_RAX = (ULong)(_a); \ + st->guest_RBX = (ULong)(_b); \ + st->guest_RCX = (ULong)(_c); \ + st->guest_RDX = (ULong)(_d); \ + } while (0) + + UInt old_eax = (UInt)st->guest_RAX; + UInt old_ecx = (UInt)st->guest_RCX; + + switch (old_eax) { + case 0x00000000: + SET_ABCD(0x0000000b, 0x756e6547, 0x6c65746e, 0x49656e69); + break; + case 0x00000001: + // & ~(1<<25): don't claim to support AES insns. See + // bug 249991. + SET_ABCD(0x00020652, 0x00100800, 0x0298e3ff & ~(1<<25), + 0xbfebfbff); + break; + case 0x00000002: + SET_ABCD(0x55035a01, 0x00f0b2e3, 0x00000000, 0x09ca212c); + break; + case 0x00000003: + SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000); + break; + case 0x00000004: + switch (old_ecx) { + case 0x00000000: SET_ABCD(0x1c004121, 0x01c0003f, + 0x0000003f, 0x00000000); break; + case 0x00000001: SET_ABCD(0x1c004122, 0x00c0003f, + 0x0000007f, 0x00000000); break; + case 0x00000002: SET_ABCD(0x1c004143, 0x01c0003f, + 0x000001ff, 0x00000000); break; + case 0x00000003: SET_ABCD(0x1c03c163, 0x03c0003f, + 0x00000fff, 0x00000002); break; + default: SET_ABCD(0x00000000, 0x00000000, + 0x00000000, 0x00000000); break; + } + break; + case 0x00000005: + SET_ABCD(0x00000040, 0x00000040, 0x00000003, 0x00001120); + break; + case 0x00000006: + SET_ABCD(0x00000007, 0x00000002, 0x00000001, 0x00000000); + break; + case 0x00000007: + SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000); + break; + case 0x00000008: + SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000); + break; + case 0x00000009: + SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000); + break; + case 0x0000000a: + SET_ABCD(0x07300403, 0x00000004, 0x00000000, 0x00000603); + break; + case 0x0000000b: + switch (old_ecx) { + case 0x00000000: + SET_ABCD(0x00000001, 0x00000002, + 0x00000100, 0x00000000); break; + case 0x00000001: + SET_ABCD(0x00000004, 0x00000004, + 0x00000201, 0x00000000); break; + default: + SET_ABCD(0x00000000, 0x00000000, + old_ecx, 0x00000000); break; + } + break; + case 0x0000000c: + SET_ABCD(0x00000001, 0x00000002, 0x00000100, 0x00000000); + break; + case 0x0000000d: + switch (old_ecx) { + case 0x00000000: SET_ABCD(0x00000001, 0x00000002, + 0x00000100, 0x00000000); break; + case 0x00000001: SET_ABCD(0x00000004, 0x00000004, + 0x00000201, 0x00000000); break; + default: SET_ABCD(0x00000000, 0x00000000, + old_ecx, 0x00000000); break; + } + break; + case 0x80000000: + SET_ABCD(0x80000008, 0x00000000, 0x00000000, 0x00000000); + break; + case 0x80000001: + SET_ABCD(0x00000000, 0x00000000, 0x00000001, 0x28100800); + break; + case 0x80000002: + SET_ABCD(0x65746e49, 0x2952286c, 0x726f4320, 0x4d542865); + break; + case 0x80000003: + SET_ABCD(0x35692029, 0x55504320, 0x20202020, 0x20202020); + break; + case 0x80000004: + SET_ABCD(0x30373620, 0x20402020, 0x37342e33, 0x007a4847); + break; + case 0x80000005: + SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000); + break; + case 0x80000006: + SET_ABCD(0x00000000, 0x00000000, 0x01006040, 0x00000000); + break; + case 0x80000007: + SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000100); + break; + case 0x80000008: + SET_ABCD(0x00003024, 0x00000000, 0x00000000, 0x00000000); + break; + default: + SET_ABCD(0x00000001, 0x00000002, 0x00000100, 0x00000000); + break; + } +# undef SET_ABCD +} + + ULong amd64g_calculate_RCR ( ULong arg, ULong rot_amt, ULong rflags_in, @@ -2126,6 +2304,51 @@ ULong amd64g_calculate_RCL ( ULong arg, return wantRflags ? rflags_in : arg; } +/* Taken from gf2x-0.9.5, released under GPLv2+ (later versions LGPLv2+) + * svn://scm.gforge.inria.fr/svn/gf2x/trunk/hardware/opteron/gf2x_mul1.h@25 + */ +ULong amd64g_calculate_pclmul(ULong a, ULong b, ULong which) +{ + ULong hi, lo, tmp, A[16]; + + A[0] = 0; A[1] = a; + A[2] = A[1] << 1; A[3] = A[2] ^ a; + A[4] = A[2] << 1; A[5] = A[4] ^ a; + A[6] = A[3] << 1; A[7] = A[6] ^ a; + A[8] = A[4] << 1; A[9] = A[8] ^ a; + A[10] = A[5] << 1; A[11] = A[10] ^ a; + A[12] = A[6] << 1; A[13] = A[12] ^ a; + A[14] = A[7] << 1; A[15] = A[14] ^ a; + + lo = (A[b >> 60] << 4) ^ A[(b >> 56) & 15]; + hi = lo >> 56; + lo = (lo << 8) ^ (A[(b >> 52) & 15] << 4) ^ A[(b >> 48) & 15]; + hi = (hi << 8) | (lo >> 56); + lo = (lo << 8) ^ (A[(b >> 44) & 15] << 4) ^ A[(b >> 40) & 15]; + hi = (hi << 8) | (lo >> 56); + lo = (lo << 8) ^ (A[(b >> 36) & 15] << 4) ^ A[(b >> 32) & 15]; + hi = (hi << 8) | (lo >> 56); + lo = (lo << 8) ^ (A[(b >> 28) & 15] << 4) ^ A[(b >> 24) & 15]; + hi = (hi << 8) | (lo >> 56); + lo = (lo << 8) ^ (A[(b >> 20) & 15] << 4) ^ A[(b >> 16) & 15]; + hi = (hi << 8) | (lo >> 56); + lo = (lo << 8) ^ (A[(b >> 12) & 15] << 4) ^ A[(b >> 8) & 15]; + hi = (hi << 8) | (lo >> 56); + lo = (lo << 8) ^ (A[(b >> 4) & 15] << 4) ^ A[b & 15]; + + ULong m0 = -1; + m0 /= 255; + tmp = -((a >> 63) & 1); tmp &= ((b & (m0 * 0xfe)) >> 1); hi = hi ^ tmp; + tmp = -((a >> 62) & 1); tmp &= ((b & (m0 * 0xfc)) >> 2); hi = hi ^ tmp; + tmp = -((a >> 61) & 1); tmp &= ((b & (m0 * 0xf8)) >> 3); hi = hi ^ tmp; + tmp = -((a >> 60) & 1); tmp &= ((b & (m0 * 0xf0)) >> 4); hi = hi ^ tmp; + tmp = -((a >> 59) & 1); tmp &= ((b & (m0 * 0xe0)) >> 5); hi = hi ^ tmp; + tmp = -((a >> 58) & 1); tmp &= ((b & (m0 * 0xc0)) >> 6); hi = hi ^ tmp; + tmp = -((a >> 57) & 1); tmp &= ((b & (m0 * 0x80)) >> 7); hi = hi ^ tmp; + + return which ? hi : lo; +} + /* CALLED FROM GENERATED CODE */ /* DIRTY HELPER (non-referentially-transparent) */ @@ -2201,6 +2424,31 @@ void amd64g_dirtyhelper_OUT ( ULong portno, ULong data, ULong sz/*1,2 or 4*/ ) # endif } +/* CALLED FROM GENERATED CODE */ +/* DIRTY HELPER (non-referentially-transparent) */ +/* Horrible hack. On non-amd64 platforms, do nothing. */ +/* op = 0: call the native SGDT instruction. + op = 1: call the native SIDT instruction. +*/ +void amd64g_dirtyhelper_SxDT ( void *address, ULong op ) { +# if defined(__x86_64__) + switch (op) { + case 0: + __asm__ __volatile__("sgdt (%0)" : : "r" (address) : "memory"); + break; + case 1: + __asm__ __volatile__("sidt (%0)" : : "r" (address) : "memory"); + break; + default: + vpanic("amd64g_dirtyhelper_SxDT"); + } +# else + /* do nothing */ + UChar* p = (UChar*)address; + p[0] = p[1] = p[2] = p[3] = p[4] = p[5] = 0; + p[6] = p[7] = p[8] = p[9] = 0; +# endif +} /*---------------------------------------------------------------*/ /*--- Helpers for MMX/SSE/SSE2. ---*/ @@ -2316,6 +2564,130 @@ ULong amd64g_calculate_sse_pmovmskb ( ULong w64hi, ULong w64lo ) } +/*---------------------------------------------------------------*/ +/*--- Helpers for SSE4.2 PCMP{E,I}STR{I,M} ---*/ +/*---------------------------------------------------------------*/ + +static UInt zmask_from_V128 ( V128* arg ) +{ + UInt i, res = 0; + for (i = 0; i < 16; i++) { + res |= ((arg->w8[i] == 0) ? 1 : 0) << i; + } + return res; +} + +/* Helps with PCMP{I,E}STR{I,M}. + + CALLED FROM GENERATED CODE: DIRTY HELPER(s). (But not really, + actually it could be a clean helper, but for the fact that we can't + pass by value 2 x V128 to a clean helper, nor have one returned.) + Reads guest state, writes to guest state for the xSTRM cases, no + accesses of memory, is a pure function. + + opc_and_imm contains (4th byte of opcode << 8) | the-imm8-byte so + the callee knows which I/E and I/M variant it is dealing with and + what the specific operation is. 4th byte of opcode is in the range + 0x60 to 0x63: + istri 66 0F 3A 63 + istrm 66 0F 3A 62 + estri 66 0F 3A 61 + estrm 66 0F 3A 60 + + gstOffL and gstOffR are the guest state offsets for the two XMM + register inputs. We never have to deal with the memory case since + that is handled by pre-loading the relevant value into the fake + XMM16 register. + + For ESTRx variants, edxIN and eaxIN hold the values of those two + registers. + + In all cases, the bottom 16 bits of the result contain the new + OSZACP %rflags values. For xSTRI variants, bits[31:16] of the + result hold the new %ecx value. For xSTRM variants, the helper + writes the result directly to the guest XMM0. + + Declarable side effects: in all cases, reads guest state at + [gstOffL, +16) and [gstOffR, +16). For xSTRM variants, also writes + guest_XMM0. + + Is expected to be called with opc_and_imm combinations which have + actually been validated, and will assert if otherwise. The front + end should ensure we're only called with verified values. +*/ +ULong amd64g_dirtyhelper_PCMPxSTRx ( + VexGuestAMD64State* gst, + HWord opc4_and_imm, + HWord gstOffL, HWord gstOffR, + HWord edxIN, HWord eaxIN + ) +{ + HWord opc4 = (opc4_and_imm >> 8) & 0xFF; + HWord imm8 = opc4_and_imm & 0xFF; + HWord isISTRx = opc4 & 2; + HWord isxSTRM = (opc4 & 1) ^ 1; + vassert((opc4 & 0xFC) == 0x60); /* 0x60 .. 0x63 */ + vassert((imm8 & 1) == 0); /* we support byte-size cases only */ + + // where the args are + V128* argL = (V128*)( ((UChar*)gst) + gstOffL ); + V128* argR = (V128*)( ((UChar*)gst) + gstOffR ); + + /* Create the arg validity masks, either from the vectors + themselves or from the supplied edx/eax values. */ + // FIXME: this is only right for the 8-bit data cases. + // At least that is asserted above. + UInt zmaskL, zmaskR; + if (isISTRx) { + zmaskL = zmask_from_V128(argL); + zmaskR = zmask_from_V128(argR); + } else { + Int tmp; + tmp = edxIN & 0xFFFFFFFF; + if (tmp < -16) tmp = -16; + if (tmp > 16) tmp = 16; + if (tmp < 0) tmp = -tmp; + vassert(tmp >= 0 && tmp <= 16); + zmaskL = (1 << tmp) & 0xFFFF; + tmp = eaxIN & 0xFFFFFFFF; + if (tmp < -16) tmp = -16; + if (tmp > 16) tmp = 16; + if (tmp < 0) tmp = -tmp; + vassert(tmp >= 0 && tmp <= 16); + zmaskR = (1 << tmp) & 0xFFFF; + } + + // temp spot for the resulting flags and vector. + V128 resV; + UInt resOSZACP; + + // do the meyaath + Bool ok = compute_PCMPxSTRx ( + &resV, &resOSZACP, argL, argR, + zmaskL, zmaskR, imm8, (Bool)isxSTRM + ); + + // front end shouldn't pass us any imm8 variants we can't + // handle. Hence: + vassert(ok); + + // So, finally we need to get the results back to the caller. + // In all cases, the new OSZACP value is the lowest 16 of + // the return value. + if (isxSTRM) { + /* gst->guest_XMM0 = resV; */ // gcc don't like that + gst->guest_XMM0[0] = resV.w32[0]; + gst->guest_XMM0[1] = resV.w32[1]; + gst->guest_XMM0[2] = resV.w32[2]; + gst->guest_XMM0[3] = resV.w32[3]; + return resOSZACP & 0x8D5; + } else { + UInt newECX = resV.w32[0] & 0xFFFF; + return (newECX << 16) | (resOSZACP & 0x8D5); + } +} + + /*---------------------------------------------------------------*/ /*--- Helpers for dealing with, and describing, ---*/ /*--- guest state as a whole. ---*/ @@ -2379,6 +2751,7 @@ void LibVEX_GuestAMD64_initialise ( /*OUT*/VexGuestAMD64State* vex_state ) SSEZERO(vex_state->guest_XMM13); SSEZERO(vex_state->guest_XMM14); SSEZERO(vex_state->guest_XMM15); + SSEZERO(vex_state->guest_XMM16); # undef SSEZERO diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 1d55bc5..79b1269 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -1,42 +1,31 @@ /*--------------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_amd64_toIR.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_amd64_toIR.c ---*/ /*--------------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -312,12 +301,12 @@ static IRExpr* mkU ( IRType ty, ULong i ) static void storeLE ( IRExpr* addr, IRExpr* data ) { - stmt( IRStmt_Store(Iend_LE, IRTemp_INVALID, addr, data) ); + stmt( IRStmt_Store(Iend_LE, addr, data) ); } -static IRExpr* loadLE ( IRType ty, IRExpr* data ) +static IRExpr* loadLE ( IRType ty, IRExpr* addr ) { - return IRExpr_Load(False, Iend_LE, ty, data); + return IRExpr_Load(Iend_LE, ty, addr); } static IROp mkSizedOp ( IRType ty, IROp op8 ) @@ -422,6 +411,7 @@ static void unimplemented ( HChar* str ) #define OFFB_FPREGS offsetof(VexGuestAMD64State,guest_FPREG[0]) #define OFFB_FPTAGS offsetof(VexGuestAMD64State,guest_FPTAG[0]) #define OFFB_DFLAG offsetof(VexGuestAMD64State,guest_DFLAG) +#define OFFB_ACFLAG offsetof(VexGuestAMD64State,guest_ACFLAG) #define OFFB_IDFLAG offsetof(VexGuestAMD64State,guest_IDFLAG) #define OFFB_FTOP offsetof(VexGuestAMD64State,guest_FTOP) #define OFFB_FC3210 offsetof(VexGuestAMD64State,guest_FC3210) @@ -453,6 +443,7 @@ static void unimplemented ( HChar* str ) #define OFFB_XMM13 offsetof(VexGuestAMD64State,guest_XMM13) #define OFFB_XMM14 offsetof(VexGuestAMD64State,guest_XMM14) #define OFFB_XMM15 offsetof(VexGuestAMD64State,guest_XMM15) +#define OFFB_XMM16 offsetof(VexGuestAMD64State,guest_XMM16) #define OFFB_EMWARN offsetof(VexGuestAMD64State,guest_EMWARN) #define OFFB_TISTART offsetof(VexGuestAMD64State,guest_TISTART) @@ -752,6 +743,13 @@ static Bool haveF3no66noF2 ( Prefix pfx ) toBool((pfx & (PFX_66|PFX_F2|PFX_F3)) == PFX_F3); } +/* Return True iff pfx has F3 set and F2 clear */ +static Bool haveF3noF2 ( Prefix pfx ) +{ + return + toBool((pfx & (PFX_F2|PFX_F3)) == PFX_F3); +} + /* Return True iff pfx has 66, F2 and F3 clear */ static Bool haveNo66noF2noF3 ( Prefix pfx ) { @@ -972,7 +970,7 @@ static IRExpr* getIRegRAX ( Int sz ) switch (sz) { case 1: return IRExpr_Get( OFFB_RAX, Ity_I8 ); case 2: return IRExpr_Get( OFFB_RAX, Ity_I16 ); - case 4: return IRExpr_Get( OFFB_RAX, Ity_I32 ); + case 4: return unop(Iop_64to32, IRExpr_Get( OFFB_RAX, Ity_I64 )); case 8: return IRExpr_Get( OFFB_RAX, Ity_I64 ); default: vpanic("getIRegRAX(amd64)"); } @@ -1020,7 +1018,7 @@ static IRExpr* getIRegRDX ( Int sz ) switch (sz) { case 1: return IRExpr_Get( OFFB_RDX, Ity_I8 ); case 2: return IRExpr_Get( OFFB_RDX, Ity_I16 ); - case 4: return IRExpr_Get( OFFB_RDX, Ity_I32 ); + case 4: return unop(Iop_64to32, IRExpr_Get( OFFB_RDX, Ity_I64 )); case 8: return IRExpr_Get( OFFB_RDX, Ity_I64 ); default: vpanic("getIRegRDX(amd64)"); } @@ -1071,8 +1069,9 @@ static HChar* nameIReg64 ( UInt regno ) static IRExpr* getIReg32 ( UInt regno ) { vassert(!host_is_bigendian); - return IRExpr_Get( integerGuestReg64Offset(regno), - Ity_I32 ); + return unop(Iop_64to32, + IRExpr_Get( integerGuestReg64Offset(regno), + Ity_I64 )); } static void putIReg32 ( UInt regno, IRExpr* e ) @@ -1136,11 +1135,22 @@ static IRExpr* getIRegRexB ( Int sz, Prefix pfx, UInt lo3bits ) vassert(lo3bits < 8); vassert(IS_VALID_PFX(pfx)); vassert(sz == 8 || sz == 4 || sz == 2 || sz == 1); - return IRExpr_Get( - offsetIReg( sz, lo3bits | (getRexB(pfx) << 3), - toBool(sz==1 && !haveREX(pfx)) ), - szToITy(sz) - ); + if (sz == 4) { + sz = 8; + return unop(Iop_64to32, + IRExpr_Get( + offsetIReg( sz, lo3bits | (getRexB(pfx) << 3), + toBool(sz==1 && !haveREX(pfx)) ), + szToITy(sz) + ) + ); + } else { + return IRExpr_Get( + offsetIReg( sz, lo3bits | (getRexB(pfx) << 3), + toBool(sz==1 && !haveREX(pfx)) ), + szToITy(sz) + ); + } } static void putIRegRexB ( Int sz, Prefix pfx, UInt lo3bits, IRExpr* e ) @@ -1206,8 +1216,15 @@ static UInt offsetIRegG ( Int sz, Prefix pfx, UChar mod_reg_rm ) static IRExpr* getIRegG ( Int sz, Prefix pfx, UChar mod_reg_rm ) { - return IRExpr_Get( offsetIRegG( sz, pfx, mod_reg_rm ), - szToITy(sz) ); + if (sz == 4) { + sz = 8; + return unop(Iop_64to32, + IRExpr_Get( offsetIRegG( sz, pfx, mod_reg_rm ), + szToITy(sz) )); + } else { + return IRExpr_Get( offsetIRegG( sz, pfx, mod_reg_rm ), + szToITy(sz) ); + } } static @@ -1246,8 +1263,15 @@ static UInt offsetIRegE ( Int sz, Prefix pfx, UChar mod_reg_rm ) static IRExpr* getIRegE ( Int sz, Prefix pfx, UChar mod_reg_rm ) { - return IRExpr_Get( offsetIRegE( sz, pfx, mod_reg_rm ), - szToITy(sz) ); + if (sz == 4) { + sz = 8; + return unop(Iop_64to32, + IRExpr_Get( offsetIRegE( sz, pfx, mod_reg_rm ), + szToITy(sz) )); + } else { + return IRExpr_Get( offsetIRegE( sz, pfx, mod_reg_rm ), + szToITy(sz) ); + } } static @@ -1371,6 +1395,11 @@ static IRExpr* getXMMRegLane32F ( UInt xmmreg, Int laneno ) return IRExpr_Get( xmmGuestRegLane32offset(xmmreg,laneno), Ity_F32 ); } +static IRExpr* getXMMRegLane16 ( UInt xmmreg, Int laneno ) +{ + return IRExpr_Get( xmmGuestRegLane16offset(xmmreg,laneno), Ity_I16 ); +} + static void putXMMReg ( UInt xmmreg, IRExpr* e ) { vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_V128); @@ -4314,6 +4343,135 @@ ULong dis_imul_I_E_G ( VexAbiInfo* vbi, } +/* Generate an IR sequence to do a popcount operation on the supplied + IRTemp, and return a new IRTemp holding the result. 'ty' may be + Ity_I16, Ity_I32 or Ity_I64 only. */ +static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src ) +{ + Int i; + if (ty == Ity_I16) { + IRTemp old = IRTemp_INVALID; + IRTemp nyu = IRTemp_INVALID; + IRTemp mask[4], shift[4]; + for (i = 0; i < 4; i++) { + mask[i] = newTemp(ty); + shift[i] = 1 << i; + } + assign(mask[0], mkU16(0x5555)); + assign(mask[1], mkU16(0x3333)); + assign(mask[2], mkU16(0x0F0F)); + assign(mask[3], mkU16(0x00FF)); + old = src; + for (i = 0; i < 4; i++) { + nyu = newTemp(ty); + assign(nyu, + binop(Iop_Add16, + binop(Iop_And16, + mkexpr(old), + mkexpr(mask[i])), + binop(Iop_And16, + binop(Iop_Shr16, mkexpr(old), mkU8(shift[i])), + mkexpr(mask[i])))); + old = nyu; + } + return nyu; + } + if (ty == Ity_I32) { + IRTemp old = IRTemp_INVALID; + IRTemp nyu = IRTemp_INVALID; + IRTemp mask[5], shift[5]; + for (i = 0; i < 5; i++) { + mask[i] = newTemp(ty); + shift[i] = 1 << i; + } + assign(mask[0], mkU32(0x55555555)); + assign(mask[1], mkU32(0x33333333)); + assign(mask[2], mkU32(0x0F0F0F0F)); + assign(mask[3], mkU32(0x00FF00FF)); + assign(mask[4], mkU32(0x0000FFFF)); + old = src; + for (i = 0; i < 5; i++) { + nyu = newTemp(ty); + assign(nyu, + binop(Iop_Add32, + binop(Iop_And32, + mkexpr(old), + mkexpr(mask[i])), + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])), + mkexpr(mask[i])))); + old = nyu; + } + return nyu; + } + if (ty == Ity_I64) { + IRTemp old = IRTemp_INVALID; + IRTemp nyu = IRTemp_INVALID; + IRTemp mask[6], shift[6]; + for (i = 0; i < 6; i++) { + mask[i] = newTemp(ty); + shift[i] = 1 << i; + } + assign(mask[0], mkU64(0x5555555555555555ULL)); + assign(mask[1], mkU64(0x3333333333333333ULL)); + assign(mask[2], mkU64(0x0F0F0F0F0F0F0F0FULL)); + assign(mask[3], mkU64(0x00FF00FF00FF00FFULL)); + assign(mask[4], mkU64(0x0000FFFF0000FFFFULL)); + assign(mask[5], mkU64(0x00000000FFFFFFFFULL)); + old = src; + for (i = 0; i < 6; i++) { + nyu = newTemp(ty); + assign(nyu, + binop(Iop_Add64, + binop(Iop_And64, + mkexpr(old), + mkexpr(mask[i])), + binop(Iop_And64, + binop(Iop_Shr64, mkexpr(old), mkU8(shift[i])), + mkexpr(mask[i])))); + old = nyu; + } + return nyu; + } + /*NOTREACHED*/ + vassert(0); +} + + +/* Generate an IR sequence to do a count-leading-zeroes operation on + the supplied IRTemp, and return a new IRTemp holding the result. + 'ty' may be Ity_I16, Ity_I32 or Ity_I64 only. In the case where + the argument is zero, return the number of bits in the word (the + natural semantics). */ +static IRTemp gen_LZCNT ( IRType ty, IRTemp src ) +{ + vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16); + + IRTemp src64 = newTemp(Ity_I64); + assign(src64, widenUto64( mkexpr(src) )); + + IRTemp src64x = newTemp(Ity_I64); + assign(src64x, + binop(Iop_Shl64, mkexpr(src64), + mkU8(64 - 8 * sizeofIRType(ty)))); + + // Clz64 has undefined semantics when its input is zero, so + // special-case around that. + IRTemp res64 = newTemp(Ity_I64); + assign(res64, + IRExpr_Mux0X( + unop(Iop_1Uto8, + binop(Iop_CmpEQ64, mkexpr(src64x), mkU64(0))), + unop(Iop_Clz64, mkexpr(src64x)), + mkU64(8 * sizeofIRType(ty)) + )); + + IRTemp res = newTemp(ty); + assign(res, narrowTo(ty, mkexpr(res64))); + return res; +} + + /*------------------------------------------------------------*/ /*--- ---*/ /*--- x87 FLOATING POINT INSTRUCTIONS ---*/ @@ -5349,7 +5507,7 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, triop(fop, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ get_ST(0), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, loadLE(Ity_I32, mkexpr(addr))))); break; @@ -5357,7 +5515,7 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, put_ST_UNCHECKED(0, triop(fop, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ - unop(Iop_I32toF64, + unop(Iop_I32StoF64, loadLE(Ity_I32, mkexpr(addr))), get_ST(0))); break; @@ -5450,27 +5608,27 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, case 0: /* FILD m32int */ DIP("fildl %s\n", dis_buf); fp_push(); - put_ST(0, unop(Iop_I32toF64, + put_ST(0, unop(Iop_I32StoF64, loadLE(Ity_I32, mkexpr(addr)))); break; case 1: /* FISTTPL m32 (SSE3) */ DIP("fisttpl %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI32, mkU32(Irrm_ZERO), get_ST(0)) ); + binop(Iop_F64toI32S, mkU32(Irrm_ZERO), get_ST(0)) ); fp_pop(); break; case 2: /* FIST m32 */ DIP("fistl %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI32, get_roundingmode(), get_ST(0)) ); + binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ); break; case 3: /* FISTP m32 */ DIP("fistpl %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI32, get_roundingmode(), get_ST(0)) ); + binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ); fp_pop(); break; @@ -5781,7 +5939,7 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, case 1: /* FISTTPQ m64 (SSE3) */ DIP("fistppll %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI64, mkU32(Irrm_ZERO), get_ST(0)) ); + binop(Iop_F64toI64S, mkU32(Irrm_ZERO), get_ST(0)) ); fp_pop(); break; @@ -6025,7 +6183,7 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, triop(fop, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ get_ST(0), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(addr)))))); break; @@ -6034,7 +6192,7 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, put_ST_UNCHECKED(0, triop(fop, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(addr)))), get_ST(0))); @@ -6113,7 +6271,7 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, case 0: /* FILD m16int */ DIP("fildw %s\n", dis_buf); fp_push(); - put_ST(0, unop(Iop_I32toF64, + put_ST(0, unop(Iop_I32StoF64, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(addr))))); break; @@ -6122,28 +6280,29 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, DIP("fisttps %s\n", dis_buf); storeLE( mkexpr(addr), x87ishly_qnarrow_32_to_16( - binop(Iop_F64toI32, mkU32(Irrm_ZERO), get_ST(0)) )); + binop(Iop_F64toI32S, mkU32(Irrm_ZERO), get_ST(0)) )); fp_pop(); break; -//.. case 2: /* FIST m16 */ -//.. DIP("fistp %s\n", dis_buf); -//.. storeLE( mkexpr(addr), -//.. binop(Iop_F64toI16, get_roundingmode(), get_ST(0)) ); -//.. break; + case 2: /* FIST m16 */ + DIP("fists %s\n", dis_buf); + storeLE( mkexpr(addr), + x87ishly_qnarrow_32_to_16( + binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) )); + break; case 3: /* FISTP m16 */ DIP("fistps %s\n", dis_buf); storeLE( mkexpr(addr), x87ishly_qnarrow_32_to_16( - binop(Iop_F64toI32, get_roundingmode(), get_ST(0)) )); + binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) )); fp_pop(); break; case 5: /* FILD m64 */ DIP("fildll %s\n", dis_buf); fp_push(); - put_ST(0, binop(Iop_I64toF64, + put_ST(0, binop(Iop_I64StoF64, get_roundingmode(), loadLE(Ity_I64, mkexpr(addr)))); break; @@ -6151,7 +6310,7 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok, case 7: /* FISTP m64 */ DIP("fistpll %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI64, get_roundingmode(), get_ST(0)) ); + binop(Iop_F64toI64S, get_roundingmode(), get_ST(0)) ); fp_pop(); break; @@ -7210,11 +7369,25 @@ ULong dis_bt_G_E ( VexAbiInfo* vbi, if (epartIsReg(modrm)) { delta++; - /* Get it onto the client's stack. */ + /* Get it onto the client's stack. Oh, this is a horrible + kludge. See https://bugs.kde.org/show_bug.cgi?id=245925. + Because of the ELF ABI stack redzone, there may be live data + up to 128 bytes below %RSP. So we can't just push it on the + stack, else we may wind up trashing live data, and causing + impossible-to-find simulation errors. (Yes, this did + happen.) So we need to drop RSP before at least 128 before + pushing it. That unfortunately means hitting Memcheck's + fast-case painting code. Ideally we should drop more than + 128, to reduce the chances of breaking buggy programs that + have live data below -128(%RSP). Memcheck fast-cases moves + of 288 bytes due to the need to handle ppc64-linux quickly, + so let's use 288. Of course the real fix is to get rid of + this kludge entirely. */ t_rsp = newTemp(Ity_I64); t_addr0 = newTemp(Ity_I64); - assign( t_rsp, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(sz)) ); + vassert(vbi->guest_stack_redzone_size == 128); + assign( t_rsp, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(288)) ); putIReg64(R_RSP, mkexpr(t_rsp)); storeLE( mkexpr(t_rsp), getIRegE(sz, pfx, modrm) ); @@ -7313,7 +7486,7 @@ ULong dis_bt_G_E ( VexAbiInfo* vbi, standard zero-extend rule */ if (op != BtOpNone) putIRegE(sz, pfx, modrm, loadLE(szToITy(sz), mkexpr(t_rsp)) ); - putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t_rsp), mkU64(sz)) ); + putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t_rsp), mkU64(288)) ); } DIP("bt%s%c %s, %s\n", @@ -7553,9 +7726,6 @@ ULong dis_cmpxchg_G_E ( /*OUT*/Bool* ok, if (epartIsReg(rm)) { /* case 1 */ - *ok = False; - return delta0; - /* awaiting test case */ assign( dest, getIRegE(size, pfx, rm) ); delta0++; assign( src, getIRegG(size, pfx, rm) ); @@ -7699,7 +7869,8 @@ ULong dis_xadd_G_E ( /*OUT*/Bool* decode_ok, /* There are 3 cases to consider: - reg-reg: currently unhandled + reg-reg: ignore any lock prefix, + generate 'naive' (non-atomic) sequence reg-mem, not locked: ignore any lock prefix, generate 'naive' (non-atomic) sequence @@ -7709,9 +7880,18 @@ ULong dis_xadd_G_E ( /*OUT*/Bool* decode_ok, if (epartIsReg(rm)) { /* case 1 */ - *decode_ok = False; - return delta0; - /* Currently we don't handle xadd_G_E with register operand. */ + assign( tmpd, getIRegE(sz, pfx, rm) ); + assign( tmpt0, getIRegG(sz, pfx, rm) ); + assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8), + mkexpr(tmpd), mkexpr(tmpt0)) ); + setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty ); + putIRegG(sz, pfx, rm, mkexpr(tmpd)); + putIRegE(sz, pfx, rm, mkexpr(tmpt1)); + DIP("xadd%c %s, %s\n", + nameISize(sz), nameIRegG(sz,pfx,rm), + nameIRegE(sz,pfx,rm)); + *decode_ok = True; + return 1+delta0; } else if (!epartIsReg(rm) && !(pfx & PFX_LOCK)) { /* case 2 */ @@ -8802,6 +8982,7 @@ DisResult disInstr_AMD64_WRK ( /*OUT*/Bool* expect_CAS, Bool put_IP, Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, Long delta64, VexArchInfo* archinfo, @@ -9192,14 +9373,14 @@ DisResult disInstr_AMD64_WRK ( gregOfRexRM(pfx,modrm), 0, binop(Iop_F64toF32, mkexpr(rmode), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)) )) ); putXMMRegLane32F( gregOfRexRM(pfx,modrm), 1, binop(Iop_F64toF32, mkexpr(rmode), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)) )) ); goto decode_success; @@ -9233,7 +9414,7 @@ DisResult disInstr_AMD64_WRK ( gregOfRexRM(pfx,modrm), 0, binop(Iop_F64toF32, mkexpr(rmode), - unop(Iop_I32toF64, mkexpr(arg32)) ) ); + unop(Iop_I32StoF64, mkexpr(arg32)) ) ); } else { /* sz == 8 */ IRTemp arg64 = newTemp(Ity_I64); @@ -9253,7 +9434,7 @@ DisResult disInstr_AMD64_WRK ( gregOfRexRM(pfx,modrm), 0, binop(Iop_F64toF32, mkexpr(rmode), - binop(Iop_I64toF64, mkexpr(rmode), mkexpr(arg64)) ) ); + binop(Iop_I64StoF64, mkexpr(rmode), mkexpr(arg64)) ) ); } goto decode_success; @@ -9302,10 +9483,10 @@ DisResult disInstr_AMD64_WRK ( assign( dst64, binop( Iop_32HLto64, - binop( Iop_F64toI32, + binop( Iop_F64toI32S, mkexpr(rmode), unop( Iop_F32toF64, mkexpr(f32hi) ) ), - binop( Iop_F64toI32, + binop( Iop_F64toI32S, mkexpr(rmode), unop( Iop_F32toF64, mkexpr(f32lo) ) ) ) @@ -9359,12 +9540,12 @@ DisResult disInstr_AMD64_WRK ( if (sz == 4) { putIReg32( gregOfRexRM(pfx,modrm), - binop( Iop_F64toI32, + binop( Iop_F64toI32S, mkexpr(rmode), unop(Iop_F32toF64, mkexpr(f32lo))) ); } else { putIReg64( gregOfRexRM(pfx,modrm), - binop( Iop_F64toI64, + binop( Iop_F64toI64S, mkexpr(rmode), unop(Iop_F32toF64, mkexpr(f32lo))) ); } @@ -9488,6 +9669,8 @@ DisResult disInstr_AMD64_WRK ( delta += 2+1; } else { addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 ); + if (insn[1] == 0x28/*movaps*/) + gen_SEGV_if_not_16_aligned( addr ); putXMMReg( gregOfRexRM(pfx,modrm), loadLE(Ity_V128, mkexpr(addr)) ); DIP("mov[ua]ps %s,%s\n", dis_buf, @@ -9507,6 +9690,8 @@ DisResult disInstr_AMD64_WRK ( /* fall through; awaiting test case */ } else { addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 ); + if (insn[1] == 0x29/*movaps*/) + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("mov[ua]ps %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf ); @@ -9663,6 +9848,7 @@ DisResult disInstr_AMD64_WRK ( modrm = getUChar(delta+2); if (!epartIsReg(modrm)) { addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 ); + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("movntp%s %s,%s\n", sz==2 ? "d" : "s", dis_buf, @@ -9817,7 +10003,8 @@ DisResult disInstr_AMD64_WRK ( /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and put it into the specified lane of mmx(G). */ - if (haveNo66noF2noF3(pfx) && sz == 4 + if (haveNo66noF2noF3(pfx) + && (sz == 4 || /* ignore redundant REX.W */ sz == 8) && insn[0] == 0x0F && insn[1] == 0xC4) { /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the mmx reg. t4 is the new lane value. t5 is the original @@ -10324,12 +10511,12 @@ DisResult disInstr_AMD64_WRK ( putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0, - unop(Iop_I32toF64, unop(Iop_64to32, mkexpr(arg64))) + unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64))) ); putXMMRegLane64F( gregOfRexRM(pfx,modrm), 1, - unop(Iop_I32toF64, unop(Iop_64HIto32, mkexpr(arg64))) + unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64))) ); goto decode_success; @@ -10361,7 +10548,7 @@ DisResult disInstr_AMD64_WRK ( # define CVT(_t) binop( Iop_F64toF32, \ mkexpr(rmode), \ - unop(Iop_I32toF64,mkexpr(_t))) + unop(Iop_I32StoF64,mkexpr(_t))) putXMMRegLane32F( gregOfRexRM(pfx,modrm), 3, CVT(t3) ); putXMMRegLane32F( gregOfRexRM(pfx,modrm), 2, CVT(t2) ); @@ -10415,7 +10602,7 @@ DisResult disInstr_AMD64_WRK ( assign( t1, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, mkexpr(argV))) ); -# define CVT(_t) binop( Iop_F64toI32, \ +# define CVT(_t) binop( Iop_F64toI32S, \ mkexpr(rmode), \ mkexpr(_t) ) @@ -10472,8 +10659,8 @@ DisResult disInstr_AMD64_WRK ( assign( dst64, binop( Iop_32HLto64, - binop( Iop_F64toI32, mkexpr(rmode), mkexpr(f64hi) ), - binop( Iop_F64toI32, mkexpr(rmode), mkexpr(f64lo) ) + binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64hi) ), + binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo) ) ) ); @@ -10535,8 +10722,14 @@ DisResult disInstr_AMD64_WRK ( IRTemp arg64 = newTemp(Ity_I64); modrm = getUChar(delta+2); - do_MMX_preamble(); if (epartIsReg(modrm)) { + /* Only switch to MMX mode if the source is a MMX register. + This is inconsistent with all other instructions which + convert between XMM and (M64 or MMX), which always switch + to MMX mode even if 64-bit operand is M64 and not MMX. At + least, that's what the Intel docs seem to me to say. + Fixes #210264. */ + do_MMX_preamble(); assign( arg64, getMMXReg(eregLO3ofRM(modrm)) ); delta += 2+1; DIP("cvtpi2pd %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)), @@ -10551,12 +10744,12 @@ DisResult disInstr_AMD64_WRK ( putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0, - unop(Iop_I32toF64, unop(Iop_64to32, mkexpr(arg64)) ) + unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)) ) ); putXMMRegLane64F( gregOfRexRM(pfx,modrm), 1, - unop(Iop_I32toF64, unop(Iop_64HIto32, mkexpr(arg64)) ) + unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)) ) ); goto decode_success; @@ -10599,7 +10792,7 @@ DisResult disInstr_AMD64_WRK ( /* This is less than ideal. If it turns out to be a performance bottleneck it can be improved. */ # define CVT(_t) \ - binop( Iop_F64toI32, \ + binop( Iop_F64toI32S, \ mkexpr(rmode), \ unop( Iop_F32toF64, \ unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) @@ -10690,10 +10883,10 @@ DisResult disInstr_AMD64_WRK ( if (sz == 4) { putIReg32( gregOfRexRM(pfx,modrm), - binop( Iop_F64toI32, mkexpr(rmode), mkexpr(f64lo)) ); + binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo)) ); } else { putIReg64( gregOfRexRM(pfx,modrm), - binop( Iop_F64toI64, mkexpr(rmode), mkexpr(f64lo)) ); + binop( Iop_F64toI64S, mkexpr(rmode), mkexpr(f64lo)) ); } goto decode_success; @@ -10753,7 +10946,7 @@ DisResult disInstr_AMD64_WRK ( nameXMMReg(gregOfRexRM(pfx,modrm)) ); } putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0, - unop(Iop_I32toF64, mkexpr(arg32)) + unop(Iop_I32StoF64, mkexpr(arg32)) ); } else { /* sz == 8 */ @@ -10773,7 +10966,7 @@ DisResult disInstr_AMD64_WRK ( putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0, - binop( Iop_I64toF64, + binop( Iop_I64StoF64, get_sse_roundingmode(), mkexpr(arg64) ) @@ -10884,6 +11077,8 @@ DisResult disInstr_AMD64_WRK ( delta += 2+1; } else { addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 ); + if (insn[1] == 0x28/*movapd*/ || insn[1] == 0x6F/*movdqa*/) + gen_SEGV_if_not_16_aligned( addr ); putXMMReg( gregOfRexRM(pfx,modrm), loadLE(Ity_V128, mkexpr(addr)) ); DIP("mov%s %s,%s\n", wot, dis_buf, @@ -10895,19 +11090,26 @@ DisResult disInstr_AMD64_WRK ( /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */ /* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */ - if (have66noF2noF3(pfx) && insn[0] == 0x0F + if (have66noF2noF3(pfx) && insn[0] == 0x0F && (insn[1] == 0x29 || insn[1] == 0x11)) { + HChar* wot = insn[1]==0x29 ? "apd" : "upd"; modrm = getUChar(delta+2); if (epartIsReg(modrm)) { - /* fall through; awaiting test case */ + putXMMReg( eregOfRexRM(pfx,modrm), + getXMMReg( gregOfRexRM(pfx,modrm) ) ); + DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRexRM(pfx,modrm)), + nameXMMReg(eregOfRexRM(pfx,modrm))); + delta += 2+1; } else { addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 ); + if (insn[1] == 0x29/*movapd*/) + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); - DIP("mov[ua]pd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), - dis_buf ); + DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRexRM(pfx,modrm)), + dis_buf ); delta += 2+alen; - goto decode_success; } + goto decode_success; } /* 66 0F 6E = MOVD from ireg32/m32 to xmm lo 1/4, zeroing high 3/4 of xmm. */ @@ -10992,6 +11194,7 @@ DisResult disInstr_AMD64_WRK ( nameXMMReg(eregOfRexRM(pfx,modrm))); } else { addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0 ); + gen_SEGV_if_not_16_aligned( addr ); delta += 2+alen; storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("movdqa %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf); @@ -11212,6 +11415,7 @@ DisResult disInstr_AMD64_WRK ( modrm = getUChar(delta+2); if (!epartIsReg(modrm)) { addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 ); + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) ); DIP("movntdq %s,%s\n", dis_buf, nameXMMReg(gregOfRexRM(pfx,modrm))); @@ -12611,6 +12815,7 @@ DisResult disInstr_AMD64_WRK ( delta += 2+1; } else { addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 ); + gen_SEGV_if_not_16_aligned( addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l', dis_buf, @@ -13657,196 +13862,1890 @@ DisResult disInstr_AMD64_WRK ( /* --- end of the SSSE3 decoder. --- */ /* ---------------------------------------------------- */ - /*after_sse_decoders:*/ - - /* Get the primary opcode. */ - opc = getUChar(delta); delta++; + /* ---------------------------------------------------- */ + /* --- start of the SSE4 decoder --- */ + /* ---------------------------------------------------- */ - /* We get here if the current insn isn't SSE, or this CPU doesn't - support SSE. */ + /* 66 0F 3A 0D /r ib = BLENDPD xmm1, xmm2/m128, imm8 + Blend Packed Double Precision Floating-Point Values (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0D ) { - switch (opc) { + Int imm8; + UShort imm8_mask_16; - /* ------------------------ Control flow --------------- */ + IRTemp dst_vec = newTemp(Ity_V128); + IRTemp src_vec = newTemp(Ity_V128); + IRTemp imm8_mask = newTemp(Ity_V128); - case 0xC2: /* RET imm16 */ - if (have66orF2orF3(pfx)) goto decode_failure; - d64 = getUDisp16(delta); - delta += 2; - dis_ret(vbi, d64); - dres.whatNext = Dis_StopHere; - DIP("ret %lld\n", d64); - break; + modrm = insn[3]; + assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) ); - case 0xC3: /* RET */ - if (have66orF2(pfx)) goto decode_failure; - /* F3 is acceptable on AMD. */ - dis_ret(vbi, 0); - dres.whatNext = Dis_StopHere; - DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n"); - break; - - case 0xE8: /* CALL J4 */ - if (haveF2orF3(pfx)) goto decode_failure; - d64 = getSDisp32(delta); delta += 4; - d64 += (guest_RIP_bbstart+delta); - /* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */ - t1 = newTemp(Ity_I64); - assign(t1, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8))); - putIReg64(R_RSP, mkexpr(t1)); - storeLE( mkexpr(t1), mkU64(guest_RIP_bbstart+delta)); - t2 = newTemp(Ity_I64); - assign(t2, mkU64((Addr64)d64)); - make_redzone_AbiHint(vbi, t1, t2/*nia*/, "call-d32"); - if (resteerOkFn( callback_opaque, (Addr64)d64) ) { - /* follow into the call target. */ - dres.whatNext = Dis_Resteer; - dres.continueAt = d64; + if ( epartIsReg( modrm ) ) { + imm8 = (Int)insn[4]; + assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1+1; + DIP( "blendpd $%d, %s,%s\n", imm8, + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); } else { - jmp_lit(Ijk_Call,d64); - dres.whatNext = Dis_StopHere; + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, + 1/* imm8 is 1 byte after the amode */ ); + gen_SEGV_if_not_16_aligned( addr ); + assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); + imm8 = (Int)insn[2+alen+1]; + delta += 3+alen+1; + DIP( "blendpd $%d, %s,%s\n", + imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); } - DIP("call 0x%llx\n",d64); - break; -//.. //-- case 0xC8: /* ENTER */ -//.. //-- d32 = getUDisp16(eip); eip += 2; -//.. //-- abyte = getUChar(delta); delta++; -//.. //-- -//.. //-- vg_assert(sz == 4); -//.. //-- vg_assert(abyte == 0); -//.. //-- -//.. //-- t1 = newTemp(cb); t2 = newTemp(cb); -//.. //-- uInstr2(cb, GET, sz, ArchReg, R_EBP, TempReg, t1); -//.. //-- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2); -//.. //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2); -//.. //-- uLiteral(cb, sz); -//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP); -//.. //-- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2); -//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBP); -//.. //-- if (d32) { -//.. //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2); -//.. //-- uLiteral(cb, d32); -//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP); -//.. //-- } -//.. //-- DIP("enter 0x%x, 0x%x", d32, abyte); -//.. //-- break; + switch( imm8 & 3 ) { + case 0: imm8_mask_16 = 0x0000; break; + case 1: imm8_mask_16 = 0x00FF; break; + case 2: imm8_mask_16 = 0xFF00; break; + case 3: imm8_mask_16 = 0xFFFF; break; + default: vassert(0); break; + } + assign( imm8_mask, mkV128( imm8_mask_16 ) ); - case 0xC9: /* LEAVE */ - /* In 64-bit mode this defaults to a 64-bit operand size. There - is no way to encode a 32-bit variant. Hence sz==4 but we do - it as if sz=8. */ - if (sz != 4) - goto decode_failure; - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, getIReg64(R_RBP)); - /* First PUT RSP looks redundant, but need it because RSP must - always be up-to-date for Memcheck to work... */ - putIReg64(R_RSP, mkexpr(t1)); - assign(t2, loadLE(Ity_I64,mkexpr(t1))); - putIReg64(R_RBP, mkexpr(t2)); - putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t1), mkU64(8)) ); - DIP("leave\n"); - break; + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_OrV128, + binop( Iop_AndV128, mkexpr(src_vec), mkexpr(imm8_mask) ), + binop( Iop_AndV128, mkexpr(dst_vec), + unop( Iop_NotV128, mkexpr(imm8_mask) ) ) ) ); -//.. //-- /* ---------------- Misc weird-ass insns --------------- */ -//.. //-- -//.. //-- case 0x27: /* DAA */ -//.. //-- case 0x2F: /* DAS */ -//.. //-- t1 = newTemp(cb); -//.. //-- uInstr2(cb, GET, 1, ArchReg, R_AL, TempReg, t1); -//.. //-- /* Widen %AL to 32 bits, so it's all defined when we push it. */ -//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1); -//.. //-- uWiden(cb, 1, False); -//.. //-- uInstr0(cb, CALLM_S, 0); -//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1); -//.. //-- uInstr1(cb, CALLM, 0, Lit16, -//.. //-- opc == 0x27 ? VGOFF_(helper_DAA) : VGOFF_(helper_DAS) ); -//.. //-- uFlagsRWU(cb, FlagsAC, FlagsSZACP, FlagO); -//.. //-- uInstr1(cb, POP, 4, TempReg, t1); -//.. //-- uInstr0(cb, CALLM_E, 0); -//.. //-- uInstr2(cb, PUT, 1, TempReg, t1, ArchReg, R_AL); -//.. //-- DIP(opc == 0x27 ? "daa\n" : "das\n"); -//.. //-- break; -//.. //-- -//.. //-- case 0x37: /* AAA */ -//.. //-- case 0x3F: /* AAS */ -//.. //-- t1 = newTemp(cb); -//.. //-- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1); -//.. //-- /* Widen %AL to 32 bits, so it's all defined when we push it. */ -//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1); -//.. //-- uWiden(cb, 2, False); -//.. //-- uInstr0(cb, CALLM_S, 0); -//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1); -//.. //-- uInstr1(cb, CALLM, 0, Lit16, -//.. //-- opc == 0x37 ? VGOFF_(helper_AAA) : VGOFF_(helper_AAS) ); -//.. //-- uFlagsRWU(cb, FlagA, FlagsAC, FlagsEmpty); -//.. //-- uInstr1(cb, POP, 4, TempReg, t1); -//.. //-- uInstr0(cb, CALLM_E, 0); -//.. //-- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX); -//.. //-- DIP(opc == 0x37 ? "aaa\n" : "aas\n"); -//.. //-- break; -//.. //-- -//.. //-- case 0xD4: /* AAM */ -//.. //-- case 0xD5: /* AAD */ -//.. //-- d32 = getUChar(delta); delta++; -//.. //-- if (d32 != 10) VG_(core_panic)("disInstr: AAM/AAD but base not 10 !"); -//.. //-- t1 = newTemp(cb); -//.. //-- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1); -//.. //-- /* Widen %AX to 32 bits, so it's all defined when we push it. */ -//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1); -//.. //-- uWiden(cb, 2, False); -//.. //-- uInstr0(cb, CALLM_S, 0); -//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1); -//.. //-- uInstr1(cb, CALLM, 0, Lit16, -//.. //-- opc == 0xD4 ? VGOFF_(helper_AAM) : VGOFF_(helper_AAD) ); -//.. //-- uFlagsRWU(cb, FlagsEmpty, FlagsSZP, FlagsEmpty); -//.. //-- uInstr1(cb, POP, 4, TempReg, t1); -//.. //-- uInstr0(cb, CALLM_E, 0); -//.. //-- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX); -//.. //-- DIP(opc == 0xD4 ? "aam\n" : "aad\n"); -//.. //-- break; + goto decode_success; + } - /* ------------------------ CWD/CDQ -------------------- */ - case 0x98: /* CBW */ - if (haveF2orF3(pfx)) goto decode_failure; - if (sz == 8) { - putIRegRAX( 8, unop(Iop_32Sto64, getIRegRAX(4)) ); - DIP(/*"cdqe\n"*/"cltq"); - break; - } - if (sz == 4) { - putIRegRAX( 4, unop(Iop_16Sto32, getIRegRAX(2)) ); - DIP("cwtl\n"); - break; - } - if (sz == 2) { - putIRegRAX( 2, unop(Iop_8Sto16, getIRegRAX(1)) ); - DIP("cbw\n"); - break; - } - goto decode_failure; + /* 66 0F 3A 0C /r ib = BLENDPS xmm1, xmm2/m128, imm8 + Blend Packed Single Precision Floating-Point Values (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0C ) { - case 0x99: /* CWD/CDQ/CQO */ - if (haveF2orF3(pfx)) goto decode_failure; - vassert(sz == 2 || sz == 4 || sz == 8); - ty = szToITy(sz); - putIRegRDX( sz, - binop(mkSizedOp(ty,Iop_Sar8), - getIRegRAX(sz), - mkU8(sz == 2 ? 15 : (sz == 4 ? 31 : 63))) ); - DIP(sz == 2 ? "cwd\n" - : (sz == 4 ? /*"cdq\n"*/ "cltd\n" - : "cqo\n")); - break; + Int imm8; + IRTemp dst_vec = newTemp(Ity_V128); + IRTemp src_vec = newTemp(Ity_V128); - /* ------------------------ FPU ops -------------------- */ + modrm = insn[3]; - case 0x9E: /* SAHF */ - codegen_SAHF(); - DIP("sahf\n"); + assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) ); + + if ( epartIsReg( modrm ) ) { + imm8 = (Int)insn[3+1]; + assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1+1; + DIP( "blendps $%d, %s,%s\n", imm8, + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, + 1/* imm8 is 1 byte after the amode */ ); + gen_SEGV_if_not_16_aligned( addr ); + assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); + imm8 = (Int)insn[3+alen]; + delta += 3+alen+1; + DIP( "blendpd $%d, %s,%s\n", + imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + UShort imm8_perms[16] = { 0x0000, 0x000F, 0x00F0, 0x00FF, 0x0F00, 0x0F0F, + 0x0FF0, 0x0FFF, 0xF000, 0xF00F, 0xF0F0, 0xF0FF, + 0xFF00, 0xFF0F, 0xFFF0, 0xFFFF }; + IRTemp imm8_mask = newTemp(Ity_V128); + assign( imm8_mask, mkV128( imm8_perms[ (imm8 & 15) ] ) ); + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_OrV128, + binop( Iop_AndV128, mkexpr(src_vec), mkexpr(imm8_mask) ), + binop( Iop_AndV128, mkexpr(dst_vec), + unop( Iop_NotV128, mkexpr(imm8_mask) ) ) ) ); + + goto decode_success; + } + + + /* 66 0F 3A 44 /r ib = PCLMULQDQ xmm1, xmm2/m128, imm8 + * Carry-less multiplication of selected XMM quadwords into XMM + * registers (a.k.a multiplication of polynomials over GF(2)) + */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x44 ) { + + Int imm8; + IRTemp svec = newTemp(Ity_V128); + IRTemp dvec = newTemp(Ity_V128); + + modrm = insn[3]; + + assign( dvec, getXMMReg( gregOfRexRM(pfx, modrm) ) ); + + if ( epartIsReg( modrm ) ) { + imm8 = (Int)insn[4]; + assign( svec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1+1; + DIP( "pclmulqdq $%d, %s,%s\n", imm8, + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, + 1/* imm8 is 1 byte after the amode */ ); + gen_SEGV_if_not_16_aligned( addr ); + assign( svec, loadLE( Ity_V128, mkexpr(addr) ) ); + imm8 = (Int)insn[2+alen+1]; + delta += 3+alen+1; + DIP( "pclmulqdq $%d, %s,%s\n", + imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + t0 = newTemp(Ity_I64); + t1 = newTemp(Ity_I64); + assign(t0, unop((imm8&1)? Iop_V128HIto64 : Iop_V128to64, mkexpr(dvec))); + assign(t1, unop((imm8&16) ? Iop_V128HIto64 : Iop_V128to64, mkexpr(svec))); + + t2 = newTemp(Ity_I64); + t3 = newTemp(Ity_I64); + + IRExpr** args; + + args = mkIRExprVec_3(mkexpr(t0), mkexpr(t1), mkU64(0)); + assign(t2, + mkIRExprCCall(Ity_I64,0, "amd64g_calculate_pclmul", + &amd64g_calculate_pclmul, args)); + args = mkIRExprVec_3(mkexpr(t0), mkexpr(t1), mkU64(1)); + assign(t3, + mkIRExprCCall(Ity_I64,0, "amd64g_calculate_pclmul", + &amd64g_calculate_pclmul, args)); + + IRTemp res = newTemp(Ity_V128); + assign(res, binop(Iop_64HLtoV128, mkexpr(t3), mkexpr(t2))); + putXMMReg( gregOfRexRM(pfx,modrm), mkexpr(res) ); + + goto decode_success; + } + + /* 66 0F 3A 41 /r ib = DPPD xmm1, xmm2/m128, imm8 + Dot Product of Packed Double Precision Floating-Point Values (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x41 ) { + + Int imm8; + IRTemp src_vec = newTemp(Ity_V128); + IRTemp dst_vec = newTemp(Ity_V128); + IRTemp and_vec = newTemp(Ity_V128); + IRTemp sum_vec = newTemp(Ity_V128); + + modrm = insn[3]; + + assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) ); + + if ( epartIsReg( modrm ) ) { + imm8 = (Int)insn[4]; + assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1+1; + DIP( "dppd $%d, %s,%s\n", imm8, + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, + 1/* imm8 is 1 byte after the amode */ ); + gen_SEGV_if_not_16_aligned( addr ); + assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) ); + imm8 = (Int)insn[2+alen+1]; + delta += 3+alen+1; + DIP( "dppd $%d, %s,%s\n", + imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + UShort imm8_perms[4] = { 0x0000, 0x00FF, 0xFF00, 0xFFFF }; + + assign( and_vec, binop( Iop_AndV128, + binop( Iop_Mul64Fx2, + mkexpr(dst_vec), mkexpr(src_vec) ), + mkV128( imm8_perms[ ((imm8 >> 4) & 3) ] ) ) ); + + assign( sum_vec, binop( Iop_Add64F0x2, + binop( Iop_InterleaveHI64x2, + mkexpr(and_vec), mkexpr(and_vec) ), + binop( Iop_InterleaveLO64x2, + mkexpr(and_vec), mkexpr(and_vec) ) ) ); + + putXMMReg( gregOfRexRM( pfx, modrm ), + binop( Iop_AndV128, + binop( Iop_InterleaveLO64x2, + mkexpr(sum_vec), mkexpr(sum_vec) ), + mkV128( imm8_perms[ (imm8 & 3) ] ) ) ); + + goto decode_success; + } + + + /* 66 0F 3A 40 /r ib = DPPS xmm1, xmm2/m128, imm8 + Dot Product of Packed Single Precision Floating-Point Values (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F + && insn[1] == 0x3A + && insn[2] == 0x40 ) { + + Int imm8; + IRTemp xmm1_vec = newTemp(Ity_V128); + IRTemp xmm2_vec = newTemp(Ity_V128); + IRTemp tmp_prod_vec = newTemp(Ity_V128); + IRTemp prod_vec = newTemp(Ity_V128); + IRTemp sum_vec = newTemp(Ity_V128); + IRTemp v3, v2, v1, v0; + v3 = v2 = v1 = v0 = IRTemp_INVALID; + + modrm = insn[3]; + + assign( xmm1_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) ); + + if ( epartIsReg( modrm ) ) { + imm8 = (Int)insn[4]; + assign( xmm2_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1+1; + DIP( "dpps $%d, %s,%s\n", imm8, + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, + 1/* imm8 is 1 byte after the amode */ ); + gen_SEGV_if_not_16_aligned( addr ); + assign( xmm2_vec, loadLE( Ity_V128, mkexpr(addr) ) ); + imm8 = (Int)insn[2+alen+1]; + delta += 3+alen+1; + DIP( "dpps $%d, %s,%s\n", + imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + UShort imm8_perms[16] = { 0x0000, 0x000F, 0x00F0, 0x00FF, 0x0F00, + 0x0F0F, 0x0FF0, 0x0FFF, 0xF000, 0xF00F, + 0xF0F0, 0xF0FF, 0xFF00, 0xFF0F, 0xFFF0, 0xFFFF }; + + assign( tmp_prod_vec, + binop( Iop_AndV128, + binop( Iop_Mul32Fx4, mkexpr(xmm1_vec), mkexpr(xmm2_vec) ), + mkV128( imm8_perms[((imm8 >> 4)& 15)] ) ) ); + breakup128to32s( tmp_prod_vec, &v3, &v2, &v1, &v0 ); + assign( prod_vec, mk128from32s( v3, v1, v2, v0 ) ); + + assign( sum_vec, binop( Iop_Add32Fx4, + binop( Iop_InterleaveHI32x4, + mkexpr(prod_vec), mkexpr(prod_vec) ), + binop( Iop_InterleaveLO32x4, + mkexpr(prod_vec), mkexpr(prod_vec) ) ) ); + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_AndV128, + binop( Iop_Add32Fx4, + binop( Iop_InterleaveHI32x4, + mkexpr(sum_vec), mkexpr(sum_vec) ), + binop( Iop_InterleaveLO32x4, + mkexpr(sum_vec), mkexpr(sum_vec) ) ), + mkV128( imm8_perms[ (imm8 & 15) ] ) ) ); + + goto decode_success; + } + + + /* 66 0F 3A 21 /r ib = INSERTPS xmm1, xmm2/m32, imm8 + Insert Packed Single Precision Floating-Point Value (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x21 ) { + + Int imm8; + Int imm8_count_s; + Int imm8_count_d; + Int imm8_zmask; + IRTemp dstVec = newTemp(Ity_V128); + IRTemp srcDWord = newTemp(Ity_I32); + + modrm = insn[3]; + + assign( dstVec, getXMMReg( gregOfRexRM(pfx, modrm) ) ); + + if ( epartIsReg( modrm ) ) { + IRTemp src_vec = newTemp(Ity_V128); + assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + + IRTemp src_lane_0 = IRTemp_INVALID; + IRTemp src_lane_1 = IRTemp_INVALID; + IRTemp src_lane_2 = IRTemp_INVALID; + IRTemp src_lane_3 = IRTemp_INVALID; + breakup128to32s( src_vec, + &src_lane_3, &src_lane_2, &src_lane_1, &src_lane_0 ); + + imm8 = (Int)insn[4]; + imm8_count_s = ((imm8 >> 6) & 3); + switch( imm8_count_s ) { + case 0: assign( srcDWord, mkexpr(src_lane_0) ); break; + case 1: assign( srcDWord, mkexpr(src_lane_1) ); break; + case 2: assign( srcDWord, mkexpr(src_lane_2) ); break; + case 3: assign( srcDWord, mkexpr(src_lane_3) ); break; + default: vassert(0); break; + } + + delta += 3+1+1; + DIP( "insertps $%d, %s,%s\n", imm8, + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, + 1/* const imm8 is 1 byte after the amode */ ); + assign( srcDWord, loadLE( Ity_I32, mkexpr(addr) ) ); + imm8 = (Int)insn[2+alen+1]; + imm8_count_s = 0; + delta += 3+alen+1; + DIP( "insertps $%d, %s,%s\n", + imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + IRTemp dst_lane_0 = IRTemp_INVALID; + IRTemp dst_lane_1 = IRTemp_INVALID; + IRTemp dst_lane_2 = IRTemp_INVALID; + IRTemp dst_lane_3 = IRTemp_INVALID; + breakup128to32s( dstVec, + &dst_lane_3, &dst_lane_2, &dst_lane_1, &dst_lane_0 ); + + imm8_count_d = ((imm8 >> 4) & 3); + switch( imm8_count_d ) { + case 0: dst_lane_0 = srcDWord; break; + case 1: dst_lane_1 = srcDWord; break; + case 2: dst_lane_2 = srcDWord; break; + case 3: dst_lane_3 = srcDWord; break; + default: vassert(0); break; + } + + imm8_zmask = (imm8 & 15); + IRTemp zero_32 = newTemp(Ity_I32); + assign( zero_32, mkU32(0) ); + + IRExpr* ire_vec_128 = mk128from32s( + ((imm8_zmask & 8) == 8) ? zero_32 : dst_lane_3, + ((imm8_zmask & 4) == 4) ? zero_32 : dst_lane_2, + ((imm8_zmask & 2) == 2) ? zero_32 : dst_lane_1, + ((imm8_zmask & 1) == 1) ? zero_32 : dst_lane_0 ); + + putXMMReg( gregOfRexRM(pfx, modrm), ire_vec_128 ); + + goto decode_success; + } + + + /* 66 0F 3A 14 /r ib = PEXTRB r/m16, xmm, imm8 + Extract Byte from xmm, store in mem or zero-extend + store in gen.reg. (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x14 ) { + + Int imm8; + IRTemp xmm_vec = newTemp(Ity_V128); + IRTemp sel_lane = newTemp(Ity_I32); + IRTemp shr_lane = newTemp(Ity_I32); + + modrm = insn[3]; + assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) ); + breakup128to32s( xmm_vec, &t3, &t2, &t1, &t0 ); + + if ( epartIsReg( modrm ) ) { + imm8 = (Int)insn[3+1]; + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 ); + imm8 = (Int)insn[3+alen]; + } + switch( (imm8 >> 2) & 3 ) { + case 0: assign( sel_lane, mkexpr(t0) ); break; + case 1: assign( sel_lane, mkexpr(t1) ); break; + case 2: assign( sel_lane, mkexpr(t2) ); break; + case 3: assign( sel_lane, mkexpr(t3) ); break; + default: vassert(0); + } + assign( shr_lane, + binop( Iop_Shr32, mkexpr(sel_lane), mkU8(((imm8 & 3)*8)) ) ); + + if ( epartIsReg( modrm ) ) { + putIReg64( eregOfRexRM(pfx,modrm), + unop( Iop_32Uto64, + binop(Iop_And32, mkexpr(shr_lane), mkU32(255)) ) ); + + delta += 3+1+1; + DIP( "pextrb $%d, %s,%s\n", imm8, + nameXMMReg( gregOfRexRM(pfx, modrm) ), + nameIReg64( eregOfRexRM(pfx, modrm) ) ); + } else { + storeLE( mkexpr(addr), unop(Iop_32to8, mkexpr(shr_lane) ) ); + delta += 3+alen+1; + DIP( "$%d, pextrb %s,%s\n", + imm8, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf ); + } + + goto decode_success; + } + + + /* 66 0F 3A 16 /r ib = PEXTRD reg/mem32, xmm2, imm8 + Extract Doubleword int from xmm reg and store in gen.reg or mem. (XMM) + Note that this insn has the same opcodes as PEXTRQ, but + here the REX.W bit is _not_ present */ + if ( have66noF2noF3( pfx ) + && sz == 2 /* REX.W is _not_ present */ + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x16 ) { + + Int imm8_10; + IRTemp xmm_vec = newTemp(Ity_V128); + IRTemp src_dword = newTemp(Ity_I32); + + modrm = insn[3]; + assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) ); + breakup128to32s( xmm_vec, &t3, &t2, &t1, &t0 ); + + if ( epartIsReg( modrm ) ) { + imm8_10 = (Int)(insn[3+1] & 3); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 ); + imm8_10 = (Int)(insn[3+alen] & 3); + } + + switch ( imm8_10 ) { + case 0: assign( src_dword, mkexpr(t0) ); break; + case 1: assign( src_dword, mkexpr(t1) ); break; + case 2: assign( src_dword, mkexpr(t2) ); break; + case 3: assign( src_dword, mkexpr(t3) ); break; + default: vassert(0); + } + + if ( epartIsReg( modrm ) ) { + putIReg32( eregOfRexRM(pfx,modrm), mkexpr(src_dword) ); + delta += 3+1+1; + DIP( "pextrd $%d, %s,%s\n", imm8_10, + nameXMMReg( gregOfRexRM(pfx, modrm) ), + nameIReg32( eregOfRexRM(pfx, modrm) ) ); + } else { + storeLE( mkexpr(addr), mkexpr(src_dword) ); + delta += 3+alen+1; + DIP( "pextrd $%d, %s,%s\n", + imm8_10, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf ); + } + + goto decode_success; + } + + + /* 66 REX.W 0F 3A 16 /r ib = PEXTRQ reg/mem64, xmm2, imm8 + Extract Quadword int from xmm reg and store in gen.reg or mem. (XMM) + Note that this insn has the same opcodes as PEXTRD, but + here the REX.W bit is present */ + if ( have66noF2noF3( pfx ) + && sz == 8 /* REX.W is present */ + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x16 ) { + + Int imm8_0; + IRTemp xmm_vec = newTemp(Ity_V128); + IRTemp src_qword = newTemp(Ity_I64); + + modrm = insn[3]; + assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) ); + + if ( epartIsReg( modrm ) ) { + imm8_0 = (Int)(insn[3+1] & 1); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 ); + imm8_0 = (Int)(insn[3+alen] & 1); + } + switch ( imm8_0 ) { + case 0: assign( src_qword, unop(Iop_V128to64, mkexpr(xmm_vec)) ); break; + case 1: assign( src_qword, unop(Iop_V128HIto64, mkexpr(xmm_vec)) ); break; + default: vassert(0); + } + + if ( epartIsReg( modrm ) ) { + putIReg64( eregOfRexRM(pfx,modrm), mkexpr(src_qword) ); + delta += 3+1+1; + DIP( "pextrq $%d, %s,%s\n", imm8_0, + nameXMMReg( gregOfRexRM(pfx, modrm) ), + nameIReg64( eregOfRexRM(pfx, modrm) ) ); + } else { + storeLE( mkexpr(addr), mkexpr(src_qword) ); + delta += 3+alen+1; + DIP( "pextrq $%d, %s,%s\n", + imm8_0, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf ); + } + + goto decode_success; + } + + + /* 66 0F 3A 15 /r ib = PEXTRW r/m16, xmm, imm8 + Extract Word from xmm, store in mem or zero-extend + store in gen.reg. (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x15 ) { + + Int imm8_20; + IRTemp xmm_vec = newTemp(Ity_V128); + IRTemp src_word = newTemp(Ity_I16); + + modrm = insn[3]; + assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) ); + breakup128to32s( xmm_vec, &t3, &t2, &t1, &t0 ); + + if ( epartIsReg( modrm ) ) { + imm8_20 = (Int)(insn[3+1] & 7); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 ); + imm8_20 = (Int)(insn[3+alen] & 7); + } + + switch ( imm8_20 ) { + case 0: assign( src_word, unop(Iop_32to16, mkexpr(t0)) ); break; + case 1: assign( src_word, unop(Iop_32HIto16, mkexpr(t0)) ); break; + case 2: assign( src_word, unop(Iop_32to16, mkexpr(t1)) ); break; + case 3: assign( src_word, unop(Iop_32HIto16, mkexpr(t1)) ); break; + case 4: assign( src_word, unop(Iop_32to16, mkexpr(t2)) ); break; + case 5: assign( src_word, unop(Iop_32HIto16, mkexpr(t2)) ); break; + case 6: assign( src_word, unop(Iop_32to16, mkexpr(t3)) ); break; + case 7: assign( src_word, unop(Iop_32HIto16, mkexpr(t3)) ); break; + default: vassert(0); + } + + if ( epartIsReg( modrm ) ) { + putIReg64( eregOfRexRM(pfx,modrm), unop(Iop_16Uto64, mkexpr(src_word)) ); + delta += 3+1+1; + DIP( "pextrw $%d, %s,%s\n", imm8_20, + nameXMMReg( gregOfRexRM(pfx, modrm) ), + nameIReg64( eregOfRexRM(pfx, modrm) ) ); + } else { + storeLE( mkexpr(addr), mkexpr(src_word) ); + delta += 3+alen+1; + DIP( "pextrw $%d, %s,%s\n", + imm8_20, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf ); + } + + goto decode_success; + } + + + /* 66 REX.W 0F 3A 22 /r ib = PINSRQ xmm1, r/m64, imm8 + Extract Quadword int from gen.reg/mem64 and insert into xmm1 */ + if ( have66noF2noF3( pfx ) + && sz == 8 /* REX.W is present */ + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x22 ) { + + Int imm8_0; + IRTemp src_elems = newTemp(Ity_I64); + IRTemp src_vec = newTemp(Ity_V128); + + modrm = insn[3]; + + if ( epartIsReg( modrm ) ) { + imm8_0 = (Int)(insn[3+1] & 1); + assign( src_elems, getIReg64( eregOfRexRM(pfx,modrm) ) ); + delta += 3+1+1; + DIP( "pinsrq $%d, %s,%s\n", imm8_0, + nameIReg64( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 ); + imm8_0 = (Int)(insn[3+alen] & 1); + assign( src_elems, loadLE( Ity_I64, mkexpr(addr) ) ); + delta += 3+alen+1; + DIP( "pinsrq $%d, %s,%s\n", + imm8_0, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + UShort mask = 0; + if ( imm8_0 == 0 ) { + mask = 0xFF00; + assign( src_vec, binop( Iop_64HLtoV128, mkU64(0), mkexpr(src_elems) ) ); + } else { + mask = 0x00FF; + assign( src_vec, binop( Iop_64HLtoV128, mkexpr(src_elems), mkU64(0) ) ); + } + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_OrV128, mkexpr(src_vec), + binop( Iop_AndV128, + getXMMReg( gregOfRexRM(pfx, modrm) ), + mkV128(mask) ) ) ); + + goto decode_success; + } + + + /* 66 no-REX.W 0F 3A 22 /r ib = PINSRD xmm1, r/m32, imm8 + Extract Doubleword int from gen.reg/mem32 and insert into xmm1 */ + if ( have66noF2noF3( pfx ) + && sz == 2 /* REX.W is NOT present */ + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x22 ) { + + Int imm8_10; + IRTemp src_elems = newTemp(Ity_I32); + IRTemp src_vec = newTemp(Ity_V128); + IRTemp z32 = newTemp(Ity_I32); + + modrm = insn[3]; + + if ( epartIsReg( modrm ) ) { + imm8_10 = (Int)(insn[3+1] & 3); + assign( src_elems, getIReg32( eregOfRexRM(pfx,modrm) ) ); + delta += 3+1+1; + DIP( "pinsrd $%d, %s,%s\n", imm8_10, + nameIReg32( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 ); + imm8_10 = (Int)(insn[3+alen] & 3); + assign( src_elems, loadLE( Ity_I32, mkexpr(addr) ) ); + delta += 3+alen+1; + DIP( "pinsrd $%d, %s,%s\n", + imm8_10, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + assign(z32, mkU32(0)); + + UShort mask = 0; + switch (imm8_10) { + case 3: mask = 0x0FFF; + assign(src_vec, mk128from32s(src_elems, z32, z32, z32)); + break; + case 2: mask = 0xF0FF; + assign(src_vec, mk128from32s(z32, src_elems, z32, z32)); + break; + case 1: mask = 0xFF0F; + assign(src_vec, mk128from32s(z32, z32, src_elems, z32)); + break; + case 0: mask = 0xFFF0; + assign(src_vec, mk128from32s(z32, z32, z32, src_elems)); + break; + default: vassert(0); + } + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_OrV128, mkexpr(src_vec), + binop( Iop_AndV128, + getXMMReg( gregOfRexRM(pfx, modrm) ), + mkV128(mask) ) ) ); + + goto decode_success; + } + + /* 66 0F 3A 20 /r ib = PINSRB xmm1, r32/m8, imm8 + Extract byte from r32/m8 and insert into xmm1 */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x20 ) { + + Int imm8; + IRTemp new8 = newTemp(Ity_I64); + + modrm = insn[3]; + + if ( epartIsReg( modrm ) ) { + imm8 = (Int)(insn[3+1] & 0xF); + assign( new8, binop(Iop_And64, + unop(Iop_32Uto64, + getIReg32(eregOfRexRM(pfx,modrm))), + mkU64(0xFF))); + delta += 3+1+1; + DIP( "pinsrb $%d,%s,%s\n", imm8, + nameIReg32( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 ); + imm8 = (Int)(insn[3+alen] & 0xF); + assign( new8, unop(Iop_8Uto64, loadLE( Ity_I8, mkexpr(addr) ))); + delta += 3+alen+1; + DIP( "pinsrb $%d,%s,%s\n", + imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + // Create a V128 value which has the selected byte in the + // specified lane, and zeroes everywhere else. + IRTemp tmp128 = newTemp(Ity_V128); + IRTemp halfshift = newTemp(Ity_I64); + assign(halfshift, binop(Iop_Shl64, + mkexpr(new8), mkU8(8 * (imm8 & 7)))); + vassert(imm8 >= 0 && imm8 <= 15); + if (imm8 < 8) { + assign(tmp128, binop(Iop_64HLtoV128, mkU64(0), mkexpr(halfshift))); + } else { + assign(tmp128, binop(Iop_64HLtoV128, mkexpr(halfshift), mkU64(0))); + } + + UShort mask = ~(1 << imm8); + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_OrV128, + mkexpr(tmp128), + binop( Iop_AndV128, + getXMMReg( gregOfRexRM(pfx, modrm) ), + mkV128(mask) ) ) ); + + goto decode_success; + } + + /* 66 0F 38 37 = PCMPGTQ + 64x2 comparison (signed, presumably; the Intel docs don't say :-) + */ + if ( have66noF2noF3( pfx ) && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x37) { + /* FIXME: this needs an alignment check */ + delta = dis_SSEint_E_to_G( vbi, pfx, delta+3, + "pcmpgtq", Iop_CmpGT64Sx2, False ); + goto decode_success; + } + + /* 66 0F 38 3D /r = PMAXSD xmm1, xmm2/m128 + Maximum of Packed Signed Double Word Integers (XMM) + 66 0F 38 39 /r = PMINSD xmm1, xmm2/m128 + Minimum of Packed Signed Double Word Integers (XMM) */ + if ( have66noF2noF3( pfx ) && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 + && (insn[2] == 0x3D || insn[2] == 0x39)) { + /* FIXME: this needs an alignment check */ + Bool isMAX = insn[2] == 0x3D; + delta = dis_SSEint_E_to_G( + vbi, pfx, delta+3, + isMAX ? "pmaxsd" : "pminsd", + isMAX ? Iop_Max32Sx4 : Iop_Min32Sx4, + False + ); + goto decode_success; + } + + /* 66 0F 38 3F /r = PMAXUD xmm1, xmm2/m128 + Maximum of Packed Unsigned Doubleword Integers (XMM) + 66 0F 38 3B /r = PMINUD xmm1, xmm2/m128 + Minimum of Packed Unsigned Doubleword Integers (XMM) */ + if ( have66noF2noF3( pfx ) && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 + && (insn[2] == 0x3F || insn[2] == 0x3B)) { + /* FIXME: this needs an alignment check */ + Bool isMAX = insn[2] == 0x3F; + delta = dis_SSEint_E_to_G( + vbi, pfx, delta+3, + isMAX ? "pmaxud" : "pminud", + isMAX ? Iop_Max32Ux4 : Iop_Min32Ux4, + False + ); + goto decode_success; + } + + /* 66 0F 38 3E /r = PMAXUW xmm1, xmm2/m128 + Maximum of Packed Unsigned Word Integers (XMM) + 66 0F 38 3A /r = PMINUW xmm1, xmm2/m128 + Minimum of Packed Unsigned Word Integers (XMM) + */ + if ( have66noF2noF3( pfx ) && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 + && (insn[2] == 0x3E || insn[2] == 0x3A)) { + /* FIXME: this needs an alignment check */ + Bool isMAX = insn[2] == 0x3E; + delta = dis_SSEint_E_to_G( + vbi, pfx, delta+3, + isMAX ? "pmaxuw" : "pminuw", + isMAX ? Iop_Max16Ux8 : Iop_Min16Ux8, + False + ); + goto decode_success; + } + + /* 66 0F 38 3C /r = PMAXSB xmm1, xmm2/m128 + 8Sx16 (signed) max + 66 0F 38 38 /r = PMINSB xmm1, xmm2/m128 + 8Sx16 (signed) min + */ + if ( have66noF2noF3( pfx ) && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 + && (insn[2] == 0x3C || insn[2] == 0x38)) { + /* FIXME: this needs an alignment check */ + Bool isMAX = insn[2] == 0x3C; + delta = dis_SSEint_E_to_G( + vbi, pfx, delta+3, + isMAX ? "pmaxsb" : "pminsb", + isMAX ? Iop_Max8Sx16 : Iop_Min8Sx16, + False + ); + goto decode_success; + } + + /* 66 0f 38 20 /r = PMOVSXBW xmm1, xmm2/m64 + Packed Move with Sign Extend from Byte to Word (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x20 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg( modrm ) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovsxbw %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) ); + delta += 3+alen; + DIP( "pmovsxbw %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_SarN16x8, + binop( Iop_ShlN16x8, + binop( Iop_InterleaveLO8x16, + IRExpr_Const( IRConst_V128(0) ), + mkexpr(srcVec) ), + mkU8(8) ), + mkU8(8) ) ); + + goto decode_success; + } + + + /* 66 0f 38 21 /r = PMOVSXBD xmm1, xmm2/m32 + Packed Move with Sign Extend from Byte to DWord (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x21 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg( modrm ) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovsxbd %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) ) ) ); + delta += 3+alen; + DIP( "pmovsxbd %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + IRTemp zeroVec = newTemp(Ity_V128); + assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) ); + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_SarN32x4, + binop( Iop_ShlN32x4, + binop( Iop_InterleaveLO8x16, + mkexpr(zeroVec), + binop( Iop_InterleaveLO8x16, + mkexpr(zeroVec), + mkexpr(srcVec) ) ), + mkU8(24) ), mkU8(24) ) ); + + goto decode_success; + } + + + /* 66 0f 38 22 /r = PMOVSXBQ xmm1, xmm2/m16 + Packed Move with Sign Extend from Byte to QWord (XMM) */ + if ( have66noF2noF3(pfx) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x22 ) { + + modrm = insn[3]; + + IRTemp srcBytes = newTemp(Ity_I16); + + if ( epartIsReg(modrm) ) { + assign( srcBytes, getXMMRegLane16( eregOfRexRM(pfx, modrm), 0 ) ); + delta += 3+1; + DIP( "pmovsxbq %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcBytes, loadLE( Ity_I16, mkexpr(addr) ) ); + delta += 3+alen; + DIP( "pmovsxbq %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + putXMMReg( gregOfRexRM( pfx, modrm ), + binop( Iop_64HLtoV128, + unop( Iop_8Sto64, + unop( Iop_16HIto8, + mkexpr(srcBytes) ) ), + unop( Iop_8Sto64, + unop( Iop_16to8, mkexpr(srcBytes) ) ) ) ); + + goto decode_success; + } + + + /* 66 0f 38 23 /r = PMOVSXWD xmm1, xmm2/m64 + Packed Move with Sign Extend from Word to DWord (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x23 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg(modrm) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovsxwd %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) ); + delta += 3+alen; + DIP( "pmovsxwd %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_SarN32x4, + binop( Iop_ShlN32x4, + binop( Iop_InterleaveLO16x8, + IRExpr_Const( IRConst_V128(0) ), + mkexpr(srcVec) ), + mkU8(16) ), + mkU8(16) ) ); + + goto decode_success; + } + + + /* 66 0f 38 24 /r = PMOVSXWQ xmm1, xmm2/m32 + Packed Move with Sign Extend from Word to QWord (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x24 ) { + + modrm = insn[3]; + + IRTemp srcBytes = newTemp(Ity_I32); + + if ( epartIsReg( modrm ) ) { + assign( srcBytes, getXMMRegLane32( eregOfRexRM(pfx, modrm), 0 ) ); + delta += 3+1; + DIP( "pmovsxwq %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcBytes, loadLE( Ity_I32, mkexpr(addr) ) ); + delta += 3+alen; + DIP( "pmovsxwq %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + putXMMReg( gregOfRexRM( pfx, modrm ), + binop( Iop_64HLtoV128, + unop( Iop_16Sto64, + unop( Iop_32HIto16, mkexpr(srcBytes) ) ), + unop( Iop_16Sto64, + unop( Iop_32to16, mkexpr(srcBytes) ) ) ) ); + + goto decode_success; + } + + + /* 66 0f 38 25 /r = PMOVSXDQ xmm1, xmm2/m64 + Packed Move with Sign Extend from Double Word to Quad Word (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x25 ) { + + modrm = insn[3]; + + IRTemp srcBytes = newTemp(Ity_I64); + + if ( epartIsReg(modrm) ) { + assign( srcBytes, getXMMRegLane64( eregOfRexRM(pfx, modrm), 0 ) ); + delta += 3+1; + DIP( "pmovsxdq %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcBytes, loadLE( Ity_I64, mkexpr(addr) ) ); + delta += 3+alen; + DIP( "pmovsxdq %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_64HLtoV128, + unop( Iop_32Sto64, + unop( Iop_64HIto32, mkexpr(srcBytes) ) ), + unop( Iop_32Sto64, + unop( Iop_64to32, mkexpr(srcBytes) ) ) ) ); + + goto decode_success; + } + + + /* 66 0f 38 30 /r = PMOVZXBW xmm1, xmm2/m64 + Packed Move with Zero Extend from Byte to Word (XMM) */ + if ( have66noF2noF3(pfx) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x30 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg(modrm) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovzxbw %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) ); + delta += 3+alen; + DIP( "pmovzxbw %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_InterleaveLO8x16, + IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) ) ); + + goto decode_success; + } + + + /* 66 0f 38 31 /r = PMOVZXBD xmm1, xmm2/m32 + Packed Move with Zero Extend from Byte to DWord (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x31 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg(modrm) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovzxbd %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) ) ) ); + delta += 3+alen; + DIP( "pmovzxbd %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + IRTemp zeroVec = newTemp(Ity_V128); + assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) ); + + putXMMReg( gregOfRexRM( pfx, modrm ), + binop( Iop_InterleaveLO8x16, + mkexpr(zeroVec), + binop( Iop_InterleaveLO8x16, + mkexpr(zeroVec), mkexpr(srcVec) ) ) ); + + goto decode_success; + } + + + /* 66 0f 38 32 /r = PMOVZXBQ xmm1, xmm2/m16 + Packed Move with Zero Extend from Byte to QWord (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x32 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg(modrm) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovzxbq %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_32UtoV128, + unop( Iop_16Uto32, loadLE( Ity_I16, mkexpr(addr) ) ) ) ); + delta += 3+alen; + DIP( "pmovzxbq %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + IRTemp zeroVec = newTemp(Ity_V128); + assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) ); + + putXMMReg( gregOfRexRM( pfx, modrm ), + binop( Iop_InterleaveLO8x16, + mkexpr(zeroVec), + binop( Iop_InterleaveLO8x16, + mkexpr(zeroVec), + binop( Iop_InterleaveLO8x16, + mkexpr(zeroVec), mkexpr(srcVec) ) ) ) ); + + goto decode_success; + } + + + /* 66 0f 38 33 /r = PMOVZXWD xmm1, xmm2/m64 + Packed Move with Zero Extend from Word to DWord (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x33 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg(modrm) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovzxwd %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) ); + delta += 3+alen; + DIP( "pmovzxwd %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_InterleaveLO16x8, + IRExpr_Const( IRConst_V128(0) ), + mkexpr(srcVec) ) ); + + goto decode_success; + } + + + /* 66 0f 38 34 /r = PMOVZXWQ xmm1, xmm2/m32 + Packed Move with Zero Extend from Word to QWord (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x34 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg( modrm ) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovzxwq %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) ) ) ); + delta += 3+alen; + DIP( "pmovzxwq %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + IRTemp zeroVec = newTemp( Ity_V128 ); + assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) ); + + putXMMReg( gregOfRexRM( pfx, modrm ), + binop( Iop_InterleaveLO16x8, + mkexpr(zeroVec), + binop( Iop_InterleaveLO16x8, + mkexpr(zeroVec), mkexpr(srcVec) ) ) ); + + goto decode_success; + } + + + /* 66 0f 38 35 /r = PMOVZXDQ xmm1, xmm2/m64 + Packed Move with Zero Extend from DWord to QWord (XMM) */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x35 ) { + + modrm = insn[3]; + + IRTemp srcVec = newTemp(Ity_V128); + + if ( epartIsReg(modrm) ) { + assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmovzxdq %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( srcVec, + unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) ); + delta += 3+alen; + DIP( "pmovzxdq %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_InterleaveLO32x4, + IRExpr_Const( IRConst_V128(0) ), + mkexpr(srcVec) ) ); + + goto decode_success; + } + + + /* 66 0f 38 40 /r = PMULLD xmm1, xmm2/m128 + 32x4 integer multiply from xmm2/m128 to xmm1 */ + if ( have66noF2noF3( pfx ) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x40 ) { + + modrm = insn[3]; + + IRTemp argL = newTemp(Ity_V128); + IRTemp argR = newTemp(Ity_V128); + + if ( epartIsReg(modrm) ) { + assign( argL, getXMMReg( eregOfRexRM(pfx, modrm) ) ); + delta += 3+1; + DIP( "pmulld %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + gen_SEGV_if_not_16_aligned( addr ); + assign( argL, loadLE( Ity_V128, mkexpr(addr) )); + delta += 3+alen; + DIP( "pmulld %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + assign(argR, getXMMReg( gregOfRexRM(pfx, modrm) )); + + putXMMReg( gregOfRexRM(pfx, modrm), + binop( Iop_Mul32x4, mkexpr(argL), mkexpr(argR)) ); + + goto decode_success; + } + + + /* F3 0F B8 = POPCNT{W,L,Q} + Count the number of 1 bits in a register + */ + if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */ + && insn[0] == 0x0F && insn[1] == 0xB8) { + vassert(sz == 2 || sz == 4 || sz == 8); + /*IRType*/ ty = szToITy(sz); + IRTemp src = newTemp(ty); + modrm = insn[2]; + if (epartIsReg(modrm)) { + assign(src, getIRegE(sz, pfx, modrm)); + delta += 2+1; + DIP("popcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm), + nameIRegG(sz, pfx, modrm)); + } else { + addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0); + assign(src, loadLE(ty, mkexpr(addr))); + delta += 2+alen; + DIP("popcnt%c %s, %s\n", nameISize(sz), dis_buf, + nameIRegG(sz, pfx, modrm)); + } + + IRTemp result = gen_POPCOUNT(ty, src); + putIRegG(sz, pfx, modrm, mkexpr(result)); + + // Update flags. This is pretty lame .. perhaps can do better + // if this turns out to be performance critical. + // O S A C P are cleared. Z is set if SRC == 0. + stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) )); + stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) )); + stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) )); + stmt( IRStmt_Put( OFFB_CC_DEP1, + binop(Iop_Shl64, + unop(Iop_1Uto64, + binop(Iop_CmpEQ64, + widenUto64(mkexpr(src)), + mkU64(0))), + mkU8(AMD64G_CC_SHIFT_Z)))); + + goto decode_success; + } + + + /* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1 + (Partial implementation only -- only deal with cases where + the rounding mode is specified directly by the immediate byte.) + 66 0F 3A 0A /r ib = ROUNDSS imm8, xmm2/m32, xmm1 + (Limitations ditto) + */ + if (have66noF2noF3(pfx) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A + && (insn[2] == 0x0B || insn[2] == 0x0A)) { + + Bool isD = insn[2] == 0x0B; + IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32); + IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32); + Int imm = 0; + + modrm = insn[3]; + + if (epartIsReg(modrm)) { + assign( src, + isD ? getXMMRegLane64F( eregOfRexRM(pfx, modrm), 0 ) + : getXMMRegLane32F( eregOfRexRM(pfx, modrm), 0 ) ); + imm = insn[3+1]; + if (imm & ~3) goto decode_failure; + delta += 3+1+1; + DIP( "rounds%c $%d,%s,%s\n", + isD ? 'd' : 's', + imm, nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) )); + imm = insn[3+alen]; + if (imm & ~3) goto decode_failure; + delta += 3+alen+1; + DIP( "roundsd $%d,%s,%s\n", + imm, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + /* (imm & 3) contains an Intel-encoded rounding mode. Because + that encoding is the same as the encoding for IRRoundingMode, + we can use that value directly in the IR as a rounding + mode. */ + assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt, + mkU32(imm & 3), mkexpr(src)) ); + + if (isD) + putXMMRegLane64F( gregOfRexRM(pfx, modrm), 0, mkexpr(res) ); + else + putXMMRegLane32F( gregOfRexRM(pfx, modrm), 0, mkexpr(res) ); + + goto decode_success; + } + + /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension, + which we can only decode if we're sure this is an AMD cpu that + supports LZCNT, since otherwise it's BSR, which behaves + differently. */ + if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */ + && insn[0] == 0x0F && insn[1] == 0xBD + && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT)) { + vassert(sz == 2 || sz == 4 || sz == 8); + /*IRType*/ ty = szToITy(sz); + IRTemp src = newTemp(ty); + modrm = insn[2]; + if (epartIsReg(modrm)) { + assign(src, getIRegE(sz, pfx, modrm)); + delta += 2+1; + DIP("lzcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm), + nameIRegG(sz, pfx, modrm)); + } else { + addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0); + assign(src, loadLE(ty, mkexpr(addr))); + delta += 2+alen; + DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf, + nameIRegG(sz, pfx, modrm)); + } + + IRTemp res = gen_LZCNT(ty, src); + putIRegG(sz, pfx, modrm, mkexpr(res)); + + // Update flags. This is pretty lame .. perhaps can do better + // if this turns out to be performance critical. + // O S A P are cleared. Z is set if RESULT == 0. + // C is set if SRC is zero. + IRTemp src64 = newTemp(Ity_I64); + IRTemp res64 = newTemp(Ity_I64); + assign(src64, widenUto64(mkexpr(src))); + assign(res64, widenUto64(mkexpr(res))); + + IRTemp oszacp = newTemp(Ity_I64); + assign( + oszacp, + binop(Iop_Or64, + binop(Iop_Shl64, + unop(Iop_1Uto64, + binop(Iop_CmpEQ64, mkexpr(res64), mkU64(0))), + mkU8(AMD64G_CC_SHIFT_Z)), + binop(Iop_Shl64, + unop(Iop_1Uto64, + binop(Iop_CmpEQ64, mkexpr(src64), mkU64(0))), + mkU8(AMD64G_CC_SHIFT_C)) + ) + ); + + stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) )); + stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) )); + stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) )); + stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) )); + + goto decode_success; + } + + /* 66 0F 3A 63 /r ib = PCMPISTRI imm8, xmm2/m128, xmm1 + 66 0F 3A 62 /r ib = PCMPISTRM imm8, xmm2/m128, xmm1 + 66 0F 3A 61 /r ib = PCMPESTRI imm8, xmm2/m128, xmm1 + 66 0F 3A 60 /r ib = PCMPESTRM imm8, xmm2/m128, xmm1 + (selected special cases that actually occur in glibc, + not by any means a complete implementation.) + */ + if (have66noF2noF3(pfx) + && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A + && (insn[2] >= 0x60 && insn[2] <= 0x63)) { + + UInt isISTRx = insn[2] & 2; + UInt isxSTRM = (insn[2] & 1) ^ 1; + UInt regNoL = 0; + UInt regNoR = 0; + UChar imm = 0; + + /* This is a nasty kludge. We need to pass 2 x V128 to the + helper (which is clean). Since we can't do that, use a dirty + helper to compute the results directly from the XMM regs in + the guest state. That means for the memory case, we need to + move the left operand into a pseudo-register (XMM16, let's + call it). */ + modrm = insn[3]; + if (epartIsReg(modrm)) { + regNoL = eregOfRexRM(pfx, modrm); + regNoR = gregOfRexRM(pfx, modrm); + imm = insn[3+1]; + delta += 3+1+1; + } else { + regNoL = 16; /* use XMM16 as an intermediary */ + regNoR = gregOfRexRM(pfx, modrm); + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + /* No alignment check; I guess that makes sense, given that + these insns are for dealing with C style strings. */ + stmt( IRStmt_Put( OFFB_XMM16, loadLE(Ity_V128, mkexpr(addr)) )); + imm = insn[3+alen]; + delta += 3+alen+1; + } + + /* Now we know the XMM reg numbers for the operands, and the + immediate byte. Is it one we can actually handle? Throw out + any cases for which the helper function has not been + verified. */ + switch (imm) { + case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12: + case 0x1A: case 0x3A: case 0x44: case 0x4A: + break; + default: + goto decode_failure; + } + + /* Who ya gonna call? Presumably not Ghostbusters. */ + void* fn = &amd64g_dirtyhelper_PCMPxSTRx; + HChar* nm = "amd64g_dirtyhelper_PCMPxSTRx"; + + /* Round up the arguments. Note that this is a kludge -- the + use of mkU64 rather than mkIRExpr_HWord implies the + assumption that the host's word size is 64-bit. */ + UInt gstOffL = regNoL == 16 ? OFFB_XMM16 : xmmGuestRegOffset(regNoL); + UInt gstOffR = xmmGuestRegOffset(regNoR); + + IRExpr* opc4_and_imm = mkU64((insn[2] << 8) | (imm & 0xFF)); + IRExpr* gstOffLe = mkU64(gstOffL); + IRExpr* gstOffRe = mkU64(gstOffR); + IRExpr* edxIN = isISTRx ? mkU64(0) : getIRegRDX(8); + IRExpr* eaxIN = isISTRx ? mkU64(0) : getIRegRAX(8); + IRExpr** args + = mkIRExprVec_5( opc4_and_imm, gstOffLe, gstOffRe, edxIN, eaxIN ); + + IRTemp resT = newTemp(Ity_I64); + IRDirty* d = unsafeIRDirty_1_N( resT, 0/*regparms*/, nm, fn, args ); + /* It's not really a dirty call, but we can't use the clean + helper mechanism here for the very lame reason that we can't + pass 2 x V128s by value to a helper, nor get one back. Hence + this roundabout scheme. */ + d->needsBBP = True; + d->nFxState = 2; + d->fxState[0].fx = Ifx_Read; + d->fxState[0].offset = gstOffL; + d->fxState[0].size = sizeof(U128); + d->fxState[1].fx = Ifx_Read; + d->fxState[1].offset = gstOffR; + d->fxState[1].size = sizeof(U128); + if (isxSTRM) { + /* Declare that the helper writes XMM0. */ + d->nFxState = 3; + d->fxState[2].fx = Ifx_Write; + d->fxState[2].offset = xmmGuestRegOffset(0); + d->fxState[2].size = sizeof(U128); + } + + stmt( IRStmt_Dirty(d) ); + + /* Now resT[15:0] holds the new OSZACP values, so the condition + codes must be updated. And for a xSTRI case, resT[31:16] + holds the new ECX value, so stash that too. */ + if (!isxSTRM) { + putIReg64(R_RCX, binop(Iop_And64, + binop(Iop_Shr64, mkexpr(resT), mkU8(16)), + mkU64(0xFFFF))); + } + + stmt( IRStmt_Put( + OFFB_CC_DEP1, + binop(Iop_And64, mkexpr(resT), mkU64(0xFFFF)) + )); + stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) )); + stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) )); + stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) )); + + if (regNoL == 16) { + DIP("pcmp%cstr%c $%x,%s,%s\n", + isISTRx ? 'i' : 'e', isxSTRM ? 'm' : 'i', + (UInt)imm, dis_buf, nameXMMReg(regNoR)); + } else { + DIP("pcmp%cstr%c $%x,%s,%s\n", + isISTRx ? 'i' : 'e', isxSTRM ? 'm' : 'i', + (UInt)imm, nameXMMReg(regNoL), nameXMMReg(regNoR)); + } + + goto decode_success; + } + + + /* 66 0f 38 17 /r = PTEST xmm1, xmm2/m128 + Logical compare (set ZF and CF from AND/ANDN of the operands) */ + if (have66noF2noF3( pfx ) && sz == 2 + && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x17) { + modrm = insn[3]; + IRTemp vecE = newTemp(Ity_V128); + IRTemp vecG = newTemp(Ity_V128); + + if ( epartIsReg(modrm) ) { + assign(vecE, getXMMReg(eregOfRexRM(pfx, modrm))); + delta += 3+1; + DIP( "ptest %s,%s\n", + nameXMMReg( eregOfRexRM(pfx, modrm) ), + nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } else { + addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 ); + gen_SEGV_if_not_16_aligned( addr ); + assign(vecE, loadLE( Ity_V128, mkexpr(addr) )); + delta += 3+alen; + DIP( "ptest %s,%s\n", + dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) ); + } + + assign(vecG, getXMMReg(gregOfRexRM(pfx, modrm))); + + /* Set Z=1 iff (vecE & vecG) == 0 + Set C=1 iff (vecE & not vecG) == 0 + */ + + /* andV, andnV: vecE & vecG, vecE and not(vecG) */ + IRTemp andV = newTemp(Ity_V128); + IRTemp andnV = newTemp(Ity_V128); + assign(andV, binop(Iop_AndV128, mkexpr(vecE), mkexpr(vecG))); + assign(andnV, binop(Iop_AndV128, + mkexpr(vecE), + binop(Iop_XorV128, mkexpr(vecG), + mkV128(0xFFFF)))); + + /* The same, but reduced to 64-bit values, by or-ing the top + and bottom 64-bits together. It relies on this trick: + + InterleaveLO64x2([a,b],[c,d]) == [b,d] hence + + InterleaveLO64x2([a,b],[a,b]) == [b,b] and similarly + InterleaveHI64x2([a,b],[a,b]) == [a,a] + + and so the OR of the above 2 exprs produces + [a OR b, a OR b], from which we simply take the lower half. + */ + IRTemp and64 = newTemp(Ity_I64); + IRTemp andn64 = newTemp(Ity_I64); + + assign( + and64, + unop(Iop_V128to64, + binop(Iop_OrV128, + binop(Iop_InterleaveLO64x2, mkexpr(andV), mkexpr(andV)), + binop(Iop_InterleaveHI64x2, mkexpr(andV), mkexpr(andV)) + ) + ) + ); + + assign( + andn64, + unop(Iop_V128to64, + binop(Iop_OrV128, + binop(Iop_InterleaveLO64x2, mkexpr(andnV), mkexpr(andnV)), + binop(Iop_InterleaveHI64x2, mkexpr(andnV), mkexpr(andnV)) + ) + ) + ); + + /* Now convert and64, andn64 to all-zeroes or all-1s, so we can + slice out the Z and C bits conveniently. We use the standard + trick all-zeroes -> all-zeroes, anything-else -> all-ones + done by "(x | -x) >>s (word-size - 1)". + */ + IRTemp z64 = newTemp(Ity_I64); + IRTemp c64 = newTemp(Ity_I64); + assign(z64, + unop(Iop_Not64, + binop(Iop_Sar64, + binop(Iop_Or64, + binop(Iop_Sub64, mkU64(0), mkexpr(and64)), + mkexpr(and64) + ), + mkU8(63))) + ); + + assign(c64, + unop(Iop_Not64, + binop(Iop_Sar64, + binop(Iop_Or64, + binop(Iop_Sub64, mkU64(0), mkexpr(andn64)), + mkexpr(andn64) + ), + mkU8(63))) + ); + + /* And finally, slice out the Z and C flags and set the flags + thunk to COPY for them. OSAP are set to zero. */ + IRTemp newOSZACP = newTemp(Ity_I64); + assign(newOSZACP, + binop(Iop_Or64, + binop(Iop_And64, mkexpr(z64), mkU64(AMD64G_CC_MASK_Z)), + binop(Iop_And64, mkexpr(c64), mkU64(AMD64G_CC_MASK_C)) + ) + ); + + stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(newOSZACP))); + stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) )); + stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) )); + stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) )); + + goto decode_success; + } + + + /* ---------------------------------------------------- */ + /* --- end of the SSE4 decoder --- */ + /* ---------------------------------------------------- */ + + /*after_sse_decoders:*/ + + /* Get the primary opcode. */ + opc = getUChar(delta); delta++; + + /* We get here if the current insn isn't SSE, or this CPU doesn't + support SSE. */ + + switch (opc) { + + /* ------------------------ Control flow --------------- */ + + case 0xC2: /* RET imm16 */ + if (have66orF2orF3(pfx)) goto decode_failure; + d64 = getUDisp16(delta); + delta += 2; + dis_ret(vbi, d64); + dres.whatNext = Dis_StopHere; + DIP("ret %lld\n", d64); + break; + + case 0xC3: /* RET */ + if (have66orF2(pfx)) goto decode_failure; + /* F3 is acceptable on AMD. */ + dis_ret(vbi, 0); + dres.whatNext = Dis_StopHere; + DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n"); + break; + + case 0xE8: /* CALL J4 */ + if (haveF2orF3(pfx)) goto decode_failure; + d64 = getSDisp32(delta); delta += 4; + d64 += (guest_RIP_bbstart+delta); + /* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */ + t1 = newTemp(Ity_I64); + assign(t1, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8))); + putIReg64(R_RSP, mkexpr(t1)); + storeLE( mkexpr(t1), mkU64(guest_RIP_bbstart+delta)); + t2 = newTemp(Ity_I64); + assign(t2, mkU64((Addr64)d64)); + make_redzone_AbiHint(vbi, t1, t2/*nia*/, "call-d32"); + if (resteerOkFn( callback_opaque, (Addr64)d64) ) { + /* follow into the call target. */ + dres.whatNext = Dis_ResteerU; + dres.continueAt = d64; + } else { + jmp_lit(Ijk_Call,d64); + dres.whatNext = Dis_StopHere; + } + DIP("call 0x%llx\n",d64); + break; + +//.. //-- case 0xC8: /* ENTER */ +//.. //-- d32 = getUDisp16(eip); eip += 2; +//.. //-- abyte = getUChar(delta); delta++; +//.. //-- +//.. //-- vg_assert(sz == 4); +//.. //-- vg_assert(abyte == 0); +//.. //-- +//.. //-- t1 = newTemp(cb); t2 = newTemp(cb); +//.. //-- uInstr2(cb, GET, sz, ArchReg, R_EBP, TempReg, t1); +//.. //-- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2); +//.. //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2); +//.. //-- uLiteral(cb, sz); +//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP); +//.. //-- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2); +//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBP); +//.. //-- if (d32) { +//.. //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2); +//.. //-- uLiteral(cb, d32); +//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP); +//.. //-- } +//.. //-- DIP("enter 0x%x, 0x%x", d32, abyte); +//.. //-- break; + + case 0xC9: /* LEAVE */ + /* In 64-bit mode this defaults to a 64-bit operand size. There + is no way to encode a 32-bit variant. Hence sz==4 but we do + it as if sz=8. */ + if (sz != 4) + goto decode_failure; + t1 = newTemp(Ity_I64); + t2 = newTemp(Ity_I64); + assign(t1, getIReg64(R_RBP)); + /* First PUT RSP looks redundant, but need it because RSP must + always be up-to-date for Memcheck to work... */ + putIReg64(R_RSP, mkexpr(t1)); + assign(t2, loadLE(Ity_I64,mkexpr(t1))); + putIReg64(R_RBP, mkexpr(t2)); + putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t1), mkU64(8)) ); + DIP("leave\n"); + break; + +//.. //-- /* ---------------- Misc weird-ass insns --------------- */ +//.. //-- +//.. //-- case 0x27: /* DAA */ +//.. //-- case 0x2F: /* DAS */ +//.. //-- t1 = newTemp(cb); +//.. //-- uInstr2(cb, GET, 1, ArchReg, R_AL, TempReg, t1); +//.. //-- /* Widen %AL to 32 bits, so it's all defined when we push it. */ +//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1); +//.. //-- uWiden(cb, 1, False); +//.. //-- uInstr0(cb, CALLM_S, 0); +//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1); +//.. //-- uInstr1(cb, CALLM, 0, Lit16, +//.. //-- opc == 0x27 ? VGOFF_(helper_DAA) : VGOFF_(helper_DAS) ); +//.. //-- uFlagsRWU(cb, FlagsAC, FlagsSZACP, FlagO); +//.. //-- uInstr1(cb, POP, 4, TempReg, t1); +//.. //-- uInstr0(cb, CALLM_E, 0); +//.. //-- uInstr2(cb, PUT, 1, TempReg, t1, ArchReg, R_AL); +//.. //-- DIP(opc == 0x27 ? "daa\n" : "das\n"); +//.. //-- break; +//.. //-- +//.. //-- case 0x37: /* AAA */ +//.. //-- case 0x3F: /* AAS */ +//.. //-- t1 = newTemp(cb); +//.. //-- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1); +//.. //-- /* Widen %AL to 32 bits, so it's all defined when we push it. */ +//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1); +//.. //-- uWiden(cb, 2, False); +//.. //-- uInstr0(cb, CALLM_S, 0); +//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1); +//.. //-- uInstr1(cb, CALLM, 0, Lit16, +//.. //-- opc == 0x37 ? VGOFF_(helper_AAA) : VGOFF_(helper_AAS) ); +//.. //-- uFlagsRWU(cb, FlagA, FlagsAC, FlagsEmpty); +//.. //-- uInstr1(cb, POP, 4, TempReg, t1); +//.. //-- uInstr0(cb, CALLM_E, 0); +//.. //-- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX); +//.. //-- DIP(opc == 0x37 ? "aaa\n" : "aas\n"); +//.. //-- break; +//.. //-- +//.. //-- case 0xD4: /* AAM */ +//.. //-- case 0xD5: /* AAD */ +//.. //-- d32 = getUChar(delta); delta++; +//.. //-- if (d32 != 10) VG_(core_panic)("disInstr: AAM/AAD but base not 10 !"); +//.. //-- t1 = newTemp(cb); +//.. //-- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1); +//.. //-- /* Widen %AX to 32 bits, so it's all defined when we push it. */ +//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1); +//.. //-- uWiden(cb, 2, False); +//.. //-- uInstr0(cb, CALLM_S, 0); +//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1); +//.. //-- uInstr1(cb, CALLM, 0, Lit16, +//.. //-- opc == 0xD4 ? VGOFF_(helper_AAM) : VGOFF_(helper_AAD) ); +//.. //-- uFlagsRWU(cb, FlagsEmpty, FlagsSZP, FlagsEmpty); +//.. //-- uInstr1(cb, POP, 4, TempReg, t1); +//.. //-- uInstr0(cb, CALLM_E, 0); +//.. //-- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX); +//.. //-- DIP(opc == 0xD4 ? "aam\n" : "aad\n"); +//.. //-- break; + + /* ------------------------ CWD/CDQ -------------------- */ + + case 0x98: /* CBW */ + if (haveF2orF3(pfx)) goto decode_failure; + if (sz == 8) { + putIRegRAX( 8, unop(Iop_32Sto64, getIRegRAX(4)) ); + DIP(/*"cdqe\n"*/"cltq"); + break; + } + if (sz == 4) { + putIRegRAX( 4, unop(Iop_16Sto32, getIRegRAX(2)) ); + DIP("cwtl\n"); + break; + } + if (sz == 2) { + putIRegRAX( 2, unop(Iop_8Sto16, getIRegRAX(1)) ); + DIP("cbw\n"); + break; + } + goto decode_failure; + + case 0x99: /* CWD/CDQ/CQO */ + if (haveF2orF3(pfx)) goto decode_failure; + vassert(sz == 2 || sz == 4 || sz == 8); + ty = szToITy(sz); + putIRegRDX( sz, + binop(mkSizedOp(ty,Iop_Sar8), + getIRegRAX(sz), + mkU8(sz == 2 ? 15 : (sz == 4 ? 31 : 63))) ); + DIP(sz == 2 ? "cwd\n" + : (sz == 4 ? /*"cdq\n"*/ "cltd\n" + : "cqo\n")); + break; + + /* ------------------------ FPU ops -------------------- */ + + case 0x9E: /* SAHF */ + codegen_SAHF(); + DIP("sahf\n"); break; case 0x9F: /* LAHF */ @@ -13930,7 +15829,7 @@ DisResult disInstr_AMD64_WRK ( d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta); delta++; if (resteerOkFn(callback_opaque,d64)) { - dres.whatNext = Dis_Resteer; + dres.whatNext = Dis_ResteerU; dres.continueAt = d64; } else { jmp_lit(Ijk_Boring,d64); @@ -13946,7 +15845,7 @@ DisResult disInstr_AMD64_WRK ( d64 = (guest_RIP_bbstart+delta+sz) + getSDisp(sz,delta); delta += sz; if (resteerOkFn(callback_opaque,d64)) { - dres.whatNext = Dis_Resteer; + dres.whatNext = Dis_ResteerU; dres.continueAt = d64; } else { jmp_lit(Ijk_Boring,d64); @@ -13971,15 +15870,62 @@ DisResult disInstr_AMD64_WRK ( case 0x7D: /* JGEb/JNLb (jump greater or equal) */ case 0x7E: /* JLEb/JNGb (jump less or equal) */ case 0x7F: /* JGb/JNLEb (jump greater) */ + { Long jmpDelta; + HChar* comment = ""; if (haveF2orF3(pfx)) goto decode_failure; - d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta); + jmpDelta = getSDisp8(delta); + vassert(-128 <= jmpDelta && jmpDelta < 128); + d64 = (guest_RIP_bbstart+delta+1) + jmpDelta; delta++; - jcc_01( (AMD64Condcode)(opc - 0x70), - guest_RIP_bbstart+delta, - d64 ); - dres.whatNext = Dis_StopHere; - DIP("j%s-8 0x%llx\n", name_AMD64Condcode(opc - 0x70), d64); + if (resteerCisOk + && vex_control.guest_chase_cond + && (Addr64)d64 != (Addr64)guest_RIP_bbstart + && jmpDelta < 0 + && resteerOkFn( callback_opaque, d64) ) { + /* Speculation: assume this backward branch is taken. So we + need to emit a side-exit to the insn following this one, + on the negation of the condition, and continue at the + branch target address (d64). If we wind up back at the + first instruction of the trace, just stop; it's better to + let the IR loop unroller handle that case. */ + stmt( IRStmt_Exit( + mk_amd64g_calculate_condition( + (AMD64Condcode)(1 ^ (opc - 0x70))), + Ijk_Boring, + IRConst_U64(guest_RIP_bbstart+delta) ) ); + dres.whatNext = Dis_ResteerC; + dres.continueAt = d64; + comment = "(assumed taken)"; + } + else + if (resteerCisOk + && vex_control.guest_chase_cond + && (Addr64)d64 != (Addr64)guest_RIP_bbstart + && jmpDelta >= 0 + && resteerOkFn( callback_opaque, guest_RIP_bbstart+delta ) ) { + /* Speculation: assume this forward branch is not taken. So + we need to emit a side-exit to d64 (the dest) and continue + disassembling at the insn immediately following this + one. */ + stmt( IRStmt_Exit( + mk_amd64g_calculate_condition((AMD64Condcode)(opc - 0x70)), + Ijk_Boring, + IRConst_U64(d64) ) ); + dres.whatNext = Dis_ResteerC; + dres.continueAt = guest_RIP_bbstart+delta; + comment = "(assumed not taken)"; + } + else { + /* Conservative default translation - end the block at this + point. */ + jcc_01( (AMD64Condcode)(opc - 0x70), + guest_RIP_bbstart+delta, + d64 ); + dres.whatNext = Dis_StopHere; + } + DIP("j%s-8 0x%llx %s\n", name_AMD64Condcode(opc - 0x70), d64, comment); break; + } case 0xE3: /* JRCXZ or JECXZ, depending address size override. */ @@ -14032,12 +15978,12 @@ DisResult disInstr_AMD64_WRK ( case 0xE1: xtra = "e"; zbit = mk_amd64g_calculate_condition( AMD64CondZ ); - cond = mkAnd1(cond, zbit); + cond = mkAnd1(cond, zbit); break; case 0xE0: xtra = "ne"; zbit = mk_amd64g_calculate_condition( AMD64CondNZ ); - cond = mkAnd1(cond, zbit); + cond = mkAnd1(cond, zbit); break; default: vassert(0); @@ -14276,18 +16222,20 @@ DisResult disInstr_AMD64_WRK ( if (haveF2orF3(pfx)) goto decode_failure; delta = dis_op_imm_A( 1, True, Iop_Add8, True, delta, "adc" ); break; -//.. //-- case 0x15: /* ADC Iv, eAX */ -//.. //-- delta = dis_op_imm_A( sz, ADC, True, delta, "adc" ); -//.. //-- break; + case 0x15: /* ADC Iv, eAX */ + if (haveF2orF3(pfx)) goto decode_failure; + delta = dis_op_imm_A( sz, True, Iop_Add8, True, delta, "adc" ); + break; case 0x1C: /* SBB Ib, AL */ if (haveF2orF3(pfx)) goto decode_failure; delta = dis_op_imm_A( 1, True, Iop_Sub8, True, delta, "sbb" ); break; -//.. //-- case 0x1D: /* SBB Iv, eAX */ -//.. //-- delta = dis_op_imm_A( sz, SBB, True, delta, "sbb" ); -//.. //-- break; -//.. //-- + case 0x1D: /* SBB Iv, eAX */ + if (haveF2orF3(pfx)) goto decode_failure; + delta = dis_op_imm_A( sz, True, Iop_Sub8, True, delta, "sbb" ); + break; + case 0x24: /* AND Ib, AL */ if (haveF2orF3(pfx)) goto decode_failure; delta = dis_op_imm_A( 1, False, Iop_And8, True, delta, "and" ); @@ -14362,9 +16310,10 @@ DisResult disInstr_AMD64_WRK ( delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" ); break; -//.. //-- case 0x1A: /* SBB Eb,Gb */ -//.. //-- delta = dis_op2_E_G ( sorb, True, SBB, True, 1, delta, "sbb" ); -//.. //-- break; + case 0x1A: /* SBB Eb,Gb */ + if (haveF2orF3(pfx)) goto decode_failure; + delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" ); + break; case 0x1B: /* SBB Ev,Gv */ if (haveF2orF3(pfx)) goto decode_failure; delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" ); @@ -14564,6 +16513,19 @@ DisResult disInstr_AMD64_WRK ( mkU64(1))) ); + /* And set the AC flag too */ + stmt( IRStmt_Put( + OFFB_ACFLAG, + IRExpr_Mux0X( + unop(Iop_32to8, + unop(Iop_64to32, + binop(Iop_And64, + binop(Iop_Shr64, mkexpr(t1), mkU8(18)), + mkU64(1)))), + mkU64(0), + mkU64(1))) + ); + DIP("popf%c\n", nameISize(sz)); break; @@ -14728,12 +16690,22 @@ DisResult disInstr_AMD64_WRK ( mkU64(1<<21))) ); + /* And patch in the AC flag too. */ + t5 = newTemp(Ity_I64); + assign( t5, binop(Iop_Or64, + mkexpr(t4), + binop(Iop_And64, + binop(Iop_Shl64, IRExpr_Get(OFFB_ACFLAG,Ity_I64), + mkU8(18)), + mkU64(1<<18))) + ); + /* if sz==2, the stored value needs to be narrowed. */ if (sz == 2) storeLE( mkexpr(t1), unop(Iop_32to16, - unop(Iop_64to32,mkexpr(t4))) ); + unop(Iop_64to32,mkexpr(t5))) ); else - storeLE( mkexpr(t1), mkexpr(t4) ); + storeLE( mkexpr(t1), mkexpr(t5) ); DIP("pushf%c\n", nameISize(sz)); break; @@ -15649,13 +17621,16 @@ DisResult disInstr_AMD64_WRK ( if (haveF2orF3(pfx)) goto decode_failure; if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3 |VEX_HWCAPS_AMD64_CX16)) { - fName = "amd64g_dirtyhelper_CPUID_sse3_and_cx16"; - fAddr = &amd64g_dirtyhelper_CPUID_sse3_and_cx16; + //fName = "amd64g_dirtyhelper_CPUID_sse3_and_cx16"; + //fAddr = &amd64g_dirtyhelper_CPUID_sse3_and_cx16; /* This is a Core-2-like machine */ + fName = "amd64g_dirtyhelper_CPUID_sse42_and_cx16"; + fAddr = &amd64g_dirtyhelper_CPUID_sse42_and_cx16; + /* This is a Core-i5-like machine */ } else { - /* Give a CPUID for at least a baseline machine, no SSE2 - and no CX16 */ + /* Give a CPUID for at least a baseline machine, SSE2 + only, and no CX16 */ fName = "amd64g_dirtyhelper_CPUID_baseline"; fAddr = &amd64g_dirtyhelper_CPUID_baseline; } @@ -15765,15 +17740,62 @@ DisResult disInstr_AMD64_WRK ( case 0x8D: /* JGEb/JNLb (jump greater or equal) */ case 0x8E: /* JLEb/JNGb (jump less or equal) */ case 0x8F: /* JGb/JNLEb (jump greater) */ + { Long jmpDelta; + HChar* comment = ""; if (haveF2orF3(pfx)) goto decode_failure; - d64 = (guest_RIP_bbstart+delta+4) + getSDisp32(delta); + jmpDelta = getSDisp32(delta); + d64 = (guest_RIP_bbstart+delta+4) + jmpDelta; delta += 4; - jcc_01( (AMD64Condcode)(opc - 0x80), - guest_RIP_bbstart+delta, - d64 ); - dres.whatNext = Dis_StopHere; - DIP("j%s-32 0x%llx\n", name_AMD64Condcode(opc - 0x80), d64); + if (resteerCisOk + && vex_control.guest_chase_cond + && (Addr64)d64 != (Addr64)guest_RIP_bbstart + && jmpDelta < 0 + && resteerOkFn( callback_opaque, d64) ) { + /* Speculation: assume this backward branch is taken. So + we need to emit a side-exit to the insn following this + one, on the negation of the condition, and continue at + the branch target address (d64). If we wind up back at + the first instruction of the trace, just stop; it's + better to let the IR loop unroller handle that case. */ + stmt( IRStmt_Exit( + mk_amd64g_calculate_condition( + (AMD64Condcode)(1 ^ (opc - 0x80))), + Ijk_Boring, + IRConst_U64(guest_RIP_bbstart+delta) ) ); + dres.whatNext = Dis_ResteerC; + dres.continueAt = d64; + comment = "(assumed taken)"; + } + else + if (resteerCisOk + && vex_control.guest_chase_cond + && (Addr64)d64 != (Addr64)guest_RIP_bbstart + && jmpDelta >= 0 + && resteerOkFn( callback_opaque, guest_RIP_bbstart+delta ) ) { + /* Speculation: assume this forward branch is not taken. + So we need to emit a side-exit to d64 (the dest) and + continue disassembling at the insn immediately + following this one. */ + stmt( IRStmt_Exit( + mk_amd64g_calculate_condition((AMD64Condcode) + (opc - 0x80)), + Ijk_Boring, + IRConst_U64(d64) ) ); + dres.whatNext = Dis_ResteerC; + dres.continueAt = guest_RIP_bbstart+delta; + comment = "(assumed not taken)"; + } + else { + /* Conservative default translation - end the block at + this point. */ + jcc_01( (AMD64Condcode)(opc - 0x80), + guest_RIP_bbstart+delta, + d64 ); + dres.whatNext = Dis_StopHere; + } + DIP("j%s-32 0x%llx %s\n", name_AMD64Condcode(opc - 0x80), d64, comment); break; + } /* =-=-=-=-=-=-=-=-=- PREFETCH =-=-=-=-=-=-=-=-=-= */ case 0x0D: /* 0F 0D /0 -- prefetch mem8 */ @@ -16024,6 +18046,41 @@ DisResult disInstr_AMD64_WRK ( DIP("{f}emms\n"); break; + /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */ + case 0x01: /* 0F 01 /0 -- SGDT */ + /* 0F 01 /1 -- SIDT */ + { + /* This is really revolting, but ... since each processor + (core) only has one IDT and one GDT, just let the guest + see it (pass-through semantics). I can't see any way to + construct a faked-up value, so don't bother to try. */ + modrm = getUChar(delta); + addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); + delta += alen; + if (epartIsReg(modrm)) goto decode_failure; + if (gregLO3ofRM(modrm) != 0 && gregLO3ofRM(modrm) != 1) + goto decode_failure; + switch (gregLO3ofRM(modrm)) { + case 0: DIP("sgdt %s\n", dis_buf); break; + case 1: DIP("sidt %s\n", dis_buf); break; + default: vassert(0); /*NOTREACHED*/ + } + + IRDirty* d = unsafeIRDirty_0_N ( + 0/*regparms*/, + "amd64g_dirtyhelper_SxDT", + &amd64g_dirtyhelper_SxDT, + mkIRExprVec_2( mkexpr(addr), + mkU64(gregLO3ofRM(modrm)) ) + ); + /* declare we're writing memory */ + d->mFx = Ifx_Write; + d->mAddr = mkexpr(addr); + d->mSize = 6; + stmt( IRStmt_Dirty(d) ); + break; + } + /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */ default: @@ -16086,6 +18143,7 @@ DisResult disInstr_AMD64_WRK ( DisResult disInstr_AMD64 ( IRSB* irsb_IN, Bool put_IP, Bool (*resteerOkFn) ( void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, UChar* guest_code_IN, Long delta, @@ -16114,6 +18172,7 @@ DisResult disInstr_AMD64 ( IRSB* irsb_IN, x1 = irsb_IN->stmts_used; expect_CAS = False; dres = disInstr_AMD64_WRK ( &expect_CAS, put_IP, resteerOkFn, + resteerCisOk, callback_opaque, delta, archinfo, abiinfo ); x2 = irsb_IN->stmts_used; @@ -16146,6 +18205,7 @@ DisResult disInstr_AMD64 ( IRSB* irsb_IN, to generate a useful error message; then assert. */ vex_traceflags |= VEX_TRACE_FE; dres = disInstr_AMD64_WRK ( &expect_CAS, put_IP, resteerOkFn, + resteerCisOk, callback_opaque, delta, archinfo, abiinfo ); for (i = x1; i < x2; i++) { @@ -16162,6 +18222,72 @@ DisResult disInstr_AMD64 ( IRSB* irsb_IN, } +/*------------------------------------------------------------*/ +/*--- Unused stuff ---*/ +/*------------------------------------------------------------*/ + +// A potentially more Memcheck-friendly version of gen_LZCNT, if +// this should ever be needed. +// +//static IRTemp gen_LZCNT ( IRType ty, IRTemp src ) +//{ +// /* Scheme is simple: propagate the most significant 1-bit into all +// lower positions in the word. This gives a word of the form +// 0---01---1. Now invert it, giving a word of the form +// 1---10---0, then do a population-count idiom (to count the 1s, +// which is the number of leading zeroes, or the word size if the +// original word was 0. +// */ +// Int i; +// IRTemp t[7]; +// for (i = 0; i < 7; i++) { +// t[i] = newTemp(ty); +// } +// if (ty == Ity_I64) { +// assign(t[0], binop(Iop_Or64, mkexpr(src), +// binop(Iop_Shr64, mkexpr(src), mkU8(1)))); +// assign(t[1], binop(Iop_Or64, mkexpr(t[0]), +// binop(Iop_Shr64, mkexpr(t[0]), mkU8(2)))); +// assign(t[2], binop(Iop_Or64, mkexpr(t[1]), +// binop(Iop_Shr64, mkexpr(t[1]), mkU8(4)))); +// assign(t[3], binop(Iop_Or64, mkexpr(t[2]), +// binop(Iop_Shr64, mkexpr(t[2]), mkU8(8)))); +// assign(t[4], binop(Iop_Or64, mkexpr(t[3]), +// binop(Iop_Shr64, mkexpr(t[3]), mkU8(16)))); +// assign(t[5], binop(Iop_Or64, mkexpr(t[4]), +// binop(Iop_Shr64, mkexpr(t[4]), mkU8(32)))); +// assign(t[6], unop(Iop_Not64, mkexpr(t[5]))); +// return gen_POPCOUNT(ty, t[6]); +// } +// if (ty == Ity_I32) { +// assign(t[0], binop(Iop_Or32, mkexpr(src), +// binop(Iop_Shr32, mkexpr(src), mkU8(1)))); +// assign(t[1], binop(Iop_Or32, mkexpr(t[0]), +// binop(Iop_Shr32, mkexpr(t[0]), mkU8(2)))); +// assign(t[2], binop(Iop_Or32, mkexpr(t[1]), +// binop(Iop_Shr32, mkexpr(t[1]), mkU8(4)))); +// assign(t[3], binop(Iop_Or32, mkexpr(t[2]), +// binop(Iop_Shr32, mkexpr(t[2]), mkU8(8)))); +// assign(t[4], binop(Iop_Or32, mkexpr(t[3]), +// binop(Iop_Shr32, mkexpr(t[3]), mkU8(16)))); +// assign(t[5], unop(Iop_Not32, mkexpr(t[4]))); +// return gen_POPCOUNT(ty, t[5]); +// } +// if (ty == Ity_I16) { +// assign(t[0], binop(Iop_Or16, mkexpr(src), +// binop(Iop_Shr16, mkexpr(src), mkU8(1)))); +// assign(t[1], binop(Iop_Or16, mkexpr(t[0]), +// binop(Iop_Shr16, mkexpr(t[0]), mkU8(2)))); +// assign(t[2], binop(Iop_Or16, mkexpr(t[1]), +// binop(Iop_Shr16, mkexpr(t[1]), mkU8(4)))); +// assign(t[3], binop(Iop_Or16, mkexpr(t[2]), +// binop(Iop_Shr16, mkexpr(t[2]), mkU8(8)))); +// assign(t[4], unop(Iop_Not16, mkexpr(t[3]))); +// return gen_POPCOUNT(ty, t[4]); +// } +// vassert(0); +//} + /*--------------------------------------------------------------------*/ /*--- end guest_amd64_toIR.c ---*/ diff --git a/VEX/priv/guest_arm_defs.h b/VEX/priv/guest_arm_defs.h index 04864a3..02078c4 100644 --- a/VEX/priv/guest_arm_defs.h +++ b/VEX/priv/guest_arm_defs.h @@ -1,47 +1,30 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_arm_defs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_arm_defs.h ---*/ /*---------------------------------------------------------------*/ - /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - This library is made available under a dual licensing scheme. + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. - - Neither the names of the U.S. Department of Energy nor the - University of California nor the names of its contributors may be - used to endorse or promote products derived from this software - without prior written permission. + The GNU General Public License is contained in the file COPYING. */ /* Only to be used within the guest-arm directory. */ @@ -54,19 +37,28 @@ /*--- arm to IR conversion ---*/ /*---------------------------------------------------------*/ +/* Convert one ARM insn to IR. See the type DisOneInstrFn in + bb_to_IR.h. */ extern -IRSB* bbToIR_ARM ( UChar* armCode, - Addr64 eip, - VexGuestExtents* vge, - Bool (*byte_accessible)(Addr64), - Bool (*resteerOkFn)(Addr64), - Bool host_bigendian, - VexArchInfo* archinfo_guest ); +DisResult disInstr_ARM ( IRSB* irbb, + Bool put_IP, + Bool (*resteerOkFn) ( void*, Addr64 ), + Bool resteerCisOk, + void* callback_opaque, + UChar* guest_code, + Long delta, + Addr64 guest_IP, + VexArch guest_arch, + VexArchInfo* archinfo, + VexAbiInfo* abiinfo, + Bool host_bigendian ); /* Used by the optimiser to specialise calls to helpers. */ extern -IRExpr* guest_arm_spechelper ( HChar* function_name, - IRExpr** args ); +IRExpr* guest_arm_spechelper ( HChar* function_name, + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ); /* Describes to the optimser which part of the guest state require precise memory exceptions. This is logically part of the guest @@ -84,18 +76,37 @@ VexGuestLayout armGuest_layout; /* --- CLEAN HELPERS --- */ -extern UInt armg_calculate_flags_all ( - UInt cc_op, UInt cc_dep1, UInt cc_dep2 - ); -extern UInt armg_calculate_flags_c ( - UInt cc_op, UInt cc_dep1, UInt cc_dep2 - ); +/* Calculate NZCV from the supplied thunk components, in the positions + they appear in the CPSR, viz bits 31:28 for N Z V C respectively. + Returned bits 27:0 are zero. */ +extern +UInt armg_calculate_flags_nzcv ( UInt cc_op, UInt cc_dep1, + UInt cc_dep2, UInt cc_dep3 ); + +/* Calculate the C flag from the thunk components, in the lowest bit + of the word (bit 0). */ +extern +UInt armg_calculate_flag_c ( UInt cc_op, UInt cc_dep1, + UInt cc_dep2, UInt cc_dep3 ); + +/* Calculate the V flag from the thunk components, in the lowest bit + of the word (bit 0). */ +extern +UInt armg_calculate_flag_v ( UInt cc_op, UInt cc_dep1, + UInt cc_dep2, UInt cc_dep3 ); + +/* Calculate the specified condition from the thunk components, in the + lowest bit of the word (bit 0). */ +extern +UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */, + UInt cc_dep1, + UInt cc_dep2, UInt cc_dep3 ); -extern UInt armg_calculate_condition ( - UInt/*ARMCondcode*/ cond, - UInt cc_op, - UInt cc_dep1, UInt cc_dep2 - ); +/* Calculate the QC flag from the thunk components, in the lowest bit + of the word (bit 0). */ +extern +UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2, + UInt resR1, UInt resR2 ); /*---------------------------------------------------------*/ @@ -107,67 +118,82 @@ extern UInt armg_calculate_condition ( #define ARMG_CC_SHIFT_Z 30 #define ARMG_CC_SHIFT_C 29 #define ARMG_CC_SHIFT_V 28 +#define ARMG_CC_SHIFT_Q 27 #define ARMG_CC_MASK_N (1 << ARMG_CC_SHIFT_N) #define ARMG_CC_MASK_Z (1 << ARMG_CC_SHIFT_Z) -#define ARMG_CC_MASK_V (1 << ARMG_CC_SHIFT_V) #define ARMG_CC_MASK_C (1 << ARMG_CC_SHIFT_C) +#define ARMG_CC_MASK_V (1 << ARMG_CC_SHIFT_V) +#define ARMG_CC_MASK_Q (1 << ARMG_CC_SHIFT_Q) -/* Flag thunk descriptors. A three-word thunk is used to record - details of the most recent flag-setting operation, so the flags can +/* Flag thunk descriptors. A four-word thunk is used to record + details of the most recent flag-setting operation, so NZCV can be computed later if needed. - The three words are: + The four words are: CC_OP, which describes the operation. - CC_DEP1 and CC_DEP2. These are arguments to the operation. - We want Memcheck to believe that the resulting flags are - data-dependent on both CC_DEP1 and CC_DEP2, hence the - name DEP. + CC_DEP1, CC_DEP2, CC_DEP3. These are arguments to the + operation. We want set up the mcx_masks in flag helper calls + involving these fields so that Memcheck "believes" that the + resulting flags are data-dependent on both CC_DEP1 and + CC_DEP2. Hence the name DEP. When building the thunk, it is always necessary to write words into - CC_DEP1 and CC_DEP2, even if those args are not used given the + CC_DEP1/2/3, even if those args are not used given the CC_OP field. This is important because otherwise Memcheck could give false positives as it does not understand the relationship - between the CC_OP field and CC_DEP1 and CC_DEP2, and so believes - that the definedness of the stored flags always depends on both - CC_DEP1 and CC_DEP2. + between the CC_OP field and CC_DEP1/2/3, and so believes + that the definedness of the stored flags always depends on + all 3 DEP values. A summary of the field usages is: - TODO: make this right - Operation DEP1 DEP2 NDEP - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + OP DEP1 DEP2 DEP3 + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + OP_COPY current NZCV unused unused + OP_ADD argL argR unused + OP_SUB argL argR unused + OP_ADC argL argR old_C + OP_SBB argL argR old_C + OP_LOGIC result shifter_co old_V + OP_MUL result unused old_C:old_V + OP_MULL resLO32 resHI32 old_C:old_V +*/ - and/or/xor result shift_carry_out - tst/teq/bic result shift_carry_out - mov/mvn result shift_carry_out +enum { + ARMG_CC_OP_COPY=0, /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0 + just copy DEP1 to output */ - add/cmn first arg second arg - sub/cmp first arg second arg + ARMG_CC_OP_ADD, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), + DEP3 = 0 */ - ... + ARMG_CC_OP_SUB, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), + DEP3 = 0 */ + ARMG_CC_OP_ADC, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op), + DEP3 = oldC (in LSB) */ - Therefore Memcheck will believe the following: + ARMG_CC_OP_SBB, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op), + DEP3 = oldC (in LSB) */ - * ... + ARMG_CC_OP_LOGIC, /* DEP1 = result, DEP2 = shifter_carry_out (in LSB), + DEP3 = old V flag (in LSB) */ + + ARMG_CC_OP_MUL, /* DEP1 = result, DEP2 = 0, DEP3 = oldC:old_V + (in bits 1:0) */ + + ARMG_CC_OP_MULL, /* DEP1 = resLO32, DEP2 = resHI32, DEP3 = oldC:old_V + (in bits 1:0) */ -*/ -enum { - ARMG_CC_OP_COPY, /* DEP1 = current flags, DEP2 = 0 */ - /* just copy DEP1 to output */ - - ARMG_CC_OP_LOGIC, /* DEP1 = result, DEP2 = shifter_carry_out */ - - ARMG_CC_OP_SUB, /* DEP1 = arg1(Rn), DEP2 = arg2 (shifter_op) */ - ARMG_CC_OP_ADD, /* DEP1 = arg1(Rn), DEP2 = arg2 (shifter_op) */ - ARMG_CC_OP_NUMBER }; -/* requires further study */ +/* XXXX because of the calling conventions for + armg_calculate_condition, all this OP values MUST be in the range + 0 .. 15 only (viz, 4-bits). */ @@ -175,33 +201,33 @@ enum { typedef enum { - ARMCondEQ = 0, /* equal : Z=1 */ - ARMCondNE = 1, /* not equal : Z=0 */ + ARMCondEQ = 0, /* equal : Z=1 */ + ARMCondNE = 1, /* not equal : Z=0 */ - ARMCondHS = 2, /* >=u (higher or same) : C=1 */ - ARMCondLO = 3, /* =u (higher or same) : C=1 */ + ARMCondLO = 3, /* u (higher) : C=1 && Z=0 */ - ARMCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */ + ARMCondHI = 8, /* >u (higher) : C=1 && Z=0 */ + ARMCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */ - ARMCondGE = 10, /* >=s (signed greater or equal) : N=V */ - ARMCondLT = 11, /* =s (signed greater or equal) : N=V */ + ARMCondLT = 11, /* s (signed greater) : Z=0 && N=V */ - ARMCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */ + ARMCondGT = 12, /* >s (signed greater) : Z=0 && N=V */ + ARMCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */ - ARMCondAL = 14, /* always (unconditional) : */ - ARMCondNV = 15 /* never (basically undefined meaning) : */ - /* NB: ARM have deprecated the use of the NV condition code - - you are now supposed to use MOV R0,R0 as a noop - rather than MOVNV R0,R0 as was previously recommended. - Future processors may have the NV condition code reused to do other things. */ + ARMCondAL = 14, /* always (unconditional) : 1 */ + ARMCondNV = 15 /* never (unconditional): : 0 */ + /* NB: ARM have deprecated the use of the NV condition code. + You are now supposed to use MOV R0,R0 as a noop rather than + MOVNV R0,R0 as was previously recommended. Future processors + may have the NV condition code reused to do other things. */ } ARMCondcode; diff --git a/VEX/priv/guest_arm_helpers.c b/VEX/priv/guest_arm_helpers.c index 3c4a156..f6689a0 100644 --- a/VEX/priv/guest_arm_helpers.c +++ b/VEX/priv/guest_arm_helpers.c @@ -1,63 +1,48 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_arm_helpers.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_arm_helpers.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. - - Neither the names of the U.S. Department of Energy nor the - University of California nor the names of its contributors may be - used to endorse or promote products derived from this software - without prior written permission. + The GNU General Public License is contained in the file COPYING. */ #include "libvex_basictypes.h" +#include "libvex_emwarn.h" #include "libvex_guest_arm.h" #include "libvex_ir.h" #include "libvex.h" #include "main_util.h" +#include "guest_generic_bb_to_IR.h" #include "guest_arm_defs.h" -/* This file contains helper functions for arm guest code. - Calls to these functions are generated by the back end. - These calls are of course in the host machine code and - this file will be compiled to host machine code, so that - all makes sense. +/* This file contains helper functions for arm guest code. Calls to + these functions are generated by the back end. These calls are of + course in the host machine code and this file will be compiled to + host machine code, so that all makes sense. Only change the signatures of these helper functions very carefully. If you change the signature here, you'll have to change @@ -67,244 +52,403 @@ - - - - -#define BORROWFROM() \ -{ \ -} -#define OVERFLOWFROM() \ -{ \ +/* generalised left-shifter */ +static inline UInt lshift ( UInt x, Int n ) +{ + if (n >= 0) + return x << n; + else + return x >> (-n); } -/*-------------------------------------------------------------*/ -/* - LOGIC: EOR, AND, TST, TEQ, MOV, ORR, MVN, BIC - ---------------- - n: Rd[31] - z: Rd==0 ? 1:0 - c: shifter_carry_out - v: unaffected -*/ -#define ACTIONS_LOGIC() \ -{ \ - { Int nf, zf, cf, vf; \ - Int oldV=0; /* CAB: vf unaffected: what todo? */ \ - nf = cc_dep1_formal & ARMG_CC_MASK_N; \ - zf = cc_dep1_formal == 0 ? 1 : 0; \ - cf = (cc_dep2_formal << ARMG_CC_SHIFT_C) & ARMG_CC_MASK_C; \ - vf = oldV & ARMG_CC_MASK_V; \ - return nf | zf | cf | vf; \ - } \ +/* CALLED FROM GENERATED CODE: CLEAN HELPER */ +/* Calculate NZCV from the supplied thunk components, in the positions + they appear in the CPSR, viz bits 31:28 for N Z C V respectively. + Returned bits 27:0 are zero. */ +UInt armg_calculate_flags_nzcv ( UInt cc_op, UInt cc_dep1, + UInt cc_dep2, UInt cc_dep3 ) +{ + switch (cc_op) { + case ARMG_CC_OP_COPY: + /* (nzcv, unused, unused) */ + return cc_dep1; + case ARMG_CC_OP_ADD: { + /* (argL, argR, unused) */ + UInt argL = cc_dep1; + UInt argR = cc_dep2; + UInt res = argL + argR; + UInt nf = lshift( res & (1<<31), ARMG_CC_SHIFT_N - 31 ); + UInt zf = lshift( res == 0, ARMG_CC_SHIFT_Z ); + // CF and VF need verification + UInt cf = lshift( res < argL, ARMG_CC_SHIFT_C ); + UInt vf = lshift( (res ^ argL) & (res ^ argR), + ARMG_CC_SHIFT_V + 1 - 32 ) + & ARMG_CC_MASK_V; + //vex_printf("%08x %08x -> n %x z %x c %x v %x\n", + // argL, argR, nf, zf, cf, vf); + return nf | zf | cf | vf; + } + case ARMG_CC_OP_SUB: { + /* (argL, argR, unused) */ + UInt argL = cc_dep1; + UInt argR = cc_dep2; + UInt res = argL - argR; + UInt nf = lshift( res & (1<<31), ARMG_CC_SHIFT_N - 31 ); + UInt zf = lshift( res == 0, ARMG_CC_SHIFT_Z ); + // XXX cf is inverted relative to normal sense + UInt cf = lshift( argL >= argR, ARMG_CC_SHIFT_C ); + UInt vf = lshift( (argL ^ argR) & (argL ^ res), + ARMG_CC_SHIFT_V + 1 - 32 ) + & ARMG_CC_MASK_V; + //vex_printf("%08x %08x -> n %x z %x c %x v %x\n", + // argL, argR, nf, zf, cf, vf); + return nf | zf | cf | vf; + } + case ARMG_CC_OP_ADC: { + /* (argL, argR, oldC) */ + UInt argL = cc_dep1; + UInt argR = cc_dep2; + UInt oldC = cc_dep3; + UInt res = (argL + argR) + oldC; + UInt nf = lshift( res & (1<<31), ARMG_CC_SHIFT_N - 31 ); + UInt zf = lshift( res == 0, ARMG_CC_SHIFT_Z ); + UInt cf = oldC ? lshift( res <= argL, ARMG_CC_SHIFT_C ) + : lshift( res < argL, ARMG_CC_SHIFT_C ); + UInt vf = lshift( (res ^ argL) & (res ^ argR), + ARMG_CC_SHIFT_V + 1 - 32 ) + & ARMG_CC_MASK_V; + //vex_printf("%08x %08x -> n %x z %x c %x v %x\n", + // argL, argR, nf, zf, cf, vf); + return nf | zf | cf | vf; + } + case ARMG_CC_OP_SBB: { + /* (argL, argR, oldC) */ + UInt argL = cc_dep1; + UInt argR = cc_dep2; + UInt oldC = cc_dep3; + UInt res = argL - argR - (oldC ^ 1); + UInt nf = lshift( res & (1<<31), ARMG_CC_SHIFT_N - 31 ); + UInt zf = lshift( res == 0, ARMG_CC_SHIFT_Z ); + UInt cf = oldC ? lshift( argL >= argR, ARMG_CC_SHIFT_C ) + : lshift( argL > argR, ARMG_CC_SHIFT_C ); + UInt vf = lshift( (argL ^ argR) & (argL ^ res), + ARMG_CC_SHIFT_V + 1 - 32 ) + & ARMG_CC_MASK_V; + //vex_printf("%08x %08x -> n %x z %x c %x v %x\n", + // argL, argR, nf, zf, cf, vf); + return nf | zf | cf | vf; + } + case ARMG_CC_OP_LOGIC: { + /* (res, shco, oldV) */ + UInt res = cc_dep1; + UInt shco = cc_dep2; + UInt oldV = cc_dep3; + UInt nf = lshift( res & (1<<31), ARMG_CC_SHIFT_N - 31 ); + UInt zf = lshift( res == 0, ARMG_CC_SHIFT_Z ); + UInt cf = lshift( shco & 1, ARMG_CC_SHIFT_C ); + UInt vf = lshift( oldV & 1, ARMG_CC_SHIFT_V ); + return nf | zf | cf | vf; + } + case ARMG_CC_OP_MUL: { + /* (res, unused, oldC:oldV) */ + UInt res = cc_dep1; + UInt oldC = (cc_dep3 >> 1) & 1; + UInt oldV = (cc_dep3 >> 0) & 1; + UInt nf = lshift( res & (1<<31), ARMG_CC_SHIFT_N - 31 ); + UInt zf = lshift( res == 0, ARMG_CC_SHIFT_Z ); + UInt cf = lshift( oldC & 1, ARMG_CC_SHIFT_C ); + UInt vf = lshift( oldV & 1, ARMG_CC_SHIFT_V ); + return nf | zf | cf | vf; + } + case ARMG_CC_OP_MULL: { + /* (resLo32, resHi32, oldC:oldV) */ + UInt resLo32 = cc_dep1; + UInt resHi32 = cc_dep2; + UInt oldC = (cc_dep3 >> 1) & 1; + UInt oldV = (cc_dep3 >> 0) & 1; + UInt nf = lshift( resHi32 & (1<<31), ARMG_CC_SHIFT_N - 31 ); + UInt zf = lshift( (resHi32|resLo32) == 0, ARMG_CC_SHIFT_Z ); + UInt cf = lshift( oldC & 1, ARMG_CC_SHIFT_C ); + UInt vf = lshift( oldV & 1, ARMG_CC_SHIFT_V ); + return nf | zf | cf | vf; + } + default: + /* shouldn't really make these calls from generated code */ + vex_printf("armg_calculate_flags_nzcv" + "( op=%u, dep1=0x%x, dep2=0x%x, dep3=0x%x )\n", + cc_op, cc_dep1, cc_dep2, cc_dep3 ); + vpanic("armg_calculate_flags_nzcv"); + } } -/*-------------------------------------------------------------*/ -/* - ADD: ADD, CMN - ---------------- - n: Rd[31] - z: Rd==0 ? 1:0 - c: CarryFrom(Rn + shifter_op) - v: OverflowFrom(Rn + shifter_op) -*/ -#define ACTIONS_ADD() \ -{ \ - { Int nf, zf, cf, vf; \ - Int argL, argR, res; \ - argL = cc_dep1_formal; \ - argR = cc_dep2_formal; \ - res = argL + argR; \ - nf = res & ARMG_CC_MASK_N; \ - zf = (res == 0) << ARMG_CC_SHIFT_Z; \ - cf = ((UInt)argL < (UInt)argR) << ARMG_CC_SHIFT_C; \ - vf = (((argL ^ argR ^ -1) & (argL ^ res)) >> \ - (32 - ARMG_CC_SHIFT_V)) & ARMG_CC_MASK_V; \ - return nf | zf | cf | vf; \ - } \ -} -/*-------------------------------------------------------------*/ -/* - SUB: SUB, CMP, RSB - ---------------- - n: Rd[31] - z: Rd==0 ? 1:0 - c: NOT BorrowFrom(Rn - shifter_op) - v: OverflowFrom(Rn - shifter_op) -*/ -// CAB: cf right? ARM ARM A4-99 -#define ACTIONS_SUB() \ -{ \ - { Int nf, zf, cf, vf; \ - Int argL, argR, res; \ - argL = cc_dep1_formal; \ - argR = cc_dep2_formal; \ - res = argL - argR; \ - nf = res & ARMG_CC_MASK_N; \ - zf = (res == 0) << ARMG_CC_SHIFT_Z; \ - cf = (~((UInt)argL < (UInt)argR) << \ - ARMG_CC_SHIFT_C) & ARMG_CC_MASK_C; \ - vf = (((argL ^ argR ^ -1) & (argL ^ res)) >> \ - (32 - ARMG_CC_SHIFT_V)) & ARMG_CC_MASK_V; \ - return nf | zf | cf | vf; \ - } \ +/* CALLED FROM GENERATED CODE: CLEAN HELPER */ +/* Calculate the C flag from the thunk components, in the lowest bit + of the word (bit 0). */ +UInt armg_calculate_flag_c ( UInt cc_op, UInt cc_dep1, + UInt cc_dep2, UInt cc_dep3 ) +{ + UInt r = armg_calculate_flags_nzcv(cc_op, cc_dep1, cc_dep2, cc_dep3); + return (r >> ARMG_CC_SHIFT_C) & 1; } -/*-------------------------------------------------------------*/ -/* - ADC - ---------------- - n: Rd[31] - z: Rd==0 ? 1:0 - c: CarryFrom(Rn + shifter_op + C Flag) - v: OverflowFrom(Rn + shifter_op + C Flag) -*/ - -/*-------------------------------------------------------------*/ -/* - RSC - ---------------- - n: Rd[31] - z: Rd==0 ? 1:0 - c: NOT BorrowFrom(shifter_op - Rn - NOT(C Flag)) - v: OverflowFrom(shifter_op - Rn - NOT(C Flag)) -*/ - -/*-------------------------------------------------------------*/ -/* - SBC - ---------------- - n: Rd[31] - z: Rd==0 ? 1:0 - c: NOT BorrowFrom(Rn - shifter_op - NOT(C Flag)) - v: OverflowFrom(Rn - shifter_op - NOT(C Flag)) -*/ - - - - - - - - - /* CALLED FROM GENERATED CODE: CLEAN HELPER */ -/* Calculate all the 4 flags from the supplied thunk parameters. */ -UInt armg_calculate_flags_all ( UInt cc_op, - UInt cc_dep1_formal, - UInt cc_dep2_formal ) +/* Calculate the V flag from the thunk components, in the lowest bit + of the word (bit 0). */ +UInt armg_calculate_flag_v ( UInt cc_op, UInt cc_dep1, + UInt cc_dep2, UInt cc_dep3 ) { - switch (cc_op) { - case ARMG_CC_OP_LOGIC: ACTIONS_LOGIC(); - case ARMG_CC_OP_ADD: ACTIONS_ADD(); - case ARMG_CC_OP_SUB: ACTIONS_SUB(); - - default: - /* shouldn't really make these calls from generated code */ - vex_printf("armg_calculate_flags_all(ARM)( %u, 0x%x, 0x%x )\n", - cc_op, cc_dep1_formal, cc_dep2_formal ); - vpanic("armg_calculate_flags_all(ARM)"); - } + UInt r = armg_calculate_flags_nzcv(cc_op, cc_dep1, cc_dep2, cc_dep3); + return (r >> ARMG_CC_SHIFT_V) & 1; } /* CALLED FROM GENERATED CODE: CLEAN HELPER */ -/* Calculate just the carry flag from the supplied thunk parameters. */ -UInt armg_calculate_flags_c ( UInt cc_op, - UInt cc_dep1, - UInt cc_dep2 ) +/* Calculate the QC flag from the arguments, in the lowest bit + of the word (bit 0). Urr, having this out of line is bizarre. + Push back inline. */ +UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2, + UInt resR1, UInt resR2 ) { - /* Fast-case some common ones. */ - switch (cc_op) { - default: - break; - } - return armg_calculate_flags_all(cc_op,cc_dep1,cc_dep2) & ARMG_CC_MASK_C; + if (resL1 != resR1 || resL2 != resR2) + return 1; + else + return 0; } - - /* CALLED FROM GENERATED CODE: CLEAN HELPER */ -/* returns 1 or 0 */ -/*static*/ -UInt armg_calculate_condition ( UInt/*ARMCondcode*/ cond, - UInt cc_op, - UInt cc_dep1, - UInt cc_dep2 ) +/* Calculate the specified condition from the thunk components, in the + lowest bit of the word (bit 0). */ +extern +UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */, + UInt cc_dep1, + UInt cc_dep2, UInt cc_dep3 ) { - UInt nf,zf,vf,cf; - UInt inv = cond & 1; + UInt cond = cond_n_op >> 4; + UInt cc_op = cond_n_op & 0xF; + UInt nf, zf, vf, cf, nzcv, inv; + // vex_printf("XXXXXXXX %x %x %x %x\n", + // cond_n_op, cc_dep1, cc_dep2, cc_dep3); + + // skip flags computation in this case + if (cond == ARMCondAL) return 1; - UInt nzvc = armg_calculate_flags_all(cc_op, cc_dep1, cc_dep2); + inv = cond & 1; + nzcv = armg_calculate_flags_nzcv(cc_op, cc_dep1, cc_dep2, cc_dep3); switch (cond) { - case ARMCondEQ: // Z=1 => z - case ARMCondNE: // Z=0 - zf = nzvc >> ARMG_CC_SHIFT_Z; - return 1 & (inv ^ zf); - - case ARMCondHS: // C=1 => c - case ARMCondLO: // C=0 - cf = nzvc >> ARMG_CC_SHIFT_C; - return 1 & (inv ^ cf); - - case ARMCondMI: // N=1 => n - case ARMCondPL: // N=0 - nf = nzvc >> ARMG_CC_SHIFT_N; - return 1 & (inv ^ nf); - - case ARMCondVS: // V=1 => v - case ARMCondVC: // V=0 - vf = nzvc >> ARMG_CC_SHIFT_V; - return 1 & (inv ^ vf); - - case ARMCondHI: // C=1 && Z=0 => c & ~z - case ARMCondLS: // C=0 || Z=1 - cf = nzvc >> ARMG_CC_SHIFT_C; - zf = nzvc >> ARMG_CC_SHIFT_Z; - return 1 & (inv ^ (cf & ~zf)); - - case ARMCondGE: // N=V => ~(n^v) - case ARMCondLT: // N!=V - nf = nzvc >> ARMG_CC_SHIFT_N; - vf = nzvc >> ARMG_CC_SHIFT_V; - return 1 & (inv ^ ~(nf ^ vf)); - - case ARMCondGT: // Z=0 && N=V => (~z & ~(n^v) => ~(z | (n^v) - case ARMCondLE: // Z=1 || N!=V - nf = nzvc >> ARMG_CC_SHIFT_N; - vf = nzvc >> ARMG_CC_SHIFT_V; - zf = nzvc >> ARMG_CC_SHIFT_Z; - return 1 & (inv ^ ~(zf | (nf ^ vf))); - - case ARMCondAL: // should never get here: Always => no flags to calc - case ARMCondNV: // should never get here: Illegal instr - default: - /* shouldn't really make these calls from generated code */ - vex_printf("armg_calculate_condition(ARM)( %u, %u, 0x%x, 0x%x )\n", - cond, cc_op, cc_dep1, cc_dep2 ); - vpanic("armg_calculate_condition(ARM)"); + case ARMCondEQ: // Z=1 => z + case ARMCondNE: // Z=0 + zf = nzcv >> ARMG_CC_SHIFT_Z; + return 1 & (inv ^ zf); + + case ARMCondHS: // C=1 => c + case ARMCondLO: // C=0 + cf = nzcv >> ARMG_CC_SHIFT_C; + return 1 & (inv ^ cf); + + case ARMCondMI: // N=1 => n + case ARMCondPL: // N=0 + nf = nzcv >> ARMG_CC_SHIFT_N; + return 1 & (inv ^ nf); + + case ARMCondVS: // V=1 => v + case ARMCondVC: // V=0 + vf = nzcv >> ARMG_CC_SHIFT_V; + return 1 & (inv ^ vf); + + case ARMCondHI: // C=1 && Z=0 => c & ~z + case ARMCondLS: // C=0 || Z=1 + cf = nzcv >> ARMG_CC_SHIFT_C; + zf = nzcv >> ARMG_CC_SHIFT_Z; + return 1 & (inv ^ (cf & ~zf)); + + case ARMCondGE: // N=V => ~(n^v) + case ARMCondLT: // N!=V + nf = nzcv >> ARMG_CC_SHIFT_N; + vf = nzcv >> ARMG_CC_SHIFT_V; + return 1 & (inv ^ ~(nf ^ vf)); + + case ARMCondGT: // Z=0 && N=V => ~z & ~(n^v) => ~(z | (n^v)) + case ARMCondLE: // Z=1 || N!=V + nf = nzcv >> ARMG_CC_SHIFT_N; + vf = nzcv >> ARMG_CC_SHIFT_V; + zf = nzcv >> ARMG_CC_SHIFT_Z; + return 1 & (inv ^ ~(zf | (nf ^ vf))); + + case ARMCondAL: // handled above + case ARMCondNV: // should never get here: Illegal instr + default: + /* shouldn't really make these calls from generated code */ + vex_printf("armg_calculate_condition(ARM)" + "( %u, %u, 0x%x, 0x%x, 0x%x )\n", + cond, cc_op, cc_dep1, cc_dep2, cc_dep3 ); + vpanic("armg_calculate_condition(ARM)"); } } +/*---------------------------------------------------------------*/ +/*--- Flag-helpers translation-time function specialisers. ---*/ +/*--- These help iropt specialise calls the above run-time ---*/ +/*--- flags functions. ---*/ +/*---------------------------------------------------------------*/ + /* Used by the optimiser to try specialisations. Returns an equivalent expression, or NULL if none. */ -#if 0 -/* temporarily unused */ static Bool isU32 ( IRExpr* e, UInt n ) { - return (e->tag == Iex_Const - && e->Iex.Const.con->tag == Ico_U32 - && e->Iex.Const.con->Ico.U32 == n); + return + toBool( e->tag == Iex_Const + && e->Iex.Const.con->tag == Ico_U32 + && e->Iex.Const.con->Ico.U32 == n ); } -#endif -IRExpr* guest_arm_spechelper ( HChar* function_name, - IRExpr** args ) + +IRExpr* guest_arm_spechelper ( HChar* function_name, + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ) { +# define unop(_op,_a1) IRExpr_Unop((_op),(_a1)) +# define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2)) +# define mkU32(_n) IRExpr_Const(IRConst_U32(_n)) +# define mkU8(_n) IRExpr_Const(IRConst_U8(_n)) + + Int i, arity = 0; + for (i = 0; args[i]; i++) + arity++; +# if 0 + vex_printf("spec request:\n"); + vex_printf(" %s ", function_name); + for (i = 0; i < arity; i++) { + vex_printf(" "); + ppIRExpr(args[i]); + } + vex_printf("\n"); +# endif + + /* --------- specialising "armg_calculate_condition" --------- */ + + if (vex_streq(function_name, "armg_calculate_condition")) { + /* specialise calls to above "armg_calculate condition" function */ + IRExpr *cond_n_op, *cc_dep1, *cc_dep2, *cc_dep3; + vassert(arity == 4); + cond_n_op = args[0]; /* ARMCondcode << 4 | ARMG_CC_OP_* */ + cc_dep1 = args[1]; + cc_dep2 = args[2]; + cc_dep3 = args[3]; + + /*---------------- SUB ----------------*/ + + if (isU32(cond_n_op, (ARMCondEQ << 4) | ARMG_CC_OP_SUB)) { + /* EQ after SUB --> test argL == argR */ + return unop(Iop_1Uto32, + binop(Iop_CmpEQ32, cc_dep1, cc_dep2)); + } + if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_SUB)) { + /* NE after SUB --> test argL != argR */ + return unop(Iop_1Uto32, + binop(Iop_CmpNE32, cc_dep1, cc_dep2)); + } + + if (isU32(cond_n_op, (ARMCondLE << 4) | ARMG_CC_OP_SUB)) { + /* LE after SUB --> test argL <=s argR */ + return unop(Iop_1Uto32, + binop(Iop_CmpLE32S, cc_dep1, cc_dep2)); + } + + if (isU32(cond_n_op, (ARMCondLT << 4) | ARMG_CC_OP_SUB)) { + /* LT after SUB --> test argL test argL >=s argR + --> test argR <=s argL */ + return unop(Iop_1Uto32, + binop(Iop_CmpLE32S, cc_dep2, cc_dep1)); + } + + if (isU32(cond_n_op, (ARMCondHS << 4) | ARMG_CC_OP_SUB)) { + /* HS after SUB --> test argL >=u argR + --> test argR <=u argL */ + return unop(Iop_1Uto32, + binop(Iop_CmpLE32U, cc_dep2, cc_dep1)); + } + + if (isU32(cond_n_op, (ARMCondLS << 4) | ARMG_CC_OP_SUB)) { + /* LS after SUB --> test argL <=u argR */ + return unop(Iop_1Uto32, + binop(Iop_CmpLE32U, cc_dep1, cc_dep2)); + } + + /*---------------- LOGIC ----------------*/ + if (isU32(cond_n_op, (ARMCondEQ << 4) | ARMG_CC_OP_LOGIC)) { + /* EQ after LOGIC --> test res == 0 */ + return unop(Iop_1Uto32, + binop(Iop_CmpEQ32, cc_dep1, mkU32(0))); + } + if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_LOGIC)) { + /* NE after LOGIC --> test res != 0 */ + return unop(Iop_1Uto32, + binop(Iop_CmpNE32, cc_dep1, mkU32(0))); + } + + /*----------------- AL -----------------*/ + /* A critically important case for Thumb code. + + What we're trying to spot is the case where cond_n_op is an + expression of the form Or32(..., 0xE0) since that means the + caller is asking for CondAL and we can simply return 1 + without caring what the ... part is. This is a potentially + dodgy kludge in that it assumes that the ... part has zeroes + in bits 7:4, so that the result of the Or32 is guaranteed to + be 0xE in bits 7:4. Given that the places where this first + arg are constructed (in guest_arm_toIR.c) are very + constrained, we can get away with this. To make this + guaranteed safe would require to have a new primop, Slice44 + or some such, thusly + + Slice44(arg1, arg2) = 0--(24)--0 arg1[7:4] arg2[3:0] + + and we would then look for Slice44(0xE0, ...) + which would give the required safety property. + + It would be infeasibly expensive to scan backwards through + the entire block looking for an assignment to the temp, so + just look at the previous 16 statements. That should find it + if it is an interesting case, as a result of how the + boilerplate guff at the start of each Thumb insn translation + is made. + */ + if (cond_n_op->tag == Iex_RdTmp) { + Int j; + IRTemp look_for = cond_n_op->Iex.RdTmp.tmp; + Int limit = n_precedingStmts - 16; + if (limit < 0) limit = 0; + if (0) vex_printf("scanning %d .. %d\n", n_precedingStmts-1, limit); + for (j = n_precedingStmts - 1; j >= limit; j--) { + IRStmt* st = precedingStmts[j]; + if (st->tag == Ist_WrTmp + && st->Ist.WrTmp.tmp == look_for + && st->Ist.WrTmp.data->tag == Iex_Binop + && st->Ist.WrTmp.data->Iex.Binop.op == Iop_Or32 + && isU32(st->Ist.WrTmp.data->Iex.Binop.arg2, (ARMCondAL << 4))) + return mkU32(1); + } + /* Didn't find any useful binding to the first arg + in the previous 16 stmts. */ + } + } + +# undef unop +# undef binop +# undef mkU32 +# undef mkU8 + return NULL; } @@ -327,21 +471,46 @@ void LibVEX_GuestARM_put_flags ( UInt flags_native, vex_state->guest_CC_OP = ARMG_CC_OP_COPY; vex_state->guest_CC_DEP1 = flags_native; vex_state->guest_CC_DEP2 = 0; + vex_state->guest_CC_NDEP = 0; } #endif /* VISIBLE TO LIBVEX CLIENT */ -UInt LibVEX_GuestARM_get_flags ( /*IN*/VexGuestARMState* vex_state ) +UInt LibVEX_GuestARM_get_cpsr ( /*IN*/VexGuestARMState* vex_state ) { - UInt flags; - vassert(0); // FIXME - - flags = armg_calculate_flags_all( - vex_state->guest_CC_OP, - vex_state->guest_CC_DEP1, - vex_state->guest_CC_DEP2 - ); - return flags; + UInt cpsr = 0; + // NZCV + cpsr |= armg_calculate_flags_nzcv( + vex_state->guest_CC_OP, + vex_state->guest_CC_DEP1, + vex_state->guest_CC_DEP2, + vex_state->guest_CC_NDEP + ); + vassert(0 == (cpsr & 0x0FFFFFFF)); + // Q + if (vex_state->guest_QFLAG32 > 0) + cpsr |= (1 << 27); + // GE + if (vex_state->guest_GEFLAG0 > 0) + cpsr |= (1 << 16); + if (vex_state->guest_GEFLAG1 > 0) + cpsr |= (1 << 17); + if (vex_state->guest_GEFLAG2 > 0) + cpsr |= (1 << 18); + if (vex_state->guest_GEFLAG3 > 0) + cpsr |= (1 << 19); + // M + cpsr |= (1 << 4); // 0b10000 means user-mode + // J,T J (bit 24) is zero by initialisation above + // T we copy from R15T[0] + if (vex_state->guest_R15T & 1) + cpsr |= (1 << 5); + // ITSTATE we punt on for the time being. Could compute it + // if needed though. + // E, endianness, 0 (littleendian) from initialisation above + // A,I,F disable some async exceptions. Not sure about these. + // Leave as zero for the time being. + return cpsr; } /* VISIBLE TO LIBVEX CLIENT */ @@ -362,19 +531,70 @@ void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state ) vex_state->guest_R12 = 0; vex_state->guest_R13 = 0; vex_state->guest_R14 = 0; - vex_state->guest_R15 = 0; + vex_state->guest_R15T = 0; /* NB: implies ARM mode */ - // CAB: Want this? - //vex_state->guest_SYSCALLNO = 0; - - vex_state->guest_CC_OP = 0;// CAB: ? ARMG_CC_OP_COPY; + vex_state->guest_CC_OP = ARMG_CC_OP_COPY; vex_state->guest_CC_DEP1 = 0; vex_state->guest_CC_DEP2 = 0; - - // CAB: Want this? - //vex_state->guest_EMWARN = 0; - - vex_state->guest_SYSCALLNO = 0; + vex_state->guest_CC_NDEP = 0; + vex_state->guest_QFLAG32 = 0; + vex_state->guest_GEFLAG0 = 0; + vex_state->guest_GEFLAG1 = 0; + vex_state->guest_GEFLAG2 = 0; + vex_state->guest_GEFLAG3 = 0; + + vex_state->guest_EMWARN = 0; + vex_state->guest_TISTART = 0; + vex_state->guest_TILEN = 0; + vex_state->guest_NRADDR = 0; + vex_state->guest_IP_AT_SYSCALL = 0; + + vex_state->guest_D0 = 0; + vex_state->guest_D1 = 0; + vex_state->guest_D2 = 0; + vex_state->guest_D3 = 0; + vex_state->guest_D4 = 0; + vex_state->guest_D5 = 0; + vex_state->guest_D6 = 0; + vex_state->guest_D7 = 0; + vex_state->guest_D8 = 0; + vex_state->guest_D9 = 0; + vex_state->guest_D10 = 0; + vex_state->guest_D11 = 0; + vex_state->guest_D12 = 0; + vex_state->guest_D13 = 0; + vex_state->guest_D14 = 0; + vex_state->guest_D15 = 0; + vex_state->guest_D16 = 0; + vex_state->guest_D17 = 0; + vex_state->guest_D18 = 0; + vex_state->guest_D19 = 0; + vex_state->guest_D20 = 0; + vex_state->guest_D21 = 0; + vex_state->guest_D22 = 0; + vex_state->guest_D23 = 0; + vex_state->guest_D24 = 0; + vex_state->guest_D25 = 0; + vex_state->guest_D26 = 0; + vex_state->guest_D27 = 0; + vex_state->guest_D28 = 0; + vex_state->guest_D29 = 0; + vex_state->guest_D30 = 0; + vex_state->guest_D31 = 0; + + /* ARM encoded; zero is the default as it happens (result flags + (NZCV) cleared, FZ disabled, round to nearest, non-vector mode, + all exns masked, all exn sticky bits cleared). */ + vex_state->guest_FPSCR = 0; + + vex_state->guest_TPIDRURO = 0; + + /* Not in a Thumb IT block. */ + vex_state->guest_ITSTATE = 0; + + vex_state->padding1 = 0; + vex_state->padding2 = 0; + vex_state->padding3 = 0; } @@ -387,32 +607,51 @@ void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state ) .. maxoff requires precise memory exceptions. If in doubt return True (but this is generates significantly slower code). - We enforce precise exns for guest %ESP and %EIP only. + We enforce precise exns for guest R13(sp), R15T(pc). */ Bool guest_arm_state_requires_precise_mem_exns ( Int minoff, Int maxoff) { - return True; // FIXME (also comment above) -#if 0 - Int esp_min = offsetof(VexGuestX86State, guest_ESP); - Int esp_max = esp_min + 4 - 1; - Int eip_min = offsetof(VexGuestX86State, guest_EIP); - Int eip_max = eip_min + 4 - 1; + Int sp_min = offsetof(VexGuestARMState, guest_R13); + Int sp_max = sp_min + 4 - 1; + Int pc_min = offsetof(VexGuestARMState, guest_R15T); + Int pc_max = pc_min + 4 - 1; + + if (maxoff < sp_min || minoff > sp_max) { + /* no overlap with sp */ + } else { + return True; + } - if (maxoff < esp_min || minoff > esp_max) { - /* no overlap with esp */ + if (maxoff < pc_min || minoff > pc_max) { + /* no overlap with pc */ } else { return True; } - if (maxoff < eip_min || minoff > eip_max) { - /* no overlap with eip */ + /* We appear to need precise updates of R11 in order to get proper + stacktraces from non-optimised code. */ + Int r11_min = offsetof(VexGuestARMState, guest_R11); + Int r11_max = r11_min + 4 - 1; + + if (maxoff < r11_min || minoff > r11_max) { + /* no overlap with r11 */ + } else { + return True; + } + + /* Ditto R7, particularly needed for proper stacktraces in Thumb + code. */ + Int r7_min = offsetof(VexGuestARMState, guest_R7); + Int r7_max = r7_min + 4 - 1; + + if (maxoff < r7_min || minoff > r7_max) { + /* no overlap with r7 */ } else { return True; } return False; -#endif } @@ -432,19 +671,27 @@ VexGuestLayout .sizeof_SP = 4, /* Describe the instruction pointer. */ - .offset_IP = offsetof(VexGuestARMState,guest_R15), + .offset_IP = offsetof(VexGuestARMState,guest_R15T), .sizeof_IP = 4, /* Describe any sections to be regarded by Memcheck as 'always-defined'. */ - .n_alwaysDefd = 2, + .n_alwaysDefd = 10, + /* flags thunk: OP is always defd, whereas DEP1 and DEP2 have to be tracked. See detailed comment in gdefs.h on meaning of thunk fields. */ - - .alwaysDefd - = { /* 0 */ ALWAYSDEFD(guest_CC_OP), - /* 1 */ ALWAYSDEFD(guest_SYSCALLNO) + .alwaysDefd + = { /* 0 */ ALWAYSDEFD(guest_R15T), + /* 1 */ ALWAYSDEFD(guest_CC_OP), + /* 2 */ ALWAYSDEFD(guest_CC_NDEP), + /* 3 */ ALWAYSDEFD(guest_EMWARN), + /* 4 */ ALWAYSDEFD(guest_TISTART), + /* 5 */ ALWAYSDEFD(guest_TILEN), + /* 6 */ ALWAYSDEFD(guest_NRADDR), + /* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL), + /* 8 */ ALWAYSDEFD(guest_TPIDRURO), + /* 9 */ ALWAYSDEFD(guest_ITSTATE) } }; diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index dd36a00..c1f9211 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -1,50 +1,104 @@ /*--------------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_arm_toIR.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_arm_toIR.c ---*/ /*--------------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net + + NEON support is + Copyright (C) 2010-2010 Samsung Electronics + contributed by Dmitry Zhurikhin + and Kirill Batuzov + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. + + The GNU General Public License is contained in the file COPYING. +*/ - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. +/* XXXX thumb to check: + that all cases where putIRegT writes r15, we generate a jump. - This library is made available under a dual licensing scheme. + All uses of newTemp assign to an IRTemp and not a UInt - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA - 02110-1301, USA. + For all thumb loads and stores, including VFP ones, new-ITSTATE is + backed out before the memory op, and restored afterwards. This + needs to happen even after we go uncond. (and for sure it doesn't + happen for VFP loads/stores right now). + + VFP on thumb: check that we exclude all r13/r15 cases that we + should. + + XXXX thumb to do: improve the ITSTATE-zeroing optimisation by + taking into account the number of insns guarded by an IT. + + remove the nasty hack, in the spechelper, of looking for Or32(..., + 0xE0) in as the first arg to armg_calculate_condition, and instead + use Slice44 as specified in comments in the spechelper. + + add specialisations for armg_calculate_flag_c and _v, as they + are moderately often needed in Thumb code. + + Correctness: ITSTATE handling in Thumb SVCs is wrong. + + Correctness (obscure): in m_transtab, when invalidating code + address ranges, invalidate up to 18 bytes after the end of the + range. This is because the ITSTATE optimisation at the top of + _THUMB_WRK below analyses up to 18 bytes before the start of any + given instruction, and so might depend on the invalidated area. +*/ + +/* Limitations, etc + + - pretty dodgy exception semantics for {LD,ST}Mxx, no doubt + + - SWP: the restart jump back is Ijk_Boring; it should be + Ijk_NoRedir but that's expensive. See comments on casLE() in + guest_x86_toIR.c. +*/ + +/* "Special" instructions. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. - - Neither the names of the U.S. Department of Energy nor the - University of California nor the names of its contributors may be - used to endorse or promote products derived from this software - without prior written permission. + This instruction decoder can decode four special instructions + which mean nothing natively (are no-ops as far as regs/mem are + concerned) but have meaning for supporting Valgrind. A special + instruction is flagged by a 16-byte preamble: + + E1A0C1EC E1A0C6EC E1A0CEEC E1A0C9EC + (mov r12, r12, ROR #3; mov r12, r12, ROR #13; + mov r12, r12, ROR #29; mov r12, r12, ROR #19) + + Following that, one of the following 3 are allowed + (standard interpretation in parentheses): + + E18AA00A (orr r10,r10,r10) R3 = client_request ( R4 ) + E18BB00B (orr r11,r11,r11) R3 = guest_NRADDR + E18CC00C (orr r12,r12,r12) branch-and-link-to-noredir R4 + + Any other bytes following the 16-byte preamble are illegal and + constitute a failure in instruction decoding. This all assumes + that the preamble will never occur except in specific code + fragments designed for Valgrind to catch. */ -/* Translates ARM(v4) code to IR. */ +/* Translates ARM(v5) code to IR. */ #include "libvex_basictypes.h" #include "libvex_ir.h" @@ -53,6 +107,7 @@ #include "main_util.h" #include "main_globals.h" +#include "guest_generic_bb_to_IR.h" #include "guest_arm_defs.h" @@ -60,26 +115,51 @@ /*--- Globals ---*/ /*------------------------------------------------------------*/ -/* These are set at the start of the translation of a BB, so that we - don't have to pass them around endlessly. CONST means does not - change during translation of a bb. +/* These are set at the start of the translation of a instruction, so + that we don't have to pass them around endlessly. CONST means does + not change during translation of the instruction. */ -/* We need to know this to do sub-register accesses correctly. */ -/* CONST */ +/* CONST: is the host bigendian? This has to do with float vs double + register accesses on VFP, but it's complex and not properly thought + out. */ static Bool host_is_bigendian; -/* Pointer to the guest code area. */ -/* CONST */ -static UChar* guest_code; +/* CONST: The guest address for the instruction currently being + translated. This is the real, "decoded" address (not subject + to the CPSR.T kludge). */ +static Addr32 guest_R15_curr_instr_notENC; -/* The guest address corresponding to guest_code[0]. */ -/* CONST */ -static Addr32 guest_pc_bbstart; +/* CONST, FOR ASSERTIONS ONLY. Indicates whether currently processed + insn is Thumb (True) or ARM (False). */ +static Bool __curr_is_Thumb; -/* The IRSB* into which we're generating code. */ +/* MOD: The IRSB* into which we're generating code. */ static IRSB* irsb; +/* These are to do with handling writes to r15. They are initially + set at the start of disInstr_ARM_WRK to indicate no update, + possibly updated during the routine, and examined again at the end. + If they have been set to indicate a r15 update then a jump is + generated. Note, "explicit" jumps (b, bx, etc) are generated + directly, not using this mechanism -- this is intended to handle + the implicit-style jumps resulting from (eg) assigning to r15 as + the result of insns we wouldn't normally consider branchy. */ + +/* MOD. Initially False; set to True iff abovementioned handling is + required. */ +static Bool r15written; + +/* MOD. Initially IRTemp_INVALID. If the r15 branch to be generated + is conditional, this holds the gating IRTemp :: Ity_I32. If the + branch to be generated is unconditional, this remains + IRTemp_INVALID. */ +static IRTemp r15guard; /* :: Ity_I32, 0 or 1 */ + +/* MOD. Initially Ijk_Boring. If an r15 branch is to be generated, + this holds the jump kind. */ +static IRTemp r15kind; + /*------------------------------------------------------------*/ /*--- Debugging output ---*/ @@ -93,2100 +173,17798 @@ static IRSB* irsb; if (vex_traceflags & VEX_TRACE_FE) \ vex_sprintf(buf, format, ## args) +#define ASSERT_IS_THUMB \ + do { vassert(__curr_is_Thumb); } while (0) +#define ASSERT_IS_ARM \ + do { vassert(! __curr_is_Thumb); } while (0) /*------------------------------------------------------------*/ -/*--- Offsets of various parts of the arm guest state. ---*/ +/*--- Helper bits and pieces for deconstructing the ---*/ +/*--- arm insn stream. ---*/ /*------------------------------------------------------------*/ -#define OFFB_R0 offsetof(VexGuestARMState,guest_R0) -#define OFFB_R1 offsetof(VexGuestARMState,guest_R1) -#define OFFB_R2 offsetof(VexGuestARMState,guest_R2) -#define OFFB_R3 offsetof(VexGuestARMState,guest_R3) -#define OFFB_R4 offsetof(VexGuestARMState,guest_R4) -#define OFFB_R5 offsetof(VexGuestARMState,guest_R5) -#define OFFB_R6 offsetof(VexGuestARMState,guest_R6) -#define OFFB_R7 offsetof(VexGuestARMState,guest_R7) -#define OFFB_R8 offsetof(VexGuestARMState,guest_R8) -#define OFFB_R9 offsetof(VexGuestARMState,guest_R9) -#define OFFB_R10 offsetof(VexGuestARMState,guest_R10) -#define OFFB_R11 offsetof(VexGuestARMState,guest_R11) -#define OFFB_R12 offsetof(VexGuestARMState,guest_R12) -#define OFFB_R13 offsetof(VexGuestARMState,guest_R13) -#define OFFB_R14 offsetof(VexGuestARMState,guest_R14) -#define OFFB_R15 offsetof(VexGuestARMState,guest_R15) - -// CAB: ? guest_SYSCALLNO; - -#define OFFB_CC_OP offsetof(VexGuestARMState,guest_CC_OP) -#define OFFB_CC_DEP1 offsetof(VexGuestARMState,guest_CC_DEP1) -#define OFFB_CC_DEP2 offsetof(VexGuestARMState,guest_CC_DEP2) +/* Do a little-endian load of a 32-bit word, regardless of the + endianness of the underlying host. */ +static inline UInt getUIntLittleEndianly ( UChar* p ) +{ + UInt w = 0; + w = (w << 8) | p[3]; + w = (w << 8) | p[2]; + w = (w << 8) | p[1]; + w = (w << 8) | p[0]; + return w; +} -// CAB: ? guest_EMWARN; +/* Do a little-endian load of a 16-bit word, regardless of the + endianness of the underlying host. */ +static inline UShort getUShortLittleEndianly ( UChar* p ) +{ + UShort w = 0; + w = (w << 8) | p[1]; + w = (w << 8) | p[0]; + return w; +} +static UInt ROR32 ( UInt x, UInt sh ) { + vassert(sh >= 0 && sh < 32); + if (sh == 0) + return x; + else + return (x << (32-sh)) | (x >> sh); +} -/*------------------------------------------------------------*/ -/*--- Disassemble an entire basic block ---*/ -/*------------------------------------------------------------*/ +static Int popcount32 ( UInt x ) +{ + Int res = 0, i; + for (i = 0; i < 32; i++) { + res += (x & 1); + x >>= 1; + } + return res; +} -/* The results of disassembling an instruction. There are three - possible outcomes. For Dis_Resteer, the disassembler _must_ - continue at the specified address. For Dis_StopHere, the - disassembler _must_ terminate the BB. For Dis_Continue, we may at - our option either disassemble the next insn, or terminate the BB; - but in the latter case we must set the bb's ->next field to point - to the next instruction. */ +static UInt setbit32 ( UInt x, Int ix, UInt b ) +{ + UInt mask = 1 << ix; + x &= ~mask; + x |= ((b << ix) & mask); + return x; +} -typedef - enum { - Dis_StopHere, /* this insn terminates the BB; we must stop. */ - Dis_Continue, /* we can optionally continue into the next insn */ - Dis_Resteer /* followed a branch; continue at the spec'd addr */ - } - DisResult; +#define BITS2(_b1,_b0) \ + (((_b1) << 1) | (_b0)) +#define BITS3(_b2,_b1,_b0) \ + (((_b2) << 2) | ((_b1) << 1) | (_b0)) -/* forward decls .. */ -static IRExpr* mkU32 ( UInt i ); -static void stmt ( IRStmt* st ); +#define BITS4(_b3,_b2,_b1,_b0) \ + (((_b3) << 3) | ((_b2) << 2) | ((_b1) << 1) | (_b0)) +#define BITS8(_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ + ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \ + | BITS4((_b3),(_b2),(_b1),(_b0))) -/* disInstr disassembles an instruction located at &guest_code[delta], - and sets *size to its size. If the returned value is Dis_Resteer, - the next guest address is assigned to *whereNext. disInstr is not - permitted to return Dis_Resteer if either (1) resteerOK is False, - or (2) resteerOkFn, when applied to the address which it wishes to - resteer into, returns False. */ - -static DisResult disInstr ( /*IN*/ Bool resteerOK, - /*IN*/ Bool (*resteerOkFn) ( Addr64 ), - /*IN*/ Long delta, - /*OUT*/ Int* size, - /*OUT*/ Addr64* whereNext ); +#define BITS5(_b4,_b3,_b2,_b1,_b0) \ + (BITS8(0,0,0,(_b4),(_b3),(_b2),(_b1),(_b0))) +#define BITS6(_b5,_b4,_b3,_b2,_b1,_b0) \ + (BITS8(0,0,(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) +#define BITS7(_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ + (BITS8(0,(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) +#define BITS9(_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ + (((_b8) << 8) \ + | BITS8((_b7),(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -/* This is the main (only, in fact) entry point for this module. */ +#define BITS10(_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ + (((_b9) << 9) | ((_b8) << 8) \ + | BITS8((_b7),(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -/* Disassemble a complete basic block, starting at guest_pc_start, and - dumping the IR into global irsb. Returns the size, in bytes, of - the basic block. -*/ -IRSB* bbToIR_ARM ( UChar* armCode, - Addr64 guest_pc_start, - VexGuestExtents* vge, - Bool (*byte_accessible)(Addr64), - Bool (*chase_into_ok)(Addr64), - Bool host_bigendian, - VexArchInfo* archinfo_guest ) -{ - Long delta; - Int i, n_instrs, size, first_stmt_idx; - Addr64 guest_next; - Bool resteerOK; - DisResult dres; - static Int n_resteers = 0; - Int d_resteers = 0; - - /* check sanity .. */ - vassert(vex_control.guest_max_insns >= 1); - vassert(vex_control.guest_max_insns < 500); - vassert(vex_control.guest_chase_thresh >= 0); - vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns); - - vassert(archinfo_guest->hwcaps == 0); - - /* Start a new, empty extent. */ - vge->n_used = 1; - vge->base[0] = guest_pc_start; - vge->len[0] = 0; - - /* Set up globals. */ - host_is_bigendian = host_bigendian; - guest_code = armCode; - guest_pc_bbstart = (Addr32)guest_pc_start; - irsb = emptyIRSB(); - - vassert((guest_pc_start >> 32) == 0); - - /* Delta keeps track of how far along the armCode array we - have so far gone. */ - delta = 0; - n_instrs = 0; - - while (True) { - vassert(n_instrs < vex_control.guest_max_insns); - - guest_next = 0; - resteerOK = toBool(n_instrs < vex_control.guest_chase_thresh); - first_stmt_idx = irsb->stmts_used; - - if (n_instrs > 0) { - /* for the first insn, the dispatch loop will have set - R15, but for all the others we have to do it ourselves. */ - stmt( IRStmt_Put( OFFB_R15, mkU32(toUInt(guest_pc_bbstart + delta))) ); - } - - dres = disInstr( resteerOK, chase_into_ok, - delta, &size, &guest_next ); - - /* Print the resulting IR, if needed. */ - if (vex_traceflags & VEX_TRACE_FE) { - for (i = first_stmt_idx; i < irsb->stmts_used; i++) { - vex_printf(" "); - ppIRStmt(irsb->stmts[i]); - vex_printf("\n"); - } - } - - if (dres == Dis_StopHere) { - vassert(irsb->next != NULL); - if (vex_traceflags & VEX_TRACE_FE) { - vex_printf(" "); - vex_printf( "goto {"); - ppIRJumpKind(irsb->jumpkind); - vex_printf( "} "); - ppIRExpr( irsb->next ); - vex_printf( "\n"); - } - } - - delta += size; - vge->len[vge->n_used-1] = toUShort(vge->len[vge->n_used-1] + size); - n_instrs++; - DIP("\n"); - - vassert(size > 0 && size <= 18); - if (!resteerOK) - vassert(dres != Dis_Resteer); - if (dres != Dis_Resteer) - vassert(guest_next == 0); - - switch (dres) { - case Dis_Continue: - vassert(irsb->next == NULL); - if (n_instrs < vex_control.guest_max_insns) { - /* keep going */ - } else { - irsb->next = mkU32(toUInt(guest_pc_start+delta)); - return irsb; - } - break; - case Dis_StopHere: - vassert(irsb->next != NULL); - return irsb; - case Dis_Resteer: - vpanic("bbToIR_ARM: Dis_Resteer: fixme"); - /* need to add code here to start a new extent ... */ - vassert(irsb->next == NULL); - /* figure out a new delta to continue at. */ - vassert(chase_into_ok(guest_next)); - delta = guest_next - guest_pc_start; - n_resteers++; - d_resteers++; - if (0 && (n_resteers & 0xFF) == 0) - vex_printf("resteer[%d,%d] to %p (delta = %lld)\n", - n_resteers, d_resteers, - ULong_to_Ptr(guest_next), delta); - break; - } - } -} +/* produces _uint[_bMax:_bMin] */ +#define SLICE_UInt(_uint,_bMax,_bMin) \ + (( ((UInt)(_uint)) >> (_bMin)) \ + & (UInt)((1ULL << ((_bMax) - (_bMin) + 1)) - 1ULL)) /*------------------------------------------------------------*/ -/*--- Helper bits and pieces for deconstructing the ---*/ -/*--- ARM insn stream. ---*/ +/*--- Helper bits and pieces for creating IR fragments. ---*/ /*------------------------------------------------------------*/ -/* Add a statement to the list held by "irsb". */ -static void stmt ( IRStmt* st ) +static IRExpr* mkU64 ( ULong i ) { - addStmtToIRSB( irsb, st ); + return IRExpr_Const(IRConst_U64(i)); } -/* Generate a new temporary of the given type. */ -static IRTemp newTemp ( IRType ty ) +static IRExpr* mkU32 ( UInt i ) { - vassert(isPlausibleIRType(ty)); - return newIRTemp( irsb->tyenv, ty ); + return IRExpr_Const(IRConst_U32(i)); } -#if 0 -/* Bomb out if we can't handle something. */ -__attribute__ ((noreturn)) -static void unimplemented ( Char* str ) +static IRExpr* mkU8 ( UInt i ) { - vex_printf("armToIR: unimplemented feature\n"); - vpanic(str); + vassert(i < 256); + return IRExpr_Const(IRConst_U8( (UChar)i )); } -#endif -/* Various simple conversions */ +static IRExpr* mkexpr ( IRTemp tmp ) +{ + return IRExpr_RdTmp(tmp); +} -#if 0 -static UInt extend_s_8to32( UInt x ) +static IRExpr* unop ( IROp op, IRExpr* a ) { - return (UInt)((((Int)x) << 24) >> 24); + return IRExpr_Unop(op, a); } -static UInt extend_s_16to32 ( UInt x ) +static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) { - return (UInt)((((Int)x) << 16) >> 16); + return IRExpr_Binop(op, a1, a2); } -#endif -static UInt extend_s_24to32 ( UInt x ) +static IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) { - return (UInt)((((Int)x) << 8) >> 8); + return IRExpr_Triop(op, a1, a2, a3); } -#if 0 -/* Fetch a byte from the guest insn stream. */ -static UChar getIByte ( UInt delta ) +static IRExpr* loadLE ( IRType ty, IRExpr* addr ) { - return guest_code[delta]; + return IRExpr_Load(Iend_LE, ty, addr); } -#endif -/* Get a 8/16/32-bit unsigned value out of the insn stream. */ +/* Add a statement to the list held by "irbb". */ +static void stmt ( IRStmt* st ) +{ + addStmtToIRSB( irsb, st ); +} -#if 0 -static UInt getUChar ( UInt delta ) +static void assign ( IRTemp dst, IRExpr* e ) { - UInt v = guest_code[delta+0]; - return v & 0xFF; + stmt( IRStmt_WrTmp(dst, e) ); } -#endif -#if 0 -static UInt getUDisp16 ( UInt delta ) +static void storeLE ( IRExpr* addr, IRExpr* data ) { - UInt v = guest_code[delta+1]; v <<= 8; - v |= guest_code[delta+0]; - return v & 0xFFFF; + stmt( IRStmt_Store(Iend_LE, addr, data) ); } -#endif -#if 0 -static UInt getUDisp32 ( UInt delta ) +/* Generate a new temporary of the given type. */ +static IRTemp newTemp ( IRType ty ) { - UInt v = guest_code[delta+3]; v <<= 8; - v |= guest_code[delta+2]; v <<= 8; - v |= guest_code[delta+1]; v <<= 8; - v |= guest_code[delta+0]; - return v; + vassert(isPlausibleIRType(ty)); + return newIRTemp( irsb->tyenv, ty ); } -#endif -#if 0 -static UInt getUDisp ( Int size, UInt delta ) +/* Produces a value in 0 .. 3, which is encoded as per the type + IRRoundingMode. */ +static IRExpr* /* :: Ity_I32 */ get_FAKE_roundingmode ( void ) { - switch (size) { - case 4: return getUDisp32(delta); - case 2: return getUDisp16(delta); - case 1: return getUChar(delta); - default: vpanic("getUDisp(ARM)"); - } - return 0; /*notreached*/ + return mkU32(Irrm_NEAREST); } -#endif -#if 0 -/* Get a byte value out of the insn stream and sign-extend to 32 - bits. */ -static UInt getSDisp8 ( UInt delta ) +/* Generate an expression for SRC rotated right by ROT. */ +static IRExpr* genROR32( IRTemp src, Int rot ) { - return extend_s_8to32( (UInt) (guest_code[delta]) ); + vassert(rot >= 0 && rot < 32); + if (rot == 0) + return mkexpr(src); + return + binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(src), mkU8(32 - rot)), + binop(Iop_Shr32, mkexpr(src), mkU8(rot))); } -#endif -#if 0 -static UInt getSDisp16 ( UInt delta0 ) +static IRExpr* mkU128 ( ULong i ) { - UChar* eip = (UChar*)(&guest_code[delta0]); - UInt d = *eip++; - d |= ((*eip++) << 8); - return extend_s_16to32(d); + return binop(Iop_64HLtoV128, mkU64(i), mkU64(i)); } -#endif -#if 0 -static UInt getSDisp ( Int size, UInt delta ) +/* Generate a 4-aligned version of the given expression if + the given condition is true. Else return it unchanged. */ +static IRExpr* align4if ( IRExpr* e, Bool b ) { - switch (size) { - case 4: return getUDisp32(delta); - case 2: return getSDisp16(delta); - case 1: return getSDisp8(delta); - default: vpanic("getSDisp(ARM)"); - } - return 0; /*notreached*/ + if (b) + return binop(Iop_And32, e, mkU32(~3)); + else + return e; } -#endif /*------------------------------------------------------------*/ -/*--- Helpers for constructing IR. ---*/ +/*--- Helpers for accessing guest registers. ---*/ /*------------------------------------------------------------*/ -/* Create a 1/2/4 byte read of an x86 integer registers. For 16/8 bit - register references, we need to take the host endianness into - account. Supplied value is 0 .. 7 and in the Intel instruction - encoding. */ +#define OFFB_R0 offsetof(VexGuestARMState,guest_R0) +#define OFFB_R1 offsetof(VexGuestARMState,guest_R1) +#define OFFB_R2 offsetof(VexGuestARMState,guest_R2) +#define OFFB_R3 offsetof(VexGuestARMState,guest_R3) +#define OFFB_R4 offsetof(VexGuestARMState,guest_R4) +#define OFFB_R5 offsetof(VexGuestARMState,guest_R5) +#define OFFB_R6 offsetof(VexGuestARMState,guest_R6) +#define OFFB_R7 offsetof(VexGuestARMState,guest_R7) +#define OFFB_R8 offsetof(VexGuestARMState,guest_R8) +#define OFFB_R9 offsetof(VexGuestARMState,guest_R9) +#define OFFB_R10 offsetof(VexGuestARMState,guest_R10) +#define OFFB_R11 offsetof(VexGuestARMState,guest_R11) +#define OFFB_R12 offsetof(VexGuestARMState,guest_R12) +#define OFFB_R13 offsetof(VexGuestARMState,guest_R13) +#define OFFB_R14 offsetof(VexGuestARMState,guest_R14) +#define OFFB_R15T offsetof(VexGuestARMState,guest_R15T) -#if 0 -static IRType szToITy ( Int n ) +#define OFFB_CC_OP offsetof(VexGuestARMState,guest_CC_OP) +#define OFFB_CC_DEP1 offsetof(VexGuestARMState,guest_CC_DEP1) +#define OFFB_CC_DEP2 offsetof(VexGuestARMState,guest_CC_DEP2) +#define OFFB_CC_NDEP offsetof(VexGuestARMState,guest_CC_NDEP) +#define OFFB_NRADDR offsetof(VexGuestARMState,guest_NRADDR) + +#define OFFB_D0 offsetof(VexGuestARMState,guest_D0) +#define OFFB_D1 offsetof(VexGuestARMState,guest_D1) +#define OFFB_D2 offsetof(VexGuestARMState,guest_D2) +#define OFFB_D3 offsetof(VexGuestARMState,guest_D3) +#define OFFB_D4 offsetof(VexGuestARMState,guest_D4) +#define OFFB_D5 offsetof(VexGuestARMState,guest_D5) +#define OFFB_D6 offsetof(VexGuestARMState,guest_D6) +#define OFFB_D7 offsetof(VexGuestARMState,guest_D7) +#define OFFB_D8 offsetof(VexGuestARMState,guest_D8) +#define OFFB_D9 offsetof(VexGuestARMState,guest_D9) +#define OFFB_D10 offsetof(VexGuestARMState,guest_D10) +#define OFFB_D11 offsetof(VexGuestARMState,guest_D11) +#define OFFB_D12 offsetof(VexGuestARMState,guest_D12) +#define OFFB_D13 offsetof(VexGuestARMState,guest_D13) +#define OFFB_D14 offsetof(VexGuestARMState,guest_D14) +#define OFFB_D15 offsetof(VexGuestARMState,guest_D15) +#define OFFB_D16 offsetof(VexGuestARMState,guest_D16) +#define OFFB_D17 offsetof(VexGuestARMState,guest_D17) +#define OFFB_D18 offsetof(VexGuestARMState,guest_D18) +#define OFFB_D19 offsetof(VexGuestARMState,guest_D19) +#define OFFB_D20 offsetof(VexGuestARMState,guest_D20) +#define OFFB_D21 offsetof(VexGuestARMState,guest_D21) +#define OFFB_D22 offsetof(VexGuestARMState,guest_D22) +#define OFFB_D23 offsetof(VexGuestARMState,guest_D23) +#define OFFB_D24 offsetof(VexGuestARMState,guest_D24) +#define OFFB_D25 offsetof(VexGuestARMState,guest_D25) +#define OFFB_D26 offsetof(VexGuestARMState,guest_D26) +#define OFFB_D27 offsetof(VexGuestARMState,guest_D27) +#define OFFB_D28 offsetof(VexGuestARMState,guest_D28) +#define OFFB_D29 offsetof(VexGuestARMState,guest_D29) +#define OFFB_D30 offsetof(VexGuestARMState,guest_D30) +#define OFFB_D31 offsetof(VexGuestARMState,guest_D31) + +#define OFFB_FPSCR offsetof(VexGuestARMState,guest_FPSCR) +#define OFFB_TPIDRURO offsetof(VexGuestARMState,guest_TPIDRURO) +#define OFFB_ITSTATE offsetof(VexGuestARMState,guest_ITSTATE) +#define OFFB_QFLAG32 offsetof(VexGuestARMState,guest_QFLAG32) +#define OFFB_GEFLAG0 offsetof(VexGuestARMState,guest_GEFLAG0) +#define OFFB_GEFLAG1 offsetof(VexGuestARMState,guest_GEFLAG1) +#define OFFB_GEFLAG2 offsetof(VexGuestARMState,guest_GEFLAG2) +#define OFFB_GEFLAG3 offsetof(VexGuestARMState,guest_GEFLAG3) + + +/* ---------------- Integer registers ---------------- */ + +static Int integerGuestRegOffset ( UInt iregNo ) { - switch (n) { - case 1: return Ity_I8; - case 2: return Ity_I16; - case 4: return Ity_I32; - default: vpanic("szToITy(ARM)"); + /* Do we care about endianness here? We do if sub-parts of integer + registers are accessed, but I don't think that ever happens on + ARM. */ + switch (iregNo) { + case 0: return OFFB_R0; + case 1: return OFFB_R1; + case 2: return OFFB_R2; + case 3: return OFFB_R3; + case 4: return OFFB_R4; + case 5: return OFFB_R5; + case 6: return OFFB_R6; + case 7: return OFFB_R7; + case 8: return OFFB_R8; + case 9: return OFFB_R9; + case 10: return OFFB_R10; + case 11: return OFFB_R11; + case 12: return OFFB_R12; + case 13: return OFFB_R13; + case 14: return OFFB_R14; + case 15: return OFFB_R15T; + default: vassert(0); } } -#endif -static Int integerGuestRegOffset ( UInt archreg ) +/* Plain ("low level") read from a reg; no +8 offset magic for r15. */ +static IRExpr* llGetIReg ( UInt iregNo ) { - vassert(archreg < 16); + vassert(iregNo < 16); + return IRExpr_Get( integerGuestRegOffset(iregNo), Ity_I32 ); +} - vassert(!host_is_bigendian); //TODO: is this necessary? - // jrs: probably not; only matters if we reference sub-parts - // of the arm registers, but that isn't the case - switch (archreg) { - case 0: return offsetof(VexGuestARMState,guest_R0); - case 1: return offsetof(VexGuestARMState,guest_R1); - case 2: return offsetof(VexGuestARMState,guest_R2); - case 3: return offsetof(VexGuestARMState,guest_R3); - case 4: return offsetof(VexGuestARMState,guest_R4); - case 5: return offsetof(VexGuestARMState,guest_R5); - case 6: return offsetof(VexGuestARMState,guest_R6); - case 7: return offsetof(VexGuestARMState,guest_R7); - case 8: return offsetof(VexGuestARMState,guest_R8); - case 9: return offsetof(VexGuestARMState,guest_R9); - case 10: return offsetof(VexGuestARMState,guest_R10); - case 11: return offsetof(VexGuestARMState,guest_R11); - case 12: return offsetof(VexGuestARMState,guest_R12); - case 13: return offsetof(VexGuestARMState,guest_R13); - case 14: return offsetof(VexGuestARMState,guest_R14); - case 15: return offsetof(VexGuestARMState,guest_R15); +/* Architected read from a reg in ARM mode. This automagically adds 8 + to all reads of r15. */ +static IRExpr* getIRegA ( UInt iregNo ) +{ + IRExpr* e; + ASSERT_IS_ARM; + vassert(iregNo < 16); + if (iregNo == 15) { + /* If asked for r15, don't read the guest state value, as that + may not be up to date in the case where loop unrolling has + happened, because the first insn's write to the block is + omitted; hence in the 2nd and subsequent unrollings we don't + have a correct value in guest r15. Instead produce the + constant that we know would be produced at this point. */ + vassert(0 == (guest_R15_curr_instr_notENC & 3)); + e = mkU32(guest_R15_curr_instr_notENC + 8); + } else { + e = IRExpr_Get( integerGuestRegOffset(iregNo), Ity_I32 ); } - - vpanic("integerGuestRegOffset(arm,le)"); /*notreached*/ + return e; } -static IRExpr* getIReg ( UInt archreg ) +/* Architected read from a reg in Thumb mode. This automagically adds + 4 to all reads of r15. */ +static IRExpr* getIRegT ( UInt iregNo ) { - vassert(archreg < 16); - return IRExpr_Get( integerGuestRegOffset(archreg), Ity_I32 ); + IRExpr* e; + ASSERT_IS_THUMB; + vassert(iregNo < 16); + if (iregNo == 15) { + /* Ditto comment in getIReg. */ + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + e = mkU32(guest_R15_curr_instr_notENC + 4); + } else { + e = IRExpr_Get( integerGuestRegOffset(iregNo), Ity_I32 ); + } + return e; } -/* Ditto, but write to a reg instead. */ -static void putIReg ( UInt archreg, IRExpr* e ) +/* Plain ("low level") write to a reg; no jump or alignment magic for + r15. */ +static void llPutIReg ( UInt iregNo, IRExpr* e ) { - vassert(archreg < 16); - stmt( IRStmt_Put(integerGuestRegOffset(archreg), e) ); + vassert(iregNo < 16); + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); + stmt( IRStmt_Put(integerGuestRegOffset(iregNo), e) ); } -static void assign ( IRTemp dst, IRExpr* e ) +/* Architected write to an integer register in ARM mode. If it is to + r15, record info so at the end of this insn's translation, a branch + to it can be made. Also handles conditional writes to the + register: if guardT == IRTemp_INVALID then the write is + unconditional. If writing r15, also 4-align it. */ +static void putIRegA ( UInt iregNo, + IRExpr* e, + IRTemp guardT /* :: Ity_I32, 0 or 1 */, + IRJumpKind jk /* if a jump is generated */ ) { - stmt( IRStmt_WrTmp(dst, e) ); + /* if writing r15, force e to be 4-aligned. */ + // INTERWORKING FIXME. this needs to be relaxed so that + // puts caused by LDMxx which load r15 interwork right. + // but is no aligned too relaxed? + //if (iregNo == 15) + // e = binop(Iop_And32, e, mkU32(~3)); + ASSERT_IS_ARM; + /* So, generate either an unconditional or a conditional write to + the reg. */ + if (guardT == IRTemp_INVALID) { + /* unconditional write */ + llPutIReg( iregNo, e ); + } else { + llPutIReg( iregNo, + IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)), + llGetIReg(iregNo), + e )); + } + if (iregNo == 15) { + // assert against competing r15 updates. Shouldn't + // happen; should be ruled out by the instr matching + // logic. + vassert(r15written == False); + vassert(r15guard == IRTemp_INVALID); + vassert(r15kind == Ijk_Boring); + r15written = True; + r15guard = guardT; + r15kind = jk; + } } -static void storeLE ( IRExpr* addr, IRExpr* data ) + +/* Architected write to an integer register in Thumb mode. Writes to + r15 are not allowed. Handles conditional writes to the register: + if guardT == IRTemp_INVALID then the write is unconditional. */ +static void putIRegT ( UInt iregNo, + IRExpr* e, + IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) { - stmt( IRStmt_Store(Iend_LE, IRTemp_INVALID, addr, data) ); + /* So, generate either an unconditional or a conditional write to + the reg. */ + ASSERT_IS_THUMB; + vassert(iregNo >= 0 && iregNo <= 14); + if (guardT == IRTemp_INVALID) { + /* unconditional write */ + llPutIReg( iregNo, e ); + } else { + llPutIReg( iregNo, + IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)), + llGetIReg(iregNo), + e )); + } } -static IRExpr* unop ( IROp op, IRExpr* a ) + +/* Thumb16 and Thumb32 only. + Returns true if reg is 13 or 15. Implements the BadReg + predicate in the ARM ARM. */ +static Bool isBadRegT ( UInt r ) { - return IRExpr_Unop(op, a); + vassert(r <= 15); + ASSERT_IS_THUMB; + return r == 13 || r == 15; } -static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) + +/* ---------------- Double registers ---------------- */ + +static Int doubleGuestRegOffset ( UInt dregNo ) { - return IRExpr_Binop(op, a1, a2); + /* Do we care about endianness here? Probably do if we ever get + into the situation of dealing with the single-precision VFP + registers. */ + switch (dregNo) { + case 0: return OFFB_D0; + case 1: return OFFB_D1; + case 2: return OFFB_D2; + case 3: return OFFB_D3; + case 4: return OFFB_D4; + case 5: return OFFB_D5; + case 6: return OFFB_D6; + case 7: return OFFB_D7; + case 8: return OFFB_D8; + case 9: return OFFB_D9; + case 10: return OFFB_D10; + case 11: return OFFB_D11; + case 12: return OFFB_D12; + case 13: return OFFB_D13; + case 14: return OFFB_D14; + case 15: return OFFB_D15; + case 16: return OFFB_D16; + case 17: return OFFB_D17; + case 18: return OFFB_D18; + case 19: return OFFB_D19; + case 20: return OFFB_D20; + case 21: return OFFB_D21; + case 22: return OFFB_D22; + case 23: return OFFB_D23; + case 24: return OFFB_D24; + case 25: return OFFB_D25; + case 26: return OFFB_D26; + case 27: return OFFB_D27; + case 28: return OFFB_D28; + case 29: return OFFB_D29; + case 30: return OFFB_D30; + case 31: return OFFB_D31; + default: vassert(0); + } } -static IRExpr* mkexpr ( IRTemp tmp ) +/* Plain ("low level") read from a VFP Dreg. */ +static IRExpr* llGetDReg ( UInt dregNo ) { - return IRExpr_RdTmp(tmp); + vassert(dregNo < 32); + return IRExpr_Get( doubleGuestRegOffset(dregNo), Ity_F64 ); } -static IRExpr* mkU8 ( UChar i ) -{ - return IRExpr_Const(IRConst_U8(i)); +/* Architected read from a VFP Dreg. */ +static IRExpr* getDReg ( UInt dregNo ) { + return llGetDReg( dregNo ); } -#if 0 -static IRExpr* mkU16 ( UInt i ) +/* Plain ("low level") write to a VFP Dreg. */ +static void llPutDReg ( UInt dregNo, IRExpr* e ) { - vassert(i < 65536); - return IRExpr_Const(IRConst_U16(i)); + vassert(dregNo < 32); + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64); + stmt( IRStmt_Put(doubleGuestRegOffset(dregNo), e) ); } -#endif -static IRExpr* mkU32 ( UInt i ) +/* Architected write to a VFP Dreg. Handles conditional writes to the + register: if guardT == IRTemp_INVALID then the write is + unconditional. */ +static void putDReg ( UInt dregNo, + IRExpr* e, + IRTemp guardT /* :: Ity_I32, 0 or 1 */) { - return IRExpr_Const(IRConst_U32(i)); + /* So, generate either an unconditional or a conditional write to + the reg. */ + if (guardT == IRTemp_INVALID) { + /* unconditional write */ + llPutDReg( dregNo, e ); + } else { + llPutDReg( dregNo, + IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)), + llGetDReg(dregNo), + e )); + } } -#if 0 -static IRExpr* mkU ( IRType ty, UInt i ) +/* And now exactly the same stuff all over again, but this time + taking/returning I64 rather than F64, to support 64-bit Neon + ops. */ + +/* Plain ("low level") read from a Neon Integer Dreg. */ +static IRExpr* llGetDRegI64 ( UInt dregNo ) { - if (ty == Ity_I8) return mkU8(i); - if (ty == Ity_I16) return mkU16(i); - if (ty == Ity_I32) return mkU32(i); - /* If this panics, it usually means you passed a size (1,2,4) - value as the IRType, rather than a real IRType. */ - vpanic("mkU(ARM)"); + vassert(dregNo < 32); + return IRExpr_Get( doubleGuestRegOffset(dregNo), Ity_I64 ); } -#endif -static IRExpr* loadLE ( IRType ty, IRExpr* data ) -{ - return IRExpr_Load(False, Iend_LE, ty, data); +/* Architected read from a Neon Integer Dreg. */ +static IRExpr* getDRegI64 ( UInt dregNo ) { + return llGetDRegI64( dregNo ); } -#if 0 -static IROp mkSizedOp ( IRType ty, IROp op8 ) -{ - Int adj; - vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); - vassert(op8 == Iop_Add8 || op8 == Iop_Sub8 - || op8 == Iop_Mul8 - || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 - || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 - || op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 - || op8 == Iop_Not8 ); - adj = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2); - return adj + op8; +/* Plain ("low level") write to a Neon Integer Dreg. */ +static void llPutDRegI64 ( UInt dregNo, IRExpr* e ) +{ + vassert(dregNo < 32); + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); + stmt( IRStmt_Put(doubleGuestRegOffset(dregNo), e) ); } -#endif -#if 0 -static IROp mkWidenOp ( Int szSmall, Int szBig, Bool signd ) +/* Architected write to a Neon Integer Dreg. Handles conditional + writes to the register: if guardT == IRTemp_INVALID then the write + is unconditional. */ +static void putDRegI64 ( UInt dregNo, + IRExpr* e, + IRTemp guardT /* :: Ity_I32, 0 or 1 */) { - if (szSmall == 1 && szBig == 4) { - return signd ? Iop_8Sto32 : Iop_8Uto32; - } - if (szSmall == 1 && szBig == 2) { - return signd ? Iop_8Sto16 : Iop_8Uto16; - } - if (szSmall == 2 && szBig == 4) { - return signd ? Iop_16Sto32 : Iop_16Uto32; + /* So, generate either an unconditional or a conditional write to + the reg. */ + if (guardT == IRTemp_INVALID) { + /* unconditional write */ + llPutDRegI64( dregNo, e ); + } else { + llPutDRegI64( dregNo, + IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)), + llGetDRegI64(dregNo), + e )); } - vpanic("mkWidenOp(ARM,guest)"); } -#endif +/* ---------------- Quad registers ---------------- */ +static Int quadGuestRegOffset ( UInt qregNo ) +{ + /* Do we care about endianness here? Probably do if we ever get + into the situation of dealing with the 64 bit Neon registers. */ + switch (qregNo) { + case 0: return OFFB_D0; + case 1: return OFFB_D2; + case 2: return OFFB_D4; + case 3: return OFFB_D6; + case 4: return OFFB_D8; + case 5: return OFFB_D10; + case 6: return OFFB_D12; + case 7: return OFFB_D14; + case 8: return OFFB_D16; + case 9: return OFFB_D18; + case 10: return OFFB_D20; + case 11: return OFFB_D22; + case 12: return OFFB_D24; + case 13: return OFFB_D26; + case 14: return OFFB_D28; + case 15: return OFFB_D30; + default: vassert(0); + } +} +/* Plain ("low level") read from a Neon Qreg. */ +static IRExpr* llGetQReg ( UInt qregNo ) +{ + vassert(qregNo < 16); + return IRExpr_Get( quadGuestRegOffset(qregNo), Ity_V128 ); +} +/* Architected read from a Neon Qreg. */ +static IRExpr* getQReg ( UInt qregNo ) { + return llGetQReg( qregNo ); +} +/* Plain ("low level") write to a Neon Qreg. */ +static void llPutQReg ( UInt qregNo, IRExpr* e ) +{ + vassert(qregNo < 16); + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); + stmt( IRStmt_Put(quadGuestRegOffset(qregNo), e) ); +} +/* Architected write to a Neon Qreg. Handles conditional writes to the + register: if guardT == IRTemp_INVALID then the write is + unconditional. */ +static void putQReg ( UInt qregNo, + IRExpr* e, + IRTemp guardT /* :: Ity_I32, 0 or 1 */) +{ + /* So, generate either an unconditional or a conditional write to + the reg. */ + if (guardT == IRTemp_INVALID) { + /* unconditional write */ + llPutQReg( qregNo, e ); + } else { + llPutQReg( qregNo, + IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)), + llGetQReg(qregNo), + e )); + } +} +/* ---------------- Float registers ---------------- */ +static Int floatGuestRegOffset ( UInt fregNo ) +{ + /* Start with the offset of the containing double, and then correct + for endianness. Actually this is completely bogus and needs + careful thought. */ + Int off; + vassert(fregNo < 32); + off = doubleGuestRegOffset(fregNo >> 1); + if (host_is_bigendian) { + vassert(0); + } else { + if (fregNo & 1) + off += 4; + } + return off; +} +/* Plain ("low level") read from a VFP Freg. */ +static IRExpr* llGetFReg ( UInt fregNo ) +{ + vassert(fregNo < 32); + return IRExpr_Get( floatGuestRegOffset(fregNo), Ity_F32 ); +} +/* Architected read from a VFP Freg. */ +static IRExpr* getFReg ( UInt fregNo ) { + return llGetFReg( fregNo ); +} +/* Plain ("low level") write to a VFP Freg. */ +static void llPutFReg ( UInt fregNo, IRExpr* e ) +{ + vassert(fregNo < 32); + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32); + stmt( IRStmt_Put(floatGuestRegOffset(fregNo), e) ); +} +/* Architected write to a VFP Freg. Handles conditional writes to the + register: if guardT == IRTemp_INVALID then the write is + unconditional. */ +static void putFReg ( UInt fregNo, + IRExpr* e, + IRTemp guardT /* :: Ity_I32, 0 or 1 */) +{ + /* So, generate either an unconditional or a conditional write to + the reg. */ + if (guardT == IRTemp_INVALID) { + /* unconditional write */ + llPutFReg( fregNo, e ); + } else { + llPutFReg( fregNo, + IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)), + llGetFReg(fregNo), + e )); + } +} -/*------------------------------------------------------------*/ -/*--- Helpers for %flags. ---*/ -/*------------------------------------------------------------*/ -/* -------------- Evaluating the flags-thunk. -------------- */ +/* ---------------- Misc registers ---------------- */ -#if 0 -/* Build IR to calculate all the flags from stored - CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. - Returns an expression :: Ity_I32. */ -static IRExpr* mk_armg_calculate_flags_all ( void ) +static void putMiscReg32 ( UInt gsoffset, + IRExpr* e, /* :: Ity_I32 */ + IRTemp guardT /* :: Ity_I32, 0 or 1 */) { - IRExpr** args - = mkIRExprVec_3( IRExpr_Get(OFFB_CC_OP, Ity_I32), - IRExpr_Get(OFFB_CC_DEP1, Ity_I32), - IRExpr_Get(OFFB_CC_DEP2, Ity_I32) ); - IRExpr* call - = mkIRExprCCall( - Ity_I32, - 0/*regparm*/, - "armg_calculate_flags_all", &armg_calculate_flags_all, - args - ); + switch (gsoffset) { + case OFFB_FPSCR: break; + case OFFB_QFLAG32: break; + case OFFB_GEFLAG0: break; + case OFFB_GEFLAG1: break; + case OFFB_GEFLAG2: break; + case OFFB_GEFLAG3: break; + default: vassert(0); /* awaiting more cases */ + } + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); - /* Exclude OP from definedness checking. We're only - interested in DEP1 and DEP2. */ - call->Iex.CCall.cee->mcx_mask = 1; - return call; + if (guardT == IRTemp_INVALID) { + /* unconditional write */ + stmt(IRStmt_Put(gsoffset, e)); + } else { + stmt(IRStmt_Put( + gsoffset, + IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)), + IRExpr_Get(gsoffset, Ity_I32), + e + ) + )); + } } -#endif -/* Build IR to calculate just the carry flag from stored - CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: Ity_I32. */ -static IRExpr* mk_armg_calculate_flags_c ( void ) +static IRTemp get_ITSTATE ( void ) { - IRExpr** args - = mkIRExprVec_3( IRExpr_Get(OFFB_CC_OP, Ity_I32), - IRExpr_Get(OFFB_CC_DEP1, Ity_I32), - IRExpr_Get(OFFB_CC_DEP2, Ity_I32) ); - IRExpr* call - = mkIRExprCCall( - Ity_I32, - 0/*regparm*/, - "armg_calculate_flags_c", &armg_calculate_flags_c, - args - ); - /* Exclude OP from definedness checking. We're only - interested in DEP1 and DEP2. */ - call->Iex.CCall.cee->mcx_mask = 1; - return call; + ASSERT_IS_THUMB; + IRTemp t = newTemp(Ity_I32); + assign(t, IRExpr_Get( OFFB_ITSTATE, Ity_I32)); + return t; } +static void put_ITSTATE ( IRTemp t ) +{ + ASSERT_IS_THUMB; + stmt( IRStmt_Put( OFFB_ITSTATE, mkexpr(t)) ); +} -/* Build IR to calculate some particular condition from stored - CC_OP/CC_DEP1/CC_DEP2. Returns an expression - of type Ity_I1. -*/ -static IRExpr* mk_armg_calculate_condition ( ARMCondcode cond ) +static IRTemp get_QFLAG32 ( void ) { - IRExpr** args - = mkIRExprVec_4( mkU32(cond), - IRExpr_Get(OFFB_CC_OP, Ity_I32), - IRExpr_Get(OFFB_CC_DEP1, Ity_I32), - IRExpr_Get(OFFB_CC_DEP2, Ity_I32) ); - IRExpr* call - = mkIRExprCCall( - Ity_I32, - 0/*regparm*/, - "armg_calculate_condition", &armg_calculate_condition, - args - ); + IRTemp t = newTemp(Ity_I32); + assign(t, IRExpr_Get( OFFB_QFLAG32, Ity_I32)); + return t; +} - /* Exclude the requested condition and OP from definedness - checking. We're only interested in DEP1 and DEP2. */ - call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<1); - return unop(Iop_32to1, call); +static void put_QFLAG32 ( IRTemp t, IRTemp condT ) +{ + putMiscReg32( OFFB_QFLAG32, mkexpr(t), condT ); } +/* Stickily set the 'Q' flag (APSR bit 27) of the APSR (Application Program + Status Register) to indicate that overflow or saturation occurred. + Nb: t must be zero to denote no saturation, and any nonzero + value to indicate saturation. */ +static void or_into_QFLAG32 ( IRExpr* e, IRTemp condT ) +{ + IRTemp old = get_QFLAG32(); + IRTemp nyu = newTemp(Ity_I32); + assign(nyu, binop(Iop_Or32, mkexpr(old), e) ); + put_QFLAG32(nyu, condT); +} +/* Generate code to set APSR.GE[flagNo]. Each fn call sets 1 bit. + flagNo: which flag bit to set [3...0] + lowbits_to_ignore: 0 = look at all 32 bits + 8 = look at top 24 bits only + 16 = look at top 16 bits only + 31 = look at the top bit only + e: input value to be evaluated. + The new value is taken from 'e' with the lowest 'lowbits_to_ignore' + masked out. If the resulting value is zero then the GE flag is + set to 0; any other value sets the flag to 1. */ +static void put_GEFLAG32 ( Int flagNo, /* 0, 1, 2 or 3 */ + Int lowbits_to_ignore, /* 0, 8, 16 or 31 */ + IRExpr* e, /* Ity_I32 */ + IRTemp condT ) +{ + vassert( flagNo >= 0 && flagNo <= 3 ); + vassert( lowbits_to_ignore == 0 || + lowbits_to_ignore == 8 || + lowbits_to_ignore == 16 || + lowbits_to_ignore == 31 ); + IRTemp masked = newTemp(Ity_I32); + assign(masked, binop(Iop_Shr32, e, mkU8(lowbits_to_ignore))); + + switch (flagNo) { + case 0: putMiscReg32(OFFB_GEFLAG0, mkexpr(masked), condT); break; + case 1: putMiscReg32(OFFB_GEFLAG1, mkexpr(masked), condT); break; + case 2: putMiscReg32(OFFB_GEFLAG2, mkexpr(masked), condT); break; + case 3: putMiscReg32(OFFB_GEFLAG3, mkexpr(masked), condT); break; + default: vassert(0); + } +} +/* Return the (32-bit, zero-or-nonzero representation scheme) of + the specified GE flag. */ +static IRExpr* get_GEFLAG32( Int flagNo /* 0, 1, 2, 3 */ ) +{ + switch (flagNo) { + case 0: return IRExpr_Get( OFFB_GEFLAG0, Ity_I32 ); + case 1: return IRExpr_Get( OFFB_GEFLAG1, Ity_I32 ); + case 2: return IRExpr_Get( OFFB_GEFLAG2, Ity_I32 ); + case 3: return IRExpr_Get( OFFB_GEFLAG3, Ity_I32 ); + default: vassert(0); + } +} +/* Set all 4 GE flags from the given 32-bit value as follows: GE 3 and + 2 are set from bit 31 of the value, and GE 1 and 0 are set from bit + 15 of the value. All other bits are ignored. */ +static void set_GE_32_10_from_bits_31_15 ( IRTemp t32, IRTemp condT ) +{ + IRTemp ge10 = newTemp(Ity_I32); + IRTemp ge32 = newTemp(Ity_I32); + assign(ge10, binop(Iop_And32, mkexpr(t32), mkU32(0x00008000))); + assign(ge32, binop(Iop_And32, mkexpr(t32), mkU32(0x80000000))); + put_GEFLAG32( 0, 0, mkexpr(ge10), condT ); + put_GEFLAG32( 1, 0, mkexpr(ge10), condT ); + put_GEFLAG32( 2, 0, mkexpr(ge32), condT ); + put_GEFLAG32( 3, 0, mkexpr(ge32), condT ); +} +/* Set all 4 GE flags from the given 32-bit value as follows: GE 3 + from bit 31, GE 2 from bit 23, GE 1 from bit 15, and GE0 from + bit 7. All other bits are ignored. */ +static void set_GE_3_2_1_0_from_bits_31_23_15_7 ( IRTemp t32, IRTemp condT ) +{ + IRTemp ge0 = newTemp(Ity_I32); + IRTemp ge1 = newTemp(Ity_I32); + IRTemp ge2 = newTemp(Ity_I32); + IRTemp ge3 = newTemp(Ity_I32); + assign(ge0, binop(Iop_And32, mkexpr(t32), mkU32(0x00000080))); + assign(ge1, binop(Iop_And32, mkexpr(t32), mkU32(0x00008000))); + assign(ge2, binop(Iop_And32, mkexpr(t32), mkU32(0x00800000))); + assign(ge3, binop(Iop_And32, mkexpr(t32), mkU32(0x80000000))); + put_GEFLAG32( 0, 0, mkexpr(ge0), condT ); + put_GEFLAG32( 1, 0, mkexpr(ge1), condT ); + put_GEFLAG32( 2, 0, mkexpr(ge2), condT ); + put_GEFLAG32( 3, 0, mkexpr(ge3), condT ); +} -/* -------------- Building the flags-thunk. -------------- */ -/* The machinery in this section builds the flag-thunk following a - flag-setting operation. Hence the various setFlags_* functions. -*/ +/* ---------------- FPSCR stuff ---------------- */ -#if 0 -static Bool isAddSub ( IROp op8 ) +/* Generate IR to get hold of the rounding mode bits in FPSCR, and + convert them to IR format. Bind the final result to the + returned temp. */ +static IRTemp /* :: Ity_I32 */ mk_get_IR_rounding_mode ( void ) { - return op8 == Iop_Add8 || op8 == Iop_Sub8; + /* The ARMvfp encoding for rounding mode bits is: + 00 to nearest + 01 to +infinity + 10 to -infinity + 11 to zero + We need to convert that to the IR encoding: + 00 to nearest (the default) + 10 to +infinity + 01 to -infinity + 11 to zero + Which can be done by swapping bits 0 and 1. + The rmode bits are at 23:22 in FPSCR. + */ + IRTemp armEncd = newTemp(Ity_I32); + IRTemp swapped = newTemp(Ity_I32); + /* Fish FPSCR[23:22] out, and slide to bottom. Doesn't matter that + we don't zero out bits 24 and above, since the assignment to + 'swapped' will mask them out anyway. */ + assign(armEncd, + binop(Iop_Shr32, IRExpr_Get(OFFB_FPSCR, Ity_I32), mkU8(22))); + /* Now swap them. */ + assign(swapped, + binop(Iop_Or32, + binop(Iop_And32, + binop(Iop_Shl32, mkexpr(armEncd), mkU8(1)), + mkU32(2)), + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(armEncd), mkU8(1)), + mkU32(1)) + )); + return swapped; } -#endif -#if 0 -static Bool isLogic ( IROp op8 ) -{ - return op8 == Iop_And8 || op8 == Iop_Or8 || op8 == Iop_Xor8; -} -#endif -/* U-widen 8/16/32 bit int expr to 32. */ -static IRExpr* widenUto32 ( IRExpr* e ) +/*------------------------------------------------------------*/ +/*--- Helpers for flag handling and conditional insns ---*/ +/*------------------------------------------------------------*/ + +static HChar* name_ARMCondcode ( ARMCondcode cond ) { - switch (typeOfIRExpr(irsb->tyenv,e)) { - case Ity_I32: return e; - case Ity_I16: return unop(Iop_16Uto32,e); - case Ity_I8: return unop(Iop_8Uto32,e); - default: vpanic("widenUto32"); + switch (cond) { + case ARMCondEQ: return "{eq}"; + case ARMCondNE: return "{ne}"; + case ARMCondHS: return "{hs}"; // or 'cs' + case ARMCondLO: return "{lo}"; // or 'cc' + case ARMCondMI: return "{mi}"; + case ARMCondPL: return "{pl}"; + case ARMCondVS: return "{vs}"; + case ARMCondVC: return "{vc}"; + case ARMCondHI: return "{hi}"; + case ARMCondLS: return "{ls}"; + case ARMCondGE: return "{ge}"; + case ARMCondLT: return "{lt}"; + case ARMCondGT: return "{gt}"; + case ARMCondLE: return "{le}"; + case ARMCondAL: return ""; // {al}: is the default + case ARMCondNV: return "{nv}"; + default: vpanic("name_ARMCondcode"); } } +/* and a handy shorthand for it */ +static HChar* nCC ( ARMCondcode cond ) { + return name_ARMCondcode(cond); +} -#if 0 -/* S-widen 8/16/32 bit int expr to 32. */ -static IRExpr* widenSto32 ( IRExpr* e ) + +/* Build IR to calculate some particular condition from stored + CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression of type + Ity_I32, suitable for narrowing. Although the return type is + Ity_I32, the returned value is either 0 or 1. 'cond' must be + :: Ity_I32 and must denote the condition to compute in + bits 7:4, and be zero everywhere else. +*/ +static IRExpr* mk_armg_calculate_condition_dyn ( IRExpr* cond ) { - switch (typeOfIRExpr(irsb->tyenv,e)) { - case Ity_I32: return e; - case Ity_I16: return unop(Iop_16Sto32,e); - case Ity_I8: return unop(Iop_8Sto32,e); - default: vpanic("widenSto32"); - } + vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I32); + /* And 'cond' had better produce a value in which only bits 7:4 + bits are nonzero. However, obviously we can't assert for + that. */ + + /* So what we're constructing for the first argument is + "(cond << 4) | stored-operation-operation". However, + as per comments above, must be supplied pre-shifted to this + function. + + This pairing scheme requires that the ARM_CC_OP_ values all fit + in 4 bits. Hence we are passing a (COND, OP) pair in the lowest + 8 bits of the first argument. */ + IRExpr** args + = mkIRExprVec_4( + binop(Iop_Or32, IRExpr_Get(OFFB_CC_OP, Ity_I32), cond), + IRExpr_Get(OFFB_CC_DEP1, Ity_I32), + IRExpr_Get(OFFB_CC_DEP2, Ity_I32), + IRExpr_Get(OFFB_CC_NDEP, Ity_I32) + ); + IRExpr* call + = mkIRExprCCall( + Ity_I32, + 0/*regparm*/, + "armg_calculate_condition", &armg_calculate_condition, + args + ); + + /* Exclude the requested condition, OP and NDEP from definedness + checking. We're only interested in DEP1 and DEP2. */ + call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); + return call; } -#endif -/* Narrow 8/16/32 bit int expr to 8/16/32. Clearly only some - of these combinations make sense. */ -static IRExpr* narrowTo ( IRType dst_ty, IRExpr* e ) + +/* Build IR to calculate some particular condition from stored + CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression of type + Ity_I32, suitable for narrowing. Although the return type is + Ity_I32, the returned value is either 0 or 1. +*/ +static IRExpr* mk_armg_calculate_condition ( ARMCondcode cond ) { - IRType src_ty = typeOfIRExpr(irsb->tyenv,e); - if (src_ty == dst_ty) - return e; - if (src_ty == Ity_I32 && dst_ty == Ity_I16) - return unop(Iop_32to16, e); - if (src_ty == Ity_I32 && dst_ty == Ity_I8) - return unop(Iop_32to8, e); + /* First arg is "(cond << 4) | condition". This requires that the + ARM_CC_OP_ values all fit in 4 bits. Hence we are passing a + (COND, OP) pair in the lowest 8 bits of the first argument. */ + vassert(cond >= 0 && cond <= 15); + return mk_armg_calculate_condition_dyn( mkU32(cond << 4) ); +} - vex_printf("\nsrc, dst tys are: "); - ppIRType(src_ty); - vex_printf(", "); - ppIRType(dst_ty); - vex_printf("\n"); - vpanic("narrowTo(ARM)"); + +/* Build IR to calculate just the carry flag from stored + CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: + Ity_I32. */ +static IRExpr* mk_armg_calculate_flag_c ( void ) +{ + IRExpr** args + = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), + IRExpr_Get(OFFB_CC_DEP1, Ity_I32), + IRExpr_Get(OFFB_CC_DEP2, Ity_I32), + IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); + IRExpr* call + = mkIRExprCCall( + Ity_I32, + 0/*regparm*/, + "armg_calculate_flag_c", &armg_calculate_flag_c, + args + ); + /* Exclude OP and NDEP from definedness checking. We're only + interested in DEP1 and DEP2. */ + call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); + return call; } -/* Set the flags thunk OP, DEP1 and DEP2 fields. The supplied op is - auto-sized up to the real op. */ +/* Build IR to calculate just the overflow flag from stored + CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: + Ity_I32. */ +static IRExpr* mk_armg_calculate_flag_v ( void ) +{ + IRExpr** args + = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), + IRExpr_Get(OFFB_CC_DEP1, Ity_I32), + IRExpr_Get(OFFB_CC_DEP2, Ity_I32), + IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); + IRExpr* call + = mkIRExprCCall( + Ity_I32, + 0/*regparm*/, + "armg_calculate_flag_v", &armg_calculate_flag_v, + args + ); + /* Exclude OP and NDEP from definedness checking. We're only + interested in DEP1 and DEP2. */ + call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); + return call; +} + -static -void setFlags_DEP1_DEP2 ( IROp op, IRTemp dep1, IRTemp dep2 ) +/* Build IR to calculate N Z C V in bits 31:28 of the + returned word. */ +static IRExpr* mk_armg_calculate_flags_nzcv ( void ) { - stmt( IRStmt_Put( OFFB_CC_OP, mkU32(op)) ); - stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(dep1))) ); - stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(mkexpr(dep2))) ); + IRExpr** args + = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), + IRExpr_Get(OFFB_CC_DEP1, Ity_I32), + IRExpr_Get(OFFB_CC_DEP2, Ity_I32), + IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); + IRExpr* call + = mkIRExprCCall( + Ity_I32, + 0/*regparm*/, + "armg_calculate_flags_nzcv", &armg_calculate_flags_nzcv, + args + ); + /* Exclude OP and NDEP from definedness checking. We're only + interested in DEP1 and DEP2. */ + call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); + return call; } +static IRExpr* mk_armg_calculate_flag_qc ( IRExpr* resL, IRExpr* resR, Bool Q ) +{ + IRExpr** args1; + IRExpr** args2; + IRExpr *call1, *call2, *res; + + if (Q) { + args1 = mkIRExprVec_4 ( binop(Iop_GetElem32x4, resL, mkU8(0)), + binop(Iop_GetElem32x4, resL, mkU8(1)), + binop(Iop_GetElem32x4, resR, mkU8(0)), + binop(Iop_GetElem32x4, resR, mkU8(1)) ); + args2 = mkIRExprVec_4 ( binop(Iop_GetElem32x4, resL, mkU8(2)), + binop(Iop_GetElem32x4, resL, mkU8(3)), + binop(Iop_GetElem32x4, resR, mkU8(2)), + binop(Iop_GetElem32x4, resR, mkU8(3)) ); + } else { + args1 = mkIRExprVec_4 ( binop(Iop_GetElem32x2, resL, mkU8(0)), + binop(Iop_GetElem32x2, resL, mkU8(1)), + binop(Iop_GetElem32x2, resR, mkU8(0)), + binop(Iop_GetElem32x2, resR, mkU8(1)) ); + } + +#if 1 + call1 = mkIRExprCCall( + Ity_I32, + 0/*regparm*/, + "armg_calculate_flag_qc", &armg_calculate_flag_qc, + args1 + ); + if (Q) { + call2 = mkIRExprCCall( + Ity_I32, + 0/*regparm*/, + "armg_calculate_flag_qc", &armg_calculate_flag_qc, + args2 + ); + } + if (Q) { + res = binop(Iop_Or32, call1, call2); + } else { + res = call1; + } +#else + if (Q) { + res = unop(Iop_1Uto32, + binop(Iop_CmpNE32, + binop(Iop_Or32, + binop(Iop_Or32, + binop(Iop_Xor32, + args1[0], + args1[2]), + binop(Iop_Xor32, + args1[1], + args1[3])), + binop(Iop_Or32, + binop(Iop_Xor32, + args2[0], + args2[2]), + binop(Iop_Xor32, + args2[1], + args2[3]))), + mkU32(0))); + } else { + res = unop(Iop_1Uto32, + binop(Iop_CmpNE32, + binop(Iop_Or32, + binop(Iop_Xor32, + args1[0], + args1[2]), + binop(Iop_Xor32, + args1[1], + args1[3])), + mkU32(0))); + } +#endif + return res; +} -/* Set the OP and DEP1 fields only, and write zero to DEP2. */ +// FIXME: this is named wrongly .. looks like a sticky set of +// QC, not a write to it. +static void setFlag_QC ( IRExpr* resL, IRExpr* resR, Bool Q, + IRTemp condT ) +{ + putMiscReg32 (OFFB_FPSCR, + binop(Iop_Or32, + IRExpr_Get(OFFB_FPSCR, Ity_I32), + binop(Iop_Shl32, + mk_armg_calculate_flag_qc(resL, resR, Q), + mkU8(27))), + condT); +} -#if 0 -static -void setFlags_DEP1 ( IROp op, IRTemp dep1 ) +/* Build IR to conditionally set the flags thunk. As with putIReg, if + guard is IRTemp_INVALID then it's unconditional, else it holds a + condition :: Ity_I32. */ +static +void setFlags_D1_D2_ND ( UInt cc_op, IRTemp t_dep1, + IRTemp t_dep2, IRTemp t_ndep, + IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) { - stmt( IRStmt_Put( OFFB_CC_OP, mkU32(op)) ); - stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(dep1))) ); - stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0)) ); + IRTemp c8; + vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I32)); + vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I32)); + vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I32)); + vassert(cc_op >= ARMG_CC_OP_COPY && cc_op < ARMG_CC_OP_NUMBER); + if (guardT == IRTemp_INVALID) { + /* unconditional */ + stmt( IRStmt_Put( OFFB_CC_OP, mkU32(cc_op) )); + stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(t_dep1) )); + stmt( IRStmt_Put( OFFB_CC_DEP2, mkexpr(t_dep2) )); + stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(t_ndep) )); + } else { + /* conditional */ + c8 = newTemp(Ity_I8); + assign( c8, unop(Iop_32to8, mkexpr(guardT)) ); + stmt( IRStmt_Put( + OFFB_CC_OP, + IRExpr_Mux0X( mkexpr(c8), + IRExpr_Get(OFFB_CC_OP, Ity_I32), + mkU32(cc_op) ))); + stmt( IRStmt_Put( + OFFB_CC_DEP1, + IRExpr_Mux0X( mkexpr(c8), + IRExpr_Get(OFFB_CC_DEP1, Ity_I32), + mkexpr(t_dep1) ))); + stmt( IRStmt_Put( + OFFB_CC_DEP2, + IRExpr_Mux0X( mkexpr(c8), + IRExpr_Get(OFFB_CC_DEP2, Ity_I32), + mkexpr(t_dep2) ))); + stmt( IRStmt_Put( + OFFB_CC_NDEP, + IRExpr_Mux0X( mkexpr(c8), + IRExpr_Get(OFFB_CC_NDEP, Ity_I32), + mkexpr(t_ndep) ))); + } } -#endif -#if 0 -/* For shift operations, we put in the result and the undershifted - result. Except if the shift amount is zero, the thunk is left - unchanged. */ -static void setFlags_DEP1_DEP2_shift ( IROp op, - IRTemp res, - IRTemp resUS, - IRTemp guard ) +/* Minor variant of the above that sets NDEP to zero (if it + sets it at all) */ +static void setFlags_D1_D2 ( UInt cc_op, IRTemp t_dep1, + IRTemp t_dep2, + IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) { - vassert(guard); - - /* DEP1 contains the result, DEP2 contains the undershifted value. */ - stmt( IRStmt_Put( OFFB_CC_OP, - IRExpr_Mux0X( mkexpr(guard), - IRExpr_Get(OFFB_CC_OP,Ity_I32), - mkU32(op))) ); - stmt( IRStmt_Put( OFFB_CC_DEP1, - IRExpr_Mux0X( mkexpr(guard), - IRExpr_Get(OFFB_CC_DEP1,Ity_I32), - widenUto32(mkexpr(res)))) ); - stmt( IRStmt_Put( OFFB_CC_DEP2, - IRExpr_Mux0X( mkexpr(guard), - IRExpr_Get(OFFB_CC_DEP2,Ity_I32), - widenUto32(mkexpr(resUS)))) ); + IRTemp z32 = newTemp(Ity_I32); + assign( z32, mkU32(0) ); + setFlags_D1_D2_ND( cc_op, t_dep1, t_dep2, z32, guardT ); } -#endif +/* Minor variant of the above that sets DEP2 to zero (if it + sets it at all) */ +static void setFlags_D1_ND ( UInt cc_op, IRTemp t_dep1, + IRTemp t_ndep, + IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) +{ + IRTemp z32 = newTemp(Ity_I32); + assign( z32, mkU32(0) ); + setFlags_D1_D2_ND( cc_op, t_dep1, z32, t_ndep, guardT ); +} +/* Minor variant of the above that sets DEP2 and NDEP to zero (if it + sets them at all) */ +static void setFlags_D1 ( UInt cc_op, IRTemp t_dep1, + IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) +{ + IRTemp z32 = newTemp(Ity_I32); + assign( z32, mkU32(0) ); + setFlags_D1_D2_ND( cc_op, t_dep1, z32, z32, guardT ); +} -#if 0 -/* Multiplies are pretty much like add and sub: DEP1 and DEP2 hold the - two arguments. */ -static -void setFlags_MUL ( IRTemp arg1, IRTemp arg2, UInt op ) +/* ARM only */ +/* Generate a side-exit to the next instruction, if the given guard + expression :: Ity_I32 is 0 (note! the side exit is taken if the + condition is false!) This is used to skip over conditional + instructions which we can't generate straight-line code for, either + because they are too complex or (more likely) they potentially + generate exceptions. +*/ +static void mk_skip_over_A32_if_cond_is_false ( + IRTemp guardT /* :: Ity_I32, 0 or 1 */ + ) { - stmt( IRStmt_Put( OFFB_CC_OP, mkU32(op) ) ); - stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(arg1)) )); - stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(mkexpr(arg2)) )); + ASSERT_IS_ARM; + vassert(guardT != IRTemp_INVALID); + vassert(0 == (guest_R15_curr_instr_notENC & 3)); + stmt( IRStmt_Exit( + unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))), + Ijk_Boring, + IRConst_U32(toUInt(guest_R15_curr_instr_notENC + 4)) + )); } -#endif +/* Thumb16 only */ +/* ditto, but jump over a 16-bit thumb insn */ +static void mk_skip_over_T16_if_cond_is_false ( + IRTemp guardT /* :: Ity_I32, 0 or 1 */ + ) +{ + ASSERT_IS_THUMB; + vassert(guardT != IRTemp_INVALID); + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + stmt( IRStmt_Exit( + unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))), + Ijk_Boring, + IRConst_U32(toUInt((guest_R15_curr_instr_notENC + 2) | 1)) + )); +} +/* Thumb32 only */ +/* ditto, but jump over a 32-bit thumb insn */ +static void mk_skip_over_T32_if_cond_is_false ( + IRTemp guardT /* :: Ity_I32, 0 or 1 */ + ) +{ + ASSERT_IS_THUMB; + vassert(guardT != IRTemp_INVALID); + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + stmt( IRStmt_Exit( + unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))), + Ijk_Boring, + IRConst_U32(toUInt((guest_R15_curr_instr_notENC + 4) | 1)) + )); +} +/* Thumb16 and Thumb32 only + Generate a SIGILL followed by a restart of the current instruction + if the given temp is nonzero. */ +static void gen_SIGILL_T_if_nonzero ( IRTemp t /* :: Ity_I32 */ ) +{ + ASSERT_IS_THUMB; + vassert(t != IRTemp_INVALID); + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + stmt( + IRStmt_Exit( + binop(Iop_CmpNE32, mkexpr(t), mkU32(0)), + Ijk_NoDecode, + IRConst_U32(toUInt(guest_R15_curr_instr_notENC | 1)) + ) + ); +} +/* Inspect the old_itstate, and generate a SIGILL if it indicates that + we are currently in an IT block and are not the last in the block. + This also rolls back guest_ITSTATE to its old value before the exit + and restores it to its new value afterwards. This is so that if + the exit is taken, we have an up to date version of ITSTATE + available. Without doing that, we have no hope of making precise + exceptions work. */ +static void gen_SIGILL_T_if_in_but_NLI_ITBlock ( + IRTemp old_itstate /* :: Ity_I32 */, + IRTemp new_itstate /* :: Ity_I32 */ + ) +{ + ASSERT_IS_THUMB; + put_ITSTATE(old_itstate); // backout + IRTemp guards_for_next3 = newTemp(Ity_I32); + assign(guards_for_next3, + binop(Iop_Shr32, mkexpr(old_itstate), mkU8(8))); + gen_SIGILL_T_if_nonzero(guards_for_next3); + put_ITSTATE(new_itstate); //restore +} -/* -------------- Condition codes. -------------- */ +/* Simpler version of the above, which generates a SIGILL if + we're anywhere within an IT block. */ +static void gen_SIGILL_T_if_in_ITBlock ( + IRTemp old_itstate /* :: Ity_I32 */, + IRTemp new_itstate /* :: Ity_I32 */ + ) +{ + put_ITSTATE(old_itstate); // backout + gen_SIGILL_T_if_nonzero(old_itstate); + put_ITSTATE(new_itstate); //restore +} -/* Condition codes, using the ARM encoding. */ -static HChar* name_ARMCondcode ( ARMCondcode cond ) +/* Generate an APSR value, from the NZCV thunk, and + from QFLAG32 and GEFLAG0 .. GEFLAG3. */ +static IRTemp synthesise_APSR ( void ) { - switch (cond) { - case ARMCondEQ: return "{eq}"; - case ARMCondNE: return "{ne}"; - case ARMCondHS: return "{hs}"; // or 'cs' - case ARMCondLO: return "{lo}"; // or 'cc' - case ARMCondMI: return "{mi}"; - case ARMCondPL: return "{pl}"; - case ARMCondVS: return "{vs}"; - case ARMCondVC: return "{vc}"; - case ARMCondHI: return "{hi}"; - case ARMCondLS: return "{ls}"; - case ARMCondGE: return "{ge}"; - case ARMCondLT: return "{lt}"; - case ARMCondGT: return "{gt}"; - case ARMCondLE: return "{le}"; - case ARMCondAL: return ""; // {al}: default, doesn't need specifying - case ARMCondNV: return "{nv}"; - default: vpanic("name_ARMCondcode"); - } + IRTemp res1 = newTemp(Ity_I32); + // Get NZCV + assign( res1, mk_armg_calculate_flags_nzcv() ); + // OR in the Q value + IRTemp res2 = newTemp(Ity_I32); + assign( + res2, + binop(Iop_Or32, + mkexpr(res1), + binop(Iop_Shl32, + unop(Iop_1Uto32, + binop(Iop_CmpNE32, + mkexpr(get_QFLAG32()), + mkU32(0))), + mkU8(ARMG_CC_SHIFT_Q))) + ); + // OR in GE0 .. GE3 + IRExpr* ge0 + = unop(Iop_1Uto32, binop(Iop_CmpNE32, get_GEFLAG32(0), mkU32(0))); + IRExpr* ge1 + = unop(Iop_1Uto32, binop(Iop_CmpNE32, get_GEFLAG32(1), mkU32(0))); + IRExpr* ge2 + = unop(Iop_1Uto32, binop(Iop_CmpNE32, get_GEFLAG32(2), mkU32(0))); + IRExpr* ge3 + = unop(Iop_1Uto32, binop(Iop_CmpNE32, get_GEFLAG32(3), mkU32(0))); + IRTemp res3 = newTemp(Ity_I32); + assign(res3, + binop(Iop_Or32, + mkexpr(res2), + binop(Iop_Or32, + binop(Iop_Or32, + binop(Iop_Shl32, ge0, mkU8(16)), + binop(Iop_Shl32, ge1, mkU8(17))), + binop(Iop_Or32, + binop(Iop_Shl32, ge2, mkU8(18)), + binop(Iop_Shl32, ge3, mkU8(19))) ))); + return res3; } -#if 0 -static -ARMCondcode positiveIse_ARMCondcode ( ARMCondcode cond, - Bool* needInvert ) + +/* and the inverse transformation: given an APSR value, + set the NZCV thunk, the Q flag, and the GE flags. */ +static void desynthesise_APSR ( Bool write_nzcvq, Bool write_ge, + IRTemp apsrT, IRTemp condT ) { - vassert(cond >= ARMCondEQ && cond <= ARMCondNV); - if (cond & 1) { - *needInvert = True; - return cond-1; - } else { - *needInvert = False; - return cond; + vassert(write_nzcvq || write_ge); + if (write_nzcvq) { + // Do NZCV + IRTemp immT = newTemp(Ity_I32); + assign(immT, binop(Iop_And32, mkexpr(apsrT), mkU32(0xF0000000)) ); + setFlags_D1(ARMG_CC_OP_COPY, immT, condT); + // Do Q + IRTemp qnewT = newTemp(Ity_I32); + assign(qnewT, binop(Iop_And32, mkexpr(apsrT), mkU32(ARMG_CC_MASK_Q))); + put_QFLAG32(qnewT, condT); + } + if (write_ge) { + // Do GE3..0 + put_GEFLAG32(0, 0, binop(Iop_And32, mkexpr(apsrT), mkU32(1<<16)), + condT); + put_GEFLAG32(1, 0, binop(Iop_And32, mkexpr(apsrT), mkU32(1<<17)), + condT); + put_GEFLAG32(2, 0, binop(Iop_And32, mkexpr(apsrT), mkU32(1<<18)), + condT); + put_GEFLAG32(3, 0, binop(Iop_And32, mkexpr(apsrT), mkU32(1<<19)), + condT); } } -#endif -/* Addressing Mode 1 - DP ops - Addressing Mode 2 - Load/Store word/ubyte (scaled) - */ -static HChar* name_ARMShiftOp ( UChar shift_op, UChar imm_val ) +/*------------------------------------------------------------*/ +/*--- Helpers for saturation ---*/ +/*------------------------------------------------------------*/ + +/* FIXME: absolutely the only diff. between (a) armUnsignedSatQ and + (b) armSignedSatQ is that in (a) the floor is set to 0, whereas in + (b) the floor is computed from the value of imm5. these two fnsn + should be commoned up. */ + +/* UnsignedSatQ(): 'clamp' each value so it lies between 0 <= x <= (2^N)-1 + Optionally return flag resQ saying whether saturation occurred. + See definition in manual, section A2.2.1, page 41 + (bits(N), boolean) UnsignedSatQ( integer i, integer N ) + { + if ( i > (2^N)-1 ) { result = (2^N)-1; saturated = TRUE; } + elsif ( i < 0 ) { result = 0; saturated = TRUE; } + else { result = i; saturated = FALSE; } + return ( result, saturated ); + } +*/ +static void armUnsignedSatQ( IRTemp* res, /* OUT - Ity_I32 */ + IRTemp* resQ, /* OUT - Ity_I32 */ + IRTemp regT, /* value to clamp - Ity_I32 */ + UInt imm5 ) /* saturation ceiling */ { - switch (shift_op) { - case 0x0: case 0x1: case 0x8: return "lsl"; - case 0x2: case 0x3: case 0xA: return "lsr"; - case 0x4: case 0x5: case 0xC: return "asr"; - case 0x6: return (imm_val==0) ? "rrx" : "ror"; - case 0x7: case 0xE: return "ror"; - default: vpanic("name_ARMShiftcode"); + UInt ceil = (1 << imm5) - 1; // (2^imm5)-1 + UInt floor = 0; + + IRTemp node0 = newTemp(Ity_I32); + IRTemp node1 = newTemp(Ity_I32); + IRTemp node2 = newTemp(Ity_I1); + IRTemp node3 = newTemp(Ity_I32); + IRTemp node4 = newTemp(Ity_I32); + IRTemp node5 = newTemp(Ity_I1); + IRTemp node6 = newTemp(Ity_I32); + + assign( node0, mkexpr(regT) ); + assign( node1, mkU32(ceil) ); + assign( node2, binop( Iop_CmpLT32S, mkexpr(node1), mkexpr(node0) ) ); + assign( node3, IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(node2)), + mkexpr(node0), + mkexpr(node1) ) ); + assign( node4, mkU32(floor) ); + assign( node5, binop( Iop_CmpLT32S, mkexpr(node3), mkexpr(node4) ) ); + assign( node6, IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(node5)), + mkexpr(node3), + mkexpr(node4) ) ); + assign( *res, mkexpr(node6) ); + + /* if saturation occurred, then resQ is set to some nonzero value + if sat did not occur, resQ is guaranteed to be zero. */ + if (resQ) { + assign( *resQ, binop(Iop_Xor32, mkexpr(*res), mkexpr(regT)) ); } } -/* Addressing Mode 4 - Load/Store Multiple */ -static HChar* name_ARMAddrMode4 ( UChar mode ) +/* SignedSatQ(): 'clamp' each value so it lies between -2^N <= x <= (2^N) - 1 + Optionally return flag resQ saying whether saturation occurred. + - see definition in manual, section A2.2.1, page 41 + (bits(N), boolean ) SignedSatQ( integer i, integer N ) + { + if ( i > 2^(N-1) - 1 ) { result = 2^(N-1) - 1; saturated = TRUE; } + elsif ( i < -(2^(N-1)) ) { result = -(2^(N-1)); saturated = FALSE; } + else { result = i; saturated = FALSE; } + return ( result[N-1:0], saturated ); + } +*/ +static void armSignedSatQ( IRTemp regT, /* value to clamp - Ity_I32 */ + UInt imm5, /* saturation ceiling */ + IRTemp* res, /* OUT - Ity_I32 */ + IRTemp* resQ ) /* OUT - Ity_I32 */ { - /* See ARM ARM A5-55 for alternative names for stack operations - ldmfa (full ascending), etc. */ - switch (mode) { - case 0x0: return "da"; // Decrement after - case 0x1: return "ia"; // Increment after - case 0x2: return "db"; // Decrement before - case 0x3: return "ib"; // Increment before - default: vpanic("name_ARMAddrMode4"); + Int ceil = (1 << (imm5-1)) - 1; // (2^(imm5-1))-1 + Int floor = -(1 << (imm5-1)); // -(2^(imm5-1)) + + IRTemp node0 = newTemp(Ity_I32); + IRTemp node1 = newTemp(Ity_I32); + IRTemp node2 = newTemp(Ity_I1); + IRTemp node3 = newTemp(Ity_I32); + IRTemp node4 = newTemp(Ity_I32); + IRTemp node5 = newTemp(Ity_I1); + IRTemp node6 = newTemp(Ity_I32); + + assign( node0, mkexpr(regT) ); + assign( node1, mkU32(ceil) ); + assign( node2, binop( Iop_CmpLT32S, mkexpr(node1), mkexpr(node0) ) ); + assign( node3, IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(node2)), + mkexpr(node0), mkexpr(node1) ) ); + assign( node4, mkU32(floor) ); + assign( node5, binop( Iop_CmpLT32S, mkexpr(node3), mkexpr(node4) ) ); + assign( node6, IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(node5)), + mkexpr(node3), mkexpr(node4) ) ); + assign( *res, mkexpr(node6) ); + + /* if saturation occurred, then resQ is set to some nonzero value + if sat did not occur, resQ is guaranteed to be zero. */ + if (resQ) { + assign( *resQ, binop(Iop_Xor32, mkexpr(*res), mkexpr(regT)) ); } } -/* Data Processing ops */ -static HChar* name_ARMDataProcOp ( UChar opc ) + +/* Compute a value 0 :: I32 or 1 :: I32, indicating whether signed + overflow occurred for 32-bit addition. Needs both args and the + result. HD p27. */ +static +IRExpr* signed_overflow_after_Add32 ( IRExpr* resE, + IRTemp argL, IRTemp argR ) { - switch (opc) { - case 0x0: return "and"; - case 0x1: return "eor"; - case 0x2: return "sub"; - case 0x3: return "rsb"; - case 0x4: return "add"; - case 0x5: return "adc"; - case 0x6: return "sbc"; - case 0x7: return "rsc"; - case 0x8: return "tst"; - case 0x9: return "teq"; - case 0xA: return "cmp"; - case 0xB: return "cmn"; - case 0xC: return "orr"; - case 0xD: return "mov"; - case 0xE: return "bic"; - case 0xF: return "mvn"; - default: vpanic("name_ARMDataProcOp"); - } + IRTemp res = newTemp(Ity_I32); + assign(res, resE); + return + binop( Iop_Shr32, + binop( Iop_And32, + binop( Iop_Xor32, mkexpr(res), mkexpr(argL) ), + binop( Iop_Xor32, mkexpr(res), mkexpr(argR) )), + mkU8(31) ); } +/*------------------------------------------------------------*/ +/*--- Larger helpers ---*/ +/*------------------------------------------------------------*/ + +/* Compute both the result and new C flag value for a LSL by an imm5 + or by a register operand. May generate reads of the old C value + (hence only safe to use before any writes to guest state happen). + Are factored out so can be used by both ARM and Thumb. -/* - Addressing mode 4 - LOAD/STORE multiple, LDM|STM - ARM ARM A5-48 + Note that in compute_result_and_C_after_{LSL,LSR,ASR}_by{imm5,reg}, + "res" (the result) is a.k.a. "shop", shifter operand + "newC" (the new C) is a.k.a. "shco", shifter carry out + + The calling convention for res and newC is a bit funny. They could + be passed by value, but instead are passed by ref. */ -static -Bool dis_loadstore_mult ( UInt theInstr ) + +static void compute_result_and_C_after_LSL_by_imm5 ( + /*OUT*/HChar* buf, + IRTemp* res, + IRTemp* newC, + IRTemp rMt, UInt shift_amt, /* operands */ + UInt rM /* only for debug printing */ + ) { - UChar flags = toUChar((theInstr >> 20) & 0x1F); // theInstr[24:20] - UChar Rn_addr = toUChar((theInstr >> 16) & 0xF); - IRTemp Rn = newTemp(Ity_I32); - IRTemp Rn_orig = newTemp(Ity_I32); - UInt reg_list = theInstr & 0xFFFF; // each bit addresses a register: R15 to R0 - - // Load(1) | Store(0) - UChar L = toUChar((flags >> 0) & 1); - // (W)riteback Rn (incr(U=1) | decr(U=0) by n_bytes) - UChar W = toUChar((flags >> 1) & 1); - // Priviledged mode flag - *** CAB TODO *** - UChar S = toUChar((flags >> 2) & 1); - // Txfr ctl: Direction = upwards(1) | downwards(0) - UChar U = toUChar((flags >> 3) & 1); - // Txfr ctl: Rn within(P=1) | outside(P=0) accessed mem - UChar PU = toUChar((flags >> 3) & 3); - - IRTemp start_addr = newTemp(Ity_I32); - IRTemp end_addr = newTemp(Ity_I32); - IRTemp data=0; - UInt n_bytes=0; - UInt tmp_reg = reg_list; - UInt reg_idx, offset; - Bool decode_ok = True; - - HChar* cond_name = name_ARMCondcode( (theInstr >> 28) & 0xF ); - HChar reg_names[70]; - UInt buf_offset; - - while (tmp_reg > 0) { // Count num bits in reg_list => num_bytes - if (tmp_reg & 1) { n_bytes += 4; } - tmp_reg = tmp_reg >> 1; + if (shift_amt == 0) { + if (newC) { + assign( *newC, mk_armg_calculate_flag_c() ); + } + assign( *res, mkexpr(rMt) ); + DIS(buf, "r%u", rM); + } else { + vassert(shift_amt >= 1 && shift_amt <= 31); + if (newC) { + assign( *newC, + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(rMt), + mkU8(32 - shift_amt)), + mkU32(1))); + } + assign( *res, + binop(Iop_Shl32, mkexpr(rMt), mkU8(shift_amt)) ); + DIS(buf, "r%u, LSL #%u", rM, shift_amt); } - - assign( Rn, getIReg(Rn_addr) ); - assign( Rn_orig, mkexpr(Rn) ); - - switch (PU) { // - case 0x0: // Decrement after (DA) - assign( start_addr, binop( Iop_Add32, mkexpr(Rn), mkU32(n_bytes + 4) ) ); - assign( end_addr, mkexpr(Rn) ); - break; - - case 0x1: // Increment after (IA) - assign( start_addr, mkexpr(Rn) ); - assign( end_addr, binop( Iop_Add32, mkexpr(Rn), mkU32(n_bytes - 4) ) ); - break; - - case 0x2: // Decrement before (DB) - assign( start_addr, binop( Iop_Sub32, mkexpr(Rn), mkU32(n_bytes) ) ); - assign( end_addr, binop( Iop_Sub32, mkexpr(Rn), mkU32(4) ) ); - break; - - case 0x3: // Increment before (IB) - assign( start_addr, binop( Iop_Add32, mkexpr(Rn), mkU32(4) ) ); - assign( end_addr, binop( Iop_Add32, mkexpr(Rn), mkU32(n_bytes) ) ); - break; - - default: - vex_printf("dis_loadstore_mult(ARM): No such case: 0x%x", PU); - return False; +} + + +static void compute_result_and_C_after_LSL_by_reg ( + /*OUT*/HChar* buf, + IRTemp* res, + IRTemp* newC, + IRTemp rMt, IRTemp rSt, /* operands */ + UInt rM, UInt rS /* only for debug printing */ + ) +{ + // shift left in range 0 .. 255 + // amt = rS & 255 + // res = amt < 32 ? Rm << amt : 0 + // newC = amt == 0 ? oldC : + // amt in 1..32 ? Rm[32-amt] : 0 + IRTemp amtT = newTemp(Ity_I32); + assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) ); + if (newC) { + /* mux0X(amt == 0, + mux0X(amt < 32, + 0, + Rm[(32-amt) & 31]) + oldC) + */ + /* About the best you can do is pray that iropt is able + to nuke most or all of the following junk. */ + IRTemp oldC = newTemp(Ity_I32); + assign(oldC, mk_armg_calculate_flag_c() ); + assign( + *newC, + IRExpr_Mux0X( + unop(Iop_1Uto8, + binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))), + IRExpr_Mux0X( + unop(Iop_1Uto8, + binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))), + mkU32(0), + binop(Iop_Shr32, + mkexpr(rMt), + unop(Iop_32to8, + binop(Iop_And32, + binop(Iop_Sub32, + mkU32(32), + mkexpr(amtT)), + mkU32(31) + ) + ) + ) + ), + mkexpr(oldC) + ) + ); } + // (Rm << (Rs & 31)) & (((Rs & 255) - 32) >>s 31) + // Lhs of the & limits the shift to 31 bits, so as to + // give known IR semantics. Rhs of the & is all 1s for + // Rs <= 31 and all 0s for Rs >= 32. + assign( + *res, + binop( + Iop_And32, + binop(Iop_Shl32, + mkexpr(rMt), + unop(Iop_32to8, + binop(Iop_And32, mkexpr(rSt), mkU32(31)))), + binop(Iop_Sar32, + binop(Iop_Sub32, + mkexpr(amtT), + mkU32(32)), + mkU8(31)))); + DIS(buf, "r%u, LSL r%u", rM, rS); +} - if (W==1) { - if (U==1) { // upwards - putIReg( Rn_addr, binop( Iop_Add32, mkexpr(Rn), mkU32(n_bytes) ) ); - } else { // downwards - putIReg( Rn_addr, binop( Iop_Sub32, mkexpr(Rn), mkU32(n_bytes) ) ); + +static void compute_result_and_C_after_LSR_by_imm5 ( + /*OUT*/HChar* buf, + IRTemp* res, + IRTemp* newC, + IRTemp rMt, UInt shift_amt, /* operands */ + UInt rM /* only for debug printing */ + ) +{ + if (shift_amt == 0) { + // conceptually a 32-bit shift, however: + // res = 0 + // newC = Rm[31] + if (newC) { + assign( *newC, + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(rMt), mkU8(31)), + mkU32(1))); } - } - - - /* - Loop through register list, LOAD/STORE indicated registers - Lowest numbered reg -> lowest address, so start with lowest register - reg_idx: guest register address - offset : current mem offset from start_addr - */ - reg_names[0] = '\0'; - buf_offset=0; - offset=0; - for (reg_idx=0; reg_idx < 16; reg_idx++) { - if (( reg_list >> reg_idx ) & 1) { // reg_list[i] == 1? - - if (L==1) { // LOAD Ri, (start_addr + offset) - - if (Rn_addr == reg_idx && W==1) { // Undefined - ARM ARM A4-31 - decode_ok=False; - break; - } - - assign( data, loadLE(Ity_I32, binop(Iop_Add32, - mkexpr(start_addr), - mkU32(offset))) ); - if (reg_idx == 15) { - // assuming architecture < 5: See ARM ARM A4-31 - putIReg( reg_idx, binop(Iop_And32, mkexpr(data), mkU32(0xFFFFFFFC)) ); - } else { - putIReg( reg_idx, mkexpr(data) ); - } - } else { // STORE Ri, (start_addr + offset) - - // ARM ARM A4-85 (Operand restrictions) - if (reg_idx == Rn_addr && W==1) { // Rn in reg_list && writeback - if (offset != 0) { // Undefined - See ARM ARM A4-85 - decode_ok=False; - break; - } - // is lowest reg in reg_list: store Rn_orig - storeLE( mkexpr(start_addr), mkexpr(Rn_orig) ); - } else { - storeLE( binop(Iop_Add32, mkexpr(start_addr), mkU32(offset) ), - getIReg(reg_idx) ); - } - } - offset += 4; - - reg_names[buf_offset++] = 'R'; - if (reg_idx > 9) { - reg_names[buf_offset++] = '1'; - reg_names[buf_offset++] = (HChar)toUChar(38 + reg_idx); - } else { - reg_names[buf_offset++] = (HChar)toUChar(48 + reg_idx); - } - reg_names[buf_offset++] = ','; - // CAB: Eugh! Where's strcpy?! + assign( *res, mkU32(0) ); + DIS(buf, "r%u, LSR #0(a.k.a. 32)", rM); + } else { + // shift in range 1..31 + // res = Rm >>u shift_amt + // newC = Rm[shift_amt - 1] + vassert(shift_amt >= 1 && shift_amt <= 31); + if (newC) { + assign( *newC, + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(rMt), + mkU8(shift_amt - 1)), + mkU32(1))); } + assign( *res, + binop(Iop_Shr32, mkexpr(rMt), mkU8(shift_amt)) ); + DIS(buf, "r%u, LSR #%u", rM, shift_amt); } - if (buf_offset > 0) { - reg_names[buf_offset-1] = '\0'; - } - DIP("%s%s%s R%d%s, {%s}%s\n", (L==1) ? "ldm":"stm", cond_name, - name_ARMAddrMode4( PU ), Rn_addr, (W==1) ? "!" : "", - reg_names, (S==1) ? "^" : ""); - - // CAB TODO: - // IR assert( end_addr == (start_addr + offset) - 8 ) - - if (offset == 0) { // Unpredictable - ARM ARM A5-21 - vex_printf("dis_loadstore_mult(arm): Unpredictable - offset==0\n"); - decode_ok = False; - } - - return decode_ok; } +static void compute_result_and_C_after_LSR_by_reg ( + /*OUT*/HChar* buf, + IRTemp* res, + IRTemp* newC, + IRTemp rMt, IRTemp rSt, /* operands */ + UInt rM, UInt rS /* only for debug printing */ + ) +{ + // shift right in range 0 .. 255 + // amt = rS & 255 + // res = amt < 32 ? Rm >>u amt : 0 + // newC = amt == 0 ? oldC : + // amt in 1..32 ? Rm[amt-1] : 0 + IRTemp amtT = newTemp(Ity_I32); + assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) ); + if (newC) { + /* mux0X(amt == 0, + mux0X(amt < 32, + 0, + Rm[(amt-1) & 31]) + oldC) + */ + IRTemp oldC = newTemp(Ity_I32); + assign(oldC, mk_armg_calculate_flag_c() ); + assign( + *newC, + IRExpr_Mux0X( + unop(Iop_1Uto8, + binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))), + IRExpr_Mux0X( + unop(Iop_1Uto8, + binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))), + mkU32(0), + binop(Iop_Shr32, + mkexpr(rMt), + unop(Iop_32to8, + binop(Iop_And32, + binop(Iop_Sub32, + mkexpr(amtT), + mkU32(1)), + mkU32(31) + ) + ) + ) + ), + mkexpr(oldC) + ) + ); + } + // (Rm >>u (Rs & 31)) & (((Rs & 255) - 32) >>s 31) + // Lhs of the & limits the shift to 31 bits, so as to + // give known IR semantics. Rhs of the & is all 1s for + // Rs <= 31 and all 0s for Rs >= 32. + assign( + *res, + binop( + Iop_And32, + binop(Iop_Shr32, + mkexpr(rMt), + unop(Iop_32to8, + binop(Iop_And32, mkexpr(rSt), mkU32(31)))), + binop(Iop_Sar32, + binop(Iop_Sub32, + mkexpr(amtT), + mkU32(32)), + mkU8(31)))); + DIS(buf, "r%u, LSR r%u", rM, rS); +} - -static -Bool dis_loadstore_w_ub_address ( UInt theInstr, IRTemp* address, HChar* buf ) -{ - UChar is_reg = toUChar((theInstr >> 25) & 0x1); - // immediate | register offset/index - UInt flags = (theInstr >> 20) & 0x3F; // theInstr[25:20] - UChar Rn_addr = toUChar((theInstr >> 16) & 0xF); - UChar Rm_addr = toUChar((theInstr >> 00) & 0xF); - UChar shift_op = toUChar((theInstr >> 04) & 0xFF); - UInt offset_12 = (theInstr >> 00) & 0xFFF; - IRTemp Rn = newTemp(Ity_I32); - IRTemp Rm = newTemp(Ity_I32); - UChar shift_imm, shift; - - UChar W = toUChar((flags >> 1) & 1); // base register writeback flag - See *Note - UChar U = toUChar((flags >> 3) & 1); // offset is added(1)|subtracted(0) from the base - UChar P = toUChar((flags >> 4) & 1); // addressing mode flag - See *Note - /* *Note - P==0: post-indexed addressing: addr -> Rn - W==0: normal mem access - W==1: unprivileged mem access - P==1: W==0: offset addressing: Rn not updated - ARM ARM A5-20 - W==1: pre-indexed addressing: addr -> Rn - */ - - IRTemp scaled_index = newTemp(Ity_I32); - IRTemp reg_offset = newTemp(Ity_I32); - - IRTemp oldFlagC = newTemp(Ity_I32); - - HChar buf2[30]; - HChar buf3[20]; - buf3[0] = '\0'; - - if (Rn_addr == 15) { - if (P==1 && W==0) { // offset addressing - // CAB: This right? - assign( Rn, binop(Iop_And32, getIReg(15), mkU32(8)) ); - } else { // Unpredictable - ARM ARM A5-25,29... - vex_printf("dis_loadstore_w_ub_address(arm): Unpredictable - Rn_addr==15\n"); - return False; +static void compute_result_and_C_after_ASR_by_imm5 ( + /*OUT*/HChar* buf, + IRTemp* res, + IRTemp* newC, + IRTemp rMt, UInt shift_amt, /* operands */ + UInt rM /* only for debug printing */ + ) +{ + if (shift_amt == 0) { + // conceptually a 32-bit shift, however: + // res = Rm >>s 31 + // newC = Rm[31] + if (newC) { + assign( *newC, + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(rMt), mkU8(31)), + mkU32(1))); } + assign( *res, binop(Iop_Sar32, mkexpr(rMt), mkU8(31)) ); + DIS(buf, "r%u, ASR #0(a.k.a. 32)", rM); } else { - assign( Rn, getIReg(Rn_addr) ); - } - - /* - Retrieve / Calculate reg_offset - */ - if (is_reg) { - if (Rm_addr == 15) { // Unpredictable - ARM ARM A5-21 - vex_printf("dis_loadstore_w_ub_address(arm): Unpredictable - Rm_addr==15\n"); - return False; - } - if (P==0 || W==1) { // pre|post-indexed addressing - if (Rm_addr == Rn_addr) { // Unpredictable - ARM ARM A5-25 - vex_printf("dis_loadstore_w_ub_address(arm): Unpredictable - Rm_addr==Rn_addr\n"); - return False; - } + // shift in range 1..31 + // res = Rm >>s shift_amt + // newC = Rm[shift_amt - 1] + vassert(shift_amt >= 1 && shift_amt <= 31); + if (newC) { + assign( *newC, + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(rMt), + mkU8(shift_amt - 1)), + mkU32(1))); } - assign( Rm, getIReg(Rm_addr) ); - - if (shift_op == 0) { // Register addressing - assign( reg_offset, mkexpr(Rm) ); - } else { // Scaled Register addressing - shift_imm = toUChar((shift_op >> 3) & 0x1F); - shift = toUChar((shift_op >> 1) & 0x3); - - switch (shift) { - case 0x0: // LSL - assign( scaled_index, binop(Iop_Shl32, mkexpr(Rm), mkU8(shift_imm)) ); - break; - - case 0x1: // LSR - if (shift_imm) { - assign( scaled_index, binop(Iop_Shr32, mkexpr(Rm), mkU8(shift_imm)) ); - } else { - assign( scaled_index, mkU32(0) ); - } - break; - - case 0x2: // ASR - if (shift_imm) { - assign( scaled_index, binop(Iop_Sar32, mkexpr(Rm), mkU32(shift_imm)) ); - } else { - assign( scaled_index, // Rm[31] ? 0xFFFFFFFF : 0x0 - IRExpr_Mux0X(binop(Iop_And32, mkexpr(Rm), mkU32(0x8FFFFFFF)), - mkexpr(0x0), mkexpr(0xFFFFFFFF)) ); - } - break; - - case 0x3: // ROR|RRX - assign( oldFlagC, binop(Iop_Shr32, - mk_armg_calculate_flags_c(), - mkU8(ARMG_CC_SHIFT_C)) ); - - if (shift_imm == 0) { // RRX (ARM ARM A5-17) - // 33 bit ROR using carry flag as the 33rd bit - // op = Rm >> 1, carry flag replacing vacated bit position. - // scaled_index = (c_flag << 31) | (Rm >> 1) - assign( scaled_index, binop(Iop_Or32, - binop(Iop_Shl32, mkexpr(oldFlagC), mkU32(31)), - binop(Iop_Shr32, mkexpr(Rm), mkU8(1))) ); - - } else { // ROR - // scaled_index = Rm ROR shift_imm - // = (Rm >> shift_imm) | (Rm << (32-shift_imm)) - assign( scaled_index, - binop(Iop_Or32, - binop(Iop_Shr32, mkexpr(Rm), mkU8(shift_imm)), - binop(Iop_Shl32, mkexpr(Rm), - binop(Iop_Sub8, mkU8(32), mkU32(shift_imm)))) ); - } - break; - - default: - vex_printf("dis_loadstore_w_ub(ARM): No such case: 0x%x", shift); - return False; - } - assign( reg_offset, mkexpr(scaled_index) ); - - if (shift == 0x3 && shift_imm == 0) { - DIS(buf3, ", %s", name_ARMShiftOp(toUChar(shift_op * 2), shift_imm)); - } else { - DIS(buf3, ", %s #%d", - name_ARMShiftOp(toUChar(shift_op * 2), shift_imm), - shift_imm); - } - } - DIS(buf2, "%cR%d%s", (U==1) ? '+' : '-', Rm_addr, buf3); - } else { // immediate - assign( reg_offset, mkU32(offset_12) ); - - DIS(buf2, "#%c%u", (U==1) ? '+' : '-', offset_12); + assign( *res, + binop(Iop_Sar32, mkexpr(rMt), mkU8(shift_amt)) ); + DIS(buf, "r%u, ASR #%u", rM, shift_amt); } - DIS(buf, "[R%d%s, %s%s", Rn_addr, - (P==0) ? "]" : "", buf2, - (P==1) ? ((W==1) ? "]!" : "]") : ""); - - /* - Depending on P,U,W, write to Rn and set address to load/store - */ - if (P==1) { // offset | pre-indexed addressing - if (U == 1) { // - increment - assign( *address, binop(Iop_Add32, mkexpr(Rn), mkexpr(reg_offset)) ); - } else { // - decrement - assign( *address, binop(Iop_Sub32, mkexpr(Rn), mkexpr(reg_offset)) ); - } - if (W == 1) { // pre-indexed addressing, base register writeback - putIReg( Rn_addr, mkexpr(*address) ); - } - } else { // post-indexed addressing - assign( *address, mkexpr(Rn) ); - if (U == 1) { // - increment - putIReg( Rn_addr, binop( Iop_Add32, mkexpr(Rn), mkexpr(reg_offset) ) ); - } else { // - decrement - putIReg( Rn_addr, binop( Iop_Sub32, mkexpr(Rn), mkexpr(reg_offset) ) ); - } +} + + +static void compute_result_and_C_after_ASR_by_reg ( + /*OUT*/HChar* buf, + IRTemp* res, + IRTemp* newC, + IRTemp rMt, IRTemp rSt, /* operands */ + UInt rM, UInt rS /* only for debug printing */ + ) +{ + // arithmetic shift right in range 0 .. 255 + // amt = rS & 255 + // res = amt < 32 ? Rm >>s amt : Rm >>s 31 + // newC = amt == 0 ? oldC : + // amt in 1..32 ? Rm[amt-1] : Rm[31] + IRTemp amtT = newTemp(Ity_I32); + assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) ); + if (newC) { + /* mux0X(amt == 0, + mux0X(amt < 32, + Rm[31], + Rm[(amt-1) & 31]) + oldC) + */ + IRTemp oldC = newTemp(Ity_I32); + assign(oldC, mk_armg_calculate_flag_c() ); + assign( + *newC, + IRExpr_Mux0X( + unop(Iop_1Uto8, + binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))), + IRExpr_Mux0X( + unop(Iop_1Uto8, + binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))), + binop(Iop_Shr32, + mkexpr(rMt), + mkU8(31) + ), + binop(Iop_Shr32, + mkexpr(rMt), + unop(Iop_32to8, + binop(Iop_And32, + binop(Iop_Sub32, + mkexpr(amtT), + mkU32(1)), + mkU32(31) + ) + ) + ) + ), + mkexpr(oldC) + ) + ); } - return True; + // (Rm >>s (amt > 20) & 0x3F; // theInstr[25:20] - UChar Rn_addr = toUChar((theInstr >> 16) & 0xF); - UChar Rd_addr = toUChar((theInstr >> 12) & 0xF); - IRTemp address = newTemp(Ity_I32); - - UChar L = toUChar((flags >> 0) & 1); // Load(1) | Store(0) - UChar W = toUChar((flags >> 1) & 1); // base register writeback - UChar B = toUChar((flags >> 2) & 1); // access = unsigned byte(1) | word(0) - - IRTemp value = newTemp(Ity_I32); - IRTemp data = newTemp(Ity_I32); - IRTemp data_ror8 = newTemp(Ity_I32); - IRTemp data_ror16 = newTemp(Ity_I32); - IRTemp data_ror24 = newTemp(Ity_I32); - IRExpr* expr_addr_10; - HChar* cond_name = name_ARMCondcode( (theInstr >> 28) & 0xF ); - HChar dis_buf[50]; - - - vassert(((theInstr >> 26) & 0x3) == 0x1); - - // Get the address to load/store - if (!dis_loadstore_w_ub_address(theInstr, &address, dis_buf)) { return False; } - - DIP("%s%s%s R%d, %s\n", (L==1) ? "ldr" : "str", cond_name, - (B==1) ? "b" : "", Rd_addr, dis_buf); - - if (Rd_addr == Rn_addr && W==1) { // Unpredictable - ARM ARM A4-39,41,89,91 - vex_printf("dis_loadstore_w_ub(arm): Unpredictable - Rd_addr==Rn_addr\n"); - return False; - } - - /* - LOAD/STORE Rd, address - */ - if (L==1) { // LOAD - if (B==1) { // unsigned byte (LDRB): ARM ARM A4-40 - if (Rd_addr == 15) { // Unpredictable - ARM ARM A4-40 - vex_printf("dis_loadstore_w_ub(arm): Unpredictable - Rd_addr==15\n"); - return False; - } - putIReg( Rd_addr, loadLE( Ity_I8, mkexpr( address ) ) ); - } - else { // word (LDR): ARM ARM A4-38 - expr_addr_10 = binop(Iop_And32, mkexpr(address), mkU32(0x3)); - - /* - CAB TODO - if (Rd_addr == 15 && address[1:0] == 0) => Unpredictable - How to bomb out using IR? - */ - - /* LOAD memory data (4 bytes) */ - assign( data, loadLE( Ity_I32, mkexpr( address ) ) ); - - // data ROR 8 - assign( data_ror8, binop(Iop_Sub8, mkU8(32), mkU32(8)) ); - assign( data_ror8, - binop( Iop_Or32, - binop( Iop_Shr32, mkexpr(data), mkU8(8) ), - binop( Iop_Shl32, mkexpr(data), mkexpr(data_ror8) ))); - // data ROR 16 - assign( data_ror16, binop(Iop_Sub8, mkU8(32), mkU32(16)) ); - assign( data_ror16, - binop( Iop_Or32, - binop( Iop_Shr32, mkexpr(data), mkU8(16) ), - binop( Iop_Shl32, mkexpr(data), mkexpr(data_ror16) ))); - - // data ROR 24 - assign( data_ror24, binop(Iop_Sub8, mkU8(32), mkU32(24)) ); - assign( data_ror24, - binop( Iop_Or32, - binop( Iop_Shr32, mkexpr(data), mkU8(24) ), - binop( Iop_Shl32, mkexpr(data), mkexpr(data_ror24) ))); - - /* switch (address[1:0]) { - 0x0: value = data; - 0x1: value = data ROR 8; - 0x2: value = data ROR 16; - 0x3: value = data ROR 24; } */ - assign( value, IRExpr_Mux0X( - binop(Iop_CmpEQ32, expr_addr_10, mkU32(0x0)), - IRExpr_Mux0X( - binop(Iop_CmpEQ32, expr_addr_10, mkU32(0x1)), - IRExpr_Mux0X( - binop(Iop_CmpEQ32, expr_addr_10, mkU32(0x2)), - mkexpr(data_ror24), - mkexpr(data_ror16) ), - mkexpr(data_ror8) ), - mkexpr(data) ) ); - - if (Rd_addr == 15) { - // assuming architecture < 5: See ARM ARM A4-28 - putIReg( Rd_addr, binop(Iop_And32, mkexpr(value), mkU32(0xFFFFFFFC)) ); - - // CAB: Need to tell vex we're doing a jump here? - // irsb->jumpkind = Ijk_Boring; - // irsb->next = mkexpr(value); - } else { - putIReg( Rd_addr, mkexpr(value) ); - } - - } - } else { // STORE: ARM ARM A4-88 - if (B==1) { // unsigned byte - if (Rd_addr == 15) { // Unpredictable - ARM ARM A4-90 - vex_printf("dis_loadstore_w_ub(arm): Unpredictable - Rd_addr==15\n"); - return False; - } - storeLE( mkexpr(address), unop(Iop_32to8, getIReg(Rd_addr)) ); // Rd[7:0] - } else { // word - - if (Rd_addr == 15) { // Implementation Defined - ARM ARM A4-88 - vex_printf("dis_loadstore_w_ub(arm): Implementation Defined - Rd_addr==15\n"); - return False; - // CAB TODO: What to do here? - } - storeLE( mkexpr(address), getIReg(Rd_addr) ); - } - } - return True; -} - - +/* Generate an expression corresponding to the immediate-shift case of + a shifter operand. This is used both for ARM and Thumb2. + Bind it to a temporary, and return that via *res. If newC is + non-NULL, also compute a value for the shifter's carry out (in the + LSB of a word), bind it to a temporary, and return that via *shco. + Generates GETs from the guest state and is therefore not safe to + use once we start doing PUTs to it, for any given instruction. + 'how' is encoded thusly: + 00b LSL, 01b LSR, 10b ASR, 11b ROR + Most but not all ARM and Thumb integer insns use this encoding. + Be careful to ensure the right value is passed here. +*/ +static void compute_result_and_C_after_shift_by_imm5 ( + /*OUT*/HChar* buf, + /*OUT*/IRTemp* res, + /*OUT*/IRTemp* newC, + IRTemp rMt, /* reg to shift */ + UInt how, /* what kind of shift */ + UInt shift_amt, /* shift amount (0..31) */ + UInt rM /* only for debug printing */ + ) +{ + vassert(shift_amt < 32); + vassert(how < 4); -/* - ARMG_CC_OP_LSL, ARMG_CC_OP_LSR, ARMG_CC_OP_ASR - ARM ARM A5-9... + switch (how) { - carry = carry_out[0] -*/ -static -IRExpr* dis_shift( Bool* decode_ok, UInt theInstr, IRTemp* carry_out, HChar* buf ) -{ - UChar Rn_addr = toUChar((theInstr >> 16) & 0xF); - UChar Rd_addr = toUChar((theInstr >> 12) & 0xF); - UChar Rs_addr = toUChar((theInstr >> 8) & 0xF); - UChar Rm_addr = toUChar((theInstr >> 0) & 0xF); - UChar by_reg = toUChar((theInstr >> 4) & 0x1); // instr[4] - UChar shift_imm = toUChar((theInstr >> 7) & 0x1F); // instr[11:7] - UChar shift_op = toUChar((theInstr >> 4) & 0xF); // instr[7:4] - IRTemp Rm = newTemp(Ity_I32); - IRTemp Rs = newTemp(Ity_I32); - IRTemp shift_amt = newTemp(Ity_I8); - IRTemp carry_shift = newTemp(Ity_I8); - IRTemp oldFlagC = newTemp(Ity_I32); - IRTemp mux_false = newTemp(Ity_I32); - IRExpr* expr; - IROp op; - - assign( oldFlagC, binop(Iop_Shr32, - mk_armg_calculate_flags_c(), - mkU8(ARMG_CC_SHIFT_C)) ); - - switch (shift_op) { - case 0x0: case 0x8: case 0x1: op = Iop_Shl32; break; - case 0x2: case 0xA: case 0x3: op = Iop_Shr32; break; - case 0x4: case 0xC: case 0x5: op = Iop_Sar32; break; - default: - vex_printf("dis_shift(arm): No such case: 0x%x\n", shift_op); - *decode_ok = False; - return mkU32(0); - } - - - if (by_reg) { // Register Shift - assign( Rm, getIReg(Rm_addr) ); - - if (Rd_addr == 15 || Rm_addr == 15 || - Rn_addr == 15 || Rs_addr == 15) { // Unpredictable (ARM ARM A5-10) - vex_printf("dis_shift(arm): Unpredictable - Rd|Rm|Rn|Rs == R15\n"); - *decode_ok = False; - return mkU32(0); - } - - assign( Rs, getIReg((theInstr >> 8) & 0xF) ); // instr[11:8] - - // shift_amt = shift_expr & 31 => Rs[5:0] - assign( shift_amt, - narrowTo(Ity_I8, binop( Iop_And32, mkexpr(Rs), mkU32(0x1F)) ) ); - - // CAB TODO: support for >31 shift ? (Rs[7:0]) - - switch (shift_op) { - case 0x1: // LSL(reg) - assign( mux_false, mkU32(0) ); - assign( carry_shift, binop(Iop_Add8, mkU8(32), mkexpr(shift_amt)) ); + case 0: + compute_result_and_C_after_LSL_by_imm5( + buf, res, newC, rMt, shift_amt, rM + ); break; - - case 0x3: // LSR(reg) - assign( mux_false, mkU32(0) ); - assign( carry_shift, binop(Iop_Sub8, mkexpr(shift_amt), mkU8(1)) ); + + case 1: + compute_result_and_C_after_LSR_by_imm5( + buf, res, newC, rMt, shift_amt, rM + ); break; - - case 0x5: // ASR(reg) - // Rs[31] == 0 ? 0x0 : 0xFFFFFFFF - assign( mux_false, - IRExpr_Mux0X( - binop(Iop_CmpLT32U, mkexpr(Rs), mkU32(0x80000000)), - mkU32(0xFFFFFFFF), mkU32(0) ) ); - assign( carry_shift, - binop(Iop_Sub8, mkexpr(shift_amt), mkU8(1)) ); + + case 2: + compute_result_and_C_after_ASR_by_imm5( + buf, res, newC, rMt, shift_amt, rM + ); break; - - default: - vex_printf("dis_shift(arm): Reg shift: No such case: 0x%x\n", shift_op); - *decode_ok = False; - return mkU32(0); - } - - expr = IRExpr_Mux0X( - binop(Iop_CmpLT32U, widenUto32(mkexpr(shift_amt)), mkU32(32)), - mkexpr(mux_false), - binop(op, mkexpr(Rm), mkexpr(shift_amt)) ); - - // shift_amt == 0 ? old_flag_c : Rm >> x - assign( *carry_out, - IRExpr_Mux0X( - binop(Iop_CmpEQ8, mkexpr(shift_amt), mkU8(0)), - binop(Iop_Shr32, mkexpr(Rm), mkexpr(carry_shift)), - mkexpr(oldFlagC) ) ); - - DIS(buf, "R%d, %s R%d", Rm_addr, name_ARMShiftOp(shift_op, 0), Rs_addr); - } - else { // Immediate shift - - // CAB: This right? - // "the value used is the address of the current intruction plus 8" - if (Rm_addr == 15 || Rn_addr == 15) { // ARM ARM A5-9 - assign( Rm, binop(Iop_Add32, getIReg(15), mkU32(8)) ); - } else { - assign( Rm, getIReg(Rm_addr) ); - } - - if (shift_imm == 0) { - switch (shift_op) { - case 0x0: case 0x8: // LSL(imm) - expr = mkexpr(Rm); - assign( *carry_out, mkexpr(oldFlagC) ); - break; - - case 0x2: case 0xA: // LSR(imm) - expr = mkexpr(0); - // Rm >> 31: carry = R[0] - assign( *carry_out, binop(Iop_Shr32, mkexpr(Rm), mkU8(31)) ); - break; - - case 0x4: case 0xC: // ASR(imm) - // Rs[31] == 0 ? 0x0 : 0xFFFFFFFF - expr = IRExpr_Mux0X( - binop(Iop_CmpLT32U, mkexpr(Rs), mkU32(0x80000000)), - mkU32(0xFFFFFFFF), mkU32(0) ); - // Rm >> 31: carry = R[0] - assign( *carry_out, binop(Iop_Shr32, mkexpr(Rm), mkU8(31)) ); - break; - - default: - vex_printf("dis_shift(arm): Imm shift: No such case: 0x%x\n", shift_op); - *decode_ok = False; - return mkU32(0); + + case 3: + if (shift_amt == 0) { + IRTemp oldcT = newTemp(Ity_I32); + // rotate right 1 bit through carry (?) + // RRX -- described at ARM ARM A5-17 + // res = (oldC << 31) | (Rm >>u 1) + // newC = Rm[0] + if (newC) { + assign( *newC, + binop(Iop_And32, mkexpr(rMt), mkU32(1))); + } + assign( oldcT, mk_armg_calculate_flag_c() ); + assign( *res, + binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(oldcT), mkU8(31)), + binop(Iop_Shr32, mkexpr(rMt), mkU8(1))) ); + DIS(buf, "r%u, RRX", rM); + } else { + // rotate right in range 1..31 + // res = Rm `ror` shift_amt + // newC = Rm[shift_amt - 1] + vassert(shift_amt >= 1 && shift_amt <= 31); + if (newC) { + assign( *newC, + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(rMt), + mkU8(shift_amt - 1)), + mkU32(1))); + } + assign( *res, + binop(Iop_Or32, + binop(Iop_Shr32, mkexpr(rMt), mkU8(shift_amt)), + binop(Iop_Shl32, mkexpr(rMt), + mkU8(32-shift_amt)))); + DIS(buf, "r%u, ROR #%u", rM, shift_amt); } - DIS(buf, "R%d", Rm_addr); - } else { - expr = binop(op, mkexpr(Rm), mkU8(shift_imm)); - assign( *carry_out, binop(op, mkexpr(Rm), - binop(Iop_Sub32, mkU32(shift_imm), mkU32(1)) ) ); + break; - DIS(buf, "R%d, %s #%d", Rm_addr, name_ARMShiftOp(shift_op, 0), shift_imm); - } + default: + /*NOTREACHED*/ + vassert(0); } - return expr; } +/* Generate an expression corresponding to the register-shift case of + a shifter operand. This is used both for ARM and Thumb2. + Bind it to a temporary, and return that via *res. If newC is + non-NULL, also compute a value for the shifter's carry out (in the + LSB of a word), bind it to a temporary, and return that via *shco. -/* - ARMG_CC_OP_ROR - ARM ARM A5-15,16,17 + Generates GETs from the guest state and is therefore not safe to + use once we start doing PUTs to it, for any given instruction. + + 'how' is encoded thusly: + 00b LSL, 01b LSR, 10b ASR, 11b ROR + Most but not all ARM and Thumb integer insns use this encoding. + Be careful to ensure the right value is passed here. */ -static -IRExpr* dis_rotate ( Bool* decode_ok, UInt theInstr, IRTemp* carry_out, HChar* buf ) -{ - UChar Rn_addr = toUChar((theInstr >> 16) & 0xF); - UChar Rd_addr = toUChar((theInstr >> 12) & 0xF); - UChar Rs_addr = toUChar((theInstr >> 8) & 0xF); - UChar Rm_addr = toUChar((theInstr >> 0) & 0xF); - UChar by_reg = toUChar((theInstr >> 4) & 0x1); // instr[4] - UChar rot_imm = toUChar((theInstr >> 7) & 0x1F); // instr[11:7] - IRTemp Rm = newTemp(Ity_I32); - IRTemp Rs = newTemp(Ity_I32); - IRTemp rot_amt = newTemp(Ity_I8); // Rs[7:0] - IRTemp oldFlagC = newTemp(Ity_I32); - IRExpr* expr=0; - - assign( oldFlagC, binop(Iop_Shr32, - mk_armg_calculate_flags_c(), - mkU8(ARMG_CC_SHIFT_C)) ); - - if (by_reg) { // Register rotate - assign( Rm, getIReg(Rm_addr) ); - - if (Rd_addr == 15 || Rm_addr == 15 || - Rn_addr == 15 || Rs_addr == 15) { // Unpredictable (ARM ARM A5-10) - vex_printf("dis_rotate(arm): Unpredictable - Rd|Rm|Rn|Rs == R15\n"); - *decode_ok = False; - return mkU32(0); - } - - assign( Rs, getIReg((theInstr >> 8) & 0xF) ); // instr[11:8] - // Rs[4:0] - assign( rot_amt, narrowTo(Ity_I8, - binop(Iop_And32, mkexpr(Rs), mkU32(0x1F))) ); - - // CAB: This right? - // Rs[7:0] == 0 ? oldFlagC : (Rs[4:0] == 0 ? Rm >> 31 : Rm >> rot-1 ) - assign( *carry_out, - IRExpr_Mux0X( - binop(Iop_CmpNE32, mkU32(0), - binop(Iop_And32, mkexpr(Rs), mkU32(0xFF))), - mkexpr(oldFlagC), - IRExpr_Mux0X( - binop(Iop_CmpEQ8, mkexpr(rot_amt), mkU8(0)), - binop(Iop_Shr32, mkexpr(Rm), - binop(Iop_Sub8, mkexpr(rot_amt), mkU8(1))), - binop(Iop_Shr32, mkexpr(Rm), - binop(Iop_Shr32, mkexpr(Rm), mkU8(31))) ) ) ); - - - /* expr = (dst0 >> rot_amt) | (dst0 << (wordsize-rot_amt)) */ - expr = binop(Iop_Or32, - binop(Iop_Shr32, mkexpr(Rm), mkexpr(rot_amt)), - binop(Iop_Shl32, mkexpr(Rm), - binop(Iop_Sub8, mkU8(32), mkexpr(rot_amt)))); - - DIS(buf, "R%d, ror R%d", Rm_addr, Rs_addr); - } - else { // Immediate rotate - - // CAB: This right? - // "the value used is the address of the current intruction plus 8" - if (Rm_addr == 15 || Rn_addr == 15) { // ARM ARM A5-9 - assign( Rm, binop(Iop_Add32, getIReg(15), mkU32(8)) ); - } else { - assign( Rm, getIReg(Rm_addr) ); - } - - // Rm >> rot-1: carry = R[0] - assign( *carry_out, binop(Iop_Shr32, mkexpr(Rm), - binop(Iop_Sub8, mkU8(rot_imm), mkU8(1)) ) ); - - if (rot_imm == 0) { // RRX (ARM ARM A5-17) - // 33 bit ROR using carry flag as the 33rd bit - // op = Rm >> 1, carry flag replacing vacated bit position. - - // CAB: This right? - expr = binop(Iop_Or32, - binop(Iop_Shl32, mkexpr(oldFlagC), mkU8(31)), - binop(Iop_Shr32, mkexpr(Rm), mkU8(1))); - DIS(buf, "R%d, rrx", Rm_addr); - } else { - expr = binop(Iop_Or32, - binop(Iop_Shr32, mkexpr(Rm), mkU8(rot_imm)), - binop(Iop_Shl32, mkexpr(Rm), - binop(Iop_Sub8, mkU8(32), mkU8(rot_imm)))); - - DIS(buf, "R%d, ror #%u", Rm_addr, (UInt)rot_imm); +static void compute_result_and_C_after_shift_by_reg ( + /*OUT*/HChar* buf, + /*OUT*/IRTemp* res, + /*OUT*/IRTemp* newC, + IRTemp rMt, /* reg to shift */ + UInt how, /* what kind of shift */ + IRTemp rSt, /* shift amount */ + UInt rM, /* only for debug printing */ + UInt rS /* only for debug printing */ + ) +{ + vassert(how < 4); + switch (how) { + case 0: { /* LSL */ + compute_result_and_C_after_LSL_by_reg( + buf, res, newC, rMt, rSt, rM, rS + ); + break; } + case 1: { /* LSR */ + compute_result_and_C_after_LSR_by_reg( + buf, res, newC, rMt, rSt, rM, rS + ); + break; + } + case 2: { /* ASR */ + compute_result_and_C_after_ASR_by_reg( + buf, res, newC, rMt, rSt, rM, rS + ); + break; + } + case 3: { /* ROR */ + compute_result_and_C_after_ROR_by_reg( + buf, res, newC, rMt, rSt, rM, rS + ); + break; + } + default: + /*NOTREACHED*/ + vassert(0); } - return expr; } +/* Generate an expression corresponding to a shifter_operand, bind it + to a temporary, and return that via *shop. If shco is non-NULL, + also compute a value for the shifter's carry out (in the LSB of a + word), bind it to a temporary, and return that via *shco. + If for some reason we can't come up with a shifter operand (missing + case? not really a shifter operand?) return False. -/* - CAB TODO: - - Not all shifts by 0 leave c_flag unchanged, so guard_expr is more difficult... - assign( flags_guard, binop( Iop_CmpEQ32, mkexpr(shift_amt), mkU32(0) ) ); - setFlags_DEP1_DEP2_shift( ARMG_CC_OP_LSL, Rm, shift_op, flags_guard ); -*/ + Generates GETs from the guest state and is therefore not safe to + use once we start doing PUTs to it, for any given instruction. + For ARM insns only; not for Thumb. +*/ +static Bool mk_shifter_operand ( UInt insn_25, UInt insn_11_0, + /*OUT*/IRTemp* shop, + /*OUT*/IRTemp* shco, + /*OUT*/HChar* buf ) +{ + UInt insn_4 = (insn_11_0 >> 4) & 1; + UInt insn_7 = (insn_11_0 >> 7) & 1; + vassert(insn_25 <= 0x1); + vassert(insn_11_0 <= 0xFFF); + vassert(shop && *shop == IRTemp_INVALID); + *shop = newTemp(Ity_I32); + if (shco) { + vassert(*shco == IRTemp_INVALID); + *shco = newTemp(Ity_I32); + } -/* Addressing mode 1 - Data Processing ops - General syntax: {}{S} , , - Returns expression -*/ -static -IRExpr* dis_shifter_op ( Bool *decode_ok, UInt theInstr, IRTemp* carry_out, HChar* buf ) -{ - UChar is_immed = toUChar((theInstr >> 25) & 1); // immediate / register shift - UChar shift_op = toUChar((theInstr >> 4) & 0xF); // second byte - UInt immed_8, rot_imm; - UInt imm; - IRTemp oldFlagC = newTemp(Ity_I32); - - if (is_immed) { // ARM ARM A5-2 - // dst = src ROR rot << 1 - // = (src >> rot) | (src << (32-rot)); - immed_8 = theInstr & 0xFF; - rot_imm = ((theInstr >> 8) & 0xF) << 1; - imm = (immed_8 >> rot_imm) | (immed_8 << (32-rot_imm)); - - if (rot_imm == 0) { - assign( oldFlagC, binop(Iop_Shr32, - mk_armg_calculate_flags_c(), - mkU8(ARMG_CC_SHIFT_C)) ); - assign( *carry_out, mkexpr(oldFlagC) ); - } else { - assign( *carry_out, binop(Iop_Shr32, mkU32(imm), mkU8(31)) ); - } - DIS(buf, "#%u", imm); - return mkU32(imm); - } else { - - // We shouldn't have any 'op' with bits 4=1 and 7=1 : 1xx1 - switch (shift_op) { - case 0x0: case 0x8: case 0x1: - case 0x2: case 0xA: case 0x3: - case 0x4: case 0xC: case 0x5: - return dis_shift( decode_ok, theInstr, carry_out, buf ); - - case 0x6: case 0xE: case 0x7: - return dis_rotate( decode_ok, theInstr, carry_out, buf ); - - default: // Error: Any other value shouldn't be here. - *decode_ok = False; - vex_printf("dis_shifter_op(arm): shift: No such case: 0x%x\n", shift_op); - return mkU32(0); + /* 32-bit immediate */ + + if (insn_25 == 1) { + /* immediate: (7:0) rotated right by 2 * (11:8) */ + UInt imm = (insn_11_0 >> 0) & 0xFF; + UInt rot = 2 * ((insn_11_0 >> 8) & 0xF); + vassert(rot <= 30); + imm = ROR32(imm, rot); + if (shco) { + if (rot == 0) { + assign( *shco, mk_armg_calculate_flag_c() ); + } else { + assign( *shco, mkU32( (imm >> 31) & 1 ) ); + } } + DIS(buf, "#0x%x", imm); + assign( *shop, mkU32(imm) ); + return True; } -} + /* Shift/rotate by immediate */ + if (insn_25 == 0 && insn_4 == 0) { + /* Rm (3:0) shifted (6:5) by immediate (11:7) */ + UInt shift_amt = (insn_11_0 >> 7) & 0x1F; + UInt rM = (insn_11_0 >> 0) & 0xF; + UInt how = (insn_11_0 >> 5) & 3; + /* how: 00 = Shl, 01 = Shr, 10 = Sar, 11 = Ror */ + IRTemp rMt = newTemp(Ity_I32); + assign(rMt, getIRegA(rM)); + vassert(shift_amt <= 31); - -/* -------------- Helper for DPI's. -------------- -*/ -static -Bool dis_dataproc ( UInt theInstr ) -{ - UChar opc = toUChar((theInstr >> 21) & 0xF); - UChar set_flags = toUChar((theInstr >> 20) & 1); - UChar Rn_addr = toUChar((theInstr >> 16) & 0xF); - UChar Rd_addr = toUChar((theInstr >> 12) & 0xF); - IRTemp Rn = newTemp(Ity_I32); - IRTemp Rd = newTemp(Ity_I32); - IRTemp alu_out = newTemp(Ity_I32); - IRTemp shifter_op = newTemp(Ity_I32); - IRTemp carry_out = newTemp(Ity_I32); - IROp op_set_flags = ARMG_CC_OP_LOGIC; - Bool testing_instr = False; - Bool decode_ok = True; - HChar* cond_name = name_ARMCondcode( (theInstr >> 28) & 0xF ); - HChar* ch_set_flags = (set_flags == 1) ? "S" : ""; - HChar dis_buf[50]; - - assign( shifter_op, dis_shifter_op( &decode_ok, theInstr, &carry_out, dis_buf ) ); - if (!decode_ok) return False; - - assign( Rd, getIReg(Rd_addr) ); - assign( Rn, getIReg(Rn_addr) ); - - - switch (opc) { - case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: - case 0xC: case 0xE: - DIP("%s%s%s R%d, R%d, %s\n", name_ARMDataProcOp(opc), - cond_name, ch_set_flags, Rd_addr, Rn_addr, dis_buf); - break; - case 0x5: case 0x6: case 0x7: - // CAB: Unimplemented - break; - case 0x8: case 0x9: case 0xA: case 0xB: - DIP("%s%s R%d, %s\n", name_ARMDataProcOp(opc), - cond_name, Rn_addr, dis_buf); - break; - case 0xD: case 0xF: - DIP("%s%s%s R%d, %s\n", name_ARMDataProcOp(opc), - cond_name, ch_set_flags, Rd_addr, dis_buf); - break; - default:break; + compute_result_and_C_after_shift_by_imm5( + buf, shop, shco, rMt, how, shift_amt, rM + ); + return True; } + /* Shift/rotate by register */ + if (insn_25 == 0 && insn_4 == 1) { + /* Rm (3:0) shifted (6:5) by Rs (11:8) */ + UInt rM = (insn_11_0 >> 0) & 0xF; + UInt rS = (insn_11_0 >> 8) & 0xF; + UInt how = (insn_11_0 >> 5) & 3; + /* how: 00 = Shl, 01 = Shr, 10 = Sar, 11 = Ror */ + IRTemp rMt = newTemp(Ity_I32); + IRTemp rSt = newTemp(Ity_I32); + + if (insn_7 == 1) + return False; /* not really a shifter operand */ + + assign(rMt, getIRegA(rM)); + assign(rSt, getIRegA(rS)); + + compute_result_and_C_after_shift_by_reg( + buf, shop, shco, rMt, how, rSt, rM, rS + ); + return True; + } - switch (opc) { - case 0x0: // AND - assign( alu_out, binop(Iop_And32, getIReg(Rn_addr), mkexpr(shifter_op)) ); - break; - - case 0x1: // EOR - assign( alu_out, binop(Iop_Xor32, getIReg(Rn_addr), mkexpr(shifter_op)) ); - break; + vex_printf("mk_shifter_operand(0x%x,0x%x)\n", insn_25, insn_11_0 ); + return False; +} - case 0x2: // SUB - assign( alu_out, binop( Iop_Sub32, getIReg(Rn_addr), mkexpr(shifter_op) ) ); - op_set_flags = ARMG_CC_OP_SUB; - break; - case 0x3: // RSB - assign( alu_out, binop( Iop_Sub32, mkexpr(shifter_op), getIReg(Rn_addr) ) ); - op_set_flags = ARMG_CC_OP_SUB; - /* set_flags(), below, switches the args for this case */ - break; +/* ARM only */ +static +IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12, + /*OUT*/HChar* buf ) +{ + vassert(rN < 16); + vassert(bU < 2); + vassert(imm12 < 0x1000); + UChar opChar = bU == 1 ? '+' : '-'; + DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12); + return + binop( (bU == 1 ? Iop_Add32 : Iop_Sub32), + getIRegA(rN), + mkU32(imm12) ); +} - case 0x4: // ADD - assign( alu_out, binop( Iop_Add32, getIReg(Rn_addr), mkexpr(shifter_op) ) ); - op_set_flags = ARMG_CC_OP_ADD; - break; - case 0x5: // ADC // CAB: Unimplemented - case 0x6: // SBC // CAB: Unimplemented - case 0x7: // RSC // CAB: Unimplemented - goto decode_failure; +/* ARM only. + NB: This is "DecodeImmShift" in newer versions of the the ARM ARM. +*/ +static +IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM, + UInt sh2, UInt imm5, + /*OUT*/HChar* buf ) +{ + vassert(rN < 16); + vassert(bU < 2); + vassert(rM < 16); + vassert(sh2 < 4); + vassert(imm5 < 32); + UChar opChar = bU == 1 ? '+' : '-'; + IRExpr* index = NULL; + switch (sh2) { + case 0: /* LSL */ + /* imm5 can be in the range 0 .. 31 inclusive. */ + index = binop(Iop_Shl32, getIRegA(rM), mkU8(imm5)); + DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); + break; + case 1: /* LSR */ + if (imm5 == 0) { + index = mkU32(0); + vassert(0); // ATC + } else { + index = binop(Iop_Shr32, getIRegA(rM), mkU8(imm5)); + } + DIS(buf, "[r%u, %cr%u, LSR #%u]", + rN, opChar, rM, imm5 == 0 ? 32 : imm5); + break; + case 2: /* ASR */ + /* Doesn't this just mean that the behaviour with imm5 == 0 + is the same as if it had been 31 ? */ + if (imm5 == 0) { + index = binop(Iop_Sar32, getIRegA(rM), mkU8(31)); + vassert(0); // ATC + } else { + index = binop(Iop_Sar32, getIRegA(rM), mkU8(imm5)); + } + DIS(buf, "[r%u, %cr%u, ASR #%u]", + rN, opChar, rM, imm5 == 0 ? 32 : imm5); + break; + case 3: /* ROR or RRX */ + if (imm5 == 0) { + IRTemp rmT = newTemp(Ity_I32); + IRTemp cflagT = newTemp(Ity_I32); + assign(rmT, getIRegA(rM)); + assign(cflagT, mk_armg_calculate_flag_c()); + index = binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(cflagT), mkU8(31)), + binop(Iop_Shr32, mkexpr(rmT), mkU8(1))); + DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM); + } else { + IRTemp rmT = newTemp(Ity_I32); + assign(rmT, getIRegA(rM)); + vassert(imm5 >= 1 && imm5 <= 31); + index = binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(rmT), mkU8(32-imm5)), + binop(Iop_Shr32, mkexpr(rmT), mkU8(imm5))); + DIS(buf, "[r%u, %cr%u, ROR #%u]", rN, opChar, rM, imm5); + } + break; + default: + vassert(0); + } + vassert(index); + return binop(bU == 1 ? Iop_Add32 : Iop_Sub32, + getIRegA(rN), index); +} - case 0x8: // TST - vassert(set_flags==1); - assign( alu_out, binop(Iop_And32, getIReg(Rn_addr), mkexpr(shifter_op)) ); - testing_instr = True; - break; - - case 0x9: // TEQ - vassert(set_flags==1); - assign( alu_out, binop(Iop_Xor32, getIReg(Rn_addr), mkexpr(shifter_op)) ); - testing_instr = True; - break; - - case 0xA: // CMP - vassert(set_flags==1); - op_set_flags = ARMG_CC_OP_SUB; - testing_instr = True; - break; - case 0xB: // CMN - vassert(set_flags==1); - op_set_flags = ARMG_CC_OP_ADD; - testing_instr = True; - break; +/* ARM only */ +static +IRExpr* mk_EA_reg_plusminus_imm8 ( UInt rN, UInt bU, UInt imm8, + /*OUT*/HChar* buf ) +{ + vassert(rN < 16); + vassert(bU < 2); + vassert(imm8 < 0x100); + UChar opChar = bU == 1 ? '+' : '-'; + DIS(buf, "[r%u, #%c%u]", rN, opChar, imm8); + return + binop( (bU == 1 ? Iop_Add32 : Iop_Sub32), + getIRegA(rN), + mkU32(imm8) ); +} - case 0xC: // ORR - assign( alu_out, binop(Iop_Or32, getIReg(Rn_addr), mkexpr(shifter_op)) ); - break; - case 0xD: // MOV - assign( alu_out, mkexpr(shifter_op) ); - break; +/* ARM only */ +static +IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM, + /*OUT*/HChar* buf ) +{ + vassert(rN < 16); + vassert(bU < 2); + vassert(rM < 16); + UChar opChar = bU == 1 ? '+' : '-'; + IRExpr* index = getIRegA(rM); + DIS(buf, "[r%u, %c r%u]", rN, opChar, rM); + return binop(bU == 1 ? Iop_Add32 : Iop_Sub32, + getIRegA(rN), index); +} - case 0xE: // BIC - assign( alu_out, binop(Iop_And32, getIReg(Rn_addr), - unop( Iop_Not32, mkexpr(shifter_op))) ); - break; - case 0xF: // MVN - assign( alu_out, unop(Iop_Not32, mkexpr(shifter_op)) ); - break; +/* irRes :: Ity_I32 holds a floating point comparison result encoded + as an IRCmpF64Result. Generate code to convert it to an + ARM-encoded (N,Z,C,V) group in the lowest 4 bits of an I32 value. + Assign a new temp to hold that value, and return the temp. */ +static +IRTemp mk_convert_IRCmpF64Result_to_NZCV ( IRTemp irRes ) +{ + IRTemp ix = newTemp(Ity_I32); + IRTemp termL = newTemp(Ity_I32); + IRTemp termR = newTemp(Ity_I32); + IRTemp nzcv = newTemp(Ity_I32); + + /* This is where the fun starts. We have to convert 'irRes' from + an IR-convention return result (IRCmpF64Result) to an + ARM-encoded (N,Z,C,V) group. The final result is in the bottom + 4 bits of 'nzcv'. */ + /* Map compare result from IR to ARM(nzcv) */ + /* + FP cmp result | IR | ARM(nzcv) + -------------------------------- + UN 0x45 0011 + LT 0x01 1000 + GT 0x00 0010 + EQ 0x40 0110 + */ + /* Now since you're probably wondering WTF .. - default: - decode_failure: - vex_printf("dis_dataproc(arm): unhandled opcode: 0x%x\n", opc); - return False; - } + ix fishes the useful bits out of the IR value, bits 6 and 0, and + places them side by side, giving a number which is 0, 1, 2 or 3. - if (!testing_instr) { - if ( Rd_addr == 15) { // dest reg == PC - // CPSR = SPSR: Unpredictable in User | System mode (no SPSR!) - // Unpredictable - We're only supporting user mode... - vex_printf("dis_dataproc(arm): Unpredictable - Rd_addr==15\n"); - return False; - } - putIReg( Rd_addr, mkexpr(alu_out) ); - } - - if (set_flags) { - if (op_set_flags == ARMG_CC_OP_LOGIC) { - setFlags_DEP1_DEP2( op_set_flags, alu_out, carry_out ); - } else { - if (opc == 0x3) { - setFlags_DEP1_DEP2( op_set_flags, shifter_op, Rn ); - } else { - setFlags_DEP1_DEP2( op_set_flags, Rn, shifter_op ); - } - } - } - return decode_ok; -} + termL is a sequence cooked up by GNU superopt. It converts ix + into an almost correct value NZCV value (incredibly), except + for the case of UN, where it produces 0100 instead of the + required 0011. + termR is therefore a correction term, also computed from ix. It + is 1 in the UN case and 0 for LT, GT and UN. Hence, to get + the final correct value, we subtract termR from termL. + Don't take my word for it. There's a test program at the bottom + of this file, to try this out with. + */ + assign( + ix, + binop(Iop_Or32, + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(irRes), mkU8(5)), + mkU32(3)), + binop(Iop_And32, mkexpr(irRes), mkU32(1)))); + + assign( + termL, + binop(Iop_Add32, + binop(Iop_Shr32, + binop(Iop_Sub32, + binop(Iop_Shl32, + binop(Iop_Xor32, mkexpr(ix), mkU32(1)), + mkU8(30)), + mkU32(1)), + mkU8(29)), + mkU32(1))); + + assign( + termR, + binop(Iop_And32, + binop(Iop_And32, + mkexpr(ix), + binop(Iop_Shr32, mkexpr(ix), mkU8(1))), + mkU32(1))); + + assign(nzcv, binop(Iop_Sub32, mkexpr(termL), mkexpr(termR))); + return nzcv; +} -/* -------------- Helper for Branch. -------------- +/* Thumb32 only. This is "ThumbExpandImm" in the ARM ARM. If + updatesC is non-NULL, a boolean is written to it indicating whether + or not the C flag is updated, as per ARM ARM "ThumbExpandImm_C". */ -static -void dis_branch ( UInt theInstr ) +static UInt thumbExpandImm ( Bool* updatesC, + UInt imm1, UInt imm3, UInt imm8 ) { - UChar link = toUChar((theInstr >> 24) & 1); - UInt signed_immed_24 = theInstr & 0xFFFFFF; - UInt branch_offset; - IRTemp addr = newTemp(Ity_I32); - IRTemp dest = newTemp(Ity_I32); - - if (link) { // LR (R14) = addr of instr after branch instr - assign( addr, binop(Iop_Add32, getIReg(15), mkU32(4)) ); - putIReg( 14, mkexpr(addr) ); + vassert(imm1 < (1<<1)); + vassert(imm3 < (1<<3)); + vassert(imm8 < (1<<8)); + UInt i_imm3_a = (imm1 << 4) | (imm3 << 1) | ((imm8 >> 7) & 1); + UInt abcdefgh = imm8; + UInt lbcdefgh = imm8 | 0x80; + if (updatesC) { + *updatesC = i_imm3_a >= 8; } - - // PC = PC + (SignExtend(signed_immed_24) << 2) - branch_offset = extend_s_24to32( signed_immed_24 ) << 2; - assign( dest, binop(Iop_Add32, getIReg(15), mkU32(branch_offset)) ); - - irsb->jumpkind = link ? Ijk_Call : Ijk_Boring; - irsb->next = mkexpr(dest); - - // Note: Not actually writing to R15 - let the IR stuff do that. - - DIP("b%s%s 0x%x\n", - link ? "l" : "", - name_ARMCondcode( (theInstr >> 28) & 0xF ), - branch_offset); + switch (i_imm3_a) { + case 0: case 1: + return abcdefgh; + case 2: case 3: + return (abcdefgh << 16) | abcdefgh; + case 4: case 5: + return (abcdefgh << 24) | (abcdefgh << 8); + case 6: case 7: + return (abcdefgh << 24) | (abcdefgh << 16) + | (abcdefgh << 8) | abcdefgh; + case 8 ... 31: + return lbcdefgh << (32 - i_imm3_a); + default: + break; + } + /*NOTREACHED*/vassert(0); } +/* Version of thumbExpandImm where we simply feed it the + instruction halfwords (the lowest addressed one is I0). */ +static UInt thumbExpandImm_from_I0_I1 ( Bool* updatesC, + UShort i0s, UShort i1s ) +{ + UInt i0 = (UInt)i0s; + UInt i1 = (UInt)i1s; + UInt imm1 = SLICE_UInt(i0,10,10); + UInt imm3 = SLICE_UInt(i1,14,12); + UInt imm8 = SLICE_UInt(i1,7,0); + return thumbExpandImm(updatesC, imm1, imm3, imm8); +} +/* Thumb16 only. Given the firstcond and mask fields from an IT + instruction, compute the 32-bit ITSTATE value implied, as described + in libvex_guest_arm.h. This is not the ARM ARM representation. + Also produce the t/e chars for the 2nd, 3rd, 4th insns, for + disassembly printing. Returns False if firstcond or mask + denote something invalid. + The number and conditions for the instructions to be + conditionalised depend on firstcond and mask: + mask cond 1 cond 2 cond 3 cond 4 + 1000 fc[3:0] + x100 fc[3:0] fc[3:1]:x + xy10 fc[3:0] fc[3:1]:x fc[3:1]:y + xyz1 fc[3:0] fc[3:1]:x fc[3:1]:y fc[3:1]:z + The condition fields are assembled in *itstate backwards (cond 4 at + the top, cond 1 at the bottom). Conditions are << 4'd and then + ^0xE'd, and those fields that correspond to instructions in the IT + block are tagged with a 1 bit. +*/ +static Bool compute_ITSTATE ( /*OUT*/UInt* itstate, + /*OUT*/UChar* ch1, + /*OUT*/UChar* ch2, + /*OUT*/UChar* ch3, + UInt firstcond, UInt mask ) +{ + vassert(firstcond <= 0xF); + vassert(mask <= 0xF); + *itstate = 0; + *ch1 = *ch2 = *ch3 = '.'; + if (mask == 0) + return False; /* the logic below actually ensures this anyway, + but clearer to make it explicit. */ + if (firstcond == 0xF) + return False; /* NV is not allowed */ + if (firstcond == 0xE && popcount32(mask) != 1) + return False; /* if firstcond is AL then all the rest must be too */ + + UInt m3 = (mask >> 3) & 1; + UInt m2 = (mask >> 2) & 1; + UInt m1 = (mask >> 1) & 1; + UInt m0 = (mask >> 0) & 1; + + UInt fc = (firstcond << 4) | 1/*in-IT-block*/; + UInt ni = (0xE/*AL*/ << 4) | 0/*not-in-IT-block*/; + + if (m3 == 1 && (m2|m1|m0) == 0) { + *itstate = (ni << 24) | (ni << 16) | (ni << 8) | fc; + *itstate ^= 0xE0E0E0E0; + return True; + } + if (m2 == 1 && (m1|m0) == 0) { + *itstate = (ni << 24) | (ni << 16) | (setbit32(fc, 4, m3) << 8) | fc; + *itstate ^= 0xE0E0E0E0; + *ch1 = m3 == (firstcond & 1) ? 't' : 'e'; + return True; + } + if (m1 == 1 && m0 == 0) { + *itstate = (ni << 24) + | (setbit32(fc, 4, m2) << 16) + | (setbit32(fc, 4, m3) << 8) | fc; + *itstate ^= 0xE0E0E0E0; + *ch1 = m3 == (firstcond & 1) ? 't' : 'e'; + *ch2 = m2 == (firstcond & 1) ? 't' : 'e'; + return True; + } + if (m0 == 1) { + *itstate = (setbit32(fc, 4, m1) << 24) + | (setbit32(fc, 4, m2) << 16) + | (setbit32(fc, 4, m3) << 8) | fc; + *itstate ^= 0xE0E0E0E0; + *ch1 = m3 == (firstcond & 1) ? 't' : 'e'; + *ch2 = m2 == (firstcond & 1) ? 't' : 'e'; + *ch3 = m1 == (firstcond & 1) ? 't' : 'e'; + return True; + } + return False; +} +/* Generate IR to do 32-bit bit reversal, a la Hacker's Delight + Chapter 7 Section 1. */ +static IRTemp gen_BITREV ( IRTemp x0 ) +{ + IRTemp x1 = newTemp(Ity_I32); + IRTemp x2 = newTemp(Ity_I32); + IRTemp x3 = newTemp(Ity_I32); + IRTemp x4 = newTemp(Ity_I32); + IRTemp x5 = newTemp(Ity_I32); + UInt c1 = 0x55555555; + UInt c2 = 0x33333333; + UInt c3 = 0x0F0F0F0F; + UInt c4 = 0x00FF00FF; + UInt c5 = 0x0000FFFF; + assign(x1, + binop(Iop_Or32, + binop(Iop_Shl32, + binop(Iop_And32, mkexpr(x0), mkU32(c1)), + mkU8(1)), + binop(Iop_Shr32, + binop(Iop_And32, mkexpr(x0), mkU32(~c1)), + mkU8(1)) + )); + assign(x2, + binop(Iop_Or32, + binop(Iop_Shl32, + binop(Iop_And32, mkexpr(x1), mkU32(c2)), + mkU8(2)), + binop(Iop_Shr32, + binop(Iop_And32, mkexpr(x1), mkU32(~c2)), + mkU8(2)) + )); + assign(x3, + binop(Iop_Or32, + binop(Iop_Shl32, + binop(Iop_And32, mkexpr(x2), mkU32(c3)), + mkU8(4)), + binop(Iop_Shr32, + binop(Iop_And32, mkexpr(x2), mkU32(~c3)), + mkU8(4)) + )); + assign(x4, + binop(Iop_Or32, + binop(Iop_Shl32, + binop(Iop_And32, mkexpr(x3), mkU32(c4)), + mkU8(8)), + binop(Iop_Shr32, + binop(Iop_And32, mkexpr(x3), mkU32(~c4)), + mkU8(8)) + )); + assign(x5, + binop(Iop_Or32, + binop(Iop_Shl32, + binop(Iop_And32, mkexpr(x4), mkU32(c5)), + mkU8(16)), + binop(Iop_Shr32, + binop(Iop_And32, mkexpr(x4), mkU32(~c5)), + mkU8(16)) + )); + return x5; +} -/*------------------------------------------------------------*/ -/*--- Disassemble a single instruction ---*/ -/*------------------------------------------------------------*/ - -/* Disassemble a single instruction into IR. The instruction - is located in host memory at &guest_code[delta]. - Set *size to be the size of the instruction. - If the returned value is Dis_Resteer, - the next guest address is assigned to *whereNext. If resteerOK - is False, disInstr may not return Dis_Resteer. */ - -static DisResult disInstr ( /*IN*/ Bool resteerOK, - /*IN*/ Bool (*resteerOkFn) ( Addr64 ), - /*IN*/ Long delta, - /*OUT*/ Int* size, - /*OUT*/ Addr64* whereNext ) -{ - // IRType ty; - // IRTemp addr, t1, t2; - // Int alen; - UChar opc1, opc2, opc_tmp; //, modrm, abyte; - ARMCondcode cond; - // UInt d32; - // UChar dis_buf[50]; - // Int am_sz, d_sz; - DisResult whatNext = Dis_Continue; - UInt theInstr; - - - /* At least this is simple on ARM: insns are all 4 bytes long, and - 4-aligned. So just fish the whole thing out of memory right now - and have done. */ - - /* We will set *size to 4 if the insn is successfully decoded. - Setting it to 0 by default makes bbToIR_ARM abort if we fail the - decode. */ - *size = 0; +/* Generate IR to do rearrange bytes 3:2:1:0 in a word in to the order + 0:1:2:3 (aka byte-swap). */ +static IRTemp gen_REV ( IRTemp arg ) +{ + IRTemp res = newTemp(Ity_I32); + assign(res, + binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(arg), mkU8(24)), + binop(Iop_Or32, + binop(Iop_And32, binop(Iop_Shl32, mkexpr(arg), mkU8(8)), + mkU32(0x00FF0000)), + binop(Iop_Or32, + binop(Iop_And32, binop(Iop_Shr32, mkexpr(arg), mkU8(8)), + mkU32(0x0000FF00)), + binop(Iop_And32, binop(Iop_Shr32, mkexpr(arg), mkU8(24)), + mkU32(0x000000FF) ) + )))); + return res; +} - theInstr = *(UInt*)(&guest_code[delta]); -// vex_printf("START: 0x%x, %,b\n", theInstr, theInstr ); +/* Generate IR to do rearrange bytes 3:2:1:0 in a word in to the order + 2:3:0:1 (swap within lo and hi halves). */ +static IRTemp gen_REV16 ( IRTemp arg ) +{ + IRTemp res = newTemp(Ity_I32); + assign(res, + binop(Iop_Or32, + binop(Iop_And32, + binop(Iop_Shl32, mkexpr(arg), mkU8(8)), + mkU32(0xFF00FF00)), + binop(Iop_And32, + binop(Iop_Shr32, mkexpr(arg), mkU8(8)), + mkU32(0x00FF00FF)))); + return res; +} - DIP("\t0x%x: ", toUInt(guest_pc_bbstart+delta)); +/*------------------------------------------------------------*/ +/*--- Advanced SIMD (NEON) instructions ---*/ +/*------------------------------------------------------------*/ +/*------------------------------------------------------------*/ +/*--- NEON data processing ---*/ +/*------------------------------------------------------------*/ - // TODO: fix the client-request stuff, else nothing will work +/* For all NEON DP ops, we use the normal scheme to handle conditional + writes to registers -- pass in condT and hand that on to the + put*Reg functions. In ARM mode condT is always IRTemp_INVALID + since NEON is unconditional for ARM. In Thumb mode condT is + derived from the ITSTATE shift register in the normal way. */ - /* Spot the client-request magic sequence. */ - // Essentially a v. unlikely sequence of noops that we can catch - { - UInt* code = (UInt*)(guest_code + delta); - - /* Spot this: - E1A00EE0 mov r0, r0, ror #29 - E1A001E0 mov r0, r0, ror #3 - E1A00DE0 mov r0, r0, ror #27 - E1A002E0 mov r0, r0, ror #5 - E1A006E0 mov r0, r0, ror #13 - E1A009E0 mov r0, r0, ror #19 - */ - /* I suspect these will have to be turned the other way round to - work on little-endian arm. */ - if (code[0] == 0xE1A00EE0 && - code[1] == 0xE1A001E0 && - code[2] == 0xE1A00DE0 && - code[3] == 0xE1A002E0 && - code[4] == 0xE1A006E0 && - code[5] == 0xE1A009E0) { +static +UInt get_neon_d_regno(UInt theInstr) +{ + UInt x = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); + if (theInstr & 0x40) { + if (x & 1) { + x = x + 0x100; + } else { + x = x >> 1; + } + } + return x; +} - // uh ... I'll figure this out later. possibly r0 = client_request(r0) */ - DIP("?CAB? = client_request ( ?CAB? )\n"); - - *size = 24; - - irsb->next = mkU32(toUInt(guest_pc_bbstart+delta)); - irsb->jumpkind = Ijk_ClientReq; - - whatNext = Dis_StopHere; - goto decode_success; +static +UInt get_neon_n_regno(UInt theInstr) +{ + UInt x = ((theInstr >> 3) & 0x10) | ((theInstr >> 16) & 0xF); + if (theInstr & 0x40) { + if (x & 1) { + x = x + 0x100; + } else { + x = x >> 1; } } + return x; +} +static +UInt get_neon_m_regno(UInt theInstr) +{ + UInt x = ((theInstr >> 1) & 0x10) | (theInstr & 0xF); + if (theInstr & 0x40) { + if (x & 1) { + x = x + 0x100; + } else { + x = x >> 1; + } + } + return x; +} +static +Bool dis_neon_vext ( UInt theInstr, IRTemp condT ) +{ + UInt dreg = get_neon_d_regno(theInstr); + UInt mreg = get_neon_m_regno(theInstr); + UInt nreg = get_neon_n_regno(theInstr); + UInt imm4 = (theInstr >> 8) & 0xf; + UInt Q = (theInstr >> 6) & 1; + HChar reg_t = Q ? 'q' : 'd'; + + if (Q) { + putQReg(dreg, triop(Iop_ExtractV128, getQReg(nreg), + getQReg(mreg), mkU8(imm4)), condT); + } else { + putDRegI64(dreg, triop(Iop_Extract64, getDRegI64(nreg), + getDRegI64(mreg), mkU8(imm4)), condT); + } + DIP("vext.8 %c%d, %c%d, %c%d, #%d\n", reg_t, dreg, reg_t, nreg, + reg_t, mreg, imm4); + return True; +} +/* VTBL, VTBX */ +static +Bool dis_neon_vtb ( UInt theInstr, IRTemp condT ) +{ + UInt op = (theInstr >> 6) & 1; + UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); + UInt nreg = get_neon_n_regno(theInstr & ~(1 << 6)); + UInt mreg = get_neon_m_regno(theInstr & ~(1 << 6)); + UInt len = (theInstr >> 8) & 3; + Int i; + IROp cmp; + ULong imm; + IRTemp arg_l; + IRTemp old_mask, new_mask, cur_mask; + IRTemp old_res, new_res; + IRTemp old_arg, new_arg; + + if (dreg >= 0x100 || mreg >= 0x100 || nreg >= 0x100) + return False; + if (nreg + len > 31) + return False; + cmp = Iop_CmpGT8Ux8; + + old_mask = newTemp(Ity_I64); + old_res = newTemp(Ity_I64); + old_arg = newTemp(Ity_I64); + assign(old_mask, mkU64(0)); + assign(old_res, mkU64(0)); + assign(old_arg, getDRegI64(mreg)); + imm = 8; + imm = (imm << 8) | imm; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + + for (i = 0; i <= len; i++) { + arg_l = newTemp(Ity_I64); + new_mask = newTemp(Ity_I64); + cur_mask = newTemp(Ity_I64); + new_res = newTemp(Ity_I64); + new_arg = newTemp(Ity_I64); + assign(arg_l, getDRegI64(nreg+i)); + assign(new_arg, binop(Iop_Sub8x8, mkexpr(old_arg), mkU64(imm))); + assign(cur_mask, binop(cmp, mkU64(imm), mkexpr(old_arg))); + assign(new_mask, binop(Iop_Or64, mkexpr(old_mask), mkexpr(cur_mask))); + assign(new_res, binop(Iop_Or64, + mkexpr(old_res), + binop(Iop_And64, + binop(Iop_Perm8x8, + mkexpr(arg_l), + binop(Iop_And64, + mkexpr(old_arg), + mkexpr(cur_mask))), + mkexpr(cur_mask)))); + + old_arg = new_arg; + old_mask = new_mask; + old_res = new_res; + } + if (op) { + new_res = newTemp(Ity_I64); + assign(new_res, binop(Iop_Or64, + binop(Iop_And64, + getDRegI64(dreg), + unop(Iop_Not64, mkexpr(old_mask))), + mkexpr(old_res))); + old_res = new_res; + } - /* - Deal with condition first - */ - cond = (theInstr >> 28) & 0xF; /* opcode: bits 31:28 */ -// vex_printf("\ndisInstr(arm): cond: 0x%x, %b\n", cond, cond ); - - switch (cond) { - case 0xF: // => Illegal instruction prior to v5 (see ARM ARM A3-5) - vex_printf("disInstr(arm): illegal condition\n"); - goto decode_failure; - - case 0xE: // => Unconditional: go translate the instruction - break; + putDRegI64(dreg, mkexpr(old_res), condT); + DIP("vtb%c.8 d%u, {", op ? 'x' : 'l', dreg); + if (len > 0) { + DIP("d%u-d%u", nreg, nreg + len); + } else { + DIP("d%u", nreg); + } + DIP("}, d%u\n", mreg); + return True; +} - default: - // => Valid condition: translate the condition test first - stmt( IRStmt_Exit( mk_armg_calculate_condition(cond), - Ijk_Boring, - IRConst_U32(toUInt(guest_pc_bbstart+delta+4)) ) ); - //irsb->next = mkU32(guest_pc_bbstart+delta+4); - //irsb->jumpkind = Ijk_Boring; +/* VDUP (scalar) */ +static +Bool dis_neon_vdup ( UInt theInstr, IRTemp condT ) +{ + UInt Q = (theInstr >> 6) & 1; + UInt dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); + UInt mreg = ((theInstr >> 1) & 0x10) | (theInstr & 0xF); + UInt imm4 = (theInstr >> 16) & 0xF; + UInt index; + UInt size; + IRTemp arg_m; + IRTemp res; + IROp op, op2; + + if ((imm4 == 0) || (imm4 == 8)) + return False; + if ((Q == 1) && ((dreg & 1) == 1)) + return False; + if (Q) + dreg >>= 1; + arg_m = newTemp(Ity_I64); + assign(arg_m, getDRegI64(mreg)); + if (Q) + res = newTemp(Ity_V128); + else + res = newTemp(Ity_I64); + if ((imm4 & 1) == 1) { + op = Q ? Iop_Dup8x16 : Iop_Dup8x8; + op2 = Iop_GetElem8x8; + index = imm4 >> 1; + size = 8; + } else if ((imm4 & 3) == 2) { + op = Q ? Iop_Dup16x8 : Iop_Dup16x4; + op2 = Iop_GetElem16x4; + index = imm4 >> 2; + size = 16; + } else if ((imm4 & 7) == 4) { + op = Q ? Iop_Dup32x4 : Iop_Dup32x2; + op2 = Iop_GetElem32x2; + index = imm4 >> 3; + size = 32; + } else { + return False; // can this ever happen? } - + assign(res, unop(op, binop(op2, mkexpr(arg_m), mkU8(index)))); + if (Q) { + putQReg(dreg, mkexpr(res), condT); + } else { + putDRegI64(dreg, mkexpr(res), condT); + } + DIP("vdup.%d %c%d, d%d[%d]\n", size, Q ? 'q' : 'd', dreg, mreg, index); + return True; +} +/* A7.4.1 Three registers of the same length */ +static +Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT ) +{ + UInt Q = (theInstr >> 6) & 1; + UInt dreg = get_neon_d_regno(theInstr); + UInt nreg = get_neon_n_regno(theInstr); + UInt mreg = get_neon_m_regno(theInstr); + UInt A = (theInstr >> 8) & 0xF; + UInt B = (theInstr >> 4) & 1; + UInt C = (theInstr >> 20) & 0x3; + UInt U = (theInstr >> 24) & 1; + UInt size = C; + + IRTemp arg_n; + IRTemp arg_m; + IRTemp res; + + if (Q) { + arg_n = newTemp(Ity_V128); + arg_m = newTemp(Ity_V128); + res = newTemp(Ity_V128); + assign(arg_n, getQReg(nreg)); + assign(arg_m, getQReg(mreg)); + } else { + arg_n = newTemp(Ity_I64); + arg_m = newTemp(Ity_I64); + res = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + assign(arg_m, getDRegI64(mreg)); + } - /* Primary opcode is roughly bits 27:20 (ARM ARM(v2) A3-2) - secondary opcode is bits 4:0 */ - opc1 = toUChar((theInstr >> 20) & 0xFF); /* opcode1: bits 27:20 */ - opc2 = toUChar((theInstr >> 4 ) & 0xF); /* opcode2: bits 7:4 */ -// vex_printf("disInstr(arm): opcode1: 0x%2x, %,09b\n", opc1, opc1 ); -// vex_printf("disInstr(arm): opcode2: 0x%02x, %,04b\n", opc2, opc2 ); - - switch (opc1 >> 4) { // instr[27:24] - case 0x0: - case 0x1: - /* - Multiplies, extra load/store instructions: ARM ARM A3-3 - */ - if ( (opc1 & 0xE0) == 0x0 && (opc2 & 0x9) == 0x9 ) { // 000xxxxx && 1xx1 - if (opc2 == 0x9) { - if ((opc1 & 0x1C) == 0x00) { // multiply (accumulate) - goto decode_failure; - } - if ((opc1 & 0x18) == 0x08) { // multiply (accumulate) long - goto decode_failure; + switch(A) { + case 0: + if (B == 0) { + /* VHADD */ + ULong imm = 0; + IRExpr *imm_val; + IROp addOp; + IROp andOp; + IROp shOp; + char regType = Q ? 'q' : 'd'; + + if (size == 3) + return False; + switch(size) { + case 0: imm = 0x101010101010101LL; break; + case 1: imm = 0x1000100010001LL; break; + case 2: imm = 0x100000001LL; break; + default: vassert(0); } - if ((opc1 & 0x1B) == 0x10) { // swap/swap byte - goto decode_failure; + if (Q) { + imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm)); + andOp = Iop_AndV128; + } else { + imm_val = mkU64(imm); + andOp = Iop_And64; } - } - if ( opc2 == 0xB ) { - if ((opc1 & 0x04) == 0x00) { // load/store 1/2word reg offset - goto decode_failure; - } else { // load/store 1/2word imm offset - goto decode_failure; + if (U) { + switch(size) { + case 0: + addOp = Q ? Iop_Add8x16 : Iop_Add8x8; + shOp = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + break; + case 1: + addOp = Q ? Iop_Add16x8 : Iop_Add16x4; + shOp = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + break; + case 2: + addOp = Q ? Iop_Add32x4 : Iop_Add32x2; + shOp = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + break; + default: + vassert(0); + } + } else { + switch(size) { + case 0: + addOp = Q ? Iop_Add8x16 : Iop_Add8x8; + shOp = Q ? Iop_SarN8x16 : Iop_SarN8x8; + break; + case 1: + addOp = Q ? Iop_Add16x8 : Iop_Add16x4; + shOp = Q ? Iop_SarN16x8 : Iop_SarN16x4; + break; + case 2: + addOp = Q ? Iop_Add32x4 : Iop_Add32x2; + shOp = Q ? Iop_SarN32x4 : Iop_SarN32x2; + break; + default: + vassert(0); + } + } + assign(res, + binop(addOp, + binop(addOp, + binop(shOp, mkexpr(arg_m), mkU8(1)), + binop(shOp, mkexpr(arg_n), mkU8(1))), + binop(shOp, + binop(addOp, + binop(andOp, mkexpr(arg_m), imm_val), + binop(andOp, mkexpr(arg_n), imm_val)), + mkU8(1)))); + DIP("vhadd.%c%d %c%d, %c%d, %c%d\n", + U ? 'u' : 's', 8 << size, regType, + dreg, regType, nreg, regType, mreg); + } else { + /* VQADD */ + IROp op, op2; + IRTemp tmp; + char reg_t = Q ? 'q' : 'd'; + if (Q) { + switch (size) { + case 0: + op = U ? Iop_QAdd8Ux16 : Iop_QAdd8Sx16; + op2 = Iop_Add8x16; + break; + case 1: + op = U ? Iop_QAdd16Ux8 : Iop_QAdd16Sx8; + op2 = Iop_Add16x8; + break; + case 2: + op = U ? Iop_QAdd32Ux4 : Iop_QAdd32Sx4; + op2 = Iop_Add32x4; + break; + case 3: + op = U ? Iop_QAdd64Ux2 : Iop_QAdd64Sx2; + op2 = Iop_Add64x2; + break; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op = U ? Iop_QAdd8Ux8 : Iop_QAdd8Sx8; + op2 = Iop_Add8x8; + break; + case 1: + op = U ? Iop_QAdd16Ux4 : Iop_QAdd16Sx4; + op2 = Iop_Add16x4; + break; + case 2: + op = U ? Iop_QAdd32Ux2 : Iop_QAdd32Sx2; + op2 = Iop_Add32x2; + break; + case 3: + op = U ? Iop_QAdd64Ux1 : Iop_QAdd64Sx1; + op2 = Iop_Add64; + break; + default: + vassert(0); + } + } + if (Q) { + tmp = newTemp(Ity_V128); + } else { + tmp = newTemp(Ity_I64); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); +#ifndef DISABLE_QC_FLAG + assign(tmp, binop(op2, mkexpr(arg_n), mkexpr(arg_m))); + setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT); +#endif + DIP("vqadd.%c%d %c%d, %c%d, %c%d\n", + U ? 'u' : 's', + 8 << size, reg_t, dreg, reg_t, nreg, reg_t, mreg); + } + break; + case 1: + if (B == 0) { + /* VRHADD */ + /* VRHADD C, A, B ::= + C = (A >> 1) + (B >> 1) + (((A & 1) + (B & 1) + 1) >> 1) */ + IROp shift_op, add_op; + IRTemp cc; + ULong one = 1; + HChar reg_t = Q ? 'q' : 'd'; + switch (size) { + case 0: one = (one << 8) | one; /* fall through */ + case 1: one = (one << 16) | one; /* fall through */ + case 2: one = (one << 32) | one; break; + case 3: return False; + default: vassert(0); + } + if (Q) { + switch (size) { + case 0: + shift_op = U ? Iop_ShrN8x16 : Iop_SarN8x16; + add_op = Iop_Add8x16; + break; + case 1: + shift_op = U ? Iop_ShrN16x8 : Iop_SarN16x8; + add_op = Iop_Add16x8; + break; + case 2: + shift_op = U ? Iop_ShrN32x4 : Iop_SarN32x4; + add_op = Iop_Add32x4; + break; + case 3: + return False; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + shift_op = U ? Iop_ShrN8x8 : Iop_SarN8x8; + add_op = Iop_Add8x8; + break; + case 1: + shift_op = U ? Iop_ShrN16x4 : Iop_SarN16x4; + add_op = Iop_Add16x4; + break; + case 2: + shift_op = U ? Iop_ShrN32x2 : Iop_SarN32x2; + add_op = Iop_Add32x2; + break; + case 3: + return False; + default: + vassert(0); + } + } + if (Q) { + cc = newTemp(Ity_V128); + assign(cc, binop(shift_op, + binop(add_op, + binop(add_op, + binop(Iop_AndV128, + mkexpr(arg_n), + binop(Iop_64HLtoV128, + mkU64(one), + mkU64(one))), + binop(Iop_AndV128, + mkexpr(arg_m), + binop(Iop_64HLtoV128, + mkU64(one), + mkU64(one)))), + binop(Iop_64HLtoV128, + mkU64(one), + mkU64(one))), + mkU8(1))); + assign(res, binop(add_op, + binop(add_op, + binop(shift_op, + mkexpr(arg_n), + mkU8(1)), + binop(shift_op, + mkexpr(arg_m), + mkU8(1))), + mkexpr(cc))); + } else { + cc = newTemp(Ity_I64); + assign(cc, binop(shift_op, + binop(add_op, + binop(add_op, + binop(Iop_And64, + mkexpr(arg_n), + mkU64(one)), + binop(Iop_And64, + mkexpr(arg_m), + mkU64(one))), + mkU64(one)), + mkU8(1))); + assign(res, binop(add_op, + binop(add_op, + binop(shift_op, + mkexpr(arg_n), + mkU8(1)), + binop(shift_op, + mkexpr(arg_m), + mkU8(1))), + mkexpr(cc))); + } + DIP("vrhadd.%c%d %c%d, %c%d, %c%d\n", + U ? 'u' : 's', + 8 << size, reg_t, dreg, reg_t, nreg, reg_t, mreg); + } else { + if (U == 0) { + switch(C) { + case 0: { + /* VAND */ + HChar reg_t = Q ? 'q' : 'd'; + if (Q) { + assign(res, binop(Iop_AndV128, mkexpr(arg_n), + mkexpr(arg_m))); + } else { + assign(res, binop(Iop_And64, mkexpr(arg_n), + mkexpr(arg_m))); + } + DIP("vand %c%d, %c%d, %c%d\n", + reg_t, dreg, reg_t, nreg, reg_t, mreg); + break; + } + case 1: { + /* VBIC */ + HChar reg_t = Q ? 'q' : 'd'; + if (Q) { + assign(res, binop(Iop_AndV128,mkexpr(arg_n), + unop(Iop_NotV128, mkexpr(arg_m)))); + } else { + assign(res, binop(Iop_And64, mkexpr(arg_n), + unop(Iop_Not64, mkexpr(arg_m)))); + } + DIP("vbic %c%d, %c%d, %c%d\n", + reg_t, dreg, reg_t, nreg, reg_t, mreg); + break; + } + case 2: + if ( nreg != mreg) { + /* VORR */ + HChar reg_t = Q ? 'q' : 'd'; + if (Q) { + assign(res, binop(Iop_OrV128, mkexpr(arg_n), + mkexpr(arg_m))); + } else { + assign(res, binop(Iop_Or64, mkexpr(arg_n), + mkexpr(arg_m))); + } + DIP("vorr %c%d, %c%d, %c%d\n", + reg_t, dreg, reg_t, nreg, reg_t, mreg); + } else { + /* VMOV */ + HChar reg_t = Q ? 'q' : 'd'; + assign(res, mkexpr(arg_m)); + DIP("vmov %c%d, %c%d\n", reg_t, dreg, reg_t, mreg); + } + break; + case 3:{ + /* VORN */ + HChar reg_t = Q ? 'q' : 'd'; + if (Q) { + assign(res, binop(Iop_OrV128,mkexpr(arg_n), + unop(Iop_NotV128, mkexpr(arg_m)))); + } else { + assign(res, binop(Iop_Or64, mkexpr(arg_n), + unop(Iop_Not64, mkexpr(arg_m)))); + } + DIP("vorn %c%d, %c%d, %c%d\n", + reg_t, dreg, reg_t, nreg, reg_t, mreg); + break; + } + } + } else { + switch(C) { + case 0: + /* VEOR (XOR) */ + if (Q) { + assign(res, binop(Iop_XorV128, mkexpr(arg_n), + mkexpr(arg_m))); + } else { + assign(res, binop(Iop_Xor64, mkexpr(arg_n), + mkexpr(arg_m))); + } + DIP("veor %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + break; + case 1: + /* VBSL */ + if (Q) { + IRTemp reg_d = newTemp(Ity_V128); + assign(reg_d, getQReg(dreg)); + assign(res, + binop(Iop_OrV128, + binop(Iop_AndV128, mkexpr(arg_n), + mkexpr(reg_d)), + binop(Iop_AndV128, + mkexpr(arg_m), + unop(Iop_NotV128, + mkexpr(reg_d)) ) ) ); + } else { + IRTemp reg_d = newTemp(Ity_I64); + assign(reg_d, getDRegI64(dreg)); + assign(res, + binop(Iop_Or64, + binop(Iop_And64, mkexpr(arg_n), + mkexpr(reg_d)), + binop(Iop_And64, + mkexpr(arg_m), + unop(Iop_Not64, mkexpr(reg_d))))); + } + DIP("vbsl %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + break; + case 2: + /* VBIT */ + if (Q) { + IRTemp reg_d = newTemp(Ity_V128); + assign(reg_d, getQReg(dreg)); + assign(res, + binop(Iop_OrV128, + binop(Iop_AndV128, mkexpr(arg_n), + mkexpr(arg_m)), + binop(Iop_AndV128, + mkexpr(reg_d), + unop(Iop_NotV128, mkexpr(arg_m))))); + } else { + IRTemp reg_d = newTemp(Ity_I64); + assign(reg_d, getDRegI64(dreg)); + assign(res, + binop(Iop_Or64, + binop(Iop_And64, mkexpr(arg_n), + mkexpr(arg_m)), + binop(Iop_And64, + mkexpr(reg_d), + unop(Iop_Not64, mkexpr(arg_m))))); + } + DIP("vbit %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + break; + case 3: + /* VBIF */ + if (Q) { + IRTemp reg_d = newTemp(Ity_V128); + assign(reg_d, getQReg(dreg)); + assign(res, + binop(Iop_OrV128, + binop(Iop_AndV128, mkexpr(reg_d), + mkexpr(arg_m)), + binop(Iop_AndV128, + mkexpr(arg_n), + unop(Iop_NotV128, mkexpr(arg_m))))); + } else { + IRTemp reg_d = newTemp(Ity_I64); + assign(reg_d, getDRegI64(dreg)); + assign(res, + binop(Iop_Or64, + binop(Iop_And64, mkexpr(reg_d), + mkexpr(arg_m)), + binop(Iop_And64, + mkexpr(arg_n), + unop(Iop_Not64, mkexpr(arg_m))))); + } + DIP("vbif %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + break; + } + } + } + break; + case 2: + if (B == 0) { + /* VHSUB */ + /* (A >> 1) - (B >> 1) - (NOT (A) & B & 1) */ + ULong imm = 0; + IRExpr *imm_val; + IROp subOp; + IROp notOp; + IROp andOp; + IROp shOp; + if (size == 3) + return False; + switch(size) { + case 0: imm = 0x101010101010101LL; break; + case 1: imm = 0x1000100010001LL; break; + case 2: imm = 0x100000001LL; break; + default: vassert(0); + } + if (Q) { + imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm)); + andOp = Iop_AndV128; + notOp = Iop_NotV128; + } else { + imm_val = mkU64(imm); + andOp = Iop_And64; + notOp = Iop_Not64; + } + if (U) { + switch(size) { + case 0: + subOp = Q ? Iop_Sub8x16 : Iop_Sub8x8; + shOp = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + break; + case 1: + subOp = Q ? Iop_Sub16x8 : Iop_Sub16x4; + shOp = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + break; + case 2: + subOp = Q ? Iop_Sub32x4 : Iop_Sub32x2; + shOp = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + break; + default: + vassert(0); + } + } else { + switch(size) { + case 0: + subOp = Q ? Iop_Sub8x16 : Iop_Sub8x8; + shOp = Q ? Iop_SarN8x16 : Iop_SarN8x8; + break; + case 1: + subOp = Q ? Iop_Sub16x8 : Iop_Sub16x4; + shOp = Q ? Iop_SarN16x8 : Iop_SarN16x4; + break; + case 2: + subOp = Q ? Iop_Sub32x4 : Iop_Sub32x2; + shOp = Q ? Iop_SarN32x4 : Iop_SarN32x2; + break; + default: + vassert(0); + } + } + assign(res, + binop(subOp, + binop(subOp, + binop(shOp, mkexpr(arg_n), mkU8(1)), + binop(shOp, mkexpr(arg_m), mkU8(1))), + binop(andOp, + binop(andOp, + unop(notOp, mkexpr(arg_n)), + mkexpr(arg_m)), + imm_val))); + DIP("vhsub.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } else { + /* VQSUB */ + IROp op, op2; + IRTemp tmp; + if (Q) { + switch (size) { + case 0: + op = U ? Iop_QSub8Ux16 : Iop_QSub8Sx16; + op2 = Iop_Sub8x16; + break; + case 1: + op = U ? Iop_QSub16Ux8 : Iop_QSub16Sx8; + op2 = Iop_Sub16x8; + break; + case 2: + op = U ? Iop_QSub32Ux4 : Iop_QSub32Sx4; + op2 = Iop_Sub32x4; + break; + case 3: + op = U ? Iop_QSub64Ux2 : Iop_QSub64Sx2; + op2 = Iop_Sub64x2; + break; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op = U ? Iop_QSub8Ux8 : Iop_QSub8Sx8; + op2 = Iop_Sub8x8; + break; + case 1: + op = U ? Iop_QSub16Ux4 : Iop_QSub16Sx4; + op2 = Iop_Sub16x4; + break; + case 2: + op = U ? Iop_QSub32Ux2 : Iop_QSub32Sx2; + op2 = Iop_Sub32x2; + break; + case 3: + op = U ? Iop_QSub64Ux1 : Iop_QSub64Sx1; + op2 = Iop_Sub64; + break; + default: + vassert(0); + } + } + if (Q) + tmp = newTemp(Ity_V128); + else + tmp = newTemp(Ity_I64); + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); +#ifndef DISABLE_QC_FLAG + assign(tmp, binop(op2, mkexpr(arg_n), mkexpr(arg_m))); + setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT); +#endif + DIP("vqsub.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } + break; + case 3: { + IROp op; + if (Q) { + switch (size) { + case 0: op = U ? Iop_CmpGT8Ux16 : Iop_CmpGT8Sx16; break; + case 1: op = U ? Iop_CmpGT16Ux8 : Iop_CmpGT16Sx8; break; + case 2: op = U ? Iop_CmpGT32Ux4 : Iop_CmpGT32Sx4; break; + case 3: return False; + default: vassert(0); + } + } else { + switch (size) { + case 0: op = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8; break; + case 1: op = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4; break; + case 2: op = U ? Iop_CmpGT32Ux2: Iop_CmpGT32Sx2; break; + case 3: return False; + default: vassert(0); + } + } + if (B == 0) { + /* VCGT */ + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vcgt.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } else { + /* VCGE */ + /* VCGE res, argn, argm + is equal to + VCGT tmp, argm, argn + VNOT res, tmp */ + assign(res, + unop(Q ? Iop_NotV128 : Iop_Not64, + binop(op, mkexpr(arg_m), mkexpr(arg_n)))); + DIP("vcge.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } + } + break; + case 4: + if (B == 0) { + /* VSHL */ + IROp op, sub_op; + IRTemp tmp; + if (U) { + switch (size) { + case 0: op = Q ? Iop_Shl8x16 : Iop_Shl8x8; break; + case 1: op = Q ? Iop_Shl16x8 : Iop_Shl16x4; break; + case 2: op = Q ? Iop_Shl32x4 : Iop_Shl32x2; break; + case 3: op = Q ? Iop_Shl64x2 : Iop_Shl64; break; + default: vassert(0); + } + } else { + tmp = newTemp(Q ? Ity_V128 : Ity_I64); + switch (size) { + case 0: + op = Q ? Iop_Sar8x16 : Iop_Sar8x8; + sub_op = Q ? Iop_Sub8x16 : Iop_Sub8x8; + break; + case 1: + op = Q ? Iop_Sar16x8 : Iop_Sar16x4; + sub_op = Q ? Iop_Sub16x8 : Iop_Sub16x4; + break; + case 2: + op = Q ? Iop_Sar32x4 : Iop_Sar32x2; + sub_op = Q ? Iop_Sub32x4 : Iop_Sub32x2; + break; + case 3: + op = Q ? Iop_Sar64x2 : Iop_Sar64; + sub_op = Q ? Iop_Sub64x2 : Iop_Sub64; + break; + default: + vassert(0); + } + } + if (U) { + if (!Q && (size == 3)) + assign(res, binop(op, mkexpr(arg_m), + unop(Iop_64to8, mkexpr(arg_n)))); + else + assign(res, binop(op, mkexpr(arg_m), mkexpr(arg_n))); + } else { + if (Q) + assign(tmp, binop(sub_op, + binop(Iop_64HLtoV128, mkU64(0), mkU64(0)), + mkexpr(arg_n))); + else + assign(tmp, binop(sub_op, mkU64(0), mkexpr(arg_n))); + if (!Q && (size == 3)) + assign(res, binop(op, mkexpr(arg_m), + unop(Iop_64to8, mkexpr(tmp)))); + else + assign(res, binop(op, mkexpr(arg_m), mkexpr(tmp))); + } + DIP("vshl.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd', + nreg); + } else { + /* VQSHL */ + IROp op, op_rev, op_shrn, op_shln, cmp_neq, cmp_gt; + IRTemp tmp, shval, mask, old_shval; + UInt i; + ULong esize; + cmp_neq = Q ? Iop_CmpNEZ8x16 : Iop_CmpNEZ8x8; + cmp_gt = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; + if (U) { + switch (size) { + case 0: + op = Q ? Iop_QShl8x16 : Iop_QShl8x8; + op_rev = Q ? Iop_Shr8x16 : Iop_Shr8x8; + op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; + break; + case 1: + op = Q ? Iop_QShl16x8 : Iop_QShl16x4; + op_rev = Q ? Iop_Shr16x8 : Iop_Shr16x4; + op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; + break; + case 2: + op = Q ? Iop_QShl32x4 : Iop_QShl32x2; + op_rev = Q ? Iop_Shr32x4 : Iop_Shr32x2; + op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; + break; + case 3: + op = Q ? Iop_QShl64x2 : Iop_QShl64x1; + op_rev = Q ? Iop_Shr64x2 : Iop_Shr64; + op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; + op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64; + break; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op = Q ? Iop_QSal8x16 : Iop_QSal8x8; + op_rev = Q ? Iop_Sar8x16 : Iop_Sar8x8; + op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; + break; + case 1: + op = Q ? Iop_QSal16x8 : Iop_QSal16x4; + op_rev = Q ? Iop_Sar16x8 : Iop_Sar16x4; + op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; + break; + case 2: + op = Q ? Iop_QSal32x4 : Iop_QSal32x2; + op_rev = Q ? Iop_Sar32x4 : Iop_Sar32x2; + op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; + break; + case 3: + op = Q ? Iop_QSal64x2 : Iop_QSal64x1; + op_rev = Q ? Iop_Sar64x2 : Iop_Sar64; + op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; + op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64; + break; + default: + vassert(0); + } + } + if (Q) { + tmp = newTemp(Ity_V128); + shval = newTemp(Ity_V128); + mask = newTemp(Ity_V128); + } else { + tmp = newTemp(Ity_I64); + shval = newTemp(Ity_I64); + mask = newTemp(Ity_I64); + } + assign(res, binop(op, mkexpr(arg_m), mkexpr(arg_n))); +#ifndef DISABLE_QC_FLAG + /* Only least significant byte from second argument is used. + Copy this byte to the whole vector element. */ + assign(shval, binop(op_shrn, + binop(op_shln, + mkexpr(arg_n), + mkU8((8 << size) - 8)), + mkU8((8 << size) - 8))); + for(i = 0; i < size; i++) { + old_shval = shval; + shval = newTemp(Q ? Ity_V128 : Ity_I64); + assign(shval, binop(Q ? Iop_OrV128 : Iop_Or64, + mkexpr(old_shval), + binop(op_shln, + mkexpr(old_shval), + mkU8(8 << i)))); + } + /* If shift is greater or equal to the element size and + element is non-zero, then QC flag should be set. */ + esize = (8 << size) - 1; + esize = (esize << 8) | esize; + esize = (esize << 16) | esize; + esize = (esize << 32) | esize; + setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64, + binop(cmp_gt, mkexpr(shval), + Q ? mkU128(esize) : mkU64(esize)), + unop(cmp_neq, mkexpr(arg_m))), + Q ? mkU128(0) : mkU64(0), + Q, condT); + /* Othervise QC flag should be set if shift value is positive and + result beign rightshifted the same value is not equal to left + argument. */ + assign(mask, binop(cmp_gt, mkexpr(shval), + Q ? mkU128(0) : mkU64(0))); + if (!Q && size == 3) + assign(tmp, binop(op_rev, mkexpr(res), + unop(Iop_64to8, mkexpr(arg_n)))); + else + assign(tmp, binop(op_rev, mkexpr(res), mkexpr(arg_n))); + setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(tmp), mkexpr(mask)), + binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(arg_m), mkexpr(mask)), + Q, condT); +#endif + DIP("vqshl.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd', + nreg); + } + break; + case 5: + if (B == 0) { + /* VRSHL */ + IROp op, op_shrn, op_shln, cmp_gt, op_sub, op_add; + IRTemp shval, old_shval, imm_val, round; + UInt i; + ULong imm; + cmp_gt = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; + imm = 1L; + switch (size) { + case 0: imm = (imm << 8) | imm; /* fall through */ + case 1: imm = (imm << 16) | imm; /* fall through */ + case 2: imm = (imm << 32) | imm; /* fall through */ + case 3: break; + default: vassert(0); + } + imm_val = newTemp(Q ? Ity_V128 : Ity_I64); + round = newTemp(Q ? Ity_V128 : Ity_I64); + assign(imm_val, Q ? mkU128(imm) : mkU64(imm)); + if (U) { + switch (size) { + case 0: + op = Q ? Iop_Shl8x16 : Iop_Shl8x8; + op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; + op_add = Q ? Iop_Add8x16 : Iop_Add8x8; + op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; + break; + case 1: + op = Q ? Iop_Shl16x8 : Iop_Shl16x4; + op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; + op_add = Q ? Iop_Add16x8 : Iop_Add16x4; + op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; + break; + case 2: + op = Q ? Iop_Shl32x4 : Iop_Shl32x2; + op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; + op_add = Q ? Iop_Add32x4 : Iop_Add32x2; + op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; + break; + case 3: + op = Q ? Iop_Shl64x2 : Iop_Shl64; + op_sub = Q ? Iop_Sub64x2 : Iop_Sub64; + op_add = Q ? Iop_Add64x2 : Iop_Add64; + op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; + op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64; + break; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op = Q ? Iop_Sal8x16 : Iop_Sal8x8; + op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; + op_add = Q ? Iop_Add8x16 : Iop_Add8x8; + op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; + break; + case 1: + op = Q ? Iop_Sal16x8 : Iop_Sal16x4; + op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; + op_add = Q ? Iop_Add16x8 : Iop_Add16x4; + op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; + break; + case 2: + op = Q ? Iop_Sal32x4 : Iop_Sal32x2; + op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; + op_add = Q ? Iop_Add32x4 : Iop_Add32x2; + op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; + break; + case 3: + op = Q ? Iop_Sal64x2 : Iop_Sal64x1; + op_sub = Q ? Iop_Sub64x2 : Iop_Sub64; + op_add = Q ? Iop_Add64x2 : Iop_Add64; + op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; + op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64; + break; + default: + vassert(0); + } + } + if (Q) { + shval = newTemp(Ity_V128); + } else { + shval = newTemp(Ity_I64); + } + /* Only least significant byte from second argument is used. + Copy this byte to the whole vector element. */ + assign(shval, binop(op_shrn, + binop(op_shln, + mkexpr(arg_n), + mkU8((8 << size) - 8)), + mkU8((8 << size) - 8))); + for (i = 0; i < size; i++) { + old_shval = shval; + shval = newTemp(Q ? Ity_V128 : Ity_I64); + assign(shval, binop(Q ? Iop_OrV128 : Iop_Or64, + mkexpr(old_shval), + binop(op_shln, + mkexpr(old_shval), + mkU8(8 << i)))); + } + /* Compute the result */ + if (!Q && size == 3 && U) { + assign(round, binop(Q ? Iop_AndV128 : Iop_And64, + binop(op, + mkexpr(arg_m), + unop(Iop_64to8, + binop(op_add, + mkexpr(arg_n), + mkexpr(imm_val)))), + binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(imm_val), + binop(cmp_gt, + Q ? mkU128(0) : mkU64(0), + mkexpr(arg_n))))); + assign(res, binop(op_add, + binop(op, + mkexpr(arg_m), + unop(Iop_64to8, mkexpr(arg_n))), + mkexpr(round))); + } else { + assign(round, binop(Q ? Iop_AndV128 : Iop_And64, + binop(op, + mkexpr(arg_m), + binop(op_add, + mkexpr(arg_n), + mkexpr(imm_val))), + binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(imm_val), + binop(cmp_gt, + Q ? mkU128(0) : mkU64(0), + mkexpr(arg_n))))); + assign(res, binop(op_add, + binop(op, mkexpr(arg_m), mkexpr(arg_n)), + mkexpr(round))); + } + DIP("vrshl.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd', + nreg); + } else { + /* VQRSHL */ + IROp op, op_rev, op_shrn, op_shln, cmp_neq, cmp_gt, op_sub, op_add; + IRTemp tmp, shval, mask, old_shval, imm_val, round; + UInt i; + ULong esize, imm; + cmp_neq = Q ? Iop_CmpNEZ8x16 : Iop_CmpNEZ8x8; + cmp_gt = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; + imm = 1L; + switch (size) { + case 0: imm = (imm << 8) | imm; /* fall through */ + case 1: imm = (imm << 16) | imm; /* fall through */ + case 2: imm = (imm << 32) | imm; /* fall through */ + case 3: break; + default: vassert(0); + } + imm_val = newTemp(Q ? Ity_V128 : Ity_I64); + round = newTemp(Q ? Ity_V128 : Ity_I64); + assign(imm_val, Q ? mkU128(imm) : mkU64(imm)); + if (U) { + switch (size) { + case 0: + op = Q ? Iop_QShl8x16 : Iop_QShl8x8; + op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; + op_add = Q ? Iop_Add8x16 : Iop_Add8x8; + op_rev = Q ? Iop_Shr8x16 : Iop_Shr8x8; + op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; + break; + case 1: + op = Q ? Iop_QShl16x8 : Iop_QShl16x4; + op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; + op_add = Q ? Iop_Add16x8 : Iop_Add16x4; + op_rev = Q ? Iop_Shr16x8 : Iop_Shr16x4; + op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; + break; + case 2: + op = Q ? Iop_QShl32x4 : Iop_QShl32x2; + op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; + op_add = Q ? Iop_Add32x4 : Iop_Add32x2; + op_rev = Q ? Iop_Shr32x4 : Iop_Shr32x2; + op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; + break; + case 3: + op = Q ? Iop_QShl64x2 : Iop_QShl64x1; + op_sub = Q ? Iop_Sub64x2 : Iop_Sub64; + op_add = Q ? Iop_Add64x2 : Iop_Add64; + op_rev = Q ? Iop_Shr64x2 : Iop_Shr64; + op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; + op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64; + break; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op = Q ? Iop_QSal8x16 : Iop_QSal8x8; + op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; + op_add = Q ? Iop_Add8x16 : Iop_Add8x8; + op_rev = Q ? Iop_Sar8x16 : Iop_Sar8x8; + op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; + break; + case 1: + op = Q ? Iop_QSal16x8 : Iop_QSal16x4; + op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; + op_add = Q ? Iop_Add16x8 : Iop_Add16x4; + op_rev = Q ? Iop_Sar16x8 : Iop_Sar16x4; + op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; + break; + case 2: + op = Q ? Iop_QSal32x4 : Iop_QSal32x2; + op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; + op_add = Q ? Iop_Add32x4 : Iop_Add32x2; + op_rev = Q ? Iop_Sar32x4 : Iop_Sar32x2; + op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; + break; + case 3: + op = Q ? Iop_QSal64x2 : Iop_QSal64x1; + op_sub = Q ? Iop_Sub64x2 : Iop_Sub64; + op_add = Q ? Iop_Add64x2 : Iop_Add64; + op_rev = Q ? Iop_Sar64x2 : Iop_Sar64; + op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64; + op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64; + break; + default: + vassert(0); + } + } + if (Q) { + tmp = newTemp(Ity_V128); + shval = newTemp(Ity_V128); + mask = newTemp(Ity_V128); + } else { + tmp = newTemp(Ity_I64); + shval = newTemp(Ity_I64); + mask = newTemp(Ity_I64); + } + /* Only least significant byte from second argument is used. + Copy this byte to the whole vector element. */ + assign(shval, binop(op_shrn, + binop(op_shln, + mkexpr(arg_n), + mkU8((8 << size) - 8)), + mkU8((8 << size) - 8))); + for (i = 0; i < size; i++) { + old_shval = shval; + shval = newTemp(Q ? Ity_V128 : Ity_I64); + assign(shval, binop(Q ? Iop_OrV128 : Iop_Or64, + mkexpr(old_shval), + binop(op_shln, + mkexpr(old_shval), + mkU8(8 << i)))); + } + /* Compute the result */ + assign(round, binop(Q ? Iop_AndV128 : Iop_And64, + binop(op, + mkexpr(arg_m), + binop(op_add, + mkexpr(arg_n), + mkexpr(imm_val))), + binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(imm_val), + binop(cmp_gt, + Q ? mkU128(0) : mkU64(0), + mkexpr(arg_n))))); + assign(res, binop(op_add, + binop(op, mkexpr(arg_m), mkexpr(arg_n)), + mkexpr(round))); +#ifndef DISABLE_QC_FLAG + /* If shift is greater or equal to the element size and element is + non-zero, then QC flag should be set. */ + esize = (8 << size) - 1; + esize = (esize << 8) | esize; + esize = (esize << 16) | esize; + esize = (esize << 32) | esize; + setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64, + binop(cmp_gt, mkexpr(shval), + Q ? mkU128(esize) : mkU64(esize)), + unop(cmp_neq, mkexpr(arg_m))), + Q ? mkU128(0) : mkU64(0), + Q, condT); + /* Othervise QC flag should be set if shift value is positive and + result beign rightshifted the same value is not equal to left + argument. */ + assign(mask, binop(cmp_gt, mkexpr(shval), + Q ? mkU128(0) : mkU64(0))); + if (!Q && size == 3) + assign(tmp, binop(op_rev, mkexpr(res), + unop(Iop_64to8, mkexpr(arg_n)))); + else + assign(tmp, binop(op_rev, mkexpr(res), mkexpr(arg_n))); + setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(tmp), mkexpr(mask)), + binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(arg_m), mkexpr(mask)), + Q, condT); +#endif + DIP("vqrshl.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd', + nreg); + } + break; + case 6: + /* VMAX, VMIN */ + if (B == 0) { + /* VMAX */ + IROp op; + if (U == 0) { + switch (size) { + case 0: op = Q ? Iop_Max8Sx16 : Iop_Max8Sx8; break; + case 1: op = Q ? Iop_Max16Sx8 : Iop_Max16Sx4; break; + case 2: op = Q ? Iop_Max32Sx4 : Iop_Max32Sx2; break; + case 3: return False; + default: vassert(0); + } + } else { + switch (size) { + case 0: op = Q ? Iop_Max8Ux16 : Iop_Max8Ux8; break; + case 1: op = Q ? Iop_Max16Ux8 : Iop_Max16Ux4; break; + case 2: op = Q ? Iop_Max32Ux4 : Iop_Max32Ux2; break; + case 3: return False; + default: vassert(0); + } + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vmax.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } else { + /* VMIN */ + IROp op; + if (U == 0) { + switch (size) { + case 0: op = Q ? Iop_Min8Sx16 : Iop_Min8Sx8; break; + case 1: op = Q ? Iop_Min16Sx8 : Iop_Min16Sx4; break; + case 2: op = Q ? Iop_Min32Sx4 : Iop_Min32Sx2; break; + case 3: return False; + default: vassert(0); + } + } else { + switch (size) { + case 0: op = Q ? Iop_Min8Ux16 : Iop_Min8Ux8; break; + case 1: op = Q ? Iop_Min16Ux8 : Iop_Min16Ux4; break; + case 2: op = Q ? Iop_Min32Ux4 : Iop_Min32Ux2; break; + case 3: return False; + default: vassert(0); + } + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vmin.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } + break; + case 7: + if (B == 0) { + /* VABD */ + IROp op_cmp, op_sub; + IRTemp cond; + if ((theInstr >> 23) & 1) { + vpanic("VABDL should not be in dis_neon_data_3same\n"); + } + if (Q) { + switch (size) { + case 0: + op_cmp = U ? Iop_CmpGT8Ux16 : Iop_CmpGT8Sx16; + op_sub = Iop_Sub8x16; + break; + case 1: + op_cmp = U ? Iop_CmpGT16Ux8 : Iop_CmpGT16Sx8; + op_sub = Iop_Sub16x8; + break; + case 2: + op_cmp = U ? Iop_CmpGT32Ux4 : Iop_CmpGT32Sx4; + op_sub = Iop_Sub32x4; + break; + case 3: + return False; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op_cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8; + op_sub = Iop_Sub8x8; + break; + case 1: + op_cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4; + op_sub = Iop_Sub16x4; + break; + case 2: + op_cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2; + op_sub = Iop_Sub32x2; + break; + case 3: + return False; + default: + vassert(0); + } + } + if (Q) { + cond = newTemp(Ity_V128); + } else { + cond = newTemp(Ity_I64); + } + assign(cond, binop(op_cmp, mkexpr(arg_n), mkexpr(arg_m))); + assign(res, binop(Q ? Iop_OrV128 : Iop_Or64, + binop(Q ? Iop_AndV128 : Iop_And64, + binop(op_sub, mkexpr(arg_n), + mkexpr(arg_m)), + mkexpr(cond)), + binop(Q ? Iop_AndV128 : Iop_And64, + binop(op_sub, mkexpr(arg_m), + mkexpr(arg_n)), + unop(Q ? Iop_NotV128 : Iop_Not64, + mkexpr(cond))))); + DIP("vabd.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } else { + /* VABA */ + IROp op_cmp, op_sub, op_add; + IRTemp cond, acc, tmp; + if ((theInstr >> 23) & 1) { + vpanic("VABAL should not be in dis_neon_data_3same"); + } + if (Q) { + switch (size) { + case 0: + op_cmp = U ? Iop_CmpGT8Ux16 : Iop_CmpGT8Sx16; + op_sub = Iop_Sub8x16; + op_add = Iop_Add8x16; + break; + case 1: + op_cmp = U ? Iop_CmpGT16Ux8 : Iop_CmpGT16Sx8; + op_sub = Iop_Sub16x8; + op_add = Iop_Add16x8; + break; + case 2: + op_cmp = U ? Iop_CmpGT32Ux4 : Iop_CmpGT32Sx4; + op_sub = Iop_Sub32x4; + op_add = Iop_Add32x4; + break; + case 3: + return False; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op_cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8; + op_sub = Iop_Sub8x8; + op_add = Iop_Add8x8; + break; + case 1: + op_cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4; + op_sub = Iop_Sub16x4; + op_add = Iop_Add16x4; + break; + case 2: + op_cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2; + op_sub = Iop_Sub32x2; + op_add = Iop_Add32x2; + break; + case 3: + return False; + default: + vassert(0); + } + } + if (Q) { + cond = newTemp(Ity_V128); + acc = newTemp(Ity_V128); + tmp = newTemp(Ity_V128); + assign(acc, getQReg(dreg)); + } else { + cond = newTemp(Ity_I64); + acc = newTemp(Ity_I64); + tmp = newTemp(Ity_I64); + assign(acc, getDRegI64(dreg)); + } + assign(cond, binop(op_cmp, mkexpr(arg_n), mkexpr(arg_m))); + assign(tmp, binop(Q ? Iop_OrV128 : Iop_Or64, + binop(Q ? Iop_AndV128 : Iop_And64, + binop(op_sub, mkexpr(arg_n), + mkexpr(arg_m)), + mkexpr(cond)), + binop(Q ? Iop_AndV128 : Iop_And64, + binop(op_sub, mkexpr(arg_m), + mkexpr(arg_n)), + unop(Q ? Iop_NotV128 : Iop_Not64, + mkexpr(cond))))); + assign(res, binop(op_add, mkexpr(acc), mkexpr(tmp))); + DIP("vaba.%c%u %c%u, %c%u, %c%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } + break; + case 8: + if (B == 0) { + IROp op; + if (U == 0) { + /* VADD */ + switch (size) { + case 0: op = Q ? Iop_Add8x16 : Iop_Add8x8; break; + case 1: op = Q ? Iop_Add16x8 : Iop_Add16x4; break; + case 2: op = Q ? Iop_Add32x4 : Iop_Add32x2; break; + case 3: op = Q ? Iop_Add64x2 : Iop_Add64; break; + default: vassert(0); + } + DIP("vadd.i%u %c%u, %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', + dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + /* VSUB */ + switch (size) { + case 0: op = Q ? Iop_Sub8x16 : Iop_Sub8x8; break; + case 1: op = Q ? Iop_Sub16x8 : Iop_Sub16x4; break; + case 2: op = Q ? Iop_Sub32x4 : Iop_Sub32x2; break; + case 3: op = Q ? Iop_Sub64x2 : Iop_Sub64; break; + default: vassert(0); + } + DIP("vsub.i%u %c%u, %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', + dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + } else { + IROp op; + switch (size) { + case 0: op = Q ? Iop_CmpNEZ8x16 : Iop_CmpNEZ8x8; break; + case 1: op = Q ? Iop_CmpNEZ16x8 : Iop_CmpNEZ16x4; break; + case 2: op = Q ? Iop_CmpNEZ32x4 : Iop_CmpNEZ32x2; break; + case 3: op = Q ? Iop_CmpNEZ64x2 : Iop_CmpwNEZ64; break; + default: vassert(0); + } + if (U == 0) { + /* VTST */ + assign(res, unop(op, binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(arg_n), + mkexpr(arg_m)))); + DIP("vtst.%u %c%u, %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', + dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + /* VCEQ */ + assign(res, unop(Q ? Iop_NotV128 : Iop_Not64, + unop(op, + binop(Q ? Iop_XorV128 : Iop_Xor64, + mkexpr(arg_n), + mkexpr(arg_m))))); + DIP("vceq.i%u %c%u, %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', + dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + } + break; + case 9: + if (B == 0) { + /* VMLA, VMLS (integer) */ + IROp op, op2; + UInt P = (theInstr >> 24) & 1; + if (P) { + switch (size) { + case 0: + op = Q ? Iop_Mul8x16 : Iop_Mul8x8; + op2 = Q ? Iop_Sub8x16 : Iop_Sub8x8; + break; + case 1: + op = Q ? Iop_Mul16x8 : Iop_Mul16x4; + op2 = Q ? Iop_Sub16x8 : Iop_Sub16x4; + break; + case 2: + op = Q ? Iop_Mul32x4 : Iop_Mul32x2; + op2 = Q ? Iop_Sub32x4 : Iop_Sub32x2; + break; + case 3: + return False; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op = Q ? Iop_Mul8x16 : Iop_Mul8x8; + op2 = Q ? Iop_Add8x16 : Iop_Add8x8; + break; + case 1: + op = Q ? Iop_Mul16x8 : Iop_Mul16x4; + op2 = Q ? Iop_Add16x8 : Iop_Add16x4; + break; + case 2: + op = Q ? Iop_Mul32x4 : Iop_Mul32x2; + op2 = Q ? Iop_Add32x4 : Iop_Add32x2; + break; + case 3: + return False; + default: + vassert(0); + } + } + assign(res, binop(op2, + Q ? getQReg(dreg) : getDRegI64(dreg), + binop(op, mkexpr(arg_n), mkexpr(arg_m)))); + DIP("vml%c.i%u %c%u, %c%u, %c%u\n", + P ? 's' : 'a', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } else { + /* VMUL */ + IROp op; + UInt P = (theInstr >> 24) & 1; + if (P) { + switch (size) { + case 0: + op = Q ? Iop_PolynomialMul8x16 : Iop_PolynomialMul8x8; + break; + case 1: case 2: case 3: return False; + default: vassert(0); + } + } else { + switch (size) { + case 0: op = Q ? Iop_Mul8x16 : Iop_Mul8x8; break; + case 1: op = Q ? Iop_Mul16x8 : Iop_Mul16x4; break; + case 2: op = Q ? Iop_Mul32x4 : Iop_Mul32x2; break; + case 3: return False; + default: vassert(0); + } + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vmul.%c%u %c%u, %c%u, %c%u\n", + P ? 'p' : 'i', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', + mreg); + } + break; + case 10: { + /* VPMAX, VPMIN */ + UInt P = (theInstr >> 4) & 1; + IROp op; + if (Q) + return False; + if (P) { + switch (size) { + case 0: op = U ? Iop_PwMin8Ux8 : Iop_PwMin8Sx8; break; + case 1: op = U ? Iop_PwMin16Ux4 : Iop_PwMin16Sx4; break; + case 2: op = U ? Iop_PwMin32Ux2 : Iop_PwMin32Sx2; break; + case 3: return False; + default: vassert(0); + } + } else { + switch (size) { + case 0: op = U ? Iop_PwMax8Ux8 : Iop_PwMax8Sx8; break; + case 1: op = U ? Iop_PwMax16Ux4 : Iop_PwMax16Sx4; break; + case 2: op = U ? Iop_PwMax32Ux2 : Iop_PwMax32Sx2; break; + case 3: return False; + default: vassert(0); + } + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vp%s.%c%u %c%u, %c%u, %c%u\n", + P ? "min" : "max", U ? 'u' : 's', + 8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, + Q ? 'q' : 'd', mreg); + break; + } + case 11: + if (B == 0) { + if (U == 0) { + /* VQDMULH */ + IROp op ,op2; + ULong imm; + switch (size) { + case 0: case 3: + return False; + case 1: + op = Q ? Iop_QDMulHi16Sx8 : Iop_QDMulHi16Sx4; + op2 = Q ? Iop_CmpEQ16x8 : Iop_CmpEQ16x4; + imm = 1LL << 15; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 2: + op = Q ? Iop_QDMulHi32Sx4 : Iop_QDMulHi32Sx2; + op2 = Q ? Iop_CmpEQ32x4 : Iop_CmpEQ32x2; + imm = 1LL << 31; + imm = (imm << 32) | imm; + break; + default: + vassert(0); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); +#ifndef DISABLE_QC_FLAG + setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64, + binop(op2, mkexpr(arg_n), + Q ? mkU128(imm) : mkU64(imm)), + binop(op2, mkexpr(arg_m), + Q ? mkU128(imm) : mkU64(imm))), + Q ? mkU128(0) : mkU64(0), + Q, condT); +#endif + DIP("vqdmulh.s%u %c%u, %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', + dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + /* VQRDMULH */ + IROp op ,op2; + ULong imm; + switch(size) { + case 0: case 3: + return False; + case 1: + imm = 1LL << 15; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + op = Q ? Iop_QRDMulHi16Sx8 : Iop_QRDMulHi16Sx4; + op2 = Q ? Iop_CmpEQ16x8 : Iop_CmpEQ16x4; + break; + case 2: + imm = 1LL << 31; + imm = (imm << 32) | imm; + op = Q ? Iop_QRDMulHi32Sx4 : Iop_QRDMulHi32Sx2; + op2 = Q ? Iop_CmpEQ32x4 : Iop_CmpEQ32x2; + break; + default: + vassert(0); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); +#ifndef DISABLE_QC_FLAG + setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64, + binop(op2, mkexpr(arg_n), + Q ? mkU128(imm) : mkU64(imm)), + binop(op2, mkexpr(arg_m), + Q ? mkU128(imm) : mkU64(imm))), + Q ? mkU128(0) : mkU64(0), + Q, condT); +#endif + DIP("vqrdmulh.s%u %c%u, %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', + dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + } else { + if (U == 0) { + /* VPADD */ + IROp op; + if (Q) + return False; + switch (size) { + case 0: op = Q ? Iop_PwAdd8x16 : Iop_PwAdd8x8; break; + case 1: op = Q ? Iop_PwAdd16x8 : Iop_PwAdd16x4; break; + case 2: op = Q ? Iop_PwAdd32x4 : Iop_PwAdd32x2; break; + case 3: return False; + default: vassert(0); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vpadd.i%d %c%u, %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', + dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + } + break; + /* Starting from here these are FP SIMD cases */ + case 13: + if (B == 0) { + IROp op; + if (U == 0) { + if ((C >> 1) == 0) { + /* VADD */ + op = Q ? Iop_Add32Fx4 : Iop_Add32Fx2 ; + DIP("vadd.f32 %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + /* VSUB */ + op = Q ? Iop_Sub32Fx4 : Iop_Sub32Fx2 ; + DIP("vsub.f32 %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + } else { + if ((C >> 1) == 0) { + /* VPADD */ + if (Q) + return False; + op = Iop_PwAdd32Fx2; + DIP("vpadd.f32 d%u, d%u, d%u\n", dreg, nreg, mreg); + } else { + /* VABD */ + if (Q) { + assign(res, unop(Iop_Abs32Fx4, + binop(Iop_Sub32Fx4, + mkexpr(arg_n), + mkexpr(arg_m)))); + } else { + assign(res, unop(Iop_Abs32Fx2, + binop(Iop_Sub32Fx2, + mkexpr(arg_n), + mkexpr(arg_m)))); + } + DIP("vabd.f32 %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + break; + } + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + } else { + if (U == 0) { + /* VMLA, VMLS */ + IROp op, op2; + UInt P = (theInstr >> 21) & 1; + if (P) { + switch (size & 1) { + case 0: + op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2; + op2 = Q ? Iop_Sub32Fx4 : Iop_Sub32Fx2; + break; + case 1: return False; + default: vassert(0); + } + } else { + switch (size & 1) { + case 0: + op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2; + op2 = Q ? Iop_Add32Fx4 : Iop_Add32Fx2; + break; + case 1: return False; + default: vassert(0); + } + } + assign(res, binop(op2, + Q ? getQReg(dreg) : getDRegI64(dreg), + binop(op, mkexpr(arg_n), mkexpr(arg_m)))); + + DIP("vml%c.f32 %c%u, %c%u, %c%u\n", + P ? 's' : 'a', Q ? 'q' : 'd', + dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + /* VMUL */ + IROp op; + if ((C >> 1) != 0) + return False; + op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2 ; + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vmul.f32 %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + } + break; + case 14: + if (B == 0) { + if (U == 0) { + if ((C >> 1) == 0) { + /* VCEQ */ + IROp op; + if ((theInstr >> 20) & 1) + return False; + op = Q ? Iop_CmpEQ32Fx4 : Iop_CmpEQ32Fx2; + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vceq.f32 %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + return False; + } + } else { + if ((C >> 1) == 0) { + /* VCGE */ + IROp op; + if ((theInstr >> 20) & 1) + return False; + op = Q ? Iop_CmpGE32Fx4 : Iop_CmpGE32Fx2; + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vcge.f32 %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + /* VCGT */ + IROp op; + if ((theInstr >> 20) & 1) + return False; + op = Q ? Iop_CmpGT32Fx4 : Iop_CmpGT32Fx2; + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + DIP("vcgt.f32 %c%u, %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + } + } else { + if (U == 1) { + /* VACGE, VACGT */ + UInt op_bit = (theInstr >> 21) & 1; + IROp op, op2; + op2 = Q ? Iop_Abs32Fx4 : Iop_Abs32Fx2; + if (op_bit) { + op = Q ? Iop_CmpGT32Fx4 : Iop_CmpGT32Fx2; + assign(res, binop(op, + unop(op2, mkexpr(arg_n)), + unop(op2, mkexpr(arg_m)))); + } else { + op = Q ? Iop_CmpGE32Fx4 : Iop_CmpGE32Fx2; + assign(res, binop(op, + unop(op2, mkexpr(arg_n)), + unop(op2, mkexpr(arg_m)))); + } + DIP("vacg%c.f32 %c%u, %c%u, %c%u\n", op_bit ? 't' : 'e', + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, + Q ? 'q' : 'd', mreg); + } + } + break; + case 15: + if (B == 0) { + if (U == 0) { + /* VMAX, VMIN */ + IROp op; + if ((theInstr >> 20) & 1) + return False; + if ((theInstr >> 21) & 1) { + op = Q ? Iop_Min32Fx4 : Iop_Min32Fx2; + DIP("vmin.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + op = Q ? Iop_Max32Fx4 : Iop_Max32Fx2; + DIP("vmax.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + } else { + /* VPMAX, VPMIN */ + IROp op; + if (Q) + return False; + if ((theInstr >> 20) & 1) + return False; + if ((theInstr >> 21) & 1) { + op = Iop_PwMin32Fx2; + DIP("vpmin.f32 d%u, d%u, d%u\n", dreg, nreg, mreg); + } else { + op = Iop_PwMax32Fx2; + DIP("vpmax.f32 d%u, d%u, d%u\n", dreg, nreg, mreg); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + } + } else { + if (U == 0) { + if ((C >> 1) == 0) { + /* VRECPS */ + if ((theInstr >> 20) & 1) + return False; + assign(res, binop(Q ? Iop_Recps32Fx4 : Iop_Recps32Fx2, + mkexpr(arg_n), + mkexpr(arg_m))); + DIP("vrecps.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } else { + /* VRSQRTS */ + if ((theInstr >> 20) & 1) + return False; + assign(res, binop(Q ? Iop_Rsqrts32Fx4 : Iop_Rsqrts32Fx2, + mkexpr(arg_n), + mkexpr(arg_m))); + DIP("vrsqrts.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); + } + } + } + break; + } + + if (Q) { + putQReg(dreg, mkexpr(res), condT); + } else { + putDRegI64(dreg, mkexpr(res), condT); + } + + return True; +} + +/* A7.4.2 Three registers of different length */ +static +Bool dis_neon_data_3diff ( UInt theInstr, IRTemp condT ) +{ + UInt A = (theInstr >> 8) & 0xf; + UInt B = (theInstr >> 20) & 3; + UInt U = (theInstr >> 24) & 1; + UInt P = (theInstr >> 9) & 1; + UInt mreg = get_neon_m_regno(theInstr); + UInt nreg = get_neon_n_regno(theInstr); + UInt dreg = get_neon_d_regno(theInstr); + UInt size = B; + ULong imm; + IRTemp res, arg_m, arg_n, cond, tmp; + IROp cvt, cvt2, cmp, op, op2, sh, add; + switch (A) { + case 0: case 1: case 2: case 3: + /* VADDL, VADDW, VSUBL, VSUBW */ + if (dreg & 1) + return False; + dreg >>= 1; + size = B; + switch (size) { + case 0: + cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8; + op = (A & 2) ? Iop_Sub16x8 : Iop_Add16x8; + break; + case 1: + cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4; + op = (A & 2) ? Iop_Sub32x4 : Iop_Add32x4; + break; + case 2: + cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2; + op = (A & 2) ? Iop_Sub64x2 : Iop_Add64x2; + break; + case 3: + return False; + default: + vassert(0); + } + arg_n = newTemp(Ity_V128); + arg_m = newTemp(Ity_V128); + if (A & 1) { + if (nreg & 1) + return False; + nreg >>= 1; + assign(arg_n, getQReg(nreg)); + } else { + assign(arg_n, unop(cvt, getDRegI64(nreg))); + } + assign(arg_m, unop(cvt, getDRegI64(mreg))); + putQReg(dreg, binop(op, mkexpr(arg_n), mkexpr(arg_m)), + condT); + DIP("v%s%c.%c%u q%u, %c%u, d%u\n", (A & 2) ? "sub" : "add", + (A & 1) ? 'w' : 'l', U ? 'u' : 's', 8 << size, dreg, + (A & 1) ? 'q' : 'd', nreg, mreg); + return True; + case 4: + /* VADDHN, VRADDHN */ + if (mreg & 1) + return False; + mreg >>= 1; + if (nreg & 1) + return False; + nreg >>= 1; + size = B; + switch (size) { + case 0: + op = Iop_Add16x8; + cvt = Iop_Shorten16x8; + sh = Iop_ShrN16x8; + imm = 1U << 7; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 1: + op = Iop_Add32x4; + cvt = Iop_Shorten32x4; + sh = Iop_ShrN32x4; + imm = 1U << 15; + imm = (imm << 32) | imm; + break; + case 2: + op = Iop_Add64x2; + cvt = Iop_Shorten64x2; + sh = Iop_ShrN64x2; + imm = 1U << 31; + break; + case 3: + return False; + default: + vassert(0); + } + tmp = newTemp(Ity_V128); + res = newTemp(Ity_V128); + assign(tmp, binop(op, getQReg(nreg), getQReg(mreg))); + if (U) { + /* VRADDHN */ + assign(res, binop(op, mkexpr(tmp), + binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm)))); + } else { + assign(res, mkexpr(tmp)); + } + putDRegI64(dreg, unop(cvt, binop(sh, mkexpr(res), mkU8(8 << size))), + condT); + DIP("v%saddhn.i%u d%u, q%u, q%u\n", U ? "r" : "", 16 << size, dreg, + nreg, mreg); + return True; + case 5: + /* VABAL */ + if (!((theInstr >> 23) & 1)) { + vpanic("VABA should not be in dis_neon_data_3diff\n"); + } + if (dreg & 1) + return False; + dreg >>= 1; + switch (size) { + case 0: + cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8; + cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8; + cvt2 = Iop_Longen8Sx8; + op = Iop_Sub16x8; + op2 = Iop_Add16x8; + break; + case 1: + cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4; + cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4; + cvt2 = Iop_Longen16Sx4; + op = Iop_Sub32x4; + op2 = Iop_Add32x4; + break; + case 2: + cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2; + cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2; + cvt2 = Iop_Longen32Sx2; + op = Iop_Sub64x2; + op2 = Iop_Add64x2; + break; + case 3: + return False; + default: + vassert(0); + } + arg_n = newTemp(Ity_V128); + arg_m = newTemp(Ity_V128); + cond = newTemp(Ity_V128); + res = newTemp(Ity_V128); + assign(arg_n, unop(cvt, getDRegI64(nreg))); + assign(arg_m, unop(cvt, getDRegI64(mreg))); + assign(cond, unop(cvt2, binop(cmp, getDRegI64(nreg), + getDRegI64(mreg)))); + assign(res, binop(op2, + binop(Iop_OrV128, + binop(Iop_AndV128, + binop(op, mkexpr(arg_n), mkexpr(arg_m)), + mkexpr(cond)), + binop(Iop_AndV128, + binop(op, mkexpr(arg_m), mkexpr(arg_n)), + unop(Iop_NotV128, mkexpr(cond)))), + getQReg(dreg))); + putQReg(dreg, mkexpr(res), condT); + DIP("vabal.%c%u q%u, d%u, d%u\n", U ? 'u' : 's', 8 << size, dreg, + nreg, mreg); + return True; + case 6: + /* VSUBHN, VRSUBHN */ + if (mreg & 1) + return False; + mreg >>= 1; + if (nreg & 1) + return False; + nreg >>= 1; + size = B; + switch (size) { + case 0: + op = Iop_Sub16x8; + op2 = Iop_Add16x8; + cvt = Iop_Shorten16x8; + sh = Iop_ShrN16x8; + imm = 1U << 7; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 1: + op = Iop_Sub32x4; + op2 = Iop_Add32x4; + cvt = Iop_Shorten32x4; + sh = Iop_ShrN32x4; + imm = 1U << 15; + imm = (imm << 32) | imm; + break; + case 2: + op = Iop_Sub64x2; + op2 = Iop_Add64x2; + cvt = Iop_Shorten64x2; + sh = Iop_ShrN64x2; + imm = 1U << 31; + break; + case 3: + return False; + default: + vassert(0); + } + tmp = newTemp(Ity_V128); + res = newTemp(Ity_V128); + assign(tmp, binop(op, getQReg(nreg), getQReg(mreg))); + if (U) { + /* VRSUBHN */ + assign(res, binop(op2, mkexpr(tmp), + binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm)))); + } else { + assign(res, mkexpr(tmp)); + } + putDRegI64(dreg, unop(cvt, binop(sh, mkexpr(res), mkU8(8 << size))), + condT); + DIP("v%ssubhn.i%u d%u, q%u, q%u\n", U ? "r" : "", 16 << size, dreg, + nreg, mreg); + return True; + case 7: + /* VABDL */ + if (!((theInstr >> 23) & 1)) { + vpanic("VABL should not be in dis_neon_data_3diff\n"); + } + if (dreg & 1) + return False; + dreg >>= 1; + switch (size) { + case 0: + cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8; + cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8; + cvt2 = Iop_Longen8Sx8; + op = Iop_Sub16x8; + break; + case 1: + cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4; + cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4; + cvt2 = Iop_Longen16Sx4; + op = Iop_Sub32x4; + break; + case 2: + cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2; + cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2; + cvt2 = Iop_Longen32Sx2; + op = Iop_Sub64x2; + break; + case 3: + return False; + default: + vassert(0); + } + arg_n = newTemp(Ity_V128); + arg_m = newTemp(Ity_V128); + cond = newTemp(Ity_V128); + res = newTemp(Ity_V128); + assign(arg_n, unop(cvt, getDRegI64(nreg))); + assign(arg_m, unop(cvt, getDRegI64(mreg))); + assign(cond, unop(cvt2, binop(cmp, getDRegI64(nreg), + getDRegI64(mreg)))); + assign(res, binop(Iop_OrV128, + binop(Iop_AndV128, + binop(op, mkexpr(arg_n), mkexpr(arg_m)), + mkexpr(cond)), + binop(Iop_AndV128, + binop(op, mkexpr(arg_m), mkexpr(arg_n)), + unop(Iop_NotV128, mkexpr(cond))))); + putQReg(dreg, mkexpr(res), condT); + DIP("vabdl.%c%u q%u, d%u, d%u\n", U ? 'u' : 's', 8 << size, dreg, + nreg, mreg); + return True; + case 8: + case 10: + /* VMLAL, VMLSL (integer) */ + if (dreg & 1) + return False; + dreg >>= 1; + size = B; + switch (size) { + case 0: + op = U ? Iop_Mull8Ux8 : Iop_Mull8Sx8; + op2 = P ? Iop_Sub16x8 : Iop_Add16x8; + break; + case 1: + op = U ? Iop_Mull16Ux4 : Iop_Mull16Sx4; + op2 = P ? Iop_Sub32x4 : Iop_Add32x4; + break; + case 2: + op = U ? Iop_Mull32Ux2 : Iop_Mull32Sx2; + op2 = P ? Iop_Sub64x2 : Iop_Add64x2; + break; + case 3: + return False; + default: + vassert(0); + } + res = newTemp(Ity_V128); + assign(res, binop(op, getDRegI64(nreg),getDRegI64(mreg))); + putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)), condT); + DIP("vml%cl.%c%u q%u, d%u, d%u\n", P ? 's' : 'a', U ? 'u' : 's', + 8 << size, dreg, nreg, mreg); + return True; + case 9: + case 11: + /* VQDMLAL, VQDMLSL */ + if (U) + return False; + if (dreg & 1) + return False; + dreg >>= 1; + size = B; + switch (size) { + case 0: case 3: + return False; + case 1: + op = Iop_QDMulLong16Sx4; + cmp = Iop_CmpEQ16x4; + add = P ? Iop_QSub32Sx4 : Iop_QAdd32Sx4; + op2 = P ? Iop_Sub32x4 : Iop_Add32x4; + imm = 1LL << 15; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 2: + op = Iop_QDMulLong32Sx2; + cmp = Iop_CmpEQ32x2; + add = P ? Iop_QSub64Sx2 : Iop_QAdd64Sx2; + op2 = P ? Iop_Sub64x2 : Iop_Add64x2; + imm = 1LL << 31; + imm = (imm << 32) | imm; + break; + default: + vassert(0); + } + res = newTemp(Ity_V128); + tmp = newTemp(Ity_V128); + assign(res, binop(op, getDRegI64(nreg), getDRegI64(mreg))); +#ifndef DISABLE_QC_FLAG + assign(tmp, binop(op2, getQReg(dreg), mkexpr(res))); + setFlag_QC(mkexpr(tmp), binop(add, getQReg(dreg), mkexpr(res)), + True, condT); + setFlag_QC(binop(Iop_And64, + binop(cmp, getDRegI64(nreg), mkU64(imm)), + binop(cmp, getDRegI64(mreg), mkU64(imm))), + mkU64(0), + False, condT); +#endif + putQReg(dreg, binop(add, getQReg(dreg), mkexpr(res)), condT); + DIP("vqdml%cl.s%u q%u, d%u, d%u\n", P ? 's' : 'a', 8 << size, dreg, + nreg, mreg); + return True; + case 12: + case 14: + /* VMULL (integer or polynomial) */ + if (dreg & 1) + return False; + dreg >>= 1; + size = B; + switch (size) { + case 0: + op = (U) ? Iop_Mull8Ux8 : Iop_Mull8Sx8; + if (P) + op = Iop_PolynomialMull8x8; + break; + case 1: + op = (U) ? Iop_Mull16Ux4 : Iop_Mull16Sx4; + break; + case 2: + op = (U) ? Iop_Mull32Ux2 : Iop_Mull32Sx2; + break; + default: + vassert(0); + } + putQReg(dreg, binop(op, getDRegI64(nreg), + getDRegI64(mreg)), condT); + DIP("vmull.%c%u q%u, d%u, d%u\n", P ? 'p' : (U ? 'u' : 's'), + 8 << size, dreg, nreg, mreg); + return True; + case 13: + /* VQDMULL */ + if (U) + return False; + if (dreg & 1) + return False; + dreg >>= 1; + size = B; + switch (size) { + case 0: + case 3: + return False; + case 1: + op = Iop_QDMulLong16Sx4; + op2 = Iop_CmpEQ16x4; + imm = 1LL << 15; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 2: + op = Iop_QDMulLong32Sx2; + op2 = Iop_CmpEQ32x2; + imm = 1LL << 31; + imm = (imm << 32) | imm; + break; + default: + vassert(0); + } + putQReg(dreg, binop(op, getDRegI64(nreg), getDRegI64(mreg)), + condT); +#ifndef DISABLE_QC_FLAG + setFlag_QC(binop(Iop_And64, + binop(op2, getDRegI64(nreg), mkU64(imm)), + binop(op2, getDRegI64(mreg), mkU64(imm))), + mkU64(0), + False, condT); +#endif + DIP("vqdmull.s%u q%u, d%u, d%u\n", 8 << size, dreg, nreg, mreg); + return True; + default: + return False; + } + return False; +} + +/* A7.4.3 Two registers and a scalar */ +static +Bool dis_neon_data_2reg_and_scalar ( UInt theInstr, IRTemp condT ) +{ +# define INSN(_bMax,_bMin) SLICE_UInt(theInstr, (_bMax), (_bMin)) + UInt U = INSN(24,24); + UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); + UInt nreg = get_neon_n_regno(theInstr & ~(1 << 6)); + UInt mreg = get_neon_m_regno(theInstr & ~(1 << 6)); + UInt size = INSN(21,20); + UInt index; + UInt Q = INSN(24,24); + + if (INSN(27,25) != 1 || INSN(23,23) != 1 + || INSN(6,6) != 1 || INSN(4,4) != 0) + return False; + + /* VMLA, VMLS (scalar) */ + if ((INSN(11,8) & BITS4(1,0,1,0)) == BITS4(0,0,0,0)) { + IRTemp res, arg_m, arg_n; + IROp dup, get, op, op2, add, sub; + if (Q) { + if ((dreg & 1) || (nreg & 1)) + return False; + dreg >>= 1; + nreg >>= 1; + res = newTemp(Ity_V128); + arg_m = newTemp(Ity_V128); + arg_n = newTemp(Ity_V128); + assign(arg_n, getQReg(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x8; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x4; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + } else { + res = newTemp(Ity_I64); + arg_m = newTemp(Ity_I64); + arg_n = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x4; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x2; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + } + if (INSN(8,8)) { + switch (size) { + case 2: + op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2; + add = Q ? Iop_Add32Fx4 : Iop_Add32Fx2; + sub = Q ? Iop_Sub32Fx4 : Iop_Sub32Fx2; + break; + case 0: + case 1: + case 3: + return False; + default: + vassert(0); + } + } else { + switch (size) { + case 1: + op = Q ? Iop_Mul16x8 : Iop_Mul16x4; + add = Q ? Iop_Add16x8 : Iop_Add16x4; + sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; + break; + case 2: + op = Q ? Iop_Mul32x4 : Iop_Mul32x2; + add = Q ? Iop_Add32x4 : Iop_Add32x2; + sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + } + op2 = INSN(10,10) ? sub : add; + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + if (Q) + putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)), + condT); + else + putDRegI64(dreg, binop(op2, getDRegI64(dreg), mkexpr(res)), + condT); + DIP("vml%c.%c%u %c%u, %c%u, d%u[%u]\n", INSN(10,10) ? 's' : 'a', + INSN(8,8) ? 'f' : 'i', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, mreg, index); + return True; + } + + /* VMLAL, VMLSL (scalar) */ + if ((INSN(11,8) & BITS4(1,0,1,1)) == BITS4(0,0,1,0)) { + IRTemp res, arg_m, arg_n; + IROp dup, get, op, op2, add, sub; + if (dreg & 1) + return False; + dreg >>= 1; + res = newTemp(Ity_V128); + arg_m = newTemp(Ity_I64); + arg_n = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x4; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x2; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + switch (size) { + case 1: + op = U ? Iop_Mull16Ux4 : Iop_Mull16Sx4; + add = Iop_Add32x4; + sub = Iop_Sub32x4; + break; + case 2: + op = U ? Iop_Mull32Ux2 : Iop_Mull32Sx2; + add = Iop_Add64x2; + sub = Iop_Sub64x2; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + op2 = INSN(10,10) ? sub : add; + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)), condT); + DIP("vml%cl.%c%u q%u, d%u, d%u[%u]\n", + INSN(10,10) ? 's' : 'a', U ? 'u' : 's', + 8 << size, dreg, nreg, mreg, index); + return True; + } + + /* VQDMLAL, VQDMLSL (scalar) */ + if ((INSN(11,8) & BITS4(1,0,1,1)) == BITS4(0,0,1,1) && !U) { + IRTemp res, arg_m, arg_n, tmp; + IROp dup, get, op, op2, add, cmp; + UInt P = INSN(10,10); + ULong imm; + if (dreg & 1) + return False; + dreg >>= 1; + res = newTemp(Ity_V128); + arg_m = newTemp(Ity_I64); + arg_n = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x4; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x2; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + switch (size) { + case 0: + case 3: + return False; + case 1: + op = Iop_QDMulLong16Sx4; + cmp = Iop_CmpEQ16x4; + add = P ? Iop_QSub32Sx4 : Iop_QAdd32Sx4; + op2 = P ? Iop_Sub32x4 : Iop_Add32x4; + imm = 1LL << 15; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 2: + op = Iop_QDMulLong32Sx2; + cmp = Iop_CmpEQ32x2; + add = P ? Iop_QSub64Sx2 : Iop_QAdd64Sx2; + op2 = P ? Iop_Sub64x2 : Iop_Add64x2; + imm = 1LL << 31; + imm = (imm << 32) | imm; + break; + default: + vassert(0); + } + res = newTemp(Ity_V128); + tmp = newTemp(Ity_V128); + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); +#ifndef DISABLE_QC_FLAG + assign(tmp, binop(op2, getQReg(dreg), mkexpr(res))); + setFlag_QC(binop(Iop_And64, + binop(cmp, mkexpr(arg_n), mkU64(imm)), + binop(cmp, mkexpr(arg_m), mkU64(imm))), + mkU64(0), + False, condT); + setFlag_QC(mkexpr(tmp), binop(add, getQReg(dreg), mkexpr(res)), + True, condT); +#endif + putQReg(dreg, binop(add, getQReg(dreg), mkexpr(res)), condT); + DIP("vqdml%cl.s%u q%u, d%u, d%u[%u]\n", P ? 's' : 'a', 8 << size, + dreg, nreg, mreg, index); + return True; + } + + /* VMUL (by scalar) */ + if ((INSN(11,8) & BITS4(1,1,1,0)) == BITS4(1,0,0,0)) { + IRTemp res, arg_m, arg_n; + IROp dup, get, op; + if (Q) { + if ((dreg & 1) || (nreg & 1)) + return False; + dreg >>= 1; + nreg >>= 1; + res = newTemp(Ity_V128); + arg_m = newTemp(Ity_V128); + arg_n = newTemp(Ity_V128); + assign(arg_n, getQReg(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x8; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x4; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + } else { + res = newTemp(Ity_I64); + arg_m = newTemp(Ity_I64); + arg_n = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x4; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x2; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + } + switch (size) { + case 1: + op = Q ? Iop_Mul16x8 : Iop_Mul16x4; + break; + case 2: + op = Q ? Iop_Mul32x4 : Iop_Mul32x2; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + if (Q) + putQReg(dreg, mkexpr(res), condT); + else + putDRegI64(dreg, mkexpr(res), condT); + DIP("vmul.i%u %c%u, %c%u, d%u[%u]\n", 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, mreg, index); + return True; + } + + /* VMULL (scalar) */ + if (INSN(11,8) == BITS4(1,0,1,0)) { + IRTemp res, arg_m, arg_n; + IROp dup, get, op; + if (dreg & 1) + return False; + dreg >>= 1; + res = newTemp(Ity_V128); + arg_m = newTemp(Ity_I64); + arg_n = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x4; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x2; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + switch (size) { + case 1: op = U ? Iop_Mull16Ux4 : Iop_Mull16Sx4; break; + case 2: op = U ? Iop_Mull32Ux2 : Iop_Mull32Sx2; break; + case 0: case 3: return False; + default: vassert(0); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); + putQReg(dreg, mkexpr(res), condT); + DIP("vmull.%c%u q%u, d%u, d%u[%u]\n", U ? 'u' : 's', 8 << size, dreg, + nreg, mreg, index); + return True; + } + + /* VQDMULL */ + if (INSN(11,8) == BITS4(1,0,1,1) && !U) { + IROp op ,op2, dup, get; + ULong imm; + IRTemp res, arg_m, arg_n; + if (dreg & 1) + return False; + dreg >>= 1; + res = newTemp(Ity_V128); + arg_m = newTemp(Ity_I64); + arg_n = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x4; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x2; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + switch (size) { + case 0: + case 3: + return False; + case 1: + op = Iop_QDMulLong16Sx4; + op2 = Iop_CmpEQ16x4; + imm = 1LL << 15; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 2: + op = Iop_QDMulLong32Sx2; + op2 = Iop_CmpEQ32x2; + imm = 1LL << 31; + imm = (imm << 32) | imm; + break; + default: + vassert(0); + } + putQReg(dreg, binop(op, mkexpr(arg_n), mkexpr(arg_m)), + condT); +#ifndef DISABLE_QC_FLAG + setFlag_QC(binop(Iop_And64, + binop(op2, mkexpr(arg_n), mkU64(imm)), + binop(op2, mkexpr(arg_m), mkU64(imm))), + mkU64(0), + False, condT); +#endif + DIP("vqdmull.s%u q%u, d%u, d%u[%u]\n", 8 << size, dreg, nreg, mreg, + index); + return True; + } + + /* VQDMULH */ + if (INSN(11,8) == BITS4(1,1,0,0)) { + IROp op ,op2, dup, get; + ULong imm; + IRTemp res, arg_m, arg_n; + if (Q) { + if ((dreg & 1) || (nreg & 1)) + return False; + dreg >>= 1; + nreg >>= 1; + res = newTemp(Ity_V128); + arg_m = newTemp(Ity_V128); + arg_n = newTemp(Ity_V128); + assign(arg_n, getQReg(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x8; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x4; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + } else { + res = newTemp(Ity_I64); + arg_m = newTemp(Ity_I64); + arg_n = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x4; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x2; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + } + switch (size) { + case 0: + case 3: + return False; + case 1: + op = Q ? Iop_QDMulHi16Sx8 : Iop_QDMulHi16Sx4; + op2 = Q ? Iop_CmpEQ16x8 : Iop_CmpEQ16x4; + imm = 1LL << 15; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 2: + op = Q ? Iop_QDMulHi32Sx4 : Iop_QDMulHi32Sx2; + op2 = Q ? Iop_CmpEQ32x4 : Iop_CmpEQ32x2; + imm = 1LL << 31; + imm = (imm << 32) | imm; + break; + default: + vassert(0); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); +#ifndef DISABLE_QC_FLAG + setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64, + binop(op2, mkexpr(arg_n), + Q ? mkU128(imm) : mkU64(imm)), + binop(op2, mkexpr(arg_m), + Q ? mkU128(imm) : mkU64(imm))), + Q ? mkU128(0) : mkU64(0), + Q, condT); +#endif + if (Q) + putQReg(dreg, mkexpr(res), condT); + else + putDRegI64(dreg, mkexpr(res), condT); + DIP("vqdmulh.s%u %c%u, %c%u, d%u[%u]\n", + 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, mreg, index); + return True; + } + + /* VQRDMULH (scalar) */ + if (INSN(11,8) == BITS4(1,1,0,1)) { + IROp op ,op2, dup, get; + ULong imm; + IRTemp res, arg_m, arg_n; + if (Q) { + if ((dreg & 1) || (nreg & 1)) + return False; + dreg >>= 1; + nreg >>= 1; + res = newTemp(Ity_V128); + arg_m = newTemp(Ity_V128); + arg_n = newTemp(Ity_V128); + assign(arg_n, getQReg(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x8; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x4; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + } else { + res = newTemp(Ity_I64); + arg_m = newTemp(Ity_I64); + arg_n = newTemp(Ity_I64); + assign(arg_n, getDRegI64(nreg)); + switch(size) { + case 1: + dup = Iop_Dup16x4; + get = Iop_GetElem16x4; + index = mreg >> 3; + mreg &= 7; + break; + case 2: + dup = Iop_Dup32x2; + get = Iop_GetElem32x2; + index = mreg >> 4; + mreg &= 0xf; + break; + case 0: + case 3: + return False; + default: + vassert(0); + } + assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index)))); + } + switch (size) { + case 0: + case 3: + return False; + case 1: + op = Q ? Iop_QRDMulHi16Sx8 : Iop_QRDMulHi16Sx4; + op2 = Q ? Iop_CmpEQ16x8 : Iop_CmpEQ16x4; + imm = 1LL << 15; + imm = (imm << 16) | imm; + imm = (imm << 32) | imm; + break; + case 2: + op = Q ? Iop_QRDMulHi32Sx4 : Iop_QRDMulHi32Sx2; + op2 = Q ? Iop_CmpEQ32x4 : Iop_CmpEQ32x2; + imm = 1LL << 31; + imm = (imm << 32) | imm; + break; + default: + vassert(0); + } + assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); +#ifndef DISABLE_QC_FLAG + setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64, + binop(op2, mkexpr(arg_n), + Q ? mkU128(imm) : mkU64(imm)), + binop(op2, mkexpr(arg_m), + Q ? mkU128(imm) : mkU64(imm))), + Q ? mkU128(0) : mkU64(0), + Q, condT); +#endif + if (Q) + putQReg(dreg, mkexpr(res), condT); + else + putDRegI64(dreg, mkexpr(res), condT); + DIP("vqrdmulh.s%u %c%u, %c%u, d%u[%u]\n", + 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', nreg, mreg, index); + return True; + } + + return False; +# undef INSN +} + +/* A7.4.4 Two registers and a shift amount */ +static +Bool dis_neon_data_2reg_and_shift ( UInt theInstr, IRTemp condT ) +{ + UInt A = (theInstr >> 8) & 0xf; + UInt B = (theInstr >> 6) & 1; + UInt L = (theInstr >> 7) & 1; + UInt U = (theInstr >> 24) & 1; + UInt Q = B; + UInt imm6 = (theInstr >> 16) & 0x3f; + UInt shift_imm; + UInt size = 4; + UInt tmp; + UInt mreg = get_neon_m_regno(theInstr); + UInt dreg = get_neon_d_regno(theInstr); + ULong imm = 0; + IROp op, cvt, add = Iop_INVALID, cvt2, op_rev; + IRTemp reg_m, res, mask; + + if (L == 0 && ((theInstr >> 19) & 7) == 0) + /* It is one reg and immediate */ + return False; + + tmp = (L << 6) | imm6; + if (tmp & 0x40) { + size = 3; + shift_imm = 64 - imm6; + } else if (tmp & 0x20) { + size = 2; + shift_imm = 64 - imm6; + } else if (tmp & 0x10) { + size = 1; + shift_imm = 32 - imm6; + } else if (tmp & 0x8) { + size = 0; + shift_imm = 16 - imm6; + } else { + return False; + } + + switch (A) { + case 3: + case 2: + /* VRSHR, VRSRA */ + if (shift_imm > 0) { + IRExpr *imm_val; + imm = 1L; + switch (size) { + case 0: + imm = (imm << 8) | imm; + /* fall through */ + case 1: + imm = (imm << 16) | imm; + /* fall through */ + case 2: + imm = (imm << 32) | imm; + /* fall through */ + case 3: + break; + default: + vassert(0); + } + if (Q) { + reg_m = newTemp(Ity_V128); + res = newTemp(Ity_V128); + imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm)); + assign(reg_m, getQReg(mreg)); + switch (size) { + case 0: + add = Iop_Add8x16; + op = U ? Iop_ShrN8x16 : Iop_SarN8x16; + break; + case 1: + add = Iop_Add16x8; + op = U ? Iop_ShrN16x8 : Iop_SarN16x8; + break; + case 2: + add = Iop_Add32x4; + op = U ? Iop_ShrN32x4 : Iop_SarN32x4; + break; + case 3: + add = Iop_Add64x2; + op = U ? Iop_ShrN64x2 : Iop_SarN64x2; + break; + default: + vassert(0); + } + } else { + reg_m = newTemp(Ity_I64); + res = newTemp(Ity_I64); + imm_val = mkU64(imm); + assign(reg_m, getDRegI64(mreg)); + switch (size) { + case 0: + add = Iop_Add8x8; + op = U ? Iop_ShrN8x8 : Iop_SarN8x8; + break; + case 1: + add = Iop_Add16x4; + op = U ? Iop_ShrN16x4 : Iop_SarN16x4; + break; + case 2: + add = Iop_Add32x2; + op = U ? Iop_ShrN32x2 : Iop_SarN32x2; + break; + case 3: + add = Iop_Add64; + op = U ? Iop_Shr64 : Iop_Sar64; + break; + default: + vassert(0); + } + } + assign(res, + binop(add, + binop(op, + mkexpr(reg_m), + mkU8(shift_imm)), + binop(Q ? Iop_AndV128 : Iop_And64, + binop(op, + mkexpr(reg_m), + mkU8(shift_imm - 1)), + imm_val))); + } else { + if (Q) { + res = newTemp(Ity_V128); + assign(res, getQReg(mreg)); + } else { + res = newTemp(Ity_I64); + assign(res, getDRegI64(mreg)); + } + } + if (A == 3) { + if (Q) { + putQReg(dreg, binop(add, mkexpr(res), getQReg(dreg)), + condT); + } else { + putDRegI64(dreg, binop(add, mkexpr(res), getDRegI64(dreg)), + condT); + } + DIP("vrsra.%c%u %c%u, %c%u, #%u\n", + U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm); + } else { + if (Q) { + putQReg(dreg, mkexpr(res), condT); + } else { + putDRegI64(dreg, mkexpr(res), condT); + } + DIP("vrshr.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm); + } + return True; + case 1: + case 0: + /* VSHR, VSRA */ + if (Q) { + reg_m = newTemp(Ity_V128); + assign(reg_m, getQReg(mreg)); + res = newTemp(Ity_V128); + } else { + reg_m = newTemp(Ity_I64); + assign(reg_m, getDRegI64(mreg)); + res = newTemp(Ity_I64); + } + if (Q) { + switch (size) { + case 0: + op = U ? Iop_ShrN8x16 : Iop_SarN8x16; + add = Iop_Add8x16; + break; + case 1: + op = U ? Iop_ShrN16x8 : Iop_SarN16x8; + add = Iop_Add16x8; + break; + case 2: + op = U ? Iop_ShrN32x4 : Iop_SarN32x4; + add = Iop_Add32x4; + break; + case 3: + op = U ? Iop_ShrN64x2 : Iop_SarN64x2; + add = Iop_Add64x2; + break; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op = U ? Iop_ShrN8x8 : Iop_SarN8x8; + add = Iop_Add8x8; + break; + case 1: + op = U ? Iop_ShrN16x4 : Iop_SarN16x4; + add = Iop_Add16x4; + break; + case 2: + op = U ? Iop_ShrN32x2 : Iop_SarN32x2; + add = Iop_Add32x2; + break; + case 3: + op = U ? Iop_Shr64 : Iop_Sar64; + add = Iop_Add64; + break; + default: + vassert(0); + } + } + assign(res, binop(op, mkexpr(reg_m), mkU8(shift_imm))); + if (A == 1) { + if (Q) { + putQReg(dreg, binop(add, mkexpr(res), getQReg(dreg)), + condT); + } else { + putDRegI64(dreg, binop(add, mkexpr(res), getDRegI64(dreg)), + condT); + } + DIP("vsra.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm); + } else { + if (Q) { + putQReg(dreg, mkexpr(res), condT); + } else { + putDRegI64(dreg, mkexpr(res), condT); + } + DIP("vshr.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm); + } + return True; + case 4: + /* VSRI */ + if (!U) + return False; + if (Q) { + res = newTemp(Ity_V128); + mask = newTemp(Ity_V128); + } else { + res = newTemp(Ity_I64); + mask = newTemp(Ity_I64); + } + switch (size) { + case 0: op = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; break; + case 1: op = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; break; + case 2: op = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; break; + case 3: op = Q ? Iop_ShrN64x2 : Iop_Shr64; break; + default: vassert(0); + } + if (Q) { + assign(mask, binop(op, binop(Iop_64HLtoV128, + mkU64(0xFFFFFFFFFFFFFFFFLL), + mkU64(0xFFFFFFFFFFFFFFFFLL)), + mkU8(shift_imm))); + assign(res, binop(Iop_OrV128, + binop(Iop_AndV128, + getQReg(dreg), + unop(Iop_NotV128, + mkexpr(mask))), + binop(op, + getQReg(mreg), + mkU8(shift_imm)))); + putQReg(dreg, mkexpr(res), condT); + } else { + assign(mask, binop(op, mkU64(0xFFFFFFFFFFFFFFFFLL), + mkU8(shift_imm))); + assign(res, binop(Iop_Or64, + binop(Iop_And64, + getDRegI64(dreg), + unop(Iop_Not64, + mkexpr(mask))), + binop(op, + getDRegI64(mreg), + mkU8(shift_imm)))); + putDRegI64(dreg, mkexpr(res), condT); + } + DIP("vsri.%u %c%u, %c%u, #%u\n", + 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg, shift_imm); + return True; + case 5: + if (U) { + /* VSLI */ + shift_imm = 8 * (1 << size) - shift_imm; + if (Q) { + res = newTemp(Ity_V128); + mask = newTemp(Ity_V128); + } else { + res = newTemp(Ity_I64); + mask = newTemp(Ity_I64); + } + switch (size) { + case 0: op = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; break; + case 1: op = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; break; + case 2: op = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; break; + case 3: op = Q ? Iop_ShlN64x2 : Iop_Shl64; break; + default: vassert(0); + } + if (Q) { + assign(mask, binop(op, binop(Iop_64HLtoV128, + mkU64(0xFFFFFFFFFFFFFFFFLL), + mkU64(0xFFFFFFFFFFFFFFFFLL)), + mkU8(shift_imm))); + assign(res, binop(Iop_OrV128, + binop(Iop_AndV128, + getQReg(dreg), + unop(Iop_NotV128, + mkexpr(mask))), + binop(op, + getQReg(mreg), + mkU8(shift_imm)))); + putQReg(dreg, mkexpr(res), condT); + } else { + assign(mask, binop(op, mkU64(0xFFFFFFFFFFFFFFFFLL), + mkU8(shift_imm))); + assign(res, binop(Iop_Or64, + binop(Iop_And64, + getDRegI64(dreg), + unop(Iop_Not64, + mkexpr(mask))), + binop(op, + getDRegI64(mreg), + mkU8(shift_imm)))); + putDRegI64(dreg, mkexpr(res), condT); + } + DIP("vsli.%u %c%u, %c%u, #%u\n", + 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg, shift_imm); + return True; + } else { + /* VSHL #imm */ + shift_imm = 8 * (1 << size) - shift_imm; + if (Q) { + res = newTemp(Ity_V128); + } else { + res = newTemp(Ity_I64); + } + switch (size) { + case 0: op = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; break; + case 1: op = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; break; + case 2: op = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; break; + case 3: op = Q ? Iop_ShlN64x2 : Iop_Shl64; break; + default: vassert(0); + } + assign(res, binop(op, Q ? getQReg(mreg) : getDRegI64(mreg), + mkU8(shift_imm))); + if (Q) { + putQReg(dreg, mkexpr(res), condT); + } else { + putDRegI64(dreg, mkexpr(res), condT); + } + DIP("vshl.i%u %c%u, %c%u, #%u\n", + 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg, shift_imm); + return True; + } + break; + case 6: + case 7: + /* VQSHL, VQSHLU */ + shift_imm = 8 * (1 << size) - shift_imm; + if (U) { + if (A & 1) { + switch (size) { + case 0: + op = Q ? Iop_QShlN8x16 : Iop_QShlN8x8; + op_rev = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + break; + case 1: + op = Q ? Iop_QShlN16x8 : Iop_QShlN16x4; + op_rev = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + break; + case 2: + op = Q ? Iop_QShlN32x4 : Iop_QShlN32x2; + op_rev = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + break; + case 3: + op = Q ? Iop_QShlN64x2 : Iop_QShlN64x1; + op_rev = Q ? Iop_ShrN64x2 : Iop_Shr64; + break; + default: + vassert(0); + } + DIP("vqshl.u%u %c%u, %c%u, #%u\n", + 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm); + } else { + switch (size) { + case 0: + op = Q ? Iop_QShlN8Sx16 : Iop_QShlN8Sx8; + op_rev = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; + break; + case 1: + op = Q ? Iop_QShlN16Sx8 : Iop_QShlN16Sx4; + op_rev = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; + break; + case 2: + op = Q ? Iop_QShlN32Sx4 : Iop_QShlN32Sx2; + op_rev = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; + break; + case 3: + op = Q ? Iop_QShlN64Sx2 : Iop_QShlN64Sx1; + op_rev = Q ? Iop_ShrN64x2 : Iop_Shr64; + break; + default: + vassert(0); + } + DIP("vqshlu.s%u %c%u, %c%u, #%u\n", + 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm); + } + } else { + if (!(A & 1)) + return False; + switch (size) { + case 0: + op = Q ? Iop_QSalN8x16 : Iop_QSalN8x8; + op_rev = Q ? Iop_SarN8x16 : Iop_SarN8x8; + break; + case 1: + op = Q ? Iop_QSalN16x8 : Iop_QSalN16x4; + op_rev = Q ? Iop_SarN16x8 : Iop_SarN16x4; + break; + case 2: + op = Q ? Iop_QSalN32x4 : Iop_QSalN32x2; + op_rev = Q ? Iop_SarN32x4 : Iop_SarN32x2; + break; + case 3: + op = Q ? Iop_QSalN64x2 : Iop_QSalN64x1; + op_rev = Q ? Iop_SarN64x2 : Iop_Sar64; + break; + default: + vassert(0); + } + DIP("vqshl.s%u %c%u, %c%u, #%u\n", + 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm); + } + if (Q) { + tmp = newTemp(Ity_V128); + res = newTemp(Ity_V128); + reg_m = newTemp(Ity_V128); + assign(reg_m, getQReg(mreg)); + } else { + tmp = newTemp(Ity_I64); + res = newTemp(Ity_I64); + reg_m = newTemp(Ity_I64); + assign(reg_m, getDRegI64(mreg)); + } + assign(res, binop(op, mkexpr(reg_m), mkU8(shift_imm))); +#ifndef DISABLE_QC_FLAG + assign(tmp, binop(op_rev, mkexpr(res), mkU8(shift_imm))); + setFlag_QC(mkexpr(tmp), mkexpr(reg_m), Q, condT); +#endif + if (Q) + putQReg(dreg, mkexpr(res), condT); + else + putDRegI64(dreg, mkexpr(res), condT); + return True; + case 8: + if (!U) { + if (L == 1) + return False; + size++; + dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); + mreg = ((theInstr >> 1) & 0x10) | (theInstr & 0xF); + if (mreg & 1) + return False; + mreg >>= 1; + if (!B) { + /* VSHRN*/ + IROp narOp; + reg_m = newTemp(Ity_V128); + assign(reg_m, getQReg(mreg)); + res = newTemp(Ity_I64); + switch (size) { + case 1: + op = Iop_ShrN16x8; + narOp = Iop_Shorten16x8; + break; + case 2: + op = Iop_ShrN32x4; + narOp = Iop_Shorten32x4; + break; + case 3: + op = Iop_ShrN64x2; + narOp = Iop_Shorten64x2; + break; + default: + vassert(0); + } + assign(res, unop(narOp, + binop(op, + mkexpr(reg_m), + mkU8(shift_imm)))); + putDRegI64(dreg, mkexpr(res), condT); + DIP("vshrn.i%u d%u, q%u, #%u\n", 8 << size, dreg, mreg, + shift_imm); + return True; + } else { + /* VRSHRN */ + IROp addOp, shOp, narOp; + IRExpr *imm_val; + reg_m = newTemp(Ity_V128); + assign(reg_m, getQReg(mreg)); + res = newTemp(Ity_I64); + imm = 1L; + switch (size) { + case 0: imm = (imm << 8) | imm; /* fall through */ + case 1: imm = (imm << 16) | imm; /* fall through */ + case 2: imm = (imm << 32) | imm; /* fall through */ + case 3: break; + default: vassert(0); + } + imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm)); + switch (size) { + case 1: + addOp = Iop_Add16x8; + shOp = Iop_ShrN16x8; + narOp = Iop_Shorten16x8; + break; + case 2: + addOp = Iop_Add32x4; + shOp = Iop_ShrN32x4; + narOp = Iop_Shorten32x4; + break; + case 3: + addOp = Iop_Add64x2; + shOp = Iop_ShrN64x2; + narOp = Iop_Shorten64x2; + break; + default: + vassert(0); + } + assign(res, unop(narOp, + binop(addOp, + binop(shOp, + mkexpr(reg_m), + mkU8(shift_imm)), + binop(Iop_AndV128, + binop(shOp, + mkexpr(reg_m), + mkU8(shift_imm - 1)), + imm_val)))); + putDRegI64(dreg, mkexpr(res), condT); + if (shift_imm == 0) { + DIP("vmov%u d%u, q%u, #%u\n", 8 << size, dreg, mreg, + shift_imm); + } else { + DIP("vrshrn.i%u d%u, q%u, #%u\n", 8 << size, dreg, mreg, + shift_imm); + } + return True; + } + } else { + /* fall through */ + } + case 9: + dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); + mreg = ((theInstr >> 1) & 0x10) | (theInstr & 0xF); + if (mreg & 1) + return False; + mreg >>= 1; + size++; + if ((theInstr >> 8) & 1) { + switch (size) { + case 1: + op = U ? Iop_ShrN16x8 : Iop_SarN16x8; + cvt = U ? Iop_QShortenU16Ux8 : Iop_QShortenS16Sx8; + cvt2 = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8; + break; + case 2: + op = U ? Iop_ShrN32x4 : Iop_SarN32x4; + cvt = U ? Iop_QShortenU32Ux4 : Iop_QShortenS32Sx4; + cvt2 = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4; + break; + case 3: + op = U ? Iop_ShrN64x2 : Iop_SarN64x2; + cvt = U ? Iop_QShortenU64Ux2 : Iop_QShortenS64Sx2; + cvt2 = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2; + break; + default: + vassert(0); + } + DIP("vq%sshrn.%c%u d%u, q%u, #%u\n", B ? "r" : "", + U ? 'u' : 's', 8 << size, dreg, mreg, shift_imm); + } else { + vassert(U); + switch (size) { + case 1: + op = Iop_SarN16x8; + cvt = Iop_QShortenU16Sx8; + cvt2 = Iop_Longen8Ux8; + break; + case 2: + op = Iop_SarN32x4; + cvt = Iop_QShortenU32Sx4; + cvt2 = Iop_Longen16Ux4; + break; + case 3: + op = Iop_SarN64x2; + cvt = Iop_QShortenU64Sx2; + cvt2 = Iop_Longen32Ux2; + break; + default: + vassert(0); + } + DIP("vq%sshrun.s%u d%u, q%u, #%u\n", B ? "r" : "", + 8 << size, dreg, mreg, shift_imm); + } + if (B) { + if (shift_imm > 0) { + imm = 1; + switch (size) { + case 1: imm = (imm << 16) | imm; /* fall through */ + case 2: imm = (imm << 32) | imm; /* fall through */ + case 3: break; + case 0: default: vassert(0); + } + switch (size) { + case 1: add = Iop_Add16x8; break; + case 2: add = Iop_Add32x4; break; + case 3: add = Iop_Add64x2; break; + case 0: default: vassert(0); + } + } + } + reg_m = newTemp(Ity_V128); + res = newTemp(Ity_V128); + assign(reg_m, getQReg(mreg)); + if (B) { + /* VQRSHRN, VQRSHRUN */ + assign(res, binop(add, + binop(op, mkexpr(reg_m), mkU8(shift_imm)), + binop(Iop_AndV128, + binop(op, + mkexpr(reg_m), + mkU8(shift_imm - 1)), + mkU128(imm)))); + } else { + /* VQSHRN, VQSHRUN */ + assign(res, binop(op, mkexpr(reg_m), mkU8(shift_imm))); + } +#ifndef DISABLE_QC_FLAG + setFlag_QC(unop(cvt2, unop(cvt, mkexpr(res))), mkexpr(res), + True, condT); +#endif + putDRegI64(dreg, unop(cvt, mkexpr(res)), condT); + return True; + case 10: + /* VSHLL + VMOVL ::= VSHLL #0 */ + if (B) + return False; + if (dreg & 1) + return False; + dreg >>= 1; + shift_imm = (8 << size) - shift_imm; + res = newTemp(Ity_V128); + switch (size) { + case 0: + op = Iop_ShlN16x8; + cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8; + break; + case 1: + op = Iop_ShlN32x4; + cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4; + break; + case 2: + op = Iop_ShlN64x2; + cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2; + break; + case 3: + return False; + default: + vassert(0); + } + assign(res, binop(op, unop(cvt, getDRegI64(mreg)), mkU8(shift_imm))); + putQReg(dreg, mkexpr(res), condT); + if (shift_imm == 0) { + DIP("vmovl.%c%u q%u, d%u\n", U ? 'u' : 's', 8 << size, + dreg, mreg); + } else { + DIP("vshll.%c%u q%u, d%u, #%u\n", U ? 'u' : 's', 8 << size, + dreg, mreg, shift_imm); + } + return True; + case 14: + case 15: + /* VCVT floating-point <-> fixed-point */ + if ((theInstr >> 8) & 1) { + if (U) { + op = Q ? Iop_F32ToFixed32Ux4_RZ : Iop_F32ToFixed32Ux2_RZ; + } else { + op = Q ? Iop_F32ToFixed32Sx4_RZ : Iop_F32ToFixed32Sx2_RZ; + } + DIP("vcvt.%c32.f32 %c%u, %c%u, #%u\n", U ? 'u' : 's', + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, + 64 - ((theInstr >> 16) & 0x3f)); + } else { + if (U) { + op = Q ? Iop_Fixed32UToF32x4_RN : Iop_Fixed32UToF32x2_RN; + } else { + op = Q ? Iop_Fixed32SToF32x4_RN : Iop_Fixed32SToF32x2_RN; + } + DIP("vcvt.f32.%c32 %c%u, %c%u, #%u\n", U ? 'u' : 's', + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, + 64 - ((theInstr >> 16) & 0x3f)); + } + if (((theInstr >> 21) & 1) == 0) + return False; + if (Q) { + putQReg(dreg, binop(op, getQReg(mreg), + mkU8(64 - ((theInstr >> 16) & 0x3f))), condT); + } else { + putDRegI64(dreg, binop(op, getDRegI64(mreg), + mkU8(64 - ((theInstr >> 16) & 0x3f))), condT); + } + return True; + default: + return False; + + } + return False; +} + +/* A7.4.5 Two registers, miscellaneous */ +static +Bool dis_neon_data_2reg_misc ( UInt theInstr, IRTemp condT ) +{ + UInt A = (theInstr >> 16) & 3; + UInt B = (theInstr >> 6) & 0x1f; + UInt Q = (theInstr >> 6) & 1; + UInt U = (theInstr >> 24) & 1; + UInt size = (theInstr >> 18) & 3; + UInt dreg = get_neon_d_regno(theInstr); + UInt mreg = get_neon_m_regno(theInstr); + UInt F = (theInstr >> 10) & 1; + IRTemp arg_d; + IRTemp arg_m; + IRTemp res; + switch (A) { + case 0: + if (Q) { + arg_m = newTemp(Ity_V128); + res = newTemp(Ity_V128); + assign(arg_m, getQReg(mreg)); + } else { + arg_m = newTemp(Ity_I64); + res = newTemp(Ity_I64); + assign(arg_m, getDRegI64(mreg)); + } + switch (B >> 1) { + case 0: { + /* VREV64 */ + IROp op; + switch (size) { + case 0: + op = Q ? Iop_Reverse64_8x16 : Iop_Reverse64_8x8; + break; + case 1: + op = Q ? Iop_Reverse64_16x8 : Iop_Reverse64_16x4; + break; + case 2: + op = Q ? Iop_Reverse64_32x4 : Iop_Reverse64_32x2; + break; + case 3: + return False; + default: + vassert(0); + } + assign(res, unop(op, mkexpr(arg_m))); + DIP("vrev64.%u %c%u, %c%u\n", 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 1: { + /* VREV32 */ + IROp op; + switch (size) { + case 0: + op = Q ? Iop_Reverse32_8x16 : Iop_Reverse32_8x8; + break; + case 1: + op = Q ? Iop_Reverse32_16x8 : Iop_Reverse32_16x4; + break; + case 2: + case 3: + return False; + default: + vassert(0); + } + assign(res, unop(op, mkexpr(arg_m))); + DIP("vrev32.%u %c%u, %c%u\n", 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 2: { + /* VREV16 */ + IROp op; + switch (size) { + case 0: + op = Q ? Iop_Reverse16_8x16 : Iop_Reverse16_8x8; + break; + case 1: + case 2: + case 3: + return False; + default: + vassert(0); + } + assign(res, unop(op, mkexpr(arg_m))); + DIP("vrev16.%u %c%u, %c%u\n", 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 3: + return False; + case 4: + case 5: { + /* VPADDL */ + IROp op; + U = (theInstr >> 7) & 1; + if (Q) { + switch (size) { + case 0: op = U ? Iop_PwAddL8Ux16 : Iop_PwAddL8Sx16; break; + case 1: op = U ? Iop_PwAddL16Ux8 : Iop_PwAddL16Sx8; break; + case 2: op = U ? Iop_PwAddL32Ux4 : Iop_PwAddL32Sx4; break; + case 3: return False; + default: vassert(0); + } + } else { + switch (size) { + case 0: op = U ? Iop_PwAddL8Ux8 : Iop_PwAddL8Sx8; break; + case 1: op = U ? Iop_PwAddL16Ux4 : Iop_PwAddL16Sx4; break; + case 2: op = U ? Iop_PwAddL32Ux2 : Iop_PwAddL32Sx2; break; + case 3: return False; + default: vassert(0); + } + } + assign(res, unop(op, mkexpr(arg_m))); + DIP("vpaddl.%c%u %c%u, %c%u\n", U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 6: + case 7: + return False; + case 8: { + /* VCLS */ + IROp op; + switch (size) { + case 0: op = Q ? Iop_Cls8Sx16 : Iop_Cls8Sx8; break; + case 1: op = Q ? Iop_Cls16Sx8 : Iop_Cls16Sx4; break; + case 2: op = Q ? Iop_Cls32Sx4 : Iop_Cls32Sx2; break; + case 3: return False; + default: vassert(0); + } + assign(res, unop(op, mkexpr(arg_m))); + DIP("vcls.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg); + break; + } + case 9: { + /* VCLZ */ + IROp op; + switch (size) { + case 0: op = Q ? Iop_Clz8Sx16 : Iop_Clz8Sx8; break; + case 1: op = Q ? Iop_Clz16Sx8 : Iop_Clz16Sx4; break; + case 2: op = Q ? Iop_Clz32Sx4 : Iop_Clz32Sx2; break; + case 3: return False; + default: vassert(0); + } + assign(res, unop(op, mkexpr(arg_m))); + DIP("vclz.i%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg); + break; + } + case 10: + /* VCNT */ + assign(res, unop(Q ? Iop_Cnt8x16 : Iop_Cnt8x8, mkexpr(arg_m))); + DIP("vcnt.8 %c%u, %c%u\n", Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', + mreg); + break; + case 11: + /* VMVN */ + if (Q) + assign(res, unop(Iop_NotV128, mkexpr(arg_m))); + else + assign(res, unop(Iop_Not64, mkexpr(arg_m))); + DIP("vmvn %c%u, %c%u\n", Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', + mreg); + break; + case 12: + case 13: { + /* VPADAL */ + IROp op, add_op; + U = (theInstr >> 7) & 1; + if (Q) { + switch (size) { + case 0: + op = U ? Iop_PwAddL8Ux16 : Iop_PwAddL8Sx16; + add_op = Iop_Add16x8; + break; + case 1: + op = U ? Iop_PwAddL16Ux8 : Iop_PwAddL16Sx8; + add_op = Iop_Add32x4; + break; + case 2: + op = U ? Iop_PwAddL32Ux4 : Iop_PwAddL32Sx4; + add_op = Iop_Add64x2; + break; + case 3: + return False; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op = U ? Iop_PwAddL8Ux8 : Iop_PwAddL8Sx8; + add_op = Iop_Add16x4; + break; + case 1: + op = U ? Iop_PwAddL16Ux4 : Iop_PwAddL16Sx4; + add_op = Iop_Add32x2; + break; + case 2: + op = U ? Iop_PwAddL32Ux2 : Iop_PwAddL32Sx2; + add_op = Iop_Add64; + break; + case 3: + return False; + default: + vassert(0); + } + } + if (Q) { + arg_d = newTemp(Ity_V128); + assign(arg_d, getQReg(dreg)); + } else { + arg_d = newTemp(Ity_I64); + assign(arg_d, getDRegI64(dreg)); + } + assign(res, binop(add_op, unop(op, mkexpr(arg_m)), + mkexpr(arg_d))); + DIP("vpadal.%c%u %c%u, %c%u\n", U ? 'u' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 14: { + /* VQABS */ + IROp op_sub, op_qsub, op_cmp; + IRTemp mask, tmp; + IRExpr *zero1, *zero2; + IRExpr *neg, *neg2; + if (Q) { + zero1 = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + zero2 = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + mask = newTemp(Ity_V128); + tmp = newTemp(Ity_V128); + } else { + zero1 = mkU64(0); + zero2 = mkU64(0); + mask = newTemp(Ity_I64); + tmp = newTemp(Ity_I64); + } + switch (size) { + case 0: + op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8; + op_qsub = Q ? Iop_QSub8Sx16 : Iop_QSub8Sx8; + op_cmp = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; + break; + case 1: + op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4; + op_qsub = Q ? Iop_QSub16Sx8 : Iop_QSub16Sx4; + op_cmp = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; + break; + case 2: + op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2; + op_qsub = Q ? Iop_QSub32Sx4 : Iop_QSub32Sx2; + op_cmp = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; + break; + case 3: + return False; + default: + vassert(0); + } + assign(mask, binop(op_cmp, mkexpr(arg_m), zero1)); + neg = binop(op_qsub, zero2, mkexpr(arg_m)); + neg2 = binop(op_sub, zero2, mkexpr(arg_m)); + assign(res, binop(Q ? Iop_OrV128 : Iop_Or64, + binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(mask), + mkexpr(arg_m)), + binop(Q ? Iop_AndV128 : Iop_And64, + unop(Q ? Iop_NotV128 : Iop_Not64, + mkexpr(mask)), + neg))); +#ifndef DISABLE_QC_FLAG + assign(tmp, binop(Q ? Iop_OrV128 : Iop_Or64, + binop(Q ? Iop_AndV128 : Iop_And64, + mkexpr(mask), + mkexpr(arg_m)), + binop(Q ? Iop_AndV128 : Iop_And64, + unop(Q ? Iop_NotV128 : Iop_Not64, + mkexpr(mask)), + neg2))); + setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT); +#endif + DIP("vqabs.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg); + break; + } + case 15: { + /* VQNEG */ + IROp op, op2; + IRExpr *zero; + if (Q) { + zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + } else { + zero = mkU64(0); + } + switch (size) { + case 0: + op = Q ? Iop_QSub8Sx16 : Iop_QSub8Sx8; + op2 = Q ? Iop_Sub8x16 : Iop_Sub8x8; + break; + case 1: + op = Q ? Iop_QSub16Sx8 : Iop_QSub16Sx4; + op2 = Q ? Iop_Sub16x8 : Iop_Sub16x4; + break; + case 2: + op = Q ? Iop_QSub32Sx4 : Iop_QSub32Sx2; + op2 = Q ? Iop_Sub32x4 : Iop_Sub32x2; + break; + case 3: + return False; + default: + vassert(0); + } + assign(res, binop(op, zero, mkexpr(arg_m))); +#ifndef DISABLE_QC_FLAG + setFlag_QC(mkexpr(res), binop(op2, zero, mkexpr(arg_m)), + Q, condT); +#endif + DIP("vqneg.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg); + break; + } + default: + vassert(0); + } + if (Q) { + putQReg(dreg, mkexpr(res), condT); + } else { + putDRegI64(dreg, mkexpr(res), condT); + } + return True; + case 1: + if (Q) { + arg_m = newTemp(Ity_V128); + res = newTemp(Ity_V128); + assign(arg_m, getQReg(mreg)); + } else { + arg_m = newTemp(Ity_I64); + res = newTemp(Ity_I64); + assign(arg_m, getDRegI64(mreg)); + } + switch ((B >> 1) & 0x7) { + case 0: { + /* VCGT #0 */ + IRExpr *zero; + IROp op; + if (Q) { + zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + } else { + zero = mkU64(0); + } + if (F) { + switch (size) { + case 0: case 1: case 3: return False; + case 2: op = Q ? Iop_CmpGT32Fx4 : Iop_CmpGT32Fx2; break; + default: vassert(0); + } + } else { + switch (size) { + case 0: op = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; break; + case 1: op = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; break; + case 2: op = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; break; + case 3: return False; + default: vassert(0); + } + } + assign(res, binop(op, mkexpr(arg_m), zero)); + DIP("vcgt.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 1: { + /* VCGE #0 */ + IROp op; + IRExpr *zero; + if (Q) { + zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + } else { + zero = mkU64(0); + } + if (F) { + switch (size) { + case 0: case 1: case 3: return False; + case 2: op = Q ? Iop_CmpGE32Fx4 : Iop_CmpGE32Fx2; break; + default: vassert(0); + } + assign(res, binop(op, mkexpr(arg_m), zero)); + } else { + switch (size) { + case 0: op = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; break; + case 1: op = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; break; + case 2: op = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; break; + case 3: return False; + default: vassert(0); + } + assign(res, unop(Q ? Iop_NotV128 : Iop_Not64, + binop(op, zero, mkexpr(arg_m)))); + } + DIP("vcge.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 2: { + /* VCEQ #0 */ + IROp op; + IRExpr *zero; + if (F) { + if (Q) { + zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + } else { + zero = mkU64(0); + } + switch (size) { + case 0: case 1: case 3: return False; + case 2: op = Q ? Iop_CmpEQ32Fx4 : Iop_CmpEQ32Fx2; break; + default: vassert(0); + } + assign(res, binop(op, zero, mkexpr(arg_m))); + } else { + switch (size) { + case 0: op = Q ? Iop_CmpNEZ8x16 : Iop_CmpNEZ8x8; break; + case 1: op = Q ? Iop_CmpNEZ16x8 : Iop_CmpNEZ16x4; break; + case 2: op = Q ? Iop_CmpNEZ32x4 : Iop_CmpNEZ32x2; break; + case 3: return False; + default: vassert(0); + } + assign(res, unop(Q ? Iop_NotV128 : Iop_Not64, + unop(op, mkexpr(arg_m)))); + } + DIP("vceq.%c%u %c%u, %c%u, #0\n", F ? 'f' : 'i', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 3: { + /* VCLE #0 */ + IRExpr *zero; + IROp op; + if (Q) { + zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + } else { + zero = mkU64(0); + } + if (F) { + switch (size) { + case 0: case 1: case 3: return False; + case 2: op = Q ? Iop_CmpGE32Fx4 : Iop_CmpGE32Fx2; break; + default: vassert(0); + } + assign(res, binop(op, zero, mkexpr(arg_m))); + } else { + switch (size) { + case 0: op = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; break; + case 1: op = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; break; + case 2: op = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; break; + case 3: return False; + default: vassert(0); + } + assign(res, unop(Q ? Iop_NotV128 : Iop_Not64, + binop(op, mkexpr(arg_m), zero))); + } + DIP("vcle.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 4: { + /* VCLT #0 */ + IROp op; + IRExpr *zero; + if (Q) { + zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + } else { + zero = mkU64(0); + } + if (F) { + switch (size) { + case 0: case 1: case 3: return False; + case 2: op = Q ? Iop_CmpGT32Fx4 : Iop_CmpGT32Fx2; break; + default: vassert(0); + } + assign(res, binop(op, zero, mkexpr(arg_m))); + } else { + switch (size) { + case 0: op = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; break; + case 1: op = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; break; + case 2: op = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; break; + case 3: return False; + default: vassert(0); + } + assign(res, binop(op, zero, mkexpr(arg_m))); + } + DIP("vclt.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size, + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + } + case 5: + return False; + case 6: { + /* VABS */ + if (!F) { + IROp op; + switch(size) { + case 0: op = Q ? Iop_Abs8x16 : Iop_Abs8x8; break; + case 1: op = Q ? Iop_Abs16x8 : Iop_Abs16x4; break; + case 2: op = Q ? Iop_Abs32x4 : Iop_Abs32x2; break; + case 3: return False; + default: vassert(0); + } + assign(res, unop(op, mkexpr(arg_m))); + } else { + assign(res, unop(Q ? Iop_Abs32Fx4 : Iop_Abs32Fx2, + mkexpr(arg_m))); + } + DIP("vabs.%c%u %c%u, %c%u\n", + F ? 'f' : 's', 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg); + break; + } + case 7: { + /* VNEG */ + IROp op; + IRExpr *zero; + if (F) { + switch (size) { + case 0: case 1: case 3: return False; + case 2: op = Q ? Iop_Neg32Fx4 : Iop_Neg32Fx2; break; + default: vassert(0); + } + assign(res, unop(op, mkexpr(arg_m))); + } else { + if (Q) { + zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0)); + } else { + zero = mkU64(0); + } + switch (size) { + case 0: op = Q ? Iop_Sub8x16 : Iop_Sub8x8; break; + case 1: op = Q ? Iop_Sub16x8 : Iop_Sub16x4; break; + case 2: op = Q ? Iop_Sub32x4 : Iop_Sub32x2; break; + case 3: return False; + default: vassert(0); + } + assign(res, binop(op, zero, mkexpr(arg_m))); + } + DIP("vneg.%c%u %c%u, %c%u\n", + F ? 'f' : 's', 8 << size, Q ? 'q' : 'd', dreg, + Q ? 'q' : 'd', mreg); + break; + } + default: + vassert(0); + } + if (Q) { + putQReg(dreg, mkexpr(res), condT); + } else { + putDRegI64(dreg, mkexpr(res), condT); + } + return True; + case 2: + if ((B >> 1) == 0) { + /* VSWP */ + if (Q) { + arg_m = newTemp(Ity_V128); + assign(arg_m, getQReg(mreg)); + putQReg(mreg, getQReg(dreg), condT); + putQReg(dreg, mkexpr(arg_m), condT); + } else { + arg_m = newTemp(Ity_I64); + assign(arg_m, getDRegI64(mreg)); + putDRegI64(mreg, getDRegI64(dreg), condT); + putDRegI64(dreg, mkexpr(arg_m), condT); + } + DIP("vswp %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + return True; + } else if ((B >> 1) == 1) { + /* VTRN */ + IROp op_lo, op_hi; + IRTemp res1, res2; + if (Q) { + arg_m = newTemp(Ity_V128); + arg_d = newTemp(Ity_V128); + res1 = newTemp(Ity_V128); + res2 = newTemp(Ity_V128); + assign(arg_m, getQReg(mreg)); + assign(arg_d, getQReg(dreg)); + } else { + res1 = newTemp(Ity_I64); + res2 = newTemp(Ity_I64); + arg_m = newTemp(Ity_I64); + arg_d = newTemp(Ity_I64); + assign(arg_m, getDRegI64(mreg)); + assign(arg_d, getDRegI64(dreg)); + } + if (Q) { + switch (size) { + case 0: + op_lo = Iop_InterleaveOddLanes8x16; + op_hi = Iop_InterleaveEvenLanes8x16; + break; + case 1: + op_lo = Iop_InterleaveOddLanes16x8; + op_hi = Iop_InterleaveEvenLanes16x8; + break; + case 2: + op_lo = Iop_InterleaveOddLanes32x4; + op_hi = Iop_InterleaveEvenLanes32x4; + break; + case 3: + return False; + default: + vassert(0); + } + } else { + switch (size) { + case 0: + op_lo = Iop_InterleaveOddLanes8x8; + op_hi = Iop_InterleaveEvenLanes8x8; + break; + case 1: + op_lo = Iop_InterleaveOddLanes16x4; + op_hi = Iop_InterleaveEvenLanes16x4; + break; + case 2: + op_lo = Iop_InterleaveLO32x2; + op_hi = Iop_InterleaveHI32x2; + break; + case 3: + return False; + default: + vassert(0); + } + } + assign(res1, binop(op_lo, mkexpr(arg_m), mkexpr(arg_d))); + assign(res2, binop(op_hi, mkexpr(arg_m), mkexpr(arg_d))); + if (Q) { + putQReg(dreg, mkexpr(res1), condT); + putQReg(mreg, mkexpr(res2), condT); + } else { + putDRegI64(dreg, mkexpr(res1), condT); + putDRegI64(mreg, mkexpr(res2), condT); + } + DIP("vtrn.%u %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + return True; + } else if ((B >> 1) == 2) { + /* VUZP */ + IROp op_lo, op_hi; + IRTemp res1, res2; + if (!Q && size == 2) + return False; + if (Q) { + arg_m = newTemp(Ity_V128); + arg_d = newTemp(Ity_V128); + res1 = newTemp(Ity_V128); + res2 = newTemp(Ity_V128); + assign(arg_m, getQReg(mreg)); + assign(arg_d, getQReg(dreg)); + } else { + res1 = newTemp(Ity_I64); + res2 = newTemp(Ity_I64); + arg_m = newTemp(Ity_I64); + arg_d = newTemp(Ity_I64); + assign(arg_m, getDRegI64(mreg)); + assign(arg_d, getDRegI64(dreg)); + } + switch (size) { + case 0: + op_lo = Q ? Iop_CatOddLanes8x16 : Iop_CatOddLanes8x8; + op_hi = Q ? Iop_CatEvenLanes8x16 : Iop_CatEvenLanes8x8; + break; + case 1: + op_lo = Q ? Iop_CatOddLanes16x8 : Iop_CatOddLanes16x4; + op_hi = Q ? Iop_CatEvenLanes16x8 : Iop_CatEvenLanes16x4; + break; + case 2: + op_lo = Iop_CatOddLanes32x4; + op_hi = Iop_CatEvenLanes32x4; + break; + case 3: + return False; + default: + vassert(0); + } + assign(res1, binop(op_lo, mkexpr(arg_m), mkexpr(arg_d))); + assign(res2, binop(op_hi, mkexpr(arg_m), mkexpr(arg_d))); + if (Q) { + putQReg(dreg, mkexpr(res1), condT); + putQReg(mreg, mkexpr(res2), condT); + } else { + putDRegI64(dreg, mkexpr(res1), condT); + putDRegI64(mreg, mkexpr(res2), condT); + } + DIP("vuzp.%u %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + return True; + } else if ((B >> 1) == 3) { + /* VZIP */ + IROp op_lo, op_hi; + IRTemp res1, res2; + if (!Q && size == 2) + return False; + if (Q) { + arg_m = newTemp(Ity_V128); + arg_d = newTemp(Ity_V128); + res1 = newTemp(Ity_V128); + res2 = newTemp(Ity_V128); + assign(arg_m, getQReg(mreg)); + assign(arg_d, getQReg(dreg)); + } else { + res1 = newTemp(Ity_I64); + res2 = newTemp(Ity_I64); + arg_m = newTemp(Ity_I64); + arg_d = newTemp(Ity_I64); + assign(arg_m, getDRegI64(mreg)); + assign(arg_d, getDRegI64(dreg)); + } + switch (size) { + case 0: + op_lo = Q ? Iop_InterleaveHI8x16 : Iop_InterleaveHI8x8; + op_hi = Q ? Iop_InterleaveLO8x16 : Iop_InterleaveLO8x8; + break; + case 1: + op_lo = Q ? Iop_InterleaveHI16x8 : Iop_InterleaveHI16x4; + op_hi = Q ? Iop_InterleaveLO16x8 : Iop_InterleaveLO16x4; + break; + case 2: + op_lo = Iop_InterleaveHI32x4; + op_hi = Iop_InterleaveLO32x4; + break; + case 3: + return False; + default: + vassert(0); + } + assign(res1, binop(op_lo, mkexpr(arg_m), mkexpr(arg_d))); + assign(res2, binop(op_hi, mkexpr(arg_m), mkexpr(arg_d))); + if (Q) { + putQReg(dreg, mkexpr(res1), condT); + putQReg(mreg, mkexpr(res2), condT); + } else { + putDRegI64(dreg, mkexpr(res1), condT); + putDRegI64(mreg, mkexpr(res2), condT); + } + DIP("vzip.%u %c%u, %c%u\n", + 8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + return True; + } else if (B == 8) { + /* VMOVN */ + IROp op; + mreg >>= 1; + switch (size) { + case 0: op = Iop_Shorten16x8; break; + case 1: op = Iop_Shorten32x4; break; + case 2: op = Iop_Shorten64x2; break; + case 3: return False; + default: vassert(0); + } + putDRegI64(dreg, unop(op, getQReg(mreg)), condT); + DIP("vmovn.i%u d%u, q%u\n", 16 << size, dreg, mreg); + return True; + } else if (B == 9 || (B >> 1) == 5) { + /* VQMOVN, VQMOVUN */ + IROp op, op2; + IRTemp tmp; + dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); + mreg = ((theInstr >> 1) & 0x10) | (theInstr & 0xF); + if (mreg & 1) + return False; + mreg >>= 1; + switch (size) { + case 0: op2 = Iop_Shorten16x8; break; + case 1: op2 = Iop_Shorten32x4; break; + case 2: op2 = Iop_Shorten64x2; break; + case 3: return False; + default: vassert(0); + } + switch (B & 3) { + case 0: + vassert(0); + case 1: + switch (size) { + case 0: op = Iop_QShortenU16Sx8; break; + case 1: op = Iop_QShortenU32Sx4; break; + case 2: op = Iop_QShortenU64Sx2; break; + case 3: return False; + default: vassert(0); + } + DIP("vqmovun.s%u d%u, q%u\n", 16 << size, dreg, mreg); + break; + case 2: + switch (size) { + case 0: op = Iop_QShortenS16Sx8; break; + case 1: op = Iop_QShortenS32Sx4; break; + case 2: op = Iop_QShortenS64Sx2; break; + case 3: return False; + default: vassert(0); + } + DIP("vqmovn.s%u d%u, q%u\n", 16 << size, dreg, mreg); + break; + case 3: + switch (size) { + case 0: op = Iop_QShortenU16Ux8; break; + case 1: op = Iop_QShortenU32Ux4; break; + case 2: op = Iop_QShortenU64Ux2; break; + case 3: return False; + default: vassert(0); + } + DIP("vqmovn.u%u d%u, q%u\n", 16 << size, dreg, mreg); + break; + default: + vassert(0); + } + res = newTemp(Ity_I64); + tmp = newTemp(Ity_I64); + assign(res, unop(op, getQReg(mreg))); +#ifndef DISABLE_QC_FLAG + assign(tmp, unop(op2, getQReg(mreg))); + setFlag_QC(mkexpr(res), mkexpr(tmp), False, condT); +#endif + putDRegI64(dreg, mkexpr(res), condT); + return True; + } else if (B == 12) { + /* VSHLL (maximum shift) */ + IROp op, cvt; + UInt shift_imm; + if (Q) + return False; + if (dreg & 1) + return False; + dreg >>= 1; + shift_imm = 8 << size; + res = newTemp(Ity_V128); + switch (size) { + case 0: op = Iop_ShlN16x8; cvt = Iop_Longen8Ux8; break; + case 1: op = Iop_ShlN32x4; cvt = Iop_Longen16Ux4; break; + case 2: op = Iop_ShlN64x2; cvt = Iop_Longen32Ux2; break; + case 3: return False; + default: vassert(0); + } + assign(res, binop(op, unop(cvt, getDRegI64(mreg)), + mkU8(shift_imm))); + putQReg(dreg, mkexpr(res), condT); + DIP("vshll.i%u q%u, d%u, #%u\n", 8 << size, dreg, mreg, 8 << size); + return True; + } else if ((B >> 3) == 3 && (B & 3) == 0) { + /* VCVT (half<->single) */ + /* Half-precision extensions are needed to run this */ + vassert(0); // ATC + if (((theInstr >> 18) & 3) != 1) + return False; + if ((theInstr >> 8) & 1) { + if (dreg & 1) + return False; + dreg >>= 1; + putQReg(dreg, unop(Iop_F16toF32x4, getDRegI64(mreg)), + condT); + DIP("vcvt.f32.f16 q%u, d%u\n", dreg, mreg); + } else { + if (mreg & 1) + return False; + mreg >>= 1; + putDRegI64(dreg, unop(Iop_F32toF16x4, getQReg(mreg)), + condT); + DIP("vcvt.f16.f32 d%u, q%u\n", dreg, mreg); + } + return True; + } else { + return False; + } + vassert(0); + return True; + case 3: + if (((B >> 1) & BITS4(1,1,0,1)) == BITS4(1,0,0,0)) { + /* VRECPE */ + IROp op; + F = (theInstr >> 8) & 1; + if (size != 2) + return False; + if (Q) { + op = F ? Iop_Recip32Fx4 : Iop_Recip32x4; + putQReg(dreg, unop(op, getQReg(mreg)), condT); + DIP("vrecpe.%c32 q%u, q%u\n", F ? 'f' : 'u', dreg, mreg); + } else { + op = F ? Iop_Recip32Fx2 : Iop_Recip32x2; + putDRegI64(dreg, unop(op, getDRegI64(mreg)), condT); + DIP("vrecpe.%c32 d%u, d%u\n", F ? 'f' : 'u', dreg, mreg); + } + return True; + } else if (((B >> 1) & BITS4(1,1,0,1)) == BITS4(1,0,0,1)) { + /* VRSQRTE */ + IROp op; + F = (B >> 2) & 1; + if (size != 2) + return False; + if (F) { + /* fp */ + op = Q ? Iop_Rsqrte32Fx4 : Iop_Rsqrte32Fx2; + } else { + /* unsigned int */ + op = Q ? Iop_Rsqrte32x4 : Iop_Rsqrte32x2; + } + if (Q) { + putQReg(dreg, unop(op, getQReg(mreg)), condT); + DIP("vrsqrte.%c32 q%u, q%u\n", F ? 'f' : 'u', dreg, mreg); + } else { + putDRegI64(dreg, unop(op, getDRegI64(mreg)), condT); + DIP("vrsqrte.%c32 d%u, d%u\n", F ? 'f' : 'u', dreg, mreg); + } + return True; + } else if ((B >> 3) == 3) { + /* VCVT (fp<->integer) */ + IROp op; + if (size != 2) + return False; + switch ((B >> 1) & 3) { + case 0: + op = Q ? Iop_I32StoFx4 : Iop_I32StoFx2; + DIP("vcvt.f32.s32 %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + case 1: + op = Q ? Iop_I32UtoFx4 : Iop_I32UtoFx2; + DIP("vcvt.f32.u32 %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + case 2: + op = Q ? Iop_FtoI32Sx4_RZ : Iop_FtoI32Sx2_RZ; + DIP("vcvt.s32.f32 %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + case 3: + op = Q ? Iop_FtoI32Ux4_RZ : Iop_FtoI32Ux2_RZ; + DIP("vcvt.u32.f32 %c%u, %c%u\n", + Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg); + break; + default: + vassert(0); + } + if (Q) { + putQReg(dreg, unop(op, getQReg(mreg)), condT); + } else { + putDRegI64(dreg, unop(op, getDRegI64(mreg)), condT); + } + return True; + } else { + return False; + } + vassert(0); + return True; + default: + vassert(0); + } + return False; +} + +/* A7.4.6 One register and a modified immediate value */ +static +void ppNeonImm(UInt imm, UInt cmode, UInt op) +{ + int i; + switch (cmode) { + case 0: case 1: case 8: case 9: + vex_printf("0x%x", imm); + break; + case 2: case 3: case 10: case 11: + vex_printf("0x%x00", imm); + break; + case 4: case 5: + vex_printf("0x%x0000", imm); + break; + case 6: case 7: + vex_printf("0x%x000000", imm); + break; + case 12: + vex_printf("0x%xff", imm); + break; + case 13: + vex_printf("0x%xffff", imm); + break; + case 14: + if (op) { + vex_printf("0x"); + for (i = 7; i >= 0; i--) + vex_printf("%s", (imm & (1 << i)) ? "ff" : "00"); + } else { + vex_printf("0x%x", imm); + } + break; + case 15: + vex_printf("0x%x", imm); + break; + } +} + +static +const char *ppNeonImmType(UInt cmode, UInt op) +{ + switch (cmode) { + case 0 ... 7: + case 12: case 13: + return "i32"; + case 8 ... 11: + return "i16"; + case 14: + if (op) + return "i64"; + else + return "i8"; + case 15: + if (op) + vassert(0); + else + return "f32"; + default: + vassert(0); + } +} + +static +void DIPimm(UInt imm, UInt cmode, UInt op, + const char *instr, UInt Q, UInt dreg) +{ + if (vex_traceflags & VEX_TRACE_FE) { + vex_printf("%s.%s %c%u, #", instr, + ppNeonImmType(cmode, op), Q ? 'q' : 'd', dreg); + ppNeonImm(imm, cmode, op); + vex_printf("\n"); + } +} + +static +Bool dis_neon_data_1reg_and_imm ( UInt theInstr, IRTemp condT ) +{ + UInt dreg = get_neon_d_regno(theInstr); + ULong imm_raw = ((theInstr >> 17) & 0x80) | ((theInstr >> 12) & 0x70) | + (theInstr & 0xf); + ULong imm_raw_pp = imm_raw; + UInt cmode = (theInstr >> 8) & 0xf; + UInt op_bit = (theInstr >> 5) & 1; + ULong imm = 0; + UInt Q = (theInstr >> 6) & 1; + int i, j; + UInt tmp; + IRExpr *imm_val; + IRExpr *expr; + IRTemp tmp_var; + switch(cmode) { + case 7: case 6: + imm_raw = imm_raw << 8; + /* fallthrough */ + case 5: case 4: + imm_raw = imm_raw << 8; + /* fallthrough */ + case 3: case 2: + imm_raw = imm_raw << 8; + /* fallthrough */ + case 0: case 1: + imm = (imm_raw << 32) | imm_raw; + break; + case 11: case 10: + imm_raw = imm_raw << 8; + /* fallthrough */ + case 9: case 8: + imm_raw = (imm_raw << 16) | imm_raw; + imm = (imm_raw << 32) | imm_raw; + break; + case 13: + imm_raw = (imm_raw << 8) | 0xff; + /* fallthrough */ + case 12: + imm_raw = (imm_raw << 8) | 0xff; + imm = (imm_raw << 32) | imm_raw; + break; + case 14: + if (! op_bit) { + for(i = 0; i < 8; i++) { + imm = (imm << 8) | imm_raw; + } + } else { + for(i = 7; i >= 0; i--) { + tmp = 0; + for(j = 0; j < 8; j++) { + tmp = (tmp << 1) | ((imm_raw >> i) & 1); + } + imm = (imm << 8) | tmp; + } + } + break; + case 15: + imm = (imm_raw & 0x80) << 5; + imm |= ~((imm_raw & 0x40) << 5); + for(i = 1; i <= 4; i++) + imm |= (imm_raw & 0x40) << i; + imm |= (imm_raw & 0x7f); + imm = imm << 19; + imm = (imm << 32) | imm; + break; + default: + return False; + } + if (Q) { + imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm)); + } else { + imm_val = mkU64(imm); + } + if (((op_bit == 0) && + (((cmode & 9) == 0) || ((cmode & 13) == 8) || ((cmode & 12) == 12))) || + ((op_bit == 1) && (cmode == 14))) { + /* VMOV (immediate) */ + if (Q) { + putQReg(dreg, imm_val, condT); + } else { + putDRegI64(dreg, imm_val, condT); + } + DIPimm(imm_raw_pp, cmode, op_bit, "vmov", Q, dreg); + return True; + } + if ((op_bit == 1) && + (((cmode & 9) == 0) || ((cmode & 13) == 8) || ((cmode & 14) == 12))) { + /* VMVN (immediate) */ + if (Q) { + putQReg(dreg, unop(Iop_NotV128, imm_val), condT); + } else { + putDRegI64(dreg, unop(Iop_Not64, imm_val), condT); + } + DIPimm(imm_raw_pp, cmode, op_bit, "vmvn", Q, dreg); + return True; + } + if (Q) { + tmp_var = newTemp(Ity_V128); + assign(tmp_var, getQReg(dreg)); + } else { + tmp_var = newTemp(Ity_I64); + assign(tmp_var, getDRegI64(dreg)); + } + if ((op_bit == 0) && (((cmode & 9) == 1) || ((cmode & 13) == 9))) { + /* VORR (immediate) */ + if (Q) + expr = binop(Iop_OrV128, mkexpr(tmp_var), imm_val); + else + expr = binop(Iop_Or64, mkexpr(tmp_var), imm_val); + DIPimm(imm_raw_pp, cmode, op_bit, "vorr", Q, dreg); + } else if ((op_bit == 1) && (((cmode & 9) == 1) || ((cmode & 13) == 9))) { + /* VBIC (immediate) */ + if (Q) + expr = binop(Iop_AndV128, mkexpr(tmp_var), + unop(Iop_NotV128, imm_val)); + else + expr = binop(Iop_And64, mkexpr(tmp_var), unop(Iop_Not64, imm_val)); + DIPimm(imm_raw_pp, cmode, op_bit, "vbic", Q, dreg); + } else { + return False; + } + if (Q) + putQReg(dreg, expr, condT); + else + putDRegI64(dreg, expr, condT); + return True; +} + +/* A7.4 Advanced SIMD data-processing instructions */ +static +Bool dis_neon_data_processing ( UInt theInstr, IRTemp condT ) +{ + UInt A = (theInstr >> 19) & 0x1F; + UInt B = (theInstr >> 8) & 0xF; + UInt C = (theInstr >> 4) & 0xF; + UInt U = (theInstr >> 24) & 0x1; + + if (! (A & 0x10)) { + return dis_neon_data_3same(theInstr, condT); + } + if (((A & 0x17) == 0x10) && ((C & 0x9) == 0x1)) { + return dis_neon_data_1reg_and_imm(theInstr, condT); + } + if ((C & 1) == 1) { + return dis_neon_data_2reg_and_shift(theInstr, condT); + } + if (((C & 5) == 0) && (((A & 0x14) == 0x10) || ((A & 0x16) == 0x14))) { + return dis_neon_data_3diff(theInstr, condT); + } + if (((C & 5) == 4) && (((A & 0x14) == 0x10) || ((A & 0x16) == 0x14))) { + return dis_neon_data_2reg_and_scalar(theInstr, condT); + } + if ((A & 0x16) == 0x16) { + if ((U == 0) && ((C & 1) == 0)) { + return dis_neon_vext(theInstr, condT); + } + if ((U != 1) || ((C & 1) == 1)) + return False; + if ((B & 8) == 0) { + return dis_neon_data_2reg_misc(theInstr, condT); + } + if ((B & 12) == 8) { + return dis_neon_vtb(theInstr, condT); + } + if ((B == 12) && ((C & 9) == 0)) { + return dis_neon_vdup(theInstr, condT); + } + } + return False; +} + + +/*------------------------------------------------------------*/ +/*--- NEON loads and stores ---*/ +/*------------------------------------------------------------*/ + +/* For NEON memory operations, we use the standard scheme to handle + conditionalisation: generate a jump around the instruction if the + condition is false. That's only necessary in Thumb mode, however, + since in ARM mode NEON instructions are unconditional. */ + +/* A helper function for what follows. It assumes we already went + uncond as per comments at the top of this section. */ +static +void mk_neon_elem_load_to_one_lane( UInt rD, UInt inc, UInt index, + UInt N, UInt size, IRTemp addr ) +{ + UInt i; + switch (size) { + case 0: + putDRegI64(rD, triop(Iop_SetElem8x8, getDRegI64(rD), mkU8(index), + loadLE(Ity_I8, mkexpr(addr))), IRTemp_INVALID); + break; + case 1: + putDRegI64(rD, triop(Iop_SetElem16x4, getDRegI64(rD), mkU8(index), + loadLE(Ity_I16, mkexpr(addr))), IRTemp_INVALID); + break; + case 2: + putDRegI64(rD, triop(Iop_SetElem32x2, getDRegI64(rD), mkU8(index), + loadLE(Ity_I32, mkexpr(addr))), IRTemp_INVALID); + break; + default: + vassert(0); + } + for (i = 1; i <= N; i++) { + switch (size) { + case 0: + putDRegI64(rD + i * inc, + triop(Iop_SetElem8x8, + getDRegI64(rD + i * inc), + mkU8(index), + loadLE(Ity_I8, binop(Iop_Add32, + mkexpr(addr), + mkU32(i * 1)))), + IRTemp_INVALID); + break; + case 1: + putDRegI64(rD + i * inc, + triop(Iop_SetElem16x4, + getDRegI64(rD + i * inc), + mkU8(index), + loadLE(Ity_I16, binop(Iop_Add32, + mkexpr(addr), + mkU32(i * 2)))), + IRTemp_INVALID); + break; + case 2: + putDRegI64(rD + i * inc, + triop(Iop_SetElem32x2, + getDRegI64(rD + i * inc), + mkU8(index), + loadLE(Ity_I32, binop(Iop_Add32, + mkexpr(addr), + mkU32(i * 4)))), + IRTemp_INVALID); + break; + default: + vassert(0); + } + } +} + +/* A(nother) helper function for what follows. It assumes we already + went uncond as per comments at the top of this section. */ +static +void mk_neon_elem_store_from_one_lane( UInt rD, UInt inc, UInt index, + UInt N, UInt size, IRTemp addr ) +{ + UInt i; + switch (size) { + case 0: + storeLE(mkexpr(addr), + binop(Iop_GetElem8x8, getDRegI64(rD), mkU8(index))); + break; + case 1: + storeLE(mkexpr(addr), + binop(Iop_GetElem16x4, getDRegI64(rD), mkU8(index))); + break; + case 2: + storeLE(mkexpr(addr), + binop(Iop_GetElem32x2, getDRegI64(rD), mkU8(index))); + break; + default: + vassert(0); + } + for (i = 1; i <= N; i++) { + switch (size) { + case 0: + storeLE(binop(Iop_Add32, mkexpr(addr), mkU32(i * 1)), + binop(Iop_GetElem8x8, getDRegI64(rD + i * inc), + mkU8(index))); + break; + case 1: + storeLE(binop(Iop_Add32, mkexpr(addr), mkU32(i * 2)), + binop(Iop_GetElem16x4, getDRegI64(rD + i * inc), + mkU8(index))); + break; + case 2: + storeLE(binop(Iop_Add32, mkexpr(addr), mkU32(i * 4)), + binop(Iop_GetElem32x2, getDRegI64(rD + i * inc), + mkU8(index))); + break; + default: + vassert(0); + } + } +} + +/* A7.7 Advanced SIMD element or structure load/store instructions */ +static +Bool dis_neon_elem_or_struct_load ( UInt theInstr, + Bool isT, IRTemp condT ) +{ +# define INSN(_bMax,_bMin) SLICE_UInt(theInstr, (_bMax), (_bMin)) + UInt A = INSN(23,23); + UInt B = INSN(11,8); + UInt L = INSN(21,21); + UInt rD = (INSN(22,22) << 4) | INSN(15,12); + UInt rN = INSN(19,16); + UInt rM = INSN(3,0); + UInt N, size, i, j; + UInt inc; + UInt regs = 1; + + if (isT) { + vassert(condT != IRTemp_INVALID); + } else { + vassert(condT == IRTemp_INVALID); + } + /* So now, if condT is not IRTemp_INVALID, we know we're + dealing with Thumb code. */ + + if (INSN(20,20) != 0) + return False; + + IRTemp initialRn = newTemp(Ity_I32); + assign(initialRn, isT ? getIRegT(rN) : getIRegA(rN)); + + IRTemp initialRm = newTemp(Ity_I32); + assign(initialRm, isT ? getIRegT(rM) : getIRegA(rM)); + + if (A) { + N = B & 3; + if ((B >> 2) < 3) { + /* VSTn / VLDn (n-element structure from/to one lane) */ + + size = B >> 2; + + switch (size) { + case 0: i = INSN(7,5); inc = 1; break; + case 1: i = INSN(7,6); inc = INSN(5,5) ? 2 : 1; break; + case 2: i = INSN(7,7); inc = INSN(6,6) ? 2 : 1; break; + case 3: return False; + default: vassert(0); + } + + IRTemp addr = newTemp(Ity_I32); + assign(addr, mkexpr(initialRn)); + + // go uncond + if (condT != IRTemp_INVALID) + mk_skip_over_T32_if_cond_is_false(condT); + // now uncond + + if (L) + mk_neon_elem_load_to_one_lane(rD, inc, i, N, size, addr); + else + mk_neon_elem_store_from_one_lane(rD, inc, i, N, size, addr); + DIP("v%s%u.%u {", L ? "ld" : "st", N + 1, 8 << size); + for (j = 0; j <= N; j++) { + if (j) + DIP(", "); + DIP("d%u[%u]", rD + j * inc, i); + } + DIP("}, [r%u]", rN); + if (rM != 13 && rM != 15) { + DIP(", r%u\n", rM); + } else { + DIP("%s\n", (rM != 15) ? "!" : ""); + } + } else { + /* VLDn (single element to all lanes) */ + UInt r; + if (L == 0) + return False; + + inc = INSN(5,5) + 1; + size = INSN(7,6); + + /* size == 3 and size == 2 cases differ in alignment constraints */ + if (size == 3 && N == 3 && INSN(4,4) == 1) + size = 2; + + if (size == 0 && N == 0 && INSN(4,4) == 1) + return False; + if (N == 2 && INSN(4,4) == 1) + return False; + if (size == 3) + return False; + + // go uncond + if (condT != IRTemp_INVALID) + mk_skip_over_T32_if_cond_is_false(condT); + // now uncond + + IRTemp addr = newTemp(Ity_I32); + assign(addr, mkexpr(initialRn)); + + if (N == 0 && INSN(5,5)) + regs = 2; + + for (r = 0; r < regs; r++) { + switch (size) { + case 0: + putDRegI64(rD + r, unop(Iop_Dup8x8, + loadLE(Ity_I8, mkexpr(addr))), + IRTemp_INVALID); + break; + case 1: + putDRegI64(rD + r, unop(Iop_Dup16x4, + loadLE(Ity_I16, mkexpr(addr))), + IRTemp_INVALID); + break; + case 2: + putDRegI64(rD + r, unop(Iop_Dup32x2, + loadLE(Ity_I32, mkexpr(addr))), + IRTemp_INVALID); + break; + default: + vassert(0); + } + for (i = 1; i <= N; i++) { + switch (size) { + case 0: + putDRegI64(rD + r + i * inc, + unop(Iop_Dup8x8, + loadLE(Ity_I8, binop(Iop_Add32, + mkexpr(addr), + mkU32(i * 1)))), + IRTemp_INVALID); + break; + case 1: + putDRegI64(rD + r + i * inc, + unop(Iop_Dup16x4, + loadLE(Ity_I16, binop(Iop_Add32, + mkexpr(addr), + mkU32(i * 2)))), + IRTemp_INVALID); + break; + case 2: + putDRegI64(rD + r + i * inc, + unop(Iop_Dup32x2, + loadLE(Ity_I32, binop(Iop_Add32, + mkexpr(addr), + mkU32(i * 4)))), + IRTemp_INVALID); + break; + default: + vassert(0); + } + } + } + DIP("vld%u.%u {", N + 1, 8 << size); + for (r = 0; r < regs; r++) { + for (i = 0; i <= N; i++) { + if (i || r) + DIP(", "); + DIP("d%u[]", rD + r + i * inc); + } + } + DIP("}, [r%u]", rN); + if (rM != 13 && rM != 15) { + DIP(", r%u\n", rM); + } else { + DIP("%s\n", (rM != 15) ? "!" : ""); + } + } + /* Writeback. We're uncond here, so no condT-ing. */ + if (rM != 15) { + if (rM == 13) { + IRExpr* e = binop(Iop_Add32, + mkexpr(initialRn), + mkU32((1 << size) * (N + 1))); + if (isT) + putIRegT(rN, e, IRTemp_INVALID); + else + putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring); + } else { + IRExpr* e = binop(Iop_Add32, + mkexpr(initialRn), + mkexpr(initialRm)); + if (isT) + putIRegT(rN, e, IRTemp_INVALID); + else + putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring); + } + } + return True; + } else { + IRTemp tmp; + UInt r, elems; + /* VSTn / VLDn (multiple n-element structures) */ + if (B == BITS4(0,0,1,0) || B == BITS4(0,1,1,0) + || B == BITS4(0,1,1,1) || B == BITS4(1,0,1,0)) { + N = 0; + } else if (B == BITS4(0,0,1,1) || B == BITS4(1,0,0,0) + || B == BITS4(1,0,0,1)) { + N = 1; + } else if (B == BITS4(0,1,0,0) || B == BITS4(0,1,0,1)) { + N = 2; + } else if (B == BITS4(0,0,0,0) || B == BITS4(0,0,0,1)) { + N = 3; + } else { + return False; + } + inc = (B & 1) + 1; + if (N == 1 && B == BITS4(0,0,1,1)) { + regs = 2; + } else if (N == 0) { + if (B == BITS4(1,0,1,0)) { + regs = 2; + } else if (B == BITS4(0,1,1,0)) { + regs = 3; + } else if (B == BITS4(0,0,1,0)) { + regs = 4; + } + } + + size = INSN(7,6); + if (N == 0 && size == 3) + size = 2; + if (size == 3) + return False; + + elems = 8 / (1 << size); + + // go uncond + if (condT != IRTemp_INVALID) + mk_skip_over_T32_if_cond_is_false(condT); + // now uncond + + IRTemp addr = newTemp(Ity_I32); + assign(addr, mkexpr(initialRn)); + + for (r = 0; r < regs; r++) { + for (i = 0; i < elems; i++) { + if (L) + mk_neon_elem_load_to_one_lane(rD + r, inc, i, N, size, addr); + else + mk_neon_elem_store_from_one_lane(rD + r, inc, i, N, size, addr); + tmp = newTemp(Ity_I32); + assign(tmp, binop(Iop_Add32, mkexpr(addr), + mkU32((1 << size) * (N + 1)))); + addr = tmp; + } + } + /* Writeback */ + if (rM != 15) { + if (rM == 13) { + IRExpr* e = binop(Iop_Add32, + mkexpr(initialRn), + mkU32(8 * (N + 1) * regs)); + if (isT) + putIRegT(rN, e, IRTemp_INVALID); + else + putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring); + } else { + IRExpr* e = binop(Iop_Add32, + mkexpr(initialRn), + mkexpr(initialRm)); + if (isT) + putIRegT(rN, e, IRTemp_INVALID); + else + putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring); + } + } + DIP("v%s%u.%u {", L ? "ld" : "st", N + 1, 8 << INSN(7,6)); + if ((inc == 1 && regs * (N + 1) > 1) + || (inc == 2 && regs > 1 && N > 0)) { + DIP("d%u-d%u", rD, rD + regs * (N + 1) - 1); + } else { + for (r = 0; r < regs; r++) { + for (i = 0; i <= N; i++) { + if (i || r) + DIP(", "); + DIP("d%u", rD + r + i * inc); + } + } + } + DIP("}, [r%u]", rN); + if (rM != 13 && rM != 15) { + DIP(", r%u\n", rM); + } else { + DIP("%s\n", (rM != 15) ? "!" : ""); + } + return True; + } +# undef INSN +} + + +/*------------------------------------------------------------*/ +/*--- NEON, top level control ---*/ +/*------------------------------------------------------------*/ + +/* Both ARM and Thumb */ + +/* Translate a NEON instruction. If successful, returns + True and *dres may or may not be updated. If failure, returns + False and doesn't change *dres nor create any IR. + + The Thumb and ARM encodings are similar for the 24 bottom bits, but + the top 8 bits are slightly different. In both cases, the caller + must pass the entire 32 bits. Callers may pass any instruction; + this ignores non-NEON ones. + + Caller must supply an IRTemp 'condT' holding the gating condition, + or IRTemp_INVALID indicating the insn is always executed. In ARM + code, this must always be IRTemp_INVALID because NEON insns are + unconditional for ARM. + + Finally, the caller must indicate whether this occurs in ARM or in + Thumb code. +*/ +static Bool decode_NEON_instruction ( + /*MOD*/DisResult* dres, + UInt insn32, + IRTemp condT, + Bool isT + ) +{ +# define INSN(_bMax,_bMin) SLICE_UInt(insn32, (_bMax), (_bMin)) + + /* There are two kinds of instruction to deal with: load/store and + data processing. In each case, in ARM mode we merely identify + the kind, and pass it on to the relevant sub-handler. In Thumb + mode we identify the kind, swizzle the bits around to make it + have the same encoding as in ARM, and hand it on to the + sub-handler. + */ + + /* In ARM mode, NEON instructions can't be conditional. */ + if (!isT) + vassert(condT == IRTemp_INVALID); + + /* Data processing: + Thumb: 111U 1111 AAAA Axxx xxxx BBBB CCCC xxxx + ARM: 1111 001U AAAA Axxx xxxx BBBB CCCC xxxx + */ + if (!isT && INSN(31,25) == BITS7(1,1,1,1,0,0,1)) { + // ARM, DP + return dis_neon_data_processing(INSN(31,0), condT); + } + if (isT && INSN(31,29) == BITS3(1,1,1) + && INSN(27,24) == BITS4(1,1,1,1)) { + // Thumb, DP + UInt reformatted = INSN(23,0); + reformatted |= (INSN(28,28) << 24); // U bit + reformatted |= (BITS7(1,1,1,1,0,0,1) << 25); + return dis_neon_data_processing(reformatted, condT); + } + + /* Load/store: + Thumb: 1111 1001 AxL0 xxxx xxxx BBBB xxxx xxxx + ARM: 1111 0100 AxL0 xxxx xxxx BBBB xxxx xxxx + */ + if (!isT && INSN(31,24) == BITS8(1,1,1,1,0,1,0,0)) { + // ARM, memory + return dis_neon_elem_or_struct_load(INSN(31,0), isT, condT); + } + if (isT && INSN(31,24) == BITS8(1,1,1,1,1,0,0,1)) { + UInt reformatted = INSN(23,0); + reformatted |= (BITS8(1,1,1,1,0,1,0,0) << 24); + return dis_neon_elem_or_struct_load(reformatted, isT, condT); + } + + /* Doesn't match. */ + return False; + +# undef INSN +} + + +/*------------------------------------------------------------*/ +/*--- V6 MEDIA instructions ---*/ +/*------------------------------------------------------------*/ + +/* Both ARM and Thumb */ + +/* Translate a V6 media instruction. If successful, returns + True and *dres may or may not be updated. If failure, returns + False and doesn't change *dres nor create any IR. + + The Thumb and ARM encodings are completely different. In Thumb + mode, the caller must pass the entire 32 bits. In ARM mode it must + pass the lower 28 bits. Apart from that, callers may pass any + instruction; this function ignores anything it doesn't recognise. + + Caller must supply an IRTemp 'condT' holding the gating condition, + or IRTemp_INVALID indicating the insn is always executed. + + Caller must also supply an ARMCondcode 'cond'. This is only used + for debug printing, no other purpose. For ARM, this is simply the + top 4 bits of the original instruction. For Thumb, the condition + is not (really) known until run time, and so ARMCondAL should be + passed, only so that printing of these instructions does not show + any condition. + + Finally, the caller must indicate whether this occurs in ARM or in + Thumb code. +*/ +static Bool decode_V6MEDIA_instruction ( + /*MOD*/DisResult* dres, + UInt insnv6m, + IRTemp condT, + ARMCondcode conq, + Bool isT + ) +{ +# define INSNA(_bMax,_bMin) SLICE_UInt(insnv6m, (_bMax), (_bMin)) +# define INSNT0(_bMax,_bMin) SLICE_UInt( ((insnv6m >> 16) & 0xFFFF), \ + (_bMax), (_bMin) ) +# define INSNT1(_bMax,_bMin) SLICE_UInt( ((insnv6m >> 0) & 0xFFFF), \ + (_bMax), (_bMin) ) + HChar dis_buf[128]; + dis_buf[0] = 0; + + if (isT) { + vassert(conq == ARMCondAL); + } else { + vassert(INSNA(31,28) == BITS4(0,0,0,0)); // caller's obligation + vassert(conq >= ARMCondEQ && conq <= ARMCondAL); + } + + /* ----------- smulbb, smulbt, smultb, smultt ----------- */ + { + UInt regD = 99, regM = 99, regN = 99, bitM = 0, bitN = 0; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFB1 && INSNT1(15,12) == BITS4(1,1,1,1) + && INSNT1(7,6) == BITS2(0,0)) { + regD = INSNT1(11,8); + regM = INSNT1(3,0); + regN = INSNT0(3,0); + bitM = INSNT1(4,4); + bitN = INSNT1(5,5); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (BITS8(0,0,0,1,0,1,1,0) == INSNA(27,20) && + BITS4(0,0,0,0) == INSNA(15,12) && + BITS4(1,0,0,0) == (INSNA(7,4) & BITS4(1,0,0,1)) ) { + regD = INSNA(19,16); + regM = INSNA(11,8); + regN = INSNA(3,0); + bitM = INSNA(6,6); + bitN = INSNA(5,5); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp srcN = newTemp(Ity_I32); + IRTemp srcM = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + + assign( srcN, binop(Iop_Sar32, + binop(Iop_Shl32, + isT ? getIRegT(regN) : getIRegA(regN), + mkU8(bitN ? 0 : 16)), mkU8(16)) ); + assign( srcM, binop(Iop_Sar32, + binop(Iop_Shl32, + isT ? getIRegT(regM) : getIRegA(regM), + mkU8(bitM ? 0 : 16)), mkU8(16)) ); + assign( res, binop(Iop_Mul32, mkexpr(srcN), mkexpr(srcM)) ); + + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + DIP( "smul%c%c%s r%u, r%u, r%u\n", bitN ? 't' : 'b', bitM ? 't' : 'b', + nCC(conq), regD, regN, regM ); + return True; + } + /* fall through */ + } + + /* ------------ smulwb ,, ------------- */ + /* ------------ smulwt ,, ------------- */ + { + UInt regD = 99, regN = 99, regM = 99, bitM = 0; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFB3 && INSNT1(15,12) == BITS4(1,1,1,1) + && INSNT1(7,5) == BITS3(0,0,0)) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + bitM = INSNT1(4,4); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,0,0,1,0,0,1,0) && + INSNA(15,12) == BITS4(0,0,0,0) && + (INSNA(7,4) & BITS4(1,0,1,1)) == BITS4(1,0,1,0)) { + regD = INSNA(19,16); + regN = INSNA(3,0); + regM = INSNA(11,8); + bitM = INSNA(6,6); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_prod = newTemp(Ity_I64); + + assign( irt_prod, + binop(Iop_MullS32, + isT ? getIRegT(regN) : getIRegA(regN), + binop(Iop_Sar32, + binop(Iop_Shl32, + isT ? getIRegT(regM) : getIRegA(regM), + mkU8(bitM ? 0 : 16)), + mkU8(16))) ); + + IRExpr* ire_result = binop(Iop_Or32, + binop( Iop_Shl32, + unop(Iop_64HIto32, mkexpr(irt_prod)), + mkU8(16) ), + binop( Iop_Shr32, + unop(Iop_64to32, mkexpr(irt_prod)), + mkU8(16) ) ); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + DIP("smulw%c%s r%u, r%u, r%u\n", + bitM ? 't' : 'b', nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------ pkhbt Rd, Rn, Rm {,LSL #imm} ------------- */ + /* ------------ pkhtb Rd, Rn, Rm {,ASR #imm} ------------- */ + { + UInt regD = 99, regN = 99, regM = 99, imm5 = 99, shift_type = 99; + Bool tbform = False; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xEAC + && INSNT1(15,15) == 0 && INSNT1(4,4) == 0) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + imm5 = (INSNT1(14,12) << 2) | INSNT1(7,6); + shift_type = (INSNT1(5,5) << 1) | 0; + tbform = (INSNT1(5,5) == 0) ? False : True; + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,1,0,0,0) && + INSNA(5,4) == BITS2(0,1) && + (INSNA(6,6) == 0 || INSNA(6,6) == 1) ) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + imm5 = INSNA(11,7); + shift_type = (INSNA(6,6) << 1) | 0; + tbform = (INSNA(6,6) == 0) ? False : True; + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regM = newTemp(Ity_I32); + IRTemp irt_regM_shift = newTemp(Ity_I32); + assign( irt_regM, isT ? getIRegT(regM) : getIRegA(regM) ); + compute_result_and_C_after_shift_by_imm5( + dis_buf, &irt_regM_shift, NULL, irt_regM, shift_type, imm5, regM ); + + UInt mask = (tbform == True) ? 0x0000FFFF : 0xFFFF0000; + IRExpr* ire_result + = binop( Iop_Or32, + binop(Iop_And32, mkexpr(irt_regM_shift), mkU32(mask)), + binop(Iop_And32, isT ? getIRegT(regN) : getIRegA(regN), + unop(Iop_Not32, mkU32(mask))) ); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + DIP( "pkh%s%s r%u, r%u, r%u %s\n", tbform ? "tb" : "bt", + nCC(conq), regD, regN, regM, dis_buf ); + + return True; + } + /* fall through */ + } + + /* ---------- usat ,#,{,} ----------- */ + { + UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,6) == BITS10(1,1,1,1,0,0,1,1,1,0) + && INSNT0(4,4) == 0 + && INSNT1(15,15) == 0 && INSNT1(5,5) == 0) { + regD = INSNT1(11,8); + regN = INSNT0(3,0); + shift_type = (INSNT0(5,5) << 1) | 0; + imm5 = (INSNT1(14,12) << 2) | INSNT1(7,6); + sat_imm = INSNT1(4,0); + if (!isBadRegT(regD) && !isBadRegT(regN)) + gate = True; + if (shift_type == BITS2(1,0) && imm5 == 0) + gate = False; + } + } else { + if (INSNA(27,21) == BITS7(0,1,1,0,1,1,1) && + INSNA(5,4) == BITS2(0,1)) { + regD = INSNA(15,12); + regN = INSNA(3,0); + shift_type = (INSNA(6,6) << 1) | 0; + imm5 = INSNA(11,7); + sat_imm = INSNA(20,16); + if (regD != 15 && regN != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + IRTemp irt_regN_shift = newTemp(Ity_I32); + IRTemp irt_sat_Q = newTemp(Ity_I32); + IRTemp irt_result = newTemp(Ity_I32); + + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + compute_result_and_C_after_shift_by_imm5( + dis_buf, &irt_regN_shift, NULL, + irt_regN, shift_type, imm5, regN ); + + armUnsignedSatQ( &irt_result, &irt_sat_Q, irt_regN_shift, sat_imm ); + or_into_QFLAG32( mkexpr(irt_sat_Q), condT ); + + if (isT) + putIRegT( regD, mkexpr(irt_result), condT ); + else + putIRegA( regD, mkexpr(irt_result), condT, Ijk_Boring ); + + DIP("usat%s r%u, #0x%04x, %s\n", + nCC(conq), regD, imm5, dis_buf); + return True; + } + /* fall through */ + } + + /* ----------- ssat ,#,{,} ----------- */ + { + UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,6) == BITS10(1,1,1,1,0,0,1,1,0,0) + && INSNT0(4,4) == 0 + && INSNT1(15,15) == 0 && INSNT1(5,5) == 0) { + regD = INSNT1(11,8); + regN = INSNT0(3,0); + shift_type = (INSNT0(5,5) << 1) | 0; + imm5 = (INSNT1(14,12) << 2) | INSNT1(7,6); + sat_imm = INSNT1(4,0) + 1; + if (!isBadRegT(regD) && !isBadRegT(regN)) + gate = True; + if (shift_type == BITS2(1,0) && imm5 == 0) + gate = False; + } + } else { + if (INSNA(27,21) == BITS7(0,1,1,0,1,0,1) && + INSNA(5,4) == BITS2(0,1)) { + regD = INSNA(15,12); + regN = INSNA(3,0); + shift_type = (INSNA(6,6) << 1) | 0; + imm5 = INSNA(11,7); + sat_imm = INSNA(20,16) + 1; + if (regD != 15 && regN != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + IRTemp irt_regN_shift = newTemp(Ity_I32); + IRTemp irt_sat_Q = newTemp(Ity_I32); + IRTemp irt_result = newTemp(Ity_I32); + + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + compute_result_and_C_after_shift_by_imm5( + dis_buf, &irt_regN_shift, NULL, + irt_regN, shift_type, imm5, regN ); + + armSignedSatQ( irt_regN_shift, sat_imm, &irt_result, &irt_sat_Q ); + or_into_QFLAG32( mkexpr(irt_sat_Q), condT ); + + if (isT) + putIRegT( regD, mkexpr(irt_result), condT ); + else + putIRegA( regD, mkexpr(irt_result), condT, Ijk_Boring ); + + DIP( "ssat%s r%u, #0x%04x, %s\n", + nCC(conq), regD, imm5, dis_buf); + return True; + } + /* fall through */ + } + + /* -------------- usat16 ,#, --------------- */ + { + UInt regD = 99, regN = 99, sat_imm = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xF3A && (INSNT1(15,0) & 0xF0F0) == 0x0000) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + sat_imm = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,1,1,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,0,1,1)) { + regD = INSNA(15,12); + regN = INSNA(3,0); + sat_imm = INSNA(19,16); + if (regD != 15 && regN != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + IRTemp irt_regN_lo = newTemp(Ity_I32); + IRTemp irt_regN_hi = newTemp(Ity_I32); + IRTemp irt_Q_lo = newTemp(Ity_I32); + IRTemp irt_Q_hi = newTemp(Ity_I32); + IRTemp irt_res_lo = newTemp(Ity_I32); + IRTemp irt_res_hi = newTemp(Ity_I32); + + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( irt_regN_lo, binop( Iop_Sar32, + binop(Iop_Shl32, mkexpr(irt_regN), mkU8(16)), + mkU8(16)) ); + assign( irt_regN_hi, binop(Iop_Sar32, mkexpr(irt_regN), mkU8(16)) ); + + armUnsignedSatQ( &irt_res_lo, &irt_Q_lo, irt_regN_lo, sat_imm ); + or_into_QFLAG32( mkexpr(irt_Q_lo), condT ); + + armUnsignedSatQ( &irt_res_hi, &irt_Q_hi, irt_regN_hi, sat_imm ); + or_into_QFLAG32( mkexpr(irt_Q_hi), condT ); + + IRExpr* ire_result = binop( Iop_Or32, + binop(Iop_Shl32, mkexpr(irt_res_hi), mkU8(16)), + mkexpr(irt_res_lo) ); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + DIP( "usat16%s r%u, #0x%04x, r%u\n", nCC(conq), regD, sat_imm, regN ); + return True; + } + /* fall through */ + } + + /* -------------- uadd16 ,, -------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA9 && (INSNT1(15,0) & 0xF0F0) == 0xF040) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,1,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,0,0,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp reso = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res, binop(Iop_Add16x2, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + assign(reso, binop(Iop_HAdd16Ux2, mkexpr(rNt), mkexpr(rMt))); + set_GE_32_10_from_bits_31_15(reso, condT); + + DIP("uadd16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* -------------- sadd16 ,, -------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA9 && (INSNT1(15,0) & 0xF0F0) == 0xF000) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,0,0,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp reso = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res, binop(Iop_Add16x2, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + assign(reso, unop(Iop_Not32, + binop(Iop_HAdd16Sx2, mkexpr(rNt), mkexpr(rMt)))); + set_GE_32_10_from_bits_31_15(reso, condT); + + DIP("sadd16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ---------------- usub16 ,, ---------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF040) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,1,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,1,1,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp reso = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res, binop(Iop_Sub16x2, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + assign(reso, unop(Iop_Not32, + binop(Iop_HSub16Ux2, mkexpr(rNt), mkexpr(rMt)))); + set_GE_32_10_from_bits_31_15(reso, condT); + + DIP("usub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* -------------- ssub16 ,, -------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF000) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,1,1,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp reso = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res, binop(Iop_Sub16x2, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + assign(reso, unop(Iop_Not32, + binop(Iop_HSub16Sx2, mkexpr(rNt), mkexpr(rMt)))); + set_GE_32_10_from_bits_31_15(reso, condT); + + DIP("ssub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ----------------- uadd8 ,, ---------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF040) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,1,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + (INSNA(7,4) == BITS4(1,0,0,1))) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp reso = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res, binop(Iop_Add8x4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + assign(reso, binop(Iop_HAdd8Ux4, mkexpr(rNt), mkexpr(rMt))); + set_GE_3_2_1_0_from_bits_31_23_15_7(reso, condT); + + DIP("uadd8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------- sadd8 ,, ------------------ */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF000) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + (INSNA(7,4) == BITS4(1,0,0,1))) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp reso = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res, binop(Iop_Add8x4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + assign(reso, unop(Iop_Not32, + binop(Iop_HAdd8Sx4, mkexpr(rNt), mkexpr(rMt)))); + set_GE_3_2_1_0_from_bits_31_23_15_7(reso, condT); + + DIP("sadd8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------- usub8 ,, ------------------ */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAC && (INSNT1(15,0) & 0xF0F0) == 0xF040) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,1,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + (INSNA(7,4) == BITS4(1,1,1,1))) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp reso = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res, binop(Iop_Sub8x4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + assign(reso, unop(Iop_Not32, + binop(Iop_HSub8Ux4, mkexpr(rNt), mkexpr(rMt)))); + set_GE_3_2_1_0_from_bits_31_23_15_7(reso, condT); + + DIP("usub8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------- ssub8 ,, ------------------ */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAC && (INSNT1(15,0) & 0xF0F0) == 0xF000) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(1,1,1,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp reso = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res, binop(Iop_Sub8x4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res), condT ); + else + putIRegA( regD, mkexpr(res), condT, Ijk_Boring ); + + assign(reso, unop(Iop_Not32, + binop(Iop_HSub8Sx4, mkexpr(rNt), mkexpr(rMt)))); + set_GE_3_2_1_0_from_bits_31_23_15_7(reso, condT); + + DIP("ssub8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------ qadd8 ,, ------------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF010) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(1,0,0,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res_q = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res_q, binop(Iop_QAdd8Sx4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res_q), condT ); + else + putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring ); + + DIP("qadd8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------ qsub8 ,, ------------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAC && (INSNT1(15,0) & 0xF0F0) == 0xF010) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(1,1,1,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res_q = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res_q, binop(Iop_QSub8Sx4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res_q), condT ); + else + putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring ); + + DIP("qsub8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------ uqadd8 ,, ------------------ */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF050) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + (INSNA(7,4) == BITS4(1,0,0,1))) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res_q = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res_q, binop(Iop_QAdd8Ux4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res_q), condT ); + else + putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring ); + + DIP("uqadd8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------ uqsub8 ,, ------------------ */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAC && (INSNT1(15,0) & 0xF0F0) == 0xF050) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + (INSNA(7,4) == BITS4(1,1,1,1))) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res_q = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res_q, binop(Iop_QSub8Ux4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res_q), condT ); + else + putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring ); + + DIP("uqsub8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ----------------- uhadd8 ,, ------------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF060) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(1,0,0,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res_q = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res_q, binop(Iop_HAdd8Ux4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res_q), condT ); + else + putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring ); + + DIP("uhadd8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ----------------- shadd8 ,, ------------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF020) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(1,0,0,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res_q = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res_q, binop(Iop_HAdd8Sx4, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res_q), condT ); + else + putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring ); + + DIP("shadd8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------ qadd16 ,, ------------------ */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA9 && (INSNT1(15,0) & 0xF0F0) == 0xF010) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,0,0,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res_q = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res_q, binop(Iop_QAdd16Sx2, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res_q), condT ); + else + putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring ); + + DIP("qadd16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + /* ------------------ qsub16 ,, ------------------ */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF010) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,1,1,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res_q = newTemp(Ity_I32); + + assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign(res_q, binop(Iop_QSub16Sx2, mkexpr(rNt), mkexpr(rMt))); + if (isT) + putIRegT( regD, mkexpr(res_q), condT ); + else + putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring ); + + DIP("qsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM); + return True; + } + /* fall through */ + } + + ///////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////// + + /* ------------------- qsax ,, ------------------- */ + /* note: the hardware seems to construct the result differently + from wot the manual says. */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAE && (INSNT1(15,0) & 0xF0F0) == 0xF010) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,1,0,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + IRTemp irt_regM = newTemp(Ity_I32); + IRTemp irt_sum = newTemp(Ity_I32); + IRTemp irt_diff = newTemp(Ity_I32); + IRTemp irt_sum_res = newTemp(Ity_I32); + IRTemp irt_diff_res = newTemp(Ity_I32); + + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( irt_regM, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign( irt_diff, + binop( Iop_Sub32, + binop( Iop_Sar32, mkexpr(irt_regN), mkU8(16) ), + binop( Iop_Sar32, + binop(Iop_Shl32, mkexpr(irt_regM), mkU8(16)), + mkU8(16) ) ) ); + armSignedSatQ( irt_diff, 0x10, &irt_diff_res, NULL); + + assign( irt_sum, + binop( Iop_Add32, + binop( Iop_Sar32, + binop( Iop_Shl32, mkexpr(irt_regN), mkU8(16) ), + mkU8(16) ), + binop( Iop_Sar32, mkexpr(irt_regM), mkU8(16) )) ); + armSignedSatQ( irt_sum, 0x10, &irt_sum_res, NULL ); + + IRExpr* ire_result = binop( Iop_Or32, + binop( Iop_Shl32, mkexpr(irt_diff_res), + mkU8(16) ), + binop( Iop_And32, mkexpr(irt_sum_res), + mkU32(0xFFFF)) ); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + DIP( "qsax%s r%u, r%u, r%u\n", nCC(conq), regD, regN, regM ); + return True; + } + /* fall through */ + } + + /* ------------------- qasx ,, ------------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAA && (INSNT1(15,0) & 0xF0F0) == 0xF010) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,0,1,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + IRTemp irt_regM = newTemp(Ity_I32); + IRTemp irt_sum = newTemp(Ity_I32); + IRTemp irt_diff = newTemp(Ity_I32); + IRTemp irt_res_sum = newTemp(Ity_I32); + IRTemp irt_res_diff = newTemp(Ity_I32); + + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( irt_regM, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign( irt_diff, + binop( Iop_Sub32, + binop( Iop_Sar32, + binop( Iop_Shl32, mkexpr(irt_regN), mkU8(16) ), + mkU8(16) ), + binop( Iop_Sar32, mkexpr(irt_regM), mkU8(16) ) ) ); + armSignedSatQ( irt_diff, 0x10, &irt_res_diff, NULL ); + + assign( irt_sum, + binop( Iop_Add32, + binop( Iop_Sar32, mkexpr(irt_regN), mkU8(16) ), + binop( Iop_Sar32, + binop( Iop_Shl32, mkexpr(irt_regM), mkU8(16) ), + mkU8(16) ) ) ); + armSignedSatQ( irt_sum, 0x10, &irt_res_sum, NULL ); + + IRExpr* ire_result + = binop( Iop_Or32, + binop( Iop_Shl32, mkexpr(irt_res_sum), mkU8(16) ), + binop( Iop_And32, mkexpr(irt_res_diff), mkU32(0xFFFF) ) ); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + DIP( "qasx%s r%u, r%u, r%u\n", nCC(conq), regD, regN, regM ); + return True; + } + /* fall through */ + } + + /* ------------------- sasx ,, ------------------- */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAA && (INSNT1(15,0) & 0xF0F0) == 0xF000) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,0,0,0,1) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(0,0,1,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + IRTemp irt_regM = newTemp(Ity_I32); + IRTemp irt_sum = newTemp(Ity_I32); + IRTemp irt_diff = newTemp(Ity_I32); + + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( irt_regM, isT ? getIRegT(regM) : getIRegA(regM) ); + + assign( irt_diff, + binop( Iop_Sub32, + binop( Iop_Sar32, + binop( Iop_Shl32, mkexpr(irt_regN), mkU8(16) ), + mkU8(16) ), + binop( Iop_Sar32, mkexpr(irt_regM), mkU8(16) ) ) ); + + assign( irt_sum, + binop( Iop_Add32, + binop( Iop_Sar32, mkexpr(irt_regN), mkU8(16) ), + binop( Iop_Sar32, + binop( Iop_Shl32, mkexpr(irt_regM), mkU8(16) ), + mkU8(16) ) ) ); + + IRExpr* ire_result + = binop( Iop_Or32, + binop( Iop_Shl32, mkexpr(irt_sum), mkU8(16) ), + binop( Iop_And32, mkexpr(irt_diff), mkU32(0xFFFF) ) ); + + IRTemp ge10 = newTemp(Ity_I32); + assign(ge10, unop(Iop_Not32, mkexpr(irt_diff))); + put_GEFLAG32( 0, 31, mkexpr(ge10), condT ); + put_GEFLAG32( 1, 31, mkexpr(ge10), condT ); + + IRTemp ge32 = newTemp(Ity_I32); + assign(ge32, unop(Iop_Not32, mkexpr(irt_sum))); + put_GEFLAG32( 2, 31, mkexpr(ge32), condT ); + put_GEFLAG32( 3, 31, mkexpr(ge32), condT ); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + DIP( "sasx%s r%u, r%u, r%u\n", nCC(conq), regD, regN, regM ); + return True; + } + /* fall through */ + } + + /* --------------- smuad, smuadx,, --------------- */ + /* --------------- smsad, smsadx,, --------------- */ + { + UInt regD = 99, regN = 99, regM = 99, bitM = 99; + Bool gate = False, isAD = False; + + if (isT) { + if ((INSNT0(15,4) == 0xFB2 || INSNT0(15,4) == 0xFB4) + && (INSNT1(15,0) & 0xF0E0) == 0xF000) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + bitM = INSNT1(4,4); + isAD = INSNT0(15,4) == 0xFB2; + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,1,0,0,0,0) && + INSNA(15,12) == BITS4(1,1,1,1) && + (INSNA(7,4) & BITS4(1,0,0,1)) == BITS4(0,0,0,1) ) { + regD = INSNA(19,16); + regN = INSNA(3,0); + regM = INSNA(11,8); + bitM = INSNA(5,5); + isAD = INSNA(6,6) == 0; + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + IRTemp irt_regM = newTemp(Ity_I32); + IRTemp irt_prod_lo = newTemp(Ity_I32); + IRTemp irt_prod_hi = newTemp(Ity_I32); + IRTemp tmpM = newTemp(Ity_I32); + + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + + assign( tmpM, isT ? getIRegT(regM) : getIRegA(regM) ); + assign( irt_regM, genROR32(tmpM, (bitM & 1) ? 16 : 0) ); + + assign( irt_prod_lo, + binop( Iop_Mul32, + binop( Iop_Sar32, + binop(Iop_Shl32, mkexpr(irt_regN), mkU8(16)), + mkU8(16) ), + binop( Iop_Sar32, + binop(Iop_Shl32, mkexpr(irt_regM), mkU8(16)), + mkU8(16) ) ) ); + assign( irt_prod_hi, binop(Iop_Mul32, + binop(Iop_Sar32, mkexpr(irt_regN), mkU8(16)), + binop(Iop_Sar32, mkexpr(irt_regM), mkU8(16))) ); + IRExpr* ire_result + = binop( isAD ? Iop_Add32 : Iop_Sub32, + mkexpr(irt_prod_lo), mkexpr(irt_prod_hi) ); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + if (isAD) { + or_into_QFLAG32( + signed_overflow_after_Add32( ire_result, + irt_prod_lo, irt_prod_hi ), + condT + ); + } + + DIP("smu%cd%s%s r%u, r%u, r%u\n", + isAD ? 'a' : 's', + bitM ? "x" : "", nCC(conq), regD, regN, regM); + return True; + } + /* fall through */ + } + + /* --------------- smlad{X} ,,, -------------- */ + /* --------------- smlsd{X} ,,, -------------- */ + { + UInt regD = 99, regN = 99, regM = 99, regA = 99, bitM = 99; + Bool gate = False, isAD = False; + + if (isT) { + if ((INSNT0(15,4) == 0xFB2 || INSNT0(15,4) == 0xFB4) + && INSNT1(7,5) == BITS3(0,0,0)) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + regA = INSNT1(15,12); + bitM = INSNT1(4,4); + isAD = INSNT0(15,4) == 0xFB2; + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM) + && !isBadRegT(regA)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,1,0,0,0,0) && + (INSNA(7,4) & BITS4(1,0,0,1)) == BITS4(0,0,0,1)) { + regD = INSNA(19,16); + regA = INSNA(15,12); + regN = INSNA(3,0); + regM = INSNA(11,8); + bitM = INSNA(5,5); + isAD = INSNA(6,6) == 0; + if (regD != 15 && regN != 15 && regM != 15 && regA != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + IRTemp irt_regM = newTemp(Ity_I32); + IRTemp irt_regA = newTemp(Ity_I32); + IRTemp irt_prod_lo = newTemp(Ity_I32); + IRTemp irt_prod_hi = newTemp(Ity_I32); + IRTemp irt_sum = newTemp(Ity_I32); + IRTemp tmpM = newTemp(Ity_I32); + + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + assign( irt_regA, isT ? getIRegT(regA) : getIRegA(regA) ); + + assign( tmpM, isT ? getIRegT(regM) : getIRegA(regM) ); + assign( irt_regM, genROR32(tmpM, (bitM & 1) ? 16 : 0) ); + + assign( irt_prod_lo, + binop(Iop_Mul32, + binop(Iop_Sar32, + binop( Iop_Shl32, mkexpr(irt_regN), mkU8(16) ), + mkU8(16)), + binop(Iop_Sar32, + binop( Iop_Shl32, mkexpr(irt_regM), mkU8(16) ), + mkU8(16))) ); + assign( irt_prod_hi, + binop( Iop_Mul32, + binop( Iop_Sar32, mkexpr(irt_regN), mkU8(16) ), + binop( Iop_Sar32, mkexpr(irt_regM), mkU8(16) ) ) ); + assign( irt_sum, binop( isAD ? Iop_Add32 : Iop_Sub32, + mkexpr(irt_prod_lo), mkexpr(irt_prod_hi) ) ); + + IRExpr* ire_result = binop(Iop_Add32, mkexpr(irt_sum), mkexpr(irt_regA)); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + if (isAD) { + or_into_QFLAG32( + signed_overflow_after_Add32( mkexpr(irt_sum), + irt_prod_lo, irt_prod_hi ), + condT + ); + } + + or_into_QFLAG32( + signed_overflow_after_Add32( ire_result, irt_sum, irt_regA ), + condT + ); + + DIP("sml%cd%s%s r%u, r%u, r%u, r%u\n", + isAD ? 'a' : 's', + bitM ? "x" : "", nCC(conq), regD, regN, regM, regA); + return True; + } + /* fall through */ + } + + /* ----- smlabb, smlabt, smlatb, smlatt ,,, ----- */ + { + UInt regD = 99, regN = 99, regM = 99, regA = 99, bitM = 99, bitN = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFB1 && INSNT1(7,6) == BITS2(0,0)) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + regA = INSNT1(15,12); + bitM = INSNT1(4,4); + bitN = INSNT1(5,5); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM) + && !isBadRegT(regA)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,0,0,1,0,0,0,0) && + (INSNA(7,4) & BITS4(1,0,0,1)) == BITS4(1,0,0,0)) { + regD = INSNA(19,16); + regN = INSNA(3,0); + regM = INSNA(11,8); + regA = INSNA(15,12); + bitM = INSNA(6,6); + bitN = INSNA(5,5); + if (regD != 15 && regN != 15 && regM != 15 && regA != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regA = newTemp(Ity_I32); + IRTemp irt_prod = newTemp(Ity_I32); + + assign( irt_prod, + binop(Iop_Mul32, + binop(Iop_Sar32, + binop(Iop_Shl32, + isT ? getIRegT(regN) : getIRegA(regN), + mkU8(bitN ? 0 : 16)), + mkU8(16)), + binop(Iop_Sar32, + binop(Iop_Shl32, + isT ? getIRegT(regM) : getIRegA(regM), + mkU8(bitM ? 0 : 16)), + mkU8(16))) ); + + assign( irt_regA, isT ? getIRegT(regA) : getIRegA(regA) ); + + IRExpr* ire_result = binop(Iop_Add32, mkexpr(irt_prod), mkexpr(irt_regA)); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + or_into_QFLAG32( + signed_overflow_after_Add32( ire_result, irt_prod, irt_regA ), + condT + ); + + DIP( "smla%c%c%s r%u, r%u, r%u, r%u\n", + bitN ? 't' : 'b', bitM ? 't' : 'b', + nCC(conq), regD, regN, regM, regA ); + return True; + } + /* fall through */ + } + + /* ----- smlawb, smlawt ,,, ----- */ + { + UInt regD = 99, regN = 99, regM = 99, regA = 99, bitM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFB3 && INSNT1(7,5) == BITS3(0,0,0)) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + regA = INSNT1(15,12); + bitM = INSNT1(4,4); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM) + && !isBadRegT(regA)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,0,0,1,0,0,1,0) && + (INSNA(7,4) & BITS4(1,0,1,1)) == BITS4(1,0,0,0)) { + regD = INSNA(19,16); + regN = INSNA(3,0); + regM = INSNA(11,8); + regA = INSNA(15,12); + bitM = INSNA(6,6); + if (regD != 15 && regN != 15 && regM != 15 && regA != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regA = newTemp(Ity_I32); + IRTemp irt_prod = newTemp(Ity_I64); + + assign( irt_prod, + binop(Iop_MullS32, + isT ? getIRegT(regN) : getIRegA(regN), + binop(Iop_Sar32, + binop(Iop_Shl32, + isT ? getIRegT(regM) : getIRegA(regM), + mkU8(bitM ? 0 : 16)), + mkU8(16))) ); + + assign( irt_regA, isT ? getIRegT(regA) : getIRegA(regA) ); + + IRTemp prod32 = newTemp(Ity_I32); + assign(prod32, + binop(Iop_Or32, + binop(Iop_Shl32, unop(Iop_64HIto32, mkexpr(irt_prod)), mkU8(16)), + binop(Iop_Shr32, unop(Iop_64to32, mkexpr(irt_prod)), mkU8(16)) + )); + + IRExpr* ire_result = binop(Iop_Add32, mkexpr(prod32), mkexpr(irt_regA)); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + or_into_QFLAG32( + signed_overflow_after_Add32( ire_result, prod32, irt_regA ), + condT + ); + + DIP( "smlaw%c%s r%u, r%u, r%u, r%u\n", + bitM ? 't' : 'b', + nCC(conq), regD, regN, regM, regA ); + return True; + } + /* fall through */ + } + + /* ------------------- sel ,, -------------------- */ + /* fixme: fix up the test in v6media.c so that we can pass the ge + flags as part of the test. */ + { + UInt regD = 99, regN = 99, regM = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFAA && (INSNT1(15,0) & 0xF0F0) == 0xF080) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,1,0,0,0) && + INSNA(11,8) == BITS4(1,1,1,1) && + INSNA(7,4) == BITS4(1,0,1,1)) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_ge_flag0 = newTemp(Ity_I32); + IRTemp irt_ge_flag1 = newTemp(Ity_I32); + IRTemp irt_ge_flag2 = newTemp(Ity_I32); + IRTemp irt_ge_flag3 = newTemp(Ity_I32); + + assign( irt_ge_flag0, get_GEFLAG32(0) ); + assign( irt_ge_flag1, get_GEFLAG32(1) ); + assign( irt_ge_flag2, get_GEFLAG32(2) ); + assign( irt_ge_flag3, get_GEFLAG32(3) ); + + IRExpr* ire_ge_flag0_or + = binop(Iop_Or32, mkexpr(irt_ge_flag0), + binop(Iop_Sub32, mkU32(0), mkexpr(irt_ge_flag0))); + IRExpr* ire_ge_flag1_or + = binop(Iop_Or32, mkexpr(irt_ge_flag1), + binop(Iop_Sub32, mkU32(0), mkexpr(irt_ge_flag1))); + IRExpr* ire_ge_flag2_or + = binop(Iop_Or32, mkexpr(irt_ge_flag2), + binop(Iop_Sub32, mkU32(0), mkexpr(irt_ge_flag2))); + IRExpr* ire_ge_flag3_or + = binop(Iop_Or32, mkexpr(irt_ge_flag3), + binop(Iop_Sub32, mkU32(0), mkexpr(irt_ge_flag3))); + + IRExpr* ire_ge_flags + = binop( Iop_Or32, + binop(Iop_Or32, + binop(Iop_And32, + binop(Iop_Sar32, ire_ge_flag0_or, mkU8(31)), + mkU32(0x000000ff)), + binop(Iop_And32, + binop(Iop_Sar32, ire_ge_flag1_or, mkU8(31)), + mkU32(0x0000ff00))), + binop(Iop_Or32, + binop(Iop_And32, + binop(Iop_Sar32, ire_ge_flag2_or, mkU8(31)), + mkU32(0x00ff0000)), + binop(Iop_And32, + binop(Iop_Sar32, ire_ge_flag3_or, mkU8(31)), + mkU32(0xff000000))) ); + + IRExpr* ire_result + = binop(Iop_Or32, + binop(Iop_And32, + isT ? getIRegT(regN) : getIRegA(regN), + ire_ge_flags ), + binop(Iop_And32, + isT ? getIRegT(regM) : getIRegA(regM), + unop(Iop_Not32, ire_ge_flags))); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + DIP("sel%s r%u, r%u, r%u\n", nCC(conq), regD, regN, regM ); + return True; + } + /* fall through */ + } + + /* ----------------- uxtab16 Rd,Rn,Rm{,rot} ------------------ */ + { + UInt regD = 99, regN = 99, regM = 99, rotate = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFA3 && (INSNT1(15,0) & 0xF0C0) == 0xF080) { + regN = INSNT0(3,0); + regD = INSNT1(11,8); + regM = INSNT1(3,0); + rotate = INSNT1(5,4); + if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM)) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,0,1,1,0,0) && + INSNA(9,4) == BITS6(0,0,0,1,1,1) ) { + regD = INSNA(15,12); + regN = INSNA(19,16); + regM = INSNA(3,0); + rotate = INSNA(11,10); + if (regD != 15 && regN != 15 && regM != 15) + gate = True; + } + } + + if (gate) { + IRTemp irt_regN = newTemp(Ity_I32); + assign( irt_regN, isT ? getIRegT(regN) : getIRegA(regN) ); + + IRTemp irt_regM = newTemp(Ity_I32); + assign( irt_regM, isT ? getIRegT(regM) : getIRegA(regM) ); + + IRTemp irt_rot = newTemp(Ity_I32); + assign( irt_rot, binop(Iop_And32, + genROR32(irt_regM, 8 * rotate), + mkU32(0x00FF00FF)) ); + + IRExpr* resLo + = binop(Iop_And32, + binop(Iop_Add32, mkexpr(irt_regN), mkexpr(irt_rot)), + mkU32(0x0000FFFF)); + + IRExpr* resHi + = binop(Iop_Add32, + binop(Iop_And32, mkexpr(irt_regN), mkU32(0xFFFF0000)), + binop(Iop_And32, mkexpr(irt_rot), mkU32(0xFFFF0000))); + + IRExpr* ire_result + = binop( Iop_Or32, resHi, resLo ); + + if (isT) + putIRegT( regD, ire_result, condT ); + else + putIRegA( regD, ire_result, condT, Ijk_Boring ); + + DIP( "uxtab16%s r%u, r%u, r%u, ROR #%u\n", + nCC(conq), regD, regN, regM, 8 * rotate ); + return True; + } + /* fall through */ + } + + /* --------------- usad8 Rd,Rn,Rm ---------------- */ + /* --------------- usada8 Rd,Rn,Rm,Ra ---------------- */ + { + UInt rD = 99, rN = 99, rM = 99, rA = 99; + Bool gate = False; + + if (isT) { + if (INSNT0(15,4) == 0xFB7 && INSNT1(7,4) == BITS4(0,0,0,0)) { + rN = INSNT0(3,0); + rA = INSNT1(15,12); + rD = INSNT1(11,8); + rM = INSNT1(3,0); + if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && rA != 13) + gate = True; + } + } else { + if (INSNA(27,20) == BITS8(0,1,1,1,1,0,0,0) && + INSNA(7,4) == BITS4(0,0,0,1) ) { + rD = INSNA(19,16); + rA = INSNA(15,12); + rM = INSNA(11,8); + rN = INSNA(3,0); + if (rD != 15 && rN != 15 && rM != 15 /* but rA can be 15 */) + gate = True; + } + } + /* We allow rA == 15, to denote the usad8 (no accumulator) case. */ + + if (gate) { + IRExpr* rNe = isT ? getIRegT(rN) : getIRegA(rN); + IRExpr* rMe = isT ? getIRegT(rM) : getIRegA(rM); + IRExpr* rAe = rA == 15 ? mkU32(0) + : (isT ? getIRegT(rA) : getIRegA(rA)); + IRExpr* res = binop(Iop_Add32, + binop(Iop_Sad8Ux4, rNe, rMe), + rAe); + if (isT) + putIRegT( rD, res, condT ); + else + putIRegA( rD, res, condT, Ijk_Boring ); + + if (rA == 15) { + DIP( "usad8%s r%u, r%u, r%u\n", + nCC(conq), rD, rN, rM ); + } else { + DIP( "usada8%s r%u, r%u, r%u, r%u\n", + nCC(conq), rD, rN, rM, rA ); + } + return True; + } + /* fall through */ + } + + /* ---------- Doesn't match anything. ---------- */ + return False; + +# undef INSNA +# undef INSNT0 +# undef INSNT1 +} + + +/*------------------------------------------------------------*/ +/*--- LDMxx/STMxx helper (both ARM and Thumb32) ---*/ +/*------------------------------------------------------------*/ + +/* Generate IR for LDMxx and STMxx. This is complex. Assumes it's + unconditional, so the caller must produce a jump-around before + calling this, if the insn is to be conditional. Caller is + responsible for all validation of parameters. For LDMxx, if PC is + amongst the values loaded, caller is also responsible for + generating the jump. */ +static void mk_ldm_stm ( Bool arm, /* True: ARM, False: Thumb */ + UInt rN, /* base reg */ + UInt bINC, /* 1: inc, 0: dec */ + UInt bBEFORE, /* 1: inc/dec before, 0: after */ + UInt bW, /* 1: writeback to Rn */ + UInt bL, /* 1: load, 0: store */ + UInt regList ) +{ + Int i, r, m, nRegs; + + /* Get hold of the old Rn value. We might need to write its value + to memory during a store, and if it's also the writeback + register then we need to get its value now. We can't treat it + exactly like the other registers we're going to transfer, + because for xxMDA and xxMDB writeback forms, the generated IR + updates Rn in the guest state before any transfers take place. + We have to do this as per comments below, in order that if Rn is + the stack pointer then it always has a value is below or equal + to any of the transfer addresses. Ick. */ + IRTemp oldRnT = newTemp(Ity_I32); + assign(oldRnT, arm ? getIRegA(rN) : getIRegT(rN)); + + IRTemp anchorT = newTemp(Ity_I32); + /* The old (Addison-Wesley) ARM ARM seems to say that LDMxx/STMxx + ignore the bottom two bits of the address. However, Cortex-A8 + doesn't seem to care. Hence: */ + /* No .. don't force alignment .. */ + /* assign(anchorT, binop(Iop_And32, mkexpr(oldRnT), mkU32(~3U))); */ + /* Instead, use the potentially misaligned address directly. */ + assign(anchorT, mkexpr(oldRnT)); + + IROp opADDorSUB = bINC ? Iop_Add32 : Iop_Sub32; + // bINC == 1: xxMIA, xxMIB + // bINC == 0: xxMDA, xxMDB + + // For xxMDA and xxMDB, update Rn first if necessary. We have + // to do this first so that, for the common idiom of the transfers + // faulting because we're pushing stuff onto a stack and the stack + // is growing down onto allocate-on-fault pages (as Valgrind simulates), + // we need to have the SP up-to-date "covering" (pointing below) the + // transfer area. For the same reason, if we are doing xxMIA or xxMIB, + // do the transfer first, and then update rN afterwards. + nRegs = 0; + for (i = 0; i < 16; i++) { + if ((regList & (1 << i)) != 0) + nRegs++; + } + if (bW == 1 && !bINC) { + IRExpr* e = binop(opADDorSUB, mkexpr(oldRnT), mkU32(4*nRegs)); + if (arm) + putIRegA( rN, e, IRTemp_INVALID, Ijk_Boring ); + else + putIRegT( rN, e, IRTemp_INVALID ); + } + + // Make up a list of the registers to transfer, and their offsets + // in memory relative to the anchor. If the base reg (Rn) is part + // of the transfer, then do it last for a load and first for a store. + UInt xReg[16], xOff[16]; + Int nX = 0; + m = 0; + for (i = 0; i < 16; i++) { + r = bINC ? i : (15-i); + if (0 == (regList & (1< 0); + for (i = 0; i < nX; i++) { + if (xReg[i] == rN) + break; + } + vassert(i < nX); /* else we didn't find it! */ + UInt tReg = xReg[i]; + UInt tOff = xOff[i]; + if (bL == 1) { + /* load; make this transfer happen last */ + if (i < nX-1) { + for (m = i+1; m < nX; m++) { + xReg[m-1] = xReg[m]; + xOff[m-1] = xOff[m]; + } + vassert(m == nX); + xReg[m-1] = tReg; + xOff[m-1] = tOff; + } + } else { + /* store; make this transfer happen first */ + if (i > 0) { + for (m = i-1; m >= 0; m--) { + xReg[m+1] = xReg[m]; + xOff[m+1] = xOff[m]; + } + vassert(m == -1); + xReg[0] = tReg; + xOff[0] = tOff; + } + } + + if (0) { + vex_printf("REG_LIST_POST:\n"); + for (i = 0; i < nX; i++) + vex_printf("reg %d off %d\n", xReg[i], xOff[i]); + vex_printf("\n"); + } + } + + /* Actually generate the transfers */ + for (i = 0; i < nX; i++) { + r = xReg[i]; + if (bL == 1) { + IRExpr* e = loadLE(Ity_I32, + binop(opADDorSUB, mkexpr(anchorT), + mkU32(xOff[i]))); + if (arm) { + putIRegA( r, e, IRTemp_INVALID, Ijk_Ret ); + } else { + // no: putIRegT( r, e, IRTemp_INVALID ); + // putIRegT refuses to write to R15. But that might happen. + // Since this is uncond, and we need to be able to + // write the PC, just use the low level put: + llPutIReg( r, e ); + } + } else { + /* if we're storing Rn, make sure we use the correct + value, as per extensive comments above */ + storeLE( binop(opADDorSUB, mkexpr(anchorT), mkU32(xOff[i])), + r == rN ? mkexpr(oldRnT) + : (arm ? getIRegA(r) : getIRegT(r) ) ); + } + } + + // If we are doing xxMIA or xxMIB, + // do the transfer first, and then update rN afterwards. + if (bW == 1 && bINC) { + IRExpr* e = binop(opADDorSUB, mkexpr(oldRnT), mkU32(4*nRegs)); + if (arm) + putIRegA( rN, e, IRTemp_INVALID, Ijk_Boring ); + else + putIRegT( rN, e, IRTemp_INVALID ); + } +} + + +/*------------------------------------------------------------*/ +/*--- VFP (CP 10 and 11) instructions ---*/ +/*------------------------------------------------------------*/ + +/* Both ARM and Thumb */ + +/* Translate a CP10 or CP11 instruction. If successful, returns + True and *dres may or may not be updated. If failure, returns + False and doesn't change *dres nor create any IR. + + The ARM and Thumb encodings are identical for the low 28 bits of + the insn (yay!) and that's what the caller must supply, iow, imm28 + has the top 4 bits masked out. Caller is responsible for + determining whether the masked-out bits are valid for a CP10/11 + insn. The rules for the top 4 bits are: + + ARM: 0000 to 1110 allowed, and this is the gating condition. + 1111 (NV) is not allowed. + + Thumb: must be 1110. The gating condition is taken from + ITSTATE in the normal way. + + Conditionalisation: + + Caller must supply an IRTemp 'condT' holding the gating condition, + or IRTemp_INVALID indicating the insn is always executed. + + Caller must also supply an ARMCondcode 'cond'. This is only used + for debug printing, no other purpose. For ARM, this is simply the + top 4 bits of the original instruction. For Thumb, the condition + is not (really) known until run time, and so ARMCondAL should be + passed, only so that printing of these instructions does not show + any condition. + + Finally, the caller must indicate whether this occurs in ARM or + Thumb code. +*/ +static Bool decode_CP10_CP11_instruction ( + /*MOD*/DisResult* dres, + UInt insn28, + IRTemp condT, + ARMCondcode conq, + Bool isT + ) +{ +# define INSN(_bMax,_bMin) SLICE_UInt(insn28, (_bMax), (_bMin)) + + vassert(INSN(31,28) == BITS4(0,0,0,0)); // caller's obligation + + if (isT) { + vassert(conq == ARMCondAL); + } else { + vassert(conq >= ARMCondEQ && conq <= ARMCondAL); + } + + /* ----------------------------------------------------------- */ + /* -- VFP instructions -- double precision (mostly) -- */ + /* ----------------------------------------------------------- */ + + /* --------------------- fldmx, fstmx --------------------- */ + /* + 31 27 23 19 15 11 7 0 + P U WL + C4-100, C5-26 1 FSTMX cond 1100 1000 Rn Dd 1011 offset + C4-100, C5-28 2 FSTMIAX cond 1100 1010 Rn Dd 1011 offset + C4-100, C5-30 3 FSTMDBX cond 1101 0010 Rn Dd 1011 offset + + C4-42, C5-26 1 FLDMX cond 1100 1001 Rn Dd 1011 offset + C4-42, C5-28 2 FLDMIAX cond 1100 1011 Rn Dd 1011 offset + C4-42, C5-30 3 FLDMDBX cond 1101 0011 Rn Dd 1011 offset + + Regs transferred: Dd .. D(d + (offset-3)/2) + offset must be odd, must not imply a reg > 15 + IA/DB: Rn is changed by (4 + 8 x # regs transferred) + + case coding: + 1 at-Rn (access at Rn) + 2 ia-Rn (access at Rn, then Rn += 4+8n) + 3 db-Rn (Rn -= 4+8n, then access at Rn) + */ + if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0)) + && INSN(11,8) == BITS4(1,0,1,1)) { + UInt bP = (insn28 >> 24) & 1; + UInt bU = (insn28 >> 23) & 1; + UInt bW = (insn28 >> 21) & 1; + UInt bL = (insn28 >> 20) & 1; + UInt offset = (insn28 >> 0) & 0xFF; + UInt rN = INSN(19,16); + UInt dD = (INSN(22,22) << 4) | INSN(15,12); + UInt nRegs = (offset - 1) / 2; + UInt summary = 0; + Int i; + + /**/ if (bP == 0 && bU == 1 && bW == 0) { + summary = 1; + } + else if (bP == 0 && bU == 1 && bW == 1) { + summary = 2; + } + else if (bP == 1 && bU == 0 && bW == 1) { + summary = 3; + } + else goto after_vfp_fldmx_fstmx; + + /* no writebacks to r15 allowed. No use of r15 in thumb mode. */ + if (rN == 15 && (summary == 2 || summary == 3 || isT)) + goto after_vfp_fldmx_fstmx; + + /* offset must be odd, and specify at least one register */ + if (0 == (offset & 1) || offset < 3) + goto after_vfp_fldmx_fstmx; + + /* can't transfer regs after D15 */ + if (dD + nRegs - 1 >= 32) + goto after_vfp_fldmx_fstmx; + + /* Now, we can't do a conditional load or store, since that very + likely will generate an exception. So we have to take a side + exit at this point if the condition is false. */ + if (condT != IRTemp_INVALID) { + if (isT) + mk_skip_over_T32_if_cond_is_false( condT ); + else + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + /* Ok, now we're unconditional. Do the load or store. */ + + /* get the old Rn value */ + IRTemp rnT = newTemp(Ity_I32); + assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN), + rN == 15)); + + /* make a new value for Rn, post-insn */ + IRTemp rnTnew = IRTemp_INVALID; + if (summary == 2 || summary == 3) { + rnTnew = newTemp(Ity_I32); + assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32, + mkexpr(rnT), + mkU32(4 + 8 * nRegs))); + } + + /* decide on the base transfer address */ + IRTemp taT = newTemp(Ity_I32); + assign(taT, summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT)); + + /* update Rn if necessary -- in case 3, we're moving it down, so + update before any memory reference, in order to keep Memcheck + and V's stack-extending logic (on linux) happy */ + if (summary == 3) { + if (isT) + putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID); + else + putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring); + } + + /* generate the transfers */ + for (i = 0; i < nRegs; i++) { + IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(8*i)); + if (bL) { + putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID); + } else { + storeLE(addr, getDReg(dD + i)); + } + } + + /* update Rn if necessary -- in case 2, we're moving it up, so + update after any memory reference, in order to keep Memcheck + and V's stack-extending logic (on linux) happy */ + if (summary == 2) { + if (isT) + putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID); + else + putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring); + } + + HChar* nm = bL==1 ? "ld" : "st"; + switch (summary) { + case 1: DIP("f%smx%s r%u, {d%u-d%u}\n", + nm, nCC(conq), rN, dD, dD + nRegs - 1); + break; + case 2: DIP("f%smiax%s r%u!, {d%u-d%u}\n", + nm, nCC(conq), rN, dD, dD + nRegs - 1); + break; + case 3: DIP("f%smdbx%s r%u!, {d%u-d%u}\n", + nm, nCC(conq), rN, dD, dD + nRegs - 1); + break; + default: vassert(0); + } + + goto decode_success_vfp; + /* FIXME alignment constraints? */ + } + + after_vfp_fldmx_fstmx: + + /* --------------------- fldmd, fstmd --------------------- */ + /* + 31 27 23 19 15 11 7 0 + P U WL + C4-96, C5-26 1 FSTMD cond 1100 1000 Rn Dd 1011 offset + C4-96, C5-28 2 FSTMDIA cond 1100 1010 Rn Dd 1011 offset + C4-96, C5-30 3 FSTMDDB cond 1101 0010 Rn Dd 1011 offset + + C4-38, C5-26 1 FLDMD cond 1100 1001 Rn Dd 1011 offset + C4-38, C5-28 2 FLDMIAD cond 1100 1011 Rn Dd 1011 offset + C4-38, C5-30 3 FLDMDBD cond 1101 0011 Rn Dd 1011 offset + + Regs transferred: Dd .. D(d + (offset-2)/2) + offset must be even, must not imply a reg > 15 + IA/DB: Rn is changed by (8 x # regs transferred) + + case coding: + 1 at-Rn (access at Rn) + 2 ia-Rn (access at Rn, then Rn += 8n) + 3 db-Rn (Rn -= 8n, then access at Rn) + */ + if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0)) + && INSN(11,8) == BITS4(1,0,1,1)) { + UInt bP = (insn28 >> 24) & 1; + UInt bU = (insn28 >> 23) & 1; + UInt bW = (insn28 >> 21) & 1; + UInt bL = (insn28 >> 20) & 1; + UInt offset = (insn28 >> 0) & 0xFF; + UInt rN = INSN(19,16); + UInt dD = (INSN(22,22) << 4) | INSN(15,12); + UInt nRegs = offset / 2; + UInt summary = 0; + Int i; + + /**/ if (bP == 0 && bU == 1 && bW == 0) { + summary = 1; + } + else if (bP == 0 && bU == 1 && bW == 1) { + summary = 2; + } + else if (bP == 1 && bU == 0 && bW == 1) { + summary = 3; + } + else goto after_vfp_fldmd_fstmd; + + /* no writebacks to r15 allowed. No use of r15 in thumb mode. */ + if (rN == 15 && (summary == 2 || summary == 3 || isT)) + goto after_vfp_fldmd_fstmd; + + /* offset must be even, and specify at least one register */ + if (1 == (offset & 1) || offset < 2) + goto after_vfp_fldmd_fstmd; + + /* can't transfer regs after D15 */ + if (dD + nRegs - 1 >= 32) + goto after_vfp_fldmd_fstmd; + + /* Now, we can't do a conditional load or store, since that very + likely will generate an exception. So we have to take a side + exit at this point if the condition is false. */ + if (condT != IRTemp_INVALID) { + if (isT) + mk_skip_over_T32_if_cond_is_false( condT ); + else + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + /* Ok, now we're unconditional. Do the load or store. */ + + /* get the old Rn value */ + IRTemp rnT = newTemp(Ity_I32); + assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN), + rN == 15)); + + /* make a new value for Rn, post-insn */ + IRTemp rnTnew = IRTemp_INVALID; + if (summary == 2 || summary == 3) { + rnTnew = newTemp(Ity_I32); + assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32, + mkexpr(rnT), + mkU32(8 * nRegs))); + } + + /* decide on the base transfer address */ + IRTemp taT = newTemp(Ity_I32); + assign(taT, summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT)); + + /* update Rn if necessary -- in case 3, we're moving it down, so + update before any memory reference, in order to keep Memcheck + and V's stack-extending logic (on linux) happy */ + if (summary == 3) { + if (isT) + putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID); + else + putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring); + } + + /* generate the transfers */ + for (i = 0; i < nRegs; i++) { + IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(8*i)); + if (bL) { + putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID); + } else { + storeLE(addr, getDReg(dD + i)); + } + } + + /* update Rn if necessary -- in case 2, we're moving it up, so + update after any memory reference, in order to keep Memcheck + and V's stack-extending logic (on linux) happy */ + if (summary == 2) { + if (isT) + putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID); + else + putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring); + } + + HChar* nm = bL==1 ? "ld" : "st"; + switch (summary) { + case 1: DIP("f%smd%s r%u, {d%u-d%u}\n", + nm, nCC(conq), rN, dD, dD + nRegs - 1); + break; + case 2: DIP("f%smiad%s r%u!, {d%u-d%u}\n", + nm, nCC(conq), rN, dD, dD + nRegs - 1); + break; + case 3: DIP("f%smdbd%s r%u!, {d%u-d%u}\n", + nm, nCC(conq), rN, dD, dD + nRegs - 1); + break; + default: vassert(0); + } + + goto decode_success_vfp; + /* FIXME alignment constraints? */ + } + + after_vfp_fldmd_fstmd: + + /* ------------------- fmrx, fmxr ------------------- */ + if (BITS8(1,1,1,0,1,1,1,1) == INSN(27,20) + && BITS4(1,0,1,0) == INSN(11,8) + && BITS8(0,0,0,1,0,0,0,0) == (insn28 & 0xFF)) { + UInt rD = INSN(15,12); + UInt reg = INSN(19,16); + if (reg == BITS4(0,0,0,1)) { + if (rD == 15) { + IRTemp nzcvT = newTemp(Ity_I32); + /* When rD is 15, we are copying the top 4 bits of FPSCR + into CPSR. That is, set the flags thunk to COPY and + install FPSCR[31:28] as the value to copy. */ + assign(nzcvT, binop(Iop_And32, + IRExpr_Get(OFFB_FPSCR, Ity_I32), + mkU32(0xF0000000))); + setFlags_D1(ARMG_CC_OP_COPY, nzcvT, condT); + DIP("fmstat%s\n", nCC(conq)); + } else { + /* Otherwise, merely transfer FPSCR to r0 .. r14. */ + IRExpr* e = IRExpr_Get(OFFB_FPSCR, Ity_I32); + if (isT) + putIRegT(rD, e, condT); + else + putIRegA(rD, e, condT, Ijk_Boring); + DIP("fmrx%s r%u, fpscr\n", nCC(conq), rD); + } + goto decode_success_vfp; + } + /* fall through */ + } + + if (BITS8(1,1,1,0,1,1,1,0) == INSN(27,20) + && BITS4(1,0,1,0) == INSN(11,8) + && BITS8(0,0,0,1,0,0,0,0) == (insn28 & 0xFF)) { + UInt rD = INSN(15,12); + UInt reg = INSN(19,16); + if (reg == BITS4(0,0,0,1)) { + putMiscReg32(OFFB_FPSCR, + isT ? getIRegT(rD) : getIRegA(rD), condT); + DIP("fmxr%s fpscr, r%u\n", nCC(conq), rD); + goto decode_success_vfp; + } + /* fall through */ + } + + /* --------------------- vmov --------------------- */ + // VMOV dM, rD, rN + if (0x0C400B10 == (insn28 & 0x0FF00FD0)) { + UInt dM = INSN(3,0) | (INSN(5,5) << 4); + UInt rD = INSN(15,12); /* lo32 */ + UInt rN = INSN(19,16); /* hi32 */ + if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13))) { + /* fall through */ + } else { + putDReg(dM, + unop(Iop_ReinterpI64asF64, + binop(Iop_32HLto64, + isT ? getIRegT(rN) : getIRegA(rN), + isT ? getIRegT(rD) : getIRegA(rD))), + condT); + DIP("vmov%s d%u, r%u, r%u\n", nCC(conq), dM, rD, rN); + goto decode_success_vfp; + } + /* fall through */ + } + + // VMOV rD, rN, dM + if (0x0C500B10 == (insn28 & 0x0FF00FD0)) { + UInt dM = INSN(3,0) | (INSN(5,5) << 4); + UInt rD = INSN(15,12); /* lo32 */ + UInt rN = INSN(19,16); /* hi32 */ + if (rD == 15 || rN == 15 || (isT && (rD == 13 || rN == 13)) + || rD == rN) { + /* fall through */ + } else { + IRTemp i64 = newTemp(Ity_I64); + assign(i64, unop(Iop_ReinterpF64asI64, getDReg(dM))); + IRExpr* hi32 = unop(Iop_64HIto32, mkexpr(i64)); + IRExpr* lo32 = unop(Iop_64to32, mkexpr(i64)); + if (isT) { + putIRegT(rN, hi32, condT); + putIRegT(rD, lo32, condT); + } else { + putIRegA(rN, hi32, condT, Ijk_Boring); + putIRegA(rD, lo32, condT, Ijk_Boring); + } + DIP("vmov%s r%u, r%u, d%u\n", nCC(conq), rD, rN, dM); + goto decode_success_vfp; + } + /* fall through */ + } + + // VMOV sD, sD+1, rN, rM + if (0x0C400A10 == (insn28 & 0x0FF00FD0)) { + UInt sD = (INSN(3,0) << 1) | INSN(5,5); + UInt rN = INSN(15,12); + UInt rM = INSN(19,16); + if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13)) + || sD == 31) { + /* fall through */ + } else { + putFReg(sD, + unop(Iop_ReinterpI32asF32, isT ? getIRegT(rN) : getIRegA(rN)), + condT); + putFReg(sD+1, + unop(Iop_ReinterpI32asF32, isT ? getIRegT(rM) : getIRegA(rM)), + condT); + DIP("vmov%s, s%u, s%u, r%u, r%u\n", + nCC(conq), sD, sD + 1, rN, rM); + goto decode_success_vfp; + } + } + + // VMOV rN, rM, sD, sD+1 + if (0x0C500A10 == (insn28 & 0x0FF00FD0)) { + UInt sD = (INSN(3,0) << 1) | INSN(5,5); + UInt rN = INSN(15,12); + UInt rM = INSN(19,16); + if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13)) + || sD == 31 || rN == rM) { + /* fall through */ + } else { + IRExpr* res0 = unop(Iop_ReinterpF32asI32, getFReg(sD)); + IRExpr* res1 = unop(Iop_ReinterpF32asI32, getFReg(sD+1)); + if (isT) { + putIRegT(rN, res0, condT); + putIRegT(rM, res1, condT); + } else { + putIRegA(rN, res0, condT, Ijk_Boring); + putIRegA(rM, res1, condT, Ijk_Boring); + } + DIP("vmov%s, r%u, r%u, s%u, s%u\n", + nCC(conq), rN, rM, sD, sD + 1); + goto decode_success_vfp; + } + } + + // VMOV rD[x], rT (ARM core register to scalar) + if (0x0E000B10 == (insn28 & 0x0F900F1F)) { + UInt rD = (INSN(7,7) << 4) | INSN(19,16); + UInt rT = INSN(15,12); + UInt opc = (INSN(22,21) << 2) | INSN(6,5); + UInt index; + if (rT == 15 || (isT && rT == 13)) { + /* fall through */ + } else { + if ((opc & BITS4(1,0,0,0)) == BITS4(1,0,0,0)) { + index = opc & 7; + putDRegI64(rD, triop(Iop_SetElem8x8, + getDRegI64(rD), + mkU8(index), + unop(Iop_32to8, + isT ? getIRegT(rT) : getIRegA(rT))), + condT); + DIP("vmov%s.8 d%u[%u], r%u\n", nCC(conq), rD, index, rT); + goto decode_success_vfp; + } + else if ((opc & BITS4(1,0,0,1)) == BITS4(0,0,0,1)) { + index = (opc >> 1) & 3; + putDRegI64(rD, triop(Iop_SetElem16x4, + getDRegI64(rD), + mkU8(index), + unop(Iop_32to16, + isT ? getIRegT(rT) : getIRegA(rT))), + condT); + DIP("vmov%s.16 d%u[%u], r%u\n", nCC(conq), rD, index, rT); + goto decode_success_vfp; + } + else if ((opc & BITS4(1,0,1,1)) == BITS4(0,0,0,0)) { + index = (opc >> 2) & 1; + putDRegI64(rD, triop(Iop_SetElem32x2, + getDRegI64(rD), + mkU8(index), + isT ? getIRegT(rT) : getIRegA(rT)), + condT); + DIP("vmov%s.32 d%u[%u], r%u\n", nCC(conq), rD, index, rT); + goto decode_success_vfp; + } else { + /* fall through */ + } + } + } + + // VMOV (scalar to ARM core register) + // VMOV rT, rD[x] + if (0x0E100B10 == (insn28 & 0x0F100F1F)) { + UInt rN = (INSN(7,7) << 4) | INSN(19,16); + UInt rT = INSN(15,12); + UInt U = INSN(23,23); + UInt opc = (INSN(22,21) << 2) | INSN(6,5); + UInt index; + if (rT == 15 || (isT && rT == 13)) { + /* fall through */ + } else { + if ((opc & BITS4(1,0,0,0)) == BITS4(1,0,0,0)) { + index = opc & 7; + IRExpr* e = unop(U ? Iop_8Uto32 : Iop_8Sto32, + binop(Iop_GetElem8x8, + getDRegI64(rN), + mkU8(index))); + if (isT) + putIRegT(rT, e, condT); + else + putIRegA(rT, e, condT, Ijk_Boring); + DIP("vmov%s.%c8 r%u, d%u[%u]\n", nCC(conq), U ? 'u' : 's', + rT, rN, index); + goto decode_success_vfp; + } + else if ((opc & BITS4(1,0,0,1)) == BITS4(0,0,0,1)) { + index = (opc >> 1) & 3; + IRExpr* e = unop(U ? Iop_16Uto32 : Iop_16Sto32, + binop(Iop_GetElem16x4, + getDRegI64(rN), + mkU8(index))); + if (isT) + putIRegT(rT, e, condT); + else + putIRegA(rT, e, condT, Ijk_Boring); + DIP("vmov%s.%c16 r%u, d%u[%u]\n", nCC(conq), U ? 'u' : 's', + rT, rN, index); + goto decode_success_vfp; + } + else if ((opc & BITS4(1,0,1,1)) == BITS4(0,0,0,0) && U == 0) { + index = (opc >> 2) & 1; + IRExpr* e = binop(Iop_GetElem32x2, getDRegI64(rN), mkU8(index)); + if (isT) + putIRegT(rT, e, condT); + else + putIRegA(rT, e, condT, Ijk_Boring); + DIP("vmov%s.32 r%u, d%u[%u]\n", nCC(conq), rT, rN, index); + goto decode_success_vfp; + } else { + /* fall through */ + } + } + } + + // VMOV.F32 sD, #imm + // FCONSTS sD, #imm + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,0,0,0) == INSN(7,4) && INSN(11,8) == BITS4(1,0,1,0)) { + UInt rD = (INSN(15,12) << 1) | INSN(22,22); + UInt imm8 = (INSN(19,16) << 4) | INSN(3,0); + UInt b = (imm8 >> 6) & 1; + UInt imm; + imm = (BITS8((imm8 >> 7) & 1,(~b) & 1,b,b,b,b,b,(imm8 >> 5) & 1) << 8) + | ((imm8 & 0x1f) << 3); + imm <<= 16; + putFReg(rD, unop(Iop_ReinterpI32asF32, mkU32(imm)), condT); + DIP("fconsts%s s%u #%u", nCC(conq), rD, imm8); + goto decode_success_vfp; + } + + // VMOV.F64 dD, #imm + // FCONSTD dD, #imm + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,0,0,0) == INSN(7,4) && INSN(11,8) == BITS4(1,0,1,1)) { + UInt rD = INSN(15,12) | (INSN(22,22) << 4); + UInt imm8 = (INSN(19,16) << 4) | INSN(3,0); + UInt b = (imm8 >> 6) & 1; + ULong imm; + imm = (BITS8((imm8 >> 7) & 1,(~b) & 1,b,b,b,b,b,b) << 8) + | BITS8(b,b,0,0,0,0,0,0) | (imm8 & 0x3f); + imm <<= 48; + putDReg(rD, unop(Iop_ReinterpI64asF64, mkU64(imm)), condT); + DIP("fconstd%s d%u #%u", nCC(conq), rD, imm8); + goto decode_success_vfp; + } + + /* ---------------------- vdup ------------------------- */ + // VDUP dD, rT + // VDUP qD, rT + if (BITS8(1,1,1,0,1,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,0,1)) + && BITS4(1,0,1,1) == INSN(11,8) && INSN(6,6) == 0 && INSN(4,4) == 1) { + UInt rD = (INSN(7,7) << 4) | INSN(19,16); + UInt rT = INSN(15,12); + UInt Q = INSN(21,21); + UInt size = (INSN(22,22) << 1) | INSN(5,5); + if (rT == 15 || (isT && rT == 13) || size == 3i || (Q && (rD & 1))) { + /* fall through */ + } else { + IRExpr* e = isT ? getIRegT(rT) : getIRegA(rT); + if (Q) { + rD >>= 1; + switch (size) { + case 0: + putQReg(rD, unop(Iop_Dup32x4, e), condT); + break; + case 1: + putQReg(rD, unop(Iop_Dup16x8, unop(Iop_32to16, e)), + condT); + break; + case 2: + putQReg(rD, unop(Iop_Dup8x16, unop(Iop_32to8, e)), + condT); + break; + default: + vassert(0); + } + DIP("vdup.%u q%u, r%u\n", 32 / (1<> 23) & 1; /* 1: +offset 0: -offset */ + UInt bL = (insn28 >> 20) & 1; /* 1: load 0: store */ + /* make unconditional */ + if (condT != IRTemp_INVALID) { + if (isT) + mk_skip_over_T32_if_cond_is_false( condT ); + else + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + IRTemp ea = newTemp(Ity_I32); + assign(ea, binop(bU ? Iop_Add32 : Iop_Sub32, + align4if(isT ? getIRegT(rN) : getIRegA(rN), + rN == 15), + mkU32(offset))); + if (bL) { + putDReg(dD, loadLE(Ity_F64,mkexpr(ea)), IRTemp_INVALID); + } else { + storeLE(mkexpr(ea), getDReg(dD)); + } + DIP("f%sd%s d%u, [r%u, %c#%u]\n", + bL ? "ld" : "st", nCC(conq), dD, rN, + bU ? '+' : '-', offset); + goto decode_success_vfp; + } + + /* --------------------- dp insns (D) --------------------- */ + if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0)) + && BITS4(1,0,1,1) == INSN(11,8) + && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(0,0,0,1))) { + UInt dM = INSN(3,0) | (INSN(5,5) << 4); /* argR */ + UInt dD = INSN(15,12) | (INSN(22,22) << 4); /* dst/acc */ + UInt dN = INSN(19,16) | (INSN(7,7) << 4); /* argL */ + UInt bP = (insn28 >> 23) & 1; + UInt bQ = (insn28 >> 21) & 1; + UInt bR = (insn28 >> 20) & 1; + UInt bS = (insn28 >> 6) & 1; + UInt opc = (bP << 3) | (bQ << 2) | (bR << 1) | bS; + IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */ + switch (opc) { + case BITS4(0,0,0,0): /* MAC: d + n * m */ + putDReg(dD, triop(Iop_AddF64, rm, + getDReg(dD), + triop(Iop_MulF64, rm, getDReg(dN), + getDReg(dM))), + condT); + DIP("fmacd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + case BITS4(0,0,0,1): /* NMAC: d + -(n * m) */ + putDReg(dD, triop(Iop_AddF64, rm, + getDReg(dD), + unop(Iop_NegF64, + triop(Iop_MulF64, rm, getDReg(dN), + getDReg(dM)))), + condT); + DIP("fnmacd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + case BITS4(0,0,1,0): /* MSC: - d + n * m */ + putDReg(dD, triop(Iop_AddF64, rm, + unop(Iop_NegF64, getDReg(dD)), + triop(Iop_MulF64, rm, getDReg(dN), + getDReg(dM))), + condT); + DIP("fmscd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + case BITS4(0,0,1,1): /* NMSC: - d + -(n * m) */ + putDReg(dD, triop(Iop_AddF64, rm, + unop(Iop_NegF64, getDReg(dD)), + unop(Iop_NegF64, + triop(Iop_MulF64, rm, getDReg(dN), + getDReg(dM)))), + condT); + DIP("fnmscd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + case BITS4(0,1,0,0): /* MUL: n * m */ + putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)), + condT); + DIP("fmuld%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + case BITS4(0,1,0,1): /* NMUL: - n * m */ + putDReg(dD, unop(Iop_NegF64, + triop(Iop_MulF64, rm, getDReg(dN), + getDReg(dM))), + condT); + DIP("fnmuld%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + case BITS4(0,1,1,0): /* ADD: n + m */ + putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)), + condT); + DIP("faddd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + case BITS4(0,1,1,1): /* SUB: n - m */ + putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)), + condT); + DIP("fsubd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + case BITS4(1,0,0,0): /* DIV: n / m */ + putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)), + condT); + DIP("fdivd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); + goto decode_success_vfp; + default: + break; + } + } + + /* --------------------- compares (D) --------------------- */ + /* 31 27 23 19 15 11 7 3 + 28 24 20 16 12 8 4 0 + FCMPD cond 1110 1D11 0100 Dd 1011 0100 Dm + FCMPED cond 1110 1D11 0100 Dd 1011 1100 Dm + FCMPZD cond 1110 1D11 0101 Dd 1011 0100 0000 + FCMPZED cond 1110 1D11 0101 Dd 1011 1100 0000 + Z N + + Z=0 Compare Dd vs Dm and set FPSCR 31:28 accordingly + Z=1 Compare Dd vs zero + + N=1 generates Invalid Operation exn if either arg is any kind of NaN + N=0 generates Invalid Operation exn if either arg is a signalling NaN + (Not that we pay any attention to N here) + */ + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0)) + && BITS4(1,0,1,1) == INSN(11,8) + && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) { + UInt bZ = (insn28 >> 16) & 1; + UInt bN = (insn28 >> 7) & 1; + UInt dD = INSN(15,12) | (INSN(22,22) << 4); + UInt dM = INSN(3,0) | (INSN(5,5) << 4); + if (bZ && INSN(3,0) != 0) { + /* does not decode; fall through */ + } else { + IRTemp argL = newTemp(Ity_F64); + IRTemp argR = newTemp(Ity_F64); + IRTemp irRes = newTemp(Ity_I32); + assign(argL, getDReg(dD)); + assign(argR, bZ ? IRExpr_Const(IRConst_F64i(0)) : getDReg(dM)); + assign(irRes, binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR))); + + IRTemp nzcv = IRTemp_INVALID; + IRTemp oldFPSCR = newTemp(Ity_I32); + IRTemp newFPSCR = newTemp(Ity_I32); + + /* This is where the fun starts. We have to convert 'irRes' + from an IR-convention return result (IRCmpF64Result) to an + ARM-encoded (N,Z,C,V) group. The final result is in the + bottom 4 bits of 'nzcv'. */ + /* Map compare result from IR to ARM(nzcv) */ + /* + FP cmp result | IR | ARM(nzcv) + -------------------------------- + UN 0x45 0011 + LT 0x01 1000 + GT 0x00 0010 + EQ 0x40 0110 + */ + nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes); + + /* And update FPSCR accordingly */ + assign(oldFPSCR, IRExpr_Get(OFFB_FPSCR, Ity_I32)); + assign(newFPSCR, + binop(Iop_Or32, + binop(Iop_And32, mkexpr(oldFPSCR), mkU32(0x0FFFFFFF)), + binop(Iop_Shl32, mkexpr(nzcv), mkU8(28)))); + + putMiscReg32(OFFB_FPSCR, mkexpr(newFPSCR), condT); + + if (bZ) { + DIP("fcmpz%sd%s d%u\n", bN ? "e" : "", nCC(conq), dD); + } else { + DIP("fcmp%sd%s d%u, d%u\n", bN ? "e" : "", nCC(conq), dD, dM); + } + goto decode_success_vfp; + } + /* fall through */ + } + + /* --------------------- unary (D) --------------------- */ + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0)) + && BITS4(1,0,1,1) == INSN(11,8) + && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) { + UInt dD = INSN(15,12) | (INSN(22,22) << 4); + UInt dM = INSN(3,0) | (INSN(5,5) << 4); + UInt b16 = (insn28 >> 16) & 1; + UInt b7 = (insn28 >> 7) & 1; + /**/ if (b16 == 0 && b7 == 0) { + // FCPYD + putDReg(dD, getDReg(dM), condT); + DIP("fcpyd%s d%u, d%u\n", nCC(conq), dD, dM); + goto decode_success_vfp; + } + else if (b16 == 0 && b7 == 1) { + // FABSD + putDReg(dD, unop(Iop_AbsF64, getDReg(dM)), condT); + DIP("fabsd%s d%u, d%u\n", nCC(conq), dD, dM); + goto decode_success_vfp; + } + else if (b16 == 1 && b7 == 0) { + // FNEGD + putDReg(dD, unop(Iop_NegF64, getDReg(dM)), condT); + DIP("fnegd%s d%u, d%u\n", nCC(conq), dD, dM); + goto decode_success_vfp; + } + else if (b16 == 1 && b7 == 1) { + // FSQRTD + IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */ + putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT); + DIP("fsqrtd%s d%u, d%u\n", nCC(conq), dD, dM); + goto decode_success_vfp; + } + else + vassert(0); + + /* fall through */ + } + + /* ----------------- I <-> D conversions ----------------- */ + + // F{S,U}ITOD dD, fM + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(1,0,0,0) == (INSN(19,16) & BITS4(1,1,1,1)) + && BITS4(1,0,1,1) == INSN(11,8) + && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) { + UInt bM = (insn28 >> 5) & 1; + UInt fM = (INSN(3,0) << 1) | bM; + UInt dD = INSN(15,12) | (INSN(22,22) << 4); + UInt syned = (insn28 >> 7) & 1; + if (syned) { + // FSITOD + putDReg(dD, unop(Iop_I32StoF64, + unop(Iop_ReinterpF32asI32, getFReg(fM))), + condT); + DIP("fsitod%s d%u, s%u\n", nCC(conq), dD, fM); + } else { + // FUITOD + putDReg(dD, unop(Iop_I32UtoF64, + unop(Iop_ReinterpF32asI32, getFReg(fM))), + condT); + DIP("fuitod%s d%u, s%u\n", nCC(conq), dD, fM); + } + goto decode_success_vfp; + } + + // FTO{S,U}ID fD, dM + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0)) + && BITS4(1,0,1,1) == INSN(11,8) + && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) { + UInt bD = (insn28 >> 22) & 1; + UInt fD = (INSN(15,12) << 1) | bD; + UInt dM = INSN(3,0) | (INSN(5,5) << 4); + UInt bZ = (insn28 >> 7) & 1; + UInt syned = (insn28 >> 16) & 1; + IRTemp rmode = newTemp(Ity_I32); + assign(rmode, bZ ? mkU32(Irrm_ZERO) + : mkexpr(mk_get_IR_rounding_mode())); + if (syned) { + // FTOSID + putFReg(fD, unop(Iop_ReinterpI32asF32, + binop(Iop_F64toI32S, mkexpr(rmode), + getDReg(dM))), + condT); + DIP("ftosi%sd%s s%u, d%u\n", bZ ? "z" : "", + nCC(conq), fD, dM); + } else { + // FTOUID + putFReg(fD, unop(Iop_ReinterpI32asF32, + binop(Iop_F64toI32U, mkexpr(rmode), + getDReg(dM))), + condT); + DIP("ftoui%sd%s s%u, d%u\n", bZ ? "z" : "", + nCC(conq), fD, dM); + } + goto decode_success_vfp; + } + + /* ----------------------------------------------------------- */ + /* -- VFP instructions -- single precision -- */ + /* ----------------------------------------------------------- */ + + /* --------------------- fldms, fstms --------------------- */ + /* + 31 27 23 19 15 11 7 0 + P UDWL + C4-98, C5-26 1 FSTMD cond 1100 1x00 Rn Fd 1010 offset + C4-98, C5-28 2 FSTMDIA cond 1100 1x10 Rn Fd 1010 offset + C4-98, C5-30 3 FSTMDDB cond 1101 0x10 Rn Fd 1010 offset + + C4-40, C5-26 1 FLDMD cond 1100 1x01 Rn Fd 1010 offset + C4-40, C5-26 2 FLDMIAD cond 1100 1x11 Rn Fd 1010 offset + C4-40, C5-26 3 FLDMDBD cond 1101 0x11 Rn Fd 1010 offset + + Regs transferred: F(Fd:D) .. F(Fd:d + offset) + offset must not imply a reg > 15 + IA/DB: Rn is changed by (4 x # regs transferred) + + case coding: + 1 at-Rn (access at Rn) + 2 ia-Rn (access at Rn, then Rn += 4n) + 3 db-Rn (Rn -= 4n, then access at Rn) + */ + if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0)) + && INSN(11,8) == BITS4(1,0,1,0)) { + UInt bP = (insn28 >> 24) & 1; + UInt bU = (insn28 >> 23) & 1; + UInt bW = (insn28 >> 21) & 1; + UInt bL = (insn28 >> 20) & 1; + UInt bD = (insn28 >> 22) & 1; + UInt offset = (insn28 >> 0) & 0xFF; + UInt rN = INSN(19,16); + UInt fD = (INSN(15,12) << 1) | bD; + UInt nRegs = offset; + UInt summary = 0; + Int i; + + /**/ if (bP == 0 && bU == 1 && bW == 0) { + summary = 1; + } + else if (bP == 0 && bU == 1 && bW == 1) { + summary = 2; + } + else if (bP == 1 && bU == 0 && bW == 1) { + summary = 3; + } + else goto after_vfp_fldms_fstms; + + /* no writebacks to r15 allowed. No use of r15 in thumb mode. */ + if (rN == 15 && (summary == 2 || summary == 3 || isT)) + goto after_vfp_fldms_fstms; + + /* offset must specify at least one register */ + if (offset < 1) + goto after_vfp_fldms_fstms; + + /* can't transfer regs after S31 */ + if (fD + nRegs - 1 >= 32) + goto after_vfp_fldms_fstms; + + /* Now, we can't do a conditional load or store, since that very + likely will generate an exception. So we have to take a side + exit at this point if the condition is false. */ + if (condT != IRTemp_INVALID) { + if (isT) + mk_skip_over_T32_if_cond_is_false( condT ); + else + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + /* Ok, now we're unconditional. Do the load or store. */ + + /* get the old Rn value */ + IRTemp rnT = newTemp(Ity_I32); + assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN), + rN == 15)); + + /* make a new value for Rn, post-insn */ + IRTemp rnTnew = IRTemp_INVALID; + if (summary == 2 || summary == 3) { + rnTnew = newTemp(Ity_I32); + assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32, + mkexpr(rnT), + mkU32(4 * nRegs))); + } + + /* decide on the base transfer address */ + IRTemp taT = newTemp(Ity_I32); + assign(taT, summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT)); + + /* update Rn if necessary -- in case 3, we're moving it down, so + update before any memory reference, in order to keep Memcheck + and V's stack-extending logic (on linux) happy */ + if (summary == 3) { + if (isT) + putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID); + else + putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring); + } + + /* generate the transfers */ + for (i = 0; i < nRegs; i++) { + IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(4*i)); + if (bL) { + putFReg(fD + i, loadLE(Ity_F32, addr), IRTemp_INVALID); + } else { + storeLE(addr, getFReg(fD + i)); + } + } + + /* update Rn if necessary -- in case 2, we're moving it up, so + update after any memory reference, in order to keep Memcheck + and V's stack-extending logic (on linux) happy */ + if (summary == 2) { + if (isT) + putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID); + else + putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring); + } + + HChar* nm = bL==1 ? "ld" : "st"; + switch (summary) { + case 1: DIP("f%sms%s r%u, {s%u-s%u}\n", + nm, nCC(conq), rN, fD, fD + nRegs - 1); + break; + case 2: DIP("f%smias%s r%u!, {s%u-s%u}\n", + nm, nCC(conq), rN, fD, fD + nRegs - 1); + break; + case 3: DIP("f%smdbs%s r%u!, {s%u-s%u}\n", + nm, nCC(conq), rN, fD, fD + nRegs - 1); + break; + default: vassert(0); + } + + goto decode_success_vfp; + /* FIXME alignment constraints? */ + } + + after_vfp_fldms_fstms: + + /* --------------------- fmsr, fmrs --------------------- */ + if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0)) + && BITS4(1,0,1,0) == INSN(11,8) + && BITS4(0,0,0,0) == INSN(3,0) + && BITS4(0,0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) { + UInt rD = INSN(15,12); + UInt b7 = (insn28 >> 7) & 1; + UInt fN = (INSN(19,16) << 1) | b7; + UInt b20 = (insn28 >> 20) & 1; + if (rD == 15) { + /* fall through */ + /* Let's assume that no sane person would want to do + floating-point transfers to or from the program counter, + and simply decline to decode the instruction. The ARM ARM + doesn't seem to explicitly disallow this case, though. */ + } else { + if (b20) { + IRExpr* res = unop(Iop_ReinterpF32asI32, getFReg(fN)); + if (isT) + putIRegT(rD, res, condT); + else + putIRegA(rD, res, condT, Ijk_Boring); + DIP("fmrs%s r%u, s%u\n", nCC(conq), rD, fN); + } else { + putFReg(fN, unop(Iop_ReinterpI32asF32, + isT ? getIRegT(rD) : getIRegA(rD)), + condT); + DIP("fmsr%s s%u, r%u\n", nCC(conq), fN, rD); + } + goto decode_success_vfp; + } + /* fall through */ + } + + /* --------------------- f{ld,st}s --------------------- */ + // FLDS, FSTS + if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,1,0)) + && BITS4(1,0,1,0) == INSN(11,8)) { + UInt bD = (insn28 >> 22) & 1; + UInt fD = (INSN(15,12) << 1) | bD; + UInt rN = INSN(19,16); + UInt offset = (insn28 & 0xFF) << 2; + UInt bU = (insn28 >> 23) & 1; /* 1: +offset 0: -offset */ + UInt bL = (insn28 >> 20) & 1; /* 1: load 0: store */ + /* make unconditional */ + if (condT != IRTemp_INVALID) { + if (isT) + mk_skip_over_T32_if_cond_is_false( condT ); + else + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + IRTemp ea = newTemp(Ity_I32); + assign(ea, binop(bU ? Iop_Add32 : Iop_Sub32, + align4if(isT ? getIRegT(rN) : getIRegA(rN), + rN == 15), + mkU32(offset))); + if (bL) { + putFReg(fD, loadLE(Ity_F32,mkexpr(ea)), IRTemp_INVALID); + } else { + storeLE(mkexpr(ea), getFReg(fD)); + } + DIP("f%ss%s s%u, [r%u, %c#%u]\n", + bL ? "ld" : "st", nCC(conq), fD, rN, + bU ? '+' : '-', offset); + goto decode_success_vfp; + } + + /* --------------------- dp insns (F) --------------------- */ + if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0)) + && BITS4(1,0,1,0) == (INSN(11,8) & BITS4(1,1,1,0)) + && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(0,0,0,1))) { + UInt bM = (insn28 >> 5) & 1; + UInt bD = (insn28 >> 22) & 1; + UInt bN = (insn28 >> 7) & 1; + UInt fM = (INSN(3,0) << 1) | bM; /* argR */ + UInt fD = (INSN(15,12) << 1) | bD; /* dst/acc */ + UInt fN = (INSN(19,16) << 1) | bN; /* argL */ + UInt bP = (insn28 >> 23) & 1; + UInt bQ = (insn28 >> 21) & 1; + UInt bR = (insn28 >> 20) & 1; + UInt bS = (insn28 >> 6) & 1; + UInt opc = (bP << 3) | (bQ << 2) | (bR << 1) | bS; + IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */ + switch (opc) { + case BITS4(0,0,0,0): /* MAC: d + n * m */ + putFReg(fD, triop(Iop_AddF32, rm, + getFReg(fD), + triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))), + condT); + DIP("fmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + case BITS4(0,0,0,1): /* NMAC: d + -(n * m) */ + putFReg(fD, triop(Iop_AddF32, rm, + getFReg(fD), + unop(Iop_NegF32, + triop(Iop_MulF32, rm, getFReg(fN), + getFReg(fM)))), + condT); + DIP("fnmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + case BITS4(0,0,1,0): /* MSC: - d + n * m */ + putFReg(fD, triop(Iop_AddF32, rm, + unop(Iop_NegF32, getFReg(fD)), + triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))), + condT); + DIP("fmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + case BITS4(0,0,1,1): /* NMSC: - d + -(n * m) */ + putFReg(fD, triop(Iop_AddF32, rm, + unop(Iop_NegF32, getFReg(fD)), + unop(Iop_NegF32, + triop(Iop_MulF32, rm, + getFReg(fN), + getFReg(fM)))), + condT); + DIP("fnmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + case BITS4(0,1,0,0): /* MUL: n * m */ + putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)), + condT); + DIP("fmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + case BITS4(0,1,0,1): /* NMUL: - n * m */ + putFReg(fD, unop(Iop_NegF32, + triop(Iop_MulF32, rm, getFReg(fN), + getFReg(fM))), + condT); + DIP("fnmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + case BITS4(0,1,1,0): /* ADD: n + m */ + putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)), + condT); + DIP("fadds%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + case BITS4(0,1,1,1): /* SUB: n - m */ + putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)), + condT); + DIP("fsubs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + case BITS4(1,0,0,0): /* DIV: n / m */ + putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)), + condT); + DIP("fdivs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); + goto decode_success_vfp; + default: + break; + } + } + + /* --------------------- compares (S) --------------------- */ + /* 31 27 23 19 15 11 7 3 + 28 24 20 16 12 8 4 0 + FCMPS cond 1110 1D11 0100 Fd 1010 01M0 Fm + FCMPES cond 1110 1D11 0100 Fd 1010 11M0 Fm + FCMPZS cond 1110 1D11 0101 Fd 1010 0100 0000 + FCMPZED cond 1110 1D11 0101 Fd 1010 1100 0000 + Z N + + Z=0 Compare Fd:D vs Fm:M and set FPSCR 31:28 accordingly + Z=1 Compare Fd:D vs zero + + N=1 generates Invalid Operation exn if either arg is any kind of NaN + N=0 generates Invalid Operation exn if either arg is a signalling NaN + (Not that we pay any attention to N here) + */ + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0)) + && BITS4(1,0,1,0) == INSN(11,8) + && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) { + UInt bZ = (insn28 >> 16) & 1; + UInt bN = (insn28 >> 7) & 1; + UInt bD = (insn28 >> 22) & 1; + UInt bM = (insn28 >> 5) & 1; + UInt fD = (INSN(15,12) << 1) | bD; + UInt fM = (INSN(3,0) << 1) | bM; + if (bZ && (INSN(3,0) != 0 || (INSN(7,4) & 3) != 0)) { + /* does not decode; fall through */ + } else { + IRTemp argL = newTemp(Ity_F64); + IRTemp argR = newTemp(Ity_F64); + IRTemp irRes = newTemp(Ity_I32); + + assign(argL, unop(Iop_F32toF64, getFReg(fD))); + assign(argR, bZ ? IRExpr_Const(IRConst_F64i(0)) + : unop(Iop_F32toF64, getFReg(fM))); + assign(irRes, binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR))); + + IRTemp nzcv = IRTemp_INVALID; + IRTemp oldFPSCR = newTemp(Ity_I32); + IRTemp newFPSCR = newTemp(Ity_I32); + + /* This is where the fun starts. We have to convert 'irRes' + from an IR-convention return result (IRCmpF64Result) to an + ARM-encoded (N,Z,C,V) group. The final result is in the + bottom 4 bits of 'nzcv'. */ + /* Map compare result from IR to ARM(nzcv) */ + /* + FP cmp result | IR | ARM(nzcv) + -------------------------------- + UN 0x45 0011 + LT 0x01 1000 + GT 0x00 0010 + EQ 0x40 0110 + */ + nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes); + + /* And update FPSCR accordingly */ + assign(oldFPSCR, IRExpr_Get(OFFB_FPSCR, Ity_I32)); + assign(newFPSCR, + binop(Iop_Or32, + binop(Iop_And32, mkexpr(oldFPSCR), mkU32(0x0FFFFFFF)), + binop(Iop_Shl32, mkexpr(nzcv), mkU8(28)))); + + putMiscReg32(OFFB_FPSCR, mkexpr(newFPSCR), condT); + + if (bZ) { + DIP("fcmpz%ss%s s%u\n", bN ? "e" : "", nCC(conq), fD); + } else { + DIP("fcmp%ss%s s%u, s%u\n", bN ? "e" : "", + nCC(conq), fD, fM); + } + goto decode_success_vfp; + } + /* fall through */ + } + + /* --------------------- unary (S) --------------------- */ + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0)) + && BITS4(1,0,1,0) == INSN(11,8) + && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) { + UInt bD = (insn28 >> 22) & 1; + UInt bM = (insn28 >> 5) & 1; + UInt fD = (INSN(15,12) << 1) | bD; + UInt fM = (INSN(3,0) << 1) | bM; + UInt b16 = (insn28 >> 16) & 1; + UInt b7 = (insn28 >> 7) & 1; + /**/ if (b16 == 0 && b7 == 0) { + // FCPYS + putFReg(fD, getFReg(fM), condT); + DIP("fcpys%s s%u, s%u\n", nCC(conq), fD, fM); + goto decode_success_vfp; + } + else if (b16 == 0 && b7 == 1) { + // FABSS + putFReg(fD, unop(Iop_AbsF32, getFReg(fM)), condT); + DIP("fabss%s s%u, s%u\n", nCC(conq), fD, fM); + goto decode_success_vfp; + } + else if (b16 == 1 && b7 == 0) { + // FNEGS + putFReg(fD, unop(Iop_NegF32, getFReg(fM)), condT); + DIP("fnegs%s s%u, s%u\n", nCC(conq), fD, fM); + goto decode_success_vfp; + } + else if (b16 == 1 && b7 == 1) { + // FSQRTS + IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */ + putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT); + DIP("fsqrts%s s%u, s%u\n", nCC(conq), fD, fM); + goto decode_success_vfp; + } + else + vassert(0); + + /* fall through */ + } + + /* ----------------- I <-> S conversions ----------------- */ + + // F{S,U}ITOS fD, fM + /* These are more complex than FSITOD/FUITOD. In the D cases, a 32 + bit int will always fit within the 53 bit mantissa, so there's + no possibility of a loss of precision, but that's obviously not + the case here. Hence this case possibly requires rounding, and + so it drags in the current rounding mode. */ + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(1,0,0,0) == INSN(19,16) + && BITS4(1,0,1,0) == (INSN(11,8) & BITS4(1,1,1,0)) + && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) { + UInt bM = (insn28 >> 5) & 1; + UInt bD = (insn28 >> 22) & 1; + UInt fM = (INSN(3,0) << 1) | bM; + UInt fD = (INSN(15,12) << 1) | bD; + UInt syned = (insn28 >> 7) & 1; + IRTemp rmode = newTemp(Ity_I32); + assign(rmode, mkexpr(mk_get_IR_rounding_mode())); + if (syned) { + // FSITOS + putFReg(fD, binop(Iop_F64toF32, + mkexpr(rmode), + unop(Iop_I32StoF64, + unop(Iop_ReinterpF32asI32, getFReg(fM)))), + condT); + DIP("fsitos%s s%u, s%u\n", nCC(conq), fD, fM); + } else { + // FUITOS + putFReg(fD, binop(Iop_F64toF32, + mkexpr(rmode), + unop(Iop_I32UtoF64, + unop(Iop_ReinterpF32asI32, getFReg(fM)))), + condT); + DIP("fuitos%s s%u, s%u\n", nCC(conq), fD, fM); + } + goto decode_success_vfp; + } + + // FTO{S,U}IS fD, fM + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0)) + && BITS4(1,0,1,0) == INSN(11,8) + && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) { + UInt bM = (insn28 >> 5) & 1; + UInt bD = (insn28 >> 22) & 1; + UInt fD = (INSN(15,12) << 1) | bD; + UInt fM = (INSN(3,0) << 1) | bM; + UInt bZ = (insn28 >> 7) & 1; + UInt syned = (insn28 >> 16) & 1; + IRTemp rmode = newTemp(Ity_I32); + assign(rmode, bZ ? mkU32(Irrm_ZERO) + : mkexpr(mk_get_IR_rounding_mode())); + if (syned) { + // FTOSIS + putFReg(fD, unop(Iop_ReinterpI32asF32, + binop(Iop_F64toI32S, mkexpr(rmode), + unop(Iop_F32toF64, getFReg(fM)))), + condT); + DIP("ftosi%ss%s s%u, d%u\n", bZ ? "z" : "", + nCC(conq), fD, fM); + goto decode_success_vfp; + } else { + // FTOUIS + putFReg(fD, unop(Iop_ReinterpI32asF32, + binop(Iop_F64toI32U, mkexpr(rmode), + unop(Iop_F32toF64, getFReg(fM)))), + condT); + DIP("ftoui%ss%s s%u, d%u\n", bZ ? "z" : "", + nCC(conq), fD, fM); + goto decode_success_vfp; + } + } + + /* ----------------- S <-> D conversions ----------------- */ + + // FCVTDS + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,1,1,1) == INSN(19,16) + && BITS4(1,0,1,0) == INSN(11,8) + && BITS4(1,1,0,0) == (INSN(7,4) & BITS4(1,1,0,1))) { + UInt dD = INSN(15,12) | (INSN(22,22) << 4); + UInt bM = (insn28 >> 5) & 1; + UInt fM = (INSN(3,0) << 1) | bM; + putDReg(dD, unop(Iop_F32toF64, getFReg(fM)), condT); + DIP("fcvtds%s d%u, s%u\n", nCC(conq), dD, fM); + goto decode_success_vfp; + } + + // FCVTSD + if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,1,1,1) == INSN(19,16) + && BITS4(1,0,1,1) == INSN(11,8) + && BITS4(1,1,0,0) == (INSN(7,4) & BITS4(1,1,0,1))) { + UInt bD = (insn28 >> 22) & 1; + UInt fD = (INSN(15,12) << 1) | bD; + UInt dM = INSN(3,0) | (INSN(5,5) << 4); + IRTemp rmode = newTemp(Ity_I32); + assign(rmode, mkexpr(mk_get_IR_rounding_mode())); + putFReg(fD, binop(Iop_F64toF32, mkexpr(rmode), getDReg(dM)), + condT); + DIP("fcvtsd%s s%u, d%u\n", nCC(conq), fD, dM); + goto decode_success_vfp; + } + + /* FAILURE */ + return False; + + decode_success_vfp: + /* Check that any accepted insn really is a CP10 or CP11 insn, iow, + assert that we aren't accepting, in this fn, insns that actually + should be handled somewhere else. */ + vassert(INSN(11,9) == BITS3(1,0,1)); // 11:8 = 1010 or 1011 + return True; + +# undef INSN +} + + +/*------------------------------------------------------------*/ +/*--- Instructions in NV (never) space ---*/ +/*------------------------------------------------------------*/ + +/* ARM only */ +/* Translate a NV space instruction. If successful, returns True and + *dres may or may not be updated. If failure, returns False and + doesn't change *dres nor create any IR. + + Note that all NEON instructions (in ARM mode) are handled through + here, since they are all in NV space. +*/ +static Bool decode_NV_instruction ( /*MOD*/DisResult* dres, + VexArchInfo* archinfo, + UInt insn ) +{ +# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) +# define INSN_COND SLICE_UInt(insn, 31, 28) + + HChar dis_buf[128]; + + // Should only be called for NV instructions + vassert(BITS4(1,1,1,1) == INSN_COND); + + /* ------------------------ pld ------------------------ */ + if (BITS8(0,1,0,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1)) + && BITS4(1,1,1,1) == INSN(15,12)) { + UInt rN = INSN(19,16); + UInt imm12 = INSN(11,0); + UInt bU = INSN(23,23); + DIP("pld [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12); + return True; + } + + if (BITS8(0,1,1,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1)) + && BITS4(1,1,1,1) == INSN(15,12) + && 0 == INSN(4,4)) { + UInt rN = INSN(19,16); + UInt rM = INSN(3,0); + UInt imm5 = INSN(11,7); + UInt sh2 = INSN(6,5); + UInt bU = INSN(23,23); + if (rM != 15) { + IRExpr* eaE = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM, + sh2, imm5, dis_buf); + IRTemp eaT = newTemp(Ity_I32); + /* Bind eaE to a temp merely for debugging-vex purposes, so we + can check it's a plausible decoding. It will get removed + by iropt a little later on. */ + vassert(eaE); + assign(eaT, eaE); + DIP("pld %s\n", dis_buf); + return True; + } + /* fall through */ + } + + /* ------------------------ pli ------------------------ */ + if (BITS8(0,1,0,0, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1)) + && BITS4(1,1,1,1) == INSN(15,12)) { + UInt rN = INSN(19,16); + UInt imm12 = INSN(11,0); + UInt bU = INSN(23,23); + DIP("pli [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12); + return True; + } + + /* --------------------- Interworking branches --------------------- */ + + // BLX (1), viz, unconditional branch and link to R15+simm24 + // and set CPSR.T = 1, that is, switch to Thumb mode + if (INSN(31,25) == BITS7(1,1,1,1,1,0,1)) { + UInt bitH = INSN(24,24); + Int uimm24 = INSN(23,0); + Int simm24 = (((uimm24 << 8) >> 8) << 2) + (bitH << 1); + /* Now this is a bit tricky. Since we're decoding an ARM insn, + it is implies that CPSR.T == 0. Hence the current insn's + address is guaranteed to be of the form X--(30)--X00. So, no + need to mask any bits off it. But need to set the lowest bit + to 1 to denote we're in Thumb mode after this, since + guest_R15T has CPSR.T as the lowest bit. And we can't chase + into the call, so end the block at this point. */ + UInt dst = guest_R15_curr_instr_notENC + 8 + (simm24 | 1); + putIRegA( 14, mkU32(guest_R15_curr_instr_notENC + 4), + IRTemp_INVALID/*because AL*/, Ijk_Boring ); + irsb->next = mkU32(dst); + irsb->jumpkind = Ijk_Call; + dres->whatNext = Dis_StopHere; + DIP("blx 0x%x (and switch to Thumb mode)\n", dst - 1); + return True; + } + + /* ------------------- v7 barrier insns ------------------- */ + switch (insn) { + case 0xF57FF06F: /* ISB */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("ISB\n"); + return True; + case 0xF57FF04F: /* DSB */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("DSB\n"); + return True; + case 0xF57FF05F: /* DMB */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("DMB\n"); + return True; + default: + break; + } + + /* ------------------- NEON ------------------- */ + if (archinfo->hwcaps & VEX_HWCAPS_ARM_NEON) { + Bool ok_neon = decode_NEON_instruction( + dres, insn, IRTemp_INVALID/*unconditional*/, + False/*!isT*/ + ); + if (ok_neon) + return True; + } + + // unrecognised + return False; + +# undef INSN_COND +# undef INSN +} + + +/*------------------------------------------------------------*/ +/*--- Disassemble a single ARM instruction ---*/ +/*------------------------------------------------------------*/ + +/* Disassemble a single ARM instruction into IR. The instruction is + located in host memory at guest_instr, and has (decoded) guest IP + of guest_R15_curr_instr_notENC, which will have been set before the + call here. */ + +static +DisResult disInstr_ARM_WRK ( + Bool put_IP, + Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), + Bool resteerCisOk, + void* callback_opaque, + UChar* guest_instr, + VexArchInfo* archinfo, + VexAbiInfo* abiinfo + ) +{ + // A macro to fish bits out of 'insn'. +# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) +# define INSN_COND SLICE_UInt(insn, 31, 28) + + DisResult dres; + UInt insn; + //Bool allow_VFP = False; + //UInt hwcaps = archinfo->hwcaps; + IRTemp condT; /* :: Ity_I32 */ + UInt summary; + HChar dis_buf[128]; // big enough to hold LDMIA etc text + + /* What insn variants are we supporting today? */ + //allow_VFP = (0 != (hwcaps & VEX_HWCAPS_ARM_VFP)); + // etc etc + + /* Set result defaults. */ + dres.whatNext = Dis_Continue; + dres.len = 4; + dres.continueAt = 0; + + /* Set default actions for post-insn handling of writes to r15, if + required. */ + r15written = False; + r15guard = IRTemp_INVALID; /* unconditional */ + r15kind = Ijk_Boring; + + /* At least this is simple on ARM: insns are all 4 bytes long, and + 4-aligned. So just fish the whole thing out of memory right now + and have done. */ + insn = getUIntLittleEndianly( guest_instr ); + + if (0) vex_printf("insn: 0x%x\n", insn); + + DIP("\t(arm) 0x%x: ", (UInt)guest_R15_curr_instr_notENC); + + /* We may be asked to update the guest R15 before going further. */ + vassert(0 == (guest_R15_curr_instr_notENC & 3)); + if (put_IP) { + llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC) ); + } + + /* ----------------------------------------------------------- */ + + /* Spot "Special" instructions (see comment at top of file). */ + { + UChar* code = (UChar*)guest_instr; + /* Spot the 16-byte preamble: + + e1a0c1ec mov r12, r12, ROR #3 + e1a0c6ec mov r12, r12, ROR #13 + e1a0ceec mov r12, r12, ROR #29 + e1a0c9ec mov r12, r12, ROR #19 + */ + UInt word1 = 0xE1A0C1EC; + UInt word2 = 0xE1A0C6EC; + UInt word3 = 0xE1A0CEEC; + UInt word4 = 0xE1A0C9EC; + if (getUIntLittleEndianly(code+ 0) == word1 && + getUIntLittleEndianly(code+ 4) == word2 && + getUIntLittleEndianly(code+ 8) == word3 && + getUIntLittleEndianly(code+12) == word4) { + /* Got a "Special" instruction preamble. Which one is it? */ + if (getUIntLittleEndianly(code+16) == 0xE18AA00A + /* orr r10,r10,r10 */) { + /* R3 = client_request ( R4 ) */ + DIP("r3 = client_request ( %%r4 )\n"); + irsb->next = mkU32( guest_R15_curr_instr_notENC + 20 ); + irsb->jumpkind = Ijk_ClientReq; + dres.whatNext = Dis_StopHere; + goto decode_success; + } + else + if (getUIntLittleEndianly(code+16) == 0xE18BB00B + /* orr r11,r11,r11 */) { + /* R3 = guest_NRADDR */ + DIP("r3 = guest_NRADDR\n"); + dres.len = 20; + llPutIReg(3, IRExpr_Get( OFFB_NRADDR, Ity_I32 )); + goto decode_success; + } + else + if (getUIntLittleEndianly(code+16) == 0xE18CC00C + /* orr r12,r12,r12 */) { + /* branch-and-link-to-noredir R4 */ + DIP("branch-and-link-to-noredir r4\n"); + llPutIReg(14, mkU32( guest_R15_curr_instr_notENC + 20) ); + irsb->next = llGetIReg(4); + irsb->jumpkind = Ijk_NoRedir; + dres.whatNext = Dis_StopHere; + goto decode_success; + } + /* We don't know what it is. Set opc1/opc2 so decode_failure + can print the insn following the Special-insn preamble. */ + insn = getUIntLittleEndianly(code+16); + goto decode_failure; + /*NOTREACHED*/ + } + + } + + /* ----------------------------------------------------------- */ + + /* Main ARM instruction decoder starts here. */ + + /* Deal with the condition. Strategy is to merely generate a + condition temporary at this point (or IRTemp_INVALID, meaning + unconditional). We leave it to lower-level instruction decoders + to decide whether they can generate straight-line code, or + whether they must generate a side exit before the instruction. + condT :: Ity_I32 and is always either zero or one. */ + condT = IRTemp_INVALID; + switch ( (ARMCondcode)INSN_COND ) { + case ARMCondNV: { + // Illegal instruction prior to v5 (see ARM ARM A3-5), but + // some cases are acceptable + Bool ok = decode_NV_instruction(&dres, archinfo, insn); + if (ok) + goto decode_success; + else + goto decode_failure; + } + case ARMCondAL: // Always executed + break; + case ARMCondEQ: case ARMCondNE: case ARMCondHS: case ARMCondLO: + case ARMCondMI: case ARMCondPL: case ARMCondVS: case ARMCondVC: + case ARMCondHI: case ARMCondLS: case ARMCondGE: case ARMCondLT: + case ARMCondGT: case ARMCondLE: + condT = newTemp(Ity_I32); + assign( condT, mk_armg_calculate_condition( INSN_COND )); + break; + } + + /* ----------------------------------------------------------- */ + /* -- ARMv5 integer instructions -- */ + /* ----------------------------------------------------------- */ + + /* ---------------- Data processing ops ------------------- */ + + if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0)) + && !(INSN(25,25) == 0 && INSN(7,7) == 1 && INSN(4,4) == 1)) { + IRTemp shop = IRTemp_INVALID; /* shifter operand */ + IRTemp shco = IRTemp_INVALID; /* shifter carry out */ + UInt rD = (insn >> 12) & 0xF; /* 15:12 */ + UInt rN = (insn >> 16) & 0xF; /* 19:16 */ + UInt bitS = (insn >> 20) & 1; /* 20:20 */ + IRTemp rNt = IRTemp_INVALID; + IRTemp res = IRTemp_INVALID; + IRTemp oldV = IRTemp_INVALID; + IRTemp oldC = IRTemp_INVALID; + HChar* name = NULL; + IROp op = Iop_INVALID; + Bool ok; + + switch (INSN(24,21)) { + + /* --------- ADD, SUB, AND, OR --------- */ + case BITS4(0,1,0,0): /* ADD: Rd = Rn + shifter_operand */ + name = "add"; op = Iop_Add32; goto rd_eq_rn_op_SO; + case BITS4(0,0,1,0): /* SUB: Rd = Rn - shifter_operand */ + name = "sub"; op = Iop_Sub32; goto rd_eq_rn_op_SO; + case BITS4(0,0,1,1): /* RSB: Rd = shifter_operand - Rn */ + name = "rsb"; op = Iop_Sub32; goto rd_eq_rn_op_SO; + case BITS4(0,0,0,0): /* AND: Rd = Rn & shifter_operand */ + name = "and"; op = Iop_And32; goto rd_eq_rn_op_SO; + case BITS4(1,1,0,0): /* OR: Rd = Rn | shifter_operand */ + name = "orr"; op = Iop_Or32; goto rd_eq_rn_op_SO; + case BITS4(0,0,0,1): /* EOR: Rd = Rn ^ shifter_operand */ + name = "eor"; op = Iop_Xor32; goto rd_eq_rn_op_SO; + case BITS4(1,1,1,0): /* BIC: Rd = Rn & ~shifter_operand */ + name = "bic"; op = Iop_And32; goto rd_eq_rn_op_SO; + rd_eq_rn_op_SO: { + Bool isRSB = False; + Bool isBIC = False; + switch (INSN(24,21)) { + case BITS4(0,0,1,1): + vassert(op == Iop_Sub32); isRSB = True; break; + case BITS4(1,1,1,0): + vassert(op == Iop_And32); isBIC = True; break; + default: + break; + } + rNt = newTemp(Ity_I32); + assign(rNt, getIRegA(rN)); + ok = mk_shifter_operand( + INSN(25,25), INSN(11,0), + &shop, bitS ? &shco : NULL, dis_buf + ); + if (!ok) + break; + res = newTemp(Ity_I32); + // compute the main result + if (isRSB) { + // reverse-subtract: shifter_operand - Rn + vassert(op == Iop_Sub32); + assign(res, binop(op, mkexpr(shop), mkexpr(rNt)) ); + } else if (isBIC) { + // andn: shifter_operand & ~Rn + vassert(op == Iop_And32); + assign(res, binop(op, mkexpr(rNt), + unop(Iop_Not32, mkexpr(shop))) ); + } else { + // normal: Rn op shifter_operand + assign(res, binop(op, mkexpr(rNt), mkexpr(shop)) ); + } + // but don't commit it until after we've finished + // all necessary reads from the guest state + if (bitS + && (op == Iop_And32 || op == Iop_Or32 || op == Iop_Xor32)) { + oldV = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + } + // can't safely read guest state after here + // now safe to put the main result + putIRegA( rD, mkexpr(res), condT, Ijk_Boring ); + // XXXX!! not safe to read any guest state after + // this point (I think the code below doesn't do that). + if (!bitS) + vassert(shco == IRTemp_INVALID); + /* Update the flags thunk if necessary */ + if (bitS) { + vassert(shco != IRTemp_INVALID); + switch (op) { + case Iop_Add32: + setFlags_D1_D2( ARMG_CC_OP_ADD, rNt, shop, condT ); + break; + case Iop_Sub32: + if (isRSB) { + setFlags_D1_D2( ARMG_CC_OP_SUB, shop, rNt, condT ); + } else { + setFlags_D1_D2( ARMG_CC_OP_SUB, rNt, shop, condT ); + } + break; + case Iop_And32: /* BIC and AND set the flags the same */ + case Iop_Or32: + case Iop_Xor32: + // oldV has been read just above + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, + res, shco, oldV, condT ); + break; + default: + vassert(0); + } + } + DIP("%s%s%s r%u, r%u, %s\n", + name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf ); + goto decode_success; + } + + /* --------- MOV, MVN --------- */ + case BITS4(1,1,0,1): /* MOV: Rd = shifter_operand */ + case BITS4(1,1,1,1): { /* MVN: Rd = not(shifter_operand) */ + Bool isMVN = INSN(24,21) == BITS4(1,1,1,1); + if (rN != 0) + break; /* rN must be zero */ + ok = mk_shifter_operand( + INSN(25,25), INSN(11,0), + &shop, bitS ? &shco : NULL, dis_buf + ); + if (!ok) + break; + res = newTemp(Ity_I32); + assign( res, isMVN ? unop(Iop_Not32, mkexpr(shop)) + : mkexpr(shop) ); + if (bitS) { + vassert(shco != IRTemp_INVALID); + oldV = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + } else { + vassert(shco == IRTemp_INVALID); + } + // can't safely read guest state after here + putIRegA( rD, mkexpr(res), condT, Ijk_Boring ); + /* Update the flags thunk if necessary */ + if (bitS) { + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, + res, shco, oldV, condT ); + } + DIP("%s%s%s r%u, %s\n", + isMVN ? "mvn" : "mov", + nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf ); + goto decode_success; + } + + /* --------- CMP --------- */ + case BITS4(1,0,1,0): /* CMP: (void) Rn - shifter_operand */ + case BITS4(1,0,1,1): { /* CMN: (void) Rn + shifter_operand */ + Bool isCMN = INSN(24,21) == BITS4(1,0,1,1); + if (rD != 0) + break; /* rD must be zero */ + if (bitS == 0) + break; /* if S (bit 20) is not set, it's not CMP/CMN */ + rNt = newTemp(Ity_I32); + assign(rNt, getIRegA(rN)); + ok = mk_shifter_operand( + INSN(25,25), INSN(11,0), + &shop, NULL, dis_buf + ); + if (!ok) + break; + // can't safely read guest state after here + /* Update the flags thunk. */ + setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, + rNt, shop, condT ); + DIP("%s%s r%u, %s\n", + isCMN ? "cmn" : "cmp", + nCC(INSN_COND), rN, dis_buf ); + goto decode_success; + } + + /* --------- TST --------- */ + case BITS4(1,0,0,0): /* TST: (void) Rn & shifter_operand */ + case BITS4(1,0,0,1): { /* TEQ: (void) Rn ^ shifter_operand */ + Bool isTEQ = INSN(24,21) == BITS4(1,0,0,1); + if (rD != 0) + break; /* rD must be zero */ + if (bitS == 0) + break; /* if S (bit 20) is not set, it's not TST/TEQ */ + rNt = newTemp(Ity_I32); + assign(rNt, getIRegA(rN)); + ok = mk_shifter_operand( + INSN(25,25), INSN(11,0), + &shop, &shco, dis_buf + ); + if (!ok) + break; + /* Update the flags thunk. */ + res = newTemp(Ity_I32); + assign( res, binop(isTEQ ? Iop_Xor32 : Iop_And32, + mkexpr(rNt), mkexpr(shop)) ); + oldV = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + // can't safely read guest state after here + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, + res, shco, oldV, condT ); + DIP("%s%s r%u, %s\n", + isTEQ ? "teq" : "tst", + nCC(INSN_COND), rN, dis_buf ); + goto decode_success; + } + + /* --------- ADC, SBC, RSC --------- */ + case BITS4(0,1,0,1): /* ADC: Rd = Rn + shifter_operand + oldC */ + name = "adc"; goto rd_eq_rn_op_SO_op_oldC; + case BITS4(0,1,1,0): /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */ + name = "sbc"; goto rd_eq_rn_op_SO_op_oldC; + case BITS4(0,1,1,1): /* RSC: Rd = shifter_operand - Rn - (oldC ^ 1) */ + name = "rsc"; goto rd_eq_rn_op_SO_op_oldC; + rd_eq_rn_op_SO_op_oldC: { + // FIXME: shco isn't used for anything. Get rid of it. + rNt = newTemp(Ity_I32); + assign(rNt, getIRegA(rN)); + ok = mk_shifter_operand( + INSN(25,25), INSN(11,0), + &shop, bitS ? &shco : NULL, dis_buf + ); + if (!ok) + break; + oldC = newTemp(Ity_I32); + assign( oldC, mk_armg_calculate_flag_c() ); + res = newTemp(Ity_I32); + // compute the main result + switch (INSN(24,21)) { + case BITS4(0,1,0,1): /* ADC */ + assign(res, + binop(Iop_Add32, + binop(Iop_Add32, mkexpr(rNt), mkexpr(shop)), + mkexpr(oldC) )); + break; + case BITS4(0,1,1,0): /* SBC */ + assign(res, + binop(Iop_Sub32, + binop(Iop_Sub32, mkexpr(rNt), mkexpr(shop)), + binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) )); + break; + case BITS4(0,1,1,1): /* RSC */ + assign(res, + binop(Iop_Sub32, + binop(Iop_Sub32, mkexpr(shop), mkexpr(rNt)), + binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) )); + break; + default: + vassert(0); + } + // but don't commit it until after we've finished + // all necessary reads from the guest state + // now safe to put the main result + putIRegA( rD, mkexpr(res), condT, Ijk_Boring ); + // XXXX!! not safe to read any guest state after + // this point (I think the code below doesn't do that). + if (!bitS) + vassert(shco == IRTemp_INVALID); + /* Update the flags thunk if necessary */ + if (bitS) { + vassert(shco != IRTemp_INVALID); + switch (INSN(24,21)) { + case BITS4(0,1,0,1): /* ADC */ + setFlags_D1_D2_ND( ARMG_CC_OP_ADC, + rNt, shop, oldC, condT ); + break; + case BITS4(0,1,1,0): /* SBC */ + setFlags_D1_D2_ND( ARMG_CC_OP_SBB, + rNt, shop, oldC, condT ); + break; + case BITS4(0,1,1,1): /* RSC */ + setFlags_D1_D2_ND( ARMG_CC_OP_SBB, + shop, rNt, oldC, condT ); + break; + default: + vassert(0); + } + } + DIP("%s%s%s r%u, r%u, %s\n", + name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf ); + goto decode_success; + } + + /* --------- ??? --------- */ + default: + break; + } + } /* if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0)) */ + + /* --------------------- Load/store (ubyte & word) -------- */ + // LDR STR LDRB STRB + /* 31 27 23 19 15 11 6 4 3 # highest bit + 28 24 20 16 12 + A5-20 1 | 16 cond 0101 UB0L Rn Rd imm12 + A5-22 1 | 32 cond 0111 UBOL Rn Rd imm5 sh2 0 Rm + A5-24 2 | 16 cond 0101 UB1L Rn Rd imm12 + A5-26 2 | 32 cond 0111 UB1L Rn Rd imm5 sh2 0 Rm + A5-28 3 | 16 cond 0100 UB0L Rn Rd imm12 + A5-32 3 | 32 cond 0110 UB0L Rn Rd imm5 sh2 0 Rm + */ + /* case coding: + 1 at-ea (access at ea) + 2 at-ea-then-upd (access at ea, then Rn = ea) + 3 at-Rn-then-upd (access at Rn, then Rn = ea) + ea coding + 16 Rn +/- imm12 + 32 Rn +/- Rm sh2 imm5 + */ + /* Quickly skip over all of this for hopefully most instructions */ + if ((INSN(27,24) & BITS4(1,1,0,0)) != BITS4(0,1,0,0)) + goto after_load_store_ubyte_or_word; + + summary = 0; + + /**/ if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 0) { + summary = 1 | 16; + } + else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 0 + && INSN(4,4) == 0) { + summary = 1 | 32; + } + else if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 1) { + summary = 2 | 16; + } + else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 1 + && INSN(4,4) == 0) { + summary = 2 | 32; + } + else if (INSN(27,24) == BITS4(0,1,0,0) && INSN(21,21) == 0) { + summary = 3 | 16; + } + else if (INSN(27,24) == BITS4(0,1,1,0) && INSN(21,21) == 0 + && INSN(4,4) == 0) { + summary = 3 | 32; + } + else goto after_load_store_ubyte_or_word; + + { UInt rN = (insn >> 16) & 0xF; /* 19:16 */ + UInt rD = (insn >> 12) & 0xF; /* 15:12 */ + UInt rM = (insn >> 0) & 0xF; /* 3:0 */ + UInt bU = (insn >> 23) & 1; /* 23 */ + UInt bB = (insn >> 22) & 1; /* 22 */ + UInt bL = (insn >> 20) & 1; /* 20 */ + UInt imm12 = (insn >> 0) & 0xFFF; /* 11:0 */ + UInt imm5 = (insn >> 7) & 0x1F; /* 11:7 */ + UInt sh2 = (insn >> 5) & 3; /* 6:5 */ + + /* Skip some invalid cases, which would lead to two competing + updates to the same register, or which are otherwise + disallowed by the spec. */ + switch (summary) { + case 1 | 16: + break; + case 1 | 32: + if (rM == 15) goto after_load_store_ubyte_or_word; + break; + case 2 | 16: case 3 | 16: + if (rN == 15) goto after_load_store_ubyte_or_word; + if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word; + break; + case 2 | 32: case 3 | 32: + if (rM == 15) goto after_load_store_ubyte_or_word; + if (rN == 15) goto after_load_store_ubyte_or_word; + if (rN == rM) goto after_load_store_ubyte_or_word; + if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word; + break; + default: + vassert(0); + } + + /* Now, we can't do a conditional load or store, since that very + likely will generate an exception. So we have to take a side + exit at this point if the condition is false. */ + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + /* Ok, now we're unconditional. Do the load or store. */ + + /* compute the effective address. Bind it to a tmp since we + may need to use it twice. */ + IRExpr* eaE = NULL; + switch (summary & 0xF0) { + case 16: + eaE = mk_EA_reg_plusminus_imm12( rN, bU, imm12, dis_buf ); + break; + case 32: + eaE = mk_EA_reg_plusminus_shifted_reg( rN, bU, rM, sh2, imm5, + dis_buf ); + break; + } + vassert(eaE); + IRTemp eaT = newTemp(Ity_I32); + assign(eaT, eaE); + + /* get the old Rn value */ + IRTemp rnT = newTemp(Ity_I32); + assign(rnT, getIRegA(rN)); + + /* decide on the transfer address */ + IRTemp taT = IRTemp_INVALID; + switch (summary & 0x0F) { + case 1: case 2: taT = eaT; break; + case 3: taT = rnT; break; + } + vassert(taT != IRTemp_INVALID); + + if (bL == 0) { + /* Store. If necessary, update the base register before the + store itself, so that the common idiom of "str rX, [sp, + #-4]!" (store rX at sp-4, then do new sp = sp-4, a.k.a "push + rX") doesn't cause Memcheck to complain that the access is + below the stack pointer. Also, not updating sp before the + store confuses Valgrind's dynamic stack-extending logic. So + do it before the store. Hence we need to snarf the store + data before doing the basereg update. */ + + /* get hold of the data to be stored */ + IRTemp rDt = newTemp(Ity_I32); + assign(rDt, getIRegA(rD)); + + /* Update Rn if necessary. */ + switch (summary & 0x0F) { + case 2: case 3: + putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring ); + break; + } + + /* generate the transfer */ + if (bB == 0) { // word store + storeLE( mkexpr(taT), mkexpr(rDt) ); + } else { // byte store + vassert(bB == 1); + storeLE( mkexpr(taT), unop(Iop_32to8, mkexpr(rDt)) ); + } + + } else { + /* Load */ + vassert(bL == 1); + + /* generate the transfer */ + if (bB == 0) { // word load + putIRegA( rD, loadLE(Ity_I32, mkexpr(taT)), + IRTemp_INVALID, Ijk_Boring ); + } else { // byte load + vassert(bB == 1); + putIRegA( rD, unop(Iop_8Uto32, loadLE(Ity_I8, mkexpr(taT))), + IRTemp_INVALID, Ijk_Boring ); + } + + /* Update Rn if necessary. */ + switch (summary & 0x0F) { + case 2: case 3: + // should be assured by logic above: + if (bL == 1) + vassert(rD != rN); /* since we just wrote rD */ + putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring ); + break; + } + } + + switch (summary & 0x0F) { + case 1: DIP("%sr%s%s r%u, %s\n", + bL == 0 ? "st" : "ld", + bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf); + break; + case 2: DIP("%sr%s%s r%u, %s! (at-EA-then-Rn=EA)\n", + bL == 0 ? "st" : "ld", + bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf); + break; + case 3: DIP("%sr%s%s r%u, %s! (at-Rn-then-Rn=EA)\n", + bL == 0 ? "st" : "ld", + bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf); + break; + default: vassert(0); + } + + /* XXX deal with alignment constraints */ + + goto decode_success; + + /* Complications: + + For all loads: if the Amode specifies base register + writeback, and the same register is specified for Rd and Rn, + the results are UNPREDICTABLE. + + For all loads and stores: if R15 is written, branch to + that address afterwards. + + STRB: straightforward + LDRB: loaded data is zero extended + STR: lowest 2 bits of address are ignored + LDR: if the lowest 2 bits of the address are nonzero + then the loaded value is rotated right by 8 * the lowest 2 bits + */ + } + + after_load_store_ubyte_or_word: + + /* --------------------- Load/store (sbyte & hword) -------- */ + // LDRH LDRSH STRH LDRSB + /* 31 27 23 19 15 11 7 3 # highest bit + 28 24 20 16 12 8 4 0 + A5-36 1 | 16 cond 0001 U10L Rn Rd im4h 1SH1 im4l + A5-38 1 | 32 cond 0001 U00L Rn Rd 0000 1SH1 Rm + A5-40 2 | 16 cond 0001 U11L Rn Rd im4h 1SH1 im4l + A5-42 2 | 32 cond 0001 U01L Rn Rd 0000 1SH1 Rm + A5-44 3 | 16 cond 0000 U10L Rn Rd im4h 1SH1 im4l + A5-46 3 | 32 cond 0000 U00L Rn Rd 0000 1SH1 Rm + */ + /* case coding: + 1 at-ea (access at ea) + 2 at-ea-then-upd (access at ea, then Rn = ea) + 3 at-Rn-then-upd (access at Rn, then Rn = ea) + ea coding + 16 Rn +/- imm8 + 32 Rn +/- Rm + */ + /* Quickly skip over all of this for hopefully most instructions */ + if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0)) + goto after_load_store_sbyte_or_hword; + + /* Check the "1SH1" thing. */ + if ((INSN(7,4) & BITS4(1,0,0,1)) != BITS4(1,0,0,1)) + goto after_load_store_sbyte_or_hword; + + summary = 0; + + /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,0)) { + summary = 1 | 16; + } + else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,0)) { + summary = 1 | 32; + } + else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,1)) { + summary = 2 | 16; + } + else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,1)) { + summary = 2 | 32; + } + else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(1,0)) { + summary = 3 | 16; + } + else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(0,0)) { + summary = 3 | 32; + } + else goto after_load_store_sbyte_or_hword; + + { UInt rN = (insn >> 16) & 0xF; /* 19:16 */ + UInt rD = (insn >> 12) & 0xF; /* 15:12 */ + UInt rM = (insn >> 0) & 0xF; /* 3:0 */ + UInt bU = (insn >> 23) & 1; /* 23 U=1 offset+, U=0 offset- */ + UInt bL = (insn >> 20) & 1; /* 20 L=1 load, L=0 store */ + UInt bH = (insn >> 5) & 1; /* H=1 halfword, H=0 byte */ + UInt bS = (insn >> 6) & 1; /* S=1 signed, S=0 unsigned */ + UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */ + + /* Skip combinations that are either meaningless or already + handled by main word-or-unsigned-byte load-store + instructions. */ + if (bS == 0 && bH == 0) /* "unsigned byte" */ + goto after_load_store_sbyte_or_hword; + if (bS == 1 && bL == 0) /* "signed store" */ + goto after_load_store_sbyte_or_hword; + + /* Require 11:8 == 0 for Rn +/- Rm cases */ + if ((summary & 32) != 0 && (imm8 & 0xF0) != 0) + goto after_load_store_sbyte_or_hword; + + /* Skip some invalid cases, which would lead to two competing + updates to the same register, or which are otherwise + disallowed by the spec. */ + switch (summary) { + case 1 | 16: + break; + case 1 | 32: + if (rM == 15) goto after_load_store_sbyte_or_hword; + break; + case 2 | 16: case 3 | 16: + if (rN == 15) goto after_load_store_sbyte_or_hword; + if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword; + break; + case 2 | 32: case 3 | 32: + if (rM == 15) goto after_load_store_sbyte_or_hword; + if (rN == 15) goto after_load_store_sbyte_or_hword; + if (rN == rM) goto after_load_store_sbyte_or_hword; + if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword; + break; + default: + vassert(0); + } + + /* Now, we can't do a conditional load or store, since that very + likely will generate an exception. So we have to take a side + exit at this point if the condition is false. */ + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + /* Ok, now we're unconditional. Do the load or store. */ + + /* compute the effective address. Bind it to a tmp since we + may need to use it twice. */ + IRExpr* eaE = NULL; + switch (summary & 0xF0) { + case 16: + eaE = mk_EA_reg_plusminus_imm8( rN, bU, imm8, dis_buf ); + break; + case 32: + eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf ); + break; + } + vassert(eaE); + IRTemp eaT = newTemp(Ity_I32); + assign(eaT, eaE); + + /* get the old Rn value */ + IRTemp rnT = newTemp(Ity_I32); + assign(rnT, getIRegA(rN)); + + /* decide on the transfer address */ + IRTemp taT = IRTemp_INVALID; + switch (summary & 0x0F) { + case 1: case 2: taT = eaT; break; + case 3: taT = rnT; break; + } + vassert(taT != IRTemp_INVALID); + + /* halfword store H 1 L 0 S 0 + uhalf load H 1 L 1 S 0 + shalf load H 1 L 1 S 1 + sbyte load H 0 L 1 S 1 + */ + HChar* name = NULL; + /* generate the transfer */ + /**/ if (bH == 1 && bL == 0 && bS == 0) { // halfword store + storeLE( mkexpr(taT), unop(Iop_32to16, getIRegA(rD)) ); + name = "strh"; + } + else if (bH == 1 && bL == 1 && bS == 0) { // uhalf load + putIRegA( rD, unop(Iop_16Uto32, loadLE(Ity_I16, mkexpr(taT))), + IRTemp_INVALID, Ijk_Boring ); + name = "ldrh"; + } + else if (bH == 1 && bL == 1 && bS == 1) { // shalf load + putIRegA( rD, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(taT))), + IRTemp_INVALID, Ijk_Boring ); + name = "ldrsh"; + } + else if (bH == 0 && bL == 1 && bS == 1) { // sbyte load + putIRegA( rD, unop(Iop_8Sto32, loadLE(Ity_I8, mkexpr(taT))), + IRTemp_INVALID, Ijk_Boring ); + name = "ldrsb"; + } + else + vassert(0); // should be assured by logic above + + /* Update Rn if necessary. */ + switch (summary & 0x0F) { + case 2: case 3: + // should be assured by logic above: + if (bL == 1) + vassert(rD != rN); /* since we just wrote rD */ + putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring ); + break; + } + + switch (summary & 0x0F) { + case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf); + break; + case 2: DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n", + name, nCC(INSN_COND), rD, dis_buf); + break; + case 3: DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n", + name, nCC(INSN_COND), rD, dis_buf); + break; + default: vassert(0); + } + + /* XXX deal with alignment constraints */ + + goto decode_success; + + /* Complications: + + For all loads: if the Amode specifies base register + writeback, and the same register is specified for Rd and Rn, + the results are UNPREDICTABLE. + + For all loads and stores: if R15 is written, branch to + that address afterwards. + + Misaligned halfword stores => Unpredictable + Misaligned halfword loads => Unpredictable + */ + } + + after_load_store_sbyte_or_hword: + + /* --------------------- Load/store multiple -------------- */ + // LD/STMIA LD/STMIB LD/STMDA LD/STMDB + // Remarkably complex and difficult to get right + // match 27:20 as 100XX0WL + if (BITS8(1,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))) { + // A5-50 LD/STMIA cond 1000 10WL Rn RegList + // A5-51 LD/STMIB cond 1001 10WL Rn RegList + // A5-53 LD/STMDA cond 1000 00WL Rn RegList + // A5-53 LD/STMDB cond 1001 00WL Rn RegList + // 28 24 20 16 0 + + UInt bINC = (insn >> 23) & 1; + UInt bBEFORE = (insn >> 24) & 1; + + UInt bL = (insn >> 20) & 1; /* load=1, store=0 */ + UInt bW = (insn >> 21) & 1; /* Rn wback=1, no wback=0 */ + UInt rN = (insn >> 16) & 0xF; + UInt regList = insn & 0xFFFF; + /* Skip some invalid cases, which would lead to two competing + updates to the same register, or which are otherwise + disallowed by the spec. Note the test above has required + that S == 0, since that looks like a kernel-mode only thing. + Done by forcing the real pattern, viz 100XXSWL to actually be + 100XX0WL. */ + if (rN == 15) goto after_load_store_multiple; + // reglist can't be empty + if (regList == 0) goto after_load_store_multiple; + // if requested to writeback Rn, and this is a load instruction, + // then Rn can't appear in RegList, since we'd have two competing + // new values for Rn. We do however accept this case for store + // instructions. + if (bW == 1 && bL == 1 && ((1 << rN) & regList) > 0) + goto after_load_store_multiple; + + /* Now, we can't do a conditional load or store, since that very + likely will generate an exception. So we have to take a side + exit at this point if the condition is false. */ + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + + /* Ok, now we're unconditional. Generate the IR. */ + mk_ldm_stm( True/*arm*/, rN, bINC, bBEFORE, bW, bL, regList ); + + DIP("%sm%c%c%s r%u%s, {0x%04x}\n", + bL == 1 ? "ld" : "st", bINC ? 'i' : 'd', bBEFORE ? 'b' : 'a', + nCC(INSN_COND), + rN, bW ? "!" : "", regList); + + goto decode_success; + } + + after_load_store_multiple: + + /* --------------------- Control flow --------------------- */ + // B, BL (Branch, or Branch-and-Link, to immediate offset) + // + if (BITS8(1,0,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))) { + UInt link = (insn >> 24) & 1; + UInt uimm24 = insn & ((1<<24)-1); + Int simm24 = (Int)uimm24; + UInt dst = guest_R15_curr_instr_notENC + 8 + + (((simm24 << 8) >> 8) << 2); + IRJumpKind jk = link ? Ijk_Call : Ijk_Boring; + if (link) { + putIRegA(14, mkU32(guest_R15_curr_instr_notENC + 4), + condT, Ijk_Boring); + } + if (condT == IRTemp_INVALID) { + /* unconditional transfer to 'dst'. See if we can simply + continue tracing at the destination. */ + if (resteerOkFn( callback_opaque, (Addr64)dst )) { + /* yes */ + dres.whatNext = Dis_ResteerU; + dres.continueAt = (Addr64)dst; + } else { + /* no; terminate the SB at this point. */ + irsb->next = mkU32(dst); + irsb->jumpkind = jk; + dres.whatNext = Dis_StopHere; + } + DIP("b%s 0x%x\n", link ? "l" : "", dst); + } else { + /* conditional transfer to 'dst' */ + HChar* comment = ""; + + /* First see if we can do some speculative chasing into one + arm or the other. Be conservative and only chase if + !link, that is, this is a normal conditional branch to a + known destination. */ + if (!link + && resteerCisOk + && vex_control.guest_chase_cond + && dst < guest_R15_curr_instr_notENC + && resteerOkFn( callback_opaque, (Addr64)(Addr32)dst) ) { + /* Speculation: assume this backward branch is taken. So + we need to emit a side-exit to the insn following this + one, on the negation of the condition, and continue at + the branch target address (dst). */ + stmt( IRStmt_Exit( unop(Iop_Not1, + unop(Iop_32to1, mkexpr(condT))), + Ijk_Boring, + IRConst_U32(guest_R15_curr_instr_notENC+4) )); + dres.whatNext = Dis_ResteerC; + dres.continueAt = (Addr64)(Addr32)dst; + comment = "(assumed taken)"; + } + else + if (!link + && resteerCisOk + && vex_control.guest_chase_cond + && dst >= guest_R15_curr_instr_notENC + && resteerOkFn( callback_opaque, + (Addr64)(Addr32) + (guest_R15_curr_instr_notENC+4)) ) { + /* Speculation: assume this forward branch is not taken. + So we need to emit a side-exit to dst (the dest) and + continue disassembling at the insn immediately + following this one. */ + stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(condT)), + Ijk_Boring, + IRConst_U32(dst) )); + dres.whatNext = Dis_ResteerC; + dres.continueAt = (Addr64)(Addr32) + (guest_R15_curr_instr_notENC+4); + comment = "(assumed not taken)"; + } + else { + /* Conservative default translation - end the block at + this point. */ + stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(condT)), + jk, IRConst_U32(dst) )); + irsb->next = mkU32(guest_R15_curr_instr_notENC + 4); + irsb->jumpkind = jk; + dres.whatNext = Dis_StopHere; + } + DIP("b%s%s 0x%x %s\n", link ? "l" : "", nCC(INSN_COND), + dst, comment); + } + goto decode_success; + } + + // B, BL (Branch, or Branch-and-Link, to a register) + // NB: interworking branch + if (INSN(27,20) == BITS8(0,0,0,1,0,0,1,0) + && INSN(19,12) == BITS8(1,1,1,1,1,1,1,1) + && (INSN(11,4) == BITS8(1,1,1,1,0,0,1,1) + || INSN(11,4) == BITS8(1,1,1,1,0,0,0,1))) { + IRExpr* dst; + UInt link = (INSN(11,4) >> 1) & 1; + UInt rM = INSN(3,0); + // we don't decode the case (link && rM == 15), as that's + // Unpredictable. + if (!(link && rM == 15)) { + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + } + // rM contains an interworking address exactly as we require + // (with continuation CPSR.T in bit 0), so we can use it + // as-is, with no masking. + dst = getIRegA(rM); + if (link) { + putIRegA( 14, mkU32(guest_R15_curr_instr_notENC + 4), + IRTemp_INVALID/*because AL*/, Ijk_Boring ); + } + irsb->next = dst; + irsb->jumpkind = link ? Ijk_Call + : (rM == 14 ? Ijk_Ret : Ijk_Boring); + dres.whatNext = Dis_StopHere; + if (condT == IRTemp_INVALID) { + DIP("b%sx r%u\n", link ? "l" : "", rM); + } else { + DIP("b%sx%s r%u\n", link ? "l" : "", nCC(INSN_COND), rM); + } + goto decode_success; + } + /* else: (link && rM == 15): just fall through */ + } + + /* --- NB: ARM interworking branches are in NV space, hence + are handled elsewhere by decode_NV_instruction. + --- + */ + + /* --------------------- Clz --------------------- */ + // CLZ + if (INSN(27,20) == BITS8(0,0,0,1,0,1,1,0) + && INSN(19,16) == BITS4(1,1,1,1) + && INSN(11,4) == BITS8(1,1,1,1,0,0,0,1)) { + UInt rD = INSN(15,12); + UInt rM = INSN(3,0); + IRTemp arg = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign(arg, getIRegA(rM)); + assign(res, IRExpr_Mux0X( + unop(Iop_1Uto8,binop(Iop_CmpEQ32, mkexpr(arg), + mkU32(0))), + unop(Iop_Clz32, mkexpr(arg)), + mkU32(32) + )); + putIRegA(rD, mkexpr(res), condT, Ijk_Boring); + DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM); + goto decode_success; + } + + /* --------------------- Mul etc --------------------- */ + // MUL + if (BITS8(0,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0)) + && INSN(15,12) == BITS4(0,0,0,0) + && INSN(7,4) == BITS4(1,0,0,1)) { + UInt bitS = (insn >> 20) & 1; /* 20:20 */ + UInt rD = INSN(19,16); + UInt rS = INSN(11,8); + UInt rM = INSN(3,0); + if (rD == 15 || rM == 15 || rS == 15) { + /* Unpredictable; don't decode; fall through */ + } else { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp oldC = IRTemp_INVALID; + IRTemp oldV = IRTemp_INVALID; + assign( argL, getIRegA(rM)); + assign( argR, getIRegA(rS)); + assign( res, binop(Iop_Mul32, mkexpr(argL), mkexpr(argR)) ); + if (bitS) { + oldC = newTemp(Ity_I32); + assign(oldC, mk_armg_calculate_flag_c()); + oldV = newTemp(Ity_I32); + assign(oldV, mk_armg_calculate_flag_v()); + } + // now update guest state + putIRegA( rD, mkexpr(res), condT, Ijk_Boring ); + if (bitS) { + IRTemp pair = newTemp(Ity_I32); + assign( pair, binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(oldC), mkU8(1)), + mkexpr(oldV)) ); + setFlags_D1_ND( ARMG_CC_OP_MUL, res, pair, condT ); + } + DIP("mul%c%s r%u, r%u, r%u\n", + bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS); + goto decode_success; + } + /* fall through */ + } + + // MLA, MLS + if (BITS8(0,0,0,0,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0)) + && INSN(7,4) == BITS4(1,0,0,1)) { + UInt bitS = (insn >> 20) & 1; /* 20:20 */ + UInt isMLS = (insn >> 22) & 1; /* 22:22 */ + UInt rD = INSN(19,16); + UInt rN = INSN(15,12); + UInt rS = INSN(11,8); + UInt rM = INSN(3,0); + if (bitS == 1 && isMLS == 1) { + /* This isn't allowed (MLS that sets flags). don't decode; + fall through */ + } + else + if (rD == 15 || rM == 15 || rS == 15 || rN == 15) { + /* Unpredictable; don't decode; fall through */ + } else { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp argP = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp oldC = IRTemp_INVALID; + IRTemp oldV = IRTemp_INVALID; + assign( argL, getIRegA(rM)); + assign( argR, getIRegA(rS)); + assign( argP, getIRegA(rN)); + assign( res, binop(isMLS ? Iop_Sub32 : Iop_Add32, + mkexpr(argP), + binop(Iop_Mul32, mkexpr(argL), mkexpr(argR)) )); + if (bitS) { + vassert(!isMLS); // guaranteed above + oldC = newTemp(Ity_I32); + assign(oldC, mk_armg_calculate_flag_c()); + oldV = newTemp(Ity_I32); + assign(oldV, mk_armg_calculate_flag_v()); + } + // now update guest state + putIRegA( rD, mkexpr(res), condT, Ijk_Boring ); + if (bitS) { + IRTemp pair = newTemp(Ity_I32); + assign( pair, binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(oldC), mkU8(1)), + mkexpr(oldV)) ); + setFlags_D1_ND( ARMG_CC_OP_MUL, res, pair, condT ); + } + DIP("ml%c%c%s r%u, r%u, r%u, r%u\n", + isMLS ? 's' : 'a', bitS ? 's' : ' ', + nCC(INSN_COND), rD, rM, rS, rN); + goto decode_success; + } + /* fall through */ + } + + // SMULL, UMULL + if (BITS8(0,0,0,0,1,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0)) + && INSN(7,4) == BITS4(1,0,0,1)) { + UInt bitS = (insn >> 20) & 1; /* 20:20 */ + UInt rDhi = INSN(19,16); + UInt rDlo = INSN(15,12); + UInt rS = INSN(11,8); + UInt rM = INSN(3,0); + UInt isS = (INSN(27,20) >> 2) & 1; /* 22:22 */ + if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) { + /* Unpredictable; don't decode; fall through */ + } else { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I64); + IRTemp resHi = newTemp(Ity_I32); + IRTemp resLo = newTemp(Ity_I32); + IRTemp oldC = IRTemp_INVALID; + IRTemp oldV = IRTemp_INVALID; + IROp mulOp = isS ? Iop_MullS32 : Iop_MullU32; + assign( argL, getIRegA(rM)); + assign( argR, getIRegA(rS)); + assign( res, binop(mulOp, mkexpr(argL), mkexpr(argR)) ); + assign( resHi, unop(Iop_64HIto32, mkexpr(res)) ); + assign( resLo, unop(Iop_64to32, mkexpr(res)) ); + if (bitS) { + oldC = newTemp(Ity_I32); + assign(oldC, mk_armg_calculate_flag_c()); + oldV = newTemp(Ity_I32); + assign(oldV, mk_armg_calculate_flag_v()); + } + // now update guest state + putIRegA( rDhi, mkexpr(resHi), condT, Ijk_Boring ); + putIRegA( rDlo, mkexpr(resLo), condT, Ijk_Boring ); + if (bitS) { + IRTemp pair = newTemp(Ity_I32); + assign( pair, binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(oldC), mkU8(1)), + mkexpr(oldV)) ); + setFlags_D1_D2_ND( ARMG_CC_OP_MULL, resLo, resHi, pair, condT ); + } + DIP("%cmull%c%s r%u, r%u, r%u, r%u\n", + isS ? 's' : 'u', bitS ? 's' : ' ', + nCC(INSN_COND), rDlo, rDhi, rM, rS); + goto decode_success; + } + /* fall through */ + } + + // SMLAL, UMLAL + if (BITS8(0,0,0,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0)) + && INSN(7,4) == BITS4(1,0,0,1)) { + UInt bitS = (insn >> 20) & 1; /* 20:20 */ + UInt rDhi = INSN(19,16); + UInt rDlo = INSN(15,12); + UInt rS = INSN(11,8); + UInt rM = INSN(3,0); + UInt isS = (INSN(27,20) >> 2) & 1; /* 22:22 */ + if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) { + /* Unpredictable; don't decode; fall through */ + } else { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp old = newTemp(Ity_I64); + IRTemp res = newTemp(Ity_I64); + IRTemp resHi = newTemp(Ity_I32); + IRTemp resLo = newTemp(Ity_I32); + IRTemp oldC = IRTemp_INVALID; + IRTemp oldV = IRTemp_INVALID; + IROp mulOp = isS ? Iop_MullS32 : Iop_MullU32; + assign( argL, getIRegA(rM)); + assign( argR, getIRegA(rS)); + assign( old, binop(Iop_32HLto64, getIRegA(rDhi), getIRegA(rDlo)) ); + assign( res, binop(Iop_Add64, + mkexpr(old), + binop(mulOp, mkexpr(argL), mkexpr(argR))) ); + assign( resHi, unop(Iop_64HIto32, mkexpr(res)) ); + assign( resLo, unop(Iop_64to32, mkexpr(res)) ); + if (bitS) { + oldC = newTemp(Ity_I32); + assign(oldC, mk_armg_calculate_flag_c()); + oldV = newTemp(Ity_I32); + assign(oldV, mk_armg_calculate_flag_v()); + } + // now update guest state + putIRegA( rDhi, mkexpr(resHi), condT, Ijk_Boring ); + putIRegA( rDlo, mkexpr(resLo), condT, Ijk_Boring ); + if (bitS) { + IRTemp pair = newTemp(Ity_I32); + assign( pair, binop(Iop_Or32, + binop(Iop_Shl32, mkexpr(oldC), mkU8(1)), + mkexpr(oldV)) ); + setFlags_D1_D2_ND( ARMG_CC_OP_MULL, resLo, resHi, pair, condT ); + } + DIP("%cmlal%c%s r%u, r%u, r%u, r%u\n", + isS ? 's' : 'u', bitS ? 's' : ' ', nCC(INSN_COND), + rDlo, rDhi, rM, rS); + goto decode_success; + } + /* fall through */ + } + + /* --------------------- Msr etc --------------------- */ + + // MSR apsr, #imm + if (INSN(27,20) == BITS8(0,0,1,1,0,0,1,0) + && INSN(17,12) == BITS6(0,0,1,1,1,1)) { + UInt write_ge = INSN(18,18); + UInt write_nzcvq = INSN(19,19); + if (write_nzcvq || write_ge) { + UInt imm = (INSN(11,0) >> 0) & 0xFF; + UInt rot = 2 * ((INSN(11,0) >> 8) & 0xF); + IRTemp immT = newTemp(Ity_I32); + vassert(rot <= 30); + imm = ROR32(imm, rot); + assign(immT, mkU32(imm)); + desynthesise_APSR( write_nzcvq, write_ge, immT, condT ); + DIP("msr%s cpsr%s%sf, #0x%08x\n", nCC(INSN_COND), + write_nzcvq ? "f" : "", write_ge ? "g" : "", imm); + goto decode_success; + } + /* fall through */ + } + + // MSR apsr, reg + if (INSN(27,20) == BITS8(0,0,0,1,0,0,1,0) + && INSN(17,12) == BITS6(0,0,1,1,1,1) + && INSN(11,4) == BITS8(0,0,0,0,0,0,0,0)) { + UInt rN = INSN(3,0); + UInt write_ge = INSN(18,18); + UInt write_nzcvq = INSN(19,19); + if (rN != 15 && (write_nzcvq || write_ge)) { + IRTemp rNt = newTemp(Ity_I32); + assign(rNt, getIRegA(rN)); + desynthesise_APSR( write_nzcvq, write_ge, rNt, condT ); + DIP("msr%s cpsr_%s%s, r%u\n", nCC(INSN_COND), + write_nzcvq ? "f" : "", write_ge ? "g" : "", rN); + goto decode_success; + } + /* fall through */ + } + + // MRS rD, cpsr + if ((insn & 0x0FFF0FFF) == 0x010F0000) { + UInt rD = INSN(15,12); + if (rD != 15) { + IRTemp apsr = synthesise_APSR(); + putIRegA( rD, mkexpr(apsr), condT, Ijk_Boring ); + DIP("mrs%s r%u, cpsr\n", nCC(INSN_COND), rD); + goto decode_success; + } + /* fall through */ + } + + /* --------------------- Svc --------------------- */ + if (BITS8(1,1,1,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))) { + UInt imm24 = (insn >> 0) & 0xFFFFFF; + if (imm24 == 0) { + /* A syscall. We can't do this conditionally, hence: */ + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + } + // AL after here + irsb->next = mkU32( guest_R15_curr_instr_notENC + 4 ); + irsb->jumpkind = Ijk_Sys_syscall; + dres.whatNext = Dis_StopHere; + DIP("svc%s #0x%08x\n", nCC(INSN_COND), imm24); + goto decode_success; + } + /* fall through */ + } + + /* ------------------------ swp ------------------------ */ + + // SWP, SWPB + if (BITS8(0,0,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,0,0,0) == INSN(11,8) + && BITS4(1,0,0,1) == INSN(7,4)) { + UInt rN = INSN(19,16); + UInt rD = INSN(15,12); + UInt rM = INSN(3,0); + IRTemp tRn = newTemp(Ity_I32); + IRTemp tNew = newTemp(Ity_I32); + IRTemp tOld = IRTemp_INVALID; + IRTemp tSC1 = newTemp(Ity_I1); + UInt isB = (insn >> 22) & 1; + + if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) { + /* undecodable; fall through */ + } else { + /* make unconditional */ + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + /* Ok, now we're unconditional. Generate a LL-SC loop. */ + assign(tRn, getIRegA(rN)); + assign(tNew, getIRegA(rM)); + if (isB) { + /* swpb */ + tOld = newTemp(Ity_I8); + stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn), + NULL/*=>isLL*/) ); + stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn), + unop(Iop_32to8, mkexpr(tNew))) ); + } else { + /* swp */ + tOld = newTemp(Ity_I32); + stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn), + NULL/*=>isLL*/) ); + stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn), + mkexpr(tNew)) ); + } + stmt( IRStmt_Exit(unop(Iop_Not1, mkexpr(tSC1)), + /*Ijk_NoRedir*/Ijk_Boring, + IRConst_U32(guest_R15_curr_instr_notENC)) ); + putIRegA(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld), + IRTemp_INVALID, Ijk_Boring); + DIP("swp%s%s r%u, r%u, [r%u]\n", + isB ? "b" : "", nCC(INSN_COND), rD, rM, rN); + goto decode_success; + } + /* fall through */ + } + + /* ----------------------------------------------------------- */ + /* -- ARMv6 instructions -- */ + /* ----------------------------------------------------------- */ + + /* --------------------- ldrex, strex --------------------- */ + + // LDREX + if (0x01900F9F == (insn & 0x0FF00FFF)) { + UInt rT = INSN(15,12); + UInt rN = INSN(19,16); + if (rT == 15 || rN == 15) { + /* undecodable; fall through */ + } else { + IRTemp res; + /* make unconditional */ + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + /* Ok, now we're unconditional. Do the load. */ + res = newTemp(Ity_I32); + stmt( IRStmt_LLSC(Iend_LE, res, getIRegA(rN), + NULL/*this is a load*/) ); + putIRegA(rT, mkexpr(res), IRTemp_INVALID, Ijk_Boring); + DIP("ldrex%s r%u, [r%u]\n", nCC(INSN_COND), rT, rN); + goto decode_success; + } + /* fall through */ + } + + // STREX + if (0x01800F90 == (insn & 0x0FF00FF0)) { + UInt rT = INSN(3,0); + UInt rN = INSN(19,16); + UInt rD = INSN(15,12); + if (rT == 15 || rN == 15 || rD == 15 + || rD == rT || rD == rN) { + /* undecodable; fall through */ + } else { + IRTemp resSC1, resSC32; + + /* make unconditional */ + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + + /* Ok, now we're unconditional. Do the store. */ + resSC1 = newTemp(Ity_I1); + stmt( IRStmt_LLSC(Iend_LE, resSC1, getIRegA(rN), getIRegA(rT)) ); + + /* Set rD to 1 on failure, 0 on success. Currently we have + resSC1 == 0 on failure, 1 on success. */ + resSC32 = newTemp(Ity_I32); + assign(resSC32, + unop(Iop_1Uto32, unop(Iop_Not1, mkexpr(resSC1)))); + + putIRegA(rD, mkexpr(resSC32), + IRTemp_INVALID, Ijk_Boring); + DIP("strex%s r%u, r%u, [r%u]\n", nCC(INSN_COND), rD, rT, rN); + goto decode_success; + } + /* fall through */ + } + + /* --------------------- movw, movt --------------------- */ + if (0x03000000 == (insn & 0x0FF00000) + || 0x03400000 == (insn & 0x0FF00000)) /* pray for CSE */ { + UInt rD = INSN(15,12); + UInt imm16 = (insn & 0xFFF) | ((insn >> 4) & 0x0000F000); + UInt isT = (insn >> 22) & 1; + if (rD == 15) { + /* forget it */ + } else { + if (isT) { + putIRegA(rD, + binop(Iop_Or32, + binop(Iop_And32, getIRegA(rD), mkU32(0xFFFF)), + mkU32(imm16 << 16)), + condT, Ijk_Boring); + DIP("movt%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16); + goto decode_success; + } else { + putIRegA(rD, mkU32(imm16), condT, Ijk_Boring); + DIP("movw%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16); + goto decode_success; + } + } + /* fall through */ + } + + /* ----------- uxtb, sxtb, uxth, sxth, uxtb16, sxtb16 ----------- */ + /* FIXME: this is an exact duplicate of the Thumb version. They + should be commoned up. */ + if (BITS8(0,1,1,0,1, 0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,0,0)) + && BITS4(1,1,1,1) == INSN(19,16) + && BITS4(0,1,1,1) == INSN(7,4) + && BITS4(0,0, 0,0) == (INSN(11,8) & BITS4(0,0,1,1))) { + UInt subopc = INSN(27,20) & BITS8(0,0,0,0,0, 1,1,1); + if (subopc != BITS4(0,0,0,1) && subopc != BITS4(0,1,0,1)) { + Int rot = (INSN(11,8) >> 2) & 3; + UInt rM = INSN(3,0); + UInt rD = INSN(15,12); + IRTemp srcT = newTemp(Ity_I32); + IRTemp rotT = newTemp(Ity_I32); + IRTemp dstT = newTemp(Ity_I32); + HChar* nm = "???"; + assign(srcT, getIRegA(rM)); + assign(rotT, genROR32(srcT, 8 * rot)); /* 0, 8, 16 or 24 only */ + switch (subopc) { + case BITS4(0,1,1,0): // UXTB + assign(dstT, unop(Iop_8Uto32, unop(Iop_32to8, mkexpr(rotT)))); + nm = "uxtb"; + break; + case BITS4(0,0,1,0): // SXTB + assign(dstT, unop(Iop_8Sto32, unop(Iop_32to8, mkexpr(rotT)))); + nm = "sxtb"; + break; + case BITS4(0,1,1,1): // UXTH + assign(dstT, unop(Iop_16Uto32, unop(Iop_32to16, mkexpr(rotT)))); + nm = "uxth"; + break; + case BITS4(0,0,1,1): // SXTH + assign(dstT, unop(Iop_16Sto32, unop(Iop_32to16, mkexpr(rotT)))); + nm = "sxth"; + break; + case BITS4(0,1,0,0): // UXTB16 + assign(dstT, binop(Iop_And32, mkexpr(rotT), mkU32(0x00FF00FF))); + nm = "uxtb16"; + break; + case BITS4(0,0,0,0): { // SXTB16 + IRTemp lo32 = newTemp(Ity_I32); + IRTemp hi32 = newTemp(Ity_I32); + assign(lo32, binop(Iop_And32, mkexpr(rotT), mkU32(0xFF))); + assign(hi32, binop(Iop_Shr32, mkexpr(rotT), mkU8(16))); + assign( + dstT, + binop(Iop_Or32, + binop(Iop_And32, + unop(Iop_8Sto32, + unop(Iop_32to8, mkexpr(lo32))), + mkU32(0xFFFF)), + binop(Iop_Shl32, + unop(Iop_8Sto32, + unop(Iop_32to8, mkexpr(hi32))), + mkU8(16)) + )); + nm = "sxtb16"; + break; + } + default: + vassert(0); // guarded by "if" above + } + putIRegA(rD, mkexpr(dstT), condT, Ijk_Boring); + DIP("%s%s r%u, r%u, ROR #%u\n", nm, nCC(INSN_COND), rD, rM, rot); + goto decode_success; + } + /* fall through */ + } + + /* ------------------- bfi, bfc ------------------- */ + if (BITS8(0,1,1,1,1,1,0, 0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0)) + && BITS4(0, 0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) { + UInt rD = INSN(15,12); + UInt rN = INSN(3,0); + UInt msb = (insn >> 16) & 0x1F; /* 20:16 */ + UInt lsb = (insn >> 7) & 0x1F; /* 11:7 */ + if (rD == 15 || msb < lsb) { + /* undecodable; fall through */ + } else { + IRTemp src = newTemp(Ity_I32); + IRTemp olddst = newTemp(Ity_I32); + IRTemp newdst = newTemp(Ity_I32); + UInt mask = 1 << (msb - lsb); + mask = (mask - 1) + mask; + vassert(mask != 0); // guaranteed by "msb < lsb" check above + mask <<= lsb; + + assign(src, rN == 15 ? mkU32(0) : getIRegA(rN)); + assign(olddst, getIRegA(rD)); + assign(newdst, + binop(Iop_Or32, + binop(Iop_And32, + binop(Iop_Shl32, mkexpr(src), mkU8(lsb)), + mkU32(mask)), + binop(Iop_And32, + mkexpr(olddst), + mkU32(~mask))) + ); + + putIRegA(rD, mkexpr(newdst), condT, Ijk_Boring); + + if (rN == 15) { + DIP("bfc%s r%u, #%u, #%u\n", + nCC(INSN_COND), rD, lsb, msb-lsb+1); + } else { + DIP("bfi%s r%u, r%u, #%u, #%u\n", + nCC(INSN_COND), rD, rN, lsb, msb-lsb+1); + } + goto decode_success; + } + /* fall through */ + } + + /* ------------------- {u,s}bfx ------------------- */ + if (BITS8(0,1,1,1,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0)) + && BITS4(0,1,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) { + UInt rD = INSN(15,12); + UInt rN = INSN(3,0); + UInt wm1 = (insn >> 16) & 0x1F; /* 20:16 */ + UInt lsb = (insn >> 7) & 0x1F; /* 11:7 */ + UInt msb = lsb + wm1; + UInt isU = (insn >> 22) & 1; /* 22:22 */ + if (rD == 15 || rN == 15 || msb >= 32) { + /* undecodable; fall through */ + } else { + IRTemp src = newTemp(Ity_I32); + IRTemp tmp = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + UInt mask = ((1 << wm1) - 1) + (1 << wm1); + vassert(msb >= 0 && msb <= 31); + vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive + + assign(src, getIRegA(rN)); + assign(tmp, binop(Iop_And32, + binop(Iop_Shr32, mkexpr(src), mkU8(lsb)), + mkU32(mask))); + assign(res, binop(isU ? Iop_Shr32 : Iop_Sar32, + binop(Iop_Shl32, mkexpr(tmp), mkU8(31-wm1)), + mkU8(31-wm1))); + + putIRegA(rD, mkexpr(res), condT, Ijk_Boring); + + DIP("%s%s r%u, r%u, #%u, #%u\n", + isU ? "ubfx" : "sbfx", + nCC(INSN_COND), rD, rN, lsb, wm1 + 1); + goto decode_success; + } + /* fall through */ + } + + /* --------------------- Load/store doubleword ------------- */ + // LDRD STRD + /* 31 27 23 19 15 11 7 3 # highest bit + 28 24 20 16 12 8 4 0 + A5-36 1 | 16 cond 0001 U100 Rn Rd im4h 11S1 im4l + A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm + A5-40 2 | 16 cond 0001 U110 Rn Rd im4h 11S1 im4l + A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm + A5-44 3 | 16 cond 0000 U100 Rn Rd im4h 11S1 im4l + A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm + */ + /* case coding: + 1 at-ea (access at ea) + 2 at-ea-then-upd (access at ea, then Rn = ea) + 3 at-Rn-then-upd (access at Rn, then Rn = ea) + ea coding + 16 Rn +/- imm8 + 32 Rn +/- Rm + */ + /* Quickly skip over all of this for hopefully most instructions */ + if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0)) + goto after_load_store_doubleword; + + /* Check the "11S1" thing. */ + if ((INSN(7,4) & BITS4(1,1,0,1)) != BITS4(1,1,0,1)) + goto after_load_store_doubleword; + + summary = 0; + + /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(1,0,0)) { + summary = 1 | 16; + } + else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(0,0,0)) { + summary = 1 | 32; + } + else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(1,1,0)) { + summary = 2 | 16; + } + else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(0,1,0)) { + summary = 2 | 32; + } + else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(1,0,0)) { + summary = 3 | 16; + } + else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(0,0,0)) { + summary = 3 | 32; + } + else goto after_load_store_doubleword; + + { UInt rN = (insn >> 16) & 0xF; /* 19:16 */ + UInt rD = (insn >> 12) & 0xF; /* 15:12 */ + UInt rM = (insn >> 0) & 0xF; /* 3:0 */ + UInt bU = (insn >> 23) & 1; /* 23 U=1 offset+, U=0 offset- */ + UInt bS = (insn >> 5) & 1; /* S=1 store, S=0 load */ + UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */ + + /* Require rD to be an even numbered register */ + if ((rD & 1) != 0) + goto after_load_store_doubleword; + + /* Require 11:8 == 0 for Rn +/- Rm cases */ + if ((summary & 32) != 0 && (imm8 & 0xF0) != 0) + goto after_load_store_doubleword; + + /* Skip some invalid cases, which would lead to two competing + updates to the same register, or which are otherwise + disallowed by the spec. */ + switch (summary) { + case 1 | 16: + break; + case 1 | 32: + if (rM == 15) goto after_load_store_doubleword; + break; + case 2 | 16: case 3 | 16: + if (rN == 15) goto after_load_store_doubleword; + if (bS == 0 && (rN == rD || rN == rD+1)) + goto after_load_store_doubleword; + break; + case 2 | 32: case 3 | 32: + if (rM == 15) goto after_load_store_doubleword; + if (rN == 15) goto after_load_store_doubleword; + if (rN == rM) goto after_load_store_doubleword; + if (bS == 0 && (rN == rD || rN == rD+1)) + goto after_load_store_doubleword; + break; + default: + vassert(0); + } + + /* Now, we can't do a conditional load or store, since that very + likely will generate an exception. So we have to take a side + exit at this point if the condition is false. */ + if (condT != IRTemp_INVALID) { + mk_skip_over_A32_if_cond_is_false( condT ); + condT = IRTemp_INVALID; + } + /* Ok, now we're unconditional. Do the load or store. */ + + /* compute the effective address. Bind it to a tmp since we + may need to use it twice. */ + IRExpr* eaE = NULL; + switch (summary & 0xF0) { + case 16: + eaE = mk_EA_reg_plusminus_imm8( rN, bU, imm8, dis_buf ); + break; + case 32: + eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf ); + break; + } + vassert(eaE); + IRTemp eaT = newTemp(Ity_I32); + assign(eaT, eaE); + + /* get the old Rn value */ + IRTemp rnT = newTemp(Ity_I32); + assign(rnT, getIRegA(rN)); + + /* decide on the transfer address */ + IRTemp taT = IRTemp_INVALID; + switch (summary & 0x0F) { + case 1: case 2: taT = eaT; break; + case 3: taT = rnT; break; + } + vassert(taT != IRTemp_INVALID); + + /* XXX deal with alignment constraints */ + /* XXX: but the A8 doesn't seem to trap for misaligned loads, so, + ignore alignment issues for the time being. */ + + /* doubleword store S 1 + doubleword load S 0 + */ + HChar* name = NULL; + /* generate the transfers */ + if (bS == 1) { // doubleword store + storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(0)), getIRegA(rD+0) ); + storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(4)), getIRegA(rD+1) ); + name = "strd"; + } else { // doubleword load + putIRegA( rD+0, + loadLE(Ity_I32, binop(Iop_Add32, mkexpr(taT), mkU32(0))), + IRTemp_INVALID, Ijk_Boring ); + putIRegA( rD+1, + loadLE(Ity_I32, binop(Iop_Add32, mkexpr(taT), mkU32(4))), + IRTemp_INVALID, Ijk_Boring ); + name = "ldrd"; + } + + /* Update Rn if necessary. */ + switch (summary & 0x0F) { + case 2: case 3: + // should be assured by logic above: + if (bS == 0) { + vassert(rD+0 != rN); /* since we just wrote rD+0 */ + vassert(rD+1 != rN); /* since we just wrote rD+1 */ + } + putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring ); + break; + } + + switch (summary & 0x0F) { + case 1: DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf); + break; + case 2: DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n", + name, nCC(INSN_COND), rD, dis_buf); + break; + case 3: DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n", + name, nCC(INSN_COND), rD, dis_buf); + break; + default: vassert(0); + } + + goto decode_success; + } + + after_load_store_doubleword: + + /* ------------------- {s,u}xtab ------------- */ + if (BITS8(0,1,1,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,0,0,0) == (INSN(11,8) & BITS4(0,0,1,1)) + && BITS4(0,1,1,1) == INSN(7,4)) { + UInt rN = INSN(19,16); + UInt rD = INSN(15,12); + UInt rM = INSN(3,0); + UInt rot = (insn >> 10) & 3; + UInt isU = INSN(22,22); + if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) { + /* undecodable; fall through */ + } else { + IRTemp srcL = newTemp(Ity_I32); + IRTemp srcR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign(srcR, getIRegA(rM)); + assign(srcL, getIRegA(rN)); + assign(res, binop(Iop_Add32, + mkexpr(srcL), + unop(isU ? Iop_8Uto32 : Iop_8Sto32, + unop(Iop_32to8, + genROR32(srcR, 8 * rot))))); + putIRegA(rD, mkexpr(res), condT, Ijk_Boring); + DIP("%cxtab%s r%u, r%u, r%u, ror #%u\n", + isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot); + goto decode_success; + } + /* fall through */ + } + + /* ------------------- {s,u}xtah ------------- */ + if (BITS8(0,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1)) + && BITS4(0,0,0,0) == (INSN(11,8) & BITS4(0,0,1,1)) + && BITS4(0,1,1,1) == INSN(7,4)) { + UInt rN = INSN(19,16); + UInt rD = INSN(15,12); + UInt rM = INSN(3,0); + UInt rot = (insn >> 10) & 3; + UInt isU = INSN(22,22); + if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) { + /* undecodable; fall through */ + } else { + IRTemp srcL = newTemp(Ity_I32); + IRTemp srcR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign(srcR, getIRegA(rM)); + assign(srcL, getIRegA(rN)); + assign(res, binop(Iop_Add32, + mkexpr(srcL), + unop(isU ? Iop_16Uto32 : Iop_16Sto32, + unop(Iop_32to16, + genROR32(srcR, 8 * rot))))); + putIRegA(rD, mkexpr(res), condT, Ijk_Boring); + + DIP("%cxtah%s r%u, r%u, r%u, ror #%u\n", + isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot); + goto decode_success; + } + /* fall through */ + } + + /* ------------------- rev16, rev ------------------ */ + if (INSN(27,16) == 0x6BF + && (INSN(11,4) == 0xFB/*rev16*/ || INSN(11,4) == 0xF3/*rev*/)) { + Bool isREV = INSN(11,4) == 0xF3; + UInt rM = INSN(3,0); + UInt rD = INSN(15,12); + if (rM != 15 && rD != 15) { + IRTemp rMt = newTemp(Ity_I32); + assign(rMt, getIRegA(rM)); + IRTemp res = isREV ? gen_REV(rMt) : gen_REV16(rMt); + putIRegA(rD, mkexpr(res), condT, Ijk_Boring); + DIP("rev%s%s r%u, r%u\n", isREV ? "" : "16", + nCC(INSN_COND), rD, rM); + goto decode_success; + } + } + + /* ------------------- rbit ------------------ */ + if (INSN(27,16) == 0x6FF && INSN(11,4) == 0xF3) { + UInt rD = INSN(15,12); + UInt rM = INSN(3,0); + if (rD != 15 && rM != 15) { + IRTemp arg = newTemp(Ity_I32); + assign(arg, getIRegA(rM)); + IRTemp res = gen_BITREV(arg); + putIRegA(rD, mkexpr(res), condT, Ijk_Boring); + DIP("rbit r%u, r%u\n", rD, rM); + goto decode_success; + } + } + + /* ------------------- smmul ------------------ */ + if (INSN(27,20) == BITS8(0,1,1,1,0,1,0,1) + && INSN(15,12) == BITS4(1,1,1,1) + && (INSN(7,4) & BITS4(1,1,0,1)) == BITS4(0,0,0,1)) { + UInt bitR = INSN(5,5); + UInt rD = INSN(19,16); + UInt rM = INSN(11,8); + UInt rN = INSN(3,0); + if (rD != 15 && rM != 15 && rN != 15) { + IRExpr* res + = unop(Iop_64HIto32, + binop(Iop_Add64, + binop(Iop_MullS32, getIRegA(rN), getIRegA(rM)), + mkU64(bitR ? 0x80000000ULL : 0ULL))); + putIRegA(rD, res, condT, Ijk_Boring); + DIP("smmul%s%s r%u, r%u, r%u\n", + nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM); + goto decode_success; + } + } + + /* ------------------- NOP ------------------ */ + if (0x0320F000 == (insn & 0x0FFFFFFF)) { + DIP("nop%s\n", nCC(INSN_COND)); + goto decode_success; + } + + /* ----------------------------------------------------------- */ + /* -- ARMv7 instructions -- */ + /* ----------------------------------------------------------- */ + + /* -------------- read CP15 TPIDRURO register ------------- */ + /* mrc p15, 0, r0, c13, c0, 3 up to + mrc p15, 0, r14, c13, c0, 3 + */ + /* I don't know whether this is really v7-only. But anyway, we + have to support it since arm-linux uses TPIDRURO as a thread + state register. */ + if (0x0E1D0F70 == (insn & 0x0FFF0FFF)) { + UInt rD = INSN(15,12); + if (rD <= 14) { + /* skip r15, that's too stupid to handle */ + putIRegA(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32), + condT, Ijk_Boring); + DIP("mrc%s p15,0, r%u, c13, c0, 3\n", nCC(INSN_COND), rD); + goto decode_success; + } + /* fall through */ + } + + /* Handle various kinds of barriers. This is rather indiscriminate + in the sense that they are all turned into an IR Fence, which + means we don't know which they are, so the back end has to + re-emit them all when it comes acrosss an IR Fence. + */ + switch (insn) { + case 0xEE070F9A: /* v6 */ + /* mcr 15, 0, r0, c7, c10, 4 (v6) equiv to DSB (v7). Data + Synch Barrier -- ensures completion of memory accesses. */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("mcr 15, 0, r0, c7, c10, 4 (data synch barrier)\n"); + goto decode_success; + case 0xEE070FBA: /* v6 */ + /* mcr 15, 0, r0, c7, c10, 5 (v6) equiv to DMB (v7). Data + Memory Barrier -- ensures ordering of memory accesses. */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("mcr 15, 0, r0, c7, c10, 5 (data memory barrier)\n"); + goto decode_success; + case 0xEE070F95: /* v6 */ + /* mcr 15, 0, r0, c7, c5, 4 (v6) equiv to ISB (v7). + Instruction Synchronisation Barrier (or Flush Prefetch + Buffer) -- a pipe flush, I think. I suspect we could + ignore those, but to be on the safe side emit a fence + anyway. */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("mcr 15, 0, r0, c7, c5, 4 (insn synch barrier)\n"); + goto decode_success; + default: + break; + } + + /* ----------------------------------------------------------- */ + /* -- VFP (CP 10, CP 11) instructions (in ARM mode) -- */ + /* ----------------------------------------------------------- */ + + if (INSN_COND != ARMCondNV) { + Bool ok_vfp = decode_CP10_CP11_instruction ( + &dres, INSN(27,0), condT, INSN_COND, + False/*!isT*/ + ); + if (ok_vfp) + goto decode_success; + } + + /* ----------------------------------------------------------- */ + /* -- NEON instructions (in ARM mode) -- */ + /* ----------------------------------------------------------- */ + + /* These are all in NV space, and so are taken care of (far) above, + by a call from this function to decode_NV_instruction(). */ + + /* ----------------------------------------------------------- */ + /* -- v6 media instructions (in ARM mode) -- */ + /* ----------------------------------------------------------- */ + + { Bool ok_v6m = decode_V6MEDIA_instruction( + &dres, INSN(27,0), condT, INSN_COND, + False/*!isT*/ + ); + if (ok_v6m) + goto decode_success; + } + + /* ----------------------------------------------------------- */ + /* -- Undecodable -- */ + /* ----------------------------------------------------------- */ + + goto decode_failure; + /*NOTREACHED*/ + + decode_failure: + /* All decode failures end up here. */ + vex_printf("disInstr(arm): unhandled instruction: " + "0x%x\n", insn); + vex_printf(" cond=%d(0x%x) 27:20=%u(0x%02x) " + "4:4=%d " + "3:0=%u(0x%x)\n", + (Int)INSN_COND, (UInt)INSN_COND, + (Int)INSN(27,20), (UInt)INSN(27,20), + (Int)INSN(4,4), + (Int)INSN(3,0), (UInt)INSN(3,0) ); + + /* Tell the dispatcher that this insn cannot be decoded, and so has + not been executed, and (is currently) the next to be executed. + R15 should be up-to-date since it made so at the start of each + insn, but nevertheless be paranoid and update it again right + now. */ + vassert(0 == (guest_R15_curr_instr_notENC & 3)); + llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC) ); + irsb->next = mkU32(guest_R15_curr_instr_notENC); + irsb->jumpkind = Ijk_NoDecode; + dres.whatNext = Dis_StopHere; + dres.len = 0; + return dres; + + decode_success: + /* All decode successes end up here. */ + DIP("\n"); + + vassert(dres.len == 4 || dres.len == 20); + + /* Now then. Do we have an implicit jump to r15 to deal with? */ + if (r15written) { + /* If we get jump to deal with, we assume that there's been no + other competing branch stuff previously generated for this + insn. That's reasonable, in the sense that the ARM insn set + appears to declare as "Unpredictable" any instruction which + generates more than one possible new value for r15. Hence + just assert. The decoders themselves should check against + all such instructions which are thusly Unpredictable, and + decline to decode them. Hence we should never get here if we + have competing new values for r15, and hence it is safe to + assert here. */ + vassert(dres.whatNext == Dis_Continue); + vassert(irsb->next == NULL); + vassert(irsb->jumpkind = Ijk_Boring); + /* If r15 is unconditionally written, terminate the block by + jumping to it. If it's conditionally written, still + terminate the block (a shame, but we can't do side exits to + arbitrary destinations), but first jump to the next + instruction if the condition doesn't hold. */ + /* We can't use getIReg(15) to get the destination, since that + will produce r15+8, which isn't what we want. Must use + llGetIReg(15) instead. */ + if (r15guard == IRTemp_INVALID) { + /* unconditional */ + } else { + /* conditional */ + stmt( IRStmt_Exit( + unop(Iop_32to1, + binop(Iop_Xor32, + mkexpr(r15guard), mkU32(1))), + r15kind, + IRConst_U32(guest_R15_curr_instr_notENC + 4) + )); + } + irsb->next = llGetIReg(15); + irsb->jumpkind = r15kind; + dres.whatNext = Dis_StopHere; + } + + return dres; + +# undef INSN_COND +# undef INSN +} + + +/*------------------------------------------------------------*/ +/*--- Disassemble a single Thumb2 instruction ---*/ +/*------------------------------------------------------------*/ + +/* NB: in Thumb mode we do fetches of regs with getIRegT, which + automagically adds 4 to fetches of r15. However, writes to regs + are done with putIRegT, which disallows writes to r15. Hence any + r15 writes and associated jumps have to be done "by hand". */ + +/* Disassemble a single Thumb instruction into IR. The instruction is + located in host memory at guest_instr, and has (decoded) guest IP + of guest_R15_curr_instr_notENC, which will have been set before the + call here. */ + +static +DisResult disInstr_THUMB_WRK ( + Bool put_IP, + Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), + Bool resteerCisOk, + void* callback_opaque, + UChar* guest_instr, + VexArchInfo* archinfo, + VexAbiInfo* abiinfo + ) +{ + /* A macro to fish bits out of insn0. There's also INSN1, to fish + bits out of insn1, but that's defined only after the end of the + 16-bit insn decoder, so as to stop it mistakenly being used + therein. */ +# define INSN0(_bMax,_bMin) SLICE_UInt(((UInt)insn0), (_bMax), (_bMin)) + + DisResult dres; + UShort insn0; /* first 16 bits of the insn */ + //Bool allow_VFP = False; + //UInt hwcaps = archinfo->hwcaps; + HChar dis_buf[128]; // big enough to hold LDMIA etc text + + /* Summary result of the ITxxx backwards analysis: False == safe + but suboptimal. */ + Bool guaranteedUnconditional = False; + + /* What insn variants are we supporting today? */ + //allow_VFP = (0 != (hwcaps & VEX_HWCAPS_ARM_VFP)); + // etc etc + + /* Set result defaults. */ + dres.whatNext = Dis_Continue; + dres.len = 2; + dres.continueAt = 0; + + /* Set default actions for post-insn handling of writes to r15, if + required. */ + r15written = False; + r15guard = IRTemp_INVALID; /* unconditional */ + r15kind = Ijk_Boring; + + /* Insns could be 2 or 4 bytes long. Just get the first 16 bits at + this point. If we need the second 16, get them later. We can't + get them both out immediately because it risks a fault (very + unlikely, but ..) if the second 16 bits aren't actually + necessary. */ + insn0 = getUShortLittleEndianly( guest_instr ); + + if (0) vex_printf("insn: 0x%x\n", insn0); + + DIP("\t(thumb) 0x%x: ", (UInt)guest_R15_curr_instr_notENC); + + /* We may be asked to update the guest R15 before going further. */ + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + if (put_IP) { + llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC | 1) ); + } + + /* ----------------------------------------------------------- */ + /* Spot "Special" instructions (see comment at top of file). */ + { + UChar* code = (UChar*)guest_instr; + /* Spot the 16-byte preamble: + + ea4f 0cfc mov.w ip, ip, ror #3 + ea4f 3c7c mov.w ip, ip, ror #13 + ea4f 7c7c mov.w ip, ip, ror #29 + ea4f 4cfc mov.w ip, ip, ror #19 + */ + UInt word1 = 0x0CFCEA4F; + UInt word2 = 0x3C7CEA4F; + UInt word3 = 0x7C7CEA4F; + UInt word4 = 0x4CFCEA4F; + if (getUIntLittleEndianly(code+ 0) == word1 && + getUIntLittleEndianly(code+ 4) == word2 && + getUIntLittleEndianly(code+ 8) == word3 && + getUIntLittleEndianly(code+12) == word4) { + /* Got a "Special" instruction preamble. Which one is it? */ + // 0x 0A 0A EA 4A + if (getUIntLittleEndianly(code+16) == 0x0A0AEA4A + /* orr.w r10,r10,r10 */) { + /* R3 = client_request ( R4 ) */ + DIP("r3 = client_request ( %%r4 )\n"); + irsb->next = mkU32( (guest_R15_curr_instr_notENC + 20) | 1 ); + irsb->jumpkind = Ijk_ClientReq; + dres.whatNext = Dis_StopHere; + goto decode_success; + } + else + // 0x 0B 0B EA 4B + if (getUIntLittleEndianly(code+16) == 0x0B0BEA4B + /* orr r11,r11,r11 */) { + /* R3 = guest_NRADDR */ + DIP("r3 = guest_NRADDR\n"); + dres.len = 20; + llPutIReg(3, IRExpr_Get( OFFB_NRADDR, Ity_I32 )); + goto decode_success; + } + else + // 0x 0C 0C EA 4C + if (getUIntLittleEndianly(code+16) == 0x0C0CEA4C + /* orr r12,r12,r12 */) { + /* branch-and-link-to-noredir R4 */ + DIP("branch-and-link-to-noredir r4\n"); + llPutIReg(14, mkU32( (guest_R15_curr_instr_notENC + 20) | 1 )); + irsb->next = getIRegT(4); + irsb->jumpkind = Ijk_NoRedir; + dres.whatNext = Dis_StopHere; + goto decode_success; + } + /* We don't know what it is. Set insn0 so decode_failure + can print the insn following the Special-insn preamble. */ + insn0 = getUShortLittleEndianly(code+16); + goto decode_failure; + /*NOTREACHED*/ + } + + } + + /* ----------------------------------------------------------- */ + + /* Main Thumb instruction decoder starts here. It's a series of + switches which examine ever longer bit sequences at the MSB of + the instruction word, first for 16-bit insns, then for 32-bit + insns. */ + + /* --- BEGIN ITxxx optimisation analysis --- */ + /* This is a crucial optimisation for the ITState boilerplate that + follows. Examine the 9 halfwords preceding this instruction, + and if we are absolutely sure that none of them constitute an + 'it' instruction, then we can be sure that this instruction is + not under the control of any 'it' instruction, and so + guest_ITSTATE must be zero. So write zero into ITSTATE right + now, so that iropt can fold out almost all of the resulting + junk. + + If we aren't sure, we can always safely skip this step. So be a + bit conservative about it: only poke around in the same page as + this instruction, lest we get a fault from the previous page + that would not otherwise have happened. The saving grace is + that such skipping is pretty rare -- it only happens, + statistically, 18/4096ths of the time, so is judged unlikely to + be a performance problems. + + FIXME: do better. Take into account the number of insns covered + by any IT insns we find, to rule out cases where an IT clearly + cannot cover this instruction. This would improve behaviour for + branch targets immediately following an IT-guarded group that is + not of full length. Eg, (and completely ignoring issues of 16- + vs 32-bit insn length): + + ite cond + insn1 + insn2 + label: insn3 + insn4 + + The 'it' only conditionalises insn1 and insn2. However, the + current analysis is conservative and considers insn3 and insn4 + also possibly guarded. Hence if 'label:' is the start of a hot + loop we will get a big performance hit. + */ + { + /* Summary result of this analysis: False == safe but + suboptimal. */ + vassert(guaranteedUnconditional == False); + + UInt pc = guest_R15_curr_instr_notENC; + vassert(0 == (pc & 1)); + + UInt pageoff = pc & 0xFFF; + if (pageoff >= 18) { + /* It's safe to poke about in the 9 halfwords preceding this + insn. So, have a look at them. */ + guaranteedUnconditional = True; /* assume no 'it' insn found, till we do */ + + UShort* hwp = (UShort*)(HWord)pc; + Int i; + for (i = -1; i >= -9; i--) { + /* We're in the same page. (True, but commented out due + to expense.) */ + /* + vassert( ( ((UInt)(&hwp[i])) & 0xFFFFF000 ) + == ( pc & 0xFFFFF000 ) ); + */ + /* All valid IT instructions must have the form 0xBFxy, + where x can be anything, but y must be nonzero. */ + if ((hwp[i] & 0xFF00) == 0xBF00 && (hwp[i] & 0xF) != 0) { + /* might be an 'it' insn. Play safe. */ + guaranteedUnconditional = False; + break; + } + } + } + } + /* --- END ITxxx optimisation analysis --- */ + + /* Generate the guarding condition for this insn, by examining + ITSTATE. Assign it to condT. Also, generate new + values for ITSTATE ready for stuffing back into the + guest state, but don't actually do the Put yet, since it will + need to stuffed back in only after the instruction gets to a + point where it is sure to complete. Mostly we let the code at + decode_success handle this, but in cases where the insn contains + a side exit, we have to update them before the exit. */ + + /* If the ITxxx optimisation analysis above could not prove that + this instruction is guaranteed unconditional, we insert a + lengthy IR preamble to compute the guarding condition at + runtime. If it can prove it (which obviously we hope is the + normal case) then we insert a minimal preamble, which is + equivalent to setting guest_ITSTATE to zero and then folding + that through the full preamble (which completely disappears). */ + + IRTemp condT = IRTemp_INVALID; + IRTemp old_itstate = IRTemp_INVALID; + IRTemp new_itstate = IRTemp_INVALID; + IRTemp cond_AND_notInIT_T = IRTemp_INVALID; + + if (guaranteedUnconditional) { + /* BEGIN "partial eval { ITSTATE = 0; STANDARD_PREAMBLE; }" */ + + // ITSTATE = 0 :: I32 + IRTemp z32 = newTemp(Ity_I32); + assign(z32, mkU32(0)); + put_ITSTATE(z32); + + // old_itstate = 0 :: I32 + // + // old_itstate = get_ITSTATE(); + old_itstate = z32; /* 0 :: I32 */ + + // new_itstate = old_itstate >> 8 + // = 0 >> 8 + // = 0 :: I32 + // + // new_itstate = newTemp(Ity_I32); + // assign(new_itstate, + // binop(Iop_Shr32, mkexpr(old_itstate), mkU8(8))); + new_itstate = z32; + + // ITSTATE = 0 :: I32(again) + // + // put_ITSTATE(new_itstate); + + // condT1 = calc_cond_dyn( xor(and(old_istate,0xF0), 0xE0) ) + // = calc_cond_dyn( xor(0,0xE0) ) + // = calc_cond_dyn ( 0xE0 ) + // = 1 :: I32 + // Not that this matters, since the computed value is not used: + // see condT folding below + // + // IRTemp condT1 = newTemp(Ity_I32); + // assign(condT1, + // mk_armg_calculate_condition_dyn( + // binop(Iop_Xor32, + // binop(Iop_And32, mkexpr(old_itstate), mkU32(0xF0)), + // mkU32(0xE0)) + // ) + // ); + + // condT = 32to8(and32(old_itstate,0xF0)) == 0 ? 1 : condT1 + // = 32to8(and32(0,0xF0)) == 0 ? 1 : condT1 + // = 32to8(0) == 0 ? 1 : condT1 + // = 0 == 0 ? 1 : condT1 + // = 1 + // + // condT = newTemp(Ity_I32); + // assign(condT, IRExpr_Mux0X( + // unop(Iop_32to8, binop(Iop_And32, + // mkexpr(old_itstate), + // mkU32(0xF0))), + // mkU32(1), + // mkexpr(condT1) + // )); + condT = newTemp(Ity_I32); + assign(condT, mkU32(1)); + + // notInITt = xor32(and32(old_itstate, 1), 1) + // = xor32(and32(0, 1), 1) + // = xor32(0, 1) + // = 1 :: I32 + // + // IRTemp notInITt = newTemp(Ity_I32); + // assign(notInITt, + // binop(Iop_Xor32, + // binop(Iop_And32, mkexpr(old_itstate), mkU32(1)), + // mkU32(1))); + + // cond_AND_notInIT_T = and32(notInITt, condT) + // = and32(1, 1) + // = 1 + // + // cond_AND_notInIT_T = newTemp(Ity_I32); + // assign(cond_AND_notInIT_T, + // binop(Iop_And32, mkexpr(notInITt), mkexpr(condT))); + cond_AND_notInIT_T = condT; /* 1 :: I32 */ + + /* END "partial eval { ITSTATE = 0; STANDARD_PREAMBLE; }" */ + } else { + /* BEGIN { STANDARD PREAMBLE; } */ + + old_itstate = get_ITSTATE(); + + new_itstate = newTemp(Ity_I32); + assign(new_itstate, + binop(Iop_Shr32, mkexpr(old_itstate), mkU8(8))); + + put_ITSTATE(new_itstate); + + /* Same strategy as for ARM insns: generate a condition + temporary at this point (or IRTemp_INVALID, meaning + unconditional). We leave it to lower-level instruction + decoders to decide whether they can generate straight-line + code, or whether they must generate a side exit before the + instruction. condT :: Ity_I32 and is always either zero or + one. */ + IRTemp condT1 = newTemp(Ity_I32); + assign(condT1, + mk_armg_calculate_condition_dyn( + binop(Iop_Xor32, + binop(Iop_And32, mkexpr(old_itstate), mkU32(0xF0)), + mkU32(0xE0)) + ) + ); + + /* This is a bit complex, but needed to make Memcheck understand + that, if the condition in old_itstate[7:4] denotes AL (that + is, if this instruction is to be executed unconditionally), + then condT does not depend on the results of calling the + helper. + + We test explicitly for old_itstate[7:4] == AL ^ 0xE, and in + that case set condT directly to 1. Else we use the results + of the helper. Since old_itstate is always defined and + because Memcheck does lazy V-bit propagation through Mux0X, + this will cause condT to always be a defined 1 if the + condition is 'AL'. From an execution semantics point of view + this is irrelevant since we're merely duplicating part of the + behaviour of the helper. But it makes it clear to Memcheck, + in this case, that condT does not in fact depend on the + contents of the condition code thunk. Without it, we get + quite a lot of false errors. + + So, just to clarify: from a straight semantics point of view, + we can simply do "assign(condT, mkexpr(condT1))", and the + simulator still runs fine. It's just that we get loads of + false errors from Memcheck. */ + condT = newTemp(Ity_I32); + assign(condT, IRExpr_Mux0X( + unop(Iop_32to8, binop(Iop_And32, + mkexpr(old_itstate), + mkU32(0xF0))), + mkU32(1), + mkexpr(condT1) + )); + + /* Something we don't have in ARM: generate a 0 or 1 value + indicating whether or not we are in an IT block (NB: 0 = in + IT block, 1 = not in IT block). This is used to gate + condition code updates in 16-bit Thumb instructions. */ + IRTemp notInITt = newTemp(Ity_I32); + assign(notInITt, + binop(Iop_Xor32, + binop(Iop_And32, mkexpr(old_itstate), mkU32(1)), + mkU32(1))); + + /* Compute 'condT && notInITt' -- that is, the instruction is + going to execute, and we're not in an IT block. This is the + gating condition for updating condition codes in 16-bit Thumb + instructions, except for CMP, CMN and TST. */ + cond_AND_notInIT_T = newTemp(Ity_I32); + assign(cond_AND_notInIT_T, + binop(Iop_And32, mkexpr(notInITt), mkexpr(condT))); + /* END { STANDARD PREAMBLE; } */ + } + + + /* At this point: + * ITSTATE has been updated + * condT holds the guarding condition for this instruction (0 or 1), + * notInITt is 1 if we're in "normal" code, 0 if in an IT block + * cond_AND_notInIT_T is the AND of the above two. + + If the instruction proper can't trap, then there's nothing else + to do w.r.t. ITSTATE -- just go and and generate IR for the + insn, taking into account the guarding condition. + + If, however, the instruction might trap, then we must back up + ITSTATE to the old value, and re-update it after the potentially + trapping IR section. A trap can happen either via a memory + reference or because we need to throw SIGILL. + + If an instruction has a side exit, we need to be sure that any + ITSTATE backup is re-updated before the side exit. + */ + + /* ----------------------------------------------------------- */ + /* -- -- */ + /* -- Thumb 16-bit integer instructions -- */ + /* -- -- */ + /* -- IMPORTANT: references to insn1 or INSN1 are -- */ + /* -- not allowed in this section -- */ + /* -- -- */ + /* ----------------------------------------------------------- */ + + /* 16-bit instructions inside an IT block, apart from CMP, CMN and + TST, do not set the condition codes. Hence we must dynamically + test for this case for every condition code update. */ + + IROp anOp = Iop_INVALID; + HChar* anOpNm = NULL; + + /* ================ 16-bit 15:6 cases ================ */ + + switch (INSN0(15,6)) { + + case 0x10a: // CMP + case 0x10b: { // CMN + /* ---------------- CMP Rn, Rm ---------------- */ + Bool isCMN = INSN0(15,6) == 0x10b; + UInt rN = INSN0(2,0); + UInt rM = INSN0(5,3); + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + assign( argL, getIRegT(rN) ); + assign( argR, getIRegT(rM) ); + /* Update flags regardless of whether in an IT block or not. */ + setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, + argL, argR, condT ); + DIP("%s r%u, r%u\n", isCMN ? "cmn" : "cmp", rN, rM); + goto decode_success; + } + + case 0x108: { + /* ---------------- TST Rn, Rm ---------------- */ + UInt rN = INSN0(2,0); + UInt rM = INSN0(5,3); + IRTemp oldC = newTemp(Ity_I32); + IRTemp oldV = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign( oldC, mk_armg_calculate_flag_c() ); + assign( oldV, mk_armg_calculate_flag_v() ); + assign( res, binop(Iop_And32, getIRegT(rN), getIRegT(rM)) ); + /* Update flags regardless of whether in an IT block or not. */ + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, condT ); + DIP("tst r%u, r%u\n", rN, rM); + goto decode_success; + } + + case 0x109: { + /* ---------------- NEGS Rd, Rm ---------------- */ + /* Rd = -Rm */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + IRTemp arg = newTemp(Ity_I32); + IRTemp zero = newTemp(Ity_I32); + assign(arg, getIRegT(rM)); + assign(zero, mkU32(0)); + // rD can never be r15 + putIRegT(rD, binop(Iop_Sub32, mkexpr(zero), mkexpr(arg)), condT); + setFlags_D1_D2( ARMG_CC_OP_SUB, zero, arg, cond_AND_notInIT_T); + DIP("negs r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x10F: { + /* ---------------- MVNS Rd, Rm ---------------- */ + /* Rd = ~Rm */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + IRTemp oldV = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + assign( oldC, mk_armg_calculate_flag_c() ); + assign(res, unop(Iop_Not32, getIRegT(rM))); + // rD can never be r15 + putIRegT(rD, mkexpr(res), condT); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + cond_AND_notInIT_T ); + DIP("mvns r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x10C: + /* ---------------- ORRS Rd, Rm ---------------- */ + anOp = Iop_Or32; anOpNm = "orr"; goto and_orr_eor_mul; + case 0x100: + /* ---------------- ANDS Rd, Rm ---------------- */ + anOp = Iop_And32; anOpNm = "and"; goto and_orr_eor_mul; + case 0x101: + /* ---------------- EORS Rd, Rm ---------------- */ + anOp = Iop_Xor32; anOpNm = "eor"; goto and_orr_eor_mul; + case 0x10d: + /* ---------------- MULS Rd, Rm ---------------- */ + anOp = Iop_Mul32; anOpNm = "mul"; goto and_orr_eor_mul; + and_orr_eor_mul: { + /* Rd = Rd `op` Rm */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + IRTemp res = newTemp(Ity_I32); + IRTemp oldV = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + assign( oldC, mk_armg_calculate_flag_c() ); + assign( res, binop(anOp, getIRegT(rD), getIRegT(rM) )); + // not safe to read guest state after here + // rD can never be r15 + putIRegT(rD, mkexpr(res), condT); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + cond_AND_notInIT_T ); + DIP("%s r%u, r%u\n", anOpNm, rD, rM); + goto decode_success; + } + + case 0x10E: { + /* ---------------- BICS Rd, Rm ---------------- */ + /* Rd = Rd & ~Rm */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + IRTemp res = newTemp(Ity_I32); + IRTemp oldV = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + assign( oldC, mk_armg_calculate_flag_c() ); + assign( res, binop(Iop_And32, getIRegT(rD), + unop(Iop_Not32, getIRegT(rM) ))); + // not safe to read guest state after here + // rD can never be r15 + putIRegT(rD, mkexpr(res), condT); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + cond_AND_notInIT_T ); + DIP("bics r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x105: { + /* ---------------- ADCS Rd, Rm ---------------- */ + /* Rd = Rd + Rm + oldC */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign(argL, getIRegT(rD)); + assign(argR, getIRegT(rM)); + assign(oldC, mk_armg_calculate_flag_c()); + assign(res, binop(Iop_Add32, + binop(Iop_Add32, mkexpr(argL), mkexpr(argR)), + mkexpr(oldC))); + // rD can never be r15 + putIRegT(rD, mkexpr(res), condT); + setFlags_D1_D2_ND( ARMG_CC_OP_ADC, argL, argR, oldC, + cond_AND_notInIT_T ); + DIP("adcs r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x106: { + /* ---------------- SBCS Rd, Rm ---------------- */ + /* Rd = Rd - Rm - (oldC ^ 1) */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign(argL, getIRegT(rD)); + assign(argR, getIRegT(rM)); + assign(oldC, mk_armg_calculate_flag_c()); + assign(res, binop(Iop_Sub32, + binop(Iop_Sub32, mkexpr(argL), mkexpr(argR)), + binop(Iop_Xor32, mkexpr(oldC), mkU32(1)))); + // rD can never be r15 + putIRegT(rD, mkexpr(res), condT); + setFlags_D1_D2_ND( ARMG_CC_OP_SBB, argL, argR, oldC, + cond_AND_notInIT_T ); + DIP("sbcs r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x2CB: { + /* ---------------- UXTB Rd, Rm ---------------- */ + /* Rd = 8Uto32(Rm) */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFF)), + condT); + DIP("uxtb r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x2C9: { + /* ---------------- SXTB Rd, Rm ---------------- */ + /* Rd = 8Sto32(Rm) */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + putIRegT(rD, binop(Iop_Sar32, + binop(Iop_Shl32, getIRegT(rM), mkU8(24)), + mkU8(24)), + condT); + DIP("sxtb r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x2CA: { + /* ---------------- UXTH Rd, Rm ---------------- */ + /* Rd = 16Uto32(Rm) */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFFFF)), + condT); + DIP("uxth r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x2C8: { + /* ---------------- SXTH Rd, Rm ---------------- */ + /* Rd = 16Sto32(Rm) */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + putIRegT(rD, binop(Iop_Sar32, + binop(Iop_Shl32, getIRegT(rM), mkU8(16)), + mkU8(16)), + condT); + DIP("sxth r%u, r%u\n", rD, rM); + goto decode_success; + } + + case 0x102: // LSLS + case 0x103: // LSRS + case 0x104: // ASRS + case 0x107: { // RORS + /* ---------------- LSLS Rs, Rd ---------------- */ + /* ---------------- LSRS Rs, Rd ---------------- */ + /* ---------------- ASRS Rs, Rd ---------------- */ + /* ---------------- RORS Rs, Rd ---------------- */ + /* Rd = Rd `op` Rs, and set flags */ + UInt rS = INSN0(5,3); + UInt rD = INSN0(2,0); + IRTemp oldV = newTemp(Ity_I32); + IRTemp rDt = newTemp(Ity_I32); + IRTemp rSt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp resC = newTemp(Ity_I32); + HChar* wot = "???"; + assign(rSt, getIRegT(rS)); + assign(rDt, getIRegT(rD)); + assign(oldV, mk_armg_calculate_flag_v()); + /* Does not appear to be the standard 'how' encoding. */ + switch (INSN0(15,6)) { + case 0x102: + compute_result_and_C_after_LSL_by_reg( + dis_buf, &res, &resC, rDt, rSt, rD, rS + ); + wot = "lsl"; + break; + case 0x103: + compute_result_and_C_after_LSR_by_reg( + dis_buf, &res, &resC, rDt, rSt, rD, rS + ); + wot = "lsr"; + break; + case 0x104: + compute_result_and_C_after_ASR_by_reg( + dis_buf, &res, &resC, rDt, rSt, rD, rS + ); + wot = "asr"; + break; + case 0x107: + compute_result_and_C_after_ROR_by_reg( + dis_buf, &res, &resC, rDt, rSt, rD, rS + ); + wot = "ror"; + break; + default: + /*NOTREACHED*/vassert(0); + } + // not safe to read guest state after this point + putIRegT(rD, mkexpr(res), condT); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, resC, oldV, + cond_AND_notInIT_T ); + DIP("%ss r%u, r%u\n", wot, rS, rD); + goto decode_success; + } + + case 0x2E8: // REV + case 0x2E9: { // REV16 + /* ---------------- REV Rd, Rm ---------------- */ + /* ---------------- REV16 Rd, Rm ---------------- */ + UInt rM = INSN0(5,3); + UInt rD = INSN0(2,0); + Bool isREV = INSN0(15,6) == 0x2E8; + IRTemp arg = newTemp(Ity_I32); + assign(arg, getIRegT(rM)); + IRTemp res = isREV ? gen_REV(arg) : gen_REV16(arg); + putIRegT(rD, mkexpr(res), condT); + DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM); + goto decode_success; + } + + default: + break; /* examine the next shortest prefix */ + + } + + + /* ================ 16-bit 15:7 cases ================ */ + + switch (INSN0(15,7)) { + + case BITS9(1,0,1,1,0,0,0,0,0): { + /* ------------ ADD SP, #imm7 * 4 ------------ */ + UInt uimm7 = INSN0(6,0); + putIRegT(13, binop(Iop_Add32, getIRegT(13), mkU32(uimm7 * 4)), + condT); + DIP("add sp, #%u\n", uimm7 * 4); + goto decode_success; + } + + case BITS9(1,0,1,1,0,0,0,0,1): { + /* ------------ SUB SP, #imm7 * 4 ------------ */ + UInt uimm7 = INSN0(6,0); + putIRegT(13, binop(Iop_Sub32, getIRegT(13), mkU32(uimm7 * 4)), + condT); + DIP("sub sp, #%u\n", uimm7 * 4); + goto decode_success; + } + + case BITS9(0,1,0,0,0,1,1,1,0): { + /* ---------------- BX rM ---------------- */ + /* Branch to reg, and optionally switch modes. Reg contains a + suitably encoded address therefore (w CPSR.T at the bottom). + Have to special-case r15, as usual. */ + UInt rM = (INSN0(6,6) << 3) | INSN0(5,3); + if (BITS3(0,0,0) == INSN0(2,0)) { + IRTemp dst = newTemp(Ity_I32); + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + if (rM <= 14) { + assign( dst, getIRegT(rM) ); + } else { + vassert(rM == 15); + assign( dst, mkU32(guest_R15_curr_instr_notENC + 4) ); + } + irsb->next = mkexpr(dst); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + DIP("bx r%u (possibly switch to ARM mode)\n", rM); + goto decode_success; + } + break; + } + + /* ---------------- BLX rM ---------------- */ + /* Branch and link to interworking address in rM. */ + case BITS9(0,1,0,0,0,1,1,1,1): { + if (BITS3(0,0,0) == INSN0(2,0)) { + UInt rM = (INSN0(6,6) << 3) | INSN0(5,3); + IRTemp dst = newTemp(Ity_I32); + if (rM <= 14) { + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + /* We're returning to Thumb code, hence "| 1" */ + assign( dst, getIRegT(rM) ); + putIRegT( 14, mkU32( (guest_R15_curr_instr_notENC + 2) | 1 ), + IRTemp_INVALID ); + irsb->next = mkexpr(dst); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + DIP("blx r%u (possibly switch to ARM mode)\n", rM); + goto decode_success; + } + /* else unpredictable, fall through */ + } + break; + } + + default: + break; /* examine the next shortest prefix */ + + } + + + /* ================ 16-bit 15:8 cases ================ */ + + switch (INSN0(15,8)) { + + case BITS8(1,1,0,1,1,1,1,1): { + /* ---------------- SVC ---------------- */ + UInt imm8 = INSN0(7,0); + if (imm8 == 0) { + /* A syscall. We can't do this conditionally, hence: */ + mk_skip_over_T16_if_cond_is_false( condT ); + // FIXME: what if we have to back up and restart this insn? + // then ITSTATE will be wrong (we'll have it as "used") + // when it isn't. Correct is to save ITSTATE in a + // stash pseudo-reg, and back up from that if we have to + // restart. + // uncond after here + irsb->next = mkU32( (guest_R15_curr_instr_notENC + 2) | 1 ); + irsb->jumpkind = Ijk_Sys_syscall; + dres.whatNext = Dis_StopHere; + DIP("svc #0x%08x\n", imm8); + goto decode_success; + } + /* else fall through */ + break; + } + + case BITS8(0,1,0,0,0,1,0,0): { + /* ---------------- ADD(HI) Rd, Rm ---------------- */ + UInt h1 = INSN0(7,7); + UInt h2 = INSN0(6,6); + UInt rM = (h2 << 3) | INSN0(5,3); + UInt rD = (h1 << 3) | INSN0(2,0); + //if (h1 == 0 && h2 == 0) { // Original T1 was more restrictive + if (rD == 15 && rM == 15) { + // then it's invalid + } else { + IRTemp res = newTemp(Ity_I32); + assign( res, binop(Iop_Add32, getIRegT(rD), getIRegT(rM) )); + if (rD != 15) { + putIRegT( rD, mkexpr(res), condT ); + } else { + /* Only allowed outside or last-in IT block; SIGILL if not so. */ + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + /* jump over insn if not selected */ + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + /* non-interworking branch */ + irsb->next = binop(Iop_Or32, mkexpr(res), mkU32(1)); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + } + DIP("add(hi) r%u, r%u\n", rD, rM); + goto decode_success; + } + break; + } + + case BITS8(0,1,0,0,0,1,0,1): { + /* ---------------- CMP(HI) Rd, Rm ---------------- */ + UInt h1 = INSN0(7,7); + UInt h2 = INSN0(6,6); + UInt rM = (h2 << 3) | INSN0(5,3); + UInt rN = (h1 << 3) | INSN0(2,0); + if (h1 != 0 || h2 != 0) { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + assign( argL, getIRegT(rN) ); + assign( argR, getIRegT(rM) ); + /* Update flags regardless of whether in an IT block or not. */ + setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); + DIP("cmphi r%u, r%u\n", rN, rM); + goto decode_success; + } + break; + } + + case BITS8(0,1,0,0,0,1,1,0): { + /* ---------------- MOV(HI) Rd, Rm ---------------- */ + UInt h1 = INSN0(7,7); + UInt h2 = INSN0(6,6); + UInt rM = (h2 << 3) | INSN0(5,3); + UInt rD = (h1 << 3) | INSN0(2,0); + /* The old ARM ARM seems to disallow the case where both Rd and + Rm are "low" registers, but newer versions allow it. */ + if (1 /*h1 != 0 || h2 != 0*/) { + IRTemp val = newTemp(Ity_I32); + assign( val, getIRegT(rM) ); + if (rD != 15) { + putIRegT( rD, mkexpr(val), condT ); + } else { + /* Only allowed outside or last-in IT block; SIGILL if not so. */ + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + /* jump over insn if not selected */ + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + /* non-interworking branch */ + irsb->next = binop(Iop_Or32, mkexpr(val), mkU32(1)); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + } + DIP("mov r%u, r%u\n", rD, rM); + goto decode_success; + } + break; + } + + case BITS8(1,0,1,1,1,1,1,1): { + /* ---------------- IT (if-then) ---------------- */ + UInt firstcond = INSN0(7,4); + UInt mask = INSN0(3,0); + UInt newITSTATE = 0; + /* This is the ITSTATE represented as described in + libvex_guest_arm.h. It is not the ARM ARM representation. */ + UChar c1 = '.'; + UChar c2 = '.'; + UChar c3 = '.'; + Bool valid = compute_ITSTATE( &newITSTATE, &c1, &c2, &c3, + firstcond, mask ); + if (valid && firstcond != 0xF/*NV*/) { + /* Not allowed in an IT block; SIGILL if so. */ + gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate); + + IRTemp t = newTemp(Ity_I32); + assign(t, mkU32(newITSTATE)); + put_ITSTATE(t); + + DIP("it%c%c%c %s\n", c1, c2, c3, nCC(firstcond)); + goto decode_success; + } + break; + } + + case BITS8(1,0,1,1,0,0,0,1): + case BITS8(1,0,1,1,0,0,1,1): + case BITS8(1,0,1,1,1,0,0,1): + case BITS8(1,0,1,1,1,0,1,1): { + /* ---------------- CB{N}Z ---------------- */ + UInt rN = INSN0(2,0); + UInt bOP = INSN0(11,11); + UInt imm32 = (INSN0(9,9) << 6) | (INSN0(7,3) << 1); + gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate); + /* It's a conditional branch forward. */ + IRTemp kond = newTemp(Ity_I1); + assign( kond, binop(bOP ? Iop_CmpNE32 : Iop_CmpEQ32, + getIRegT(rN), mkU32(0)) ); + + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + /* Looks like the nearest insn we can branch to is the one after + next. That makes sense, as there's no point in being able to + encode a conditional branch to the next instruction. */ + UInt dst = (guest_R15_curr_instr_notENC + 4 + imm32) | 1; + stmt(IRStmt_Exit( mkexpr(kond), + Ijk_Boring, + IRConst_U32(toUInt(dst)) )); + DIP("cb%s r%u, 0x%x\n", bOP ? "nz" : "z", rN, dst - 1); + goto decode_success; + } + + default: + break; /* examine the next shortest prefix */ + + } + + + /* ================ 16-bit 15:9 cases ================ */ + + switch (INSN0(15,9)) { + + case BITS7(1,0,1,1,0,1,0): { + /* ---------------- PUSH ---------------- */ + /* This is a bit like STMxx, but way simpler. Complications we + don't have to deal with: + * SP being one of the transferred registers + * direction (increment vs decrement) + * before-vs-after-ness + */ + Int i, nRegs; + UInt bitR = INSN0(8,8); + UInt regList = INSN0(7,0); + if (bitR) regList |= (1 << 14); + + if (regList != 0) { + /* Since we can't generate a guaranteed non-trapping IR + sequence, (1) jump over the insn if it is gated false, and + (2) back out the ITSTATE update. */ + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + put_ITSTATE(old_itstate); + // now uncond + + nRegs = 0; + for (i = 0; i < 16; i++) { + if ((regList & (1 << i)) != 0) + nRegs++; + } + vassert(nRegs >= 1 && nRegs <= 8); + + /* Move SP down first of all, so we're "covered". And don't + mess with its alignment. */ + IRTemp newSP = newTemp(Ity_I32); + assign(newSP, binop(Iop_Sub32, getIRegT(13), mkU32(4 * nRegs))); + putIRegT(13, mkexpr(newSP), IRTemp_INVALID); + + /* Generate a transfer base address as a forced-aligned + version of the final SP value. */ + IRTemp base = newTemp(Ity_I32); + assign(base, binop(Iop_And32, mkexpr(newSP), mkU32(~3))); + + /* Now the transfers */ + nRegs = 0; + for (i = 0; i < 16; i++) { + if ((regList & (1 << i)) != 0) { + storeLE( binop(Iop_Add32, mkexpr(base), mkU32(4 * nRegs)), + getIRegT(i) ); + nRegs++; + } + } + + /* Reinstate the ITSTATE update. */ + put_ITSTATE(new_itstate); + + DIP("push {%s0x%04x}\n", bitR ? "lr," : "", regList & 0xFF); + goto decode_success; + } + break; + } + + case BITS7(1,0,1,1,1,1,0): { + /* ---------------- POP ---------------- */ + Int i, nRegs; + UInt bitR = INSN0(8,8); + UInt regList = INSN0(7,0); + + if (regList != 0 || bitR) { + /* Since we can't generate a guaranteed non-trapping IR + sequence, (1) jump over the insn if it is gated false, and + (2) back out the ITSTATE update. */ + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + put_ITSTATE(old_itstate); + // now uncond + + nRegs = 0; + for (i = 0; i < 8; i++) { + if ((regList & (1 << i)) != 0) + nRegs++; + } + vassert(nRegs >= 0 && nRegs <= 7); + vassert(bitR == 0 || bitR == 1); + + IRTemp oldSP = newTemp(Ity_I32); + assign(oldSP, getIRegT(13)); + + /* Generate a transfer base address as a forced-aligned + version of the original SP value. */ + IRTemp base = newTemp(Ity_I32); + assign(base, binop(Iop_And32, mkexpr(oldSP), mkU32(~3))); + + /* Compute a new value for SP, but don't install it yet, so + that we're "covered" until all the transfers are done. + And don't mess with its alignment. */ + IRTemp newSP = newTemp(Ity_I32); + assign(newSP, binop(Iop_Add32, mkexpr(oldSP), + mkU32(4 * (nRegs + bitR)))); + + /* Now the transfers, not including PC */ + nRegs = 0; + for (i = 0; i < 8; i++) { + if ((regList & (1 << i)) != 0) { + putIRegT(i, loadLE( Ity_I32, + binop(Iop_Add32, mkexpr(base), + mkU32(4 * nRegs))), + IRTemp_INVALID ); + nRegs++; + } + } + + IRTemp newPC = IRTemp_INVALID; + if (bitR) { + newPC = newTemp(Ity_I32); + assign( newPC, loadLE( Ity_I32, + binop(Iop_Add32, mkexpr(base), + mkU32(4 * nRegs)))); + } + + /* Now we can safely install the new SP value */ + putIRegT(13, mkexpr(newSP), IRTemp_INVALID); + + /* Reinstate the ITSTATE update. */ + put_ITSTATE(new_itstate); + + /* now, do we also have to do a branch? If so, it turns out + that the new PC value is encoded exactly as we need it to + be -- with CPSR.T in the bottom bit. So we can simply use + it as is, no need to mess with it. Note, therefore, this + is an interworking return. */ + if (bitR) { + irsb->next = mkexpr(newPC); + irsb->jumpkind = Ijk_Ret; + dres.whatNext = Dis_StopHere; + } + + DIP("pop {%s0x%04x}\n", bitR ? "pc," : "", regList & 0xFF); + goto decode_success; + } + break; + } + + case BITS7(0,0,0,1,1,1,0): /* ADDS */ + case BITS7(0,0,0,1,1,1,1): { /* SUBS */ + /* ---------------- ADDS Rd, Rn, #uimm3 ---------------- */ + /* ---------------- SUBS Rd, Rn, #uimm3 ---------------- */ + UInt uimm3 = INSN0(8,6); + UInt rN = INSN0(5,3); + UInt rD = INSN0(2,0); + UInt isSub = INSN0(9,9); + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + assign( argL, getIRegT(rN) ); + assign( argR, mkU32(uimm3) ); + putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32, + mkexpr(argL), mkexpr(argR)), + condT); + setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, + argL, argR, cond_AND_notInIT_T ); + DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3); + goto decode_success; + } + + case BITS7(0,0,0,1,1,0,0): /* ADDS */ + case BITS7(0,0,0,1,1,0,1): { /* SUBS */ + /* ---------------- ADDS Rd, Rn, Rm ---------------- */ + /* ---------------- SUBS Rd, Rn, Rm ---------------- */ + UInt rM = INSN0(8,6); + UInt rN = INSN0(5,3); + UInt rD = INSN0(2,0); + UInt isSub = INSN0(9,9); + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + assign( argL, getIRegT(rN) ); + assign( argR, getIRegT(rM) ); + putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32, + mkexpr(argL), mkexpr(argR)), + condT ); + setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, + argL, argR, cond_AND_notInIT_T ); + DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM); + goto decode_success; + } + + case BITS7(0,1,0,1,0,0,0): /* STR */ + case BITS7(0,1,0,1,1,0,0): { /* LDR */ + /* ------------- LDR Rd, [Rn, Rm] ------------- */ + /* ------------- STR Rd, [Rn, Rm] ------------- */ + /* LDR/STR Rd, [Rn + Rm] */ + UInt rD = INSN0(2,0); + UInt rN = INSN0(5,3); + UInt rM = INSN0(8,6); + UInt isLD = INSN0(11,11); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM)); + put_ITSTATE(old_itstate); // backout + if (isLD) { + putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID); + } else { + storeLE(ea, getIRegT(rD)); + } + put_ITSTATE(new_itstate); // restore + + DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM); + goto decode_success; + } + + case BITS7(0,1,0,1,0,0,1): + case BITS7(0,1,0,1,1,0,1): { + /* ------------- LDRH Rd, [Rn, Rm] ------------- */ + /* ------------- STRH Rd, [Rn, Rm] ------------- */ + /* LDRH/STRH Rd, [Rn + Rm] */ + UInt rD = INSN0(2,0); + UInt rN = INSN0(5,3); + UInt rM = INSN0(8,6); + UInt isLD = INSN0(11,11); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM)); + put_ITSTATE(old_itstate); // backout + if (isLD) { + putIRegT(rD, unop(Iop_16Uto32, loadLE(Ity_I16, ea)), + IRTemp_INVALID); + } else { + storeLE( ea, unop(Iop_32to16, getIRegT(rD)) ); + } + put_ITSTATE(new_itstate); // restore + + DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM); + goto decode_success; + } + + case BITS7(0,1,0,1,1,1,1): { + /* ------------- LDRSH Rd, [Rn, Rm] ------------- */ + /* LDRSH Rd, [Rn + Rm] */ + UInt rD = INSN0(2,0); + UInt rN = INSN0(5,3); + UInt rM = INSN0(8,6); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM)); + put_ITSTATE(old_itstate); // backout + putIRegT(rD, unop(Iop_16Sto32, loadLE(Ity_I16, ea)), + IRTemp_INVALID); + put_ITSTATE(new_itstate); // restore + + DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM); + goto decode_success; + } + + case BITS7(0,1,0,1,0,1,1): { + /* ------------- LDRSB Rd, [Rn, Rm] ------------- */ + /* LDRSB Rd, [Rn + Rm] */ + UInt rD = INSN0(2,0); + UInt rN = INSN0(5,3); + UInt rM = INSN0(8,6); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM)); + put_ITSTATE(old_itstate); // backout + putIRegT(rD, unop(Iop_8Sto32, loadLE(Ity_I8, ea)), + IRTemp_INVALID); + put_ITSTATE(new_itstate); // restore + + DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM); + goto decode_success; + } + + case BITS7(0,1,0,1,0,1,0): + case BITS7(0,1,0,1,1,1,0): { + /* ------------- LDRB Rd, [Rn, Rm] ------------- */ + /* ------------- STRB Rd, [Rn, Rm] ------------- */ + /* LDRB/STRB Rd, [Rn + Rm] */ + UInt rD = INSN0(2,0); + UInt rN = INSN0(5,3); + UInt rM = INSN0(8,6); + UInt isLD = INSN0(11,11); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM)); + put_ITSTATE(old_itstate); // backout + if (isLD) { + putIRegT(rD, unop(Iop_8Uto32, loadLE(Ity_I8, ea)), + IRTemp_INVALID); + } else { + storeLE( ea, unop(Iop_32to8, getIRegT(rD)) ); + } + put_ITSTATE(new_itstate); // restore + + DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM); + goto decode_success; + } + + default: + break; /* examine the next shortest prefix */ + + } + + + /* ================ 16-bit 15:11 cases ================ */ + + switch (INSN0(15,11)) { + + case BITS5(0,0,1,1,0): + case BITS5(0,0,1,1,1): { + /* ---------------- ADDS Rn, #uimm8 ---------------- */ + /* ---------------- SUBS Rn, #uimm8 ---------------- */ + UInt isSub = INSN0(11,11); + UInt rN = INSN0(10,8); + UInt uimm8 = INSN0(7,0); + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + assign( argL, getIRegT(rN) ); + assign( argR, mkU32(uimm8) ); + putIRegT( rN, binop(isSub ? Iop_Sub32 : Iop_Add32, + mkexpr(argL), mkexpr(argR)), condT ); + setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, + argL, argR, cond_AND_notInIT_T ); + DIP("%s r%u, #%u\n", isSub ? "subs" : "adds", rN, uimm8); + goto decode_success; + } + + case BITS5(1,0,1,0,0): { + /* ---------------- ADD rD, PC, #imm8 * 4 ---------------- */ + /* a.k.a. ADR */ + /* rD = align4(PC) + imm8 * 4 */ + UInt rD = INSN0(10,8); + UInt imm8 = INSN0(7,0); + putIRegT(rD, binop(Iop_Add32, + binop(Iop_And32, getIRegT(15), mkU32(~3U)), + mkU32(imm8 * 4)), + condT); + DIP("add r%u, pc, #%u\n", rD, imm8 * 4); + goto decode_success; + } + + case BITS5(1,0,1,0,1): { + /* ---------------- ADD rD, SP, #imm8 * 4 ---------------- */ + UInt rD = INSN0(10,8); + UInt imm8 = INSN0(7,0); + putIRegT(rD, binop(Iop_Add32, getIRegT(13), mkU32(imm8 * 4)), + condT); + DIP("add r%u, r13, #%u\n", rD, imm8 * 4); + goto decode_success; + } + + case BITS5(0,0,1,0,1): { + /* ---------------- CMP Rn, #uimm8 ---------------- */ + UInt rN = INSN0(10,8); + UInt uimm8 = INSN0(7,0); + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + assign( argL, getIRegT(rN) ); + assign( argR, mkU32(uimm8) ); + /* Update flags regardless of whether in an IT block or not. */ + setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); + DIP("cmp r%u, #%u\n", rN, uimm8); + goto decode_success; + } + + case BITS5(0,0,1,0,0): { + /* -------------- (T1) MOVS Rn, #uimm8 -------------- */ + UInt rD = INSN0(10,8); + UInt uimm8 = INSN0(7,0); + IRTemp oldV = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + assign( oldC, mk_armg_calculate_flag_c() ); + assign( res, mkU32(uimm8) ); + putIRegT(rD, mkexpr(res), condT); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + cond_AND_notInIT_T ); + DIP("movs r%u, #%u\n", rD, uimm8); + goto decode_success; + } + + case BITS5(0,1,0,0,1): { + /* ------------- LDR Rd, [PC, #imm8 * 4] ------------- */ + /* LDR Rd, [align4(PC) + imm8 * 4] */ + UInt rD = INSN0(10,8); + UInt imm8 = INSN0(7,0); + IRTemp ea = newTemp(Ity_I32); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + assign(ea, binop(Iop_Add32, + binop(Iop_And32, getIRegT(15), mkU32(~3U)), + mkU32(imm8 * 4))); + put_ITSTATE(old_itstate); // backout + putIRegT(rD, loadLE(Ity_I32, mkexpr(ea)), + IRTemp_INVALID); + put_ITSTATE(new_itstate); // restore + + DIP("ldr r%u, [pc, #%u]\n", rD, imm8 * 4); + goto decode_success; + } + + case BITS5(0,1,1,0,0): /* STR */ + case BITS5(0,1,1,0,1): { /* LDR */ + /* ------------- LDR Rd, [Rn, #imm5 * 4] ------------- */ + /* ------------- STR Rd, [Rn, #imm5 * 4] ------------- */ + /* LDR/STR Rd, [Rn + imm5 * 4] */ + UInt rD = INSN0(2,0); + UInt rN = INSN0(5,3); + UInt imm5 = INSN0(10,6); + UInt isLD = INSN0(11,11); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5 * 4)); + put_ITSTATE(old_itstate); // backout + if (isLD) { + putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID); + } else { + storeLE( ea, getIRegT(rD) ); + } + put_ITSTATE(new_itstate); // restore + + DIP("%s r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 4); + goto decode_success; + } + + case BITS5(1,0,0,0,0): /* STRH */ + case BITS5(1,0,0,0,1): { /* LDRH */ + /* ------------- LDRH Rd, [Rn, #imm5 * 2] ------------- */ + /* ------------- STRH Rd, [Rn, #imm5 * 2] ------------- */ + /* LDRH/STRH Rd, [Rn + imm5 * 2] */ + UInt rD = INSN0(2,0); + UInt rN = INSN0(5,3); + UInt imm5 = INSN0(10,6); + UInt isLD = INSN0(11,11); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5 * 2)); + put_ITSTATE(old_itstate); // backout + if (isLD) { + putIRegT(rD, unop(Iop_16Uto32, loadLE(Ity_I16, ea)), + IRTemp_INVALID); + } else { + storeLE( ea, unop(Iop_32to16, getIRegT(rD)) ); + } + put_ITSTATE(new_itstate); // restore + + DIP("%sh r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 2); + goto decode_success; + } + + case BITS5(0,1,1,1,0): /* STRB */ + case BITS5(0,1,1,1,1): { /* LDRB */ + /* ------------- LDRB Rd, [Rn, #imm5] ------------- */ + /* ------------- STRB Rd, [Rn, #imm5] ------------- */ + /* LDRB/STRB Rd, [Rn + imm5] */ + UInt rD = INSN0(2,0); + UInt rN = INSN0(5,3); + UInt imm5 = INSN0(10,6); + UInt isLD = INSN0(11,11); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5)); + put_ITSTATE(old_itstate); // backout + if (isLD) { + putIRegT(rD, unop(Iop_8Uto32, loadLE(Ity_I8, ea)), + IRTemp_INVALID); + } else { + storeLE( ea, unop(Iop_32to8, getIRegT(rD)) ); + } + put_ITSTATE(new_itstate); // restore + + DIP("%sb r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5); + goto decode_success; + } + + case BITS5(1,0,0,1,0): /* STR */ + case BITS5(1,0,0,1,1): { /* LDR */ + /* ------------- LDR Rd, [SP, #imm8 * 4] ------------- */ + /* ------------- STR Rd, [SP, #imm8 * 4] ------------- */ + /* LDR/STR Rd, [SP + imm8 * 4] */ + UInt rD = INSN0(10,8); + UInt imm8 = INSN0(7,0); + UInt isLD = INSN0(11,11); + + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRExpr* ea = binop(Iop_Add32, getIRegT(13), mkU32(imm8 * 4)); + put_ITSTATE(old_itstate); // backout + if (isLD) { + putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID); + } else { + storeLE(ea, getIRegT(rD)); + } + put_ITSTATE(new_itstate); // restore + + DIP("%s r%u, [sp, #%u]\n", isLD ? "ldr" : "str", rD, imm8 * 4); + goto decode_success; + } + + case BITS5(1,1,0,0,1): { + /* ------------- LDMIA Rn!, {reglist} ------------- */ + Int i, nRegs = 0; + UInt rN = INSN0(10,8); + UInt list = INSN0(7,0); + /* Empty lists aren't allowed. */ + if (list != 0) { + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + put_ITSTATE(old_itstate); + // now uncond + + IRTemp oldRn = newTemp(Ity_I32); + IRTemp base = newTemp(Ity_I32); + assign(oldRn, getIRegT(rN)); + assign(base, binop(Iop_And32, mkexpr(oldRn), mkU32(~3U))); + for (i = 0; i < 8; i++) { + if (0 == (list & (1 << i))) + continue; + nRegs++; + putIRegT( + i, loadLE(Ity_I32, + binop(Iop_Add32, mkexpr(base), + mkU32(nRegs * 4 - 4))), + IRTemp_INVALID + ); + } + /* Only do the writeback for rN if it isn't in the list of + registers to be transferred. */ + if (0 == (list & (1 << rN))) { + putIRegT(rN, + binop(Iop_Add32, mkexpr(oldRn), + mkU32(nRegs * 4)), + IRTemp_INVALID + ); + } + + /* Reinstate the ITSTATE update. */ + put_ITSTATE(new_itstate); + + DIP("ldmia r%u!, {0x%04x}\n", rN, list); + goto decode_success; + } + break; + } + + case BITS5(1,1,0,0,0): { + /* ------------- STMIA Rn!, {reglist} ------------- */ + Int i, nRegs = 0; + UInt rN = INSN0(10,8); + UInt list = INSN0(7,0); + /* Empty lists aren't allowed. Also, if rN is in the list then + it must be the lowest numbered register in the list. */ + Bool valid = list != 0; + if (valid && 0 != (list & (1 << rN))) { + for (i = 0; i < rN; i++) { + if (0 != (list & (1 << i))) + valid = False; + } + } + if (valid) { + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + put_ITSTATE(old_itstate); + // now uncond + + IRTemp oldRn = newTemp(Ity_I32); + IRTemp base = newTemp(Ity_I32); + assign(oldRn, getIRegT(rN)); + assign(base, binop(Iop_And32, mkexpr(oldRn), mkU32(~3U))); + for (i = 0; i < 8; i++) { + if (0 == (list & (1 << i))) + continue; + nRegs++; + storeLE( binop(Iop_Add32, mkexpr(base), mkU32(nRegs * 4 - 4)), + getIRegT(i) ); + } + /* Always do the writeback. */ + putIRegT(rN, + binop(Iop_Add32, mkexpr(oldRn), + mkU32(nRegs * 4)), + IRTemp_INVALID); + + /* Reinstate the ITSTATE update. */ + put_ITSTATE(new_itstate); + + DIP("stmia r%u!, {0x%04x}\n", rN, list); + goto decode_success; + } + break; + } + + case BITS5(0,0,0,0,0): /* LSLS */ + case BITS5(0,0,0,0,1): /* LSRS */ + case BITS5(0,0,0,1,0): { /* ASRS */ + /* ---------------- LSLS Rd, Rm, #imm5 ---------------- */ + /* ---------------- LSRS Rd, Rm, #imm5 ---------------- */ + /* ---------------- ASRS Rd, Rm, #imm5 ---------------- */ + UInt rD = INSN0(2,0); + UInt rM = INSN0(5,3); + UInt imm5 = INSN0(10,6); + IRTemp res = newTemp(Ity_I32); + IRTemp resC = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp oldV = newTemp(Ity_I32); + HChar* wot = "???"; + assign(rMt, getIRegT(rM)); + assign(oldV, mk_armg_calculate_flag_v()); + /* Looks like INSN0(12,11) are the standard 'how' encoding. + Could compactify if the ROR case later appears. */ + switch (INSN0(15,11)) { + case BITS5(0,0,0,0,0): + compute_result_and_C_after_LSL_by_imm5( + dis_buf, &res, &resC, rMt, imm5, rM + ); + wot = "lsl"; + break; + case BITS5(0,0,0,0,1): + compute_result_and_C_after_LSR_by_imm5( + dis_buf, &res, &resC, rMt, imm5, rM + ); + wot = "lsr"; + break; + case BITS5(0,0,0,1,0): + compute_result_and_C_after_ASR_by_imm5( + dis_buf, &res, &resC, rMt, imm5, rM + ); + wot = "asr"; + break; + default: + /*NOTREACHED*/vassert(0); + } + // not safe to read guest state after this point + putIRegT(rD, mkexpr(res), condT); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, resC, oldV, + cond_AND_notInIT_T ); + /* ignore buf and roll our own output */ + DIP("%ss r%u, r%u, #%u\n", wot, rD, rM, imm5); + goto decode_success; + } + + case BITS5(1,1,1,0,0): { + /* ---------------- B #simm11 ---------------- */ + Int simm11 = INSN0(10,0); + simm11 = (simm11 << 21) >> 20; + UInt dst = simm11 + guest_R15_curr_instr_notENC + 4; + /* Only allowed outside or last-in IT block; SIGILL if not so. */ + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + // and skip this insn if not selected; being cleverer is too + // difficult + mk_skip_over_T16_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + irsb->next = mkU32( dst | 1 /*CPSR.T*/ ); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + DIP("b 0x%x\n", dst); + goto decode_success; + } + + default: + break; /* examine the next shortest prefix */ + + } + + + /* ================ 16-bit 15:12 cases ================ */ + + switch (INSN0(15,12)) { + + case BITS4(1,1,0,1): { + /* ---------------- Bcond #simm8 ---------------- */ + UInt cond = INSN0(11,8); + Int simm8 = INSN0(7,0); + simm8 = (simm8 << 24) >> 23; + UInt dst = simm8 + guest_R15_curr_instr_notENC + 4; + if (cond != ARMCondAL && cond != ARMCondNV) { + /* Not allowed in an IT block; SIGILL if so. */ + gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate); + + IRTemp kondT = newTemp(Ity_I32); + assign( kondT, mk_armg_calculate_condition(cond) ); + stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(kondT)), + Ijk_Boring, + IRConst_U32(dst | 1/*CPSR.T*/) )); + irsb->next = mkU32( (guest_R15_curr_instr_notENC + 2) + | 1 /*CPSR.T*/ ); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + DIP("b%s 0x%x\n", nCC(cond), dst); + goto decode_success; + } + break; + } + + default: + break; /* hmm, nothing matched */ + + } + + /* ================ 16-bit misc cases ================ */ + + /* ------ NOP ------ */ + if (INSN0(15,0) == 0xBF00) { + DIP("nop"); + goto decode_success; + } + + /* ----------------------------------------------------------- */ + /* -- -- */ + /* -- Thumb 32-bit integer instructions -- */ + /* -- -- */ + /* ----------------------------------------------------------- */ + +# define INSN1(_bMax,_bMin) SLICE_UInt(((UInt)insn1), (_bMax), (_bMin)) + + /* second 16 bits of the instruction, if any */ + UShort insn1 = getUShortLittleEndianly( guest_instr+2 ); + + anOp = Iop_INVALID; /* paranoia */ + anOpNm = NULL; /* paranoia */ + + /* Change result defaults to suit 32-bit insns. */ + vassert(dres.whatNext == Dis_Continue); + vassert(dres.len == 2); + vassert(dres.continueAt == 0); + dres.len = 4; + + /* ---------------- BL/BLX simm26 ---------------- */ + if (BITS5(1,1,1,1,0) == INSN0(15,11) && BITS2(1,1) == INSN1(15,14)) { + UInt isBL = INSN1(12,12); + UInt bS = INSN0(10,10); + UInt bJ1 = INSN1(13,13); + UInt bJ2 = INSN1(11,11); + UInt bI1 = 1 ^ (bJ1 ^ bS); + UInt bI2 = 1 ^ (bJ2 ^ bS); + Int simm25 + = (bS << (1 + 1 + 10 + 11 + 1)) + | (bI1 << (1 + 10 + 11 + 1)) + | (bI2 << (10 + 11 + 1)) + | (INSN0(9,0) << (11 + 1)) + | (INSN1(10,0) << 1); + simm25 = (simm25 << 7) >> 7; + + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + UInt dst = simm25 + guest_R15_curr_instr_notENC + 4; + + /* One further validity case to check: in the case of BLX + (not-BL), that insn1[0] must be zero. */ + Bool valid = True; + if (isBL == 0 && INSN1(0,0) == 1) valid = False; + if (valid) { + /* Only allowed outside or last-in IT block; SIGILL if not so. */ + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + // and skip this insn if not selected; being cleverer is too + // difficult + mk_skip_over_T32_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + /* We're returning to Thumb code, hence "| 1" */ + putIRegT( 14, mkU32( (guest_R15_curr_instr_notENC + 4) | 1 ), + IRTemp_INVALID); + if (isBL) { + /* BL: unconditional T -> T call */ + /* we're calling Thumb code, hence "| 1" */ + irsb->next = mkU32( dst | 1 ); + DIP("bl 0x%x (stay in Thumb mode)\n", dst); + } else { + /* BLX: unconditional T -> A call */ + /* we're calling ARM code, hence "& 3" to align to a + valid ARM insn address */ + irsb->next = mkU32( dst & ~3 ); + DIP("blx 0x%x (switch to ARM mode)\n", dst & ~3); + } + irsb->jumpkind = Ijk_Call; + dres.whatNext = Dis_StopHere; + goto decode_success; + } + } + + /* ---------------- {LD,ST}M{IA,DB} ---------------- */ + if (0x3a2 == INSN0(15,6) // {LD,ST}MIA + || 0x3a4 == INSN0(15,6)) { // {LD,ST}MDB + UInt bW = INSN0(5,5); /* writeback Rn ? */ + UInt bL = INSN0(4,4); + UInt rN = INSN0(3,0); + UInt bP = INSN1(15,15); /* reglist entry for r15 */ + UInt bM = INSN1(14,14); /* reglist entry for r14 */ + UInt rLmost = INSN1(12,0); /* reglist entry for r0 .. 12 */ + UInt rL13 = INSN1(13,13); /* must be zero */ + UInt regList = 0; + Bool valid = True; + + UInt bINC = 1; + UInt bBEFORE = 0; + if (INSN0(15,6) == 0x3a4) { + bINC = 0; + bBEFORE = 1; + } + + /* detect statically invalid cases, and construct the final + reglist */ + if (rL13 == 1) + valid = False; + + if (bL == 1) { + regList = (bP << 15) | (bM << 14) | rLmost; + if (rN == 15) valid = False; + if (popcount32(regList) < 2) valid = False; + if (bP == 1 && bM == 1) valid = False; + if (bW == 1 && (regList & (1<next = llGetIReg(15); + irsb->jumpkind = Ijk_Ret; + dres.whatNext = Dis_StopHere; + } + + DIP("%sm%c%c r%u%s, {0x%04x}\n", + bL == 1 ? "ld" : "st", bINC ? 'i' : 'd', bBEFORE ? 'b' : 'a', + rN, bW ? "!" : "", regList); + + goto decode_success; + } + } + + /* -------------- (T3) ADD{S}.W Rd, Rn, #constT -------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && INSN0(9,5) == BITS5(0,1,0,0,0) + && INSN1(15,15) == 0) { + UInt bS = INSN0(4,4); + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + Bool valid = !isBadRegT(rN) && !isBadRegT(rD); + /* but allow "add.w reg, sp, #constT" */ + if (!valid && rN == 13) + valid = True; + if (valid) { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + UInt imm32 = thumbExpandImm_from_I0_I1(NULL, insn0, insn1); + assign(argL, getIRegT(rN)); + assign(argR, mkU32(imm32)); + assign(res, binop(Iop_Add32, mkexpr(argL), mkexpr(argR))); + putIRegT(rD, mkexpr(res), condT); + if (bS == 1) + setFlags_D1_D2( ARMG_CC_OP_ADD, argL, argR, condT ); + DIP("add%s.w r%u, r%u, #%u\n", + bS == 1 ? "s" : "", rD, rN, imm32); + goto decode_success; + } + } + + /* ---------------- (T2) CMP.W Rn, #constT ---------------- */ + /* ---------------- (T2) CMN.W Rn, #constT ---------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && ( INSN0(9,4) == BITS6(0,1,1,0,1,1) // CMP + || INSN0(9,4) == BITS6(0,1,0,0,0,1)) // CMN + && INSN1(15,15) == 0 + && INSN1(11,8) == BITS4(1,1,1,1)) { + UInt rN = INSN0(3,0); + if (rN != 15) { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + Bool isCMN = INSN0(9,4) == BITS6(0,1,0,0,0,1); + UInt imm32 = thumbExpandImm_from_I0_I1(NULL, insn0, insn1); + assign(argL, getIRegT(rN)); + assign(argR, mkU32(imm32)); + setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, + argL, argR, condT ); + DIP("%s.w r%u, #%u\n", isCMN ? "cmn" : "cmp", rN, imm32); + goto decode_success; + } + } + + /* -------------- (T1) TST.W Rn, #constT -------------- */ + /* -------------- (T1) TEQ.W Rn, #constT -------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && ( INSN0(9,4) == BITS6(0,0,0,0,0,1) // TST + || INSN0(9,4) == BITS6(0,0,1,0,0,1)) // TEQ + && INSN1(15,15) == 0 + && INSN1(11,8) == BITS4(1,1,1,1)) { + UInt rN = INSN0(3,0); + if (!isBadRegT(rN)) { // yes, really, it's inconsistent with CMP.W + Bool isTST = INSN0(9,4) == BITS6(0,0,0,0,0,1); + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp oldV = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + Bool updC = False; + UInt imm32 = thumbExpandImm_from_I0_I1(&updC, insn0, insn1); + assign(argL, getIRegT(rN)); + assign(argR, mkU32(imm32)); + assign(res, binop(isTST ? Iop_And32 : Iop_Xor32, + mkexpr(argL), mkexpr(argR))); + assign( oldV, mk_armg_calculate_flag_v() ); + assign( oldC, updC + ? mkU32((imm32 >> 31) & 1) + : mk_armg_calculate_flag_c() ); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, condT ); + DIP("%s.w r%u, #%u\n", isTST ? "tst" : "teq", rN, imm32); + goto decode_success; + } + } + + /* -------------- (T3) SUB{S}.W Rd, Rn, #constT -------------- */ + /* -------------- (T3) RSB{S}.W Rd, Rn, #constT -------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && (INSN0(9,5) == BITS5(0,1,1,0,1) // SUB + || INSN0(9,5) == BITS5(0,1,1,1,0)) // RSB + && INSN1(15,15) == 0) { + Bool isRSB = INSN0(9,5) == BITS5(0,1,1,1,0); + UInt bS = INSN0(4,4); + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + Bool valid = !isBadRegT(rN) && !isBadRegT(rD); + /* but allow "sub.w sp, sp, #constT" */ + if (!valid && !isRSB && rN == 13 && rD == 13) + valid = True; + if (valid) { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + UInt imm32 = thumbExpandImm_from_I0_I1(NULL, insn0, insn1); + assign(argL, getIRegT(rN)); + assign(argR, mkU32(imm32)); + assign(res, isRSB + ? binop(Iop_Sub32, mkexpr(argR), mkexpr(argL)) + : binop(Iop_Sub32, mkexpr(argL), mkexpr(argR))); + putIRegT(rD, mkexpr(res), condT); + if (bS == 1) { + if (isRSB) + setFlags_D1_D2( ARMG_CC_OP_SUB, argR, argL, condT ); + else + setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); + } + DIP("%s%s.w r%u, r%u, #%u\n", + isRSB ? "rsb" : "sub", bS == 1 ? "s" : "", rD, rN, imm32); + goto decode_success; + } + } + + /* -------------- (T1) ADC{S}.W Rd, Rn, #constT -------------- */ + /* -------------- (T1) SBC{S}.W Rd, Rn, #constT -------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && ( INSN0(9,5) == BITS5(0,1,0,1,0) // ADC + || INSN0(9,5) == BITS5(0,1,0,1,1)) // SBC + && INSN1(15,15) == 0) { + /* ADC: Rd = Rn + constT + oldC */ + /* SBC: Rd = Rn - constT - (oldC ^ 1) */ + UInt bS = INSN0(4,4); + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + if (!isBadRegT(rN) && !isBadRegT(rD)) { + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + UInt imm32 = thumbExpandImm_from_I0_I1(NULL, insn0, insn1); + assign(argL, getIRegT(rN)); + assign(argR, mkU32(imm32)); + assign(oldC, mk_armg_calculate_flag_c() ); + HChar* nm = "???"; + switch (INSN0(9,5)) { + case BITS5(0,1,0,1,0): // ADC + nm = "adc"; + assign(res, + binop(Iop_Add32, + binop(Iop_Add32, mkexpr(argL), mkexpr(argR)), + mkexpr(oldC) )); + putIRegT(rD, mkexpr(res), condT); + if (bS) + setFlags_D1_D2_ND( ARMG_CC_OP_ADC, + argL, argR, oldC, condT ); + break; + case BITS5(0,1,0,1,1): // SBC + nm = "sbc"; + assign(res, + binop(Iop_Sub32, + binop(Iop_Sub32, mkexpr(argL), mkexpr(argR)), + binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) )); + putIRegT(rD, mkexpr(res), condT); + if (bS) + setFlags_D1_D2_ND( ARMG_CC_OP_SBB, + argL, argR, oldC, condT ); + break; + default: + vassert(0); + } + DIP("%s%s.w r%u, r%u, #%u\n", + nm, bS == 1 ? "s" : "", rD, rN, imm32); + goto decode_success; + } + } + + /* -------------- (T1) ORR{S}.W Rd, Rn, #constT -------------- */ + /* -------------- (T1) AND{S}.W Rd, Rn, #constT -------------- */ + /* -------------- (T1) BIC{S}.W Rd, Rn, #constT -------------- */ + /* -------------- (T1) EOR{S}.W Rd, Rn, #constT -------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && ( INSN0(9,5) == BITS5(0,0,0,1,0) // ORR + || INSN0(9,5) == BITS5(0,0,0,0,0) // AND + || INSN0(9,5) == BITS5(0,0,0,0,1) // BIC + || INSN0(9,5) == BITS5(0,0,1,0,0) // EOR + || INSN0(9,5) == BITS5(0,0,0,1,1)) // ORN + && INSN1(15,15) == 0) { + UInt bS = INSN0(4,4); + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + if (!isBadRegT(rN) && !isBadRegT(rD)) { + Bool notArgR = False; + IROp op = Iop_INVALID; + HChar* nm = "???"; + switch (INSN0(9,5)) { + case BITS5(0,0,0,1,0): op = Iop_Or32; nm = "orr"; break; + case BITS5(0,0,0,0,0): op = Iop_And32; nm = "and"; break; + case BITS5(0,0,0,0,1): op = Iop_And32; nm = "bic"; + notArgR = True; break; + case BITS5(0,0,1,0,0): op = Iop_Xor32; nm = "eor"; break; + case BITS5(0,0,0,1,1): op = Iop_Or32; nm = "orn"; + notArgR = True; break; + default: vassert(0); + } + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + Bool updC = False; + UInt imm32 = thumbExpandImm_from_I0_I1(&updC, insn0, insn1); + assign(argL, getIRegT(rN)); + assign(argR, mkU32(notArgR ? ~imm32 : imm32)); + assign(res, binop(op, mkexpr(argL), mkexpr(argR))); + putIRegT(rD, mkexpr(res), condT); + if (bS) { + IRTemp oldV = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + assign( oldC, updC + ? mkU32((imm32 >> 31) & 1) + : mk_armg_calculate_flag_c() ); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + condT ); + } + DIP("%s%s.w r%u, r%u, #%u\n", + nm, bS == 1 ? "s" : "", rD, rN, imm32); + goto decode_success; + } + } + + /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */ + /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */ + /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */ + if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1) + && ( INSN0(8,5) == BITS4(1,0,0,0) // add subopc + || INSN0(8,5) == BITS4(1,1,0,1) // sub subopc + || INSN0(8,5) == BITS4(1,1,1,0)) // rsb subopc + && INSN1(15,15) == 0) { + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + UInt bS = INSN0(4,4); + UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); + UInt how = INSN1(5,4); + + Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM); + /* but allow "add.w reg, sp, reg w/ no shift */ + if (!valid && INSN0(8,5) == BITS4(1,0,0,0) // add + && rN == 13 && imm5 == 0 && how == 0) { + valid = True; + } + /* also allow "sub.w sp, sp, reg w/ no shift */ + if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // add + && rD == 13 && rN == 13 && imm5 == 0 && how == 0) { + valid = True; + } + if (valid) { + Bool swap = False; + IROp op = Iop_INVALID; + HChar* nm = "???"; + switch (INSN0(8,5)) { + case BITS4(1,0,0,0): op = Iop_Add32; nm = "add"; break; + case BITS4(1,1,0,1): op = Iop_Sub32; nm = "sub"; break; + case BITS4(1,1,1,0): op = Iop_Sub32; nm = "rsb"; + swap = True; break; + default: vassert(0); + } + + IRTemp argL = newTemp(Ity_I32); + assign(argL, getIRegT(rN)); + + IRTemp rMt = newTemp(Ity_I32); + assign(rMt, getIRegT(rM)); + + IRTemp argR = newTemp(Ity_I32); + compute_result_and_C_after_shift_by_imm5( + dis_buf, &argR, NULL, rMt, how, imm5, rM + ); + + IRTemp res = newTemp(Ity_I32); + assign(res, swap + ? binop(op, mkexpr(argR), mkexpr(argL)) + : binop(op, mkexpr(argL), mkexpr(argR))); + + putIRegT(rD, mkexpr(res), condT); + if (bS) { + switch (op) { + case Iop_Add32: + setFlags_D1_D2( ARMG_CC_OP_ADD, argL, argR, condT ); + break; + case Iop_Sub32: + if (swap) + setFlags_D1_D2( ARMG_CC_OP_SUB, argR, argL, condT ); + else + setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT ); + break; + default: + vassert(0); + } + } + + DIP("%s%s.w r%u, r%u, %s\n", + nm, bS ? "s" : "", rD, rN, dis_buf); + goto decode_success; + } + } + + /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */ + /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */ + if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1) + && ( INSN0(8,5) == BITS4(1,0,1,0) // adc subopc + || INSN0(8,5) == BITS4(1,0,1,1)) // sbc subopc + && INSN1(15,15) == 0) { + /* ADC: Rd = Rn + shifter_operand + oldC */ + /* SBC: Rd = Rn - shifter_operand - (oldC ^ 1) */ + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) { + UInt bS = INSN0(4,4); + UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); + UInt how = INSN1(5,4); + + IRTemp argL = newTemp(Ity_I32); + assign(argL, getIRegT(rN)); + + IRTemp rMt = newTemp(Ity_I32); + assign(rMt, getIRegT(rM)); + + IRTemp oldC = newTemp(Ity_I32); + assign(oldC, mk_armg_calculate_flag_c()); + + IRTemp argR = newTemp(Ity_I32); + compute_result_and_C_after_shift_by_imm5( + dis_buf, &argR, NULL, rMt, how, imm5, rM + ); + + HChar* nm = "???"; + IRTemp res = newTemp(Ity_I32); + switch (INSN0(8,5)) { + case BITS4(1,0,1,0): // ADC + nm = "adc"; + assign(res, + binop(Iop_Add32, + binop(Iop_Add32, mkexpr(argL), mkexpr(argR)), + mkexpr(oldC) )); + putIRegT(rD, mkexpr(res), condT); + if (bS) + setFlags_D1_D2_ND( ARMG_CC_OP_ADC, + argL, argR, oldC, condT ); + break; + case BITS4(1,0,1,1): // SBC + nm = "sbc"; + assign(res, + binop(Iop_Sub32, + binop(Iop_Sub32, mkexpr(argL), mkexpr(argR)), + binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) )); + putIRegT(rD, mkexpr(res), condT); + if (bS) + setFlags_D1_D2_ND( ARMG_CC_OP_SBB, + argL, argR, oldC, condT ); + break; + default: + vassert(0); + } + + DIP("%s%s.w r%u, r%u, %s\n", + nm, bS ? "s" : "", rD, rN, dis_buf); + goto decode_success; + } + } + + /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */ + /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */ + /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */ + /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */ + /* ---------- (T1) ORN{S}.W Rd, Rn, Rm, {shift} ---------- */ + if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1) + && ( INSN0(8,5) == BITS4(0,0,0,0) // and subopc + || INSN0(8,5) == BITS4(0,0,1,0) // orr subopc + || INSN0(8,5) == BITS4(0,1,0,0) // eor subopc + || INSN0(8,5) == BITS4(0,0,0,1) // bic subopc + || INSN0(8,5) == BITS4(0,0,1,1)) // orn subopc + && INSN1(15,15) == 0) { + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) { + Bool notArgR = False; + IROp op = Iop_INVALID; + HChar* nm = "???"; + switch (INSN0(8,5)) { + case BITS4(0,0,0,0): op = Iop_And32; nm = "and"; break; + case BITS4(0,0,1,0): op = Iop_Or32; nm = "orr"; break; + case BITS4(0,1,0,0): op = Iop_Xor32; nm = "eor"; break; + case BITS4(0,0,0,1): op = Iop_And32; nm = "bic"; + notArgR = True; break; + case BITS4(0,0,1,1): op = Iop_Or32; nm = "orn"; + notArgR = True; break; + default: vassert(0); + } + UInt bS = INSN0(4,4); + UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); + UInt how = INSN1(5,4); + + IRTemp rNt = newTemp(Ity_I32); + assign(rNt, getIRegT(rN)); + + IRTemp rMt = newTemp(Ity_I32); + assign(rMt, getIRegT(rM)); + + IRTemp argR = newTemp(Ity_I32); + IRTemp oldC = bS ? newTemp(Ity_I32) : IRTemp_INVALID; + + compute_result_and_C_after_shift_by_imm5( + dis_buf, &argR, bS ? &oldC : NULL, rMt, how, imm5, rM + ); + + IRTemp res = newTemp(Ity_I32); + if (notArgR) { + vassert(op == Iop_And32 || op == Iop_Or32); + assign(res, binop(op, mkexpr(rNt), + unop(Iop_Not32, mkexpr(argR)))); + } else { + assign(res, binop(op, mkexpr(rNt), mkexpr(argR))); + } + + putIRegT(rD, mkexpr(res), condT); + if (bS) { + IRTemp oldV = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + condT ); + } + + DIP("%s%s.w r%u, r%u, %s\n", + nm, bS ? "s" : "", rD, rN, dis_buf); + goto decode_success; + } + } + + /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */ + /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */ + /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */ + /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */ + if (INSN0(15,7) == BITS9(1,1,1,1,1,0,1,0,0) + && INSN1(15,12) == BITS4(1,1,1,1) + && INSN1(7,4) == BITS4(0,0,0,0)) { + UInt how = INSN0(6,5); // standard encoding + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + UInt bS = INSN0(4,4); + Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD); + if (how == 3) valid = False; //ATC + if (valid) { + IRTemp rNt = newTemp(Ity_I32); + IRTemp rMt = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + IRTemp oldC = bS ? newTemp(Ity_I32) : IRTemp_INVALID; + IRTemp oldV = bS ? newTemp(Ity_I32) : IRTemp_INVALID; + HChar* nms[4] = { "lsl", "lsr", "asr", "ror" }; + HChar* nm = nms[how]; + assign(rNt, getIRegT(rN)); + assign(rMt, getIRegT(rM)); + compute_result_and_C_after_shift_by_reg( + dis_buf, &res, bS ? &oldC : NULL, + rNt, how, rMt, rN, rM + ); + if (bS) + assign(oldV, mk_armg_calculate_flag_v()); + putIRegT(rD, mkexpr(res), condT); + if (bS) { + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + condT ); + } + DIP("%s%s.w r%u, r%u, r%u\n", + nm, bS ? "s" : "", rD, rN, rM); + goto decode_success; + } + } + + /* ------------ (T?) MOV{S}.W Rd, Rn, {shift} ------------ */ + /* ------------ (T?) MVN{S}.W Rd, Rn, {shift} ------------ */ + if ((INSN0(15,0) & 0xFFCF) == 0xEA4F + && INSN1(15,15) == 0) { + UInt rD = INSN1(11,8); + UInt rN = INSN1(3,0); + if (!isBadRegT(rD) && !isBadRegT(rN)) { + UInt bS = INSN0(4,4); + UInt isMVN = INSN0(5,5); + UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); + UInt how = INSN1(5,4); + + IRTemp rNt = newTemp(Ity_I32); + assign(rNt, getIRegT(rN)); + + IRTemp oldRn = newTemp(Ity_I32); + IRTemp oldC = bS ? newTemp(Ity_I32) : IRTemp_INVALID; + compute_result_and_C_after_shift_by_imm5( + dis_buf, &oldRn, bS ? &oldC : NULL, rNt, how, imm5, rN + ); + + IRTemp res = newTemp(Ity_I32); + assign(res, isMVN ? unop(Iop_Not32, mkexpr(oldRn)) + : mkexpr(oldRn)); + + putIRegT(rD, mkexpr(res), condT); + if (bS) { + IRTemp oldV = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, condT); + } + DIP("%s%s.w r%u, %s\n", + isMVN ? "mvn" : "mov", bS ? "s" : "", rD, dis_buf); + goto decode_success; + } + } + + /* -------------- (T?) TST.W Rn, Rm, {shift} -------------- */ + /* -------------- (T?) TEQ.W Rn, Rm, {shift} -------------- */ + if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1) + && ( INSN0(8,4) == BITS5(0,0,0,0,1) // TST + || INSN0(8,4) == BITS5(0,1,0,0,1)) // TEQ + && INSN1(15,15) == 0 + && INSN1(11,8) == BITS4(1,1,1,1)) { + UInt rN = INSN0(3,0); + UInt rM = INSN1(3,0); + if (!isBadRegT(rN) && !isBadRegT(rM)) { + Bool isTST = INSN0(8,4) == BITS5(0,0,0,0,1); + + UInt how = INSN1(5,4); + UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); + + IRTemp argL = newTemp(Ity_I32); + assign(argL, getIRegT(rN)); + + IRTemp rMt = newTemp(Ity_I32); + assign(rMt, getIRegT(rM)); + + IRTemp argR = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + compute_result_and_C_after_shift_by_imm5( + dis_buf, &argR, &oldC, rMt, how, imm5, rM + ); + + IRTemp oldV = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + + IRTemp res = newTemp(Ity_I32); + assign(res, binop(isTST ? Iop_And32 : Iop_Xor32, + mkexpr(argL), mkexpr(argR))); + + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + condT ); + DIP("%s.w r%u, %s\n", isTST ? "tst" : "teq", rN, dis_buf); + goto decode_success; + } + } + + /* -------------- (T3) CMP.W Rn, Rm, {shift} -------------- */ + /* -------------- (T2) CMN.W Rn, Rm, {shift} -------------- */ + if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1) + && ( INSN0(8,4) == BITS5(1,1,0,1,1) // CMP + || INSN0(8,4) == BITS5(1,0,0,0,1)) // CMN + && INSN1(15,15) == 0 + && INSN1(11,8) == BITS4(1,1,1,1)) { + UInt rN = INSN0(3,0); + UInt rM = INSN1(3,0); + if (!isBadRegT(rN) && !isBadRegT(rM)) { + Bool isCMN = INSN0(8,4) == BITS5(1,0,0,0,1); + UInt how = INSN1(5,4); + UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6); + + IRTemp argL = newTemp(Ity_I32); + assign(argL, getIRegT(rN)); + + IRTemp rMt = newTemp(Ity_I32); + assign(rMt, getIRegT(rM)); + + IRTemp argR = newTemp(Ity_I32); + compute_result_and_C_after_shift_by_imm5( + dis_buf, &argR, NULL, rMt, how, imm5, rM + ); + + setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB, + argL, argR, condT ); + + DIP("%s.w r%u, %s\n", isCMN ? "cmn" : "cmp", rN, dis_buf); + goto decode_success; + } + } + + /* -------------- (T2) MOV{S}.W Rd, #constT -------------- */ + /* -------------- (T2) MVN{S}.W Rd, #constT -------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && ( INSN0(9,5) == BITS5(0,0,0,1,0) // MOV + || INSN0(9,5) == BITS5(0,0,0,1,1)) // MVN + && INSN0(3,0) == BITS4(1,1,1,1) + && INSN1(15,15) == 0) { + UInt rD = INSN1(11,8); + if (!isBadRegT(rD)) { + Bool updC = False; + UInt bS = INSN0(4,4); + Bool isMVN = INSN0(5,5) == 1; + UInt imm32 = thumbExpandImm_from_I0_I1(&updC, insn0, insn1); + IRTemp res = newTemp(Ity_I32); + assign(res, mkU32(isMVN ? ~imm32 : imm32)); + putIRegT(rD, mkexpr(res), condT); + if (bS) { + IRTemp oldV = newTemp(Ity_I32); + IRTemp oldC = newTemp(Ity_I32); + assign( oldV, mk_armg_calculate_flag_v() ); + assign( oldC, updC + ? mkU32((imm32 >> 31) & 1) + : mk_armg_calculate_flag_c() ); + setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, + condT ); + } + DIP("%s%s.w r%u, #%u\n", + isMVN ? "mvn" : "mov", bS ? "s" : "", rD, imm32); + goto decode_success; + } + } + + /* -------------- (T3) MOVW Rd, #imm16 -------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && INSN0(9,4) == BITS6(1,0,0,1,0,0) + && INSN1(15,15) == 0) { + UInt rD = INSN1(11,8); + if (!isBadRegT(rD)) { + UInt imm16 = (INSN0(3,0) << 12) | (INSN0(10,10) << 11) + | (INSN1(14,12) << 8) | INSN1(7,0); + putIRegT(rD, mkU32(imm16), condT); + DIP("movw r%u, #%u\n", rD, imm16); + goto decode_success; + } + } + + /* ---------------- MOVT Rd, #imm16 ---------------- */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && INSN0(9,4) == BITS6(1,0,1,1,0,0) + && INSN1(15,15) == 0) { + UInt rD = INSN1(11,8); + if (!isBadRegT(rD)) { + UInt imm16 = (INSN0(3,0) << 12) | (INSN0(10,10) << 11) + | (INSN1(14,12) << 8) | INSN1(7,0); + IRTemp res = newTemp(Ity_I32); + assign(res, + binop(Iop_Or32, + binop(Iop_And32, getIRegT(rD), mkU32(0xFFFF)), + mkU32(imm16 << 16))); + putIRegT(rD, mkexpr(res), condT); + DIP("movt r%u, #%u\n", rD, imm16); + goto decode_success; + } + } + + /* ---------------- LD/ST reg+/-#imm8 ---------------- */ + /* Loads and stores of the form: + op Rt, [Rn, #-imm8] or + op Rt, [Rn], #+/-imm8 or + op Rt, [Rn, #+/-imm8]! + where op is one of + ldrb ldrh ldr ldrsb ldrsh + strb strh str + */ + if (INSN0(15,9) == BITS7(1,1,1,1,1,0,0) && INSN1(11,11) == 1) { + Bool valid = True; + Bool syned = False; + Bool isST = False; + IRType ty = Ity_I8; + HChar* nm = "???"; + + switch (INSN0(8,4)) { + case BITS5(0,0,0,0,0): // strb + nm = "strb"; isST = True; break; + case BITS5(0,0,0,0,1): // ldrb + nm = "ldrb"; break; + case BITS5(1,0,0,0,1): // ldrsb + nm = "ldrsb"; syned = True; break; + case BITS5(0,0,0,1,0): // strh + nm = "strh"; ty = Ity_I16; isST = True; break; + case BITS5(0,0,0,1,1): // ldrh + nm = "ldrh"; ty = Ity_I16; break; + case BITS5(1,0,0,1,1): // ldrsh + nm = "ldrsh"; ty = Ity_I16; syned = True; break; + case BITS5(0,0,1,0,0): // str + nm = "str"; ty = Ity_I32; isST = True; break; + case BITS5(0,0,1,0,1): + nm = "ldr"; ty = Ity_I32; break; // ldr + default: + valid = False; break; + } + + UInt rN = INSN0(3,0); + UInt rT = INSN1(15,12); + UInt bP = INSN1(10,10); + UInt bU = INSN1(9,9); + UInt bW = INSN1(8,8); + UInt imm8 = INSN1(7,0); + Bool loadsPC = False; + + if (valid) { + if (bP == 1 && bU == 1 && bW == 0) + valid = False; + if (bP == 0 && bW == 0) + valid = False; + if (rN == 15) + valid = False; + if (bW == 1 && rN == rT) + valid = False; + if (ty == Ity_I8 || ty == Ity_I16) { + if (isBadRegT(rT)) + valid = False; + } else { + /* ty == Ity_I32 */ + if (isST && rT == 15) + valid = False; + if (!isST && rT == 15) + loadsPC = True; + } + } + + if (valid) { + // if it's a branch, it can't happen in the middle of an IT block + if (loadsPC) + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + // go uncond + mk_skip_over_T32_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRTemp preAddr = newTemp(Ity_I32); + assign(preAddr, getIRegT(rN)); + + IRTemp postAddr = newTemp(Ity_I32); + assign(postAddr, binop(bU == 1 ? Iop_Add32 : Iop_Sub32, + mkexpr(preAddr), mkU32(imm8))); + + IRTemp transAddr = bP == 1 ? postAddr : preAddr; + + if (isST) { + + /* Store. If necessary, update the base register before + the store itself, so that the common idiom of "str rX, + [sp, #-4]!" (store rX at sp-4, then do new sp = sp-4, + a.k.a "push rX") doesn't cause Memcheck to complain + that the access is below the stack pointer. Also, not + updating sp before the store confuses Valgrind's + dynamic stack-extending logic. So do it before the + store. Hence we need to snarf the store data before + doing the basereg update. */ + + /* get hold of the data to be stored */ + IRTemp oldRt = newTemp(Ity_I32); + assign(oldRt, getIRegT(rT)); + + /* Update Rn if necessary. */ + if (bW == 1) { + vassert(rN != rT); // assured by validity check above + putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID); + } + + /* generate the transfer */ + switch (ty) { + case Ity_I8: + storeLE(mkexpr(transAddr), + unop(Iop_32to8, mkexpr(oldRt))); + break; + case Ity_I16: + storeLE(mkexpr(transAddr), + unop(Iop_32to16, mkexpr(oldRt))); + break; + case Ity_I32: + storeLE(mkexpr(transAddr), mkexpr(oldRt)); + break; + default: + vassert(0); + } + + } else { + + /* Load. */ + + /* generate the transfer */ + IRTemp newRt = newTemp(Ity_I32); + IROp widen = Iop_INVALID; + switch (ty) { + case Ity_I8: + widen = syned ? Iop_8Sto32 : Iop_8Uto32; break; + case Ity_I16: + widen = syned ? Iop_16Sto32 : Iop_16Uto32; break; + case Ity_I32: + break; + default: + vassert(0); + } + if (widen == Iop_INVALID) { + assign(newRt, loadLE(ty, mkexpr(transAddr))); + } else { + assign(newRt, unop(widen, loadLE(ty, mkexpr(transAddr)))); + } + if (loadsPC) { + vassert(rT == 15); + llPutIReg(rT, mkexpr(newRt)); + } else { + putIRegT(rT, mkexpr(newRt), IRTemp_INVALID); + } + + if (loadsPC) { + /* Presumably this is an interworking branch. */ + irsb->next = mkexpr(newRt); + irsb->jumpkind = Ijk_Boring; /* or _Ret ? */ + dres.whatNext = Dis_StopHere; } + + /* Update Rn if necessary. */ + if (bW == 1) { + vassert(rN != rT); // assured by validity check above + putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID); + } + } + + if (bP == 1 && bW == 0) { + DIP("%s.w r%u, [r%u, #%c%u]\n", + nm, rT, rN, bU ? '+' : '-', imm8); } - if ((opc2 & 0xD) == 0xD) { - if ((opc1 & 0x05) == 0x00) { // load/store 2 words reg offset - goto decode_failure; + else if (bP == 1 && bW == 1) { + DIP("%s.w r%u, [r%u, #%c%u]!\n", + nm, rT, rN, bU ? '+' : '-', imm8); + } + else { + vassert(bP == 0 && bW == 1); + DIP("%s.w r%u, [r%u], #%c%u\n", + nm, rT, rN, bU ? '+' : '-', imm8); + } + + goto decode_success; + } + } + + /* ------------- LD/ST reg+(reg<next = mkexpr(newRt); + irsb->jumpkind = Ijk_Boring; /* or _Ret ? */ + dres.whatNext = Dis_StopHere; } } - } /* endif: Multiplies, extra load/store... */ - - /* - 'Misc' Instructions: ARM ARM A3-4 - */ - if ((opc1 & 0xF9) == 0x10) { // 0001 0xx0 - opc_tmp = toUChar((opc1 >> 1) & 0x3); - switch (opc2) { - case 0x0: - if ((opc_tmp & 0x1) == 0x0) { // move stat reg -> reg - goto decode_failure; - } else { // move reg -> stat reg - goto decode_failure; - } - - case 0x1: - if (opc_tmp == 0x1) { // branch/exchange instr set - goto decode_failure; - } - if (opc_tmp == 0x3) { // count leading zeros - goto decode_failure; + + DIP("%s.w r%u, [r%u, r%u, LSL #%u]\n", + nm, rT, rN, rM, imm2); + + goto decode_success; + } + } + + /* --------------- LD/ST reg+imm12 --------------- */ + /* Loads and stores of the form: + op Rt, [Rn, +#imm12] + where op is one of + ldrb ldrh ldr ldrsb ldrsh + strb strh str + */ + if (INSN0(15,9) == BITS7(1,1,1,1,1,0,0)) { + Bool valid = True; + Bool syned = False; + Bool isST = False; + IRType ty = Ity_I8; + HChar* nm = "???"; + + switch (INSN0(8,4)) { + case BITS5(0,1,0,0,0): // strb + nm = "strb"; isST = True; break; + case BITS5(0,1,0,0,1): // ldrb + nm = "ldrb"; break; + case BITS5(1,1,0,0,1): // ldrsb + nm = "ldrsb"; syned = True; break; + case BITS5(0,1,0,1,0): // strh + nm = "strh"; ty = Ity_I16; isST = True; break; + case BITS5(0,1,0,1,1): // ldrh + nm = "ldrh"; ty = Ity_I16; break; + case BITS5(1,1,0,1,1): // ldrsh + nm = "ldrsh"; ty = Ity_I16; syned = True; break; + case BITS5(0,1,1,0,0): // str + nm = "str"; ty = Ity_I32; isST = True; break; + case BITS5(0,1,1,0,1): + nm = "ldr"; ty = Ity_I32; break; // ldr + default: + valid = False; break; + } + + UInt rN = INSN0(3,0); + UInt rT = INSN1(15,12); + UInt imm12 = INSN1(11,0); + Bool loadsPC = False; + + if (ty == Ity_I8 || ty == Ity_I16) { + /* all 8- and 16-bit load and store cases have the + same exclusion set. */ + if (rN == 15 || isBadRegT(rT)) + valid = False; + } else { + vassert(ty == Ity_I32); + if (isST) { + if (rN == 15 || rT == 15) + valid = False; + } else { + /* For a 32-bit load, rT == 15 is only allowable if we not + in an IT block, or are the last in it. Need to insert + a dynamic check for that. Also, in this particular + case, rN == 15 is allowable. In this case however, the + value obtained for rN is (apparently) + "word-align(address of current insn + 4)". */ + if (rT == 15) + loadsPC = True; + } + } + + if (valid) { + // if it's a branch, it can't happen in the middle of an IT block + if (loadsPC) + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + // go uncond + mk_skip_over_T32_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRTemp rNt = newTemp(Ity_I32); + if (rN == 15) { + vassert(ty == Ity_I32 && !isST); + assign(rNt, binop(Iop_And32, getIRegT(rN), mkU32(~3))); + } else { + assign(rNt, getIRegT(rN)); + } + + IRTemp transAddr = newTemp(Ity_I32); + assign(transAddr, + binop( Iop_Add32, mkexpr(rNt), mkU32(imm12) )); + + if (isST) { + IRTemp oldRt = newTemp(Ity_I32); + assign(oldRt, getIRegT(rT)); + switch (ty) { + case Ity_I8: + storeLE(mkexpr(transAddr), + unop(Iop_32to8, mkexpr(oldRt))); + break; + case Ity_I16: + storeLE(mkexpr(transAddr), + unop(Iop_32to16, mkexpr(oldRt))); + break; + case Ity_I32: + storeLE(mkexpr(transAddr), mkexpr(oldRt)); + break; + default: + vassert(0); } - break; - - case 0x3: - if (opc_tmp == 0x1) { // branch & link/exchange instr set - goto decode_failure; + } else { + IRTemp newRt = newTemp(Ity_I32); + IROp widen = Iop_INVALID; + switch (ty) { + case Ity_I8: + widen = syned ? Iop_8Sto32 : Iop_8Uto32; break; + case Ity_I16: + widen = syned ? Iop_16Sto32 : Iop_16Uto32; break; + case Ity_I32: + break; + default: + vassert(0); } - break; - - case 0x5: // enhanced dsp add/subtracts - goto decode_failure; - - case 0x7: - if (opc_tmp == 0x1) { // software breakpoint - if (cond != 0xE) { // Unpredictable - ARM ARM A3-4 - vex_printf("disInstr(arm): Unpredictable instruction\n"); - goto decode_failure; - } - goto decode_failure; + if (widen == Iop_INVALID) { + assign(newRt, loadLE(ty, mkexpr(transAddr))); + } else { + assign(newRt, unop(widen, loadLE(ty, mkexpr(transAddr)))); } - break; - - case 0x8: case 0x9: case 0xA: // enhanced dsp multiplies - case 0xB: case 0xC: case 0xD: case 0xE: - goto decode_failure; - - default: break; - } - } /* endif: 'Misc' Instructions... */ - // fall through... - - case 0x2: - case 0x3: - if ((opc1 & 0xFB) == 0x30) goto decode_failure; // Undefined - ARM ARM A3-2 - - /* - A lonely 'MOV imm to status reg': - */ - if ((opc1 & 0xFB) == 0x32) { // 0011 0x10 - goto decode_failure; + putIRegT(rT, mkexpr(newRt), IRTemp_INVALID); + + if (loadsPC) { + /* Presumably this is an interworking branch. */ + irsb->next = mkexpr(newRt); + irsb->jumpkind = Ijk_Boring; /* or _Ret ? */ + dres.whatNext = Dis_StopHere; + } + } + + DIP("%s.w r%u, [r%u, +#%u]\n", nm, rT, rN, imm12); + + goto decode_success; } - - /* - Data Processing Instructions - (if we get here, it's a dpi) - */ - if (!dis_dataproc( theInstr )) { goto decode_failure; } - break; - + } - /* - Load/Store word | unsigned byte + /* -------------- LDRD/STRD reg+/-#imm8 -------------- */ + /* Doubleword loads and stores of the form: + ldrd/strd Rt, Rt2, [Rn, #-imm8] or + ldrd/strd Rt, Rt2, [Rn], #+/-imm8 or + ldrd/strd Rt, Rt2, [Rn, #+/-imm8]! */ - case 0x6: case 0x7: // LOAD/STORE reg offset - if ((opc2 & 0x1) == 0x1) goto decode_failure; // Undefined - ARM ARM A3-2 - - case 0x4: case 0x5: // LOAD/STORE imm offset - if (!dis_loadstore_w_ub(theInstr)) { goto decode_failure; } - break; - - /* - Load/Store multiple - */ - case 0x8: case 0x9: - if (!dis_loadstore_mult(theInstr)) { goto decode_failure; } - break; - - - /* - Branch, Branch and Link - */ - case 0xA: case 0xB: // B, BL - // B(L): L=1 => return address stored in link register (R14) - dis_branch(theInstr); - whatNext = Dis_StopHere; - break; - - - /* - Co-processor instructions - */ - case 0xC: case 0xD: // co-pro load/store & double reg trxfrs - goto decode_failure; - - case 0xE: - if ((opc2 & 0x1) == 0x0) { // co-pro data processing - goto decode_failure; - } else { // co-pro register transfers - goto decode_failure; + if (INSN0(15,9) == BITS7(1,1,1,0,1,0,0) && INSN0(6,6) == 1) { + UInt bP = INSN0(8,8); + UInt bU = INSN0(7,7); + UInt bW = INSN0(5,5); + UInt bL = INSN0(4,4); // 1: load 0: store + UInt rN = INSN0(3,0); + UInt rT = INSN1(15,12); + UInt rT2 = INSN1(11,8); + UInt imm8 = INSN1(7,0); + + Bool valid = True; + if (bP == 0 && bW == 0) valid = False; + if (bW == 1 && (rN == rT || rN == rT2)) valid = False; + if (isBadRegT(rT) || isBadRegT(rT2)) valid = False; + if (rN == 15) valid = False; + if (bL == 1 && rT == rT2) valid = False; + + if (valid) { + // go uncond + mk_skip_over_T32_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + IRTemp preAddr = newTemp(Ity_I32); + assign(preAddr, getIRegT(rN)); + + IRTemp postAddr = newTemp(Ity_I32); + assign(postAddr, binop(bU == 1 ? Iop_Add32 : Iop_Sub32, + mkexpr(preAddr), mkU32(imm8 << 2))); + + IRTemp transAddr = bP == 1 ? postAddr : preAddr; + + if (bL == 0) { + IRTemp oldRt = newTemp(Ity_I32); + IRTemp oldRt2 = newTemp(Ity_I32); + assign(oldRt, getIRegT(rT)); + assign(oldRt2, getIRegT(rT2)); + storeLE(mkexpr(transAddr), + mkexpr(oldRt)); + storeLE(binop(Iop_Add32, mkexpr(transAddr), mkU32(4)), + mkexpr(oldRt2)); + } else { + IRTemp newRt = newTemp(Ity_I32); + IRTemp newRt2 = newTemp(Ity_I32); + assign(newRt, + loadLE(Ity_I32, + mkexpr(transAddr))); + assign(newRt2, + loadLE(Ity_I32, + binop(Iop_Add32, mkexpr(transAddr), mkU32(4)))); + putIRegT(rT, mkexpr(newRt), IRTemp_INVALID); + putIRegT(rT2, mkexpr(newRt2), IRTemp_INVALID); + } + + if (bW == 1) { + putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID); + } + + HChar* nm = bL ? "ldrd" : "strd"; + + if (bP == 1 && bW == 0) { + DIP("%s.w r%u, r%u, [r%u, #%c%u]\n", + nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2); + } + else if (bP == 1 && bW == 1) { + DIP("%s.w r%u, r%u, [r%u, #%c%u]!\n", + nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2); + } + else { + vassert(bP == 0 && bW == 1); + DIP("%s.w r%u, r%u, [r%u], #%c%u\n", + nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2); + } + + goto decode_success; } - - - /* - Software Interrupt - */ - case 0xF: // swi - goto decode_failure; - - default: - decode_failure: + } + + /* -------------- (T3) Bcond.W label -------------- */ + /* This variant carries its own condition, so can't be part of an + IT block ... */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && INSN1(15,14) == BITS2(1,0) + && INSN1(12,12) == 0) { + UInt cond = INSN0(9,6); + if (cond != ARMCondAL && cond != ARMCondNV) { + Int simm21 + = (INSN0(10,10) << (1 + 1 + 6 + 11 + 1)) + | (INSN1(11,11) << (1 + 6 + 11 + 1)) + | (INSN1(13,13) << (6 + 11 + 1)) + | (INSN0(5,0) << (11 + 1)) + | (INSN1(10,0) << 1); + simm21 = (simm21 << 11) >> 11; + + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + UInt dst = simm21 + guest_R15_curr_instr_notENC + 4; + + /* Not allowed in an IT block; SIGILL if so. */ + gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate); + + IRTemp kondT = newTemp(Ity_I32); + assign( kondT, mk_armg_calculate_condition(cond) ); + stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(kondT)), + Ijk_Boring, + IRConst_U32(dst | 1/*CPSR.T*/) )); + irsb->next = mkU32( (guest_R15_curr_instr_notENC + 4) + | 1 /*CPSR.T*/ ); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + DIP("b%s.w 0x%x\n", nCC(cond), dst); + goto decode_success; + } + } + + /* ---------------- (T4) B.W label ---------------- */ + /* ... whereas this variant doesn't carry its own condition, so it + has to be either unconditional or the conditional by virtue of + being the last in an IT block. The upside is that there's 4 + more bits available for the jump offset, so it has a 16-times + greater branch range than the T3 variant. */ + if (INSN0(15,11) == BITS5(1,1,1,1,0) + && INSN1(15,14) == BITS2(1,0) + && INSN1(12,12) == 1) { + if (1) { + UInt bS = INSN0(10,10); + UInt bJ1 = INSN1(13,13); + UInt bJ2 = INSN1(11,11); + UInt bI1 = 1 ^ (bJ1 ^ bS); + UInt bI2 = 1 ^ (bJ2 ^ bS); + Int simm25 + = (bS << (1 + 1 + 10 + 11 + 1)) + | (bI1 << (1 + 10 + 11 + 1)) + | (bI2 << (10 + 11 + 1)) + | (INSN0(9,0) << (11 + 1)) + | (INSN1(10,0) << 1); + simm25 = (simm25 << 7) >> 7; + + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + UInt dst = simm25 + guest_R15_curr_instr_notENC + 4; + + /* If in an IT block, must be the last insn. */ + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + + // go uncond + mk_skip_over_T32_if_cond_is_false(condT); + condT = IRTemp_INVALID; + // now uncond + + // branch to dst + irsb->next = mkU32( dst | 1 /*CPSR.T*/ ); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + DIP("b.w 0x%x\n", dst); + goto decode_success; + } + } + + /* ------------------ TBB, TBH ------------------ */ + if (INSN0(15,4) == 0xE8D && INSN1(15,5) == 0x780) { + UInt rN = INSN0(3,0); + UInt rM = INSN1(3,0); + UInt bH = INSN1(4,4); + if (bH/*ATC*/ || (rN != 13 && !isBadRegT(rM))) { + /* Must be last or not-in IT block */ + gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate); + /* Go uncond */ + mk_skip_over_T32_if_cond_is_false(condT); + condT = IRTemp_INVALID; + + IRExpr* ea + = binop(Iop_Add32, + getIRegT(rN), + bH ? binop(Iop_Shl32, getIRegT(rM), mkU8(1)) + : getIRegT(rM)); + + IRTemp delta = newTemp(Ity_I32); + if (bH) { + assign(delta, unop(Iop_16Uto32, loadLE(Ity_I16, ea))); + } else { + assign(delta, unop(Iop_8Uto32, loadLE(Ity_I8, ea))); + } + + irsb->next + = binop(Iop_Or32, + binop(Iop_Add32, + getIRegT(15), + binop(Iop_Shl32, mkexpr(delta), mkU8(1)) + ), + mkU32(1) + ); + irsb->jumpkind = Ijk_Boring; + dres.whatNext = Dis_StopHere; + DIP("tb%c [r%u, r%u%s]\n", + bH ? 'h' : 'b', rN, rM, bH ? ", LSL #1" : ""); + goto decode_success; + } + } + + /* ------------------ UBFX ------------------ */ + /* ------------------ SBFX ------------------ */ + /* There's also ARM versions of same, but it doesn't seem worth the + hassle to common up the handling (it's only a couple of C + statements). */ + if ((INSN0(15,4) == 0xF3C // UBFX + || INSN0(15,4) == 0xF34) // SBFX + && INSN1(15,15) == 0 && INSN1(5,5) == 0) { + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt lsb = (INSN1(14,12) << 2) | INSN1(7,6); + UInt wm1 = INSN1(4,0); + UInt msb = lsb + wm1; + if (!isBadRegT(rD) && !isBadRegT(rN) && msb <= 31) { + Bool isU = INSN0(15,4) == 0xF3C; + IRTemp src = newTemp(Ity_I32); + IRTemp tmp = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + UInt mask = ((1 << wm1) - 1) + (1 << wm1); + vassert(msb >= 0 && msb <= 31); + vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive + + assign(src, getIRegT(rN)); + assign(tmp, binop(Iop_And32, + binop(Iop_Shr32, mkexpr(src), mkU8(lsb)), + mkU32(mask))); + assign(res, binop(isU ? Iop_Shr32 : Iop_Sar32, + binop(Iop_Shl32, mkexpr(tmp), mkU8(31-wm1)), + mkU8(31-wm1))); + + putIRegT(rD, mkexpr(res), condT); + + DIP("%s r%u, r%u, #%u, #%u\n", + isU ? "ubfx" : "sbfx", rD, rN, lsb, wm1 + 1); + goto decode_success; + } + } + + /* ------------------ UXTB ------------------ */ + /* ------------------ UXTH ------------------ */ + /* ------------------ SXTB ------------------ */ + /* ------------------ SXTH ------------------ */ + /* ----------------- UXTB16 ----------------- */ + /* ----------------- SXTB16 ----------------- */ + /* FIXME: this is an exact duplicate of the ARM version. They + should be commoned up. */ + if ((INSN0(15,0) == 0xFA5F // UXTB + || INSN0(15,0) == 0xFA1F // UXTH + || INSN0(15,0) == 0xFA4F // SXTB + || INSN0(15,0) == 0xFA0F // SXTH + || INSN0(15,0) == 0xFA3F // UXTB16 + || INSN0(15,0) == 0xFA2F) // SXTB16 + && INSN1(15,12) == BITS4(1,1,1,1) + && INSN1(7,6) == BITS2(1,0)) { + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + UInt rot = INSN1(5,4); + if (!isBadRegT(rD) && !isBadRegT(rM)) { + HChar* nm = "???"; + IRTemp srcT = newTemp(Ity_I32); + IRTemp rotT = newTemp(Ity_I32); + IRTemp dstT = newTemp(Ity_I32); + assign(srcT, getIRegT(rM)); + assign(rotT, genROR32(srcT, 8 * rot)); + switch (INSN0(15,0)) { + case 0xFA5F: // UXTB + nm = "uxtb"; + assign(dstT, unop(Iop_8Uto32, + unop(Iop_32to8, mkexpr(rotT)))); + break; + case 0xFA1F: // UXTH + nm = "uxth"; + assign(dstT, unop(Iop_16Uto32, + unop(Iop_32to16, mkexpr(rotT)))); + break; + case 0xFA4F: // SXTB + nm = "sxtb"; + assign(dstT, unop(Iop_8Sto32, + unop(Iop_32to8, mkexpr(rotT)))); + break; + case 0xFA0F: // SXTH + nm = "sxth"; + assign(dstT, unop(Iop_16Sto32, + unop(Iop_32to16, mkexpr(rotT)))); + break; + case 0xFA3F: // UXTB16 + nm = "uxtb16"; + assign(dstT, binop(Iop_And32, mkexpr(rotT), + mkU32(0x00FF00FF))); + break; + case 0xFA2F: { // SXTB16 + nm = "sxtb16"; + IRTemp lo32 = newTemp(Ity_I32); + IRTemp hi32 = newTemp(Ity_I32); + assign(lo32, binop(Iop_And32, mkexpr(rotT), mkU32(0xFF))); + assign(hi32, binop(Iop_Shr32, mkexpr(rotT), mkU8(16))); + assign( + dstT, + binop(Iop_Or32, + binop(Iop_And32, + unop(Iop_8Sto32, + unop(Iop_32to8, mkexpr(lo32))), + mkU32(0xFFFF)), + binop(Iop_Shl32, + unop(Iop_8Sto32, + unop(Iop_32to8, mkexpr(hi32))), + mkU8(16)) + )); + break; + } + default: + vassert(0); + } + putIRegT(rD, mkexpr(dstT), condT); + DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot); + goto decode_success; + } + } + + /* -------------- MUL.W Rd, Rn, Rm -------------- */ + if (INSN0(15,4) == 0xFB0 + && (INSN1(15,0) & 0xF0F0) == 0xF000) { + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) { + IRTemp res = newTemp(Ity_I32); + assign(res, binop(Iop_Mul32, getIRegT(rN), getIRegT(rM))); + putIRegT(rD, mkexpr(res), condT); + DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM); + goto decode_success; + } + } + + /* ------------------ {U,S}MULL ------------------ */ + if ((INSN0(15,4) == 0xFB8 || INSN0(15,4) == 0xFBA) + && INSN1(7,4) == BITS4(0,0,0,0)) { + UInt isU = INSN0(5,5); + UInt rN = INSN0(3,0); + UInt rDlo = INSN1(15,12); + UInt rDhi = INSN1(11,8); + UInt rM = INSN1(3,0); + if (!isBadRegT(rDhi) && !isBadRegT(rDlo) + && !isBadRegT(rN) && !isBadRegT(rM) && rDlo != rDhi) { + IRTemp res = newTemp(Ity_I64); + assign(res, binop(isU ? Iop_MullU32 : Iop_MullS32, + getIRegT(rN), getIRegT(rM))); + putIRegT( rDhi, unop(Iop_64HIto32, mkexpr(res)), condT ); + putIRegT( rDlo, unop(Iop_64to32, mkexpr(res)), condT ); + DIP("%cmull r%u, r%u, r%u, r%u\n", + isU ? 'u' : 's', rDlo, rDhi, rN, rM); + goto decode_success; + } + } + + /* ------------------ ML{A,S} ------------------ */ + if (INSN0(15,4) == 0xFB0 + && ( INSN1(7,4) == BITS4(0,0,0,0) // MLA + || INSN1(7,4) == BITS4(0,0,0,1))) { // MLS + UInt rN = INSN0(3,0); + UInt rA = INSN1(15,12); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + if (!isBadRegT(rD) && !isBadRegT(rN) + && !isBadRegT(rM) && !isBadRegT(rA)) { + Bool isMLA = INSN1(7,4) == BITS4(0,0,0,0); + IRTemp res = newTemp(Ity_I32); + assign(res, + binop(isMLA ? Iop_Add32 : Iop_Sub32, + getIRegT(rA), + binop(Iop_Mul32, getIRegT(rN), getIRegT(rM)))); + putIRegT(rD, mkexpr(res), condT); + DIP("%s r%u, r%u, r%u, r%u\n", + isMLA ? "mla" : "mls", rD, rN, rM, rA); + goto decode_success; + } + } + + /* ------------------ (T3) ADR ------------------ */ + if ((INSN0(15,0) == 0xF20F || INSN0(15,0) == 0xF60F) + && INSN1(15,15) == 0) { + /* rD = align4(PC) + imm32 */ + UInt rD = INSN1(11,8); + if (!isBadRegT(rD)) { + UInt imm32 = (INSN0(10,10) << 11) + | (INSN1(14,12) << 8) | INSN1(7,0); + putIRegT(rD, binop(Iop_Add32, + binop(Iop_And32, getIRegT(15), mkU32(~3U)), + mkU32(imm32)), + condT); + DIP("add r%u, pc, #%u\n", rD, imm32); + goto decode_success; + } + } + + /* ----------------- (T1) UMLAL ----------------- */ + /* ----------------- (T1) SMLAL ----------------- */ + if ((INSN0(15,4) == 0xFBE // UMLAL + || INSN0(15,4) == 0xFBC) // SMLAL + && INSN1(7,4) == BITS4(0,0,0,0)) { + UInt rN = INSN0(3,0); + UInt rDlo = INSN1(15,12); + UInt rDhi = INSN1(11,8); + UInt rM = INSN1(3,0); + if (!isBadRegT(rDlo) && !isBadRegT(rDhi) && !isBadRegT(rN) + && !isBadRegT(rM) && rDhi != rDlo) { + Bool isS = INSN0(15,4) == 0xFBC; + IRTemp argL = newTemp(Ity_I32); + IRTemp argR = newTemp(Ity_I32); + IRTemp old = newTemp(Ity_I64); + IRTemp res = newTemp(Ity_I64); + IRTemp resHi = newTemp(Ity_I32); + IRTemp resLo = newTemp(Ity_I32); + IROp mulOp = isS ? Iop_MullS32 : Iop_MullU32; + assign( argL, getIRegT(rM)); + assign( argR, getIRegT(rN)); + assign( old, binop(Iop_32HLto64, getIRegT(rDhi), getIRegT(rDlo)) ); + assign( res, binop(Iop_Add64, + mkexpr(old), + binop(mulOp, mkexpr(argL), mkexpr(argR))) ); + assign( resHi, unop(Iop_64HIto32, mkexpr(res)) ); + assign( resLo, unop(Iop_64to32, mkexpr(res)) ); + putIRegT( rDhi, mkexpr(resHi), condT ); + putIRegT( rDlo, mkexpr(resLo), condT ); + DIP("%cmlal r%u, r%u, r%u, r%u\n", + isS ? 's' : 'u', rDlo, rDhi, rN, rM); + goto decode_success; + } + } + + /* ------------------ (T2) ADR ------------------ */ + if ((INSN0(15,0) == 0xF2AF || INSN0(15,0) == 0xF6AF) + && INSN1(15,15) == 0) { + /* rD = align4(PC) - imm32 */ + UInt rD = INSN1(11,8); + if (!isBadRegT(rD)) { + UInt imm32 = (INSN0(10,10) << 11) + | (INSN1(14,12) << 8) | INSN1(7,0); + putIRegT(rD, binop(Iop_Sub32, + binop(Iop_And32, getIRegT(15), mkU32(~3U)), + mkU32(imm32)), + condT); + DIP("sub r%u, pc, #%u\n", rD, imm32); + goto decode_success; + } + } + + /* ------------------- (T1) BFI ------------------- */ + /* ------------------- (T1) BFC ------------------- */ + if (INSN0(15,4) == 0xF36 && INSN1(15,15) == 0 && INSN1(5,5) == 0) { + UInt rD = INSN1(11,8); + UInt rN = INSN0(3,0); + UInt msb = INSN1(4,0); + UInt lsb = (INSN1(14,12) << 2) | INSN1(7,6); + if (isBadRegT(rD) || rN == 13 || msb < lsb) { + /* undecodable; fall through */ + } else { + IRTemp src = newTemp(Ity_I32); + IRTemp olddst = newTemp(Ity_I32); + IRTemp newdst = newTemp(Ity_I32); + UInt mask = 1 << (msb - lsb); + mask = (mask - 1) + mask; + vassert(mask != 0); // guaranteed by "msb < lsb" check above + mask <<= lsb; + + assign(src, rN == 15 ? mkU32(0) : getIRegT(rN)); + assign(olddst, getIRegT(rD)); + assign(newdst, + binop(Iop_Or32, + binop(Iop_And32, + binop(Iop_Shl32, mkexpr(src), mkU8(lsb)), + mkU32(mask)), + binop(Iop_And32, + mkexpr(olddst), + mkU32(~mask))) + ); + + putIRegT(rD, mkexpr(newdst), condT); + + if (rN == 15) { + DIP("bfc r%u, #%u, #%u\n", + rD, lsb, msb-lsb+1); + } else { + DIP("bfi r%u, r%u, #%u, #%u\n", + rD, rN, lsb, msb-lsb+1); + } + goto decode_success; + } + } + + /* ------------------- (T1) SXTAH ------------------- */ + /* ------------------- (T1) UXTAH ------------------- */ + if ((INSN0(15,4) == 0xFA1 // UXTAH + || INSN0(15,4) == 0xFA0) // SXTAH + && INSN1(15,12) == BITS4(1,1,1,1) + && INSN1(7,6) == BITS2(1,0)) { + Bool isU = INSN0(15,4) == 0xFA1; + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + UInt rot = INSN1(5,4); + if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) { + IRTemp srcL = newTemp(Ity_I32); + IRTemp srcR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign(srcR, getIRegT(rM)); + assign(srcL, getIRegT(rN)); + assign(res, binop(Iop_Add32, + mkexpr(srcL), + unop(isU ? Iop_16Uto32 : Iop_16Sto32, + unop(Iop_32to16, + genROR32(srcR, 8 * rot))))); + putIRegT(rD, mkexpr(res), condT); + DIP("%cxtah r%u, r%u, r%u, ror #%u\n", + isU ? 'u' : 's', rD, rN, rM, rot); + goto decode_success; + } + } + + /* ------------------- (T1) SXTAB ------------------- */ + /* ------------------- (T1) UXTAB ------------------- */ + if ((INSN0(15,4) == 0xFA5 // UXTAB + || INSN0(15,4) == 0xFA4) // SXTAB + && INSN1(15,12) == BITS4(1,1,1,1) + && INSN1(7,6) == BITS2(1,0)) { + Bool isU = INSN0(15,4) == 0xFA5; + UInt rN = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + UInt rot = INSN1(5,4); + if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) { + IRTemp srcL = newTemp(Ity_I32); + IRTemp srcR = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign(srcR, getIRegT(rM)); + assign(srcL, getIRegT(rN)); + assign(res, binop(Iop_Add32, + mkexpr(srcL), + unop(isU ? Iop_8Uto32 : Iop_8Sto32, + unop(Iop_32to8, + genROR32(srcR, 8 * rot))))); + putIRegT(rD, mkexpr(res), condT); + DIP("%cxtab r%u, r%u, r%u, ror #%u\n", + isU ? 'u' : 's', rD, rN, rM, rot); + goto decode_success; + } + } + + /* ------------------- (T1) CLZ ------------------- */ + if (INSN0(15,4) == 0xFAB + && INSN1(15,12) == BITS4(1,1,1,1) + && INSN1(7,4) == BITS4(1,0,0,0)) { + UInt rM1 = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM2 = INSN1(3,0); + if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) { + IRTemp arg = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_I32); + assign(arg, getIRegT(rM1)); + assign(res, IRExpr_Mux0X( + unop(Iop_1Uto8,binop(Iop_CmpEQ32, + mkexpr(arg), + mkU32(0))), + unop(Iop_Clz32, mkexpr(arg)), + mkU32(32) + )); + putIRegT(rD, mkexpr(res), condT); + DIP("clz r%u, r%u\n", rD, rM1); + goto decode_success; + } + } + + /* ------------------- (T1) RBIT ------------------- */ + if (INSN0(15,4) == 0xFA9 + && INSN1(15,12) == BITS4(1,1,1,1) + && INSN1(7,4) == BITS4(1,0,1,0)) { + UInt rM1 = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM2 = INSN1(3,0); + if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) { + IRTemp arg = newTemp(Ity_I32); + assign(arg, getIRegT(rM1)); + IRTemp res = gen_BITREV(arg); + putIRegT(rD, mkexpr(res), condT); + DIP("rbit r%u, r%u\n", rD, rM1); + goto decode_success; + } + } + + /* ------------------- (T2) REV ------------------- */ + /* ------------------- (T2) REV16 ------------------- */ + if (INSN0(15,4) == 0xFA9 + && INSN1(15,12) == BITS4(1,1,1,1) + && ( INSN1(7,4) == BITS4(1,0,0,0) // REV + || INSN1(7,4) == BITS4(1,0,0,1))) { // REV16 + UInt rM1 = INSN0(3,0); + UInt rD = INSN1(11,8); + UInt rM2 = INSN1(3,0); + Bool isREV = INSN1(7,4) == BITS4(1,0,0,0); + if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) { + IRTemp arg = newTemp(Ity_I32); + assign(arg, getIRegT(rM1)); + IRTemp res = isREV ? gen_REV(arg) : gen_REV16(arg); + putIRegT(rD, mkexpr(res), condT); + DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM1); + goto decode_success; + } + } + + /* -------------- (T1) MSR apsr, reg -------------- */ + if (INSN0(15,4) == 0xF38 + && INSN1(15,12) == BITS4(1,0,0,0) && INSN1(9,0) == 0x000) { + UInt rN = INSN0(3,0); + UInt write_ge = INSN1(10,10); + UInt write_nzcvq = INSN1(11,11); + if (!isBadRegT(rN) && (write_nzcvq || write_ge)) { + IRTemp rNt = newTemp(Ity_I32); + assign(rNt, getIRegT(rN)); + desynthesise_APSR( write_nzcvq, write_ge, rNt, condT ); + DIP("msr cpsr_%s%s, r%u\n", + write_nzcvq ? "f" : "", write_ge ? "g" : "", rN); + goto decode_success; + } + } + + /* -------------- (T1) MRS reg, apsr -------------- */ + if (INSN0(15,0) == 0xF3EF + && INSN1(15,12) == BITS4(1,0,0,0) && INSN1(7,0) == 0x00) { + UInt rD = INSN1(11,8); + if (!isBadRegT(rD)) { + IRTemp apsr = synthesise_APSR(); + putIRegT( rD, mkexpr(apsr), condT ); + DIP("mrs r%u, cpsr\n", rD); + goto decode_success; + } + } + + /* ----------------- (T1) LDREX ----------------- */ + if (INSN0(15,4) == 0xE85 && INSN1(11,8) == BITS4(1,1,1,1)) { + UInt rN = INSN0(3,0); + UInt rT = INSN1(15,12); + UInt imm8 = INSN1(7,0); + if (!isBadRegT(rT) && rN != 15) { + IRTemp res; + // go uncond + mk_skip_over_T32_if_cond_is_false( condT ); + // now uncond + res = newTemp(Ity_I32); + stmt( IRStmt_LLSC(Iend_LE, + res, + binop(Iop_Add32, getIRegT(rN), mkU32(imm8 * 4)), + NULL/*this is a load*/ )); + putIRegT(rT, mkexpr(res), IRTemp_INVALID); + DIP("ldrex r%u, [r%u, #+%u]\n", rT, rN, imm8 * 4); + goto decode_success; + } + } + + /* ----------------- (T1) STREX ----------------- */ + if (INSN0(15,4) == 0xE84) { + UInt rN = INSN0(3,0); + UInt rT = INSN1(15,12); + UInt rD = INSN1(11,8); + UInt imm8 = INSN1(7,0); + if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15 + && rD != rN && rD != rT) { + IRTemp resSC1, resSC32; + + // go uncond + mk_skip_over_T32_if_cond_is_false( condT ); + // now uncond + + /* Ok, now we're unconditional. Do the store. */ + resSC1 = newTemp(Ity_I1); + stmt( IRStmt_LLSC(Iend_LE, + resSC1, + binop(Iop_Add32, getIRegT(rN), mkU32(imm8 * 4)), + getIRegT(rT)) ); + + /* Set rD to 1 on failure, 0 on success. Currently we have + resSC1 == 0 on failure, 1 on success. */ + resSC32 = newTemp(Ity_I32); + assign(resSC32, + unop(Iop_1Uto32, unop(Iop_Not1, mkexpr(resSC1)))); + + putIRegT(rD, mkexpr(resSC32), IRTemp_INVALID); + DIP("strex r%u, r%u, [r%u, #+%u]\n", rD, rT, rN, imm8 * 4); + goto decode_success; + } + } + + /* -------------- v7 barrier insns -------------- */ + if (INSN0(15,0) == 0xF3BF && (INSN1(15,0) & 0xFF0F) == 0x8F0F) { + /* XXX this isn't really right, is it? The generated IR does + them unconditionally. I guess it doesn't matter since it + doesn't do any harm to do them even when the guarding + condition is false -- it's just a performance loss. */ + switch (INSN1(7,4)) { + case 0x4: /* DSB */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("DSB\n"); + goto decode_success; + case 0x5: /* DMB */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("DMB\n"); + goto decode_success; + case 0x6: /* ISB */ + stmt( IRStmt_MBE(Imbe_Fence) ); + DIP("ISB\n"); + goto decode_success; + default: + break; + } + } + + /* ------------------- NOP ------------------ */ + if (INSN0(15,0) == 0xF3AF && INSN1(15,0) == 0x8000) { + DIP("nop\n"); + goto decode_success; + } + + /* ----------------------------------------------------------- */ + /* -- VFP (CP 10, CP 11) instructions (in Thumb mode) -- */ + /* ----------------------------------------------------------- */ + + if (INSN0(15,12) == BITS4(1,1,1,0)) { + UInt insn28 = (INSN0(11,0) << 16) | INSN1(15,0); + Bool ok_vfp = decode_CP10_CP11_instruction ( + &dres, insn28, condT, ARMCondAL/*bogus*/, + True/*isT*/ + ); + if (ok_vfp) + goto decode_success; + } + + /* ----------------------------------------------------------- */ + /* -- NEON instructions (in Thumb mode) -- */ + /* ----------------------------------------------------------- */ + + if (archinfo->hwcaps & VEX_HWCAPS_ARM_NEON) { + UInt insn32 = (INSN0(15,0) << 16) | INSN1(15,0); + Bool ok_neon = decode_NEON_instruction( + &dres, insn32, condT, True/*isT*/ + ); + if (ok_neon) + goto decode_success; + } + + /* ----------------------------------------------------------- */ + /* -- v6 media instructions (in Thumb mode) -- */ + /* ----------------------------------------------------------- */ + + { UInt insn32 = (INSN0(15,0) << 16) | INSN1(15,0); + Bool ok_v6m = decode_V6MEDIA_instruction( + &dres, insn32, condT, ARMCondAL/*bogus*/, + True/*isT*/ + ); + if (ok_v6m) + goto decode_success; + } + + /* ----------------------------------------------------------- */ + /* -- Undecodable -- */ + /* ----------------------------------------------------------- */ + + goto decode_failure; + /*NOTREACHED*/ + + decode_failure: /* All decode failures end up here. */ - vex_printf("disInstr(arm): unhandled instruction: " - "0x%x\n", theInstr); - vpanic("armToIR: unimplemented insn"); - - } /* switch (opc) for the main (primary) opcode switch. */ - + vex_printf("disInstr(thumb): unhandled instruction: " + "0x%04x 0x%04x\n", (UInt)insn0, (UInt)insn1); + + /* Back up ITSTATE to the initial value for this instruction. + If we don't do that, any subsequent restart of the instruction + will restart with the wrong value. */ + put_ITSTATE(old_itstate); + /* Tell the dispatcher that this insn cannot be decoded, and so has + not been executed, and (is currently) the next to be executed. + R15 should be up-to-date since it made so at the start of each + insn, but nevertheless be paranoid and update it again right + now. */ + vassert(0 == (guest_R15_curr_instr_notENC & 1)); + llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC | 1) ); + irsb->next = mkU32(guest_R15_curr_instr_notENC | 1 /* CPSR.T */); + irsb->jumpkind = Ijk_NoDecode; + dres.whatNext = Dis_StopHere; + dres.len = 0; + return dres; + decode_success: /* All decode successes end up here. */ -// vex_printf("disInstr(arm): success"); DIP("\n"); - - *size = 4; - return whatNext; + + vassert(dres.len == 2 || dres.len == 4 || dres.len == 20); + +#if 0 + // XXX is this necessary on Thumb? + /* Now then. Do we have an implicit jump to r15 to deal with? */ + if (r15written) { + /* If we get jump to deal with, we assume that there's been no + other competing branch stuff previously generated for this + insn. That's reasonable, in the sense that the ARM insn set + appears to declare as "Unpredictable" any instruction which + generates more than one possible new value for r15. Hence + just assert. The decoders themselves should check against + all such instructions which are thusly Unpredictable, and + decline to decode them. Hence we should never get here if we + have competing new values for r15, and hence it is safe to + assert here. */ + vassert(dres.whatNext == Dis_Continue); + vassert(irsb->next == NULL); + vassert(irsb->jumpkind = Ijk_Boring); + /* If r15 is unconditionally written, terminate the block by + jumping to it. If it's conditionally written, still + terminate the block (a shame, but we can't do side exits to + arbitrary destinations), but first jump to the next + instruction if the condition doesn't hold. */ + /* We can't use getIRegT(15) to get the destination, since that + will produce r15+4, which isn't what we want. Must use + llGetIReg(15) instead. */ + if (r15guard == IRTemp_INVALID) { + /* unconditional */ + } else { + /* conditional */ + stmt( IRStmt_Exit( + unop(Iop_32to1, + binop(Iop_Xor32, + mkexpr(r15guard), mkU32(1))), + r15kind, + IRConst_U32(guest_R15_curr_instr_notENC + 4) + )); + } + irsb->next = llGetIReg(15); + irsb->jumpkind = r15kind; + dres.whatNext = Dis_StopHere; + } +#endif + + return dres; + +# undef INSN0 +# undef INSN1 } #undef DIP #undef DIS + +/*------------------------------------------------------------*/ +/*--- Top-level fn ---*/ +/*------------------------------------------------------------*/ + +/* Disassemble a single instruction into IR. The instruction + is located in host memory at &guest_code[delta]. */ + +DisResult disInstr_ARM ( IRSB* irsb_IN, + Bool put_IP, + Bool (*resteerOkFn) ( void*, Addr64 ), + Bool resteerCisOk, + void* callback_opaque, + UChar* guest_code_IN, + Long delta_ENCODED, + Addr64 guest_IP_ENCODED, + VexArch guest_arch, + VexArchInfo* archinfo, + VexAbiInfo* abiinfo, + Bool host_bigendian_IN ) +{ + DisResult dres; + Bool isThumb = (Bool)(guest_IP_ENCODED & 1); + + /* Set globals (see top of this file) */ + vassert(guest_arch == VexArchARM); + + irsb = irsb_IN; + host_is_bigendian = host_bigendian_IN; + __curr_is_Thumb = isThumb; + + if (isThumb) { + guest_R15_curr_instr_notENC = (Addr32)guest_IP_ENCODED - 1; + } else { + guest_R15_curr_instr_notENC = (Addr32)guest_IP_ENCODED; + } + + if (isThumb) { + dres = disInstr_THUMB_WRK ( put_IP, resteerOkFn, + resteerCisOk, callback_opaque, + &guest_code_IN[delta_ENCODED - 1], + archinfo, abiinfo ); + } else { + dres = disInstr_ARM_WRK ( put_IP, resteerOkFn, + resteerCisOk, callback_opaque, + &guest_code_IN[delta_ENCODED], + archinfo, abiinfo ); + } + + return dres; +} + +/* Test program for the conversion of IRCmpF64Result values to VFP + nzcv values. See handling of FCMPD et al above. */ +/* +UInt foo ( UInt x ) +{ + UInt ix = ((x >> 5) & 3) | (x & 1); + UInt termL = (((((ix ^ 1) << 30) - 1) >> 29) + 1); + UInt termR = (ix & (ix >> 1) & 1); + return termL - termR; +} + +void try ( char* s, UInt ir, UInt req ) +{ + UInt act = foo(ir); + printf("%s 0x%02x -> req %d%d%d%d act %d%d%d%d (0x%x)\n", + s, ir, (req >> 3) & 1, (req >> 2) & 1, + (req >> 1) & 1, (req >> 0) & 1, + (act >> 3) & 1, (act >> 2) & 1, + (act >> 1) & 1, (act >> 0) & 1, act); + +} + +int main ( void ) +{ + printf("\n"); + try("UN", 0x45, 0b0011); + try("LT", 0x01, 0b1000); + try("GT", 0x00, 0b0010); + try("EQ", 0x40, 0b0110); + printf("\n"); + return 0; +} +*/ + /*--------------------------------------------------------------------*/ /*--- end guest_arm_toIR.c ---*/ /*--------------------------------------------------------------------*/ diff --git a/VEX/priv/guest_generic_bb_to_IR.c b/VEX/priv/guest_generic_bb_to_IR.c index 763b50f..f7dc020 100644 --- a/VEX/priv/guest_generic_bb_to_IR.c +++ b/VEX/priv/guest_generic_bb_to_IR.c @@ -1,42 +1,31 @@ /*--------------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_generic_bb_to_IR.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_generic_bb_to_IR.c ---*/ /*--------------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -54,9 +43,31 @@ /* Forwards .. */ __attribute__((regparm(2))) -static UInt genericg_compute_checksum_4al_4plus ( HWord addr, HWord len ); -__attribute__((regparm(2))) -static UInt genericg_compute_checksum_generic ( HWord addr, HWord len ); +static UInt genericg_compute_checksum_4al ( HWord first_w32, HWord n_w32s ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_1 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_2 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_3 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_4 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_5 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_6 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_7 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_8 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_9 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_10 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_11 ( HWord first_w32 ); +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_12 ( HWord first_w32 ); /* Small helpers */ static Bool const_False ( void* callback_opaque, Addr64 a ) { @@ -121,6 +132,7 @@ IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge, IRSB* irsb; Addr64 guest_IP_curr_instr; IRConst* guest_IP_bbstart_IRConst = NULL; + Int n_cond_resteers_allowed = 2; Bool (*resteerOKfn)(void*,Addr64) = NULL; @@ -209,6 +221,15 @@ IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge, resteerOKfn = resteerOK ? chase_into_ok : const_False; + /* n_cond_resteers_allowed keeps track of whether we're still + allowing dis_instr_fn to chase conditional branches. It + starts (at 2) and gets decremented each time dis_instr_fn + tells us it has chased a conditional branch. We then + decrement it, and use it to tell later calls to dis_instr_fn + whether or not it is allowed to chase conditional + branches. */ + vassert(n_cond_resteers_allowed >= 0 && n_cond_resteers_allowed <= 2); + /* This is the IP of the instruction we're just about to deal with. */ guest_IP_curr_instr = guest_IP_bbstart + delta; @@ -231,6 +252,7 @@ IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge, dres = dis_instr_fn ( irsb, need_to_put_IP, resteerOKfn, + toBool(n_cond_resteers_allowed > 0), callback_opaque, guest_code, delta, @@ -243,10 +265,17 @@ IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge, /* stay sane ... */ vassert(dres.whatNext == Dis_StopHere || dres.whatNext == Dis_Continue - || dres.whatNext == Dis_Resteer); + || dres.whatNext == Dis_ResteerU + || dres.whatNext == Dis_ResteerC); + /* ... disassembled insn length is sane ... */ vassert(dres.len >= 0 && dres.len <= 20); - if (dres.whatNext != Dis_Resteer) + /* ... continueAt is zero if no resteer requested ... */ + if (dres.whatNext != Dis_ResteerU && dres.whatNext != Dis_ResteerC) vassert(dres.continueAt == 0); + /* ... if we disallowed conditional resteers, check that one + didn't actually happen anyway ... */ + if (n_cond_resteers_allowed == 0) + vassert(dres.whatNext != Dis_ResteerC); /* Fill in the insn-mark length field. */ vassert(first_stmt_idx >= 0 && first_stmt_idx < irsb->stmts_used); @@ -313,10 +342,15 @@ IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge, case Dis_StopHere: vassert(irsb->next != NULL); goto done; - case Dis_Resteer: + case Dis_ResteerU: + case Dis_ResteerC: /* Check that we actually allowed a resteer .. */ vassert(resteerOK); vassert(irsb->next == NULL); + if (dres.whatNext == Dis_ResteerC) { + vassert(n_cond_resteers_allowed > 0); + n_cond_resteers_allowed--; + } /* figure out a new delta to continue at. */ vassert(resteerOKfn(callback_opaque,dres.continueAt)); delta = dres.continueAt - guest_IP_bbstart; @@ -341,13 +375,40 @@ IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge, done: /* We're done. The only thing that might need attending to is that - a self-checking preamble may need to be created. */ + a self-checking preamble may need to be created. + + The scheme is to compute a rather crude checksum of the code + we're making a translation of, and add to the IR a call to a + helper routine which recomputes the checksum every time the + translation is run, and requests a retranslation if it doesn't + match. This is obviously very expensive and considerable + efforts are made to speed it up: + + * the checksum is computed from all the 32-bit words that + overlap the translated code. That means it could depend on up + to 3 bytes before and 3 bytes after which aren't part of the + translated area, and so if those change then we'll + unnecessarily have to discard and retranslate. This seems + like a pretty remote possibility and it seems as if the + benefit of not having to deal with the ends of the range at + byte precision far outweigh any possible extra translations + needed. + + * there's a generic routine and 12 specialised cases, which + handle the cases of 1 through 12-word lengths respectively. + They seem to cover about 90% of the cases that occur in + practice. + */ if (do_self_check) { UInt len2check, expected32; IRTemp tistart_tmp, tilen_tmp; - UInt (*checksum_fn)(HWord, HWord) __attribute__((regparm(2))); - HWord checksum_fn_entry; + UInt (*fn_generic)(HWord, HWord) __attribute__((regparm(2))); + UInt (*fn_spec)(HWord) __attribute__((regparm(1))); + HChar* nm_generic; + HChar* nm_spec; + HWord fn_generic_entry = 0; + HWord fn_spec_entry = 0; vassert(vge->n_used == 1); len2check = vge->len[0]; @@ -355,65 +416,134 @@ IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge, /* stay sane */ vassert(len2check >= 0 && len2check < 1000/*arbitrary*/); - if (len2check >= 4 && 0 == (((HWord)guest_code) & 3)) { - checksum_fn = genericg_compute_checksum_4al_4plus; - } else { - checksum_fn = genericg_compute_checksum_generic; - } + /* Skip the check if the translation involved zero bytes */ + if (len2check > 0) { + HWord first_w32 = ((HWord)guest_code) & ~(HWord)3; + HWord last_w32 = (((HWord)guest_code) + len2check - 1) & ~(HWord)3; + vassert(first_w32 <= last_w32); + HWord w32_diff = last_w32 - first_w32; + vassert(0 == (w32_diff & 3)); + HWord w32s_to_check = (w32_diff + 4) / 4; + vassert(w32s_to_check > 0 && w32s_to_check < 1004/*arbitrary*//4); + + /* vex_printf("%lx %lx %ld\n", first_w32, last_w32, w32s_to_check); */ + + fn_generic = genericg_compute_checksum_4al; + nm_generic = "genericg_compute_checksum_4al"; + fn_spec = NULL; + nm_spec = NULL; + + switch (w32s_to_check) { + case 1: fn_spec = genericg_compute_checksum_4al_1; + nm_spec = "genericg_compute_checksum_4al_1"; break; + case 2: fn_spec = genericg_compute_checksum_4al_2; + nm_spec = "genericg_compute_checksum_4al_2"; break; + case 3: fn_spec = genericg_compute_checksum_4al_3; + nm_spec = "genericg_compute_checksum_4al_3"; break; + case 4: fn_spec = genericg_compute_checksum_4al_4; + nm_spec = "genericg_compute_checksum_4al_4"; break; + case 5: fn_spec = genericg_compute_checksum_4al_5; + nm_spec = "genericg_compute_checksum_4al_5"; break; + case 6: fn_spec = genericg_compute_checksum_4al_6; + nm_spec = "genericg_compute_checksum_4al_6"; break; + case 7: fn_spec = genericg_compute_checksum_4al_7; + nm_spec = "genericg_compute_checksum_4al_7"; break; + case 8: fn_spec = genericg_compute_checksum_4al_8; + nm_spec = "genericg_compute_checksum_4al_8"; break; + case 9: fn_spec = genericg_compute_checksum_4al_9; + nm_spec = "genericg_compute_checksum_4al_9"; break; + case 10: fn_spec = genericg_compute_checksum_4al_10; + nm_spec = "genericg_compute_checksum_4al_10"; break; + case 11: fn_spec = genericg_compute_checksum_4al_11; + nm_spec = "genericg_compute_checksum_4al_11"; break; + case 12: fn_spec = genericg_compute_checksum_4al_12; + nm_spec = "genericg_compute_checksum_4al_12"; break; + default: break; + } - expected32 = checksum_fn( (HWord)guest_code, len2check ); + expected32 = fn_generic( first_w32, w32s_to_check ); + /* If we got a specialised version, check it produces the same + result as the generic version! */ + if (fn_spec) { + vassert(nm_spec); + vassert(expected32 == fn_spec( first_w32 )); + } else { + vassert(!nm_spec); + } - /* Set TISTART and TILEN. These will describe to the despatcher - the area of guest code to invalidate should we exit with a - self-check failure. */ + /* Set TISTART and TILEN. These will describe to the despatcher + the area of guest code to invalidate should we exit with a + self-check failure. */ - tistart_tmp = newIRTemp(irsb->tyenv, guest_word_type); - tilen_tmp = newIRTemp(irsb->tyenv, guest_word_type); + tistart_tmp = newIRTemp(irsb->tyenv, guest_word_type); + tilen_tmp = newIRTemp(irsb->tyenv, guest_word_type); - irsb->stmts[selfcheck_idx+0] - = IRStmt_WrTmp(tistart_tmp, IRExpr_Const(guest_IP_bbstart_IRConst) ); + irsb->stmts[selfcheck_idx+0] + = IRStmt_WrTmp(tistart_tmp, IRExpr_Const(guest_IP_bbstart_IRConst) ); - irsb->stmts[selfcheck_idx+1] - = IRStmt_WrTmp(tilen_tmp, - guest_word_type==Ity_I32 - ? IRExpr_Const(IRConst_U32(len2check)) - : IRExpr_Const(IRConst_U64(len2check)) - ); + irsb->stmts[selfcheck_idx+1] + = IRStmt_WrTmp(tilen_tmp, + guest_word_type==Ity_I32 + ? IRExpr_Const(IRConst_U32(len2check)) + : IRExpr_Const(IRConst_U64(len2check)) + ); - irsb->stmts[selfcheck_idx+2] - = IRStmt_Put( offB_TISTART, IRExpr_RdTmp(tistart_tmp) ); + irsb->stmts[selfcheck_idx+2] + = IRStmt_Put( offB_TISTART, IRExpr_RdTmp(tistart_tmp) ); - irsb->stmts[selfcheck_idx+3] - = IRStmt_Put( offB_TILEN, IRExpr_RdTmp(tilen_tmp) ); + irsb->stmts[selfcheck_idx+3] + = IRStmt_Put( offB_TILEN, IRExpr_RdTmp(tilen_tmp) ); - if (abiinfo_both->host_ppc_calls_use_fndescrs) { - HWord* fndescr = (HWord*)checksum_fn; - checksum_fn_entry = fndescr[0]; - } else { - checksum_fn_entry = (HWord)checksum_fn; - } + /* Generate the entry point descriptors */ + if (abiinfo_both->host_ppc_calls_use_fndescrs) { + HWord* descr = (HWord*)fn_generic; + fn_generic_entry = descr[0]; + if (fn_spec) { + descr = (HWord*)fn_spec; + fn_spec_entry = descr[0]; + } else { + fn_spec_entry = (HWord)NULL; + } + } else { + fn_generic_entry = (HWord)fn_generic; + if (fn_spec) { + fn_spec_entry = (HWord)fn_spec; + } else { + fn_spec_entry = (HWord)NULL; + } + } + + IRExpr* callexpr = NULL; + if (fn_spec) { + callexpr = mkIRExprCCall( + Ity_I32, 1/*regparms*/, + nm_spec, (void*)fn_spec_entry, + mkIRExprVec_1( + mkIRExpr_HWord( (HWord)first_w32 ) + ) + ); + } else { + callexpr = mkIRExprCCall( + Ity_I32, 2/*regparms*/, + nm_generic, (void*)fn_generic_entry, + mkIRExprVec_2( + mkIRExpr_HWord( (HWord)first_w32 ), + mkIRExpr_HWord( (HWord)w32s_to_check ) + ) + ); + } - irsb->stmts[selfcheck_idx+4] - = IRStmt_Exit( - IRExpr_Binop( - Iop_CmpNE32, - mkIRExprCCall( - Ity_I32, - 2/*regparms*/, - checksum_fn == genericg_compute_checksum_4al_4plus - ? "genericg_compute_checksum_4al_4plus" - : "genericg_compute_checksum_generic", - (void*)checksum_fn_entry, - mkIRExprVec_2( - mkIRExpr_HWord( (HWord)guest_code ), - mkIRExpr_HWord( (HWord)len2check ) - ) + irsb->stmts[selfcheck_idx+4] + = IRStmt_Exit( + IRExpr_Binop( + Iop_CmpNE32, + callexpr, + IRExpr_Const(IRConst_U32(expected32)) ), - IRExpr_Const(IRConst_U32(expected32)) - ), - Ijk_TInval, - guest_IP_bbstart_IRConst - ); + Ijk_TInval, + guest_IP_bbstart_IRConst + ); + } } return irsb; @@ -441,83 +571,249 @@ static inline UInt ROL32 ( UInt w, Int n ) { } __attribute((regparm(2))) -static UInt genericg_compute_checksum_generic ( HWord addr, HWord len ) +static UInt genericg_compute_checksum_4al ( HWord first_w32, HWord n_w32s ) { - UInt sum1 = 0, sum2 = 0; - /* pull up to 4-alignment */ - while ((addr & 3) != 0 && len >= 1) { - UChar* p = (UChar*)addr; - sum1 = (sum1 << 8) | (UInt)p[0]; - addr++; - len--; - } - /* vectorised + unrolled */ - while (len >= 16) { - UInt* p = (UInt*)addr; + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + /* unrolled */ + while (n_w32s >= 4) { UInt w; w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - addr += 16; - len -= 16; + p += 4; + n_w32s -= 4; sum1 ^= sum2; } - /* vectorised fixup */ - while (len >= 4) { - UInt* p = (UInt*)addr; - UInt w = p[0]; - sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - addr += 4; - len -= 4; + while (n_w32s >= 1) { + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + p += 1; + n_w32s -= 1; sum1 ^= sum2; } - /* scalar fixup */ - while (len >= 1) { - UChar* p = (UChar*)addr; - UInt w = (UInt)p[0]; - sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - addr++; - len--; - } return sum1 + sum2; } -__attribute((regparm(2))) -static UInt genericg_compute_checksum_4al_4plus ( HWord addr, HWord len ) +/* Specialised versions of the above function */ + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_1 ( HWord first_w32 ) { - UInt sum1 = 0, sum2 = 0; - /* vassert(0 == (addr & 3)); */ - /* vassert(len >= 4); */ - /* vectorised + unrolled */ - while (len >= 16) { - UInt* p = (UInt*)addr; - UInt w; - w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - addr += 16; - len -= 16; - sum1 ^= sum2; - } - /* vectorised fixup */ - while (len >= 4) { - UInt* p = (UInt*)addr; - UInt w = p[0]; - sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - addr += 4; - len -= 4; - sum1 ^= sum2; - } - /* scalar fixup */ - while (len >= 1) { - UChar* p = (UChar*)addr; - UInt w = (UInt)p[0]; - sum1 = ROL32(sum1 ^ w, 31); sum2 += w; - addr++; - len--; - } + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_2 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_3 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_4 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_5 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[4]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_6 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[4]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[5]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_7 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[4]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[5]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[6]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_8 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[4]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[5]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[6]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[7]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_9 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[4]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[5]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[6]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[7]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[8]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_10 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[4]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[5]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[6]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[7]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[8]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[9]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_11 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[4]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[5]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[6]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[7]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[8]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[9]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[10]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + return sum1 + sum2; +} + +__attribute__((regparm(1))) +static UInt genericg_compute_checksum_4al_12 ( HWord first_w32 ) +{ + UInt sum1 = 0, sum2 = 0; + UInt* p = (UInt*)first_w32; + UInt w; + w = p[0]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[1]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[2]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[3]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[4]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[5]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[6]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[7]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; + w = p[8]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[9]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[10]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + w = p[11]; sum1 = ROL32(sum1 ^ w, 31); sum2 += w; + sum1 ^= sum2; return sum1 + sum2; } diff --git a/VEX/priv/guest_generic_bb_to_IR.h b/VEX/priv/guest_generic_bb_to_IR.h index 148346a..9ea10cb 100644 --- a/VEX/priv/guest_generic_bb_to_IR.h +++ b/VEX/priv/guest_generic_bb_to_IR.h @@ -1,42 +1,31 @@ /*--------------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_generic_bb_to_IR.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_generic_bb_to_IR.h ---*/ /*--------------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -79,9 +68,13 @@ typedef /* What happens next? Dis_StopHere: this insn terminates the BB; we must stop. Dis_Continue: we can optionally continue into the next insn - Dis_Resteer: followed a branch; continue at the spec'd addr + Dis_ResteerU: followed an unconditional branch; continue at + 'continueAt' + Dis_ResteerC: (speculatively, of course) followed a + conditional branch; continue at 'continueAt' */ - enum { Dis_StopHere, Dis_Continue, Dis_Resteer } whatNext; + enum { Dis_StopHere, Dis_Continue, + Dis_ResteerU, Dis_ResteerC } whatNext; /* For Dis_Resteer, this is the guest address we should continue at. Otherwise ignored (should be zero). */ @@ -123,9 +116,16 @@ typedef or not? */ /*IN*/ Bool put_IP, - /* Return True iff resteering to the given addr is allowed */ + /* Return True iff resteering to the given addr is allowed (for + branches/calls to destinations that are known at JIT-time) */ /*IN*/ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), + /* Should we speculatively resteer across conditional branches? + (Experimental and not enabled by default). The strategy is + to assume that backward branches are taken and forward + branches are not taken. */ + /*IN*/ Bool resteerCisOk, + /* Vex-opaque data passed to all caller (valgrind) supplied callbacks. */ /*IN*/ void* callback_opaque, diff --git a/VEX/priv/guest_generic_x87.c b/VEX/priv/guest_generic_x87.c index c4223f4..4204893 100644 --- a/VEX/priv/guest_generic_x87.c +++ b/VEX/priv/guest_generic_x87.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_generic_x87.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_generic_x87.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -464,13 +453,13 @@ ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp ) const ULong bit52 = 1ULL << 52; const ULong sigMask = bit52 - 1; - /* Mimic PIII behaviour for special cases. */ + /* Mimic Core i5 behaviour for special cases. */ if (arg == posInf) return getExp ? posInf : posInf; if (arg == negInf) return getExp ? posInf : negInf; if ((arg & nanMask) == nanMask) - return qNan; + return qNan | (arg & (1ULL << 63)); if (arg == posZero) return getExp ? negInf : posZero; if (arg == negZero) @@ -546,6 +535,354 @@ ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp ) } + +/*---------------------------------------------------------*/ +/*--- SSE4.2 PCMP{E,I}STR{I,M} helpers ---*/ +/*---------------------------------------------------------*/ + +/* We need the definitions for OSZACP eflags/rflags offsets. + #including guest_{amd64,x86}_defs.h causes chaos, so just copy the + required values directly. They are not going to change in the + foreseeable future :-) +*/ + +#define SHIFT_O 11 +#define SHIFT_S 7 +#define SHIFT_Z 6 +#define SHIFT_A 4 +#define SHIFT_C 0 +#define SHIFT_P 2 + +#define MASK_O (1 << SHIFT_O) +#define MASK_S (1 << SHIFT_S) +#define MASK_Z (1 << SHIFT_Z) +#define MASK_A (1 << SHIFT_A) +#define MASK_C (1 << SHIFT_C) +#define MASK_P (1 << SHIFT_P) + + +/* Count leading zeroes, w/ 0-produces-32 semantics, a la Hacker's + Delight. */ +static UInt clz32 ( UInt x ) +{ + Int y, m, n; + y = -(x >> 16); + m = (y >> 16) & 16; + n = 16 - m; + x = x >> m; + y = x - 0x100; + m = (y >> 16) & 8; + n = n + m; + x = x << m; + y = x - 0x1000; + m = (y >> 16) & 4; + n = n + m; + x = x << m; + y = x - 0x4000; + m = (y >> 16) & 2; + n = n + m; + x = x << m; + y = x >> 14; + m = y & ~(y >> 1); + return n + 2 - m; +} + +static UInt ctz32 ( UInt x ) +{ + return 32 - clz32((~x) & (x-1)); +} + +/* Convert a 4-bit value to a 32-bit value by cloning each bit 8 + times. There's surely a better way to do this, but I don't know + what it is. */ +static UInt bits4_to_bytes4 ( UInt bits4 ) +{ + UInt r = 0; + r |= (bits4 & 1) ? 0x000000FF : 0; + r |= (bits4 & 2) ? 0x0000FF00 : 0; + r |= (bits4 & 4) ? 0x00FF0000 : 0; + r |= (bits4 & 8) ? 0xFF000000 : 0; + return r; +} + + +/* Given partial results from a pcmpXstrX operation (intRes1, + basically), generate an I- or M-format output value, also the new + OSZACP flags. */ +static +void compute_PCMPxSTRx_gen_output (/*OUT*/V128* resV, + /*OUT*/UInt* resOSZACP, + UInt intRes1, + UInt zmaskL, UInt zmaskR, + UInt validL, + UInt pol, UInt idx, + Bool isxSTRM ) +{ + vassert((pol >> 2) == 0); + vassert((idx >> 1) == 0); + + UInt intRes2 = 0; + switch (pol) { + case 0: intRes2 = intRes1; break; // pol + + case 1: intRes2 = ~intRes1; break; // pol - + case 2: intRes2 = intRes1; break; // pol m+ + case 3: intRes2 = intRes1 ^ validL; break; // pol m- + } + intRes2 &= 0xFFFF; + + if (isxSTRM) { + + // generate M-format output (a bit or byte mask in XMM0) + if (idx) { + resV->w32[0] = bits4_to_bytes4( (intRes2 >> 0) & 0xF ); + resV->w32[1] = bits4_to_bytes4( (intRes2 >> 4) & 0xF ); + resV->w32[2] = bits4_to_bytes4( (intRes2 >> 8) & 0xF ); + resV->w32[3] = bits4_to_bytes4( (intRes2 >> 12) & 0xF ); + } else { + resV->w32[0] = intRes2 & 0xFFFF; + resV->w32[1] = 0; + resV->w32[2] = 0; + resV->w32[3] = 0; + } + + } else { + + // generate I-format output (an index in ECX) + // generate ecx value + UInt newECX = 0; + if (idx) { + // index of ms-1-bit + newECX = intRes2 == 0 ? 16 : (31 - clz32(intRes2)); + } else { + // index of ls-1-bit + newECX = intRes2 == 0 ? 16 : ctz32(intRes2); + } + + resV->w32[0] = newECX; + resV->w32[1] = 0; + resV->w32[2] = 0; + resV->w32[3] = 0; + + } + + // generate new flags, common to all ISTRI and ISTRM cases + *resOSZACP // A, P are zero + = ((intRes2 == 0) ? 0 : MASK_C) // C == 0 iff intRes2 == 0 + | ((zmaskL == 0) ? 0 : MASK_Z) // Z == 1 iff any in argL is 0 + | ((zmaskR == 0) ? 0 : MASK_S) // S == 1 iff any in argR is 0 + | ((intRes2 & 1) << SHIFT_O); // O == IntRes2[0] +} + + +/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M} + variants. + + For xSTRI variants, the new ECX value is placed in the 32 bits + pointed to by *resV, and the top 96 bits are zeroed. For xSTRM + variants, the result is a 128 bit value and is placed at *resV in + the obvious way. + + For all variants, the new OSZACP value is placed at *resOSZACP. + + argLV and argRV are the vector args. The caller must prepare a + 16-bit mask for each, zmaskL and zmaskR. For ISTRx variants this + must be 1 for each zero byte of of the respective arg. For ESTRx + variants this is derived from the explicit length indication, and + must be 0 in all places except at the bit index corresponding to + the valid length (0 .. 16). If the valid length is 16 then the + mask must be all zeroes. In all cases, bits 31:16 must be zero. + + imm8 is the original immediate from the instruction. isSTRM + indicates whether this is a xSTRM or xSTRI variant, which controls + how much of *res is written. + + If the given imm8 case can be handled, the return value is True. + If not, False is returned, and neither *res not *resOSZACP are + altered. +*/ + +Bool compute_PCMPxSTRx ( /*OUT*/V128* resV, + /*OUT*/UInt* resOSZACP, + V128* argLV, V128* argRV, + UInt zmaskL, UInt zmaskR, + UInt imm8, Bool isxSTRM ) +{ + vassert(imm8 < 0x80); + vassert((zmaskL >> 16) == 0); + vassert((zmaskR >> 16) == 0); + + /* Explicitly reject any imm8 values that haven't been validated, + even if they would probably work. Life is too short to have + unvalidated cases in the code base. */ + switch (imm8) { + case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12: + case 0x1A: case 0x3A: case 0x44: case 0x4A: + break; + default: + return False; + } + + UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format + UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation fn + UInt pol = (imm8 >> 4) & 3; // imm8[5:4] polarity + UInt idx = (imm8 >> 6) & 1; // imm8[6] 1==msb/bytemask + + /*----------------------------------------*/ + /*-- strcmp on byte data --*/ + /*----------------------------------------*/ + + if (agg == 2/*equal each, aka strcmp*/ + && (fmt == 0/*ub*/ || fmt == 2/*sb*/)) { + Int i; + UChar* argL = (UChar*)argLV; + UChar* argR = (UChar*)argRV; + UInt boolResII = 0; + for (i = 15; i >= 0; i--) { + UChar cL = argL[i]; + UChar cR = argR[i]; + boolResII = (boolResII << 1) | (cL == cR ? 1 : 0); + } + UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL)) + UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR)) + + // do invalidation, common to all equal-each cases + UInt intRes1 + = (boolResII & validL & validR) // if both valid, use cmpres + | (~ (validL | validR)); // if both invalid, force 1 + // else force 0 + intRes1 &= 0xFFFF; + + // generate I-format output + compute_PCMPxSTRx_gen_output( + resV, resOSZACP, + intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM + ); + + return True; + } + + /*----------------------------------------*/ + /*-- set membership on byte data --*/ + /*----------------------------------------*/ + + if (agg == 0/*equal any, aka find chars in a set*/ + && (fmt == 0/*ub*/ || fmt == 2/*sb*/)) { + /* argL: the string, argR: charset */ + UInt si, ci; + UChar* argL = (UChar*)argLV; + UChar* argR = (UChar*)argRV; + UInt boolRes = 0; + UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL)) + UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR)) + + for (si = 0; si < 16; si++) { + if ((validL & (1 << si)) == 0) + // run off the end of the string. + break; + UInt m = 0; + for (ci = 0; ci < 16; ci++) { + if ((validR & (1 << ci)) == 0) break; + if (argR[ci] == argL[si]) { m = 1; break; } + } + boolRes |= (m << si); + } + + // boolRes is "pre-invalidated" + UInt intRes1 = boolRes & 0xFFFF; + + // generate I-format output + compute_PCMPxSTRx_gen_output( + resV, resOSZACP, + intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM + ); + + return True; + } + + /*----------------------------------------*/ + /*-- substring search on byte data --*/ + /*----------------------------------------*/ + + if (agg == 3/*equal ordered, aka substring search*/ + && (fmt == 0/*ub*/ || fmt == 2/*sb*/)) { + + /* argL: haystack, argR: needle */ + UInt ni, hi; + UChar* argL = (UChar*)argLV; + UChar* argR = (UChar*)argRV; + UInt boolRes = 0; + UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL)) + UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR)) + for (hi = 0; hi < 16; hi++) { + if ((validL & (1 << hi)) == 0) + // run off the end of the haystack + break; + UInt m = 1; + for (ni = 0; ni < 16; ni++) { + if ((validR & (1 << ni)) == 0) break; + UInt i = ni + hi; + if (i >= 16) break; + if (argL[i] != argR[ni]) { m = 0; break; } + } + boolRes |= (m << hi); + } + + // boolRes is "pre-invalidated" + UInt intRes1 = boolRes & 0xFFFF; + + // generate I-format output + compute_PCMPxSTRx_gen_output( + resV, resOSZACP, + intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM + ); + + return True; + } + + /*----------------------------------------*/ + /*-- ranges, unsigned byte data --*/ + /*----------------------------------------*/ + + if (agg == 1/*ranges*/ + && fmt == 0/*ub*/) { + + /* argL: string, argR: range-pairs */ + UInt ri, si; + UChar* argL = (UChar*)argLV; + UChar* argR = (UChar*)argRV; + UInt boolRes = 0; + UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL)) + UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR)) + for (si = 0; si < 16; si++) { + if ((validL & (1 << si)) == 0) + // run off the end of the string + break; + UInt m = 0; + for (ri = 0; ri < 16; ri += 2) { + if ((validR & (3 << ri)) != (3 << ri)) break; + if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) { + m = 1; break; + } + } + boolRes |= (m << si); + } + + // boolRes is "pre-invalidated" + UInt intRes1 = boolRes & 0xFFFF; + + // generate I-format output + compute_PCMPxSTRx_gen_output( + resV, resOSZACP, + intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM + ); + + return True; + } + + return False; +} + + /*---------------------------------------------------------------*/ /*--- end guest_generic_x87.c ---*/ /*---------------------------------------------------------------*/ diff --git a/VEX/priv/guest_generic_x87.h b/VEX/priv/guest_generic_x87.h index b835c10..9cbe23b 100644 --- a/VEX/priv/guest_generic_x87.h +++ b/VEX/priv/guest_generic_x87.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_generic_x87.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_generic_x87.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -105,10 +94,18 @@ typedef #define FP_REG(ii) (10*(7-(ii))) -/* Do the computations for x86/amd64 FXTRACT */ +/* Do the computations for x86/amd64 FXTRACT. Called directly from + generated code. CLEAN HELPER. */ extern ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp ); - +/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M} + variants. See bigger comment on implementation of this function + for details on call/return conventions. */ +extern Bool compute_PCMPxSTRx ( /*OUT*/V128* resV, + /*OUT*/UInt* resOSZACP, + V128* argLV, V128* argRV, + UInt zmaskL, UInt zmaskR, + UInt imm8, Bool isxSTRM ); #endif /* ndef __VEX_GUEST_GENERIC_X87_H */ diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h index 73b7f6a..dd3c62e 100644 --- a/VEX/priv/guest_ppc_defs.h +++ b/VEX/priv/guest_ppc_defs.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_ppc_defs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_ppc_defs.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -61,6 +50,7 @@ extern DisResult disInstr_PPC ( IRSB* irbb, Bool put_IP, Bool (*resteerOkFn) ( void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, UChar* guest_code, Long delta, @@ -72,12 +62,16 @@ DisResult disInstr_PPC ( IRSB* irbb, /* Used by the optimiser to specialise calls to helpers. */ extern -IRExpr* guest_ppc32_spechelper ( HChar* function_name, - IRExpr** args ); +IRExpr* guest_ppc32_spechelper ( HChar* function_name, + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ); extern -IRExpr* guest_ppc64_spechelper ( HChar* function_name, - IRExpr** args ); +IRExpr* guest_ppc64_spechelper ( HChar* function_name, + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ); /* Describes to the optimser which part of the guest state require precise memory exceptions. This is logically part of the guest diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index b9d1052..e056a65 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_ppc_helpers.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_ppc_helpers.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -193,13 +182,17 @@ void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst, /* Helper-function specialiser. */ IRExpr* guest_ppc32_spechelper ( HChar* function_name, - IRExpr** args ) + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ) { return NULL; } IRExpr* guest_ppc64_spechelper ( HChar* function_name, - IRExpr** args ) + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ) { return NULL; } diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 92cc7d0..f8d220d 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -1,42 +1,31 @@ /*--------------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_ppc_toIR.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_ppc_toIR.c ---*/ /*--------------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -331,6 +320,7 @@ typedef enum { } PPC_GST; #define MASK_FPSCR_RN 0x3 +#define MASK_FPSCR_FPRF 0x1F000 #define MASK_VSCR_VALID 0x00010001 @@ -467,7 +457,7 @@ static void storeBE ( IRExpr* addr, IRExpr* data ) { IRType tyA = typeOfIRExpr(irsb->tyenv, addr); vassert(tyA == Ity_I32 || tyA == Ity_I64); - stmt( IRStmt_Store(Iend_BE, IRTemp_INVALID, addr, data) ); + stmt( IRStmt_Store(Iend_BE, addr, data) ); } static IRExpr* unop ( IROp op, IRExpr* a ) @@ -517,20 +507,9 @@ static IRExpr* mkU64 ( ULong i ) } /* This generates a normal (non load-linked) load. */ -static IRExpr* loadBE ( IRType ty, IRExpr* data ) +static IRExpr* loadBE ( IRType ty, IRExpr* addr ) { - return IRExpr_Load(False, Iend_BE, ty, data); -} - -/* And this, a linked load. */ -static IRExpr* loadlinkedBE ( IRType ty, IRExpr* data ) -{ - if (mode64) { - vassert(ty == Ity_I32 || ty == Ity_I64); - } else { - vassert(ty == Ity_I32); - } - return IRExpr_Load(True, Iend_BE, ty, data); + return IRExpr_Load(Iend_BE, ty, addr); } static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 ) @@ -2165,7 +2144,7 @@ static IRExpr* /* ::Ity_I32 */ getGST_masked ( PPC_GST reg, UInt mask ) /* We're only keeping track of the rounding mode, so if the mask isn't asking for this, just return 0x0 */ - if (mask & 0x3) { + if (mask & (MASK_FPSCR_RN|MASK_FPSCR_FPRF)) { assign( val, IRExpr_Get( OFFB_FPROUND, Ity_I32 ) ); } else { assign( val, mkU32(0x0) ); @@ -2289,7 +2268,7 @@ static void putGST_masked ( PPC_GST reg, IRExpr* src, UInt mask ) switch (reg) { case PPC_GST_FPSCR: { /* Allow writes to Rounding Mode */ - if (mask & 0x3) { + if (mask & (MASK_FPSCR_RN|MASK_FPSCR_FPRF)) { /* construct new fpround from new and old values as per mask: new fpround = (src & (3 & mask)) | (fpround & (3 & ~mask)) */ stmt( @@ -2297,11 +2276,11 @@ static void putGST_masked ( PPC_GST reg, IRExpr* src, UInt mask ) OFFB_FPROUND, binop( Iop_Or32, - binop(Iop_And32, src, mkU32(3 & mask)), + binop(Iop_And32, src, mkU32((MASK_FPSCR_RN|MASK_FPSCR_FPRF) & mask)), binop( Iop_And32, IRExpr_Get(OFFB_FPROUND,Ity_I32), - mkU32(3 & ~mask) + mkU32((MASK_FPSCR_RN|MASK_FPSCR_FPRF) & ~mask) ) ) ) @@ -3242,6 +3221,50 @@ static Bool dis_int_logic ( UInt theInstr ) // TODO: alternatively: assign(rA, verbose_Clz64(rS)); break; + case 0x1FC: // cmpb (Power6: compare bytes) + DIP("cmpb r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); + + if (mode64) + assign( rA, unop( Iop_V128to64, + binop( Iop_CmpEQ8x16, + binop( Iop_64HLtoV128, mkU64(0), mkexpr(rS) ), + binop( Iop_64HLtoV128, mkU64(0), mkexpr(rB) ) + )) ); + else + assign( rA, unop( Iop_V128to32, + binop( Iop_CmpEQ8x16, + unop( Iop_32UtoV128, mkexpr(rS) ), + unop( Iop_32UtoV128, mkexpr(rB) ) + )) ); + break; + + case 0x2DF: { // mftgpr (move floating-point to general purpose register) + IRTemp frB = newTemp(Ity_F64); + DIP("mftgpr r%u,fr%u\n", rS_addr, rB_addr); + + assign( frB, getFReg(rB_addr)); // always F64 + if (mode64) + assign( rA, unop( Iop_ReinterpF64asI64, mkexpr(frB)) ); + else + assign( rA, unop( Iop_64to32, unop( Iop_ReinterpF64asI64, mkexpr(frB))) ); + + putIReg( rS_addr, mkexpr(rA)); + return True; + } + + case 0x25F: { // mffgpr (move floating-point from general purpose register) + IRTemp frA = newTemp(Ity_F64); + DIP("mffgpr fr%u,r%u\n", rS_addr, rB_addr); + + if (mode64) + assign( frA, unop( Iop_ReinterpI64asF64, mkexpr(rB)) ); + else + assign( frA, unop( Iop_ReinterpI64asF64, unop( Iop_32Uto64, mkexpr(rB))) ); + + putFReg( rS_addr, mkexpr(frA)); + return True; + } + default: vex_printf("dis_int_logic(ppc)(opc2)\n"); return False; @@ -3261,6 +3284,133 @@ static Bool dis_int_logic ( UInt theInstr ) return True; } +/* + Integer Parity Instructions +*/ +static Bool dis_int_parity ( UInt theInstr ) +{ + /* X-Form */ + UChar opc1 = ifieldOPC(theInstr); + UChar rS_addr = ifieldRegDS(theInstr); + UChar rA_addr = ifieldRegA(theInstr); + UChar rB_addr = ifieldRegB(theInstr); + UInt opc2 = ifieldOPClo10(theInstr); + UChar b0 = ifieldBIT0(theInstr); + IRType ty = mode64 ? Ity_I64 : Ity_I32; + + IRTemp rS = newTemp(ty); + IRTemp rA = newTemp(ty); + IRTemp iTot1 = newTemp(Ity_I32); + IRTemp iTot2 = newTemp(Ity_I32); + IRTemp iTot3 = newTemp(Ity_I32); + IRTemp iTot4 = newTemp(Ity_I32); + IRTemp iTot5 = newTemp(Ity_I32); + IRTemp iTot6 = newTemp(Ity_I32); + IRTemp iTot7 = newTemp(Ity_I32); + IRTemp iTot8 = newTemp(Ity_I32); + IRTemp rS1 = newTemp(ty); + IRTemp rS2 = newTemp(ty); + IRTemp rS3 = newTemp(ty); + IRTemp rS4 = newTemp(ty); + IRTemp rS5 = newTemp(ty); + IRTemp rS6 = newTemp(ty); + IRTemp rS7 = newTemp(ty); + IRTemp iHi = newTemp(Ity_I32); + IRTemp iLo = newTemp(Ity_I32); + IROp to_bit = (mode64 ? Iop_64to1 : Iop_32to1); + IROp shr_op = (mode64 ? Iop_Shr64 : Iop_Shr32); + + if (opc1 != 0x1f || rB_addr || b0) { + vex_printf("dis_int_parity(ppc)(0x1F,opc1:rB|b0)\n"); + return False; + } + + assign( rS, getIReg(rS_addr) ); + + switch (opc2) { + case 0xba: // prtyd (Parity Doubleword, ISA 2.05 p320) + DIP("prtyd r%u,r%u\n", rA_addr, rS_addr); + assign( iTot1, unop(Iop_1Uto32, unop(to_bit, mkexpr(rS))) ); + assign( rS1, binop(shr_op, mkexpr(rS), mkU8(8)) ); + assign( iTot2, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS1))), + mkexpr(iTot1)) ); + assign( rS2, binop(shr_op, mkexpr(rS1), mkU8(8)) ); + assign( iTot3, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS2))), + mkexpr(iTot2)) ); + assign( rS3, binop(shr_op, mkexpr(rS2), mkU8(8)) ); + assign( iTot4, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS3))), + mkexpr(iTot3)) ); + if (mode64) { + assign( rS4, binop(shr_op, mkexpr(rS3), mkU8(8)) ); + assign( iTot5, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS4))), + mkexpr(iTot4)) ); + assign( rS5, binop(shr_op, mkexpr(rS4), mkU8(8)) ); + assign( iTot6, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS5))), + mkexpr(iTot5)) ); + assign( rS6, binop(shr_op, mkexpr(rS5), mkU8(8)) ); + assign( iTot7, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS6))), + mkexpr(iTot6)) ); + assign( rS7, binop(shr_op, mkexpr(rS6), mkU8(8)) ); + assign( iTot8, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS7))), + mkexpr(iTot7)) ); + assign( rA, unop(Iop_32Uto64, + binop(Iop_And32, mkexpr(iTot8), mkU32(1))) ); + } else + assign( rA, mkexpr(iTot4) ); + + break; + case 0x9a: // prtyw (Parity Word, ISA 2.05 p320) + assign( iTot1, unop(Iop_1Uto32, unop(to_bit, mkexpr(rS))) ); + assign( rS1, binop(shr_op, mkexpr(rS), mkU8(8)) ); + assign( iTot2, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS1))), + mkexpr(iTot1)) ); + assign( rS2, binop(shr_op, mkexpr(rS1), mkU8(8)) ); + assign( iTot3, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS2))), + mkexpr(iTot2)) ); + assign( rS3, binop(shr_op, mkexpr(rS2), mkU8(8)) ); + assign( iTot4, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS3))), + mkexpr(iTot3)) ); + assign( iLo, unop(Iop_1Uto32, unop(Iop_32to1, mkexpr(iTot4) )) ); + + if (mode64) { + assign( rS4, binop(shr_op, mkexpr(rS3), mkU8(8)) ); + assign( iTot5, unop(Iop_1Uto32, unop(to_bit, mkexpr(rS4))) ); + assign( rS5, binop(shr_op, mkexpr(rS4), mkU8(8)) ); + assign( iTot6, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS5))), + mkexpr(iTot5)) ); + assign( rS6, binop(shr_op, mkexpr(rS5), mkU8(8)) ); + assign( iTot7, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS6))), + mkexpr(iTot6)) ); + assign( rS7, binop(shr_op, mkexpr(rS6), mkU8(8))); + assign( iTot8, binop(Iop_Add32, + unop(Iop_1Uto32, unop(to_bit, mkexpr(rS7))), + mkexpr(iTot7)) ); + assign( iHi, binop(Iop_And32, mkU32(1), mkexpr(iTot8)) ), + assign( rA, binop(Iop_32HLto64, mkexpr(iHi), mkexpr(iLo)) ); + } else + assign( rA, binop(Iop_Or32, mkU32(0), mkexpr(iLo)) ); + break; + default: + vex_printf("dis_int_parity(ppc)(opc2)\n"); + return False; + } + + putIReg( rA_addr, mkexpr(rA) ); + + return True; +} /* @@ -4335,7 +4485,7 @@ static Bool dis_branch ( UInt theInstr, } if (resteerOkFn( callback_opaque, tgt )) { - dres->whatNext = Dis_Resteer; + dres->whatNext = Dis_ResteerU; dres->continueAt = tgt; } else { irsb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring; @@ -4861,7 +5011,8 @@ static Bool dis_memsync ( UInt theInstr ) stmt( IRStmt_MBE(Imbe_Fence) ); break; - case 0x014: // lwarx (Load Word and Reserve Indexed, PPC32 p458) + case 0x014: { // lwarx (Load Word and Reserve Indexed, PPC32 p458) + IRTemp res; /* According to the PowerPC ISA version 2.05, b0 (called EH in the documentation) is merely a hint bit to the hardware, I think as to whether or not contention is @@ -4872,10 +5023,13 @@ static Bool dis_memsync ( UInt theInstr ) gen_SIGBUS_if_misaligned( EA, 4 ); // and actually do the load - putIReg( rD_addr, mkWidenFrom32(ty, loadlinkedBE(Ity_I32, mkexpr(EA)), - False) ); + res = newTemp(Ity_I32); + stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) ); + + putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(res), False) ); break; - + } + case 0x096: { // stwcx. (Store Word Conditional Indexed, PPC32 p532) // Note this has to handle stwcx. in both 32- and 64-bit modes, @@ -4896,7 +5050,7 @@ static Bool dis_memsync ( UInt theInstr ) // Do the store, and get success/failure bit into resSC resSC = newTemp(Ity_I1); - stmt( IRStmt_Store(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) ); + stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) ); // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success @@ -4948,7 +5102,8 @@ static Bool dis_memsync ( UInt theInstr ) break; /* 64bit Memsync */ - case 0x054: // ldarx (Load DWord and Reserve Indexed, PPC64 p473) + case 0x054: { // ldarx (Load DWord and Reserve Indexed, PPC64 p473) + IRTemp res; /* According to the PowerPC ISA version 2.05, b0 (called EH in the documentation) is merely a hint bit to the hardware, I think as to whether or not contention is @@ -4961,9 +5116,13 @@ static Bool dis_memsync ( UInt theInstr ) gen_SIGBUS_if_misaligned( EA, 8 ); // and actually do the load - putIReg( rD_addr, loadlinkedBE(Ity_I64, mkexpr(EA)) ); + res = newTemp(Ity_I64); + stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) ); + + putIReg( rD_addr, mkexpr(res) ); break; - + } + case 0x0D6: { // stdcx. (Store DWord Condition Indexd, PPC64 p581) // A marginally simplified version of the stwcx. case IRTemp rS = newTemp(Ity_I64); @@ -4984,7 +5143,7 @@ static Bool dis_memsync ( UInt theInstr ) // Do the store, and get success/failure bit into resSC resSC = newTemp(Ity_I1); - stmt( IRStmt_Store(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) ); + stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) ); // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success @@ -5617,6 +5776,7 @@ static Bool dis_cache_manage ( UInt theInstr, UInt opc2 = ifieldOPClo10(theInstr); UChar b0 = ifieldBIT0(theInstr); UInt lineszB = guest_archinfo->ppc_cache_line_szB; + Bool is_dcbzl = False; IRType ty = mode64 ? Ity_I64 : Ity_I32; @@ -5628,6 +5788,16 @@ static Bool dis_cache_manage ( UInt theInstr, /* b21to25 &= ~3; */ /* if the docs were true */ b21to25 = 0; /* blunt instrument */ } + if (opc1 == 0x1F && opc2 == 0x3F6) { // dcbz + if (b21to25 == 1) { + is_dcbzl = True; + b21to25 = 0; + if (!(guest_archinfo->ppc_dcbzl_szB)) { + vex_printf("dis_cache_manage(ppc)(dcbzl not supported by host)\n"); + return False; + } + } + } if (opc1 != 0x1F || b21to25 != 0 || b0 != 0) { if (0) vex_printf("dis_cache_manage %d %d %d\n", @@ -5667,12 +5837,21 @@ static Bool dis_cache_manage ( UInt theInstr, break; case 0x3F6: { // dcbz (Data Cache Block Clear to Zero, PPC32 p387) + // dcbzl (Data Cache Block Clear to Zero Long, bug#135264) /* Clear all bytes in cache block at (rA|0) + rB. */ IRTemp EA = newTemp(ty); IRTemp addr = newTemp(ty); IRExpr* irx_addr; UInt i; - DIP("dcbz r%u,r%u\n", rA_addr, rB_addr); + UInt clearszB; + if (is_dcbzl) { + clearszB = guest_archinfo->ppc_dcbzl_szB; + DIP("dcbzl r%u,r%u\n", rA_addr, rB_addr); + } + else { + clearszB = guest_archinfo->ppc_dcbz_szB; + DIP("dcbz r%u,r%u\n", rA_addr, rB_addr); + } assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); @@ -5680,9 +5859,9 @@ static Bool dis_cache_manage ( UInt theInstr, /* Round EA down to the start of the containing block. */ assign( addr, binop( Iop_And64, mkexpr(EA), - mkU64( ~((ULong)lineszB-1) )) ); + mkU64( ~((ULong)clearszB-1) )) ); - for (i = 0; i < lineszB / 8; i++) { + for (i = 0; i < clearszB / 8; i++) { irx_addr = binop( Iop_Add64, mkexpr(addr), mkU64(i*8) ); storeBE( irx_addr, mkU64(0) ); } @@ -5690,9 +5869,9 @@ static Bool dis_cache_manage ( UInt theInstr, /* Round EA down to the start of the containing block. */ assign( addr, binop( Iop_And32, mkexpr(EA), - mkU32( ~(lineszB-1) )) ); + mkU32( ~(clearszB-1) )) ); - for (i = 0; i < lineszB / 4; i++) { + for (i = 0; i < clearszB / 4; i++) { irx_addr = binop( Iop_Add32, mkexpr(addr), mkU32(i*4) ); storeBE( irx_addr, mkU32(0) ); } @@ -5787,6 +5966,8 @@ static Bool dis_fp_load ( UInt theInstr ) IRTemp EA = newTemp(ty); IRTemp rA = newTemp(ty); IRTemp rB = newTemp(ty); + IRTemp iHi = newTemp(Ity_I32); + IRTemp iLo = newTemp(Ity_I32); assign( rA, getIReg(rA_addr) ); assign( rB, getIReg(rB_addr) ); @@ -5867,6 +6048,17 @@ static Bool dis_fp_load ( UInt theInstr ) putIReg( rA_addr, mkexpr(EA) ); break; + case 0x357: // lfiwax (Load Float As Integer, Indxd, ISA 2.05 p120) + DIP("lfiwax fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); + assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); + assign( iLo, loadBE(Ity_I32, mkexpr(EA)) ); + assign( iHi, binop(Iop_Sub32, + mkU32(0), + binop(Iop_Shr32, mkexpr(iLo), mkU8(31))) ); + putFReg( frD_addr, unop(Iop_ReinterpI64asF64, + binop(Iop_32HLto64, mkexpr(iHi), mkexpr(iLo))) ); + break; + default: vex_printf("dis_fp_load(ppc)(opc2)\n"); return False; @@ -6507,8 +6699,8 @@ static Bool dis_fp_round ( UInt theInstr ) { /* X-Form */ UChar opc1 = ifieldOPC(theInstr); - UChar frD_addr = ifieldRegDS(theInstr); UChar b16to20 = ifieldRegA(theInstr); + UChar frD_addr = ifieldRegDS(theInstr); UChar frB_addr = ifieldRegB(theInstr); UInt opc2 = ifieldOPClo10(theInstr); UChar flag_rC = ifieldBIT0(theInstr); @@ -6546,7 +6738,7 @@ static Bool dis_fp_round ( UInt theInstr ) case 0x00E: // fctiw (Float Conv to Int, PPC32 p404) DIP("fctiw%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); assign( r_tmp32, - binop(Iop_F64toI32, rm, mkexpr(frB)) ); + binop(Iop_F64toI32S, rm, mkexpr(frB)) ); assign( frD, unop( Iop_ReinterpI64asF64, unop( Iop_32Uto64, mkexpr(r_tmp32)))); /* FPRF is undefined after fctiw. Leave unchanged. */ @@ -6556,7 +6748,7 @@ static Bool dis_fp_round ( UInt theInstr ) case 0x00F: // fctiwz (Float Conv to Int, Round to Zero, PPC32 p405) DIP("fctiwz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); assign( r_tmp32, - binop(Iop_F64toI32, mkU32(Irrm_ZERO), mkexpr(frB) )); + binop(Iop_F64toI32S, mkU32(Irrm_ZERO), mkexpr(frB) )); assign( frD, unop( Iop_ReinterpI64asF64, unop( Iop_32Uto64, mkexpr(r_tmp32)))); /* FPRF is undefined after fctiwz. Leave unchanged. */ @@ -6566,7 +6758,7 @@ static Bool dis_fp_round ( UInt theInstr ) case 0x32E: // fctid (Float Conv to Int DWord, PPC64 p437) DIP("fctid%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); assign( r_tmp64, - binop(Iop_F64toI64, rm, mkexpr(frB)) ); + binop(Iop_F64toI64S, rm, mkexpr(frB)) ); assign( frD, unop( Iop_ReinterpI64asF64, mkexpr(r_tmp64)) ); /* FPRF is undefined after fctid. Leave unchanged. */ set_FPRF = False; @@ -6575,7 +6767,7 @@ static Bool dis_fp_round ( UInt theInstr ) case 0x32F: // fctidz (Float Conv to Int DWord, Round to Zero, PPC64 p437) DIP("fctidz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); assign( r_tmp64, - binop(Iop_F64toI64, mkU32(Irrm_ZERO), mkexpr(frB)) ); + binop(Iop_F64toI64S, mkU32(Irrm_ZERO), mkexpr(frB)) ); assign( frD, unop( Iop_ReinterpI64asF64, mkexpr(r_tmp64)) ); /* FPRF is undefined after fctidz. Leave unchanged. */ set_FPRF = False; @@ -6585,7 +6777,53 @@ static Bool dis_fp_round ( UInt theInstr ) DIP("fcfid%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); assign( r_tmp64, unop( Iop_ReinterpF64asI64, mkexpr(frB)) ); assign( frD, - binop(Iop_I64toF64, rm, mkexpr(r_tmp64)) ); + binop(Iop_I64StoF64, rm, mkexpr(r_tmp64)) ); + break; + + case 0x188: case 0x1A8: case 0x1C8: case 0x1E8: // frin, friz, frip, frim + switch(opc2) { + case 0x188: // frin (Floating Round to Integer Nearest) + DIP("frin%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); + assign( r_tmp64, + binop(Iop_F64toI64S, mkU32(Irrm_NEAREST), mkexpr(frB)) ); + break; + case 0x1A8: // friz (Floating Round to Integer Toward Zero) + DIP("friz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); + assign( r_tmp64, + binop(Iop_F64toI64S, mkU32(Irrm_ZERO), mkexpr(frB)) ); + break; + case 0x1C8: // frip (Floating Round to Integer Plus) + DIP("frip%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); + assign( r_tmp64, + binop(Iop_F64toI64S, mkU32(Irrm_PosINF), mkexpr(frB)) ); + break; + case 0x1E8: // frim (Floating Round to Integer Minus) + DIP("frim%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); + assign( r_tmp64, + binop(Iop_F64toI64S, mkU32(Irrm_NegINF), mkexpr(frB)) ); + break; + } + + /* don't use the rounded integer if frB is outside -9e18..9e18 */ + /* F64 has only log10(2**52) significant digits anyway */ + /* need to preserve sign of zero */ + /* frD = (fabs(frB) > 9e18) ? frB : + (sign(frB)) ? -fabs((double)r_tmp64) : (double)r_tmp64 */ + assign(frD, IRExpr_Mux0X( unop(Iop_32to8, + binop(Iop_CmpF64, + IRExpr_Const(IRConst_F64(9e18)), + unop(Iop_AbsF64, mkexpr(frB)))), + IRExpr_Mux0X(unop(Iop_32to8, + binop(Iop_Shr32, + unop(Iop_64HIto32, + unop(Iop_ReinterpF64asI64, + mkexpr(frB))), mkU8(31))), + binop(Iop_I64StoF64, mkU32(0), mkexpr(r_tmp64) ), + unop(Iop_NegF64, + unop( Iop_AbsF64, + binop(Iop_I64StoF64, mkU32(0), + mkexpr(r_tmp64)) )) ), + mkexpr(frB))); break; default: @@ -6608,6 +6846,86 @@ static Bool dis_fp_round ( UInt theInstr ) return True; } +/* + Floating Point Pair Instructions +*/ +static Bool dis_fp_pair ( UInt theInstr ) +{ + /* X-Form/DS-Form */ + UChar opc1 = ifieldOPC(theInstr); + UChar frT_hi_addr = ifieldRegDS(theInstr); + UChar frT_lo_addr = frT_hi_addr + 1; + UChar rA_addr = ifieldRegA(theInstr); + UChar rB_addr = ifieldRegB(theInstr); + UInt uimm16 = ifieldUIMM16(theInstr); + Int simm16 = extend_s_16to32(uimm16); + UInt opc2 = ifieldOPClo10(theInstr); + IRType ty = mode64 ? Ity_I64 : Ity_I32; + IRTemp EA_hi = newTemp(ty); + IRTemp EA_lo = newTemp(ty); + IRTemp frT_hi = newTemp(Ity_F64); + IRTemp frT_lo = newTemp(Ity_F64); + UChar b0 = ifieldBIT0(theInstr); + Bool is_load = 0; + + if ((frT_hi_addr %2) != 0) { + vex_printf("dis_fp_pair(ppc) : odd frT register\n"); + return False; + } + + switch (opc1) { + case 0x1F: // register offset + switch(opc2) { + case 0x317: // lfdpx (FP Load Double Pair X-form, ISA 2.05 p125) + DIP("ldpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr); + is_load = 1; + break; + case 0x397: // stfdpx (FP STORE Double Pair X-form, ISA 2.05 p125) + DIP("stdpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr); + break; + default: + vex_printf("dis_fp_pair(ppc) : X-form wrong opc2\n"); + return False; + } + + if (b0 != 0) { + vex_printf("dis_fp_pair(ppc)(0x1F,b0)\n"); + return False; + } + assign( EA_hi, ea_rAor0_idxd( rA_addr, rB_addr ) ); + break; + case 0x39: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125) + DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr); + assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) ); + is_load = 1; + break; + case 0x3d: // stfdp (FP Store Double Pair DS-form, ISA 2.05 p125) + DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr); + assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) ); + break; + default: // immediate offset + vex_printf("dis_fp_pair(ppc)(instr)\n"); + return False; + } + + if (mode64) + assign( EA_lo, binop(Iop_Add64, mkexpr(EA_hi), mkU64(8)) ); + else + assign( EA_lo, binop(Iop_Add32, mkexpr(EA_hi), mkU32(8)) ); + + assign( frT_hi, getFReg(frT_hi_addr) ); + assign( frT_lo, getFReg(frT_lo_addr) ); + + if (is_load) { + putFReg( frT_hi_addr, loadBE(Ity_F64, mkexpr(EA_hi)) ); + putFReg( frT_lo_addr, loadBE(Ity_F64, mkexpr(EA_lo)) ); + } else { + storeBE( mkexpr(EA_hi), mkexpr(frT_hi) ); + storeBE( mkexpr(EA_lo), mkexpr(frT_lo) ); + } + + return True; +} /* @@ -6618,15 +6936,19 @@ static Bool dis_fp_move ( UInt theInstr ) /* X-Form */ UChar opc1 = ifieldOPC(theInstr); UChar frD_addr = ifieldRegDS(theInstr); - UChar b16to20 = ifieldRegA(theInstr); + UChar frA_addr = ifieldRegA(theInstr); UChar frB_addr = ifieldRegB(theInstr); UInt opc2 = ifieldOPClo10(theInstr); UChar flag_rC = ifieldBIT0(theInstr); IRTemp frD = newTemp(Ity_F64); IRTemp frB = newTemp(Ity_F64); + IRTemp itmpB = newTemp(Ity_F64); + IRTemp frA; + IRTemp signA; + IRTemp hiD; - if (opc1 != 0x3F || b16to20 != 0) { + if (opc1 != 0x3F || (frA_addr != 0 && opc2 != 0x008)) { vex_printf("dis_fp_move(ppc)(instr)\n"); return False; } @@ -6634,6 +6956,39 @@ static Bool dis_fp_move ( UInt theInstr ) assign( frB, getFReg(frB_addr)); switch (opc2) { + case 0x008: // fcpsgn (Floating Copy Sign, ISA_V2.05 p126) + DIP("fcpsgn%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frA_addr, + frB_addr); + signA = newTemp(Ity_I32); + hiD = newTemp(Ity_I32); + itmpB = newTemp(Ity_I64); + frA = newTemp(Ity_F64); + assign( frA, getFReg(frA_addr) ); + + /* get A's sign bit */ + assign(signA, binop(Iop_And32, + unop(Iop_64HIto32, unop(Iop_ReinterpF64asI64, + mkexpr(frA))), + mkU32(0x80000000)) ); + + assign( itmpB, unop(Iop_ReinterpF64asI64, mkexpr(frB)) ); + + /* mask off B's sign bit and or in A's sign bit */ + assign(hiD, binop(Iop_Or32, + binop(Iop_And32, + unop(Iop_64HIto32, + mkexpr(itmpB)), /* frB's high 32 bits */ + mkU32(0x7fffffff)), + mkexpr(signA)) ); + + /* combine hiD/loB into frD */ + assign( frD, unop(Iop_ReinterpI64asF64, + binop(Iop_32HLto64, + mkexpr(hiD), + unop(Iop_64to32, + mkexpr(itmpB)))) ); /* frB's low 32 bits */ + break; + case 0x028: // fneg (Floating Negate, PPC32 p416) DIP("fneg%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); assign( frD, unop( Iop_NegF64, mkexpr(frB) )); @@ -6774,27 +7129,34 @@ static Bool dis_fp_scr ( UInt theInstr ) case 0x2C7: { // mtfsf (Move to FPSCR Fields, PPC32 p480) UChar b25 = toUChar( IFIELD(theInstr, 25, 1) ); UChar FM = toUChar( IFIELD(theInstr, 17, 8) ); - UChar b16 = toUChar( IFIELD(theInstr, 16, 1) ); UChar frB_addr = ifieldRegB(theInstr); IRTemp frB = newTemp(Ity_F64); IRTemp rB_32 = newTemp(Ity_I32); Int i, mask; - if (b25 != 0 || b16 != 0) { - vex_printf("dis_fp_scr(ppc)(instr,mtfsf)\n"); - return False; - } - DIP("mtfsf%s %d,fr%u\n", flag_rC ? ".":"", FM, frB_addr); + if (b25 == 1) { + /* new 64 bit move variant for power 6. If L field (bit 25) is + * a one do a full 64 bit move. Note, the FPSCR is not really + * properly modeled. This instruciton only changes the value of + * the rounding mode. The HW exception bits do not get set in + * the simulator. 1/12/09 + */ + DIP("mtfsf%s %d,fr%u (L=1)\n", flag_rC ? ".":"", FM, frB_addr); + mask = 0xFF; + + } else { + DIP("mtfsf%s %d,fr%u\n", flag_rC ? ".":"", FM, frB_addr); + // Build 32bit mask from FM: + mask = 0; + for (i=0; i<8; i++) { + if ((FM & (1<<(7-i))) == 1) { + mask |= 0xF << (7-i); + } + } + } assign( frB, getFReg(frB_addr)); assign( rB_32, unop( Iop_64to32, unop( Iop_ReinterpF64asI64, mkexpr(frB) ))); - // Build 32bit mask from FM: - mask = 0; - for (i=0; i<8; i++) { - if ((FM & (1<<(7-i))) == 1) { - mask |= 0xF << (7-i); - } - } putGST_masked( PPC_GST_FPSCR, mkexpr(rB_32), mask ); break; } @@ -8877,69 +9239,6 @@ static Bool dis_av_fp_convert ( UInt theInstr ) -/*------------------------------------------------------------*/ -/*--- POWER6 Instruction Translation ---*/ -/*------------------------------------------------------------*/ - -static -Bool dis_P6 ( UInt theInstr, - Bool allow_F, Bool allow_V, Bool allow_FX, Bool allow_GX) -{ - UInt opc, rd, ra, rb, opc2, dot; - - /* This is a hack. We should do P6 capability checking properly. - But anyway, make a guess at whether we should even try to handle - this instruction. All P6 capable CPUs should be able to handle - F, V, FX and GX, so that seems like a good check. */ - if (! (allow_F && allow_V && allow_FX && allow_GX) ) - return False; - if (!mode64) - return False; /* only support P6 in 64-bit mode for now */ - - opc = ifieldOPC(theInstr); /* primary opcode */ - rd = ifieldRegDS(theInstr); /* dst reg */ - ra = ifieldRegA(theInstr); /* first source reg */ - rb = ifieldRegB(theInstr); /* second source reg */ - opc2 = ifieldOPClo10(theInstr); /* secondary opc, 10:1 */ - dot = ifieldBIT0(theInstr); /* Rc field, bit 0 */ - - if (opc == 63 && ra == 0/*presumably*/ && opc2 == 488) { - /* frim (Floating Round to Integer Minus, PPC ISA 2.05 p137) */ - if (dot) return False; - putFReg( rd, unop(Iop_RoundF64toF64_NegINF, getFReg( rb )) ); - DIP("frim%s fr%u,fr%u\n", dot ? "." : "", rd, rb); - return True; - } - - if (opc == 63 && ra == 0/*presumably*/ && opc2 == 456) { - /* frip (Floating Round to Integer Plus, PPC ISA 2.05 p137) */ - if (dot) return False; - putFReg( rd, unop(Iop_RoundF64toF64_PosINF, getFReg( rb )) ); - DIP("frip%s fr%u,fr%u\n", dot ? "." : "", rd, rb); - return True; - } - - if (opc == 63 && ra == 0/*presumably*/ && opc2 == 392) { - /* frin (Floating Round to Integer Nearest, PPC ISA 2.05 p137) */ - if (dot) return False; - putFReg( rd, unop(Iop_RoundF64toF64_NEAREST, getFReg( rb )) ); - DIP("frin%s fr%u,fr%u\n", dot ? "." : "", rd, rb); - return True; - } - - if (opc == 63 && ra == 0/*presumably*/ && opc2 == 424) { - /* frin (Floating Round to Integer Zero, PPC ISA 2.05 p137) */ - if (dot) return False; - putFReg( rd, unop(Iop_RoundF64toF64_ZERO, getFReg( rb )) ); - DIP("friz%s fr%u,fr%u\n", dot ? "." : "", rd, rb); - return True; - } - - if (0) - vex_printf("dis_P6: %u %u %u %u %u %u\n", opc, rd, ra, rb, opc2, dot); - return False; -} - /*------------------------------------------------------------*/ @@ -8953,6 +9252,7 @@ static DisResult disInstr_PPC_WRK ( Bool put_IP, Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, Long delta64, VexArchInfo* archinfo, @@ -9159,6 +9459,12 @@ DisResult disInstr_PPC_WRK ( if (dis_fp_store( theInstr )) goto decode_success; goto decode_failure; + /* Floating Point Load Double Pair Instructions */ + case 0x39: case 0x3D: + if (!allow_F) goto decode_noF; + if (dis_fp_pair( theInstr )) goto decode_success; + goto decode_failure; + /* 64bit Integer Loads */ case 0x3A: // ld, ldu, lwa if (!mode64) goto decode_failure; @@ -9264,11 +9570,14 @@ DisResult disInstr_PPC_WRK ( case 0x1C8: // frip case 0x188: // frin case 0x1A8: // friz - if (dis_P6(theInstr, allow_F, allow_V, allow_FX, allow_GX)) + /* A hack to check for P6 capability . . . */ + if ((allow_F && allow_V && allow_FX && allow_GX) && + (dis_fp_round(theInstr))) goto decode_success; goto decode_failure; /* Floating Point Move Instructions */ + case 0x008: // fcpsgn case 0x028: // fneg case 0x048: // fmr case 0x088: // fnabs @@ -9342,6 +9651,10 @@ DisResult disInstr_PPC_WRK ( if (dis_int_arith( theInstr )) goto decode_success; goto decode_failure; + case 0x1FC: // cmpb + if (dis_int_logic( theInstr )) goto decode_success; + goto decode_failure; + default: break; // Fall through... } @@ -9360,6 +9673,7 @@ DisResult disInstr_PPC_WRK ( case 0x11C: case 0x3BA: case 0x39A: // eqv, extsb, extsh case 0x1DC: case 0x07C: case 0x1BC: // nand, nor, or case 0x19C: case 0x13C: // orc, xor + case 0x2DF: case 0x25F: // mftgpr, mffgpr if (dis_int_logic( theInstr )) goto decode_success; goto decode_failure; @@ -9369,6 +9683,11 @@ DisResult disInstr_PPC_WRK ( if (dis_int_logic( theInstr )) goto decode_success; goto decode_failure; + /* 64bit Integer Parity Instructions */ + case 0xba: case 0x9a: // prtyd, prtyw + if (dis_int_parity( theInstr )) goto decode_success; + goto decode_failure; + /* Integer Shift Instructions */ case 0x018: case 0x318: case 0x338: // slw, sraw, srawi case 0x218: // srw @@ -9484,6 +9803,18 @@ DisResult disInstr_PPC_WRK ( if (dis_fp_store( theInstr )) goto decode_success; goto decode_failure; + /* Floating Point Double Pair Indexed Instructions */ + case 0x317: // lfdpx (Power6) + case 0x397: // stfdpx (Power6) + if (!allow_F) goto decode_noF; + if (dis_fp_pair(theInstr)) goto decode_success; + goto decode_failure; + + case 0x357: // lfiwax + if (!allow_F) goto decode_noF; + if (dis_fp_load( theInstr )) goto decode_success; + goto decode_failure; + /* AltiVec instructions */ /* AV Cache Control - Data streams */ @@ -9751,6 +10082,7 @@ DisResult disInstr_PPC_WRK ( DisResult disInstr_PPC ( IRSB* irsb_IN, Bool put_IP, Bool (*resteerOkFn) ( void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, UChar* guest_code_IN, Long delta, @@ -9792,7 +10124,8 @@ DisResult disInstr_PPC ( IRSB* irsb_IN, guest_CIA_curr_instr = mkSzAddr(ty, guest_IP); guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta); - dres = disInstr_PPC_WRK ( put_IP, resteerOkFn, callback_opaque, + dres = disInstr_PPC_WRK ( put_IP, + resteerOkFn, resteerCisOk, callback_opaque, delta, archinfo, abiinfo ); return dres; diff --git a/VEX/priv/guest_x86_defs.h b/VEX/priv/guest_x86_defs.h index ccee35b..09d647a 100644 --- a/VEX/priv/guest_x86_defs.h +++ b/VEX/priv/guest_x86_defs.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_x86_defs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_x86_defs.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -60,6 +49,7 @@ extern DisResult disInstr_X86 ( IRSB* irbb, Bool put_IP, Bool (*resteerOkFn) ( void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, UChar* guest_code, Long delta, @@ -71,8 +61,10 @@ DisResult disInstr_X86 ( IRSB* irbb, /* Used by the optimiser to specialise calls to helpers. */ extern -IRExpr* guest_x86_spechelper ( HChar* function_name, - IRExpr** args ); +IRExpr* guest_x86_spechelper ( HChar* function_name, + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ); /* Describes to the optimiser which part of the guest state require precise memory exceptions. This is logically part of the guest @@ -163,6 +155,9 @@ extern UInt x86g_dirtyhelper_IN ( UInt portno, UInt sz/*1,2 or 4*/ ); extern void x86g_dirtyhelper_OUT ( UInt portno, UInt data, UInt sz/*1,2 or 4*/ ); +extern void x86g_dirtyhelper_SxDT ( void* address, + UInt op /* 0 or 1 */ ); + extern VexEmWarn x86g_dirtyhelper_FXRSTOR ( VexGuestX86State*, HWord ); diff --git a/VEX/priv/guest_x86_helpers.c b/VEX/priv/guest_x86_helpers.c index bec1dc3..7aa7a33 100644 --- a/VEX/priv/guest_x86_helpers.c +++ b/VEX/priv/guest_x86_helpers.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_x86_helpers.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_x86_helpers.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -783,8 +772,10 @@ static inline Bool isU32 ( IRExpr* e, UInt n ) && e->Iex.Const.con->Ico.U32 == n ); } -IRExpr* guest_x86_spechelper ( HChar* function_name, - IRExpr** args ) +IRExpr* guest_x86_spechelper ( HChar* function_name, + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ) { # define unop(_op,_a1) IRExpr_Unop((_op),(_a1)) # define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2)) @@ -1272,6 +1263,22 @@ IRExpr* guest_x86_spechelper ( HChar* function_name, binop(Iop_Add32, cc_dep1, cc_dep2), cc_dep1)); } + // ATC, requires verification, no test case known + //if (isU32(cc_op, X86G_CC_OP_SMULL)) { + // /* C after signed widening multiply denotes the case where + // the top half of the result isn't simply the sign extension + // of the bottom half (iow the result doesn't fit completely + // in the bottom half). Hence: + // C = hi-half(dep1 x dep2) != lo-half(dep1 x dep2) >>s 31 + // where 'x' denotes signed widening multiply.*/ + // return + // unop(Iop_1Uto32, + // binop(Iop_CmpNE32, + // unop(Iop_64HIto32, + // binop(Iop_MullS32, cc_dep1, cc_dep2)), + // binop(Iop_Sar32, + // binop(Iop_Mul32, cc_dep1, cc_dep2), mkU8(31)) )); + //} # if 0 if (cc_op->tag == Iex_Const) { vex_printf("CFLAG "); ppIRExpr(cc_op); vex_printf("\n"); @@ -2348,6 +2355,30 @@ void x86g_dirtyhelper_OUT ( UInt portno, UInt data, UInt sz/*1,2 or 4*/ ) # endif } +/* CALLED FROM GENERATED CODE */ +/* DIRTY HELPER (non-referentially-transparent) */ +/* Horrible hack. On non-x86 platforms, do nothing. */ +/* op = 0: call the native SGDT instruction. + op = 1: call the native SIDT instruction. +*/ +void x86g_dirtyhelper_SxDT ( void *address, UInt op ) { +# if defined(__i386__) + switch (op) { + case 0: + __asm__ __volatile__("sgdt (%0)" : : "r" (address) : "memory"); + break; + case 1: + __asm__ __volatile__("sidt (%0)" : : "r" (address) : "memory"); + break; + default: + vpanic("x86g_dirtyhelper_SxDT"); + } +# else + /* do nothing */ + UChar* p = (UChar*)address; + p[0] = p[1] = p[2] = p[3] = p[4] = p[5] = 0; +# endif +} /*---------------------------------------------------------------*/ /*--- Helpers for MMX/SSE/SSE2. ---*/ diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c index 9f4fcce..d03b6f1 100644 --- a/VEX/priv/guest_x86_toIR.c +++ b/VEX/priv/guest_x86_toIR.c @@ -1,42 +1,31 @@ /*--------------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (guest_x86_toIR.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin guest_x86_toIR.c ---*/ /*--------------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -119,6 +108,9 @@ only taken if the CAS fails, that is, the location is contended, which is relatively unlikely. + XXXX: Nov 2009: handling of SWP on ARM suffers from the same + problem. + Note also, the test for CAS success vs failure is done using Iop_CasCmp{EQ,NE}{8,16,32,64} rather than the ordinary Iop_Cmp{EQ,NE} equivalents. This is so as to tell Memcheck that it @@ -648,7 +640,7 @@ static void assign ( IRTemp dst, IRExpr* e ) static void storeLE ( IRExpr* addr, IRExpr* data ) { - stmt( IRStmt_Store(Iend_LE, IRTemp_INVALID, addr, data) ); + stmt( IRStmt_Store(Iend_LE, addr, data) ); } static IRExpr* unop ( IROp op, IRExpr* a ) @@ -708,9 +700,9 @@ static IRExpr* mkV128 ( UShort mask ) return IRExpr_Const(IRConst_V128(mask)); } -static IRExpr* loadLE ( IRType ty, IRExpr* data ) +static IRExpr* loadLE ( IRType ty, IRExpr* addr ) { - return IRExpr_Load(False, Iend_LE, ty, data); + return IRExpr_Load(Iend_LE, ty, addr); } static IROp mkSizedOp ( IRType ty, IROp op8 ) @@ -2174,9 +2166,16 @@ UInt dis_movx_E_G ( UChar sorb, { UChar rm = getIByte(delta); if (epartIsReg(rm)) { - putIReg(szd, gregOfRM(rm), - unop(mkWidenOp(szs,szd,sign_extend), - getIReg(szs,eregOfRM(rm)))); + if (szd == szs) { + // mutant case. See #250799 + putIReg(szd, gregOfRM(rm), + getIReg(szs,eregOfRM(rm))); + } else { + // normal case + putIReg(szd, gregOfRM(rm), + unop(mkWidenOp(szs,szd,sign_extend), + getIReg(szs,eregOfRM(rm)))); + } DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z', nameISize(szs), nameISize(szd), nameIReg(szs,eregOfRM(rm)), @@ -2189,10 +2188,16 @@ UInt dis_movx_E_G ( UChar sorb, Int len; HChar dis_buf[50]; IRTemp addr = disAMode ( &len, sorb, delta, dis_buf ); - - putIReg(szd, gregOfRM(rm), - unop(mkWidenOp(szs,szd,sign_extend), - loadLE(szToITy(szs),mkexpr(addr)))); + if (szd == szs) { + // mutant case. See #250799 + putIReg(szd, gregOfRM(rm), + loadLE(szToITy(szs),mkexpr(addr))); + } else { + // normal case + putIReg(szd, gregOfRM(rm), + unop(mkWidenOp(szs,szd,sign_extend), + loadLE(szToITy(szs),mkexpr(addr)))); + } DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z', nameISize(szs), nameISize(szd), dis_buf, nameIReg(szd,gregOfRM(rm))); @@ -3370,6 +3375,40 @@ UInt dis_imul_I_E_G ( UChar sorb, } +/* Generate an IR sequence to do a count-leading-zeroes operation on + the supplied IRTemp, and return a new IRTemp holding the result. + 'ty' may be Ity_I16 or Ity_I32 only. In the case where the + argument is zero, return the number of bits in the word (the + natural semantics). */ +static IRTemp gen_LZCNT ( IRType ty, IRTemp src ) +{ + vassert(ty == Ity_I32 || ty == Ity_I16); + + IRTemp src32 = newTemp(Ity_I32); + assign(src32, widenUto32( mkexpr(src) )); + + IRTemp src32x = newTemp(Ity_I32); + assign(src32x, + binop(Iop_Shl32, mkexpr(src32), + mkU8(32 - 8 * sizeofIRType(ty)))); + + // Clz32 has undefined semantics when its input is zero, so + // special-case around that. + IRTemp res32 = newTemp(Ity_I32); + assign(res32, + IRExpr_Mux0X( + unop(Iop_1Uto8, + binop(Iop_CmpEQ32, mkexpr(src32x), mkU32(0))), + unop(Iop_Clz32, mkexpr(src32x)), + mkU32(8 * sizeofIRType(ty)) + )); + + IRTemp res = newTemp(ty); + assign(res, narrowTo(ty, mkexpr(res32))); + return res; +} + + /*------------------------------------------------------------*/ /*--- ---*/ /*--- x87 FLOATING POINT INSTRUCTIONS ---*/ @@ -4380,7 +4419,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) binop(Iop_Shl32, binop(Iop_CmpF64, get_ST(0), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, loadLE(Ity_I32,mkexpr(addr)))), mkU8(8)), mkU32(0x4500) @@ -4395,7 +4434,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) binop(Iop_Shl32, binop(Iop_CmpF64, get_ST(0), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, loadLE(Ity_I32,mkexpr(addr)))), mkU8(8)), mkU32(0x4500) @@ -4428,7 +4467,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) triop(fop, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ get_ST(0), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, loadLE(Ity_I32, mkexpr(addr))))); break; @@ -4436,7 +4475,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) put_ST_UNCHECKED(0, triop(fop, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ - unop(Iop_I32toF64, + unop(Iop_I32StoF64, loadLE(Ity_I32, mkexpr(addr))), get_ST(0))); break; @@ -4528,27 +4567,27 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) case 0: /* FILD m32int */ DIP("fildl %s\n", dis_buf); fp_push(); - put_ST(0, unop(Iop_I32toF64, + put_ST(0, unop(Iop_I32StoF64, loadLE(Ity_I32, mkexpr(addr)))); break; case 1: /* FISTTPL m32 (SSE3) */ DIP("fisttpl %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI32, mkU32(Irrm_ZERO), get_ST(0)) ); + binop(Iop_F64toI32S, mkU32(Irrm_ZERO), get_ST(0)) ); fp_pop(); break; case 2: /* FIST m32 */ DIP("fistl %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI32, get_roundingmode(), get_ST(0)) ); + binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ); break; case 3: /* FISTP m32 */ DIP("fistpl %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI32, get_roundingmode(), get_ST(0)) ); + binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ); fp_pop(); break; @@ -4844,7 +4883,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) case 1: /* FISTTPQ m64 (SSE3) */ DIP("fistppll %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI64, mkU32(Irrm_ZERO), get_ST(0)) ); + binop(Iop_F64toI64S, mkU32(Irrm_ZERO), get_ST(0)) ); fp_pop(); break; @@ -5069,7 +5108,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) binop(Iop_Shl32, binop(Iop_CmpF64, get_ST(0), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_16Sto32, loadLE(Ity_I16,mkexpr(addr))))), mkU8(8)), @@ -5085,7 +5124,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) binop(Iop_Shl32, binop(Iop_CmpF64, get_ST(0), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_16Sto32, loadLE(Ity_I16,mkexpr(addr))))), mkU8(8)), @@ -5119,7 +5158,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) triop(fop, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ get_ST(0), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(addr)))))); break; @@ -5128,7 +5167,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) put_ST_UNCHECKED(0, triop(fop, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(addr)))), get_ST(0))); @@ -5206,7 +5245,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) case 0: /* FILD m16int */ DIP("fildw %s\n", dis_buf); fp_push(); - put_ST(0, unop(Iop_I32toF64, + put_ST(0, unop(Iop_I32StoF64, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(addr))))); break; @@ -5214,27 +5253,27 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) case 1: /* FISTTPS m16 (SSE3) */ DIP("fisttps %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI16, mkU32(Irrm_ZERO), get_ST(0)) ); + binop(Iop_F64toI16S, mkU32(Irrm_ZERO), get_ST(0)) ); fp_pop(); break; case 2: /* FIST m16 */ DIP("fistp %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI16, get_roundingmode(), get_ST(0)) ); + binop(Iop_F64toI16S, get_roundingmode(), get_ST(0)) ); break; case 3: /* FISTP m16 */ DIP("fistps %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI16, get_roundingmode(), get_ST(0)) ); + binop(Iop_F64toI16S, get_roundingmode(), get_ST(0)) ); fp_pop(); break; case 5: /* FILD m64 */ DIP("fildll %s\n", dis_buf); fp_push(); - put_ST(0, binop(Iop_I64toF64, + put_ST(0, binop(Iop_I64StoF64, get_roundingmode(), loadLE(Ity_I64, mkexpr(addr)))); break; @@ -5242,7 +5281,7 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, Int delta ) case 7: /* FISTP m64 */ DIP("fistpll %s\n", dis_buf); storeLE( mkexpr(addr), - binop(Iop_F64toI64, get_roundingmode(), get_ST(0)) ); + binop(Iop_F64toI64S, get_roundingmode(), get_ST(0)) ); fp_pop(); break; @@ -6135,7 +6174,8 @@ static HChar* nameBtOp ( BtOp op ) static -UInt dis_bt_G_E ( UChar sorb, Bool locked, Int sz, Int delta, BtOp op ) +UInt dis_bt_G_E ( VexAbiInfo* vbi, + UChar sorb, Bool locked, Int sz, Int delta, BtOp op ) { HChar dis_buf[50]; UChar modrm; @@ -6165,7 +6205,12 @@ UInt dis_bt_G_E ( UChar sorb, Bool locked, Int sz, Int delta, BtOp op ) t_esp = newTemp(Ity_I32); t_addr0 = newTemp(Ity_I32); - assign( t_esp, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(sz)) ); + /* For the choice of the value 128, see comment in dis_bt_G_E in + guest_amd64_toIR.c. We point out here only that 128 is + fast-cased in Memcheck and is > 0, so seems like a good + choice. */ + vassert(vbi->guest_stack_redzone_size == 0); + assign( t_esp, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(128)) ); putIReg(4, R_ESP, mkexpr(t_esp)); storeLE( mkexpr(t_esp), getIReg(sz, eregOfRM(modrm)) ); @@ -6260,7 +6305,7 @@ UInt dis_bt_G_E ( UChar sorb, Bool locked, Int sz, Int delta, BtOp op ) if (epartIsReg(modrm)) { /* t_esp still points at it. */ putIReg(sz, eregOfRM(modrm), loadLE(szToITy(sz), mkexpr(t_esp)) ); - putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t_esp), mkU32(sz)) ); + putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t_esp), mkU32(128)) ); } DIP("bt%s%c %s, %s\n", @@ -6623,7 +6668,8 @@ UInt dis_xadd_G_E ( UChar sorb, Bool locked, Int sz, Int delta0, /* There are 3 cases to consider: - reg-reg: currently unhandled + reg-reg: ignore any lock prefix, + generate 'naive' (non-atomic) sequence reg-mem, not locked: ignore any lock prefix, generate 'naive' (non-atomic) sequence @@ -6633,9 +6679,18 @@ UInt dis_xadd_G_E ( UChar sorb, Bool locked, Int sz, Int delta0, if (epartIsReg(rm)) { /* case 1 */ - *decodeOK = False; - return delta0; - /* Currently we don't handle xadd_G_E with register operand. */ + assign( tmpd, getIReg(sz, eregOfRM(rm))); + assign( tmpt0, getIReg(sz, gregOfRM(rm)) ); + assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8), + mkexpr(tmpd), mkexpr(tmpt0)) ); + setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty ); + putIReg(sz, eregOfRM(rm), mkexpr(tmpt1)); + putIReg(sz, gregOfRM(rm), mkexpr(tmpd)); + DIP("xadd%c %s, %s\n", + nameISize(sz), nameIReg(sz,gregOfRM(rm)), + nameIReg(sz,eregOfRM(rm))); + *decodeOK = True; + return 1+delta0; } else if (!epartIsReg(rm) && !locked) { /* case 2 */ @@ -7802,9 +7857,11 @@ DisResult disInstr_X86_WRK ( /*OUT*/Bool* expect_CAS, Bool put_IP, Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, Long delta64, - VexArchInfo* archinfo + VexArchInfo* archinfo, + VexAbiInfo* vbi ) { IRType ty; @@ -7915,15 +7972,29 @@ DisResult disInstr_X86_WRK ( delta += 5; goto decode_success; } - /* don't barf on recent binutils padding - 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0(%eax,%eax,1) */ - if (code[0] == 0x66 - && code[1] == 0x2E && code[2] == 0x0F && code[3] == 0x1F - && code[4] == 0x84 && code[5] == 0x00 && code[6] == 0x00 - && code[7] == 0x00 && code[8] == 0x00 && code[9] == 0x00 ) { - DIP("nopw %%cs:0x0(%%eax,%%eax,1)\n"); - delta += 10; - goto decode_success; + /* Don't barf on recent binutils padding, + all variants of which are: nopw %cs:0x0(%eax,%eax,1) + 66 2e 0f 1f 84 00 00 00 00 00 + 66 66 2e 0f 1f 84 00 00 00 00 00 + 66 66 66 2e 0f 1f 84 00 00 00 00 00 + 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 + 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 + 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 + */ + if (code[0] == 0x66) { + Int data16_cnt; + for (data16_cnt = 1; data16_cnt < 6; data16_cnt++) + if (code[data16_cnt] != 0x66) + break; + if (code[data16_cnt] == 0x2E && code[data16_cnt + 1] == 0x0F + && code[data16_cnt + 2] == 0x1F && code[data16_cnt + 3] == 0x84 + && code[data16_cnt + 4] == 0x00 && code[data16_cnt + 5] == 0x00 + && code[data16_cnt + 6] == 0x00 && code[data16_cnt + 7] == 0x00 + && code[data16_cnt + 8] == 0x00 ) { + DIP("nopw %%cs:0x0(%%eax,%%eax,1)\n"); + delta += 9 + data16_cnt; + goto decode_success; + } } } @@ -8266,14 +8337,14 @@ DisResult disInstr_X86_WRK ( gregOfRM(modrm), 0, binop(Iop_F64toF32, mkexpr(rmode), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)) )) ); putXMMRegLane32F( gregOfRM(modrm), 1, binop(Iop_F64toF32, mkexpr(rmode), - unop(Iop_I32toF64, + unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)) )) ); goto decode_success; @@ -8306,7 +8377,7 @@ DisResult disInstr_X86_WRK ( gregOfRM(modrm), 0, binop(Iop_F64toF32, mkexpr(rmode), - unop(Iop_I32toF64, mkexpr(arg32)) ) ); + unop(Iop_I32StoF64, mkexpr(arg32)) ) ); goto decode_success; } @@ -8353,10 +8424,10 @@ DisResult disInstr_X86_WRK ( assign( dst64, binop( Iop_32HLto64, - binop( Iop_F64toI32, + binop( Iop_F64toI32S, mkexpr(rmode), unop( Iop_F32toF64, mkexpr(f32hi) ) ), - binop( Iop_F64toI32, + binop( Iop_F64toI32S, mkexpr(rmode), unop( Iop_F32toF64, mkexpr(f32lo) ) ) ) @@ -8400,7 +8471,7 @@ DisResult disInstr_X86_WRK ( } putIReg(4, gregOfRM(modrm), - binop( Iop_F64toI32, + binop( Iop_F64toI32S, mkexpr(rmode), unop( Iop_F32toF64, mkexpr(f32lo) ) ) ); @@ -8516,6 +8587,8 @@ DisResult disInstr_X86_WRK ( delta += 2+1; } else { addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + if (insn[1] == 0x28/*movaps*/) + gen_SEGV_if_not_16_aligned( addr ); putXMMReg( gregOfRM(modrm), loadLE(Ity_V128, mkexpr(addr)) ); DIP("mov[ua]ps %s,%s\n", dis_buf, @@ -8534,6 +8607,8 @@ DisResult disInstr_X86_WRK ( /* fall through; awaiting test case */ } else { addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + if (insn[1] == 0x29/*movaps*/) + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); DIP("mov[ua]ps %s,%s\n", nameXMMReg(gregOfRM(modrm)), dis_buf ); @@ -8660,6 +8735,7 @@ DisResult disInstr_X86_WRK ( modrm = getIByte(delta+2); if (!epartIsReg(modrm)) { addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); DIP("movntp%s %s,%s\n", sz==2 ? "d" : "s", dis_buf, @@ -9311,12 +9387,12 @@ DisResult disInstr_X86_WRK ( putXMMRegLane64F( gregOfRM(modrm), 0, - unop(Iop_I32toF64, unop(Iop_64to32, mkexpr(arg64))) + unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64))) ); putXMMRegLane64F( gregOfRM(modrm), 1, - unop(Iop_I32toF64, unop(Iop_64HIto32, mkexpr(arg64))) + unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64))) ); goto decode_success; @@ -9347,7 +9423,7 @@ DisResult disInstr_X86_WRK ( # define CVT(_t) binop( Iop_F64toF32, \ mkexpr(rmode), \ - unop(Iop_I32toF64,mkexpr(_t))) + unop(Iop_I32StoF64,mkexpr(_t))) putXMMRegLane32F( gregOfRM(modrm), 3, CVT(t3) ); putXMMRegLane32F( gregOfRM(modrm), 2, CVT(t2) ); @@ -9388,7 +9464,7 @@ DisResult disInstr_X86_WRK ( assign( t1, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, mkexpr(argV))) ); -# define CVT(_t) binop( Iop_F64toI32, \ +# define CVT(_t) binop( Iop_F64toI32S, \ mkexpr(rmode), \ mkexpr(_t) ) @@ -9444,8 +9520,8 @@ DisResult disInstr_X86_WRK ( assign( dst64, binop( Iop_32HLto64, - binop( Iop_F64toI32, mkexpr(rmode), mkexpr(f64hi) ), - binop( Iop_F64toI32, mkexpr(rmode), mkexpr(f64lo) ) + binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64hi) ), + binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo) ) ) ); @@ -9504,8 +9580,14 @@ DisResult disInstr_X86_WRK ( IRTemp arg64 = newTemp(Ity_I64); modrm = getIByte(delta+2); - do_MMX_preamble(); if (epartIsReg(modrm)) { + /* Only switch to MMX mode if the source is a MMX register. + This is inconsistent with all other instructions which + convert between XMM and (M64 or MMX), which always switch + to MMX mode even if 64-bit operand is M64 and not MMX. At + least, that's what the Intel docs seem to me to say. + Fixes #210264. */ + do_MMX_preamble(); assign( arg64, getMMXReg(eregOfRM(modrm)) ); delta += 2+1; DIP("cvtpi2pd %s,%s\n", nameMMXReg(eregOfRM(modrm)), @@ -9520,12 +9602,12 @@ DisResult disInstr_X86_WRK ( putXMMRegLane64F( gregOfRM(modrm), 0, - unop(Iop_I32toF64, unop(Iop_64to32, mkexpr(arg64)) ) + unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)) ) ); putXMMRegLane64F( gregOfRM(modrm), 1, - unop(Iop_I32toF64, unop(Iop_64HIto32, mkexpr(arg64)) ) + unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)) ) ); goto decode_success; @@ -9557,7 +9639,7 @@ DisResult disInstr_X86_WRK ( /* This is less than ideal. If it turns out to be a performance bottleneck it can be improved. */ # define CVT(_t) \ - binop( Iop_F64toI32, \ + binop( Iop_F64toI32S, \ mkexpr(rmode), \ unop( Iop_F32toF64, \ unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) @@ -9637,7 +9719,7 @@ DisResult disInstr_X86_WRK ( } putIReg(4, gregOfRM(modrm), - binop( Iop_F64toI32, mkexpr(rmode), mkexpr(f64lo)) ); + binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo)) ); goto decode_success; } @@ -9694,7 +9776,7 @@ DisResult disInstr_X86_WRK ( putXMMRegLane64F( gregOfRM(modrm), 0, - unop(Iop_I32toF64, mkexpr(arg32)) ); + unop(Iop_I32StoF64, mkexpr(arg32)) ); goto decode_success; } @@ -9754,7 +9836,7 @@ DisResult disInstr_X86_WRK ( assign( t1, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, mkexpr(argV))) ); -# define CVT(_t) binop( Iop_F64toI32, \ +# define CVT(_t) binop( Iop_F64toI32S, \ mkexpr(rmode), \ mkexpr(_t) ) @@ -9795,7 +9877,7 @@ DisResult disInstr_X86_WRK ( /* This is less than ideal. If it turns out to be a performance bottleneck it can be improved. */ # define CVT(_t) \ - binop( Iop_F64toI32, \ + binop( Iop_F64toI32S, \ mkexpr(rmode), \ unop( Iop_F32toF64, \ unop( Iop_ReinterpI32asF32, mkexpr(_t))) ) @@ -9879,6 +9961,8 @@ DisResult disInstr_X86_WRK ( delta += 2+1; } else { addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + if (insn[1] == 0x28/*movapd*/ || insn[1] == 0x6F/*movdqa*/) + gen_SEGV_if_not_16_aligned( addr ); putXMMReg( gregOfRM(modrm), loadLE(Ity_V128, mkexpr(addr)) ); DIP("mov%s %s,%s\n", wot, dis_buf, @@ -9898,6 +9982,8 @@ DisResult disInstr_X86_WRK ( /* fall through; awaiting test case */ } else { addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + if (insn[1] == 0x29/*movapd*/) + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRM(modrm)), dis_buf ); @@ -9960,6 +10046,7 @@ DisResult disInstr_X86_WRK ( } else { addr = disAMode( &alen, sorb, delta+2, dis_buf ); delta += 2+alen; + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); DIP("movdqa %s, %s\n", nameXMMReg(gregOfRM(modrm)), dis_buf); } @@ -10171,6 +10258,7 @@ DisResult disInstr_X86_WRK ( modrm = getIByte(delta+2); if (sz == 2 && !epartIsReg(modrm)) { addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + gen_SEGV_if_not_16_aligned( addr ); storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) ); DIP("movntdq %s,%s\n", dis_buf, nameXMMReg(gregOfRM(modrm))); @@ -11473,6 +11561,7 @@ DisResult disInstr_X86_WRK ( delta += 3+1; } else { addr = disAMode ( &alen, sorb, delta+3, dis_buf ); + gen_SEGV_if_not_16_aligned( addr ); assign( sV, loadLE(Ity_V128, mkexpr(addr)) ); DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l', dis_buf, @@ -12499,6 +12588,126 @@ DisResult disInstr_X86_WRK ( /* --- end of the SSSE3 decoder. --- */ /* ---------------------------------------------------- */ + /* ---------------------------------------------------- */ + /* --- start of the SSE4 decoder --- */ + /* ---------------------------------------------------- */ + + /* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1 + (Partial implementation only -- only deal with cases where + the rounding mode is specified directly by the immediate byte.) + 66 0F 3A 0A /r ib = ROUNDSS imm8, xmm2/m32, xmm1 + (Limitations ditto) + */ + if (sz == 2 + && insn[0] == 0x0F && insn[1] == 0x3A + && (/*insn[2] == 0x0B || */insn[2] == 0x0A)) { + + Bool isD = insn[2] == 0x0B; + IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32); + IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32); + Int imm = 0; + + modrm = insn[3]; + + if (epartIsReg(modrm)) { + assign( src, + isD ? getXMMRegLane64F( eregOfRM(modrm), 0 ) + : getXMMRegLane32F( eregOfRM(modrm), 0 ) ); + imm = insn[3+1]; + if (imm & ~3) goto decode_failure; + delta += 3+1+1; + DIP( "rounds%c $%d,%s,%s\n", + isD ? 'd' : 's', + imm, nameXMMReg( eregOfRM(modrm) ), + nameXMMReg( gregOfRM(modrm) ) ); + } else { + addr = disAMode( &alen, sorb, delta+3, dis_buf ); + assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) )); + imm = insn[3+alen]; + if (imm & ~3) goto decode_failure; + delta += 3+alen+1; + DIP( "roundsd $%d,%s,%s\n", + imm, dis_buf, nameXMMReg( gregOfRM(modrm) ) ); + } + + /* (imm & 3) contains an Intel-encoded rounding mode. Because + that encoding is the same as the encoding for IRRoundingMode, + we can use that value directly in the IR as a rounding + mode. */ + assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt, + mkU32(imm & 3), mkexpr(src)) ); + + if (isD) + putXMMRegLane64F( gregOfRM(modrm), 0, mkexpr(res) ); + else + putXMMRegLane32F( gregOfRM(modrm), 0, mkexpr(res) ); + + goto decode_success; + } + + /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension, + which we can only decode if we're sure this is an AMD cpu that + supports LZCNT, since otherwise it's BSR, which behaves + differently. */ + if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xBD + && 0 != (archinfo->hwcaps & VEX_HWCAPS_X86_LZCNT)) { + vassert(sz == 2 || sz == 4); + /*IRType*/ ty = szToITy(sz); + IRTemp src = newTemp(ty); + modrm = insn[3]; + if (epartIsReg(modrm)) { + assign(src, getIReg(sz, eregOfRM(modrm))); + delta += 3+1; + DIP("lzcnt%c %s, %s\n", nameISize(sz), + nameIReg(sz, eregOfRM(modrm)), + nameIReg(sz, gregOfRM(modrm))); + } else { + addr = disAMode( &alen, sorb, delta+3, dis_buf ); + assign(src, loadLE(ty, mkexpr(addr))); + delta += 3+alen; + DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf, + nameIReg(sz, gregOfRM(modrm))); + } + + IRTemp res = gen_LZCNT(ty, src); + putIReg(sz, gregOfRM(modrm), mkexpr(res)); + + // Update flags. This is pretty lame .. perhaps can do better + // if this turns out to be performance critical. + // O S A P are cleared. Z is set if RESULT == 0. + // C is set if SRC is zero. + IRTemp src32 = newTemp(Ity_I32); + IRTemp res32 = newTemp(Ity_I32); + assign(src32, widenUto32(mkexpr(src))); + assign(res32, widenUto32(mkexpr(res))); + + IRTemp oszacp = newTemp(Ity_I32); + assign( + oszacp, + binop(Iop_Or32, + binop(Iop_Shl32, + unop(Iop_1Uto32, + binop(Iop_CmpEQ32, mkexpr(res32), mkU32(0))), + mkU8(X86G_CC_SHIFT_Z)), + binop(Iop_Shl32, + unop(Iop_1Uto32, + binop(Iop_CmpEQ32, mkexpr(src32), mkU32(0))), + mkU8(X86G_CC_SHIFT_C)) + ) + ); + + stmt( IRStmt_Put( OFFB_CC_OP, mkU32(X86G_CC_OP_COPY) )); + stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) )); + stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) )); + stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) )); + + goto decode_success; + } + + /* ---------------------------------------------------- */ + /* --- end of the SSE4 decoder --- */ + /* ---------------------------------------------------- */ + after_sse_decoders: /* ---------------------------------------------------- */ @@ -12596,7 +12805,7 @@ DisResult disInstr_X86_WRK ( storeLE( mkexpr(t1), mkU32(guest_EIP_bbstart+delta)); if (resteerOkFn( callback_opaque, (Addr64)(Addr32)d32 )) { /* follow into the call target. */ - dres.whatNext = Dis_Resteer; + dres.whatNext = Dis_ResteerU; dres.continueAt = (Addr64)(Addr32)d32; } else { jmp_lit(Ijk_Call,d32); @@ -12882,7 +13091,7 @@ DisResult disInstr_X86_WRK ( d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); delta++; if (resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { - dres.whatNext = Dis_Resteer; + dres.whatNext = Dis_ResteerU; dres.continueAt = (Addr64)(Addr32)d32; } else { jmp_lit(Ijk_Boring,d32); @@ -12896,7 +13105,7 @@ DisResult disInstr_X86_WRK ( d32 = (((Addr32)guest_EIP_bbstart)+delta+sz) + getSDisp(sz,delta); delta += sz; if (resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { - dres.whatNext = Dis_Resteer; + dres.whatNext = Dis_ResteerU; dres.continueAt = (Addr64)(Addr32)d32; } else { jmp_lit(Ijk_Boring,d32); @@ -12921,28 +13130,60 @@ DisResult disInstr_X86_WRK ( case 0x7D: /* JGEb/JNLb (jump greater or equal) */ case 0x7E: /* JLEb/JNGb (jump less or equal) */ case 0x7F: /* JGb/JNLEb (jump greater) */ - d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta); + { Int jmpDelta; + HChar* comment = ""; + jmpDelta = (Int)getSDisp8(delta); + vassert(-128 <= jmpDelta && jmpDelta < 128); + d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + jmpDelta; delta++; - if (0 && resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { - /* Unused experimental hack: speculatively follow one arm - of a conditional branch. */ - /* Assume the branch is taken. So we need to emit a - side-exit to the insn following this one, on the negation - of the condition, and continue at the branch target - address (d32). */ - if (0) vex_printf("resteer\n"); + if (resteerCisOk + && vex_control.guest_chase_cond + && (Addr32)d32 != (Addr32)guest_EIP_bbstart + && jmpDelta < 0 + && resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { + /* Speculation: assume this backward branch is taken. So we + need to emit a side-exit to the insn following this one, + on the negation of the condition, and continue at the + branch target address (d32). If we wind up back at the + first instruction of the trace, just stop; it's better to + let the IR loop unroller handle that case. */ stmt( IRStmt_Exit( mk_x86g_calculate_condition((X86Condcode)(1 ^ (opc - 0x70))), Ijk_Boring, IRConst_U32(guest_EIP_bbstart+delta) ) ); - dres.whatNext = Dis_Resteer; + dres.whatNext = Dis_ResteerC; dres.continueAt = (Addr64)(Addr32)d32; - } else { - jcc_01((X86Condcode)(opc - 0x70), (Addr32)(guest_EIP_bbstart+delta), d32); + comment = "(assumed taken)"; + } + else + if (resteerCisOk + && vex_control.guest_chase_cond + && (Addr32)d32 != (Addr32)guest_EIP_bbstart + && jmpDelta >= 0 + && resteerOkFn( callback_opaque, + (Addr64)(Addr32)(guest_EIP_bbstart+delta)) ) { + /* Speculation: assume this forward branch is not taken. So + we need to emit a side-exit to d32 (the dest) and continue + disassembling at the insn immediately following this + one. */ + stmt( IRStmt_Exit( + mk_x86g_calculate_condition((X86Condcode)(opc - 0x70)), + Ijk_Boring, + IRConst_U32(d32) ) ); + dres.whatNext = Dis_ResteerC; + dres.continueAt = (Addr64)(Addr32)(guest_EIP_bbstart+delta); + comment = "(assumed not taken)"; + } + else { + /* Conservative default translation - end the block at this + point. */ + jcc_01( (X86Condcode)(opc - 0x70), + (Addr32)(guest_EIP_bbstart+delta), d32); dres.whatNext = Dis_StopHere; } - DIP("j%s-8 0x%x\n", name_X86Condcode(opc - 0x70), d32); + DIP("j%s-8 0x%x %s\n", name_X86Condcode(opc - 0x70), d32, comment); break; + } case 0xE3: /* JECXZ (for JCXZ see above) */ if (sz != 4) goto decode_failure; @@ -14139,16 +14380,16 @@ DisResult disInstr_X86_WRK ( /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */ case 0xA3: /* BT Gv,Ev */ - delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpNone ); + delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpNone ); break; case 0xB3: /* BTR Gv,Ev */ - delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpReset ); + delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpReset ); break; case 0xAB: /* BTS Gv,Ev */ - delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpSet ); + delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpSet ); break; case 0xBB: /* BTC Gv,Ev */ - delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpComp ); + delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpComp ); break; /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */ @@ -14392,9 +14633,9 @@ DisResult disInstr_X86_WRK ( break; case 0xBF: /* MOVSXw Ew,Gv */ - if (sz != 4) + if (sz != 4 && /* accept movsww, sigh, see #250799 */sz != 2) goto decode_failure; - delta = dis_movx_E_G ( sorb, delta, 2, 4, True ); + delta = dis_movx_E_G ( sorb, delta, 2, sz, True ); break; //-- /* =-=-=-=-=-=-=-=-=-=-= MOVNTI -=-=-=-=-=-=-=-=-= */ @@ -14445,14 +14686,60 @@ DisResult disInstr_X86_WRK ( case 0x8D: /* JGEb/JNLb (jump greater or equal) */ case 0x8E: /* JLEb/JNGb (jump less or equal) */ case 0x8F: /* JGb/JNLEb (jump greater) */ - d32 = (((Addr32)guest_EIP_bbstart)+delta+4) + getUDisp32(delta); + { Int jmpDelta; + HChar* comment = ""; + jmpDelta = (Int)getUDisp32(delta); + d32 = (((Addr32)guest_EIP_bbstart)+delta+4) + jmpDelta; delta += 4; - jcc_01( (X86Condcode)(opc - 0x80), - (Addr32)(guest_EIP_bbstart+delta), - d32 ); - dres.whatNext = Dis_StopHere; - DIP("j%s-32 0x%x\n", name_X86Condcode(opc - 0x80), d32); + if (resteerCisOk + && vex_control.guest_chase_cond + && (Addr32)d32 != (Addr32)guest_EIP_bbstart + && jmpDelta < 0 + && resteerOkFn( callback_opaque, (Addr64)(Addr32)d32) ) { + /* Speculation: assume this backward branch is taken. So + we need to emit a side-exit to the insn following this + one, on the negation of the condition, and continue at + the branch target address (d32). If we wind up back at + the first instruction of the trace, just stop; it's + better to let the IR loop unroller handle that case.*/ + stmt( IRStmt_Exit( + mk_x86g_calculate_condition((X86Condcode) + (1 ^ (opc - 0x80))), + Ijk_Boring, + IRConst_U32(guest_EIP_bbstart+delta) ) ); + dres.whatNext = Dis_ResteerC; + dres.continueAt = (Addr64)(Addr32)d32; + comment = "(assumed taken)"; + } + else + if (resteerCisOk + && vex_control.guest_chase_cond + && (Addr32)d32 != (Addr32)guest_EIP_bbstart + && jmpDelta >= 0 + && resteerOkFn( callback_opaque, + (Addr64)(Addr32)(guest_EIP_bbstart+delta)) ) { + /* Speculation: assume this forward branch is not taken. + So we need to emit a side-exit to d32 (the dest) and + continue disassembling at the insn immediately + following this one. */ + stmt( IRStmt_Exit( + mk_x86g_calculate_condition((X86Condcode)(opc - 0x80)), + Ijk_Boring, + IRConst_U32(d32) ) ); + dres.whatNext = Dis_ResteerC; + dres.continueAt = (Addr64)(Addr32)(guest_EIP_bbstart+delta); + comment = "(assumed not taken)"; + } + else { + /* Conservative default translation - end the block at + this point. */ + jcc_01( (X86Condcode)(opc - 0x80), + (Addr32)(guest_EIP_bbstart+delta), d32); + dres.whatNext = Dis_StopHere; + } + DIP("j%s-32 0x%x %s\n", name_X86Condcode(opc - 0x80), d32, comment); break; + } /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */ case 0x31: { /* RDTSC */ @@ -14689,6 +14976,41 @@ DisResult disInstr_X86_WRK ( DIP("emms\n"); break; + /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */ + case 0x01: /* 0F 01 /0 -- SGDT */ + /* 0F 01 /1 -- SIDT */ + { + /* This is really revolting, but ... since each processor + (core) only has one IDT and one GDT, just let the guest + see it (pass-through semantics). I can't see any way to + construct a faked-up value, so don't bother to try. */ + modrm = getUChar(delta); + addr = disAMode ( &alen, sorb, delta, dis_buf ); + delta += alen; + if (epartIsReg(modrm)) goto decode_failure; + if (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1) + goto decode_failure; + switch (gregOfRM(modrm)) { + case 0: DIP("sgdt %s\n", dis_buf); break; + case 1: DIP("sidt %s\n", dis_buf); break; + default: vassert(0); /*NOTREACHED*/ + } + + IRDirty* d = unsafeIRDirty_0_N ( + 0/*regparms*/, + "x86g_dirtyhelper_SxDT", + &x86g_dirtyhelper_SxDT, + mkIRExprVec_2( mkexpr(addr), + mkU32(gregOfRM(modrm)) ) + ); + /* declare we're writing memory */ + d->mFx = Ifx_Write; + d->mAddr = mkexpr(addr); + d->mSize = 6; + stmt( IRStmt_Dirty(d) ); + break; + } + /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */ default: @@ -14749,6 +15071,7 @@ DisResult disInstr_X86_WRK ( DisResult disInstr_X86 ( IRSB* irsb_IN, Bool put_IP, Bool (*resteerOkFn) ( void*, Addr64 ), + Bool resteerCisOk, void* callback_opaque, UChar* guest_code_IN, Long delta, @@ -14773,7 +15096,9 @@ DisResult disInstr_X86 ( IRSB* irsb_IN, x1 = irsb_IN->stmts_used; expect_CAS = False; dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn, - callback_opaque, delta, archinfo ); + resteerCisOk, + callback_opaque, + delta, archinfo, abiinfo ); x2 = irsb_IN->stmts_used; vassert(x2 >= x1); @@ -14791,7 +15116,9 @@ DisResult disInstr_X86 ( IRSB* irsb_IN, to generate a useful error message; then assert. */ vex_traceflags |= VEX_TRACE_FE; dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn, - callback_opaque, delta, archinfo ); + resteerCisOk, + callback_opaque, + delta, archinfo, abiinfo ); for (i = x1; i < x2; i++) { vex_printf("\t\t"); ppIRStmt(irsb_IN->stmts[i]); diff --git a/VEX/priv/host_amd64_defs.c b/VEX/priv/host_amd64_defs.c index f231d36..80bb6d8 100644 --- a/VEX/priv/host_amd64_defs.c +++ b/VEX/priv/host_amd64_defs.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_amd64_defs.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_amd64_defs.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -748,11 +737,12 @@ AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode cond, AMD64RM* src, HReg dst ) { vassert(cond != Acc_ALWAYS); return i; } -AMD64Instr* AMD64Instr_MovZLQ ( HReg src, HReg dst ) { - AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr)); - i->tag = Ain_MovZLQ; - i->Ain.MovZLQ.src = src; - i->Ain.MovZLQ.dst = dst; +AMD64Instr* AMD64Instr_MovxLQ ( Bool syned, HReg src, HReg dst ) { + AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr)); + i->tag = Ain_MovxLQ; + i->Ain.MovxLQ.syned = syned; + i->Ain.MovxLQ.src = src; + i->Ain.MovxLQ.dst = dst; return i; } AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned, @@ -820,12 +810,14 @@ AMD64Instr* AMD64Instr_A87Free ( Int nregs ) vassert(nregs >= 1 && nregs <= 7); return i; } -AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush ) +AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB ) { AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr)); i->tag = Ain_A87PushPop; i->Ain.A87PushPop.addr = addr; i->Ain.A87PushPop.isPush = isPush; + i->Ain.A87PushPop.szB = szB; + vassert(szB == 8 || szB == 4); return i; } AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op ) @@ -1147,11 +1139,11 @@ void ppAMD64Instr ( AMD64Instr* i, Bool mode64 ) vex_printf(","); ppHRegAMD64(i->Ain.CMov64.dst); return; - case Ain_MovZLQ: - vex_printf("movzlq "); - ppHRegAMD64_lo32(i->Ain.MovZLQ.src); + case Ain_MovxLQ: + vex_printf("mov%clq ", i->Ain.MovxLQ.syned ? 's' : 'z'); + ppHRegAMD64_lo32(i->Ain.MovxLQ.src); vex_printf(","); - ppHRegAMD64(i->Ain.MovZLQ.dst); + ppHRegAMD64(i->Ain.MovxLQ.dst); return; case Ain_LoadEX: if (i->Ain.LoadEX.szSmall==4 && !i->Ain.LoadEX.syned) { @@ -1206,7 +1198,8 @@ void ppAMD64Instr ( AMD64Instr* i, Bool mode64 ) vex_printf("ffree %%st(7..%d)", 8 - i->Ain.A87Free.nregs ); break; case Ain_A87PushPop: - vex_printf(i->Ain.A87PushPop.isPush ? "fldl " : "fstpl "); + vex_printf(i->Ain.A87PushPop.isPush ? "fld%c " : "fstp%c ", + i->Ain.A87PushPop.szB == 4 ? 's' : 'l'); ppAMD64AMode(i->Ain.A87PushPop.addr); break; case Ain_A87FpOp: @@ -1518,9 +1511,9 @@ void getRegUsage_AMD64Instr ( HRegUsage* u, AMD64Instr* i, Bool mode64 ) addRegUsage_AMD64RM(u, i->Ain.CMov64.src, HRmRead); addHRegUse(u, HRmModify, i->Ain.CMov64.dst); return; - case Ain_MovZLQ: - addHRegUse(u, HRmRead, i->Ain.MovZLQ.src); - addHRegUse(u, HRmWrite, i->Ain.MovZLQ.dst); + case Ain_MovxLQ: + addHRegUse(u, HRmRead, i->Ain.MovxLQ.src); + addHRegUse(u, HRmWrite, i->Ain.MovxLQ.dst); return; case Ain_LoadEX: addRegUsage_AMD64AMode(u, i->Ain.LoadEX.src); @@ -1748,9 +1741,9 @@ void mapRegs_AMD64Instr ( HRegRemap* m, AMD64Instr* i, Bool mode64 ) mapRegs_AMD64RM(m, i->Ain.CMov64.src); mapReg(m, &i->Ain.CMov64.dst); return; - case Ain_MovZLQ: - mapReg(m, &i->Ain.MovZLQ.src); - mapReg(m, &i->Ain.MovZLQ.dst); + case Ain_MovxLQ: + mapReg(m, &i->Ain.MovxLQ.src); + mapReg(m, &i->Ain.MovxLQ.dst); return; case Ain_LoadEX: mapRegs_AMD64AMode(m, i->Ain.LoadEX.src); @@ -1912,37 +1905,44 @@ Bool isMove_AMD64Instr ( AMD64Instr* i, HReg* src, HReg* dst ) register allocator. Note it's critical these don't write the condition codes. */ -AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offsetB, Bool mode64 ) +void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) { AMD64AMode* am; vassert(offsetB >= 0); vassert(!hregIsVirtual(rreg)); vassert(mode64 == True); + *i1 = *i2 = NULL; am = AMD64AMode_IR(offsetB, hregAMD64_RBP()); - switch (hregClass(rreg)) { case HRcInt64: - return AMD64Instr_Alu64M ( Aalu_MOV, AMD64RI_Reg(rreg), am ); + *i1 = AMD64Instr_Alu64M ( Aalu_MOV, AMD64RI_Reg(rreg), am ); + return; case HRcVec128: - return AMD64Instr_SseLdSt ( False/*store*/, 16, rreg, am ); + *i1 = AMD64Instr_SseLdSt ( False/*store*/, 16, rreg, am ); + return; default: ppHRegClass(hregClass(rreg)); vpanic("genSpill_AMD64: unimplemented regclass"); } } -AMD64Instr* genReload_AMD64 ( HReg rreg, Int offsetB, Bool mode64 ) +void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) { AMD64AMode* am; vassert(offsetB >= 0); vassert(!hregIsVirtual(rreg)); vassert(mode64 == True); + *i1 = *i2 = NULL; am = AMD64AMode_IR(offsetB, hregAMD64_RBP()); switch (hregClass(rreg)) { case HRcInt64: - return AMD64Instr_Alu64R ( Aalu_MOV, AMD64RMI_Mem(am), rreg ); + *i1 = AMD64Instr_Alu64R ( Aalu_MOV, AMD64RMI_Mem(am), rreg ); + return; case HRcVec128: - return AMD64Instr_SseLdSt ( True/*load*/, 16, rreg, am ); + *i1 = AMD64Instr_SseLdSt ( True/*load*/, 16, rreg, am ); + return; default: ppHRegClass(hregClass(rreg)); vpanic("genReload_AMD64: unimplemented regclass"); @@ -2335,10 +2335,26 @@ Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i, if (i->Ain.Alu64R.op == Aalu_MOV) { switch (i->Ain.Alu64R.src->tag) { case Armi_Imm: - *p++ = toUChar(0x48 + (1 & iregBit3(i->Ain.Alu64R.dst))); - *p++ = 0xC7; - *p++ = toUChar(0xC0 + iregBits210(i->Ain.Alu64R.dst)); - p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32); + if (0 == (i->Ain.Alu64R.src->Armi.Imm.imm32 & ~0xFFF)) { + /* Actually we could use this form for constants in + the range 0 through 0x7FFFFFFF inclusive, but + limit it to a small range for verifiability + purposes. */ + /* Generate "movl $imm32, 32-bit-register" and let + the default zero-extend rule cause the upper half + of the dst to be zeroed out too. This saves 1 + and sometimes 2 bytes compared to the more + obvious encoding in the 'else' branch. */ + if (1 & iregBit3(i->Ain.Alu64R.dst)) + *p++ = 0x41; + *p++ = 0xB8 + iregBits210(i->Ain.Alu64R.dst); + p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32); + } else { + *p++ = toUChar(0x48 + (1 & iregBit3(i->Ain.Alu64R.dst))); + *p++ = 0xC7; + *p++ = toUChar(0xC0 + iregBits210(i->Ain.Alu64R.dst)); + p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32); + } goto done; case Armi_Reg: *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg, @@ -2815,13 +2831,22 @@ Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i, } break; - case Ain_MovZLQ: - /* Produce a 32-bit reg-reg move, since the implicit zero-extend - does what we want. */ - *p++ = clearWBit ( - rexAMode_R(i->Ain.MovZLQ.src, i->Ain.MovZLQ.dst)); - *p++ = 0x89; - p = doAMode_R(p, i->Ain.MovZLQ.src, i->Ain.MovZLQ.dst); + case Ain_MovxLQ: + /* No, _don't_ ask me why the sense of the args has to be + different in the S vs Z case. I don't know. */ + if (i->Ain.MovxLQ.syned) { + /* Need REX.W = 1 here, but rexAMode_R does that for us. */ + *p++ = rexAMode_R(i->Ain.MovxLQ.dst, i->Ain.MovxLQ.src); + *p++ = 0x63; + p = doAMode_R(p, i->Ain.MovxLQ.dst, i->Ain.MovxLQ.src); + } else { + /* Produce a 32-bit reg-reg move, since the implicit + zero-extend does what we want. */ + *p++ = clearWBit ( + rexAMode_R(i->Ain.MovxLQ.src, i->Ain.MovxLQ.dst)); + *p++ = 0x89; + p = doAMode_R(p, i->Ain.MovxLQ.src, i->Ain.MovxLQ.dst); + } goto done; case Ain_LoadEX: @@ -2936,17 +2961,18 @@ Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i, goto done; case Ain_A87PushPop: + vassert(i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4); if (i->Ain.A87PushPop.isPush) { - /* Load from memory into %st(0): fldl amode */ + /* Load from memory into %st(0): flds/fldl amode */ *p++ = clearWBit( rexAMode_M(fake(0), i->Ain.A87PushPop.addr) ); - *p++ = 0xDD; + *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD; p = doAMode_M(p, fake(0)/*subopcode*/, i->Ain.A87PushPop.addr); } else { - /* Dump %st(0) to memory: fstpl amode */ + /* Dump %st(0) to memory: fstps/fstpl amode */ *p++ = clearWBit( rexAMode_M(fake(3), i->Ain.A87PushPop.addr) ); - *p++ = 0xDD; + *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD; p = doAMode_M(p, fake(3)/*subopcode*/, i->Ain.A87PushPop.addr); goto done; } diff --git a/VEX/priv/host_amd64_defs.h b/VEX/priv/host_amd64_defs.h index a609794..cf19bac 100644 --- a/VEX/priv/host_amd64_defs.h +++ b/VEX/priv/host_amd64_defs.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_amd64_defs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_amd64_defs.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -377,7 +366,7 @@ typedef Ain_Call, /* call to address in register */ Ain_Goto, /* conditional/unconditional jmp to dst */ Ain_CMov64, /* conditional move */ - Ain_MovZLQ, /* reg-reg move, zeroing out top half */ + Ain_MovxLQ, /* reg-reg move, zx-ing/sx-ing top half */ Ain_LoadEX, /* mov{s,z}{b,w,l}q from mem to reg */ Ain_Store, /* store 32/16/8 bit value in memory */ Ain_Set64, /* convert condition code to 64-bit value */ @@ -504,11 +493,12 @@ typedef AMD64RM* src; HReg dst; } CMov64; - /* reg-reg move, zeroing out top half */ + /* reg-reg move, sx-ing/zx-ing top half */ struct { + Bool syned; HReg src; HReg dst; - } MovZLQ; + } MovxLQ; /* Sign/Zero extending loads. Dst size is always 64 bits. */ struct { UChar szSmall; /* only 1, 2 or 4 */ @@ -557,12 +547,13 @@ typedef Int nregs; /* 1 <= nregs <= 7 */ } A87Free; - /* Push a 64-bit FP value from memory onto the stack, or move - a value from the stack to memory and remove it from the - stack. */ + /* Push a 32- or 64-bit FP value from memory onto the stack, + or move a value from the stack to memory and remove it + from the stack. */ struct { AMD64AMode* addr; Bool isPush; + UChar szB; /* 4 or 8 */ } A87PushPop; /* Do an operation on the top-of-stack. This can be unary, in @@ -694,7 +685,7 @@ extern AMD64Instr* AMD64Instr_Push ( AMD64RMI* ); extern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int ); extern AMD64Instr* AMD64Instr_Goto ( IRJumpKind, AMD64CondCode cond, AMD64RI* dst ); extern AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode, AMD64RM* src, HReg dst ); -extern AMD64Instr* AMD64Instr_MovZLQ ( HReg src, HReg dst ); +extern AMD64Instr* AMD64Instr_MovxLQ ( Bool syned, HReg src, HReg dst ); extern AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned, AMD64AMode* src, HReg dst ); extern AMD64Instr* AMD64Instr_Store ( UChar sz, HReg src, AMD64AMode* dst ); @@ -705,7 +696,7 @@ extern AMD64Instr* AMD64Instr_ACAS ( AMD64AMode* addr, UChar sz ); extern AMD64Instr* AMD64Instr_DACAS ( AMD64AMode* addr, UChar sz ); extern AMD64Instr* AMD64Instr_A87Free ( Int nregs ); -extern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush ); +extern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB ); extern AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op ); extern AMD64Instr* AMD64Instr_A87LdCW ( AMD64AMode* addr ); extern AMD64Instr* AMD64Instr_A87StSW ( AMD64AMode* addr ); @@ -744,8 +735,12 @@ extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool ); extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* ); extern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr*, Bool, void* dispatch ); -extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset, Bool ); -extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset, Bool ); + +extern void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offset, Bool ); +extern void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offset, Bool ); + extern void getAllocableRegs_AMD64 ( Int*, HReg** ); extern HInstrArray* iselSB_AMD64 ( IRSB*, VexArch, VexArchInfo*, diff --git a/VEX/priv/host_amd64_isel.c b/VEX/priv/host_amd64_isel.c index e14d3f8..a54444a 100644 --- a/VEX/priv/host_amd64_isel.c +++ b/VEX/priv/host_amd64_isel.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_amd64_isel.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_amd64_isel.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -53,6 +42,7 @@ #include "main_globals.h" #include "host_generic_regs.h" #include "host_generic_simd64.h" +#include "host_generic_simd128.h" #include "host_amd64_defs.h" @@ -329,6 +319,20 @@ static void sub_from_rsp ( ISelEnv* env, Int n ) hregAMD64_RSP())); } +/* Push 64-bit constants on the stack. */ +static void push_uimm64( ISelEnv* env, ULong uimm64 ) +{ + /* If uimm64 can be expressed as the sign extension of its + lower 32 bits, we can do it the easy way. */ + Long simm64 = (Long)uimm64; + if ( simm64 == ((simm64 << 32) >> 32) ) { + addInstr( env, AMD64Instr_Push(AMD64RMI_Imm( (UInt)uimm64 )) ); + } else { + HReg tmp = newVRegI(env); + addInstr( env, AMD64Instr_Imm64(uimm64, tmp) ); + addInstr( env, AMD64Instr_Push(AMD64RMI_Reg(tmp)) ); + } +} //.. /* Given an amode, return one which references 4 bytes further //.. along. */ @@ -413,7 +417,7 @@ static AMD64Instr* iselIntExpr_single_instruction ( ISelEnv* env, && e->Iex.Unop.op == Iop_32Uto64 && e->Iex.Unop.arg->tag == Iex_RdTmp) { HReg src = lookupIRTemp(env, e->Iex.Unop.arg->Iex.RdTmp.tmp); - return AMD64Instr_MovZLQ(src, dst); + return AMD64Instr_MovxLQ(False, src, dst); } if (0) { ppIRExpr(e); vex_printf("\n"); } @@ -784,6 +788,21 @@ static HReg do_sse_NotV128 ( ISelEnv* env, HReg src ) } +/* Expand the given byte into a 64-bit word, by cloning each bit + 8 times. */ +static ULong bitmask8_to_bytemask64 ( UShort w8 ) +{ + vassert(w8 == (w8 & 0xFF)); + ULong w64 = 0; + Int i; + for (i = 0; i < 8; i++) { + if (w8 & (1<type_env,e); vassert(ty == Ity_I32 || Ity_I16 || Ity_I8); @@ -860,8 +880,6 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) /* We can't handle big-endian loads, nor load-linked. */ if (e->Iex.Load.end != Iend_LE) goto irreducible; - if (e->Iex.Load.isLL) - goto irreducible; if (ty == Ity_I64) { addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, @@ -960,7 +978,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) Aalu_AND, AMD64RMI_Imm(0xFFFF), dst)); break; case Iop_Shr32: - addInstr(env, AMD64Instr_MovZLQ(dst,dst)); + addInstr(env, AMD64Instr_MovxLQ(False, dst, dst)); break; case Iop_Sar8: addInstr(env, AMD64Instr_Sh64(Ash_SHL, 56, dst)); @@ -971,8 +989,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) addInstr(env, AMD64Instr_Sh64(Ash_SAR, 48, dst)); break; case Iop_Sar32: - addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, dst)); - addInstr(env, AMD64Instr_Sh64(Ash_SAR, 32, dst)); + addInstr(env, AMD64Instr_MovxLQ(True, dst, dst)); break; default: ppIROp(e->Iex.Binop.op); @@ -1142,7 +1159,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); if (second_is_UInt) - addInstr(env, AMD64Instr_MovZLQ(argR, argR)); + addInstr(env, AMD64Instr_MovxLQ(False, argR, argR)); addInstr(env, mk_iMOVsd_RR(argL, hregAMD64_RDI()) ); addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RSI()) ); addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 2 )); @@ -1187,8 +1204,8 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) addInstr(env, mk_iMOVsd_RR(left64, rax)); addInstr(env, AMD64Instr_Sh64(Ash_SHR, 32, rdx)); addInstr(env, AMD64Instr_Div(syned, 4, rmRight)); - addInstr(env, AMD64Instr_MovZLQ(rdx,rdx)); - addInstr(env, AMD64Instr_MovZLQ(rax,rax)); + addInstr(env, AMD64Instr_MovxLQ(False, rdx, rdx)); + addInstr(env, AMD64Instr_MovxLQ(False, rax, rax)); addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, rdx)); addInstr(env, mk_iMOVsd_RR(rax, dst)); addInstr(env, AMD64Instr_Alu64R(Aalu_OR, AMD64RMI_Reg(rdx), dst)); @@ -1203,7 +1220,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) addInstr(env, mk_iMOVsd_RR(hi32s, hi32)); addInstr(env, mk_iMOVsd_RR(lo32s, lo32)); addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, hi32)); - addInstr(env, AMD64Instr_MovZLQ(lo32,lo32)); + addInstr(env, AMD64Instr_MovxLQ(False, lo32, lo32)); addInstr(env, AMD64Instr_Alu64R( Aalu_OR, AMD64RMI_Reg(lo32), hi32)); return hi32; @@ -1282,9 +1299,9 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) return dst; } - if (e->Iex.Binop.op == Iop_F64toI32 - || e->Iex.Binop.op == Iop_F64toI64) { - Int szD = e->Iex.Binop.op==Iop_F64toI32 ? 4 : 8; + if (e->Iex.Binop.op == Iop_F64toI32S + || e->Iex.Binop.op == Iop_F64toI64S) { + Int szD = e->Iex.Binop.op==Iop_F64toI32S ? 4 : 8; HReg rf = iselDblExpr(env, e->Iex.Binop.arg2); HReg dst = newVRegI(env); set_SSE_rounding_mode( env, e->Iex.Binop.arg1 ); @@ -1360,59 +1377,55 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) /* --------- UNARY OP --------- */ case Iex_Unop: { - /* 32Uto64(8Uto32(expr8)) */ - DEFINE_PATTERN(p_8Uto64, - unop(Iop_32Uto64, unop(Iop_8Uto32, bind(0)) ) ); - if (matchIRExpr(&mi,p_8Uto64,e)) { - IRExpr* expr8 = mi.bindee[0]; - HReg dst = newVRegI(env); - HReg src = iselIntExpr_R(env, expr8); - addInstr(env, mk_iMOVsd_RR(src,dst) ); - addInstr(env, AMD64Instr_Sh64(Ash_SHL, 56, dst)); - addInstr(env, AMD64Instr_Sh64(Ash_SHR, 56, dst)); - return dst; - } /* 1Uto8(64to1(expr64)) */ - DEFINE_PATTERN( p_1Uto8_64to1, - unop(Iop_1Uto8, unop(Iop_64to1, bind(0))) ); - if (matchIRExpr(&mi,p_1Uto8_64to1,e)) { - IRExpr* expr64 = mi.bindee[0]; - HReg dst = newVRegI(env); - HReg src = iselIntExpr_R(env, expr64); - addInstr(env, mk_iMOVsd_RR(src,dst) ); - addInstr(env, AMD64Instr_Alu64R(Aalu_AND, - AMD64RMI_Imm(1), dst)); - return dst; + { + DEFINE_PATTERN( p_1Uto8_64to1, + unop(Iop_1Uto8, unop(Iop_64to1, bind(0))) ); + if (matchIRExpr(&mi,p_1Uto8_64to1,e)) { + IRExpr* expr64 = mi.bindee[0]; + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, expr64); + addInstr(env, mk_iMOVsd_RR(src,dst) ); + addInstr(env, AMD64Instr_Alu64R(Aalu_AND, + AMD64RMI_Imm(1), dst)); + return dst; + } } -//.. /* 16Uto32(LDle(expr32)) */ -//.. { -//.. DECLARE_PATTERN(p_LDle16_then_16Uto32); -//.. DEFINE_PATTERN(p_LDle16_then_16Uto32, -//.. unop(Iop_16Uto32,IRExpr_LDle(Ity_I16,bind(0))) ); -//.. if (matchIRExpr(&mi,p_LDle16_then_16Uto32,e)) { -//.. HReg dst = newVRegI(env); -//.. X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); -//.. addInstr(env, X86Instr_LoadEX(2,False,amode,dst)); -//.. return dst; -//.. } -//.. } + /* 8Uto64(LDle(expr64)) */ + { + DEFINE_PATTERN(p_LDle8_then_8Uto64, + unop(Iop_8Uto64, + IRExpr_Load(Iend_LE,Ity_I8,bind(0))) ); + if (matchIRExpr(&mi,p_LDle8_then_8Uto64,e)) { + HReg dst = newVRegI(env); + AMD64AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); + addInstr(env, AMD64Instr_LoadEX(1,False,amode,dst)); + return dst; + } + } - switch (e->Iex.Unop.op) { - case Iop_32Uto64: { + /* 16Uto64(LDle(expr64)) */ + { + DEFINE_PATTERN(p_LDle16_then_16Uto64, + unop(Iop_16Uto64, + IRExpr_Load(Iend_LE,Ity_I16,bind(0))) ); + if (matchIRExpr(&mi,p_LDle16_then_16Uto64,e)) { HReg dst = newVRegI(env); - HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); - addInstr(env, AMD64Instr_MovZLQ(src,dst) ); + AMD64AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); + addInstr(env, AMD64Instr_LoadEX(2,False,amode,dst)); return dst; } + } + + switch (e->Iex.Unop.op) { + case Iop_32Uto64: case Iop_32Sto64: { HReg dst = newVRegI(env); HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); - UInt amt = 32; - addInstr(env, mk_iMOVsd_RR(src,dst) ); - addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, dst)); - addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, dst)); + addInstr(env, AMD64Instr_MovxLQ(e->Iex.Unop.op == Iop_32Sto64, + src, dst) ); return dst; } case Iop_128HIto64: { @@ -1475,13 +1488,14 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) //.. iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); //.. return rLo; /* similar stupid comment to the above ... */ //.. } -//.. case Iop_16HIto8: + case Iop_16HIto8: case Iop_32HIto16: case Iop_64HIto32: { HReg dst = newVRegI(env); HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); Int shift = 0; switch (e->Iex.Unop.op) { + case Iop_16HIto8: shift = 8; break; case Iop_32HIto16: shift = 16; break; case Iop_64HIto32: shift = 32; break; default: vassert(0); @@ -1548,7 +1562,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) HReg dst = newVRegI(env); HReg pre = iselIntExpr_R(env, e->Iex.Unop.arg); addInstr(env, mk_iMOVsd_RR(pre,src)); - addInstr(env, AMD64Instr_MovZLQ(src,src)); + addInstr(env, AMD64Instr_MovxLQ(False, src, src)); addInstr(env, mk_iMOVsd_RR(src,dst)); addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst)); addInstr(env, AMD64Instr_Alu64R(Aalu_OR, @@ -1723,7 +1737,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) if (e->Iex.CCall.retty == Ity_I64) addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst)); else - addInstr(env, AMD64Instr_MovZLQ(hregAMD64_RAX(), dst)); + addInstr(env, AMD64Instr_MovxLQ(False, hregAMD64_RAX(), dst)); return dst; } @@ -1773,11 +1787,11 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) /* one arg -> top of x87 stack */ addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg2, m8_rsp)); - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8)); /* other arg -> top of x87 stack */ addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg1, m8_rsp)); - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8)); switch (e->Iex.Triop.op) { case Iop_PRemC3210F64: @@ -1963,7 +1977,7 @@ static AMD64RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, IRExpr* e ) /* special case: 64-bit load from memory */ if (e->tag == Iex_Load && ty == Ity_I64 - && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + && e->Iex.Load.end == Iend_LE) { AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr); return AMD64RMI_Mem(am); } @@ -2161,7 +2175,7 @@ static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); HReg tmp = newVRegI(env); AMD64RMI* rmi2 = AMD64RMI_Imm(0); - addInstr(env, AMD64Instr_MovZLQ(r1,tmp)); + addInstr(env, AMD64Instr_MovxLQ(False, r1, tmp)); addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,rmi2,tmp)); return Acc_NZ; } @@ -2749,7 +2763,7 @@ static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) return lookupIRTemp(env, e->Iex.RdTmp.tmp); } - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { AMD64AMode* am; HReg res = newVRegV(env); vassert(e->Iex.Load.ty == Ity_F32); @@ -2791,6 +2805,30 @@ static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } + if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_RoundF32toInt) { + AMD64AMode* m8_rsp = AMD64AMode_IR(-8, hregAMD64_RSP()); + HReg arg = iselFltExpr(env, e->Iex.Binop.arg2); + HReg dst = newVRegV(env); + + /* rf now holds the value to be rounded. The first thing to do + is set the FPU's rounding mode accordingly. */ + + /* Set host x87 rounding mode */ + set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); + + addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, arg, m8_rsp)); + addInstr(env, AMD64Instr_A87Free(1)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 4)); + addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 4)); + addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 4, dst, m8_rsp)); + + /* Restore default x87 rounding. */ + set_FPU_rounding_default( env ); + + return dst; + } + ppIRExpr(e); vpanic("iselFltExpr_wrk"); } @@ -2873,7 +2911,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) return res; } - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { AMD64AMode* am; HReg res = newVRegV(env); vassert(e->Iex.Load.ty == Ity_F64); @@ -2934,9 +2972,9 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp)); addInstr(env, AMD64Instr_A87Free(1)); - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8)); addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND)); - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8)); addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp)); /* Restore default x87 rounding. */ @@ -2965,12 +3003,12 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) /* one arg -> top of x87 stack */ addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, arg2first ? arg2 : arg1, m8_rsp)); - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8)); /* other arg -> top of x87 stack */ addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, arg2first ? arg1 : arg2, m8_rsp)); - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8)); /* do it */ /* XXXROUNDINGFIXME */ @@ -2999,12 +3037,12 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) } /* save result */ - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8)); addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp)); return dst; } - if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_I64toF64) { + if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_I64StoF64) { HReg dst = newVRegV(env); HReg src = iselIntExpr_R(env, e->Iex.Binop.arg2); set_SSE_rounding_mode( env, e->Iex.Binop.arg1 ); @@ -3013,7 +3051,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } - if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_I32toF64) { + if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_I32StoF64) { HReg dst = newVRegV(env); HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); set_SSE_rounding_default( env ); @@ -3064,15 +3102,15 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) Int nNeeded = e->Iex.Binop.op==Iop_TanF64 ? 2 : 1; addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp)); addInstr(env, AMD64Instr_A87Free(nNeeded)); - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8)); /* XXXROUNDINGFIXME */ /* set roundingmode here */ addInstr(env, AMD64Instr_A87FpOp(fpop)); if (e->Iex.Binop.op==Iop_TanF64) { /* get rid of the extra 1.0 that fptan pushes */ - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8)); } - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/)); + addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8)); addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp)); return dst; } @@ -3156,7 +3194,8 @@ static HReg iselVecExpr ( ISelEnv* env, IRExpr* e ) /* DO NOT CALL THIS DIRECTLY */ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) { - Bool arg1isEReg = False; + HWord fn = 0; /* address of helper fn, if required */ + Bool arg1isEReg = False; AMD64SseOp op = Asse_INVALID; IRType ty = typeOfIRExpr(env->type_env,e); vassert(e); @@ -3178,7 +3217,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { HReg dst = newVRegV(env); AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr); addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, am )); @@ -3188,35 +3227,28 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) if (e->tag == Iex_Const) { HReg dst = newVRegV(env); vassert(e->Iex.Const.con->tag == Ico_V128); - if (e->Iex.Const.con->Ico.V128 == 0x0000) { - dst = generate_zeroes_V128(env); - return dst; - } else - if (e->Iex.Const.con->Ico.V128 == 0x00FF) { - AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP()); - /* Both of these literals are sign-extended to 64 bits. */ - addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0))); - addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0xFFFFFFFF))); - addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 )); - add_to_rsp(env, 16); - return dst; - } else - if (e->Iex.Const.con->Ico.V128 == 0x000F) { - HReg tmp = newVRegI(env); - AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP()); - addInstr(env, AMD64Instr_Imm64(0xFFFFFFFFULL, tmp)); - addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0))); - addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(tmp))); - addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 )); - add_to_rsp(env, 16); - return dst; - } else { - goto vec_fail; -# if 0 - addInstr(env, X86Instr_SseConst(e->Iex.Const.con->Ico.V128, dst)); - return dst; -# endif + switch (e->Iex.Const.con->Ico.V128) { + case 0x0000: + dst = generate_zeroes_V128(env); + break; + case 0xFFFF: + dst = generate_ones_V128(env); + break; + default: { + AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP()); + /* do push_uimm64 twice, first time for the high-order half. */ + push_uimm64(env, bitmask8_to_bytemask64( + (e->Iex.Const.con->Ico.V128 >> 8) & 0xFF + )); + push_uimm64(env, bitmask8_to_bytemask64( + (e->Iex.Const.con->Ico.V128 >> 0) & 0xFF + )); + addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 )); + add_to_rsp(env, 16); + break; + } } + return dst; } if (e->tag == Iex_Unop) { @@ -3560,6 +3592,73 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } + case Iop_Mul32x4: fn = (HWord)h_generic_calc_Mul32x4; + goto do_SseAssistedBinary; + case Iop_Max32Sx4: fn = (HWord)h_generic_calc_Max32Sx4; + goto do_SseAssistedBinary; + case Iop_Min32Sx4: fn = (HWord)h_generic_calc_Min32Sx4; + goto do_SseAssistedBinary; + case Iop_Max32Ux4: fn = (HWord)h_generic_calc_Max32Ux4; + goto do_SseAssistedBinary; + case Iop_Min32Ux4: fn = (HWord)h_generic_calc_Min32Ux4; + goto do_SseAssistedBinary; + case Iop_Max16Ux8: fn = (HWord)h_generic_calc_Max16Ux8; + goto do_SseAssistedBinary; + case Iop_Min16Ux8: fn = (HWord)h_generic_calc_Min16Ux8; + goto do_SseAssistedBinary; + case Iop_Max8Sx16: fn = (HWord)h_generic_calc_Max8Sx16; + goto do_SseAssistedBinary; + case Iop_Min8Sx16: fn = (HWord)h_generic_calc_Min8Sx16; + goto do_SseAssistedBinary; + case Iop_CmpGT64Sx2: fn = (HWord)h_generic_calc_CmpGT64Sx2; + goto do_SseAssistedBinary; + do_SseAssistedBinary: { + /* RRRufff! RRRufff code is what we're generating here. Oh + well. */ + vassert(fn != 0); + HReg dst = newVRegV(env); + HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); + HReg argR = iselVecExpr(env, e->Iex.Binop.arg2); + HReg argp = newVRegI(env); + /* subq $112, %rsp -- make a space*/ + sub_from_rsp(env, 112); + /* leaq 48(%rsp), %r_argp -- point into it */ + addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, hregAMD64_RSP()), + argp)); + /* andq $-16, %r_argp -- 16-align the pointer */ + addInstr(env, AMD64Instr_Alu64R(Aalu_AND, + AMD64RMI_Imm( ~(UInt)15 ), + argp)); + /* Prepare 3 arg regs: + leaq 0(%r_argp), %rdi + leaq 16(%r_argp), %rsi + leaq 32(%r_argp), %rdx + */ + addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, argp), + hregAMD64_RDI())); + addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(16, argp), + hregAMD64_RSI())); + addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(32, argp), + hregAMD64_RDX())); + /* Store the two args, at (%rsi) and (%rdx): + movupd %argL, 0(%rsi) + movupd %argR, 0(%rdx) + */ + addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argL, + AMD64AMode_IR(0, hregAMD64_RSI()))); + addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argR, + AMD64AMode_IR(0, hregAMD64_RDX()))); + /* call the helper */ + addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 )); + /* fetch the result from memory, using %r_argp, which the + register allocator will keep alive across the call. */ + addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dst, + AMD64AMode_IR(0, argp))); + /* and finally, clear the space */ + add_to_rsp(env, 112); + return dst; + } + default: break; } /* switch (e->Iex.Binop.op) */ @@ -3576,7 +3675,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } - vec_fail: + //vec_fail: vex_printf("iselVecExpr (amd64, subarch = %s): can't reduce\n", LibVEX_ppVexHwCaps(VexArchAMD64, env->hwcaps)); ppIRExpr(e); @@ -3603,9 +3702,8 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr); IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); IREndness end = stmt->Ist.Store.end; - IRTemp resSC = stmt->Ist.Store.resSC; - if (tya != Ity_I64 || end != Iend_LE || resSC != IRTemp_INVALID) + if (tya != Ity_I64 || end != Iend_LE) goto stmt_fail; if (tyd == Ity_I64) { @@ -3976,8 +4074,10 @@ HInstrArray* iselSB_AMD64 ( IRSB* bb, VexArch arch_host, /* sanity ... */ vassert(arch_host == VexArchAMD64); - vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_AMD64_SSE3 - |VEX_HWCAPS_AMD64_CX16))); + vassert(0 == (hwcaps_host + & ~(VEX_HWCAPS_AMD64_SSE3 + | VEX_HWCAPS_AMD64_CX16 + | VEX_HWCAPS_AMD64_LZCNT))); /* Make up an initial environment to use. */ env = LibVEX_Alloc(sizeof(ISelEnv)); diff --git a/VEX/priv/host_arm_defs.c b/VEX/priv/host_arm_defs.c index 2735b27..122a9f9 100644 --- a/VEX/priv/host_arm_defs.c +++ b/VEX/priv/host_arm_defs.c @@ -1,47 +1,36 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_arm_defs.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_arm_defs.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + NEON support is + Copyright (C) 2010-2010 Samsung Electronics + contributed by Dmitry Zhurikhin + and Kirill Batuzov - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. - - Neither the names of the U.S. Department of Energy nor the - University of California nor the names of its contributors may be - used to endorse or promote products derived from this software - without prior written permission. + The GNU General Public License is contained in the file COPYING. */ #include "libvex_basictypes.h" @@ -52,6 +41,7 @@ #include "host_generic_regs.h" #include "host_arm_defs.h" +UInt arm_hwcaps = 0; /* --------- Registers. --------- */ @@ -60,15 +50,8 @@ There are 16 general purpose regs. */ - -/* --------- Registers. --------- */ - void ppHRegARM ( HReg reg ) { Int r; - static HChar* ireg32_names[16] - = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", - "r9", "r10", "r11", "r12", "r13", "r14", "r15" }; - /* Be generic for all virtual regs. */ if (hregIsVirtual(reg)) { ppHReg(reg); @@ -79,49 +62,129 @@ void ppHRegARM ( HReg reg ) { case HRcInt32: r = hregNumber(reg); vassert(r >= 0 && r < 16); - vex_printf("%s", ireg32_names[r]); + vex_printf("r%d", r); + return; + case HRcFlt64: + r = hregNumber(reg); + vassert(r >= 0 && r < 32); + vex_printf("d%d", r); + return; + case HRcFlt32: + r = hregNumber(reg); + vassert(r >= 0 && r < 32); + vex_printf("s%d", r); + return; + case HRcVec128: + r = hregNumber(reg); + vassert(r >= 0 && r < 16); + vex_printf("q%d", r); return; default: vpanic("ppHRegARM"); } } -HReg hregARM_R0 ( void ) { return mkHReg(0, HRcInt32, False); } -HReg hregARM_R1 ( void ) { return mkHReg(1, HRcInt32, False); } -HReg hregARM_R2 ( void ) { return mkHReg(2, HRcInt32, False); } -HReg hregARM_R3 ( void ) { return mkHReg(3, HRcInt32, False); } -HReg hregARM_R4 ( void ) { return mkHReg(4, HRcInt32, False); } -HReg hregARM_R5 ( void ) { return mkHReg(5, HRcInt32, False); } -HReg hregARM_R6 ( void ) { return mkHReg(6, HRcInt32, False); } -HReg hregARM_R7 ( void ) { return mkHReg(7, HRcInt32, False); } -HReg hregARM_R8 ( void ) { return mkHReg(8, HRcInt32, False); } -HReg hregARM_R9 ( void ) { return mkHReg(9, HRcInt32, False); } +HReg hregARM_R0 ( void ) { return mkHReg(0, HRcInt32, False); } +HReg hregARM_R1 ( void ) { return mkHReg(1, HRcInt32, False); } +HReg hregARM_R2 ( void ) { return mkHReg(2, HRcInt32, False); } +HReg hregARM_R3 ( void ) { return mkHReg(3, HRcInt32, False); } +HReg hregARM_R4 ( void ) { return mkHReg(4, HRcInt32, False); } +HReg hregARM_R5 ( void ) { return mkHReg(5, HRcInt32, False); } +HReg hregARM_R6 ( void ) { return mkHReg(6, HRcInt32, False); } +HReg hregARM_R7 ( void ) { return mkHReg(7, HRcInt32, False); } +HReg hregARM_R8 ( void ) { return mkHReg(8, HRcInt32, False); } +HReg hregARM_R9 ( void ) { return mkHReg(9, HRcInt32, False); } HReg hregARM_R10 ( void ) { return mkHReg(10, HRcInt32, False); } HReg hregARM_R11 ( void ) { return mkHReg(11, HRcInt32, False); } HReg hregARM_R12 ( void ) { return mkHReg(12, HRcInt32, False); } HReg hregARM_R13 ( void ) { return mkHReg(13, HRcInt32, False); } HReg hregARM_R14 ( void ) { return mkHReg(14, HRcInt32, False); } HReg hregARM_R15 ( void ) { return mkHReg(15, HRcInt32, False); } +HReg hregARM_D8 ( void ) { return mkHReg(8, HRcFlt64, False); } +HReg hregARM_D9 ( void ) { return mkHReg(9, HRcFlt64, False); } +HReg hregARM_D10 ( void ) { return mkHReg(10, HRcFlt64, False); } +HReg hregARM_D11 ( void ) { return mkHReg(11, HRcFlt64, False); } +HReg hregARM_D12 ( void ) { return mkHReg(12, HRcFlt64, False); } +HReg hregARM_S26 ( void ) { return mkHReg(26, HRcFlt32, False); } +HReg hregARM_S27 ( void ) { return mkHReg(27, HRcFlt32, False); } +HReg hregARM_S28 ( void ) { return mkHReg(28, HRcFlt32, False); } +HReg hregARM_S29 ( void ) { return mkHReg(29, HRcFlt32, False); } +HReg hregARM_S30 ( void ) { return mkHReg(30, HRcFlt32, False); } +HReg hregARM_Q8 ( void ) { return mkHReg(8, HRcVec128, False); } +HReg hregARM_Q9 ( void ) { return mkHReg(9, HRcVec128, False); } +HReg hregARM_Q10 ( void ) { return mkHReg(10, HRcVec128, False); } +HReg hregARM_Q11 ( void ) { return mkHReg(11, HRcVec128, False); } +HReg hregARM_Q12 ( void ) { return mkHReg(12, HRcVec128, False); } +HReg hregARM_Q13 ( void ) { return mkHReg(13, HRcVec128, False); } +HReg hregARM_Q14 ( void ) { return mkHReg(14, HRcVec128, False); } +HReg hregARM_Q15 ( void ) { return mkHReg(15, HRcVec128, False); } -void getAllocableRegs_ARM ( Int* nregs, HReg** arr ) { - *nregs = 20; +void getAllocableRegs_ARM ( Int* nregs, HReg** arr ) +{ + Int i = 0; + *nregs = 26; *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); - (*arr)[0] = hregARM_R0(); - (*arr)[1] = hregARM_R1(); - (*arr)[2] = hregARM_R2(); - (*arr)[3] = hregARM_R3(); - (*arr)[4] = hregARM_R4(); - (*arr)[5] = hregARM_R5(); - (*arr)[6] = hregARM_R6(); - (*arr)[7] = hregARM_R7(); - (*arr)[8] = hregARM_R8(); - (*arr)[9] = hregARM_R9(); - (*arr)[10] = hregARM_R10(); - (*arr)[11] = hregARM_R11(); - (*arr)[12] = hregARM_R12(); - (*arr)[13] = hregARM_R13(); - (*arr)[14] = hregARM_R14(); - (*arr)[15] = hregARM_R15(); + // callee saves ones are listed first, since we prefer them + // if they're available + (*arr)[i++] = hregARM_R4(); + (*arr)[i++] = hregARM_R5(); + (*arr)[i++] = hregARM_R6(); + (*arr)[i++] = hregARM_R7(); + (*arr)[i++] = hregARM_R10(); + (*arr)[i++] = hregARM_R11(); + // otherwise we'll have to slum it out with caller-saves ones + (*arr)[i++] = hregARM_R0(); + (*arr)[i++] = hregARM_R1(); + (*arr)[i++] = hregARM_R2(); + (*arr)[i++] = hregARM_R3(); + (*arr)[i++] = hregARM_R9(); + // FP hreegisters. Note: these are all callee-save. Yay! + // Hence we don't need to mention them as trashed in + // getHRegUsage for ARMInstr_Call. + (*arr)[i++] = hregARM_D8(); + (*arr)[i++] = hregARM_D9(); + (*arr)[i++] = hregARM_D10(); + (*arr)[i++] = hregARM_D11(); + (*arr)[i++] = hregARM_D12(); + (*arr)[i++] = hregARM_S26(); + (*arr)[i++] = hregARM_S27(); + (*arr)[i++] = hregARM_S28(); + (*arr)[i++] = hregARM_S29(); + (*arr)[i++] = hregARM_S30(); + + (*arr)[i++] = hregARM_Q8(); + (*arr)[i++] = hregARM_Q9(); + (*arr)[i++] = hregARM_Q10(); + (*arr)[i++] = hregARM_Q11(); + (*arr)[i++] = hregARM_Q12(); + + //(*arr)[i++] = hregARM_Q13(); + //(*arr)[i++] = hregARM_Q14(); + //(*arr)[i++] = hregARM_Q15(); + + // unavail: r8 as GSP + // r12 is used as a spill/reload temporary + // r13 as SP + // r14 as LR + // r15 as PC + // + // All in all, we have 11 allocatable integer registers: + // 0 1 2 3 4 5 6 7 9 10 11, with r8 dedicated as GSP + // and r12 dedicated as a spill temporary. + // 13 14 and 15 are not under the allocator's control. + // + // Hence for the allocatable registers we have: + // + // callee-saved: 4 5 6 7 (8) 9 10 11 + // caller-saved: 0 1 2 3 + // Note 9 is ambiguous: the base EABI does not give an e/r-saved + // designation for it, but the Linux instantiation of the ABI + // specifies it as callee-saved. + // + // If the set of available registers changes or if the e/r status + // changes, be sure to re-check/sync the definition of + // getHRegUsage for ARMInstr_Call too. + vassert(i == *nregs); } @@ -130,578 +193,2270 @@ void getAllocableRegs_ARM ( Int* nregs, HReg** arr ) { HChar* showARMCondCode ( ARMCondCode cond ) { switch (cond) { - case ARMccEQ: return "eq"; - case ARMccNE: return "ne"; - case ARMccHS: return "hs"; - case ARMccLO: return "lo"; - case ARMccMI: return "mi"; - case ARMccPL: return "pl"; - case ARMccVS: return "vs"; - case ARMccVC: return "vc"; - case ARMccHI: return "hi"; - case ARMccLS: return "ls"; - case ARMccGE: return "ge"; - case ARMccLT: return "lt"; - case ARMccGT: return "gt"; - case ARMccLE: return "le"; - case ARMccAL: return "al"; // default - case ARMccNV: return "nv"; + case ARMcc_EQ: return "eq"; + case ARMcc_NE: return "ne"; + case ARMcc_HS: return "hs"; + case ARMcc_LO: return "lo"; + case ARMcc_MI: return "mi"; + case ARMcc_PL: return "pl"; + case ARMcc_VS: return "vs"; + case ARMcc_VC: return "vc"; + case ARMcc_HI: return "hi"; + case ARMcc_LS: return "ls"; + case ARMcc_GE: return "ge"; + case ARMcc_LT: return "lt"; + case ARMcc_GT: return "gt"; + case ARMcc_LE: return "le"; + case ARMcc_AL: return "al"; // default + case ARMcc_NV: return "nv"; default: vpanic("showARMCondCode"); } } +/* --------- Mem AModes: Addressing Mode 1 --------- */ - -/* --------- ARMAMode1: memory address expressions. --------- */ - -ARMAMode1* ARMAMode1_I12A ( ARMImm12A imm ) { - ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); - am->tag = ARMam1_I12A; - am->ARMam1.I12A.imm = imm; - return am; +ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 ) { + ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); + am->tag = ARMam1_RI; + am->ARMam1.RI.reg = reg; + am->ARMam1.RI.simm13 = simm13; + vassert(-4095 <= simm13 && simm13 <= 4095); + return am; } -ARMAMode1* ARMAMode1_ShlI ( HReg Rm, ARMImm5 imm ) { - ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); - am->tag = ARMam1_ShlI; - am->ARMam1.ShlI.Rm = Rm; - am->ARMam1.ShlI.imm = imm; - return am; +ARMAMode1* ARMAMode1_RRS ( HReg base, HReg index, UInt shift ) { + ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); + am->tag = ARMam1_RRS; + am->ARMam1.RRS.base = base; + am->ARMam1.RRS.index = index; + am->ARMam1.RRS.shift = shift; + vassert(0 <= shift && shift <= 3); + return am; } -ARMAMode1* ARMAMode1_ShrI ( HReg Rm, ARMImm5 imm ) { - ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); - am->tag = ARMam1_ShrI; - am->ARMam1.ShrI.Rm = Rm; - am->ARMam1.ShrI.imm = imm; - return am; + +void ppARMAMode1 ( ARMAMode1* am ) { + switch (am->tag) { + case ARMam1_RI: + vex_printf("%d(", am->ARMam1.RI.simm13); + ppHRegARM(am->ARMam1.RI.reg); + vex_printf(")"); + break; + case ARMam1_RRS: + vex_printf("("); + ppHRegARM(am->ARMam1.RRS.base); + vex_printf(","); + ppHRegARM(am->ARMam1.RRS.index); + vex_printf(",%u)", am->ARMam1.RRS.shift); + break; + default: + vassert(0); + } } -ARMAMode1* ARMAMode1_SarI ( HReg Rm, ARMImm5 imm ) { - ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); - am->tag = ARMam1_SarI; - am->ARMam1.SarI.Rm = Rm; - am->ARMam1.SarI.imm = imm; - return am; + +static void addRegUsage_ARMAMode1 ( HRegUsage* u, ARMAMode1* am ) { + switch (am->tag) { + case ARMam1_RI: + addHRegUse(u, HRmRead, am->ARMam1.RI.reg); + return; + case ARMam1_RRS: + // addHRegUse(u, HRmRead, am->ARMam1.RRS.base); + // addHRegUse(u, HRmRead, am->ARMam1.RRS.index); + // return; + default: + vpanic("addRegUsage_ARMAmode1"); + } } -ARMAMode1* ARMAMode1_ShlR ( HReg Rm, HReg Rs ) { - ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); - am->tag = ARMam1_ShlR; - am->ARMam1.ShlR.Rm = Rm; - am->ARMam1.ShlR.Rs = Rs; - return am; + +static void mapRegs_ARMAMode1 ( HRegRemap* m, ARMAMode1* am ) { + switch (am->tag) { + case ARMam1_RI: + am->ARMam1.RI.reg = lookupHRegRemap(m, am->ARMam1.RI.reg); + return; + case ARMam1_RRS: + //am->ARMam1.RR.base =lookupHRegRemap(m, am->ARMam1.RR.base); + //am->ARMam1.RR.index = lookupHRegRemap(m, am->ARMam1.RR.index); + //return; + default: + vpanic("mapRegs_ARMAmode1"); + } } -ARMAMode1* ARMAMode1_ShrR ( HReg Rm, HReg Rs ) { - ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); - am->tag = ARMam1_ShrR; - am->ARMam1.ShrR.Rm = Rm; - am->ARMam1.ShrR.Rs = Rs; - return am; + + +/* --------- Mem AModes: Addressing Mode 2 --------- */ + +ARMAMode2* ARMAMode2_RI ( HReg reg, Int simm9 ) { + ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); + am->tag = ARMam2_RI; + am->ARMam2.RI.reg = reg; + am->ARMam2.RI.simm9 = simm9; + vassert(-255 <= simm9 && simm9 <= 255); + return am; } -ARMAMode1* ARMAMode1_SarR ( HReg Rm, HReg Rs ) { - ARMAMode1* am = LibVEX_Alloc(sizeof(ARMAMode1)); - am->tag = ARMam1_SarR; - am->ARMam1.SarR.Rm = Rm; - am->ARMam1.SarR.Rs = Rs; - return am; +ARMAMode2* ARMAMode2_RR ( HReg base, HReg index ) { + ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); + am->tag = ARMam2_RR; + am->ARMam2.RR.base = base; + am->ARMam2.RR.index = index; + return am; } -ARMAMode1* dopyARMAMode1 ( ARMAMode1* am ) { +void ppARMAMode2 ( ARMAMode2* am ) { switch (am->tag) { - case ARMam1_I12A: - return ARMAMode1_I12A( am->ARMam1.I12A.imm ); - case ARMam1_ShlI: - return ARMAMode1_ShlI( am->ARMam1.ShlI.Rm, am->ARMam1.ShlI.imm ); - case ARMam1_ShrI: - return ARMAMode1_ShrI( am->ARMam1.ShrI.Rm, am->ARMam1.ShrI.imm ); - case ARMam1_SarI: - return ARMAMode1_SarI( am->ARMam1.SarI.Rm, am->ARMam1.SarI.imm ); - case ARMam1_ShlR: - return ARMAMode1_ShlR( am->ARMam1.ShlR.Rm, am->ARMam1.ShlR.Rs ); - case ARMam1_ShrR: - return ARMAMode1_ShrR( am->ARMam1.ShrR.Rm, am->ARMam1.ShrR.Rs ); - case ARMam1_SarR: - return ARMAMode1_SarR( am->ARMam1.SarR.Rm, am->ARMam1.SarR.Rs ); - default: - vpanic("dopyARMAMode1"); + case ARMam2_RI: + vex_printf("%d(", am->ARMam2.RI.simm9); + ppHRegARM(am->ARMam2.RI.reg); + vex_printf(")"); + break; + case ARMam2_RR: + vex_printf("("); + ppHRegARM(am->ARMam2.RR.base); + vex_printf(","); + ppHRegARM(am->ARMam2.RR.index); + vex_printf(")"); + break; + default: + vassert(0); } } -void ppARMAMode1 ( ARMAMode1* am ) { +static void addRegUsage_ARMAMode2 ( HRegUsage* u, ARMAMode2* am ) { switch (am->tag) { - case ARMam1_I12A: - case ARMam1_ShlI: - case ARMam1_ShrI: - case ARMam1_SarI: - case ARMam1_ShlR: - case ARMam1_ShrR: - case ARMam1_SarR: - vex_printf("ppARMAMode1: Not implemented"); - break; - default: - vpanic("ppARMAMode1"); + case ARMam2_RI: + addHRegUse(u, HRmRead, am->ARMam2.RI.reg); + return; + case ARMam2_RR: + // addHRegUse(u, HRmRead, am->ARMam2.RR.base); + // addHRegUse(u, HRmRead, am->ARMam2.RR.index); + // return; + default: + vpanic("addRegUsage_ARMAmode2"); } } -/* -static void addRegUsage_ARMAMode1 ( HRegUsage* u, ARMAMode1* am ) { -static void mapRegs_ARMAMode1 ( HRegRemap* m, ARMAMode1* am ) { -*/ +static void mapRegs_ARMAMode2 ( HRegRemap* m, ARMAMode2* am ) { + switch (am->tag) { + case ARMam2_RI: + am->ARMam2.RI.reg = lookupHRegRemap(m, am->ARMam2.RI.reg); + return; + case ARMam2_RR: + //am->ARMam2.RR.base =lookupHRegRemap(m, am->ARMam2.RR.base); + //am->ARMam2.RR.index = lookupHRegRemap(m, am->ARMam2.RR.index); + //return; + default: + vpanic("mapRegs_ARMAmode2"); + } +} -/* ------ ARMAMode1_I12A Helper function ------ - Given imm32, find immed_8, rotate_imm. - ARM ARM A5-6: imm32 = immed_8 ROR (rotate_imm * 2) -*/ -Bool mk_ARMImm12A ( UInt imm32, ARMImm12A* imm12a ) { -// UInt imm32_orig = imm32; - UInt shr=0, rot=0; - imm12a->imm = 0; - imm12a->rot = 0; - - // Easiest case: no shift needed - if (imm32 > 0xFF) { - // Next easiest: just a shift to the right needed - while ((imm32 & 1) == 0) { imm32 = imm32 >> 1; shr++; } - rot = 32 - shr; - - if (imm32 > 0xFF) { - // Hardest: Need to rol (some minimum amount) - // valid byte could be split over first and last bytes... - - // ROL 7 (worst case for still valid imm32): - imm32 = (imm32 << 7) | (imm32 << (32-7)); - // ShR (reverse rol) if went too far: - while ((imm32 & 1) == 0) { imm32 = imm32 >> 1; shr++; } - rot = 7 - shr; // if valid imm32, shr < 7 - - if (imm32 > 0xFF) { // Can't represent this value -// vex_printf("Error: Can't represent imm32: 0x%x", imm32_orig); - return False; - } - } - } - // Valid imm32 so far... - - if (rot & 1) { - rot--; - imm32 = imm32 << 1; - if (imm32 > 0xFF) { - // Can't represent this value (can only shift even n) -// vex_printf("Error: Can't represent imm32: 0x%x\n", imm32_orig); - return False; - } - } +/* --------- Mem AModes: Addressing Mode VFP --------- */ - imm12a->imm = imm32; - imm12a->rot = rot / 2; - - vassert((imm12a->imm & 0xFF) == imm12a->imm); - vassert((imm12a->rot & 0xF ) == imm12a->rot); - return True; +ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 ) { + ARMAModeV* am = LibVEX_Alloc(sizeof(ARMAModeV)); + vassert(simm11 >= -1020 && simm11 <= 1020); + vassert(0 == (simm11 & 3)); + am->reg = reg; + am->simm11 = simm11; + return am; } +void ppARMAModeV ( ARMAModeV* am ) { + vex_printf("%d(", am->simm11); + ppHRegARM(am->reg); + vex_printf(")"); +} +static void addRegUsage_ARMAModeV ( HRegUsage* u, ARMAModeV* am ) { + addHRegUse(u, HRmRead, am->reg); +} +static void mapRegs_ARMAModeV ( HRegRemap* m, ARMAModeV* am ) { + am->reg = lookupHRegRemap(m, am->reg); +} -/* --------- ARMAMode2: memory address expressions. --------- */ +/* --------- Mem AModes: Addressing Mode Neon ------- */ -ARMAMode2* ARMAMode2_RI ( HReg Rn, ARMImm12 imm ) { - ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); - am->tag = ARMam2_RI; - am->ARMam2.RI.Rn = Rn; - am->ARMam2.RI.imm = imm; - return am; +ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { + ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN)); + am->tag = ARMamN_RR; + am->ARMamN.RR.rN = rN; + am->ARMamN.RR.rM = rM; + return am; } -ARMAMode2* ARMAMode2_RR ( HReg Rn, HReg Rm ) { - ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); - am->tag = ARMam2_RR; - am->ARMam2.RR.Rn = Rn; - am->ARMam2.RR.Rm = Rm; - return am; + +ARMAModeN *mkARMAModeN_R ( HReg rN ) { + ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN)); + am->tag = ARMamN_R; + am->ARMamN.R.rN = rN; + return am; } -ARMAMode2* ARMAMode2_RRS ( HReg Rn, HReg Rm, ARMImm5 shift ) { - ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); - am->tag = ARMam2_RRS; - am->ARMam2.RRS.Rn = Rn; - am->ARMam2.RRS.Rm = Rm; - am->ARMam2.RRS.shift = shift; - return am; + +static void addRegUsage_ARMAModeN ( HRegUsage* u, ARMAModeN* am ) { + if (am->tag == ARMamN_R) { + addHRegUse(u, HRmRead, am->ARMamN.R.rN); + } else { + addHRegUse(u, HRmRead, am->ARMamN.RR.rN); + addHRegUse(u, HRmRead, am->ARMamN.RR.rM); + } } -ARMAMode2* dopyARMAMode2 ( ARMAMode2* am ) { - switch (am->tag) { - case ARMam2_RI: - return ARMAMode2_RI( am->ARMam2.RI.Rn, am->ARMam2.RI.imm ); - case ARMam2_RR: - return ARMAMode2_RR( am->ARMam2.RR.Rn, am->ARMam2.RR.Rm ); - case ARMam2_RRS: - return ARMAMode2_RRS( am->ARMam2.RRS.Rn, am->ARMam2.RRS.Rm, - am->ARMam2.RRS.shift ); - default: - vpanic("dopyARMAMode2"); +static void mapRegs_ARMAModeN ( HRegRemap* m, ARMAModeN* am ) { + if (am->tag == ARMamN_R) { + am->ARMamN.R.rN = lookupHRegRemap(m, am->ARMamN.R.rN); + } else { + am->ARMamN.RR.rN = lookupHRegRemap(m, am->ARMamN.RR.rN); + am->ARMamN.RR.rM = lookupHRegRemap(m, am->ARMamN.RR.rM); } } -void ppARMAMode2 ( ARMAMode2* am ) { - switch (am->tag) { - case ARMam2_RI: - case ARMam2_RR: - case ARMam2_RRS: - vex_printf("ppARMAMode2: Not implemented"); - break; - default: - vpanic("ppARMAMode2"); +void ppARMAModeN ( ARMAModeN* am ) { + vex_printf("["); + if (am->tag == ARMamN_R) { + ppHRegARM(am->ARMamN.R.rN); + } else { + ppHRegARM(am->ARMamN.RR.rN); + } + vex_printf("]"); + if (am->tag == ARMamN_RR) { + vex_printf(", "); + ppHRegARM(am->ARMamN.RR.rM); } } -/* -static void addRegUsage_ARMAMode2 ( HRegUsage* u, ARMAMode1* am ) { -static void mapRegs_ARMAMode2 ( HRegRemap* m, ARMAMode1* am ) { -*/ +/* --------- Reg or imm-8x4 operands --------- */ -/* --------- ARMAMode3: memory address expressions. --------- */ +static UInt ROR32 ( UInt x, UInt sh ) { + vassert(sh >= 0 && sh < 32); + if (sh == 0) + return x; + else + return (x << (32-sh)) | (x >> sh); +} -ARMAMode3* ARMAMode3_RI ( HReg Rn, ARMImm8 imm ) { - ARMAMode3* am = LibVEX_Alloc(sizeof(ARMAMode3)); - am->tag = ARMam3_RI; - am->ARMam3.RI.Rn = Rn; - am->ARMam3.RI.imm = imm; - return am; +ARMRI84* ARMRI84_I84 ( UShort imm8, UShort imm4 ) { + ARMRI84* ri84 = LibVEX_Alloc(sizeof(ARMRI84)); + ri84->tag = ARMri84_I84; + ri84->ARMri84.I84.imm8 = imm8; + ri84->ARMri84.I84.imm4 = imm4; + vassert(imm8 >= 0 && imm8 <= 255); + vassert(imm4 >= 0 && imm4 <= 15); + return ri84; } -ARMAMode3* ARMAMode3_RR ( HReg Rn, HReg Rm ) { - ARMAMode3* am = LibVEX_Alloc(sizeof(ARMAMode3)); - am->tag = ARMam3_RR; - am->ARMam3.RR.Rn = Rn; - am->ARMam3.RR.Rm = Rm; - return am; +ARMRI84* ARMRI84_R ( HReg reg ) { + ARMRI84* ri84 = LibVEX_Alloc(sizeof(ARMRI84)); + ri84->tag = ARMri84_R; + ri84->ARMri84.R.reg = reg; + return ri84; } -ARMAMode3* dopyARMAMode3 ( ARMAMode3* am ) { - switch (am->tag) { - case ARMam3_RI: - return ARMAMode3_RI( am->ARMam3.RI.Rn, am->ARMam3.RI.imm ); - case ARMam3_RR: - return ARMAMode3_RR( am->ARMam3.RR.Rn, am->ARMam3.RR.Rm ); - default: - vpanic("dopyARMAMode3"); +void ppARMRI84 ( ARMRI84* ri84 ) { + switch (ri84->tag) { + case ARMri84_I84: + vex_printf("0x%x", ROR32(ri84->ARMri84.I84.imm8, + 2 * ri84->ARMri84.I84.imm4)); + break; + case ARMri84_R: + ppHRegARM(ri84->ARMri84.R.reg); + break; + default: + vassert(0); } } -void ppARMAMode3 ( ARMAMode3* am ) { - switch (am->tag) { - case ARMam3_RI: - case ARMam3_RR: - vex_printf("ppARMAMode3: Not implemented"); - break; - default: - vpanic("ppARMAMode3"); +static void addRegUsage_ARMRI84 ( HRegUsage* u, ARMRI84* ri84 ) { + switch (ri84->tag) { + case ARMri84_I84: + return; + case ARMri84_R: + addHRegUse(u, HRmRead, ri84->ARMri84.R.reg); + return; + default: + vpanic("addRegUsage_ARMRI84"); } } -/* -static void addRegUsage_ARMAMode1 ( HRegUsage* u, ARMAMode2* am ) { -static void mapRegs_ARMAMode2 ( HRegRemap* m, ARMAMode2* am ) { -*/ +static void mapRegs_ARMRI84 ( HRegRemap* m, ARMRI84* ri84 ) { + switch (ri84->tag) { + case ARMri84_I84: + return; + case ARMri84_R: + ri84->ARMri84.R.reg = lookupHRegRemap(m, ri84->ARMri84.R.reg); + return; + default: + vpanic("mapRegs_ARMRI84"); + } +} -/* ------ Branch destination ------ */ - -ARMBranchDest* ARMBranchDest_Imm ( ARMImm24 imm24 ) { - ARMBranchDest* branch_dest = LibVEX_Alloc(sizeof(ARMBranchDest)); - branch_dest->tag = ARMbdImm; - branch_dest->ARMbd.Imm.imm24 = imm24; - return branch_dest; -} -ARMBranchDest* ARMBranchDest_Reg ( HReg reg ) { - ARMBranchDest* branch_dest = LibVEX_Alloc(sizeof(ARMBranchDest)); - branch_dest->tag = ARMbdReg; - branch_dest->ARMbd.Reg.reg = reg; - return branch_dest; -} - -void ppARMBranchDest ( ARMBranchDest* branch_dest ) { - switch (branch_dest->tag) { - case ARMbdImm: - case ARMbdReg: - vex_printf("ppARMBranchDest: Not implemented"); - break; - default: - vpanic("ppX86RM"); - } + +/* --------- Reg or imm5 operands --------- */ + +ARMRI5* ARMRI5_I5 ( UInt imm5 ) { + ARMRI5* ri5 = LibVEX_Alloc(sizeof(ARMRI5)); + ri5->tag = ARMri5_I5; + ri5->ARMri5.I5.imm5 = imm5; + vassert(imm5 > 0 && imm5 <= 31); // zero is not allowed + return ri5; +} +ARMRI5* ARMRI5_R ( HReg reg ) { + ARMRI5* ri5 = LibVEX_Alloc(sizeof(ARMRI5)); + ri5->tag = ARMri5_R; + ri5->ARMri5.R.reg = reg; + return ri5; +} + +void ppARMRI5 ( ARMRI5* ri5 ) { + switch (ri5->tag) { + case ARMri5_I5: + vex_printf("%u", ri5->ARMri5.I5.imm5); + break; + case ARMri5_R: + ppHRegARM(ri5->ARMri5.R.reg); + break; + default: + vassert(0); + } +} + +static void addRegUsage_ARMRI5 ( HRegUsage* u, ARMRI5* ri5 ) { + switch (ri5->tag) { + case ARMri5_I5: + return; + case ARMri5_R: + addHRegUse(u, HRmRead, ri5->ARMri5.R.reg); + return; + default: + vpanic("addRegUsage_ARMRI5"); + } +} + +static void mapRegs_ARMRI5 ( HRegRemap* m, ARMRI5* ri5 ) { + switch (ri5->tag) { + case ARMri5_I5: + return; + case ARMri5_R: + ri5->ARMri5.R.reg = lookupHRegRemap(m, ri5->ARMri5.R.reg); + return; + default: + vpanic("mapRegs_ARMRI5"); + } +} + +/* -------- Neon Immediate operatnd --------- */ + +ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 ) { + ARMNImm* i = LibVEX_Alloc(sizeof(ARMNImm)); + i->type = type; + i->imm8 = imm8; + return i; +} + +ULong ARMNImm_to_Imm64 ( ARMNImm* imm ) { + int i, j; + ULong y, x = imm->imm8; + switch (imm->type) { + case 3: + x = x << 8; + case 2: + x = x << 8; + case 1: + x = x << 8; + case 0: + return (x << 32) | x; + case 5: + case 6: + if (imm->type == 5) + x = x << 8; + else + x = (x << 8) | x; + case 4: + x = (x << 16) | x; + return (x << 32) | x; + case 8: + x = (x << 8) | 0xFF; + case 7: + x = (x << 8) | 0xFF; + return (x << 32) | x; + case 9: + x = 0; + for (i = 7; i >= 0; i--) { + y = ((ULong)imm->imm8 >> i) & 1; + for (j = 0; j < 8; j++) { + x = (x << 1) | y; + } + } + return x; + case 10: + x |= (x & 0x80) << 5; + x |= ~(x & 0x40) << 5; + x &= 0x187F; /* 0001 1000 0111 1111 */ + x |= (x & 0x40) << 4; + x |= (x & 0x40) << 3; + x |= (x & 0x40) << 2; + x |= (x & 0x40) << 1; + x = x << 19; + x = (x << 32) | x; + return x; + default: + vpanic("ARMNImm_to_Imm64"); + } +} + +ARMNImm* Imm64_to_ARMNImm ( ULong x ) { + ARMNImm tmp; + if ((x & 0xFFFFFFFF) == (x >> 32)) { + if ((x & 0xFFFFFF00) == 0) + return ARMNImm_TI(0, x & 0xFF); + if ((x & 0xFFFF00FF) == 0) + return ARMNImm_TI(1, (x >> 8) & 0xFF); + if ((x & 0xFF00FFFF) == 0) + return ARMNImm_TI(2, (x >> 16) & 0xFF); + if ((x & 0x00FFFFFF) == 0) + return ARMNImm_TI(3, (x >> 24) & 0xFF); + if ((x & 0xFFFF00FF) == 0xFF) + return ARMNImm_TI(7, (x >> 8) & 0xFF); + if ((x & 0xFF00FFFF) == 0xFFFF) + return ARMNImm_TI(8, (x >> 16) & 0xFF); + if ((x & 0xFFFF) == ((x >> 16) & 0xFFFF)) { + if ((x & 0xFF00) == 0) + return ARMNImm_TI(4, x & 0xFF); + if ((x & 0x00FF) == 0) + return ARMNImm_TI(5, (x >> 8) & 0xFF); + if ((x & 0xFF) == ((x >> 8) & 0xFF)) + return ARMNImm_TI(6, x & 0xFF); + } + if ((x & 0x7FFFF) == 0) { + tmp.type = 10; + tmp.imm8 = ((x >> 19) & 0x7F) | ((x >> 24) & 0x80); + if (ARMNImm_to_Imm64(&tmp) == x) + return ARMNImm_TI(tmp.type, tmp.imm8); + } + } else { + /* This can only be type 9. */ + tmp.imm8 = (((x >> 56) & 1) << 7) + | (((x >> 48) & 1) << 6) + | (((x >> 40) & 1) << 5) + | (((x >> 32) & 1) << 4) + | (((x >> 24) & 1) << 3) + | (((x >> 16) & 1) << 2) + | (((x >> 8) & 1) << 1) + | (((x >> 0) & 1) << 0); + tmp.type = 9; + if (ARMNImm_to_Imm64 (&tmp) == x) + return ARMNImm_TI(tmp.type, tmp.imm8); + } + return NULL; +} + +void ppARMNImm (ARMNImm* i) { + ULong x = ARMNImm_to_Imm64(i); + vex_printf("0x%llX%llX", x, x); } +/* -- Register or scalar operand --- */ +ARMNRS* mkARMNRS(ARMNRS_tag tag, HReg reg, UInt index) +{ + ARMNRS *p = LibVEX_Alloc(sizeof(ARMNRS)); + p->tag = tag; + p->reg = reg; + p->index = index; + return p; +} +void ppARMNRS(ARMNRS *p) +{ + ppHRegARM(p->reg); + if (p->tag == ARMNRS_Scalar) { + vex_printf("[%d]", p->index); + } +} /* --------- Instructions. --------- */ HChar* showARMAluOp ( ARMAluOp op ) { - switch (op) { - case ARMalu_AND: return "and"; - case ARMalu_ORR: return "orr"; - case ARMalu_EOR: return "eor"; - case ARMalu_SUB: return "sub"; - case ARMalu_RSB: return "rsb"; - case ARMalu_ADD: return "add"; - case ARMalu_ADC: return "adc"; - case ARMalu_SBC: return "sbc"; - case ARMalu_RSC: return "rsc"; - case ARMalu_TST: return "tst"; - case ARMalu_TEQ: return "teq"; - case ARMalu_CMP: return "cmp"; - case ARMalu_CMN: return "cmn"; - case ARMalu_MOV: return "mov"; - case ARMalu_MVN: return "mvn"; - case ARMalu_BIC: return "bic"; - default: vpanic("showARMAluOp"); - } + switch (op) { + case ARMalu_ADD: return "add"; + case ARMalu_ADDS: return "adds"; + case ARMalu_ADC: return "adc"; + case ARMalu_SUB: return "sub"; + case ARMalu_SUBS: return "subs"; + case ARMalu_SBC: return "sbc"; + case ARMalu_AND: return "and"; + case ARMalu_BIC: return "bic"; + case ARMalu_OR: return "orr"; + case ARMalu_XOR: return "xor"; + default: vpanic("showARMAluOp"); + } } -/* --- Addressing Mode 1 --- */ -ARMInstr* ARMInstr_DPCmp ( ARMAluOp op, HReg Rn, - ARMAMode1* shifter_op ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_DPCmp; - i->ARMin.DPCmp.op = op; - i->ARMin.DPCmp.Rn = Rn; - i->ARMin.DPCmp.shifter_op = shifter_op; - return i; -} - -ARMInstr* ARMInstr_DPInstr1 ( ARMAluOp op, HReg Rd, - ARMAMode1* shifter_op ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_DPInstr1; - i->ARMin.DPInstr1.op = op; - i->ARMin.DPInstr1.Rd = Rd; - i->ARMin.DPInstr1.shifter_op = shifter_op; - return i; -} - -ARMInstr* ARMInstr_DPInstr2 ( ARMAluOp op, HReg Rd, HReg Rn, - ARMAMode1* shifter_op ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_DPInstr2; - i->ARMin.DPInstr2.op = op; - i->ARMin.DPInstr2.Rd = Rd; - i->ARMin.DPInstr2.Rn = Rn; - i->ARMin.DPInstr2.shifter_op = shifter_op; - return i; +HChar* showARMShiftOp ( ARMShiftOp op ) { + switch (op) { + case ARMsh_SHL: return "shl"; + case ARMsh_SHR: return "shr"; + case ARMsh_SAR: return "sar"; + default: vpanic("showARMShiftOp"); + } +} + +HChar* showARMUnaryOp ( ARMUnaryOp op ) { + switch (op) { + case ARMun_NEG: return "neg"; + case ARMun_NOT: return "not"; + case ARMun_CLZ: return "clz"; + default: vpanic("showARMUnaryOp"); + } +} + +HChar* showARMMulOp ( ARMMulOp op ) { + switch (op) { + case ARMmul_PLAIN: return "mul"; + case ARMmul_ZX: return "umull"; + case ARMmul_SX: return "smull"; + default: vpanic("showARMMulOp"); + } } -/* --- Addressing Mode 2 --- */ -ARMInstr* ARMInstr_LoadUB ( HReg Rd, ARMAMode2* addr_mode ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_LoadUB; - i->ARMin.LoadUB.Rd = Rd; - i->ARMin.LoadUB.addr_mode = addr_mode; - return i; +HChar* showARMVfpOp ( ARMVfpOp op ) { + switch (op) { + case ARMvfp_ADD: return "add"; + case ARMvfp_SUB: return "sub"; + case ARMvfp_MUL: return "mul"; + case ARMvfp_DIV: return "div"; + default: vpanic("showARMVfpOp"); + } } -ARMInstr* ARMInstr_StoreB ( HReg Rd, ARMAMode2* addr_mode ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_StoreB; - i->ARMin.StoreB.Rd = Rd; - i->ARMin.StoreB.addr_mode = addr_mode; - return i; +HChar* showARMVfpUnaryOp ( ARMVfpUnaryOp op ) { + switch (op) { + case ARMvfpu_COPY: return "cpy"; + case ARMvfpu_NEG: return "neg"; + case ARMvfpu_ABS: return "abs"; + case ARMvfpu_SQRT: return "sqrt"; + default: vpanic("showARMVfpUnaryOp"); + } } -ARMInstr* ARMInstr_LoadW ( HReg Rd, ARMAMode2* addr_mode ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_LoadW; - i->ARMin.LoadW.Rd = Rd; - i->ARMin.LoadW.addr_mode = addr_mode; - return i; +HChar* showARMNeonBinOp ( ARMNeonBinOp op ) { + switch (op) { + case ARMneon_VAND: return "vand"; + case ARMneon_VORR: return "vorr"; + case ARMneon_VXOR: return "veor"; + case ARMneon_VADD: return "vadd"; + case ARMneon_VRHADDS: return "vrhadd"; + case ARMneon_VRHADDU: return "vrhadd"; + case ARMneon_VADDFP: return "vadd"; + case ARMneon_VPADDFP: return "vpadd"; + case ARMneon_VABDFP: return "vabd"; + case ARMneon_VSUB: return "vsub"; + case ARMneon_VSUBFP: return "vsub"; + case ARMneon_VMINU: return "vmin"; + case ARMneon_VMINS: return "vmin"; + case ARMneon_VMINF: return "vmin"; + case ARMneon_VMAXU: return "vmax"; + case ARMneon_VMAXS: return "vmax"; + case ARMneon_VMAXF: return "vmax"; + case ARMneon_VQADDU: return "vqadd"; + case ARMneon_VQADDS: return "vqadd"; + case ARMneon_VQSUBU: return "vqsub"; + case ARMneon_VQSUBS: return "vqsub"; + case ARMneon_VCGTU: return "vcgt"; + case ARMneon_VCGTS: return "vcgt"; + case ARMneon_VCGTF: return "vcgt"; + case ARMneon_VCGEF: return "vcgt"; + case ARMneon_VCGEU: return "vcge"; + case ARMneon_VCGES: return "vcge"; + case ARMneon_VCEQ: return "vceq"; + case ARMneon_VCEQF: return "vceq"; + case ARMneon_VPADD: return "vpadd"; + case ARMneon_VPMINU: return "vpmin"; + case ARMneon_VPMINS: return "vpmin"; + case ARMneon_VPMINF: return "vpmin"; + case ARMneon_VPMAXU: return "vpmax"; + case ARMneon_VPMAXS: return "vpmax"; + case ARMneon_VPMAXF: return "vpmax"; + case ARMneon_VEXT: return "vext"; + case ARMneon_VMUL: return "vmuli"; + case ARMneon_VMULLU: return "vmull"; + case ARMneon_VMULLS: return "vmull"; + case ARMneon_VMULP: return "vmul"; + case ARMneon_VMULFP: return "vmul"; + case ARMneon_VMULLP: return "vmul"; + case ARMneon_VQDMULH: return "vqdmulh"; + case ARMneon_VQRDMULH: return "vqrdmulh"; + case ARMneon_VQDMULL: return "vqdmull"; + case ARMneon_VTBL: return "vtbl"; + case ARMneon_VRECPS: return "vrecps"; + case ARMneon_VRSQRTS: return "vrecps"; + /* ... */ + default: vpanic("showARMNeonBinOp"); + } } -ARMInstr* ARMInstr_StoreW ( HReg Rd, ARMAMode2* addr_mode ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_StoreW; - i->ARMin.StoreW.Rd = Rd; - i->ARMin.StoreW.addr_mode = addr_mode; - return i; +HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op ) { + switch (op) { + case ARMneon_VAND: + case ARMneon_VORR: + case ARMneon_VXOR: + return ""; + case ARMneon_VADD: + case ARMneon_VSUB: + case ARMneon_VEXT: + case ARMneon_VMUL: + case ARMneon_VPADD: + case ARMneon_VTBL: + case ARMneon_VCEQ: + return ".i"; + case ARMneon_VRHADDU: + case ARMneon_VMINU: + case ARMneon_VMAXU: + case ARMneon_VQADDU: + case ARMneon_VQSUBU: + case ARMneon_VCGTU: + case ARMneon_VCGEU: + case ARMneon_VMULLU: + case ARMneon_VPMINU: + case ARMneon_VPMAXU: + return ".u"; + case ARMneon_VRHADDS: + case ARMneon_VMINS: + case ARMneon_VMAXS: + case ARMneon_VQADDS: + case ARMneon_VQSUBS: + case ARMneon_VCGTS: + case ARMneon_VCGES: + case ARMneon_VQDMULL: + case ARMneon_VMULLS: + case ARMneon_VPMINS: + case ARMneon_VPMAXS: + case ARMneon_VQDMULH: + case ARMneon_VQRDMULH: + return ".s"; + case ARMneon_VMULP: + case ARMneon_VMULLP: + return ".p"; + case ARMneon_VADDFP: + case ARMneon_VABDFP: + case ARMneon_VPADDFP: + case ARMneon_VSUBFP: + case ARMneon_VMULFP: + case ARMneon_VMINF: + case ARMneon_VMAXF: + case ARMneon_VPMINF: + case ARMneon_VPMAXF: + case ARMneon_VCGTF: + case ARMneon_VCGEF: + case ARMneon_VCEQF: + case ARMneon_VRECPS: + case ARMneon_VRSQRTS: + return ".f"; + /* ... */ + default: vpanic("showARMNeonBinOpDataType"); + } } -/* --- Addressing Mode 3 --- */ -ARMInstr* ARMInstr_LoadSB ( HReg Rd, ARMAMode3* addr_mode ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_LoadSB; - i->ARMin.LoadSB.Rd = Rd; - i->ARMin.LoadSB.addr_mode = addr_mode; - return i; +HChar* showARMNeonUnOp ( ARMNeonUnOp op ) { + switch (op) { + case ARMneon_COPY: return "vmov"; + case ARMneon_COPYLS: return "vmov"; + case ARMneon_COPYLU: return "vmov"; + case ARMneon_COPYN: return "vmov"; + case ARMneon_COPYQNSS: return "vqmovn"; + case ARMneon_COPYQNUS: return "vqmovun"; + case ARMneon_COPYQNUU: return "vqmovn"; + case ARMneon_NOT: return "vmvn"; + case ARMneon_EQZ: return "vceq"; + case ARMneon_CNT: return "vcnt"; + case ARMneon_CLS: return "vcls"; + case ARMneon_CLZ: return "vclz"; + case ARMneon_DUP: return "vdup"; + case ARMneon_PADDLS: return "vpaddl"; + case ARMneon_PADDLU: return "vpaddl"; + case ARMneon_VQSHLNSS: return "vqshl"; + case ARMneon_VQSHLNUU: return "vqshl"; + case ARMneon_VQSHLNUS: return "vqshlu"; + case ARMneon_REV16: return "vrev16"; + case ARMneon_REV32: return "vrev32"; + case ARMneon_REV64: return "vrev64"; + case ARMneon_VCVTFtoU: return "vcvt"; + case ARMneon_VCVTFtoS: return "vcvt"; + case ARMneon_VCVTUtoF: return "vcvt"; + case ARMneon_VCVTStoF: return "vcvt"; + case ARMneon_VCVTFtoFixedU: return "vcvt"; + case ARMneon_VCVTFtoFixedS: return "vcvt"; + case ARMneon_VCVTFixedUtoF: return "vcvt"; + case ARMneon_VCVTFixedStoF: return "vcvt"; + case ARMneon_VCVTF32toF16: return "vcvt"; + case ARMneon_VCVTF16toF32: return "vcvt"; + case ARMneon_VRECIP: return "vrecip"; + case ARMneon_VRECIPF: return "vrecipf"; + case ARMneon_VNEGF: return "vneg"; + case ARMneon_ABS: return "vabs"; + case ARMneon_VABSFP: return "vabsfp"; + case ARMneon_VRSQRTEFP: return "vrsqrtefp"; + case ARMneon_VRSQRTE: return "vrsqrte"; + /* ... */ + default: vpanic("showARMNeonUnOp"); + } } -ARMInstr* ARMInstr_LoadUH ( HReg Rd, ARMAMode3* addr_mode ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_LoadUH; - i->ARMin.LoadUH.Rd = Rd; - i->ARMin.LoadUH.addr_mode = addr_mode; - return i; +HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op ) { + switch (op) { + case ARMneon_COPY: + case ARMneon_NOT: + return ""; + case ARMneon_COPYN: + case ARMneon_EQZ: + case ARMneon_CNT: + case ARMneon_DUP: + case ARMneon_REV16: + case ARMneon_REV32: + case ARMneon_REV64: + return ".i"; + case ARMneon_COPYLU: + case ARMneon_PADDLU: + case ARMneon_COPYQNUU: + case ARMneon_VQSHLNUU: + case ARMneon_VRECIP: + case ARMneon_VRSQRTE: + return ".u"; + case ARMneon_CLS: + case ARMneon_CLZ: + case ARMneon_COPYLS: + case ARMneon_PADDLS: + case ARMneon_COPYQNSS: + case ARMneon_COPYQNUS: + case ARMneon_VQSHLNSS: + case ARMneon_VQSHLNUS: + case ARMneon_ABS: + return ".s"; + case ARMneon_VRECIPF: + case ARMneon_VNEGF: + case ARMneon_VABSFP: + case ARMneon_VRSQRTEFP: + return ".f"; + case ARMneon_VCVTFtoU: return ".u32.f32"; + case ARMneon_VCVTFtoS: return ".s32.f32"; + case ARMneon_VCVTUtoF: return ".f32.u32"; + case ARMneon_VCVTStoF: return ".f32.s32"; + case ARMneon_VCVTF16toF32: return ".f32.f16"; + case ARMneon_VCVTF32toF16: return ".f16.f32"; + case ARMneon_VCVTFtoFixedU: return ".u32.f32"; + case ARMneon_VCVTFtoFixedS: return ".s32.f32"; + case ARMneon_VCVTFixedUtoF: return ".f32.u32"; + case ARMneon_VCVTFixedStoF: return ".f32.s32"; + /* ... */ + default: vpanic("showARMNeonUnOpDataType"); + } } -ARMInstr* ARMInstr_LoadSH ( HReg Rd, ARMAMode3* addr_mode ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_LoadSH; - i->ARMin.LoadSH.Rd = Rd; - i->ARMin.LoadSH.addr_mode = addr_mode; - return i; +HChar* showARMNeonUnOpS ( ARMNeonUnOpS op ) { + switch (op) { + case ARMneon_SETELEM: return "vmov"; + case ARMneon_GETELEMU: return "vmov"; + case ARMneon_GETELEMS: return "vmov"; + case ARMneon_VDUP: return "vdup"; + /* ... */ + default: vpanic("showARMNeonUnarySOp"); + } } -ARMInstr* ARMInstr_StoreH ( HReg Rd, ARMAMode3* addr_mode ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_StoreH; - i->ARMin.StoreH.Rd = Rd; - i->ARMin.StoreH.addr_mode = addr_mode; - return i; +HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op ) { + switch (op) { + case ARMneon_SETELEM: + case ARMneon_VDUP: + return ".i"; + case ARMneon_GETELEMS: + return ".s"; + case ARMneon_GETELEMU: + return ".u"; + /* ... */ + default: vpanic("showARMNeonUnarySOp"); + } } -/* --- Branch --- */ -ARMInstr* ARMInstr_Branch ( ARMCondCode cond, ARMBranchDest* dest ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_Branch; - i->ARMin.Branch.cond = cond; - i->ARMin.Branch.dest = dest; - return i; +HChar* showARMNeonShiftOp ( ARMNeonShiftOp op ) { + switch (op) { + case ARMneon_VSHL: return "vshl"; + case ARMneon_VSAL: return "vshl"; + case ARMneon_VQSHL: return "vqshl"; + case ARMneon_VQSAL: return "vqshl"; + /* ... */ + default: vpanic("showARMNeonShiftOp"); + } } -ARMInstr* ARMInstr_BranchL ( ARMCondCode cond, ARMBranchDest* dest ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_BranchL; - i->ARMin.BranchL.dest = dest; - return i; -} +HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op ) { + switch (op) { + case ARMneon_VSHL: + case ARMneon_VQSHL: + return ".u"; + case ARMneon_VSAL: + case ARMneon_VQSAL: + return ".s"; + /* ... */ + default: vpanic("showARMNeonShiftOpDataType"); + } +} -/* --- Literal --- */ -ARMInstr* ARMInstr_Literal ( HReg reg, UInt imm ) { - ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); - i->tag = ARMin_Literal; - i->ARMin.Literal.reg = reg; - i->ARMin.Literal.imm = imm; - return i; +HChar* showARMNeonDualOp ( ARMNeonDualOp op ) { + switch (op) { + case ARMneon_TRN: return "vtrn"; + case ARMneon_ZIP: return "vzip"; + case ARMneon_UZP: return "vuzp"; + /* ... */ + default: vpanic("showARMNeonDualOp"); + } } +HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op ) { + switch (op) { + case ARMneon_TRN: + case ARMneon_ZIP: + case ARMneon_UZP: + return "i"; + /* ... */ + default: vpanic("showARMNeonDualOp"); + } +} -void ppARMInstr ( ARMInstr* i ) { - switch (i->tag) { - case ARMin_DPCmp: - case ARMin_DPInstr1: - case ARMin_DPInstr2: - case ARMin_LoadUB: - case ARMin_StoreB: - case ARMin_LoadW: - case ARMin_StoreW: - case ARMin_LoadSB: - case ARMin_LoadUH: - case ARMin_LoadSH: - case ARMin_StoreH: - case ARMin_Branch: - case ARMin_BranchL: - case ARMin_Literal: - vex_printf("ppARMInstr: Not implemented"); - break; - - default: - vpanic("ppARMInstr"); - } +static HChar* showARMNeonDataSize_wrk ( UInt size ) +{ + switch (size) { + case 0: return "8"; + case 1: return "16"; + case 2: return "32"; + case 3: return "64"; + default: vpanic("showARMNeonDataSize"); + } } +static HChar* showARMNeonDataSize ( ARMInstr* i ) +{ + switch (i->tag) { + case ARMin_NBinary: + if (i->ARMin.NBinary.op == ARMneon_VEXT) + return "8"; + if (i->ARMin.NBinary.op == ARMneon_VAND || + i->ARMin.NBinary.op == ARMneon_VORR || + i->ARMin.NBinary.op == ARMneon_VXOR) + return ""; + return showARMNeonDataSize_wrk(i->ARMin.NBinary.size); + case ARMin_NUnary: + if (i->ARMin.NUnary.op == ARMneon_COPY || + i->ARMin.NUnary.op == ARMneon_NOT || + i->ARMin.NUnary.op == ARMneon_VCVTF32toF16|| + i->ARMin.NUnary.op == ARMneon_VCVTF16toF32|| + i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS || + i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU || + i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF || + i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF || + i->ARMin.NUnary.op == ARMneon_VCVTFtoS || + i->ARMin.NUnary.op == ARMneon_VCVTFtoU || + i->ARMin.NUnary.op == ARMneon_VCVTStoF || + i->ARMin.NUnary.op == ARMneon_VCVTUtoF) + return ""; + if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS || + i->ARMin.NUnary.op == ARMneon_VQSHLNUU || + i->ARMin.NUnary.op == ARMneon_VQSHLNUS) { + UInt size; + size = i->ARMin.NUnary.size; + if (size & 0x40) + return "64"; + if (size & 0x20) + return "32"; + if (size & 0x10) + return "16"; + if (size & 0x08) + return "8"; + vpanic("showARMNeonDataSize"); + } + return showARMNeonDataSize_wrk(i->ARMin.NUnary.size); + case ARMin_NUnaryS: + if (i->ARMin.NUnaryS.op == ARMneon_VDUP) { + int size; + size = i->ARMin.NUnaryS.size; + if ((size & 1) == 1) + return "8"; + if ((size & 3) == 2) + return "16"; + if ((size & 7) == 4) + return "32"; + vpanic("showARMNeonDataSize"); + } + return showARMNeonDataSize_wrk(i->ARMin.NUnaryS.size); + case ARMin_NShift: + return showARMNeonDataSize_wrk(i->ARMin.NShift.size); + case ARMin_NDual: + return showARMNeonDataSize_wrk(i->ARMin.NDual.size); + default: + vpanic("showARMNeonDataSize"); + } +} + +ARMInstr* ARMInstr_Alu ( ARMAluOp op, + HReg dst, HReg argL, ARMRI84* argR ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_Alu; + i->ARMin.Alu.op = op; + i->ARMin.Alu.dst = dst; + i->ARMin.Alu.argL = argL; + i->ARMin.Alu.argR = argR; + return i; +} +ARMInstr* ARMInstr_Shift ( ARMShiftOp op, + HReg dst, HReg argL, ARMRI5* argR ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_Shift; + i->ARMin.Shift.op = op; + i->ARMin.Shift.dst = dst; + i->ARMin.Shift.argL = argL; + i->ARMin.Shift.argR = argR; + return i; +} +ARMInstr* ARMInstr_Unary ( ARMUnaryOp op, HReg dst, HReg src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_Unary; + i->ARMin.Unary.op = op; + i->ARMin.Unary.dst = dst; + i->ARMin.Unary.src = src; + return i; +} +ARMInstr* ARMInstr_CmpOrTst ( Bool isCmp, HReg argL, ARMRI84* argR ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_CmpOrTst; + i->ARMin.CmpOrTst.isCmp = isCmp; + i->ARMin.CmpOrTst.argL = argL; + i->ARMin.CmpOrTst.argR = argR; + return i; +} +ARMInstr* ARMInstr_Mov ( HReg dst, ARMRI84* src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_Mov; + i->ARMin.Mov.dst = dst; + i->ARMin.Mov.src = src; + return i; +} +ARMInstr* ARMInstr_Imm32 ( HReg dst, UInt imm32 ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_Imm32; + i->ARMin.Imm32.dst = dst; + i->ARMin.Imm32.imm32 = imm32; + return i; +} +ARMInstr* ARMInstr_LdSt32 ( Bool isLoad, HReg rD, ARMAMode1* amode ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_LdSt32; + i->ARMin.LdSt32.isLoad = isLoad; + i->ARMin.LdSt32.rD = rD; + i->ARMin.LdSt32.amode = amode; + return i; +} +ARMInstr* ARMInstr_LdSt16 ( Bool isLoad, Bool signedLoad, + HReg rD, ARMAMode2* amode ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_LdSt16; + i->ARMin.LdSt16.isLoad = isLoad; + i->ARMin.LdSt16.signedLoad = signedLoad; + i->ARMin.LdSt16.rD = rD; + i->ARMin.LdSt16.amode = amode; + return i; +} +ARMInstr* ARMInstr_LdSt8U ( Bool isLoad, HReg rD, ARMAMode1* amode ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_LdSt8U; + i->ARMin.LdSt8U.isLoad = isLoad; + i->ARMin.LdSt8U.rD = rD; + i->ARMin.LdSt8U.amode = amode; + return i; +} +//extern ARMInstr* ARMInstr_Ld8S ( HReg, ARMAMode2* ); +ARMInstr* ARMInstr_Goto ( IRJumpKind jk, ARMCondCode cond, HReg gnext ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_Goto; + i->ARMin.Goto.jk = jk; + i->ARMin.Goto.cond = cond; + i->ARMin.Goto.gnext = gnext; + return i; +} +ARMInstr* ARMInstr_CMov ( ARMCondCode cond, HReg dst, ARMRI84* src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_CMov; + i->ARMin.CMov.cond = cond; + i->ARMin.CMov.dst = dst; + i->ARMin.CMov.src = src; + vassert(cond != ARMcc_AL); + return i; +} +ARMInstr* ARMInstr_Call ( ARMCondCode cond, HWord target, Int nArgRegs ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_Call; + i->ARMin.Call.cond = cond; + i->ARMin.Call.target = target; + i->ARMin.Call.nArgRegs = nArgRegs; + return i; +} +ARMInstr* ARMInstr_Mul ( ARMMulOp op ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_Mul; + i->ARMin.Mul.op = op; + return i; +} +ARMInstr* ARMInstr_LdrEX ( Int szB ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_LdrEX; + i->ARMin.LdrEX.szB = szB; + vassert(szB == 4 || szB == 1); + return i; +} +ARMInstr* ARMInstr_StrEX ( Int szB ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_StrEX; + i->ARMin.StrEX.szB = szB; + vassert(szB == 4 || szB == 1); + return i; +} +ARMInstr* ARMInstr_VLdStD ( Bool isLoad, HReg dD, ARMAModeV* am ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VLdStD; + i->ARMin.VLdStD.isLoad = isLoad; + i->ARMin.VLdStD.dD = dD; + i->ARMin.VLdStD.amode = am; + return i; +} +ARMInstr* ARMInstr_VLdStS ( Bool isLoad, HReg fD, ARMAModeV* am ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VLdStS; + i->ARMin.VLdStS.isLoad = isLoad; + i->ARMin.VLdStS.fD = fD; + i->ARMin.VLdStS.amode = am; + return i; +} +ARMInstr* ARMInstr_VAluD ( ARMVfpOp op, HReg dst, HReg argL, HReg argR ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VAluD; + i->ARMin.VAluD.op = op; + i->ARMin.VAluD.dst = dst; + i->ARMin.VAluD.argL = argL; + i->ARMin.VAluD.argR = argR; + return i; +} +ARMInstr* ARMInstr_VAluS ( ARMVfpOp op, HReg dst, HReg argL, HReg argR ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VAluS; + i->ARMin.VAluS.op = op; + i->ARMin.VAluS.dst = dst; + i->ARMin.VAluS.argL = argL; + i->ARMin.VAluS.argR = argR; + return i; +} +ARMInstr* ARMInstr_VUnaryD ( ARMVfpUnaryOp op, HReg dst, HReg src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VUnaryD; + i->ARMin.VUnaryD.op = op; + i->ARMin.VUnaryD.dst = dst; + i->ARMin.VUnaryD.src = src; + return i; +} +ARMInstr* ARMInstr_VUnaryS ( ARMVfpUnaryOp op, HReg dst, HReg src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VUnaryS; + i->ARMin.VUnaryS.op = op; + i->ARMin.VUnaryS.dst = dst; + i->ARMin.VUnaryS.src = src; + return i; +} +ARMInstr* ARMInstr_VCmpD ( HReg argL, HReg argR ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VCmpD; + i->ARMin.VCmpD.argL = argL; + i->ARMin.VCmpD.argR = argR; + return i; +} +ARMInstr* ARMInstr_VCMovD ( ARMCondCode cond, HReg dst, HReg src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VCMovD; + i->ARMin.VCMovD.cond = cond; + i->ARMin.VCMovD.dst = dst; + i->ARMin.VCMovD.src = src; + vassert(cond != ARMcc_AL); + return i; +} +ARMInstr* ARMInstr_VCMovS ( ARMCondCode cond, HReg dst, HReg src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VCMovS; + i->ARMin.VCMovS.cond = cond; + i->ARMin.VCMovS.dst = dst; + i->ARMin.VCMovS.src = src; + vassert(cond != ARMcc_AL); + return i; +} +ARMInstr* ARMInstr_VCvtSD ( Bool sToD, HReg dst, HReg src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VCvtSD; + i->ARMin.VCvtSD.sToD = sToD; + i->ARMin.VCvtSD.dst = dst; + i->ARMin.VCvtSD.src = src; + return i; +} +ARMInstr* ARMInstr_VXferD ( Bool toD, HReg dD, HReg rHi, HReg rLo ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VXferD; + i->ARMin.VXferD.toD = toD; + i->ARMin.VXferD.dD = dD; + i->ARMin.VXferD.rHi = rHi; + i->ARMin.VXferD.rLo = rLo; + return i; +} +ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VXferS; + i->ARMin.VXferS.toS = toS; + i->ARMin.VXferS.fD = fD; + i->ARMin.VXferS.rLo = rLo; + return i; +} +ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned, + HReg dst, HReg src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_VCvtID; + i->ARMin.VCvtID.iToD = iToD; + i->ARMin.VCvtID.syned = syned; + i->ARMin.VCvtID.dst = dst; + i->ARMin.VCvtID.src = src; + return i; +} +ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_FPSCR; + i->ARMin.FPSCR.toFPSCR = toFPSCR; + i->ARMin.FPSCR.iReg = iReg; + return i; +} +ARMInstr* ARMInstr_MFence ( void ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_MFence; + return i; +} + +ARMInstr* ARMInstr_NLdStQ ( Bool isLoad, HReg dQ, ARMAModeN *amode ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NLdStQ; + i->ARMin.NLdStQ.isLoad = isLoad; + i->ARMin.NLdStQ.dQ = dQ; + i->ARMin.NLdStQ.amode = amode; + return i; +} +ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg dD, ARMAModeN *amode ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NLdStD; + i->ARMin.NLdStD.isLoad = isLoad; + i->ARMin.NLdStD.dD = dD; + i->ARMin.NLdStD.amode = amode; + return i; +} +ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp op, HReg dQ, HReg nQ, + UInt size, Bool Q ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NUnary; + i->ARMin.NUnary.op = op; + i->ARMin.NUnary.src = nQ; + i->ARMin.NUnary.dst = dQ; + i->ARMin.NUnary.size = size; + i->ARMin.NUnary.Q = Q; + return i; +} -/* --------- Helpers for register allocation. --------- */ +ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOp op, ARMNRS* dst, ARMNRS* src, + UInt size, Bool Q ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NUnaryS; + i->ARMin.NUnaryS.op = op; + i->ARMin.NUnaryS.src = src; + i->ARMin.NUnaryS.dst = dst; + i->ARMin.NUnaryS.size = size; + i->ARMin.NUnaryS.Q = Q; + return i; +} -void getRegUsage_ARMInstr ( HRegUsage* u, ARMInstr* i ) { -// Bool unary; - initHRegUsage(u); - switch (i->tag) { - case ARMin_DPCmp: - case ARMin_DPInstr1: - case ARMin_DPInstr2: - case ARMin_LoadUB: - case ARMin_StoreB: - case ARMin_LoadW: - case ARMin_StoreW: - case ARMin_LoadSB: - case ARMin_LoadUH: - case ARMin_LoadSH: - case ARMin_StoreH: - case ARMin_Branch: - case ARMin_BranchL: - case ARMin_Literal: - - default: - ppARMInstr(i); - vpanic("getRegUsage_ARMInstr"); - } +ARMInstr* ARMInstr_NDual ( ARMNeonDualOp op, HReg nQ, HReg mQ, + UInt size, Bool Q ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NDual; + i->ARMin.NDual.op = op; + i->ARMin.NDual.arg1 = nQ; + i->ARMin.NDual.arg2 = mQ; + i->ARMin.NDual.size = size; + i->ARMin.NDual.Q = Q; + return i; +} + +ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp op, + HReg dst, HReg argL, HReg argR, + UInt size, Bool Q ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NBinary; + i->ARMin.NBinary.op = op; + i->ARMin.NBinary.argL = argL; + i->ARMin.NBinary.argR = argR; + i->ARMin.NBinary.dst = dst; + i->ARMin.NBinary.size = size; + i->ARMin.NBinary.Q = Q; + return i; } +ARMInstr* ARMInstr_NeonImm (HReg dst, ARMNImm* imm ) { + ARMInstr *i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NeonImm; + i->ARMin.NeonImm.dst = dst; + i->ARMin.NeonImm.imm = imm; + return i; +} -/* local helper */ -#if 0 -static void mapReg(HRegRemap* m, HReg* r) { - *r = lookupHRegRemap(m, *r); +ARMInstr* ARMInstr_NCMovQ ( ARMCondCode cond, HReg dst, HReg src ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NCMovQ; + i->ARMin.NCMovQ.cond = cond; + i->ARMin.NCMovQ.dst = dst; + i->ARMin.NCMovQ.src = src; + vassert(cond != ARMcc_AL); + return i; } -#endif -void mapRegs_ARMInstr ( HRegRemap* m, ARMInstr* i ) { - switch (i->tag) { - case ARMin_DPCmp: - case ARMin_DPInstr1: - case ARMin_DPInstr2: - case ARMin_LoadUB: - case ARMin_StoreB: - case ARMin_LoadW: - case ARMin_StoreW: - case ARMin_LoadSB: - case ARMin_LoadUH: - case ARMin_LoadSH: - case ARMin_StoreH: - case ARMin_Branch: - case ARMin_BranchL: - case ARMin_Literal: - - default: - ppARMInstr(i); - vpanic("getRegUsage_ARMInstr"); - } +ARMInstr* ARMInstr_NShift ( ARMNeonShiftOp op, + HReg dst, HReg argL, HReg argR, + UInt size, Bool Q ) { + ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); + i->tag = ARMin_NShift; + i->ARMin.NShift.op = op; + i->ARMin.NShift.argL = argL; + i->ARMin.NShift.argR = argR; + i->ARMin.NShift.dst = dst; + i->ARMin.NShift.size = size; + i->ARMin.NShift.Q = Q; + return i; +} + +/* Helper copy-pasted from isel.c */ +static Bool fitsIn8x4 ( UInt* u8, UInt* u4, UInt u ) +{ + UInt i; + for (i = 0; i < 16; i++) { + if (0 == (u & 0xFFFFFF00)) { + *u8 = u; + *u4 = i; + return True; + } + u = ROR32(u, 30); + } + vassert(i == 16); + return False; +} + +ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) { + UInt u8, u4; + ARMInstr *i = LibVEX_Alloc(sizeof(ARMInstr)); + /* Try to generate single ADD if possible */ + if (fitsIn8x4(&u8, &u4, imm32)) { + i->tag = ARMin_Alu; + i->ARMin.Alu.op = ARMalu_ADD; + i->ARMin.Alu.dst = rD; + i->ARMin.Alu.argL = rN; + i->ARMin.Alu.argR = ARMRI84_I84(u8, u4); + } else { + i->tag = ARMin_Add32; + i->ARMin.Add32.rD = rD; + i->ARMin.Add32.rN = rN; + i->ARMin.Add32.imm32 = imm32; + } + return i; +} + +/* ... */ + +void ppARMInstr ( ARMInstr* i ) { + switch (i->tag) { + case ARMin_Alu: + vex_printf("%-4s ", showARMAluOp(i->ARMin.Alu.op)); + ppHRegARM(i->ARMin.Alu.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.Alu.argL); + vex_printf(", "); + ppARMRI84(i->ARMin.Alu.argR); + return; + case ARMin_Shift: + vex_printf("%s ", showARMShiftOp(i->ARMin.Shift.op)); + ppHRegARM(i->ARMin.Shift.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.Shift.argL); + vex_printf(", "); + ppARMRI5(i->ARMin.Shift.argR); + return; + case ARMin_Unary: + vex_printf("%s ", showARMUnaryOp(i->ARMin.Unary.op)); + ppHRegARM(i->ARMin.Unary.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.Unary.src); + return; + case ARMin_CmpOrTst: + vex_printf("%s ", i->ARMin.CmpOrTst.isCmp ? "cmp" : "tst"); + ppHRegARM(i->ARMin.CmpOrTst.argL); + vex_printf(", "); + ppARMRI84(i->ARMin.CmpOrTst.argR); + return; + case ARMin_Mov: + vex_printf("mov "); + ppHRegARM(i->ARMin.Mov.dst); + vex_printf(", "); + ppARMRI84(i->ARMin.Mov.src); + return; + case ARMin_Imm32: + vex_printf("imm "); + ppHRegARM(i->ARMin.Imm32.dst); + vex_printf(", 0x%x", i->ARMin.Imm32.imm32); + return; + case ARMin_LdSt32: + if (i->ARMin.LdSt32.isLoad) { + vex_printf("ldr "); + ppHRegARM(i->ARMin.LdSt32.rD); + vex_printf(", "); + ppARMAMode1(i->ARMin.LdSt32.amode); + } else { + vex_printf("str "); + ppARMAMode1(i->ARMin.LdSt32.amode); + vex_printf(", "); + ppHRegARM(i->ARMin.LdSt32.rD); + } + return; + case ARMin_LdSt16: + if (i->ARMin.LdSt16.isLoad) { + vex_printf("%s", i->ARMin.LdSt16.signedLoad + ? "ldrsh " : "ldrh " ); + ppHRegARM(i->ARMin.LdSt16.rD); + vex_printf(", "); + ppARMAMode2(i->ARMin.LdSt16.amode); + } else { + vex_printf("strh "); + ppARMAMode2(i->ARMin.LdSt16.amode); + vex_printf(", "); + ppHRegARM(i->ARMin.LdSt16.rD); + } + return; + case ARMin_LdSt8U: + if (i->ARMin.LdSt8U.isLoad) { + vex_printf("ldrb "); + ppHRegARM(i->ARMin.LdSt8U.rD); + vex_printf(", "); + ppARMAMode1(i->ARMin.LdSt8U.amode); + } else { + vex_printf("strb "); + ppARMAMode1(i->ARMin.LdSt8U.amode); + vex_printf(", "); + ppHRegARM(i->ARMin.LdSt8U.rD); + } + return; + case ARMin_Ld8S: + goto unhandled; + case ARMin_Goto: + if (i->ARMin.Goto.cond != ARMcc_AL) { + vex_printf("if (%%cpsr.%s) { ", + showARMCondCode(i->ARMin.Goto.cond)); + } else { + vex_printf("if (1) { "); + } + if (i->ARMin.Goto.jk != Ijk_Boring + && i->ARMin.Goto.jk != Ijk_Call + && i->ARMin.Goto.jk != Ijk_Ret) { + vex_printf("mov r8, $"); + ppIRJumpKind(i->ARMin.Goto.jk); + vex_printf(" ; "); + } + vex_printf("mov r0, "); + ppHRegARM(i->ARMin.Goto.gnext); + vex_printf(" ; bx r14"); + if (i->ARMin.Goto.cond != ARMcc_AL) { + vex_printf(" }"); + } else { + vex_printf(" }"); + } + return; + case ARMin_CMov: + vex_printf("mov%s ", showARMCondCode(i->ARMin.CMov.cond)); + ppHRegARM(i->ARMin.CMov.dst); + vex_printf(", "); + ppARMRI84(i->ARMin.CMov.src); + return; + case ARMin_Call: + vex_printf("call%s ", + i->ARMin.Call.cond==ARMcc_AL + ? "" : showARMCondCode(i->ARMin.Call.cond)); + vex_printf("0x%lx [nArgRegs=%d]", + i->ARMin.Call.target, i->ARMin.Call.nArgRegs); + return; + case ARMin_Mul: + vex_printf("%-5s ", showARMMulOp(i->ARMin.Mul.op)); + if (i->ARMin.Mul.op == ARMmul_PLAIN) { + vex_printf("r0, r2, r3"); + } else { + vex_printf("r1:r0, r2, r3"); + } + return; + case ARMin_LdrEX: + vex_printf("ldrex%s ", i->ARMin.LdrEX.szB == 1 ? "b" + : i->ARMin.LdrEX.szB == 2 ? "h" : ""); + vex_printf("r0, [r1]"); + return; + case ARMin_StrEX: + vex_printf("strex%s ", i->ARMin.StrEX.szB == 1 ? "b" + : i->ARMin.StrEX.szB == 2 ? "h" : ""); + vex_printf("r0, r1, [r2]"); + return; + case ARMin_VLdStD: + if (i->ARMin.VLdStD.isLoad) { + vex_printf("fldd "); + ppHRegARM(i->ARMin.VLdStD.dD); + vex_printf(", "); + ppARMAModeV(i->ARMin.VLdStD.amode); + } else { + vex_printf("fstd "); + ppARMAModeV(i->ARMin.VLdStD.amode); + vex_printf(", "); + ppHRegARM(i->ARMin.VLdStD.dD); + } + return; + case ARMin_VLdStS: + if (i->ARMin.VLdStS.isLoad) { + vex_printf("flds "); + ppHRegARM(i->ARMin.VLdStS.fD); + vex_printf(", "); + ppARMAModeV(i->ARMin.VLdStS.amode); + } else { + vex_printf("fsts "); + ppARMAModeV(i->ARMin.VLdStS.amode); + vex_printf(", "); + ppHRegARM(i->ARMin.VLdStS.fD); + } + return; + case ARMin_VAluD: + vex_printf("f%-3sd ", showARMVfpOp(i->ARMin.VAluD.op)); + ppHRegARM(i->ARMin.VAluD.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.VAluD.argL); + vex_printf(", "); + ppHRegARM(i->ARMin.VAluD.argR); + return; + case ARMin_VAluS: + vex_printf("f%-3ss ", showARMVfpOp(i->ARMin.VAluS.op)); + ppHRegARM(i->ARMin.VAluS.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.VAluS.argL); + vex_printf(", "); + ppHRegARM(i->ARMin.VAluS.argR); + return; + case ARMin_VUnaryD: + vex_printf("f%-3sd ", showARMVfpUnaryOp(i->ARMin.VUnaryD.op)); + ppHRegARM(i->ARMin.VUnaryD.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.VUnaryD.src); + return; + case ARMin_VUnaryS: + vex_printf("f%-3ss ", showARMVfpUnaryOp(i->ARMin.VUnaryS.op)); + ppHRegARM(i->ARMin.VUnaryS.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.VUnaryS.src); + return; + case ARMin_VCmpD: + vex_printf("fcmpd "); + ppHRegARM(i->ARMin.VCmpD.argL); + vex_printf(", "); + ppHRegARM(i->ARMin.VCmpD.argR); + vex_printf(" ; fmstat"); + return; + case ARMin_VCMovD: + vex_printf("fcpyd%s ", showARMCondCode(i->ARMin.VCMovD.cond)); + ppHRegARM(i->ARMin.VCMovD.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.VCMovD.src); + return; + case ARMin_VCMovS: + vex_printf("fcpys%s ", showARMCondCode(i->ARMin.VCMovS.cond)); + ppHRegARM(i->ARMin.VCMovS.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.VCMovS.src); + return; + case ARMin_VCvtSD: + vex_printf("fcvt%s ", i->ARMin.VCvtSD.sToD ? "ds" : "sd"); + ppHRegARM(i->ARMin.VCvtSD.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.VCvtSD.src); + return; + case ARMin_VXferD: + vex_printf("vmov "); + if (i->ARMin.VXferD.toD) { + ppHRegARM(i->ARMin.VXferD.dD); + vex_printf(", "); + ppHRegARM(i->ARMin.VXferD.rLo); + vex_printf(", "); + ppHRegARM(i->ARMin.VXferD.rHi); + } else { + ppHRegARM(i->ARMin.VXferD.rLo); + vex_printf(", "); + ppHRegARM(i->ARMin.VXferD.rHi); + vex_printf(", "); + ppHRegARM(i->ARMin.VXferD.dD); + } + return; + case ARMin_VXferS: + vex_printf("vmov "); + if (i->ARMin.VXferS.toS) { + ppHRegARM(i->ARMin.VXferS.fD); + vex_printf(", "); + ppHRegARM(i->ARMin.VXferS.rLo); + } else { + ppHRegARM(i->ARMin.VXferS.rLo); + vex_printf(", "); + ppHRegARM(i->ARMin.VXferS.fD); + } + return; + case ARMin_VCvtID: { + HChar* nm = "?"; + if (i->ARMin.VCvtID.iToD) { + nm = i->ARMin.VCvtID.syned ? "fsitod" : "fuitod"; + } else { + nm = i->ARMin.VCvtID.syned ? "ftosid" : "ftouid"; + } + vex_printf("%s ", nm); + ppHRegARM(i->ARMin.VCvtID.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.VCvtID.src); + return; + } + case ARMin_FPSCR: + if (i->ARMin.FPSCR.toFPSCR) { + vex_printf("fmxr fpscr, "); + ppHRegARM(i->ARMin.FPSCR.iReg); + } else { + vex_printf("fmrx "); + ppHRegARM(i->ARMin.FPSCR.iReg); + vex_printf(", fpscr"); + } + return; + case ARMin_MFence: + vex_printf("mfence (mcr 15,0,r0,c7,c10,4; 15,0,r0,c7,c10,5; " + "15,0,r0,c7,c5,4)"); + return; + case ARMin_NLdStQ: + if (i->ARMin.NLdStQ.isLoad) + vex_printf("vld1.32 {"); + else + vex_printf("vst1.32 {"); + ppHRegARM(i->ARMin.NLdStQ.dQ); + vex_printf("} "); + ppARMAModeN(i->ARMin.NLdStQ.amode); + return; + case ARMin_NLdStD: + if (i->ARMin.NLdStD.isLoad) + vex_printf("vld1.32 {"); + else + vex_printf("vst1.32 {"); + ppHRegARM(i->ARMin.NLdStD.dD); + vex_printf("} "); + ppARMAModeN(i->ARMin.NLdStD.amode); + return; + case ARMin_NUnary: + vex_printf("%s%s%s ", + showARMNeonUnOp(i->ARMin.NUnary.op), + showARMNeonUnOpDataType(i->ARMin.NUnary.op), + showARMNeonDataSize(i)); + ppHRegARM(i->ARMin.NUnary.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.NUnary.src); + if (i->ARMin.NUnary.op == ARMneon_EQZ) + vex_printf(", #0"); + if (i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS || + i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU || + i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF || + i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF) { + vex_printf(", #%d", i->ARMin.NUnary.size); + } + if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS || + i->ARMin.NUnary.op == ARMneon_VQSHLNUU || + i->ARMin.NUnary.op == ARMneon_VQSHLNUS) { + UInt size; + size = i->ARMin.NUnary.size; + if (size & 0x40) { + vex_printf(", #%d", size - 64); + } else if (size & 0x20) { + vex_printf(", #%d", size - 32); + } else if (size & 0x10) { + vex_printf(", #%d", size - 16); + } else if (size & 0x08) { + vex_printf(", #%d", size - 8); + } + } + return; + case ARMin_NUnaryS: + vex_printf("%s%s%s ", + showARMNeonUnOpS(i->ARMin.NUnary.op), + showARMNeonUnOpSDataType(i->ARMin.NUnary.op), + showARMNeonDataSize(i)); + ppARMNRS(i->ARMin.NUnaryS.dst); + vex_printf(", "); + ppARMNRS(i->ARMin.NUnaryS.src); + return; + case ARMin_NShift: + vex_printf("%s%s%s ", + showARMNeonShiftOp(i->ARMin.NShift.op), + showARMNeonShiftOpDataType(i->ARMin.NShift.op), + showARMNeonDataSize(i)); + ppHRegARM(i->ARMin.NShift.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.NShift.argL); + vex_printf(", "); + ppHRegARM(i->ARMin.NShift.argR); + return; + case ARMin_NDual: + vex_printf("%s%s%s ", + showARMNeonDualOp(i->ARMin.NDual.op), + showARMNeonDualOpDataType(i->ARMin.NDual.op), + showARMNeonDataSize(i)); + ppHRegARM(i->ARMin.NDual.arg1); + vex_printf(", "); + ppHRegARM(i->ARMin.NDual.arg2); + return; + case ARMin_NBinary: + vex_printf("%s%s%s", + showARMNeonBinOp(i->ARMin.NBinary.op), + showARMNeonBinOpDataType(i->ARMin.NBinary.op), + showARMNeonDataSize(i)); + vex_printf(" "); + ppHRegARM(i->ARMin.NBinary.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.NBinary.argL); + vex_printf(", "); + ppHRegARM(i->ARMin.NBinary.argR); + return; + case ARMin_NeonImm: + vex_printf("vmov "); + ppHRegARM(i->ARMin.NeonImm.dst); + vex_printf(", "); + ppARMNImm(i->ARMin.NeonImm.imm); + return; + case ARMin_NCMovQ: + vex_printf("vmov%s ", showARMCondCode(i->ARMin.NCMovQ.cond)); + ppHRegARM(i->ARMin.NCMovQ.dst); + vex_printf(", "); + ppHRegARM(i->ARMin.NCMovQ.src); + return; + case ARMin_Add32: + vex_printf("add32 "); + ppHRegARM(i->ARMin.Add32.rD); + vex_printf(", "); + ppHRegARM(i->ARMin.Add32.rN); + vex_printf(", "); + vex_printf("%d", i->ARMin.Add32.imm32); + return; + default: + unhandled: + vex_printf("ppARMInstr: unhandled case (tag %d)", (Int)i->tag); + vpanic("ppARMInstr(1)"); + return; + } +} + + +/* --------- Helpers for register allocation. --------- */ + +void getRegUsage_ARMInstr ( HRegUsage* u, ARMInstr* i, Bool mode64 ) +{ + vassert(mode64 == False); + initHRegUsage(u); + switch (i->tag) { + case ARMin_Alu: + addHRegUse(u, HRmWrite, i->ARMin.Alu.dst); + addHRegUse(u, HRmRead, i->ARMin.Alu.argL); + addRegUsage_ARMRI84(u, i->ARMin.Alu.argR); + return; + case ARMin_Shift: + addHRegUse(u, HRmWrite, i->ARMin.Shift.dst); + addHRegUse(u, HRmRead, i->ARMin.Shift.argL); + addRegUsage_ARMRI5(u, i->ARMin.Shift.argR); + return; + case ARMin_Unary: + addHRegUse(u, HRmWrite, i->ARMin.Unary.dst); + addHRegUse(u, HRmRead, i->ARMin.Unary.src); + return; + case ARMin_CmpOrTst: + addHRegUse(u, HRmRead, i->ARMin.CmpOrTst.argL); + addRegUsage_ARMRI84(u, i->ARMin.CmpOrTst.argR); + return; + case ARMin_Mov: + addHRegUse(u, HRmWrite, i->ARMin.Mov.dst); + addRegUsage_ARMRI84(u, i->ARMin.Mov.src); + return; + case ARMin_Imm32: + addHRegUse(u, HRmWrite, i->ARMin.Imm32.dst); + return; + case ARMin_LdSt32: + addRegUsage_ARMAMode1(u, i->ARMin.LdSt32.amode); + if (i->ARMin.LdSt32.isLoad) { + addHRegUse(u, HRmWrite, i->ARMin.LdSt32.rD); + } else { + addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD); + } + return; + case ARMin_LdSt16: + addRegUsage_ARMAMode2(u, i->ARMin.LdSt16.amode); + if (i->ARMin.LdSt16.isLoad) { + addHRegUse(u, HRmWrite, i->ARMin.LdSt16.rD); + } else { + addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD); + } + return; + case ARMin_LdSt8U: + addRegUsage_ARMAMode1(u, i->ARMin.LdSt8U.amode); + if (i->ARMin.LdSt8U.isLoad) { + addHRegUse(u, HRmWrite, i->ARMin.LdSt8U.rD); + } else { + addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD); + } + return; + case ARMin_Ld8S: + goto unhandled; + case ARMin_Goto: + /* reads the reg holding the next guest addr */ + addHRegUse(u, HRmRead, i->ARMin.Goto.gnext); + /* writes it to the standard integer return register */ + addHRegUse(u, HRmWrite, hregARM_R0()); + /* possibly messes with the baseblock pointer */ + if (i->ARMin.Goto.jk != Ijk_Boring + && i->ARMin.Goto.jk != Ijk_Call + && i->ARMin.Goto.jk != Ijk_Ret) + /* note, this is irrelevant since r8 is not actually + available to the allocator. But still .. */ + addHRegUse(u, HRmWrite, hregARM_R8()); + return; + case ARMin_CMov: + addHRegUse(u, HRmWrite, i->ARMin.CMov.dst); + addHRegUse(u, HRmRead, i->ARMin.CMov.dst); + addRegUsage_ARMRI84(u, i->ARMin.CMov.src); + return; + case ARMin_Call: + /* logic and comments copied/modified from x86 back end */ + /* This is a bit subtle. */ + /* First off, claim it trashes all the caller-saved regs + which fall within the register allocator's jurisdiction. + These I believe to be r0,1,2,3. If it turns out that r9 + is also caller-saved, then we'll have to add that here + too. */ + addHRegUse(u, HRmWrite, hregARM_R0()); + addHRegUse(u, HRmWrite, hregARM_R1()); + addHRegUse(u, HRmWrite, hregARM_R2()); + addHRegUse(u, HRmWrite, hregARM_R3()); + /* Now we have to state any parameter-carrying registers + which might be read. This depends on nArgRegs. */ + switch (i->ARMin.Call.nArgRegs) { + case 4: addHRegUse(u, HRmRead, hregARM_R3()); /*fallthru*/ + case 3: addHRegUse(u, HRmRead, hregARM_R2()); /*fallthru*/ + case 2: addHRegUse(u, HRmRead, hregARM_R1()); /*fallthru*/ + case 1: addHRegUse(u, HRmRead, hregARM_R0()); break; + case 0: break; + default: vpanic("getRegUsage_ARM:Call:regparms"); + } + /* Finally, there is the issue that the insn trashes a + register because the literal target address has to be + loaded into a register. Fortunately, for the nArgRegs= + 0/1/2/3 case, we can use r0, r1, r2 or r3 respectively, so + this does not cause any further damage. For the + nArgRegs=4 case, we'll have to choose another register + arbitrarily since all the caller saved regs are used for + parameters, and so we might as well choose r11. + */ + if (i->ARMin.Call.nArgRegs == 4) + addHRegUse(u, HRmWrite, hregARM_R11()); + /* Upshot of this is that the assembler really must observe + the here-stated convention of which register to use as an + address temporary, depending on nArgRegs: 0==r0, + 1==r1, 2==r2, 3==r3, 4==r11 */ + return; + case ARMin_Mul: + addHRegUse(u, HRmRead, hregARM_R2()); + addHRegUse(u, HRmRead, hregARM_R3()); + addHRegUse(u, HRmWrite, hregARM_R0()); + if (i->ARMin.Mul.op != ARMmul_PLAIN) + addHRegUse(u, HRmWrite, hregARM_R1()); + return; + case ARMin_LdrEX: + addHRegUse(u, HRmWrite, hregARM_R0()); + addHRegUse(u, HRmRead, hregARM_R1()); + return; + case ARMin_StrEX: + addHRegUse(u, HRmWrite, hregARM_R0()); + addHRegUse(u, HRmRead, hregARM_R1()); + addHRegUse(u, HRmRead, hregARM_R2()); + return; + case ARMin_VLdStD: + addRegUsage_ARMAModeV(u, i->ARMin.VLdStD.amode); + if (i->ARMin.VLdStD.isLoad) { + addHRegUse(u, HRmWrite, i->ARMin.VLdStD.dD); + } else { + addHRegUse(u, HRmRead, i->ARMin.VLdStD.dD); + } + return; + case ARMin_VLdStS: + addRegUsage_ARMAModeV(u, i->ARMin.VLdStS.amode); + if (i->ARMin.VLdStS.isLoad) { + addHRegUse(u, HRmWrite, i->ARMin.VLdStS.fD); + } else { + addHRegUse(u, HRmRead, i->ARMin.VLdStS.fD); + } + return; + case ARMin_VAluD: + addHRegUse(u, HRmWrite, i->ARMin.VAluD.dst); + addHRegUse(u, HRmRead, i->ARMin.VAluD.argL); + addHRegUse(u, HRmRead, i->ARMin.VAluD.argR); + return; + case ARMin_VAluS: + addHRegUse(u, HRmWrite, i->ARMin.VAluS.dst); + addHRegUse(u, HRmRead, i->ARMin.VAluS.argL); + addHRegUse(u, HRmRead, i->ARMin.VAluS.argR); + return; + case ARMin_VUnaryD: + addHRegUse(u, HRmWrite, i->ARMin.VUnaryD.dst); + addHRegUse(u, HRmRead, i->ARMin.VUnaryD.src); + return; + case ARMin_VUnaryS: + addHRegUse(u, HRmWrite, i->ARMin.VUnaryS.dst); + addHRegUse(u, HRmRead, i->ARMin.VUnaryS.src); + return; + case ARMin_VCmpD: + addHRegUse(u, HRmRead, i->ARMin.VCmpD.argL); + addHRegUse(u, HRmRead, i->ARMin.VCmpD.argR); + return; + case ARMin_VCMovD: + addHRegUse(u, HRmWrite, i->ARMin.VCMovD.dst); + addHRegUse(u, HRmRead, i->ARMin.VCMovD.dst); + addHRegUse(u, HRmRead, i->ARMin.VCMovD.src); + return; + case ARMin_VCMovS: + addHRegUse(u, HRmWrite, i->ARMin.VCMovS.dst); + addHRegUse(u, HRmRead, i->ARMin.VCMovS.dst); + addHRegUse(u, HRmRead, i->ARMin.VCMovS.src); + return; + case ARMin_VCvtSD: + addHRegUse(u, HRmWrite, i->ARMin.VCvtSD.dst); + addHRegUse(u, HRmRead, i->ARMin.VCvtSD.src); + return; + case ARMin_VXferD: + if (i->ARMin.VXferD.toD) { + addHRegUse(u, HRmWrite, i->ARMin.VXferD.dD); + addHRegUse(u, HRmRead, i->ARMin.VXferD.rHi); + addHRegUse(u, HRmRead, i->ARMin.VXferD.rLo); + } else { + addHRegUse(u, HRmRead, i->ARMin.VXferD.dD); + addHRegUse(u, HRmWrite, i->ARMin.VXferD.rHi); + addHRegUse(u, HRmWrite, i->ARMin.VXferD.rLo); + } + return; + case ARMin_VXferS: + if (i->ARMin.VXferS.toS) { + addHRegUse(u, HRmWrite, i->ARMin.VXferS.fD); + addHRegUse(u, HRmRead, i->ARMin.VXferS.rLo); + } else { + addHRegUse(u, HRmRead, i->ARMin.VXferS.fD); + addHRegUse(u, HRmWrite, i->ARMin.VXferS.rLo); + } + return; + case ARMin_VCvtID: + addHRegUse(u, HRmWrite, i->ARMin.VCvtID.dst); + addHRegUse(u, HRmRead, i->ARMin.VCvtID.src); + return; + case ARMin_FPSCR: + if (i->ARMin.FPSCR.toFPSCR) + addHRegUse(u, HRmRead, i->ARMin.FPSCR.iReg); + else + addHRegUse(u, HRmWrite, i->ARMin.FPSCR.iReg); + return; + case ARMin_MFence: + return; + case ARMin_NLdStQ: + if (i->ARMin.NLdStQ.isLoad) + addHRegUse(u, HRmWrite, i->ARMin.NLdStQ.dQ); + else + addHRegUse(u, HRmRead, i->ARMin.NLdStQ.dQ); + addRegUsage_ARMAModeN(u, i->ARMin.NLdStQ.amode); + return; + case ARMin_NLdStD: + if (i->ARMin.NLdStD.isLoad) + addHRegUse(u, HRmWrite, i->ARMin.NLdStD.dD); + else + addHRegUse(u, HRmRead, i->ARMin.NLdStD.dD); + addRegUsage_ARMAModeN(u, i->ARMin.NLdStD.amode); + return; + case ARMin_NUnary: + addHRegUse(u, HRmWrite, i->ARMin.NUnary.dst); + addHRegUse(u, HRmRead, i->ARMin.NUnary.src); + return; + case ARMin_NUnaryS: + addHRegUse(u, HRmWrite, i->ARMin.NUnaryS.dst->reg); + addHRegUse(u, HRmRead, i->ARMin.NUnaryS.src->reg); + return; + case ARMin_NShift: + addHRegUse(u, HRmWrite, i->ARMin.NShift.dst); + addHRegUse(u, HRmRead, i->ARMin.NShift.argL); + addHRegUse(u, HRmRead, i->ARMin.NShift.argR); + return; + case ARMin_NDual: + addHRegUse(u, HRmWrite, i->ARMin.NDual.arg1); + addHRegUse(u, HRmWrite, i->ARMin.NDual.arg2); + addHRegUse(u, HRmRead, i->ARMin.NDual.arg1); + addHRegUse(u, HRmRead, i->ARMin.NDual.arg2); + return; + case ARMin_NBinary: + addHRegUse(u, HRmWrite, i->ARMin.NBinary.dst); + /* TODO: sometimes dst is also being read! */ + // XXX fix this + addHRegUse(u, HRmRead, i->ARMin.NBinary.argL); + addHRegUse(u, HRmRead, i->ARMin.NBinary.argR); + return; + case ARMin_NeonImm: + addHRegUse(u, HRmWrite, i->ARMin.NeonImm.dst); + return; + case ARMin_NCMovQ: + addHRegUse(u, HRmWrite, i->ARMin.NCMovQ.dst); + addHRegUse(u, HRmRead, i->ARMin.NCMovQ.dst); + addHRegUse(u, HRmRead, i->ARMin.NCMovQ.src); + return; + case ARMin_Add32: + addHRegUse(u, HRmWrite, i->ARMin.Add32.rD); + addHRegUse(u, HRmRead, i->ARMin.Add32.rN); + return; + unhandled: + default: + ppARMInstr(i); + vpanic("getRegUsage_ARMInstr"); + } +} + + +void mapRegs_ARMInstr ( HRegRemap* m, ARMInstr* i, Bool mode64 ) +{ + vassert(mode64 == False); + switch (i->tag) { + case ARMin_Alu: + i->ARMin.Alu.dst = lookupHRegRemap(m, i->ARMin.Alu.dst); + i->ARMin.Alu.argL = lookupHRegRemap(m, i->ARMin.Alu.argL); + mapRegs_ARMRI84(m, i->ARMin.Alu.argR); + return; + case ARMin_Shift: + i->ARMin.Shift.dst = lookupHRegRemap(m, i->ARMin.Shift.dst); + i->ARMin.Shift.argL = lookupHRegRemap(m, i->ARMin.Shift.argL); + mapRegs_ARMRI5(m, i->ARMin.Shift.argR); + return; + case ARMin_Unary: + i->ARMin.Unary.dst = lookupHRegRemap(m, i->ARMin.Unary.dst); + i->ARMin.Unary.src = lookupHRegRemap(m, i->ARMin.Unary.src); + return; + case ARMin_CmpOrTst: + i->ARMin.CmpOrTst.argL = lookupHRegRemap(m, i->ARMin.CmpOrTst.argL); + mapRegs_ARMRI84(m, i->ARMin.CmpOrTst.argR); + return; + case ARMin_Mov: + i->ARMin.Mov.dst = lookupHRegRemap(m, i->ARMin.Mov.dst); + mapRegs_ARMRI84(m, i->ARMin.Mov.src); + return; + case ARMin_Imm32: + i->ARMin.Imm32.dst = lookupHRegRemap(m, i->ARMin.Imm32.dst); + return; + case ARMin_LdSt32: + i->ARMin.LdSt32.rD = lookupHRegRemap(m, i->ARMin.LdSt32.rD); + mapRegs_ARMAMode1(m, i->ARMin.LdSt32.amode); + return; + case ARMin_LdSt16: + i->ARMin.LdSt16.rD = lookupHRegRemap(m, i->ARMin.LdSt16.rD); + mapRegs_ARMAMode2(m, i->ARMin.LdSt16.amode); + return; + case ARMin_LdSt8U: + i->ARMin.LdSt8U.rD = lookupHRegRemap(m, i->ARMin.LdSt8U.rD); + mapRegs_ARMAMode1(m, i->ARMin.LdSt8U.amode); + return; + case ARMin_Ld8S: + goto unhandled; + case ARMin_Goto: + i->ARMin.Goto.gnext = lookupHRegRemap(m, i->ARMin.Goto.gnext); + return; + case ARMin_CMov: + i->ARMin.CMov.dst = lookupHRegRemap(m, i->ARMin.CMov.dst); + mapRegs_ARMRI84(m, i->ARMin.CMov.src); + return; + case ARMin_Call: + return; + case ARMin_Mul: + return; + case ARMin_LdrEX: + return; + case ARMin_StrEX: + return; + case ARMin_VLdStD: + i->ARMin.VLdStD.dD = lookupHRegRemap(m, i->ARMin.VLdStD.dD); + mapRegs_ARMAModeV(m, i->ARMin.VLdStD.amode); + return; + case ARMin_VLdStS: + i->ARMin.VLdStS.fD = lookupHRegRemap(m, i->ARMin.VLdStS.fD); + mapRegs_ARMAModeV(m, i->ARMin.VLdStS.amode); + return; + case ARMin_VAluD: + i->ARMin.VAluD.dst = lookupHRegRemap(m, i->ARMin.VAluD.dst); + i->ARMin.VAluD.argL = lookupHRegRemap(m, i->ARMin.VAluD.argL); + i->ARMin.VAluD.argR = lookupHRegRemap(m, i->ARMin.VAluD.argR); + return; + case ARMin_VAluS: + i->ARMin.VAluS.dst = lookupHRegRemap(m, i->ARMin.VAluS.dst); + i->ARMin.VAluS.argL = lookupHRegRemap(m, i->ARMin.VAluS.argL); + i->ARMin.VAluS.argR = lookupHRegRemap(m, i->ARMin.VAluS.argR); + return; + case ARMin_VUnaryD: + i->ARMin.VUnaryD.dst = lookupHRegRemap(m, i->ARMin.VUnaryD.dst); + i->ARMin.VUnaryD.src = lookupHRegRemap(m, i->ARMin.VUnaryD.src); + return; + case ARMin_VUnaryS: + i->ARMin.VUnaryS.dst = lookupHRegRemap(m, i->ARMin.VUnaryS.dst); + i->ARMin.VUnaryS.src = lookupHRegRemap(m, i->ARMin.VUnaryS.src); + return; + case ARMin_VCmpD: + i->ARMin.VCmpD.argL = lookupHRegRemap(m, i->ARMin.VCmpD.argL); + i->ARMin.VCmpD.argR = lookupHRegRemap(m, i->ARMin.VCmpD.argR); + return; + case ARMin_VCMovD: + i->ARMin.VCMovD.dst = lookupHRegRemap(m, i->ARMin.VCMovD.dst); + i->ARMin.VCMovD.src = lookupHRegRemap(m, i->ARMin.VCMovD.src); + return; + case ARMin_VCMovS: + i->ARMin.VCMovS.dst = lookupHRegRemap(m, i->ARMin.VCMovS.dst); + i->ARMin.VCMovS.src = lookupHRegRemap(m, i->ARMin.VCMovS.src); + return; + case ARMin_VCvtSD: + i->ARMin.VCvtSD.dst = lookupHRegRemap(m, i->ARMin.VCvtSD.dst); + i->ARMin.VCvtSD.src = lookupHRegRemap(m, i->ARMin.VCvtSD.src); + return; + case ARMin_VXferD: + i->ARMin.VXferD.dD = lookupHRegRemap(m, i->ARMin.VXferD.dD); + i->ARMin.VXferD.rHi = lookupHRegRemap(m, i->ARMin.VXferD.rHi); + i->ARMin.VXferD.rLo = lookupHRegRemap(m, i->ARMin.VXferD.rLo); + return; + case ARMin_VXferS: + i->ARMin.VXferS.fD = lookupHRegRemap(m, i->ARMin.VXferS.fD); + i->ARMin.VXferS.rLo = lookupHRegRemap(m, i->ARMin.VXferS.rLo); + return; + case ARMin_VCvtID: + i->ARMin.VCvtID.dst = lookupHRegRemap(m, i->ARMin.VCvtID.dst); + i->ARMin.VCvtID.src = lookupHRegRemap(m, i->ARMin.VCvtID.src); + return; + case ARMin_FPSCR: + i->ARMin.FPSCR.iReg = lookupHRegRemap(m, i->ARMin.FPSCR.iReg); + return; + case ARMin_MFence: + return; + case ARMin_NLdStQ: + i->ARMin.NLdStQ.dQ = lookupHRegRemap(m, i->ARMin.NLdStQ.dQ); + mapRegs_ARMAModeN(m, i->ARMin.NLdStQ.amode); + return; + case ARMin_NLdStD: + i->ARMin.NLdStD.dD = lookupHRegRemap(m, i->ARMin.NLdStD.dD); + mapRegs_ARMAModeN(m, i->ARMin.NLdStD.amode); + return; + case ARMin_NUnary: + i->ARMin.NUnary.src = lookupHRegRemap(m, i->ARMin.NUnary.src); + i->ARMin.NUnary.dst = lookupHRegRemap(m, i->ARMin.NUnary.dst); + return; + case ARMin_NUnaryS: + i->ARMin.NUnaryS.src->reg + = lookupHRegRemap(m, i->ARMin.NUnaryS.src->reg); + i->ARMin.NUnaryS.dst->reg + = lookupHRegRemap(m, i->ARMin.NUnaryS.dst->reg); + return; + case ARMin_NShift: + i->ARMin.NShift.dst = lookupHRegRemap(m, i->ARMin.NShift.dst); + i->ARMin.NShift.argL = lookupHRegRemap(m, i->ARMin.NShift.argL); + i->ARMin.NShift.argR = lookupHRegRemap(m, i->ARMin.NShift.argR); + return; + case ARMin_NDual: + i->ARMin.NDual.arg1 = lookupHRegRemap(m, i->ARMin.NDual.arg1); + i->ARMin.NDual.arg2 = lookupHRegRemap(m, i->ARMin.NDual.arg2); + return; + case ARMin_NBinary: + i->ARMin.NBinary.argL = lookupHRegRemap(m, i->ARMin.NBinary.argL); + i->ARMin.NBinary.argR = lookupHRegRemap(m, i->ARMin.NBinary.argR); + i->ARMin.NBinary.dst = lookupHRegRemap(m, i->ARMin.NBinary.dst); + return; + case ARMin_NeonImm: + i->ARMin.NeonImm.dst = lookupHRegRemap(m, i->ARMin.NeonImm.dst); + return; + case ARMin_NCMovQ: + i->ARMin.NCMovQ.dst = lookupHRegRemap(m, i->ARMin.NCMovQ.dst); + i->ARMin.NCMovQ.src = lookupHRegRemap(m, i->ARMin.NCMovQ.src); + return; + case ARMin_Add32: + i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD); + i->ARMin.Add32.rN = lookupHRegRemap(m, i->ARMin.Add32.rN); + unhandled: + default: + ppARMInstr(i); + vpanic("mapRegs_ARMInstr"); + } } /* Figure out if i represents a reg-reg move, and if so assign the source and destination to *src and *dst. If in doubt say No. Used by the register allocator to do move coalescing. */ -Bool isMove_ARMInstr ( ARMInstr* i, HReg* src, HReg* dst ) { - return False; // No optimisations for now... +Bool isMove_ARMInstr ( ARMInstr* i, HReg* src, HReg* dst ) +{ + /* Moves between integer regs */ + switch (i->tag) { + case ARMin_Mov: + if (i->ARMin.Mov.src->tag == ARMri84_R) { + *src = i->ARMin.Mov.src->ARMri84.R.reg; + *dst = i->ARMin.Mov.dst; + return True; + } + break; + case ARMin_VUnaryD: + if (i->ARMin.VUnaryD.op == ARMvfpu_COPY) { + *src = i->ARMin.VUnaryD.src; + *dst = i->ARMin.VUnaryD.dst; + return True; + } + break; + case ARMin_VUnaryS: + if (i->ARMin.VUnaryS.op == ARMvfpu_COPY) { + *src = i->ARMin.VUnaryS.src; + *dst = i->ARMin.VUnaryS.dst; + return True; + } + break; + default: + break; + } + + // todo: float, vector moves + return False; } -/* Generate x86 spill/reload instructions under the direction of the +/* Generate arm spill/reload instructions under the direction of the register allocator. Note it's critical these don't write the condition codes. */ -ARMInstr* genSpill_ARM ( HReg rreg, Int offsetB ) { -// ARMAMode1* am; +void genSpill_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) +{ + HRegClass rclass; vassert(offsetB >= 0); vassert(!hregIsVirtual(rreg)); - - switch (hregClass(rreg)) { - - default: - ppHRegClass(hregClass(rreg)); - vpanic("genSpill_ARM: unimplemented regclass"); + vassert(mode64 == False); + *i1 = *i2 = NULL; + rclass = hregClass(rreg); + switch (rclass) { + case HRcInt32: + vassert(offsetB <= 4095); + *i1 = ARMInstr_LdSt32( False/*!isLoad*/, + rreg, + ARMAMode1_RI(hregARM_R8(), offsetB) ); + return; + case HRcFlt32: + case HRcFlt64: { + HReg r8 = hregARM_R8(); /* baseblock */ + HReg r12 = hregARM_R12(); /* spill temp */ + HReg base = r8; + vassert(0 == (offsetB & 3)); + if (offsetB >= 1024) { + Int offsetKB = offsetB / 1024; + /* r12 = r8 + (1024 * offsetKB) */ + *i1 = ARMInstr_Alu(ARMalu_ADD, r12, r8, + ARMRI84_I84(offsetKB, 11)); + offsetB -= (1024 * offsetKB); + base = r12; + } + vassert(offsetB <= 1020); + if (rclass == HRcFlt32) { + *i2 = ARMInstr_VLdStS( False/*!isLoad*/, + rreg, + mkARMAModeV(base, offsetB) ); + } else { + *i2 = ARMInstr_VLdStD( False/*!isLoad*/, + rreg, + mkARMAModeV(base, offsetB) ); + } + return; + } + case HRcVec128: { + HReg r8 = hregARM_R8(); + HReg r12 = hregARM_R12(); + *i1 = ARMInstr_Add32(r12, r8, offsetB); + *i2 = ARMInstr_NLdStQ(False, rreg, mkARMAModeN_R(r12)); + return; + } + default: + ppHRegClass(rclass); + vpanic("genSpill_ARM: unimplemented regclass"); } } -ARMInstr* genReload_ARM ( HReg rreg, Int offsetB ) { -// ARMAMode1* am; +void genReload_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) +{ + HRegClass rclass; vassert(offsetB >= 0); vassert(!hregIsVirtual(rreg)); - - switch (hregClass(rreg)) { - - default: - ppHRegClass(hregClass(rreg)); - vpanic("genReload_ARM: unimplemented regclass"); + vassert(mode64 == False); + *i1 = *i2 = NULL; + rclass = hregClass(rreg); + switch (rclass) { + case HRcInt32: + vassert(offsetB <= 4095); + *i1 = ARMInstr_LdSt32( True/*isLoad*/, + rreg, + ARMAMode1_RI(hregARM_R8(), offsetB) ); + return; + case HRcFlt32: + case HRcFlt64: { + HReg r8 = hregARM_R8(); /* baseblock */ + HReg r12 = hregARM_R12(); /* spill temp */ + HReg base = r8; + vassert(0 == (offsetB & 3)); + if (offsetB >= 1024) { + Int offsetKB = offsetB / 1024; + /* r12 = r8 + (1024 * offsetKB) */ + *i1 = ARMInstr_Alu(ARMalu_ADD, r12, r8, + ARMRI84_I84(offsetKB, 11)); + offsetB -= (1024 * offsetKB); + base = r12; + } + vassert(offsetB <= 1020); + if (rclass == HRcFlt32) { + *i2 = ARMInstr_VLdStS( True/*isLoad*/, + rreg, + mkARMAModeV(base, offsetB) ); + } else { + *i2 = ARMInstr_VLdStD( True/*isLoad*/, + rreg, + mkARMAModeV(base, offsetB) ); + } + return; + } + case HRcVec128: { + HReg r8 = hregARM_R8(); + HReg r12 = hregARM_R12(); + *i1 = ARMInstr_Add32(r12, r8, offsetB); + *i2 = ARMInstr_NLdStQ(True, rreg, mkARMAModeN_R(r12)); + return; + } + default: + ppHRegClass(rclass); + vpanic("genReload_ARM: unimplemented regclass"); } } @@ -710,43 +2465,1632 @@ ARMInstr* genReload_ARM ( HReg rreg, Int offsetB ) { Note that buf is not the insn's final place, and therefore it is imperative to emit position-independent code. */ -Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr* i ) { -// UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; - -// UInt xtra; - UChar* p = &buf[0]; -// UChar* ptmp; - vassert(nbuf >= 32); - - switch (i->tag) { - case ARMin_DPCmp: - case ARMin_DPInstr1: - case ARMin_DPInstr2: - case ARMin_LoadUB: - case ARMin_StoreB: - case ARMin_LoadW: - case ARMin_StoreW: - case ARMin_LoadSB: - case ARMin_LoadUH: - case ARMin_LoadSH: - case ARMin_StoreH: - case ARMin_Branch: - case ARMin_BranchL: - case ARMin_Literal: - default: - goto bad; +static inline UChar iregNo ( HReg r ) +{ + UInt n; + vassert(hregClass(r) == HRcInt32); + vassert(!hregIsVirtual(r)); + n = hregNumber(r); + vassert(n <= 15); + return toUChar(n); +} + +static inline UChar dregNo ( HReg r ) +{ + UInt n; + if (hregClass(r) != HRcFlt64) + ppHRegClass(hregClass(r)); + vassert(hregClass(r) == HRcFlt64); + vassert(!hregIsVirtual(r)); + n = hregNumber(r); + vassert(n <= 31); + return toUChar(n); +} + +static inline UChar fregNo ( HReg r ) +{ + UInt n; + vassert(hregClass(r) == HRcFlt32); + vassert(!hregIsVirtual(r)); + n = hregNumber(r); + vassert(n <= 31); + return toUChar(n); +} + +static inline UChar qregNo ( HReg r ) +{ + UInt n; + vassert(hregClass(r) == HRcVec128); + vassert(!hregIsVirtual(r)); + n = hregNumber(r); + vassert(n <= 15); + return toUChar(n); +} + +#define BITS4(zzb3,zzb2,zzb1,zzb0) \ + (((zzb3) << 3) | ((zzb2) << 2) | ((zzb1) << 1) | (zzb0)) +#define X0000 BITS4(0,0,0,0) +#define X0001 BITS4(0,0,0,1) +#define X0010 BITS4(0,0,1,0) +#define X0011 BITS4(0,0,1,1) +#define X0100 BITS4(0,1,0,0) +#define X0101 BITS4(0,1,0,1) +#define X0110 BITS4(0,1,1,0) +#define X0111 BITS4(0,1,1,1) +#define X1000 BITS4(1,0,0,0) +#define X1001 BITS4(1,0,0,1) +#define X1010 BITS4(1,0,1,0) +#define X1011 BITS4(1,0,1,1) +#define X1100 BITS4(1,1,0,0) +#define X1101 BITS4(1,1,0,1) +#define X1110 BITS4(1,1,1,0) +#define X1111 BITS4(1,1,1,1) + +#define XXXXX___(zzx7,zzx6,zzx5,zzx4,zzx3) \ + ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ + (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ + (((zzx3) & 0xF) << 12)) + +#define XXXXXX__(zzx7,zzx6,zzx5,zzx4,zzx3,zzx2) \ + ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ + (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ + (((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8)) + +#define XXXXX__X(zzx7,zzx6,zzx5,zzx4,zzx3,zzx0) \ + ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ + (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ + (((zzx3) & 0xF) << 12) | (((zzx0) & 0xF) << 0)) + +#define XXX___XX(zzx7,zzx6,zzx5,zzx1,zzx0) \ + ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ + (((zzx5) & 0xF) << 20) | (((zzx1) & 0xF) << 4) | \ + (((zzx0) & 0xF) << 0)) + +#define XXXXXXXX(zzx7,zzx6,zzx5,zzx4,zzx3,zzx2,zzx1,zzx0) \ + ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ + (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ + (((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8) | \ + (((zzx1) & 0xF) << 4) | (((zzx0) & 0xF) << 0)) + +/* Generate a skeletal insn that involves an a RI84 shifter operand. + Returns a word which is all zeroes apart from bits 25 and 11..0, + since it is those that encode the shifter operand (at least to the + extent that we care about it.) */ +static UInt skeletal_RI84 ( ARMRI84* ri ) +{ + UInt instr; + if (ri->tag == ARMri84_I84) { + vassert(0 == (ri->ARMri84.I84.imm4 & ~0x0F)); + vassert(0 == (ri->ARMri84.I84.imm8 & ~0xFF)); + instr = 1 << 25; + instr |= (ri->ARMri84.I84.imm4 << 8); + instr |= ri->ARMri84.I84.imm8; + } else { + instr = 0 << 25; + instr |= iregNo(ri->ARMri84.R.reg); + } + return instr; +} + +/* Ditto for RI5. Resulting word is zeroes apart from bit 4 and bits + 11..7. */ +static UInt skeletal_RI5 ( ARMRI5* ri ) +{ + UInt instr; + if (ri->tag == ARMri5_I5) { + UInt imm5 = ri->ARMri5.I5.imm5; + vassert(imm5 >= 1 && imm5 <= 31); + instr = 0 << 4; + instr |= imm5 << 7; + } else { + instr = 1 << 4; + instr |= iregNo(ri->ARMri5.R.reg) << 8; + } + return instr; +} + + +/* Get an immediate into a register, using only that + register. (very lame..) */ +static UInt* imm32_to_iregNo ( UInt* p, Int rD, UInt imm32 ) +{ + UInt instr; + vassert(rD >= 0 && rD <= 14); // r15 not good to mess with! +#if 0 + if (0 == (imm32 & ~0xFF)) { + /* mov with a immediate shifter operand of (0, imm32) (??) */ + instr = XXXXXX__(X1110,X0011,X1010,X0000,rD,X0000); + instr |= imm32; + *p++ = instr; + } else { + // this is very bad; causes Dcache pollution + // ldr rD, [pc] + instr = XXXXX___(X1110,X0101,X1001,X1111,rD); + *p++ = instr; + // b .+8 + instr = 0xEA000000; + *p++ = instr; + // .word imm32 + *p++ = imm32; + } +#else + if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) { + /* Generate movw rD, #low16. Then, if the high 16 are + nonzero, generate movt rD, #high16. */ + UInt lo16 = imm32 & 0xFFFF; + UInt hi16 = (imm32 >> 16) & 0xFFFF; + instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD, + (lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF, + lo16 & 0xF); + *p++ = instr; + if (hi16 != 0) { + instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD, + (hi16 >> 8) & 0xF, (hi16 >> 4) & 0xF, + hi16 & 0xF); + *p++ = instr; + } + } else { + UInt imm, rot; + UInt op = X1010; + UInt rN = 0; + if ((imm32 & 0xFF) || (imm32 == 0)) { + imm = imm32 & 0xFF; + rot = 0; + instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF); + *p++ = instr; + op = X1000; + rN = rD; + } + if (imm32 & 0xFF000000) { + imm = (imm32 >> 24) & 0xFF; + rot = 4; + instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF); + *p++ = instr; + op = X1000; + rN = rD; + } + if (imm32 & 0xFF0000) { + imm = (imm32 >> 16) & 0xFF; + rot = 8; + instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF); + *p++ = instr; + op = X1000; + rN = rD; + } + if (imm32 & 0xFF00) { + imm = (imm32 >> 8) & 0xFF; + rot = 12; + instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF); + *p++ = instr; + op = X1000; + rN = rD; + } + } +#endif + return p; +} + + +Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr* i, + Bool mode64, void* dispatch ) +{ + UInt* p = (UInt*)buf; + vassert(nbuf >= 32); + vassert(mode64 == False); + vassert(0 == (((HWord)buf) & 3)); + /* since we branch to lr(r13) to get back to dispatch: */ + vassert(dispatch == NULL); + + switch (i->tag) { + case ARMin_Alu: { + UInt instr, subopc; + UInt rD = iregNo(i->ARMin.Alu.dst); + UInt rN = iregNo(i->ARMin.Alu.argL); + ARMRI84* argR = i->ARMin.Alu.argR; + switch (i->ARMin.Alu.op) { + case ARMalu_ADDS: /* fallthru */ + case ARMalu_ADD: subopc = X0100; break; + case ARMalu_ADC: subopc = X0101; break; + case ARMalu_SUBS: /* fallthru */ + case ARMalu_SUB: subopc = X0010; break; + case ARMalu_SBC: subopc = X0110; break; + case ARMalu_AND: subopc = X0000; break; + case ARMalu_BIC: subopc = X1110; break; + case ARMalu_OR: subopc = X1100; break; + case ARMalu_XOR: subopc = X0001; break; + default: goto bad; + } + instr = skeletal_RI84(argR); + instr |= XXXXX___(X1110, (1 & (subopc >> 3)), + (subopc << 1) & 0xF, rN, rD); + if (i->ARMin.Alu.op == ARMalu_ADDS + || i->ARMin.Alu.op == ARMalu_SUBS) { + instr |= 1<<20; /* set the S bit */ + } + *p++ = instr; + goto done; + } + case ARMin_Shift: { + UInt instr, subopc; + HReg rD = iregNo(i->ARMin.Shift.dst); + HReg rM = iregNo(i->ARMin.Shift.argL); + ARMRI5* argR = i->ARMin.Shift.argR; + switch (i->ARMin.Shift.op) { + case ARMsh_SHL: subopc = X0000; break; + case ARMsh_SHR: subopc = X0001; break; + case ARMsh_SAR: subopc = X0010; break; + default: goto bad; + } + instr = skeletal_RI5(argR); + instr |= XXXXX__X(X1110,X0001,X1010,X0000,rD, /* _ _ */ rM); + instr |= (subopc & 3) << 5; + *p++ = instr; + goto done; + } + case ARMin_Unary: { + UInt instr; + HReg rDst = iregNo(i->ARMin.Unary.dst); + HReg rSrc = iregNo(i->ARMin.Unary.src); + switch (i->ARMin.Unary.op) { + case ARMun_CLZ: + instr = XXXXXXXX(X1110,X0001,X0110,X1111, + rDst,X1111,X0001,rSrc); + *p++ = instr; + goto done; + case ARMun_NEG: /* RSB rD,rS,#0 */ + instr = XXXXX___(X1110,0x2,0x6,rSrc,rDst); + *p++ = instr; + goto done; + case ARMun_NOT: { + UInt subopc = X1111; /* MVN */ + instr = rSrc; + instr |= XXXXX___(X1110, (1 & (subopc >> 3)), + (subopc << 1) & 0xF, 0, rDst); + *p++ = instr; + goto done; + } + default: + break; + } + goto bad; + } + case ARMin_CmpOrTst: { + UInt instr = skeletal_RI84(i->ARMin.CmpOrTst.argR); + UInt subopc = i->ARMin.CmpOrTst.isCmp ? X1010 : X1000; + UInt SBZ = 0; + instr |= XXXXX___(X1110, (1 & (subopc >> 3)), + ((subopc << 1) & 0xF) | 1, + i->ARMin.CmpOrTst.argL, SBZ ); + *p++ = instr; + goto done; + } + case ARMin_Mov: { + UInt instr = skeletal_RI84(i->ARMin.Mov.src); + UInt subopc = X1101; /* MOV */ + UInt SBZ = 0; + instr |= XXXXX___(X1110, (1 & (subopc >> 3)), + (subopc << 1) & 0xF, SBZ, i->ARMin.Mov.dst); + *p++ = instr; + goto done; + } + case ARMin_Imm32: { + p = imm32_to_iregNo( (UInt*)p, iregNo(i->ARMin.Imm32.dst), + i->ARMin.Imm32.imm32 ); + goto done; + } + case ARMin_LdSt32: + case ARMin_LdSt8U: { + UInt bL, bB; + HReg rD; + ARMAMode1* am; + if (i->tag == ARMin_LdSt32) { + bB = 0; + bL = i->ARMin.LdSt32.isLoad ? 1 : 0; + am = i->ARMin.LdSt32.amode; + rD = i->ARMin.LdSt32.rD; + } else { + bB = 1; + bL = i->ARMin.LdSt8U.isLoad ? 1 : 0; + am = i->ARMin.LdSt8U.amode; + rD = i->ARMin.LdSt8U.rD; + } + if (am->tag == ARMam1_RI) { + Int simm12; + UInt instr, bP; + if (am->ARMam1.RI.simm13 < 0) { + bP = 0; + simm12 = -am->ARMam1.RI.simm13; + } else { + bP = 1; + simm12 = am->ARMam1.RI.simm13; + } + vassert(simm12 >= 0 && simm12 <= 4095); + instr = XXXXX___(X1110,X0101,BITS4(bP,bB,0,bL), + iregNo(am->ARMam1.RI.reg), + iregNo(rD)); + instr |= simm12; + *p++ = instr; + goto done; + } else { + // RR case + goto bad; + } + } + case ARMin_LdSt16: { + HReg rD = i->ARMin.LdSt16.rD; + UInt bS = i->ARMin.LdSt16.signedLoad ? 1 : 0; + UInt bL = i->ARMin.LdSt16.isLoad ? 1 : 0; + ARMAMode2* am = i->ARMin.LdSt16.amode; + if (am->tag == ARMam2_RI) { + HReg rN = am->ARMam2.RI.reg; + Int simm8; + UInt bP, imm8hi, imm8lo, instr; + if (am->ARMam2.RI.simm9 < 0) { + bP = 0; + simm8 = -am->ARMam2.RI.simm9; + } else { + bP = 1; + simm8 = am->ARMam2.RI.simm9; + } + vassert(simm8 >= 0 && simm8 <= 255); + imm8hi = (simm8 >> 4) & 0xF; + imm8lo = simm8 & 0xF; + vassert(!(bL == 0 && bS == 1)); // "! signed store" + /**/ if (bL == 0 && bS == 0) { + // strh + instr = XXXXXXXX(X1110,X0001, BITS4(bP,1,0,0), iregNo(rN), + iregNo(rD), imm8hi, X1011, imm8lo); + *p++ = instr; + goto done; + } + else if (bL == 1 && bS == 0) { + // ldrh + instr = XXXXXXXX(X1110,X0001, BITS4(bP,1,0,1), iregNo(rN), + iregNo(rD), imm8hi, X1011, imm8lo); + *p++ = instr; + goto done; + } + else if (bL == 1 && bS == 1) { + goto bad; + } + else vassert(0); // ill-constructed insn + } else { + // RR case + goto bad; + } + } + case ARMin_Ld8S: + goto bad; + case ARMin_Goto: { + UInt instr; + IRJumpKind jk = i->ARMin.Goto.jk; + ARMCondCode cond = i->ARMin.Goto.cond; + UInt rnext = iregNo(i->ARMin.Goto.gnext); + Int trc = -1; + switch (jk) { + case Ijk_Ret: case Ijk_Call: case Ijk_Boring: + break; /* no need to set GST in these common cases */ + case Ijk_ClientReq: + trc = VEX_TRC_JMP_CLIENTREQ; break; + case Ijk_Sys_int128: + case Ijk_Sys_int129: + case Ijk_Sys_int130: + case Ijk_Yield: + case Ijk_EmWarn: + case Ijk_MapFail: + goto unhandled_jk; + case Ijk_NoDecode: + trc = VEX_TRC_JMP_NODECODE; break; + case Ijk_TInval: + trc = VEX_TRC_JMP_TINVAL; break; + case Ijk_NoRedir: + trc = VEX_TRC_JMP_NOREDIR; break; + case Ijk_Sys_sysenter: + case Ijk_SigTRAP: + case Ijk_SigSEGV: + goto unhandled_jk; + case Ijk_Sys_syscall: + trc = VEX_TRC_JMP_SYS_SYSCALL; break; + unhandled_jk: + default: + goto bad; + } + if (trc != -1) { + // mov{cond} r8, #trc + vassert(trc >= 0 && trc <= 255); + instr = (cond << 28) | 0x03A08000 | (0xFF & (UInt)trc); + *p++ = instr; + } + // mov{cond} r0, rnext + if (rnext != 0) { + instr = (cond << 28) | 0x01A00000 | rnext; + *p++ = instr; + } + // bx{cond} r14 + instr =(cond << 28) | 0x012FFF1E; + *p++ = instr; + goto done; + } + case ARMin_CMov: { + UInt instr = skeletal_RI84(i->ARMin.CMov.src); + UInt subopc = X1101; /* MOV */ + UInt SBZ = 0; + instr |= XXXXX___(i->ARMin.CMov.cond, (1 & (subopc >> 3)), + (subopc << 1) & 0xF, SBZ, i->ARMin.CMov.dst); + *p++ = instr; + goto done; + } + case ARMin_Call: { + UInt instr; + /* Decide on a scratch reg used to hold to the call address. + This has to be done as per the comments in getRegUsage. */ + Int scratchNo; + switch (i->ARMin.Call.nArgRegs) { + case 0: scratchNo = 0; break; + case 1: scratchNo = 1; break; + case 2: scratchNo = 2; break; + case 3: scratchNo = 3; break; + case 4: scratchNo = 11; break; + default: vassert(0); + } + // r"scratchNo" = &target + p = imm32_to_iregNo( (UInt*)p, + scratchNo, (UInt)i->ARMin.Call.target ); + // blx{cond} r"scratchNo" + instr = XXX___XX(i->ARMin.Call.cond, X0001, X0010, /*___*/ + X0011, scratchNo); + instr |= 0xFFF << 8; // stick in the SBOnes + *p++ = instr; + goto done; + } + case ARMin_Mul: { + /* E0000392 mul r0, r2, r3 + E0810392 umull r0(LO), r1(HI), r2, r3 + E0C10392 smull r0(LO), r1(HI), r2, r3 + */ + switch (i->ARMin.Mul.op) { + case ARMmul_PLAIN: *p++ = 0xE0000392; goto done; + case ARMmul_ZX: *p++ = 0xE0810392; goto done; + case ARMmul_SX: *p++ = 0xE0C10392; goto done; + default: vassert(0); + } + goto bad; + } + case ARMin_LdrEX: { + /* E1910F9F ldrex r0, [r1] + E1F10F9F ldrexh r0, [r1] + E1D10F9F ldrexb r0, [r1] + */ + switch (i->ARMin.LdrEX.szB) { + case 4: *p++ = 0xE1910F9F; goto done; + //case 2: *p++ = 0xE1F10F9F; goto done; + case 1: *p++ = 0xE1D10F9F; goto done; + default: break; + } + goto bad; + } + case ARMin_StrEX: { + /* E1820F91 strex r0, r1, [r2] + E1E20F91 strexh r0, r1, [r2] + E1C20F91 strexb r0, r1, [r2] + */ + switch (i->ARMin.StrEX.szB) { + case 4: *p++ = 0xE1820F91; goto done; + //case 2: *p++ = 0xE1E20F91; goto done; + case 1: *p++ = 0xE1C20F91; goto done; + default: break; + } + goto bad; + } + case ARMin_VLdStD: { + UInt dD = dregNo(i->ARMin.VLdStD.dD); + UInt rN = iregNo(i->ARMin.VLdStD.amode->reg); + Int simm11 = i->ARMin.VLdStD.amode->simm11; + UInt off8 = simm11 >= 0 ? simm11 : ((UInt)(-simm11)); + UInt bU = simm11 >= 0 ? 1 : 0; + UInt bL = i->ARMin.VLdStD.isLoad ? 1 : 0; + UInt insn; + vassert(0 == (off8 & 3)); + off8 >>= 2; + vassert(0 == (off8 & 0xFFFFFF00)); + insn = XXXXXX__(0xE,X1101,BITS4(bU,0,0,bL),rN,dD,X1011); + insn |= off8; + *p++ = insn; + goto done; + } + case ARMin_VLdStS: { + UInt fD = fregNo(i->ARMin.VLdStS.fD); + UInt rN = iregNo(i->ARMin.VLdStS.amode->reg); + Int simm11 = i->ARMin.VLdStS.amode->simm11; + UInt off8 = simm11 >= 0 ? simm11 : ((UInt)(-simm11)); + UInt bU = simm11 >= 0 ? 1 : 0; + UInt bL = i->ARMin.VLdStS.isLoad ? 1 : 0; + UInt bD = fD & 1; + UInt insn; + vassert(0 == (off8 & 3)); + off8 >>= 2; + vassert(0 == (off8 & 0xFFFFFF00)); + insn = XXXXXX__(0xE,X1101,BITS4(bU,bD,0,bL),rN, (fD >> 1), X1010); + insn |= off8; + *p++ = insn; + goto done; + } + case ARMin_VAluD: { + UInt dN = dregNo(i->ARMin.VAluD.argL); + UInt dD = dregNo(i->ARMin.VAluD.dst); + UInt dM = dregNo(i->ARMin.VAluD.argR); + UInt pqrs = X1111; /* undefined */ + switch (i->ARMin.VAluD.op) { + case ARMvfp_ADD: pqrs = X0110; break; + case ARMvfp_SUB: pqrs = X0111; break; + case ARMvfp_MUL: pqrs = X0100; break; + case ARMvfp_DIV: pqrs = X1000; break; + default: goto bad; + } + vassert(pqrs != X1111); + UInt bP = (pqrs >> 3) & 1; + UInt bQ = (pqrs >> 2) & 1; + UInt bR = (pqrs >> 1) & 1; + UInt bS = (pqrs >> 0) & 1; + UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,0,bQ,bR), dN, dD, + X1011, BITS4(0,bS,0,0), dM); + *p++ = insn; + goto done; + } + case ARMin_VAluS: { + UInt dN = fregNo(i->ARMin.VAluS.argL); + UInt dD = fregNo(i->ARMin.VAluS.dst); + UInt dM = fregNo(i->ARMin.VAluS.argR); + UInt bN = dN & 1; + UInt bD = dD & 1; + UInt bM = dM & 1; + UInt pqrs = X1111; /* undefined */ + switch (i->ARMin.VAluS.op) { + case ARMvfp_ADD: pqrs = X0110; break; + case ARMvfp_SUB: pqrs = X0111; break; + case ARMvfp_MUL: pqrs = X0100; break; + case ARMvfp_DIV: pqrs = X1000; break; + default: goto bad; + } + vassert(pqrs != X1111); + UInt bP = (pqrs >> 3) & 1; + UInt bQ = (pqrs >> 2) & 1; + UInt bR = (pqrs >> 1) & 1; + UInt bS = (pqrs >> 0) & 1; + UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,bD,bQ,bR), + (dN >> 1), (dD >> 1), + X1010, BITS4(bN,bS,bM,0), (dM >> 1)); + *p++ = insn; + goto done; + } + case ARMin_VUnaryD: { + UInt dD = dregNo(i->ARMin.VUnaryD.dst); + UInt dM = dregNo(i->ARMin.VUnaryD.src); + UInt insn = 0; + switch (i->ARMin.VUnaryD.op) { + case ARMvfpu_COPY: + insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X0100,dM); + break; + case ARMvfpu_ABS: + insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X1100,dM); + break; + case ARMvfpu_NEG: + insn = XXXXXXXX(0xE, X1110,X1011,X0001,dD,X1011,X0100,dM); + break; + case ARMvfpu_SQRT: + insn = XXXXXXXX(0xE, X1110,X1011,X0001,dD,X1011,X1100,dM); + break; + default: + goto bad; + } + *p++ = insn; + goto done; + } + case ARMin_VUnaryS: { + UInt fD = fregNo(i->ARMin.VUnaryS.dst); + UInt fM = fregNo(i->ARMin.VUnaryS.src); + UInt insn = 0; + switch (i->ARMin.VUnaryS.op) { + case ARMvfpu_COPY: + insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000, + (fD >> 1), X1010, BITS4(0,1,(fM & 1),0), + (fM >> 1)); + break; + case ARMvfpu_ABS: + insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000, + (fD >> 1), X1010, BITS4(1,1,(fM & 1),0), + (fM >> 1)); + break; + case ARMvfpu_NEG: + insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0001, + (fD >> 1), X1010, BITS4(0,1,(fM & 1),0), + (fM >> 1)); + break; + case ARMvfpu_SQRT: + insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0001, + (fD >> 1), X1010, BITS4(1,1,(fM & 1),0), + (fM >> 1)); + break; + default: + goto bad; + } + *p++ = insn; + goto done; + } + case ARMin_VCmpD: { + UInt dD = dregNo(i->ARMin.VCmpD.argL); + UInt dM = dregNo(i->ARMin.VCmpD.argR); + UInt insn = XXXXXXXX(0xE, X1110, X1011, X0100, dD, X1011, X0100, dM); + *p++ = insn; /* FCMPD dD, dM */ + *p++ = 0xEEF1FA10; /* FMSTAT */ + goto done; + } + case ARMin_VCMovD: { + UInt cc = (UInt)i->ARMin.VCMovD.cond; + UInt dD = dregNo(i->ARMin.VCMovD.dst); + UInt dM = dregNo(i->ARMin.VCMovD.src); + vassert(cc < 16 && cc != ARMcc_AL); + UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM); + *p++ = insn; + goto done; + } + case ARMin_VCMovS: { + UInt cc = (UInt)i->ARMin.VCMovS.cond; + UInt fD = fregNo(i->ARMin.VCMovS.dst); + UInt fM = fregNo(i->ARMin.VCMovS.src); + vassert(cc < 16 && cc != ARMcc_AL); + UInt insn = XXXXXXXX(cc, X1110, BITS4(1,(fD & 1),1,1), + X0000,(fD >> 1),X1010, + BITS4(0,1,(fM & 1),0), (fM >> 1)); + *p++ = insn; + goto done; + } + case ARMin_VCvtSD: { + if (i->ARMin.VCvtSD.sToD) { + UInt dD = dregNo(i->ARMin.VCvtSD.dst); + UInt fM = fregNo(i->ARMin.VCvtSD.src); + UInt insn = XXXXXXXX(0xE, X1110, X1011, X0111, dD, X1010, + BITS4(1,1, (fM & 1), 0), + (fM >> 1)); + *p++ = insn; + goto done; + } else { + UInt fD = fregNo(i->ARMin.VCvtSD.dst); + UInt dM = dregNo(i->ARMin.VCvtSD.src); + UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), + X0111, (fD >> 1), + X1011, X1100, dM); + *p++ = insn; + goto done; + } + goto bad; + } + case ARMin_VXferD: { + UInt dD = dregNo(i->ARMin.VXferD.dD); + UInt rHi = iregNo(i->ARMin.VXferD.rHi); + UInt rLo = iregNo(i->ARMin.VXferD.rLo); + /* vmov dD, rLo, rHi is + E C 4 rHi rLo B (0,0,dD[4],1) dD[3:0] + vmov rLo, rHi, dD is + E C 5 rHi rLo B (0,0,dD[4],1) dD[3:0] + */ + UInt insn + = XXXXXXXX(0xE, 0xC, i->ARMin.VXferD.toD ? 4 : 5, + rHi, rLo, 0xB, + BITS4(0,0, ((dD >> 4) & 1), 1), (dD & 0xF)); + *p++ = insn; + goto done; + } + case ARMin_VXferS: { + UInt fD = fregNo(i->ARMin.VXferS.fD); + UInt rLo = iregNo(i->ARMin.VXferS.rLo); + /* vmov fD, rLo is + E E 0 fD[4:1] rLo A (fD[0],0,0,1) 0 + vmov rLo, fD is + E E 1 fD[4:1] rLo A (fD[0],0,0,1) 0 + */ + UInt insn + = XXXXXXXX(0xE, 0xE, i->ARMin.VXferS.toS ? 0 : 1, + (fD >> 1) & 0xF, rLo, 0xA, + BITS4((fD & 1),0,0,1), 0); + *p++ = insn; + goto done; + } + case ARMin_VCvtID: { + Bool iToD = i->ARMin.VCvtID.iToD; + Bool syned = i->ARMin.VCvtID.syned; + if (iToD && syned) { + // FSITOD: I32S-in-freg to F64-in-dreg + UInt regF = fregNo(i->ARMin.VCvtID.src); + UInt regD = dregNo(i->ARMin.VCvtID.dst); + UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD, + X1011, BITS4(1,1,(regF & 1),0), + (regF >> 1) & 0xF); + *p++ = insn; + goto done; + } + if (iToD && (!syned)) { + // FUITOD: I32U-in-freg to F64-in-dreg + UInt regF = fregNo(i->ARMin.VCvtID.src); + UInt regD = dregNo(i->ARMin.VCvtID.dst); + UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD, + X1011, BITS4(0,1,(regF & 1),0), + (regF >> 1) & 0xF); + *p++ = insn; + goto done; + } + if ((!iToD) && syned) { + // FTOSID: F64-in-dreg to I32S-in-freg + UInt regD = dregNo(i->ARMin.VCvtID.src); + UInt regF = fregNo(i->ARMin.VCvtID.dst); + UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1), + X1101, (regF >> 1) & 0xF, + X1011, X0100, regD); + *p++ = insn; + goto done; + } + if ((!iToD) && (!syned)) { + // FTOUID: F64-in-dreg to I32U-in-freg + UInt regD = dregNo(i->ARMin.VCvtID.src); + UInt regF = fregNo(i->ARMin.VCvtID.dst); + UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1), + X1100, (regF >> 1) & 0xF, + X1011, X0100, regD); + *p++ = insn; + goto done; + } + /*UNREACHED*/ + vassert(0); + } + case ARMin_FPSCR: { + Bool toFPSCR = i->ARMin.FPSCR.toFPSCR; + HReg iReg = iregNo(i->ARMin.FPSCR.iReg); + if (toFPSCR) { + /* fmxr fpscr, iReg is EEE1 iReg A10 */ + *p++ = 0xEEE10A10 | ((iReg & 0xF) << 12); + goto done; + } + goto bad; // FPSCR -> iReg case currently ATC + } + case ARMin_MFence: { + *p++ = 0xEE070F9A; /* mcr 15,0,r0,c7,c10,4 (DSB) */ + *p++ = 0xEE070FBA; /* mcr 15,0,r0,c7,c10,5 (DMB) */ + *p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4 (ISB) */ + goto done; + } + case ARMin_NLdStQ: { + UInt regD = qregNo(i->ARMin.NLdStQ.dQ) << 1; + UInt regN, regM; + UInt D = regD >> 4; + UInt bL = i->ARMin.NLdStQ.isLoad ? 1 : 0; + UInt insn; + vassert(hregClass(i->ARMin.NLdStQ.dQ) == HRcVec128); + regD &= 0xF; + if (i->ARMin.NLdStQ.amode->tag == ARMamN_RR) { + regN = iregNo(i->ARMin.NLdStQ.amode->ARMamN.RR.rN); + regM = iregNo(i->ARMin.NLdStQ.amode->ARMamN.RR.rM); + } else { + regN = iregNo(i->ARMin.NLdStQ.amode->ARMamN.R.rN); + regM = 15; + } + insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0), + regN, regD, X1010, X1000, regM); + *p++ = insn; + goto done; + } + case ARMin_NLdStD: { + UInt regD = dregNo(i->ARMin.NLdStD.dD); + UInt regN, regM; + UInt D = regD >> 4; + UInt bL = i->ARMin.NLdStD.isLoad ? 1 : 0; + UInt insn; + vassert(hregClass(i->ARMin.NLdStD.dD) == HRcFlt64); + regD &= 0xF; + if (i->ARMin.NLdStD.amode->tag == ARMamN_RR) { + regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rN); + regM = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rM); + } else { + regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.R.rN); + regM = 15; + } + insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0), + regN, regD, X0111, X1000, regM); + *p++ = insn; + goto done; + } + case ARMin_NUnaryS: { + UInt Q = i->ARMin.NUnaryS.Q ? 1 : 0; + UInt regD, D; + UInt regM, M; + UInt size = i->ARMin.NUnaryS.size; + UInt insn; + UInt opc, opc1, opc2; + switch (i->ARMin.NUnaryS.op) { + case ARMneon_VDUP: + if (i->ARMin.NUnaryS.size >= 16) + goto bad; + if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Reg) + goto bad; + if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) + goto bad; + regD = (hregClass(i->ARMin.NUnaryS.dst->reg) == HRcVec128) + ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1) + : dregNo(i->ARMin.NUnaryS.dst->reg); + regM = (hregClass(i->ARMin.NUnaryS.src->reg) == HRcVec128) + ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) + : dregNo(i->ARMin.NUnaryS.src->reg); + D = regD >> 4; + M = regM >> 4; + regD &= 0xf; + regM &= 0xf; + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), + (i->ARMin.NUnaryS.size & 0xf), regD, + X1100, BITS4(0,Q,M,0), regM); + *p++ = insn; + goto done; + case ARMneon_SETELEM: + regD = Q ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1) : + dregNo(i->ARMin.NUnaryS.dst->reg); + regM = iregNo(i->ARMin.NUnaryS.src->reg); + M = regM >> 4; + D = regD >> 4; + regM &= 0xF; + regD &= 0xF; + if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Scalar) + goto bad; + switch (size) { + case 0: + if (i->ARMin.NUnaryS.dst->index > 7) + goto bad; + opc = X1000 | i->ARMin.NUnaryS.dst->index; + break; + case 1: + if (i->ARMin.NUnaryS.dst->index > 3) + goto bad; + opc = X0001 | (i->ARMin.NUnaryS.dst->index << 1); + break; + case 2: + if (i->ARMin.NUnaryS.dst->index > 1) + goto bad; + opc = X0000 | (i->ARMin.NUnaryS.dst->index << 2); + break; + default: + goto bad; + } + opc1 = (opc >> 2) & 3; + opc2 = opc & 3; + insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),0), + regD, regM, X1011, + BITS4(D,(opc2 >> 1),(opc2 & 1),1), X0000); + *p++ = insn; + goto done; + case ARMneon_GETELEMU: + regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) : + dregNo(i->ARMin.NUnaryS.src->reg); + regD = iregNo(i->ARMin.NUnaryS.dst->reg); + M = regM >> 4; + D = regD >> 4; + regM &= 0xF; + regD &= 0xF; + if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) + goto bad; + switch (size) { + case 0: + if (Q && i->ARMin.NUnaryS.src->index > 7) { + regM++; + i->ARMin.NUnaryS.src->index -= 8; + } + if (i->ARMin.NUnaryS.src->index > 7) + goto bad; + opc = X1000 | i->ARMin.NUnaryS.src->index; + break; + case 1: + if (Q && i->ARMin.NUnaryS.src->index > 3) { + regM++; + i->ARMin.NUnaryS.src->index -= 4; + } + if (i->ARMin.NUnaryS.src->index > 3) + goto bad; + opc = X0001 | (i->ARMin.NUnaryS.src->index << 1); + break; + case 2: + goto bad; + default: + goto bad; + } + opc1 = (opc >> 2) & 3; + opc2 = opc & 3; + insn = XXXXXXXX(0xE, X1110, BITS4(1,(opc1 >> 1),(opc1 & 1),1), + regM, regD, X1011, + BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000); + *p++ = insn; + goto done; + case ARMneon_GETELEMS: + regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) : + dregNo(i->ARMin.NUnaryS.src->reg); + regD = iregNo(i->ARMin.NUnaryS.dst->reg); + M = regM >> 4; + D = regD >> 4; + regM &= 0xF; + regD &= 0xF; + if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) + goto bad; + switch (size) { + case 0: + if (Q && i->ARMin.NUnaryS.src->index > 7) { + regM++; + i->ARMin.NUnaryS.src->index -= 8; + } + if (i->ARMin.NUnaryS.src->index > 7) + goto bad; + opc = X1000 | i->ARMin.NUnaryS.src->index; + break; + case 1: + if (Q && i->ARMin.NUnaryS.src->index > 3) { + regM++; + i->ARMin.NUnaryS.src->index -= 4; + } + if (i->ARMin.NUnaryS.src->index > 3) + goto bad; + opc = X0001 | (i->ARMin.NUnaryS.src->index << 1); + break; + case 2: + if (Q && i->ARMin.NUnaryS.src->index > 1) { + regM++; + i->ARMin.NUnaryS.src->index -= 2; + } + if (i->ARMin.NUnaryS.src->index > 1) + goto bad; + opc = X0000 | (i->ARMin.NUnaryS.src->index << 2); + break; + default: + goto bad; + } + opc1 = (opc >> 2) & 3; + opc2 = opc & 3; + insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),1), + regM, regD, X1011, + BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000); + *p++ = insn; + goto done; + default: + goto bad; + } + } + case ARMin_NUnary: { + UInt Q = i->ARMin.NUnary.Q ? 1 : 0; + UInt regD = (hregClass(i->ARMin.NUnary.dst) == HRcVec128) + ? (qregNo(i->ARMin.NUnary.dst) << 1) + : dregNo(i->ARMin.NUnary.dst); + UInt regM, M; + UInt D = regD >> 4; + UInt sz1 = i->ARMin.NUnary.size >> 1; + UInt sz2 = i->ARMin.NUnary.size & 1; + UInt sz = i->ARMin.NUnary.size; + UInt insn; + UInt F = 0; /* TODO: floating point EQZ ??? */ + if (i->ARMin.NUnary.op != ARMneon_DUP) { + regM = (hregClass(i->ARMin.NUnary.src) == HRcVec128) + ? (qregNo(i->ARMin.NUnary.src) << 1) + : dregNo(i->ARMin.NUnary.src); + M = regM >> 4; + } else { + regM = iregNo(i->ARMin.NUnary.src); + M = regM >> 4; + } + regD &= 0xF; + regM &= 0xF; + switch (i->ARMin.NUnary.op) { + case ARMneon_COPY: /* VMOV reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regM, regD, X0001, + BITS4(M,Q,M,1), regM); + break; + case ARMneon_COPYN: /* VMOVN regD, regQ */ + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), + regD, X0010, BITS4(0,0,M,0), regM); + break; + case ARMneon_COPYQNSS: /* VQMOVN regD, regQ */ + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), + regD, X0010, BITS4(1,0,M,0), regM); + break; + case ARMneon_COPYQNUS: /* VQMOVUN regD, regQ */ + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), + regD, X0010, BITS4(0,1,M,0), regM); + break; + case ARMneon_COPYQNUU: /* VQMOVN regD, regQ */ + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), + regD, X0010, BITS4(1,1,M,0), regM); + break; + case ARMneon_COPYLS: /* VMOVL regQ, regD */ + if (sz >= 3) + goto bad; + insn = XXXXXXXX(0xF, X0010, + BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0), + BITS4((sz == 0) ? 1 : 0,0,0,0), + regD, X1010, BITS4(0,0,M,1), regM); + break; + case ARMneon_COPYLU: /* VMOVL regQ, regD */ + if (sz >= 3) + goto bad; + insn = XXXXXXXX(0xF, X0011, + BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0), + BITS4((sz == 0) ? 1 : 0,0,0,0), + regD, X1010, BITS4(0,0,M,1), regM); + break; + case ARMneon_NOT: /* VMVN reg, reg*/ + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101, + BITS4(1,Q,M,0), regM); + break; + case ARMneon_EQZ: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1), + regD, BITS4(0,F,0,1), BITS4(0,Q,M,0), regM); + break; + case ARMneon_CNT: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101, + BITS4(0,Q,M,0), regM); + break; + case ARMneon_CLZ: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), + regD, X0100, BITS4(1,Q,M,0), regM); + break; + case ARMneon_CLS: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), + regD, X0100, BITS4(0,Q,M,0), regM); + break; + case ARMneon_ABS: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1), + regD, X0011, BITS4(0,Q,M,0), regM); + break; + case ARMneon_DUP: + sz1 = i->ARMin.NUnary.size == 0 ? 1 : 0; + sz2 = i->ARMin.NUnary.size == 1 ? 1 : 0; + vassert(sz1 + sz2 < 2); + insn = XXXXXXXX(0xE, X1110, BITS4(1, sz1, Q, 0), regD, regM, + X1011, BITS4(D,0,sz2,1), X0000); + break; + case ARMneon_REV16: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), + regD, BITS4(0,0,0,1), BITS4(0,Q,M,0), regM); + break; + case ARMneon_REV32: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), + regD, BITS4(0,0,0,0), BITS4(1,Q,M,0), regM); + break; + case ARMneon_REV64: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), + regD, BITS4(0,0,0,0), BITS4(0,Q,M,0), regM); + break; + case ARMneon_PADDLU: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), + regD, X0010, BITS4(1,Q,M,0), regM); + break; + case ARMneon_PADDLS: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), + regD, X0010, BITS4(0,Q,M,0), regM); + break; + case ARMneon_VQSHLNUU: + insn = XXXXXXXX(0xF, X0011, + (1 << 3) | (D << 2) | ((sz >> 4) & 3), + sz & 0xf, regD, X0111, + BITS4(sz >> 6,Q,M,1), regM); + break; + case ARMneon_VQSHLNSS: + insn = XXXXXXXX(0xF, X0010, + (1 << 3) | (D << 2) | ((sz >> 4) & 3), + sz & 0xf, regD, X0111, + BITS4(sz >> 6,Q,M,1), regM); + break; + case ARMneon_VQSHLNUS: + insn = XXXXXXXX(0xF, X0011, + (1 << 3) | (D << 2) | ((sz >> 4) & 3), + sz & 0xf, regD, X0110, + BITS4(sz >> 6,Q,M,1), regM); + break; + case ARMneon_VCVTFtoS: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111, + BITS4(0,Q,M,0), regM); + break; + case ARMneon_VCVTFtoU: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111, + BITS4(1,Q,M,0), regM); + break; + case ARMneon_VCVTStoF: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110, + BITS4(0,Q,M,0), regM); + break; + case ARMneon_VCVTUtoF: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110, + BITS4(1,Q,M,0), regM); + break; + case ARMneon_VCVTFtoFixedU: + sz1 = (sz >> 5) & 1; + sz2 = (sz >> 4) & 1; + sz &= 0xf; + insn = XXXXXXXX(0xF, X0011, + BITS4(1,D,sz1,sz2), sz, regD, X1111, + BITS4(0,Q,M,1), regM); + break; + case ARMneon_VCVTFtoFixedS: + sz1 = (sz >> 5) & 1; + sz2 = (sz >> 4) & 1; + sz &= 0xf; + insn = XXXXXXXX(0xF, X0010, + BITS4(1,D,sz1,sz2), sz, regD, X1111, + BITS4(0,Q,M,1), regM); + break; + case ARMneon_VCVTFixedUtoF: + sz1 = (sz >> 5) & 1; + sz2 = (sz >> 4) & 1; + sz &= 0xf; + insn = XXXXXXXX(0xF, X0011, + BITS4(1,D,sz1,sz2), sz, regD, X1110, + BITS4(0,Q,M,1), regM); + break; + case ARMneon_VCVTFixedStoF: + sz1 = (sz >> 5) & 1; + sz2 = (sz >> 4) & 1; + sz &= 0xf; + insn = XXXXXXXX(0xF, X0010, + BITS4(1,D,sz1,sz2), sz, regD, X1110, + BITS4(0,Q,M,1), regM); + break; + case ARMneon_VCVTF32toF16: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0110, + BITS4(0,0,M,0), regM); + break; + case ARMneon_VCVTF16toF32: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0111, + BITS4(0,0,M,0), regM); + break; + case ARMneon_VRECIP: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, + BITS4(0,Q,M,0), regM); + break; + case ARMneon_VRECIPF: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101, + BITS4(0,Q,M,0), regM); + break; + case ARMneon_VABSFP: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111, + BITS4(0,Q,M,0), regM); + break; + case ARMneon_VRSQRTEFP: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101, + BITS4(1,Q,M,0), regM); + break; + case ARMneon_VRSQRTE: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, + BITS4(1,Q,M,0), regM); + break; + case ARMneon_VNEGF: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111, + BITS4(1,Q,M,0), regM); + break; + + default: + goto bad; + } + *p++ = insn; + goto done; + } + case ARMin_NDual: { + UInt Q = i->ARMin.NDual.Q ? 1 : 0; + UInt regD = (hregClass(i->ARMin.NDual.arg1) == HRcVec128) + ? (qregNo(i->ARMin.NDual.arg1) << 1) + : dregNo(i->ARMin.NDual.arg1); + UInt regM = (hregClass(i->ARMin.NDual.arg2) == HRcVec128) + ? (qregNo(i->ARMin.NDual.arg2) << 1) + : dregNo(i->ARMin.NDual.arg2); + UInt D = regD >> 4; + UInt M = regM >> 4; + UInt sz1 = i->ARMin.NDual.size >> 1; + UInt sz2 = i->ARMin.NDual.size & 1; + UInt insn; + regD &= 0xF; + regM &= 0xF; + switch (i->ARMin.NDual.op) { + case ARMneon_TRN: /* VTRN reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), + regD, X0000, BITS4(1,Q,M,0), regM); + break; + case ARMneon_ZIP: /* VZIP reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), + regD, X0001, BITS4(1,Q,M,0), regM); + break; + case ARMneon_UZP: /* VUZP reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), + regD, X0001, BITS4(0,Q,M,0), regM); + break; + default: + goto bad; + } + *p++ = insn; + goto done; + } + case ARMin_NBinary: { + UInt Q = i->ARMin.NBinary.Q ? 1 : 0; + UInt regD = (hregClass(i->ARMin.NBinary.dst) == HRcVec128) + ? (qregNo(i->ARMin.NBinary.dst) << 1) + : dregNo(i->ARMin.NBinary.dst); + UInt regN = (hregClass(i->ARMin.NBinary.argL) == HRcVec128) + ? (qregNo(i->ARMin.NBinary.argL) << 1) + : dregNo(i->ARMin.NBinary.argL); + UInt regM = (hregClass(i->ARMin.NBinary.argR) == HRcVec128) + ? (qregNo(i->ARMin.NBinary.argR) << 1) + : dregNo(i->ARMin.NBinary.argR); + UInt sz1 = i->ARMin.NBinary.size >> 1; + UInt sz2 = i->ARMin.NBinary.size & 1; + UInt D = regD >> 4; + UInt N = regN >> 4; + UInt M = regM >> 4; + UInt insn; + regD &= 0xF; + regM &= 0xF; + regN &= 0xF; + switch (i->ARMin.NBinary.op) { + case ARMneon_VAND: /* VAND reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X0001, + BITS4(N,Q,M,1), regM); + break; + case ARMneon_VORR: /* VORR reg, reg, reg*/ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X0001, + BITS4(N,Q,M,1), regM); + break; + case ARMneon_VXOR: /* VEOR reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X0001, + BITS4(N,Q,M,1), regM); + break; + case ARMneon_VADD: /* VADD reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X1000, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VSUB: /* VSUB reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X1000, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VMINU: /* VMIN.Uxx reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0110, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VMINS: /* VMIN.Sxx reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0110, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VMAXU: /* VMAX.Uxx reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0110, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VMAXS: /* VMAX.Sxx reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0110, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VRHADDS: /* VRHADD.Sxx reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0001, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VRHADDU: /* VRHADD.Uxx reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0001, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VQADDU: /* VQADD unsigned reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0000, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VQADDS: /* VQADD signed reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0000, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VQSUBU: /* VQSUB unsigned reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0010, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VQSUBS: /* VQSUB signed reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0010, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VCGTU: /* VCGT unsigned reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0011, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VCGTS: /* VCGT signed reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0011, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VCGEU: /* VCGE unsigned reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0011, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VCGES: /* VCGE signed reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0011, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VCEQ: /* VCEQ reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X1000, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VEXT: /* VEXT.8 reg, reg, #imm4*/ + if (i->ARMin.NBinary.size >= 16) + goto bad; + insn = XXXXXXXX(0xF, X0010, BITS4(1,D,1,1), regN, regD, + i->ARMin.NBinary.size & 0xf, BITS4(N,Q,M,0), + regM); + break; + case ARMneon_VMUL: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X1001, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VMULLU: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,sz1,sz2), regN, regD, + X1100, BITS4(N,0,M,0), regM); + break; + case ARMneon_VMULLS: + insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, + X1100, BITS4(N,0,M,0), regM); + break; + case ARMneon_VMULP: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X1001, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VMULFP: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, + X1101, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VMULLP: + insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, + X1110, BITS4(N,0,M,0), regM); + break; + case ARMneon_VQDMULH: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X1011, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VQRDMULH: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X1011, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VQDMULL: + insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, + X1101, BITS4(N,0,M,0), regM); + break; + case ARMneon_VTBL: + insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), regN, regD, + X1000, BITS4(N,0,M,0), regM); + break; + case ARMneon_VPADD: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X1011, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VPADDFP: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, + X1101, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VPMINU: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X1010, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VPMINS: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X1010, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VPMAXU: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X1010, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VPMAXS: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X1010, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VADDFP: /* VADD reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, + X1101, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VSUBFP: /* VADD reg, reg, reg */ + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, + X1101, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VABDFP: /* VABD reg, reg, reg */ + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, + X1101, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VMINF: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, + X1111, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VMAXF: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, + X1111, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VPMINF: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, + X1111, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VPMAXF: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, + X1111, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VRECPS: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1111, + BITS4(N,Q,M,1), regM); + break; + case ARMneon_VCGTF: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, X1110, + BITS4(N,Q,M,0), regM); + break; + case ARMneon_VCGEF: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X1110, + BITS4(N,Q,M,0), regM); + break; + case ARMneon_VCEQF: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1110, + BITS4(N,Q,M,0), regM); + break; + case ARMneon_VRSQRTS: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X1111, + BITS4(N,Q,M,1), regM); + break; + default: + goto bad; + } + *p++ = insn; + goto done; + } + case ARMin_NShift: { + UInt Q = i->ARMin.NShift.Q ? 1 : 0; + UInt regD = (hregClass(i->ARMin.NShift.dst) == HRcVec128) + ? (qregNo(i->ARMin.NShift.dst) << 1) + : dregNo(i->ARMin.NShift.dst); + UInt regM = (hregClass(i->ARMin.NShift.argL) == HRcVec128) + ? (qregNo(i->ARMin.NShift.argL) << 1) + : dregNo(i->ARMin.NShift.argL); + UInt regN = (hregClass(i->ARMin.NShift.argR) == HRcVec128) + ? (qregNo(i->ARMin.NShift.argR) << 1) + : dregNo(i->ARMin.NShift.argR); + UInt sz1 = i->ARMin.NShift.size >> 1; + UInt sz2 = i->ARMin.NShift.size & 1; + UInt D = regD >> 4; + UInt N = regN >> 4; + UInt M = regM >> 4; + UInt insn; + regD &= 0xF; + regM &= 0xF; + regN &= 0xF; + switch (i->ARMin.NShift.op) { + case ARMneon_VSHL: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0100, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VSAL: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0100, BITS4(N,Q,M,0), regM); + break; + case ARMneon_VQSHL: + insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, + X0100, BITS4(N,Q,M,1), regM); + break; + case ARMneon_VQSAL: + insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, + X0100, BITS4(N,Q,M,1), regM); + break; + default: + goto bad; + } + *p++ = insn; + goto done; + } + case ARMin_NeonImm: { + UInt Q = (hregClass(i->ARMin.NeonImm.dst) == HRcVec128) ? 1 : 0; + UInt regD = Q ? (qregNo(i->ARMin.NeonImm.dst) << 1) : + dregNo(i->ARMin.NeonImm.dst); + UInt D = regD >> 4; + UInt imm = i->ARMin.NeonImm.imm->imm8; + UInt tp = i->ARMin.NeonImm.imm->type; + UInt j = imm >> 7; + UInt imm3 = (imm >> 4) & 0x7; + UInt imm4 = imm & 0xF; + UInt cmode, op; + UInt insn; + regD &= 0xF; + if (tp == 9) + op = 1; + else + op = 0; + switch (tp) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + cmode = tp << 1; + break; + case 9: + case 6: + cmode = 14; + break; + case 7: + cmode = 12; + break; + case 8: + cmode = 13; + break; + case 10: + cmode = 15; + break; + default: + vpanic("ARMin_NeonImm"); + + } + insn = XXXXXXXX(0xF, BITS4(0,0,1,j), BITS4(1,D,0,0), imm3, regD, + cmode, BITS4(0,Q,op,1), imm4); + *p++ = insn; + goto done; + } + case ARMin_NCMovQ: { + UInt cc = (UInt)i->ARMin.NCMovQ.cond; + UInt qM = qregNo(i->ARMin.NCMovQ.src) << 1; + UInt qD = qregNo(i->ARMin.NCMovQ.dst) << 1; + UInt vM = qM & 0xF; + UInt vD = qD & 0xF; + UInt M = (qM >> 4) & 1; + UInt D = (qD >> 4) & 1; + vassert(cc < 16 && cc != ARMcc_AL && cc != ARMcc_NV); + /* b!cc here+8: !cc A00 0000 */ + UInt insn = XXXXXXXX(cc ^ 1, 0xA, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0); + *p++ = insn; + /* vmov qD, qM */ + insn = XXXXXXXX(0xF, 0x2, BITS4(0,D,1,0), + vM, vD, BITS4(0,0,0,1), BITS4(M,1,M,1), vM); + *p++ = insn; + goto done; + } + case ARMin_Add32: { + UInt regD = iregNo(i->ARMin.Add32.rD); + UInt regN = iregNo(i->ARMin.Add32.rN); + UInt imm32 = i->ARMin.Add32.imm32; + vassert(regD != regN); + /* MOV regD, imm32 */ + p = imm32_to_iregNo((UInt *)p, regD, imm32); + /* ADD regD, regN, regD */ + UInt insn = XXXXXXXX(0xE, 0, X1000, regN, regD, 0, 0, regD); + *p++ = insn; + goto done; + } + /* ... */ + default: + goto bad; } - bad: - ppARMInstr(i); - vpanic("emit_ARMInstr"); - /*NOTREACHED*/ - -// done: - vassert(p - &buf[0] <= 32); - return p - &buf[0]; + bad: + ppARMInstr(i); + vpanic("emit_ARMInstr"); + /*NOTREACHED*/ + + done: + vassert(((UChar*)p) - &buf[0] <= 32); + return ((UChar*)p) - &buf[0]; } +#undef BITS4 +#undef X0000 +#undef X0001 +#undef X0010 +#undef X0011 +#undef X0100 +#undef X0101 +#undef X0110 +#undef X0111 +#undef X1000 +#undef X1001 +#undef X1010 +#undef X1011 +#undef X1100 +#undef X1101 +#undef X1110 +#undef X1111 +#undef XXXXX___ +#undef XXXXXX__ +#undef XXX___XX +#undef XXXXX__X +#undef XXXXXXXX /*---------------------------------------------------------------*/ /*--- end host_arm_defs.c ---*/ diff --git a/VEX/priv/host_arm_defs.h b/VEX/priv/host_arm_defs.h index 1d22685..1901e80 100644 --- a/VEX/priv/host_arm_defs.h +++ b/VEX/priv/host_arm_defs.h @@ -1,52 +1,38 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_arm_defs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_arm_defs.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. - - Neither the names of the U.S. Department of Energy nor the - University of California nor the names of its contributors may be - used to endorse or promote products derived from this software - without prior written permission. + The GNU General Public License is contained in the file COPYING. */ #ifndef __VEX_HOST_ARM_DEFS_H #define __VEX_HOST_ARM_DEFS_H +extern UInt arm_hwcaps; + /* --------- Registers. --------- */ @@ -56,59 +42,72 @@ extern void ppHRegARM ( HReg ); -extern HReg hregARM_R0 ( void ); -extern HReg hregARM_R1 ( void ); -extern HReg hregARM_R2 ( void ); -extern HReg hregARM_R3 ( void ); -extern HReg hregARM_R4 ( void ); -extern HReg hregARM_R5 ( void ); -extern HReg hregARM_R6 ( void ); -extern HReg hregARM_R7 ( void ); -extern HReg hregARM_R8 ( void ); -extern HReg hregARM_R9 ( void ); +extern HReg hregARM_R0 ( void ); +extern HReg hregARM_R1 ( void ); +extern HReg hregARM_R2 ( void ); +extern HReg hregARM_R3 ( void ); +extern HReg hregARM_R4 ( void ); +extern HReg hregARM_R5 ( void ); +extern HReg hregARM_R6 ( void ); +extern HReg hregARM_R7 ( void ); +extern HReg hregARM_R8 ( void ); +extern HReg hregARM_R9 ( void ); extern HReg hregARM_R10 ( void ); extern HReg hregARM_R11 ( void ); extern HReg hregARM_R12 ( void ); extern HReg hregARM_R13 ( void ); extern HReg hregARM_R14 ( void ); extern HReg hregARM_R15 ( void ); - - -#define GET_BP_REG() hregARM_R12() // x86 ebp -#define GET_SP_REG() hregARM_R13() // x86 esp -#define GET_LN_REG() hregARM_R14() -#define GET_PC_REG() hregARM_R15() - - - - -/* --------- Condition codes, Intel encoding. --------- */ +extern HReg hregARM_D8 ( void ); +extern HReg hregARM_D9 ( void ); +extern HReg hregARM_D10 ( void ); +extern HReg hregARM_D11 ( void ); +extern HReg hregARM_D12 ( void ); +extern HReg hregARM_S26 ( void ); +extern HReg hregARM_S27 ( void ); +extern HReg hregARM_S28 ( void ); +extern HReg hregARM_S29 ( void ); +extern HReg hregARM_S30 ( void ); +extern HReg hregARM_Q8 ( void ); +extern HReg hregARM_Q9 ( void ); +extern HReg hregARM_Q10 ( void ); +extern HReg hregARM_Q11 ( void ); +extern HReg hregARM_Q12 ( void ); +extern HReg hregARM_Q13 ( void ); +extern HReg hregARM_Q14 ( void ); +extern HReg hregARM_Q15 ( void ); + +/* Number of registers used arg passing in function calls */ +#define ARM_N_ARGREGS 4 /* r0, r1, r2, r3 */ + + +/* --------- Condition codes. --------- */ typedef enum { - ARMccEQ = 0, /* equal : Z=1 */ - ARMccNE = 1, /* not equal : Z=0 */ + ARMcc_EQ = 0, /* equal : Z=1 */ + ARMcc_NE = 1, /* not equal : Z=0 */ - ARMccHS = 2, /* >=u (higher or same) : C=1 */ - ARMccLO = 3, /* =u (higher or same) : C=1 */ + ARMcc_LO = 3, /* u (higher) : C=1 && Z=0 */ - ARMccLS = 9, /* <=u (lower or same) : C=0 || Z=1 */ + ARMcc_HI = 8, /* >u (higher) : C=1 && Z=0 */ + ARMcc_LS = 9, /* <=u (lower or same) : C=0 || Z=1 */ - ARMccGE = 10, /* >=s (signed greater or equal) : N=V */ - ARMccLT = 11, /* =s (signed greater or equal) : N=V */ + ARMcc_LT = 11, /* s (signed greater) : Z=0 && N=V */ - ARMccLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */ + ARMcc_GT = 12, /* >s (signed greater) : Z=0 && N=V */ + ARMcc_LE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */ - ARMccAL = 14, /* always (unconditional) */ - ARMccNV = 15 /* never (basically undefined meaning), deprecated */ + ARMcc_AL = 14, /* always (unconditional) */ + ARMcc_NV = 15 /* never (basically undefined meaning), deprecated */ } ARMCondCode; @@ -116,95 +115,44 @@ extern HChar* showARMCondCode ( ARMCondCode ); - -/* --------- Immediate types. --------- */ - -typedef UInt ARMImm4; -typedef UInt ARMImm5; -typedef UInt ARMImm8; -typedef UInt ARMImm12; -typedef UInt ARMImm24; // Branch imm -typedef - struct { - ARMImm8 imm; - ARMImm4 rot; - } - ARMImm12A; /* extended (rotated) immedate */ - -extern Bool mk_ARMImm12A ( UInt, ARMImm12A*); - - - /* --------- Memory address expressions (amodes). --------- */ /* --- Addressing Mode 1 --- */ typedef enum { - ARMam1_I12A, /* Imm12A: extended (rotated) immedate */ - ARMam1_ShlI, /* ShlI reg Imm5 */ - ARMam1_ShrI, /* ShrI reg Imm5 */ - ARMam1_SarI, /* SarI reg Imm5 */ - ARMam1_ShlR, /* ShlR reg reg */ - ARMam1_ShrR, /* ShrR reg reg */ - ARMam1_SarR, /* SarR reg reg */ + ARMam1_RI=1, /* reg +/- imm12 */ + ARMam1_RRS /* reg1 + (reg2 << 0, 1 2 or 3) */ } ARMAMode1Tag; typedef struct { - ARMAMode1Tag tag; - union { - struct { - ARMImm12A imm; - } I12A; - struct { - HReg Rm; - ARMImm5 imm; - } ShlI; - struct { - HReg Rm; - ARMImm5 imm; - } ShrI; - struct { - HReg Rm; - ARMImm5 imm; - } SarI; - struct { - HReg Rm; - HReg Rs; - } ShlR; - struct { - HReg Rm; - HReg Rs; - } ShrR; - struct { - HReg Rm; - HReg Rs; - } SarR; - } ARMam1; + ARMAMode1Tag tag; + union { + struct { + HReg reg; + Int simm13; /* -4095 .. +4095 */ + } RI; + struct { + HReg base; + HReg index; + UInt shift; /* 0, 1 2 or 3 */ + } RRS; + } ARMam1; } ARMAMode1; -extern ARMAMode1* ARMAMode1_I12A ( ARMImm12A ); -extern ARMAMode1* ARMAMode1_ShlI ( HReg, ARMImm5 ); -extern ARMAMode1* ARMAMode1_ShrI ( HReg, ARMImm5 ); -extern ARMAMode1* ARMAMode1_SarI ( HReg, ARMImm5 ); -extern ARMAMode1* ARMAMode1_ShlR ( HReg, HReg ); -extern ARMAMode1* ARMAMode1_ShrR ( HReg, HReg ); -extern ARMAMode1* ARMAMode1_SarR ( HReg, HReg ); - -extern ARMAMode1* dopyARMAMode1 ( ARMAMode1* ); +extern ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 ); +extern ARMAMode1* ARMAMode1_RRS ( HReg base, HReg index, UInt shift ); extern void ppARMAMode1 ( ARMAMode1* ); - /* --- Addressing Mode 2 --- */ typedef enum { - ARMam2_RI, /* Reg +/- Imm12 */ - ARMam2_RR, /* Reg +/- Reg */ - ARMam2_RRS, /* Reg +/- (Reg << Imm5) */ + ARMam2_RI=3, /* reg +/- imm8 */ + ARMam2_RR /* reg1 + reg2 */ } ARMAMode2Tag; @@ -213,245 +161,815 @@ typedef ARMAMode2Tag tag; union { struct { - HReg Rn; - ARMImm12 imm; + HReg reg; + Int simm9; /* -255 .. 255 */ } RI; struct { - HReg Rn; - HReg Rm; - } RR; - struct { - HReg Rn; - HReg Rm; - ARMImm5 shift; - } RRS; + HReg base; + HReg index; + } RR; } ARMam2; } ARMAMode2; -extern ARMAMode2* ARMAMode2_RI ( HReg, ARMImm12 ); -extern ARMAMode2* ARMAMode2_RR ( HReg, HReg ); -extern ARMAMode2* ARMAMode2_RRS ( HReg, HReg, ARMImm5 ); - -extern ARMAMode2* dopyARMAMode2 ( ARMAMode2* ); +extern ARMAMode2* ARMAMode2_RI ( HReg reg, Int simm9 ); +extern ARMAMode2* ARMAMode2_RR ( HReg base, HReg index ); extern void ppARMAMode2 ( ARMAMode2* ); -/* --- Addressing Mode 3 --- */ +/* --- Addressing Mode suitable for VFP --- */ +/* The simm11 is encoded as 8 bits + 1 sign bit, + so can only be 0 % 4. */ +typedef + struct { + HReg reg; + Int simm11; /* -1020, -1016 .. 1016, 1020 */ + } + ARMAModeV; + +extern ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 ); + +extern void ppARMAModeV ( ARMAModeV* ); + +/* --- Addressing Mode suitable for Neon --- */ typedef enum { - ARMam3_RI, /* Reg +/- Imm8 */ - ARMam3_RR, /* Reg +/- Reg */ + ARMamN_R=5, + ARMamN_RR + /* ... */ } - ARMAMode3Tag; + ARMAModeNTag; typedef struct { - ARMAMode3Tag tag; + ARMAModeNTag tag; union { struct { - HReg Rn; - ARMImm8 imm; - } RI; + HReg rN; + HReg rM; + } RR; struct { - HReg Rn; - HReg Rm; - } RR; - } ARMam3; + HReg rN; + } R; + /* ... */ + } ARMamN; } - ARMAMode3; + ARMAModeN; +extern ARMAModeN* mkARMAModeN_RR ( HReg, HReg ); +extern ARMAModeN* mkARMAModeN_R ( HReg ); +extern void ppARMAModeN ( ARMAModeN* ); -extern ARMAMode3* ARMAMode3_RI ( HReg, ARMImm8 ); -extern ARMAMode3* ARMAMode3_RR ( HReg, HReg ); +/* --------- Reg or imm-8x4 operands --------- */ +/* a.k.a (a very restricted form of) Shifter Operand, + in the ARM parlance. */ -extern ARMAMode3* dopyARMAMode3 ( ARMAMode3* ); +typedef + enum { + ARMri84_I84=7, /* imm8 `ror` (2 * imm4) */ + ARMri84_R /* reg */ + } + ARMRI84Tag; -extern void ppARMAMode3 ( ARMAMode3* ); +typedef + struct { + ARMRI84Tag tag; + union { + struct { + UShort imm8; + UShort imm4; + } I84; + struct { + HReg reg; + } R; + } ARMri84; + } + ARMRI84; +extern ARMRI84* ARMRI84_I84 ( UShort imm8, UShort imm4 ); +extern ARMRI84* ARMRI84_R ( HReg ); +extern void ppARMRI84 ( ARMRI84* ); -/* ------ Branch destination ------ */ +/* --------- Reg or imm5 operands --------- */ typedef enum { - ARMbdImm, - ARMbdReg + ARMri5_I5=9, /* imm5, 1 .. 31 only (no zero!) */ + ARMri5_R /* reg */ } - ARMBranchTag; + ARMRI5Tag; typedef - struct { - ARMBranchTag tag; + struct { + ARMRI5Tag tag; union { - struct { - ARMImm24 imm24; - } Imm; - struct { - HReg reg; - } Reg; - } ARMbd; - } - ARMBranchDest; + struct { + UInt imm5; + } I5; + struct { + HReg reg; + } R; + } ARMri5; + } + ARMRI5; + +extern ARMRI5* ARMRI5_I5 ( UInt imm5 ); +extern ARMRI5* ARMRI5_R ( HReg ); + +extern void ppARMRI5 ( ARMRI5* ); + +/* -------- Neon Immediate operand -------- */ + +/* imm8 = abcdefgh, B = NOT(b); + +type | value (64bit binary) +-----+------------------------------------------------------------------------- + 0 | 00000000 00000000 00000000 abcdefgh 00000000 00000000 00000000 abcdefgh + 1 | 00000000 00000000 abcdefgh 00000000 00000000 00000000 abcdefgh 00000000 + 2 | 00000000 abcdefgh 00000000 00000000 00000000 abcdefgh 00000000 00000000 + 3 | abcdefgh 00000000 00000000 00000000 abcdefgh 00000000 00000000 00000000 + 4 | 00000000 abcdefgh 00000000 abcdefgh 00000000 abcdefgh 00000000 abcdefgh + 5 | abcdefgh 00000000 abcdefgh 00000000 abcdefgh 00000000 abcdefgh 00000000 + 6 | abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh + 7 | 00000000 00000000 abcdefgh 11111111 00000000 00000000 abcdefgh 11111111 + 8 | 00000000 abcdefgh 11111111 11111111 00000000 abcdefgh 11111111 11111111 + 9 | aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh + 10 | aBbbbbbc defgh000 00000000 00000000 aBbbbbbc defgh000 00000000 00000000 +-----+------------------------------------------------------------------------- + +Type 10 is: + (-1)^S * 2^exp * mantissa +where S = a, exp = UInt(B:c:d) - 3, mantissa = (16 + UInt(e:f:g:h)) / 16 +*/ -extern ARMBranchDest* ARMBranchDest_Imm ( ARMImm24 ); -extern ARMBranchDest* ARMBranchDest_Reg ( HReg ); +typedef + struct { + UInt type; + UInt imm8; + } + ARMNImm; -extern void ppARMBranchDest ( ARMBranchDest* ); +extern ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 ); +extern ULong ARMNImm_to_Imm64 ( ARMNImm* ); +extern ARMNImm* Imm64_to_ARMNImm ( ULong ); +extern void ppARMNImm ( ARMNImm* ); -/* --------- Instructions. --------- */ +/* ------ Neon Register or Scalar Operand ------ */ +typedef + enum { + ARMNRS_Reg=11, + ARMNRS_Scalar + } + ARMNRS_tag; + +typedef + struct { + ARMNRS_tag tag; + HReg reg; + UInt index; + } + ARMNRS; + +extern ARMNRS* mkARMNRS(ARMNRS_tag, HReg reg, UInt index); +extern void ppARMNRS ( ARMNRS* ); + +/* --------- Instructions. --------- */ -/* --- DPI's --- */ +/* --------- */ typedef enum { - ARMalu_AND, ARMalu_ORR, ARMalu_EOR, ARMalu_BIC, // Logic - ARMalu_SUB, ARMalu_RSB, ARMalu_ADD, ARMalu_ADC, ARMalu_SBC, ARMalu_RSC, // Arith - ARMalu_TST, ARMalu_TEQ, ARMalu_CMP, ARMalu_CMN, // Test - ARMalu_MOV, ARMalu_MVN // Move + ARMalu_ADD=20, /* plain 32-bit add */ + ARMalu_ADDS, /* 32-bit add, and set the flags */ + ARMalu_ADC, /* 32-bit add with carry */ + ARMalu_SUB, /* plain 32-bit subtract */ + ARMalu_SUBS, /* 32-bit subtract, and set the flags */ + ARMalu_SBC, /* 32-bit subtract with carry */ + ARMalu_AND, + ARMalu_BIC, + ARMalu_OR, + ARMalu_XOR } ARMAluOp; -extern HChar* showARMAluOp ( ARMAluOp ); +extern HChar* showARMAluOp ( ARMAluOp op ); +typedef + enum { + ARMsh_SHL=40, + ARMsh_SHR, + ARMsh_SAR + } + ARMShiftOp; + +extern HChar* showARMShiftOp ( ARMShiftOp op ); + + +typedef + enum { + ARMun_NEG=50, + ARMun_NOT, + ARMun_CLZ + } + ARMUnaryOp; + +extern HChar* showARMUnaryOp ( ARMUnaryOp op ); + + +typedef + enum { + ARMmul_PLAIN=60, + ARMmul_ZX, + ARMmul_SX + } + ARMMulOp; + +extern HChar* showARMMulOp ( ARMMulOp op ); + -/* --------- */ typedef enum { - ARMin_DPCmp, - ARMin_DPInstr1, - ARMin_DPInstr2, - - ARMin_LoadUB, - ARMin_StoreB, - ARMin_LoadW, - ARMin_StoreW, - ARMin_LoadSB, - ARMin_LoadUH, - ARMin_LoadSH, - ARMin_StoreH, - - ARMin_Branch, - ARMin_BranchL, - ARMin_Literal + ARMvfp_ADD=70, + ARMvfp_SUB, + ARMvfp_MUL, + ARMvfp_DIV + } + ARMVfpOp; + +extern HChar* showARMVfpOp ( ARMVfpOp op ); + + +typedef + enum { + ARMvfpu_COPY=80, + ARMvfpu_NEG, + ARMvfpu_ABS, + ARMvfpu_SQRT + } + ARMVfpUnaryOp; + +extern HChar* showARMVfpUnaryOp ( ARMVfpUnaryOp op ); + +typedef + enum { + ARMneon_VAND=90, + ARMneon_VORR, + ARMneon_VXOR, + ARMneon_VADD, + ARMneon_VADDFP, + ARMneon_VRHADDS, + ARMneon_VRHADDU, + ARMneon_VPADDFP, + ARMneon_VABDFP, + ARMneon_VSUB, + ARMneon_VSUBFP, + ARMneon_VMAXU, + ARMneon_VMAXS, + ARMneon_VMAXF, + ARMneon_VMINU, + ARMneon_VMINS, + ARMneon_VMINF, + ARMneon_VQADDU, + ARMneon_VQADDS, + ARMneon_VQSUBU, + ARMneon_VQSUBS, + ARMneon_VCGTU, + ARMneon_VCGTS, + ARMneon_VCGEU, + ARMneon_VCGES, + ARMneon_VCGTF, + ARMneon_VCGEF, + ARMneon_VCEQ, + ARMneon_VCEQF, + ARMneon_VEXT, + ARMneon_VMUL, + ARMneon_VMULFP, + ARMneon_VMULLU, + ARMneon_VMULLS, + ARMneon_VMULP, + ARMneon_VMULLP, + ARMneon_VQDMULH, + ARMneon_VQRDMULH, + ARMneon_VPADD, + ARMneon_VPMINU, + ARMneon_VPMINS, + ARMneon_VPMINF, + ARMneon_VPMAXU, + ARMneon_VPMAXS, + ARMneon_VPMAXF, + ARMneon_VTBL, + ARMneon_VQDMULL, + ARMneon_VRECPS, + ARMneon_VRSQRTS, + /* ... */ + } + ARMNeonBinOp; + +typedef + enum { + ARMneon_VSHL=150, + ARMneon_VSAL, /* Yah, not SAR but SAL */ + ARMneon_VQSHL, + ARMneon_VQSAL + } + ARMNeonShiftOp; + +typedef + enum { + ARMneon_COPY=160, + ARMneon_COPYLU, + ARMneon_COPYLS, + ARMneon_COPYN, + ARMneon_COPYQNSS, + ARMneon_COPYQNUS, + ARMneon_COPYQNUU, + ARMneon_NOT, + ARMneon_EQZ, + ARMneon_DUP, + ARMneon_PADDLS, + ARMneon_PADDLU, + ARMneon_CNT, + ARMneon_CLZ, + ARMneon_CLS, + ARMneon_VCVTxFPxINT, + ARMneon_VQSHLNSS, + ARMneon_VQSHLNUU, + ARMneon_VQSHLNUS, + ARMneon_VCVTFtoU, + ARMneon_VCVTFtoS, + ARMneon_VCVTUtoF, + ARMneon_VCVTStoF, + ARMneon_VCVTFtoFixedU, + ARMneon_VCVTFtoFixedS, + ARMneon_VCVTFixedUtoF, + ARMneon_VCVTFixedStoF, + ARMneon_VCVTF16toF32, + ARMneon_VCVTF32toF16, + ARMneon_REV16, + ARMneon_REV32, + ARMneon_REV64, + ARMneon_ABS, + ARMneon_VNEGF, + ARMneon_VRECIP, + ARMneon_VRECIPF, + ARMneon_VABSFP, + ARMneon_VRSQRTEFP, + ARMneon_VRSQRTE + /* ... */ + } + ARMNeonUnOp; + +typedef + enum { + ARMneon_SETELEM=200, + ARMneon_GETELEMU, + ARMneon_GETELEMS, + ARMneon_VDUP, + } + ARMNeonUnOpS; + +typedef + enum { + ARMneon_TRN=210, + ARMneon_ZIP, + ARMneon_UZP + /* ... */ + } + ARMNeonDualOp; + +extern HChar* showARMNeonBinOp ( ARMNeonBinOp op ); +extern HChar* showARMNeonUnOp ( ARMNeonUnOp op ); +extern HChar* showARMNeonUnOpS ( ARMNeonUnOpS op ); +extern HChar* showARMNeonShiftOp ( ARMNeonShiftOp op ); +extern HChar* showARMNeonDualOp ( ARMNeonDualOp op ); +extern HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op ); +extern HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op ); +extern HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op ); +extern HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op ); +extern HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op ); + +typedef + enum { + /* baseline */ + ARMin_Alu=220, + ARMin_Shift, + ARMin_Unary, + ARMin_CmpOrTst, + ARMin_Mov, + ARMin_Imm32, + ARMin_LdSt32, + ARMin_LdSt16, + ARMin_LdSt8U, + ARMin_Ld8S, + ARMin_Goto, + ARMin_CMov, + ARMin_Call, + ARMin_Mul, + ARMin_LdrEX, + ARMin_StrEX, + /* vfp */ + ARMin_VLdStD, + ARMin_VLdStS, + ARMin_VAluD, + ARMin_VAluS, + ARMin_VUnaryD, + ARMin_VUnaryS, + ARMin_VCmpD, + ARMin_VCMovD, + ARMin_VCMovS, + ARMin_VCvtSD, + ARMin_VXferD, + ARMin_VXferS, + ARMin_VCvtID, + ARMin_FPSCR, + ARMin_MFence, + /* Neon */ + ARMin_NLdStQ, + ARMin_NLdStD, + ARMin_NUnary, + ARMin_NUnaryS, + ARMin_NDual, + ARMin_NBinary, + ARMin_NBinaryS, + ARMin_NShift, + ARMin_NeonImm, + ARMin_NCMovQ, + /* This is not a NEON instruction. Actually there is no corresponding + instruction in ARM instruction set at all. We need this one to + generate spill/reload of 128-bit registers since current register + allocator demands them to consist of no more than two instructions. + We will split this instruction into 2 or 3 ARM instructions on the + emiting phase. + + NOTE: source and destination registers should be different! */ + ARMin_Add32 } ARMInstrTag; +/* Destinations are on the LEFT (first operand) */ typedef struct { ARMInstrTag tag; union { - /* Addressing Mode 1 */ - struct { - ARMAluOp op; - HReg Rn; - ARMAMode1* shifter_op; - } DPCmp; // test instrs - compare Rd with RIS and set flags - struct { - ARMAluOp op; - HReg Rd; - ARMAMode1* shifter_op; - } DPInstr1; // 1 reg: Mov - struct { - ARMAluOp op; - HReg Rd; - HReg Rn; - ARMAMode1* shifter_op; - } DPInstr2; // 2 regs: Logic, Arith, Bic - - /* Addressing Mode 2 */ - struct { - HReg Rd; - ARMAMode2* addr_mode; - } LoadUB; - struct { - HReg Rd; - ARMAMode2* addr_mode; - } StoreB; - struct { - HReg Rd; - ARMAMode2* addr_mode; - } LoadW; - struct { - HReg Rd; - ARMAMode2* addr_mode; - } StoreW; - - /* Addressing Mode 3 */ - struct { - HReg Rd; - ARMAMode3* addr_mode; - } LoadSB; - struct { - HReg Rd; - ARMAMode3* addr_mode; - } LoadUH; - struct { - HReg Rd; - ARMAMode3* addr_mode; - } LoadSH; - struct { - HReg Rd; - ARMAMode3* addr_mode; - } StoreH; - - - /* Branch */ - struct { - ARMCondCode cond; - ARMBranchDest* dest; - } Branch; - struct { - ARMCondCode cond; - ARMBranchDest* dest; - } BranchL; - - /* Literal */ - struct { - HReg reg; - UInt imm; - } Literal; // -- reg = imm - + /* ADD/SUB/AND/OR/XOR, vanilla ALU op */ + struct { + ARMAluOp op; + HReg dst; + HReg argL; + ARMRI84* argR; + } Alu; + /* SHL/SHR/SAR, 2nd arg is reg or imm */ + struct { + ARMShiftOp op; + HReg dst; + HReg argL; + ARMRI5* argR; + } Shift; + /* NOT/NEG/CLZ */ + struct { + ARMUnaryOp op; + HReg dst; + HReg src; + } Unary; + /* CMP/TST; subtract/and, discard result, set NZCV */ + struct { + Bool isCmp; + HReg argL; + ARMRI84* argR; + } CmpOrTst; + /* MOV dst, src -- reg-reg (or reg-imm8x4) move */ + struct { + HReg dst; + ARMRI84* src; + } Mov; + /* Pseudo-insn; make a 32-bit immediate */ + struct { + HReg dst; + UInt imm32; + } Imm32; + /* 32-bit load or store */ + struct { + Bool isLoad; + HReg rD; + ARMAMode1* amode; + } LdSt32; + /* 16-bit load or store */ + struct { + Bool isLoad; + Bool signedLoad; + HReg rD; + ARMAMode2* amode; + } LdSt16; + /* 8-bit (unsigned) load or store */ + struct { + Bool isLoad; + HReg rD; + ARMAMode1* amode; + } LdSt8U; + /* 8-bit signed load */ + struct { + HReg rD; + ARMAMode2* amode; + } Ld8S; + /* Pseudo-insn. Go to guest address gnext, on given + condition, which could be ARMcc_AL. */ + struct { + IRJumpKind jk; + ARMCondCode cond; + HReg gnext; + } Goto; + /* Mov src to dst on the given condition, which may not + be ARMcc_AL. */ + struct { + ARMCondCode cond; + HReg dst; + ARMRI84* src; + } CMov; + /* Pseudo-insn. Call target (an absolute address), on given + condition (which could be ARMcc_AL). */ + struct { + ARMCondCode cond; + HWord target; + Int nArgRegs; /* # regs carrying args: 0 .. 4 */ + } Call; + /* (PLAIN) 32 * 32 -> 32: r0 = r2 * r3 + (ZX) 32 *u 32 -> 64: r1:r0 = r2 *u r3 + (SX) 32 *s 32 -> 64: r1:r0 = r2 *s r3 + Why hardwired registers? Because the ARM ARM specifies + (eg for straight MUL) the result (Rd) and the left arg (Rm) + may not be the same register. That's not a constraint we + can enforce in the register allocator (without mucho extra + complexity). Hence hardwire it. At least using caller-saves + registers, which are less likely to be in use. */ + struct { + ARMMulOp op; + } Mul; + /* LDREX{,H,B} r0, [r1] + Again, hardwired registers since this is not performance + critical, and there are possibly constraints on the + registers that we can't express in the register allocator.*/ + struct { + Int szB; /* currently only 4 is allowed */ + } LdrEX; + /* STREX{,H,B} r0, r1, [r2] + r0 = SC( [r2] = r1 ) + Ditto comment re fixed registers. */ + struct { + Int szB; /* currently only 4 is allowed */ + } StrEX; + /* VFP INSTRUCTIONS */ + /* 64-bit Fp load/store */ + struct { + Bool isLoad; + HReg dD; + ARMAModeV* amode; + } VLdStD; + /* 32-bit Fp load/store */ + struct { + Bool isLoad; + HReg fD; + ARMAModeV* amode; + } VLdStS; + /* 64-bit FP binary arithmetic */ + struct { + ARMVfpOp op; + HReg dst; + HReg argL; + HReg argR; + } VAluD; + /* 32-bit FP binary arithmetic */ + struct { + ARMVfpOp op; + HReg dst; + HReg argL; + HReg argR; + } VAluS; + /* 64-bit FP unary, also reg-reg move */ + struct { + ARMVfpUnaryOp op; + HReg dst; + HReg src; + } VUnaryD; + /* 32-bit FP unary, also reg-reg move */ + struct { + ARMVfpUnaryOp op; + HReg dst; + HReg src; + } VUnaryS; + /* 64-bit FP compare and move results to CPSR (FCMPD;FMSTAT) */ + struct { + HReg argL; + HReg argR; + } VCmpD; + /* 64-bit FP mov src to dst on the given condition, which may + not be ARMcc_AL. */ + struct { + ARMCondCode cond; + HReg dst; + HReg src; + } VCMovD; + /* 32-bit FP mov src to dst on the given condition, which may + not be ARMcc_AL. */ + struct { + ARMCondCode cond; + HReg dst; + HReg src; + } VCMovS; + /* Convert between 32-bit and 64-bit FP values (both ways). + (FCVTSD, FCVTDS) */ + struct { + Bool sToD; /* True: F32->F64. False: F64->F32 */ + HReg dst; + HReg src; + } VCvtSD; + /* Transfer a VFP D reg to/from two integer registers (VMOV) */ + struct { + Bool toD; + HReg dD; + HReg rHi; + HReg rLo; + } VXferD; + /* Transfer a VFP S reg to/from an integer register (VMOV) */ + struct { + Bool toS; + HReg fD; + HReg rLo; + } VXferS; + /* Convert between 32-bit ints and 64-bit FP values (both ways + and both signednesses). (FSITOD, FUITOD, FTOSID, FTOUID) */ + struct { + Bool iToD; /* True: I32->F64. False: F64->I32 */ + Bool syned; /* True: I32 is signed. False: I32 is unsigned */ + HReg dst; + HReg src; + } VCvtID; + /* Move a 32-bit value to/from the FPSCR (FMXR, FMRX) */ + struct { + Bool toFPSCR; + HReg iReg; + } FPSCR; + /* Mem fence. An insn which fences all loads and stores as + much as possible before continuing. On ARM we emit the + sequence + mcr 15,0,r0,c7,c10,4 (DSB) + mcr 15,0,r0,c7,c10,5 (DMB) + mcr 15,0,r0,c7,c5,4 (ISB) + which is probably total overkill, but better safe than + sorry. + */ + struct { + } MFence; + /* Neon data processing instruction: 3 registers of the same + length */ + struct { + ARMNeonBinOp op; + HReg dst; + HReg argL; + HReg argR; + UInt size; + Bool Q; + } NBinary; + struct { + ARMNeonBinOp op; + ARMNRS* dst; + ARMNRS* argL; + ARMNRS* argR; + UInt size; + Bool Q; + } NBinaryS; + struct { + ARMNeonShiftOp op; + HReg dst; + HReg argL; + HReg argR; + UInt size; + Bool Q; + } NShift; + struct { + Bool isLoad; + HReg dQ; + ARMAModeN *amode; + } NLdStQ; + struct { + Bool isLoad; + HReg dD; + ARMAModeN *amode; + } NLdStD; + struct { + ARMNeonUnOpS op; + ARMNRS* dst; + ARMNRS* src; + UInt size; + Bool Q; + } NUnaryS; + struct { + ARMNeonUnOp op; + HReg dst; + HReg src; + UInt size; + Bool Q; + } NUnary; + /* Takes two arguments and modifies them both. */ + struct { + ARMNeonDualOp op; + HReg arg1; + HReg arg2; + UInt size; + Bool Q; + } NDual; + struct { + HReg dst; + ARMNImm* imm; + } NeonImm; + /* 128-bit Neon move src to dst on the given condition, which + may not be ARMcc_AL. */ + struct { + ARMCondCode cond; + HReg dst; + HReg src; + } NCMovQ; + struct { + /* Note: rD != rN */ + HReg rD; + HReg rN; + UInt imm32; + } Add32; } ARMin; } ARMInstr; -extern ARMInstr* ARMInstr_DPCmp ( ARMAluOp, HReg, ARMAMode1* ); -extern ARMInstr* ARMInstr_DPInstr1 ( ARMAluOp, HReg, ARMAMode1* ); -extern ARMInstr* ARMInstr_DPInstr2 ( ARMAluOp, HReg, HReg, ARMAMode1* ); - -extern ARMInstr* ARMInstr_LoadUB ( HReg, ARMAMode2* ); -extern ARMInstr* ARMInstr_StoreB ( HReg, ARMAMode2* ); -extern ARMInstr* ARMInstr_LoadW ( HReg, ARMAMode2* ); -extern ARMInstr* ARMInstr_StoreW ( HReg, ARMAMode2* ); -extern ARMInstr* ARMInstr_LoadSB ( HReg, ARMAMode3* ); -extern ARMInstr* ARMInstr_LoadUH ( HReg, ARMAMode3* ); -extern ARMInstr* ARMInstr_LoadSH ( HReg, ARMAMode3* ); -extern ARMInstr* ARMInstr_StoreH ( HReg, ARMAMode3* ); - -extern ARMInstr* ARMInstr_Branch ( ARMCondCode, ARMBranchDest* ); -extern ARMInstr* ARMInstr_BranchL ( ARMCondCode, ARMBranchDest* ); -extern ARMInstr* ARMInstr_Literal ( HReg, UInt ); +extern ARMInstr* ARMInstr_Alu ( ARMAluOp, HReg, HReg, ARMRI84* ); +extern ARMInstr* ARMInstr_Shift ( ARMShiftOp, HReg, HReg, ARMRI5* ); +extern ARMInstr* ARMInstr_Unary ( ARMUnaryOp, HReg, HReg ); +extern ARMInstr* ARMInstr_CmpOrTst ( Bool isCmp, HReg, ARMRI84* ); +extern ARMInstr* ARMInstr_Mov ( HReg, ARMRI84* ); +extern ARMInstr* ARMInstr_Imm32 ( HReg, UInt ); +extern ARMInstr* ARMInstr_LdSt32 ( Bool isLoad, HReg, ARMAMode1* ); +extern ARMInstr* ARMInstr_LdSt16 ( Bool isLoad, Bool signedLoad, + HReg, ARMAMode2* ); +extern ARMInstr* ARMInstr_LdSt8U ( Bool isLoad, HReg, ARMAMode1* ); +extern ARMInstr* ARMInstr_Ld8S ( HReg, ARMAMode2* ); +extern ARMInstr* ARMInstr_Goto ( IRJumpKind, ARMCondCode, HReg gnext ); +extern ARMInstr* ARMInstr_CMov ( ARMCondCode, HReg dst, ARMRI84* src ); +extern ARMInstr* ARMInstr_Call ( ARMCondCode, HWord, Int nArgRegs ); +extern ARMInstr* ARMInstr_Mul ( ARMMulOp op ); +extern ARMInstr* ARMInstr_LdrEX ( Int szB ); +extern ARMInstr* ARMInstr_StrEX ( Int szB ); +extern ARMInstr* ARMInstr_VLdStD ( Bool isLoad, HReg, ARMAModeV* ); +extern ARMInstr* ARMInstr_VLdStS ( Bool isLoad, HReg, ARMAModeV* ); +extern ARMInstr* ARMInstr_VAluD ( ARMVfpOp op, HReg, HReg, HReg ); +extern ARMInstr* ARMInstr_VAluS ( ARMVfpOp op, HReg, HReg, HReg ); +extern ARMInstr* ARMInstr_VUnaryD ( ARMVfpUnaryOp, HReg dst, HReg src ); +extern ARMInstr* ARMInstr_VUnaryS ( ARMVfpUnaryOp, HReg dst, HReg src ); +extern ARMInstr* ARMInstr_VCmpD ( HReg argL, HReg argR ); +extern ARMInstr* ARMInstr_VCMovD ( ARMCondCode, HReg dst, HReg src ); +extern ARMInstr* ARMInstr_VCMovS ( ARMCondCode, HReg dst, HReg src ); +extern ARMInstr* ARMInstr_VCvtSD ( Bool sToD, HReg dst, HReg src ); +extern ARMInstr* ARMInstr_VXferD ( Bool toD, HReg dD, HReg rHi, HReg rLo ); +extern ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo ); +extern ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned, + HReg dst, HReg src ); +extern ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg ); +extern ARMInstr* ARMInstr_MFence ( void ); +extern ARMInstr* ARMInstr_NLdStQ ( Bool isLoad, HReg, ARMAModeN* ); +extern ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg, ARMAModeN* ); +extern ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp, HReg, HReg, UInt, Bool ); +extern ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOp, ARMNRS*, ARMNRS*, + UInt, Bool ); +extern ARMInstr* ARMInstr_NDual ( ARMNeonDualOp, HReg, HReg, UInt, Bool ); +extern ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp, HReg, HReg, HReg, + UInt, Bool ); +extern ARMInstr* ARMInstr_NShift ( ARMNeonShiftOp, HReg, HReg, HReg, + UInt, Bool ); +extern ARMInstr* ARMInstr_NeonImm ( HReg, ARMNImm* ); +extern ARMInstr* ARMInstr_NCMovQ ( ARMCondCode, HReg, HReg ); +extern ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ); extern void ppARMInstr ( ARMInstr* ); /* Some functions that insulate the register allocator from details of the underlying instruction set. */ -extern void getAllocableRegs_ARM ( Int*, HReg** ); -extern void getRegUsage_ARMInstr ( HRegUsage*, ARMInstr* ); -extern void mapRegs_ARMInstr ( HRegRemap*, ARMInstr* ); -extern Bool isMove_ARMInstr ( ARMInstr*, HReg*, HReg* ); -extern Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr* ); -extern ARMInstr* genSpill_ARM ( HReg rreg, Int offset ); -extern ARMInstr* genReload_ARM ( HReg rreg, Int offset ); -extern void getAllocableRegs_ARM ( Int*, HReg** ); -extern HInstrArray* iselSB_ARM ( IRSB* ); +extern void getRegUsage_ARMInstr ( HRegUsage*, ARMInstr*, Bool ); +extern void mapRegs_ARMInstr ( HRegRemap*, ARMInstr*, Bool ); +extern Bool isMove_ARMInstr ( ARMInstr*, HReg*, HReg* ); +extern Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr*, + Bool, void* dispatch ); + +extern void genSpill_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offset, Bool ); +extern void genReload_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offset, Bool ); + +extern void getAllocableRegs_ARM ( Int*, HReg** ); +extern HInstrArray* iselSB_ARM ( IRSB*, VexArch, + VexArchInfo*, VexAbiInfo* ); #endif /* ndef __VEX_HOST_ARM_DEFS_H */ diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c index 302d80f..4bba9a3 100644 --- a/VEX/priv/host_arm_isel.c +++ b/VEX/priv/host_arm_isel.c @@ -1,59 +1,67 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_arm_isel.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_arm_isel.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. - - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. - - This library is made available under a dual licensing scheme. - - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net + + NEON support is + Copyright (C) 2010-2010 Samsung Electronics + contributed by Dmitry Zhurikhin + and Kirill Batuzov + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. - - Neither the names of the U.S. Department of Energy nor the - University of California nor the names of its contributors may be - used to endorse or promote products derived from this software - without prior written permission. + The GNU General Public License is contained in the file COPYING. */ #include "libvex_basictypes.h" #include "libvex_ir.h" #include "libvex.h" +#include "ir_match.h" #include "main_util.h" #include "main_globals.h" #include "host_generic_regs.h" +#include "host_generic_simd64.h" // for 32-bit SIMD helpers #include "host_arm_defs.h" +/*---------------------------------------------------------*/ +/*--- ARMvfp control word stuff ---*/ +/*---------------------------------------------------------*/ + +/* Vex-generated code expects to run with the FPU set as follows: all + exceptions masked, round-to-nearest, non-vector mode, with the NZCV + flags cleared, and FZ (flush to zero) disabled. Curiously enough, + this corresponds to a FPSCR value of zero. + + fpscr should therefore be zero on entry to Vex-generated code, and + should be unchanged at exit. (Or at least the bottom 28 bits + should be zero). +*/ + +#define DEFAULT_FPSCR 0 + + /*---------------------------------------------------------*/ /*--- ISelEnv ---*/ /*---------------------------------------------------------*/ @@ -71,11 +79,21 @@ same set of IRTemps as the type mapping does. - vregmap holds the primary register for the IRTemp. + - vregmapHI is only used for 64-bit integer-typed + IRTemps. It holds the identity of a second + 32-bit virtual HReg, which holds the high half + of the value. + + - The name of the vreg in which we stash a copy of the link reg, so + helper functions don't kill it. - The code array, that is, the insns selected so far. - A counter, for generating new virtual registers. + - The host hardware capabilities word. This is set at the start + and does not change. + Note, this is all host-independent. */ typedef @@ -83,11 +101,16 @@ typedef IRTypeEnv* type_env; HReg* vregmap; + HReg* vregmapHI; Int n_vregmap; + HReg savedLR; + HInstrArray* code; Int vreg_ctr; + + UInt hwcaps; } ISelEnv; @@ -98,6 +121,15 @@ static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp ) return env->vregmap[tmp]; } +static void lookupIRTemp64 ( HReg* vrHI, HReg* vrLO, ISelEnv* env, IRTemp tmp ) +{ + vassert(tmp >= 0); + vassert(tmp < env->n_vregmap); + vassert(env->vregmapHI[tmp] != INVALID_HREG); + *vrLO = env->vregmap[tmp]; + *vrHI = env->vregmapHI[tmp]; +} + static void addInstr ( ISelEnv* env, ARMInstr* instr ) { addHInstr(env->code, instr); @@ -105,6 +137,14 @@ static void addInstr ( ISelEnv* env, ARMInstr* instr ) ppARMInstr(instr); vex_printf("\n"); } +#if 0 + if (instr->tag == ARMin_NUnary || instr->tag == ARMin_NBinary + || instr->tag == ARMin_NUnaryS || instr->tag == ARMin_NBinaryS + || instr->tag == ARMin_NDual || instr->tag == ARMin_NShift) { + ppARMInstr(instr); + vex_printf("\n"); + } +#endif } static HReg newVRegI ( ISelEnv* env ) @@ -114,6 +154,42 @@ static HReg newVRegI ( ISelEnv* env ) return reg; } +static HReg newVRegD ( ISelEnv* env ) +{ + HReg reg = mkHReg(env->vreg_ctr, HRcFlt64, True/*virtual reg*/); + env->vreg_ctr++; + return reg; +} + +static HReg newVRegF ( ISelEnv* env ) +{ + HReg reg = mkHReg(env->vreg_ctr, HRcFlt32, True/*virtual reg*/); + env->vreg_ctr++; + return reg; +} + +static HReg newVRegV ( ISelEnv* env ) +{ + HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/); + env->vreg_ctr++; + return reg; +} + +/* These are duplicated in guest_arm_toIR.c */ +static IRExpr* unop ( IROp op, IRExpr* a ) +{ + return IRExpr_Unop(op, a); +} + +static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) +{ + return IRExpr_Binop(op, a1, a2); +} + +static IRExpr* bind ( Int binder ) +{ + return IRExpr_Binder(binder); +} /*---------------------------------------------------------*/ @@ -126,579 +202,747 @@ static HReg newVRegI ( ISelEnv* env ) checks that all returned registers are virtual. You should not call the _wrk version directly. */ -static ARMAMode1* iselIntExpr_AMode1_wrk ( ISelEnv* env, IRExpr* e ); -static ARMAMode1* iselIntExpr_AMode1 ( ISelEnv* env, IRExpr* e ); +static ARMAMode1* iselIntExpr_AMode1_wrk ( ISelEnv* env, IRExpr* e ); +static ARMAMode1* iselIntExpr_AMode1 ( ISelEnv* env, IRExpr* e ); -/* static ARMAMode2* iselIntExpr_AMode2_wrk ( ISelEnv* env, IRExpr* e ); */ -static ARMAMode2* iselIntExpr_AMode2 ( ISelEnv* env, IRExpr* e ); +static ARMAMode2* iselIntExpr_AMode2_wrk ( ISelEnv* env, IRExpr* e ); +static ARMAMode2* iselIntExpr_AMode2 ( ISelEnv* env, IRExpr* e ); -static ARMAMode3* iselIntExpr_AMode3_wrk ( ISelEnv* env, IRExpr* e ); -static ARMAMode3* iselIntExpr_AMode3 ( ISelEnv* env, IRExpr* e ); +static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e ); +static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e ); -static ARMBranchDest* iselIntExpr_BD_wrk ( ISelEnv* env, IRExpr* e ); -static ARMBranchDest* iselIntExpr_BD ( ISelEnv* env, IRExpr* e ); +static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e ); +static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e ); -static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ); -static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e ); +static ARMRI84* iselIntExpr_RI84_wrk + ( /*OUT*/Bool* didInv, Bool mayInv, ISelEnv* env, IRExpr* e ); +static ARMRI84* iselIntExpr_RI84 + ( /*OUT*/Bool* didInv, Bool mayInv, ISelEnv* env, IRExpr* e ); -static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ); -static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ); +static ARMRI5* iselIntExpr_RI5_wrk ( ISelEnv* env, IRExpr* e ); +static ARMRI5* iselIntExpr_RI5 ( ISelEnv* env, IRExpr* e ); -#if 0 -static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, - ISelEnv* env, IRExpr* e ); -static void iselInt64Expr ( HReg* rHi, HReg* rLo, - ISelEnv* env, IRExpr* e ); -#endif +static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ); +static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e ); + +static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ); + +static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, + ISelEnv* env, IRExpr* e ); +static void iselInt64Expr ( HReg* rHi, HReg* rLo, + ISelEnv* env, IRExpr* e ); + +static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselDblExpr ( ISelEnv* env, IRExpr* e ); + +static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ); + +static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e ); +static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e ); /*---------------------------------------------------------*/ /*--- ISEL: Misc helpers ---*/ /*---------------------------------------------------------*/ -#if 0 -/* Is this a 32-bit zero expression? */ -static Bool isZero32 ( IRExpr* e ) + +static UInt ROR32 ( UInt x, UInt sh ) { + vassert(sh >= 0 && sh < 32); + if (sh == 0) + return x; + else + return (x << (32-sh)) | (x >> sh); +} + +/* Figure out if 'u' fits in the special shifter-operand 8x4 immediate + form, and if so return the components. */ +static Bool fitsIn8x4 ( /*OUT*/UInt* u8, /*OUT*/UInt* u4, UInt u ) { - return e->tag == Iex_Const - && e->Iex.Const.con->tag == Ico_U32 - && e->Iex.Const.con->Ico.U32 == 0; + UInt i; + for (i = 0; i < 16; i++) { + if (0 == (u & 0xFFFFFF00)) { + *u8 = u; + *u4 = i; + return True; + } + u = ROR32(u, 30); + } + vassert(i == 16); + return False; } -#endif /* Make a int reg-reg move. */ -static ARMInstr* mk_iMOVsd_RR ( HReg src, HReg dst ) +static ARMInstr* mk_iMOVds_RR ( HReg dst, HReg src ) { vassert(hregClass(src) == HRcInt32); vassert(hregClass(dst) == HRcInt32); - return ARMInstr_DPInstr1(ARMalu_MOV, dst, ARMAMode1_ShlI(src, 0)); + return ARMInstr_Mov(dst, ARMRI84_R(src)); } -#if 0 -/* Advance/retreat stack pointer by n. */ - -static void add_to_sp ( ISelEnv* env, Int n ) -{ - HReg tmp; - ARMImm12A imm12a; - vassert(n > 0 && n < 256 && (n%4) == 0); - - if ( mk_ARMImm12A( (UInt)n, &imm12a ) ) { - addInstr(env, ARMInstr_DPInstr2(ARMalu_ADD, - GET_SP_REG(), GET_SP_REG(), - ARMAMode1_I12A( imm12a ))); - } else { - tmp = newVRegI(env); - addInstr(env, ARMInstr_Literal( tmp, (UInt)n )); - addInstr(env, ARMInstr_DPInstr2(ARMalu_ADD, - GET_SP_REG(), GET_SP_REG(), - ARMAMode1_ShlI( tmp, 0 ))); - } -} - -static void sub_from_sp ( ISelEnv* env, Int n ) -{ - HReg tmp; - ARMImm12A imm12a; - vassert(n > 0 && n < 256 && (n%4) == 0); - - if ( mk_ARMImm12A( (UInt)n, &imm12a ) ) { - addInstr(env, ARMInstr_DPInstr2(ARMalu_SUB, - GET_SP_REG(), GET_SP_REG(), - ARMAMode1_I12A( imm12a ))); - } else { - tmp = newVRegI(env); - addInstr(env, ARMInstr_Literal( tmp, (UInt)n )); - addInstr(env, ARMInstr_DPInstr2(ARMalu_SUB, - GET_SP_REG(), GET_SP_REG(), - ARMAMode1_ShlI( tmp, 0 ))); - } -} -#endif - -#if 0 -/* Push an arg onto the host stack, in preparation for a call to a - helper function of some kind. Returns the number of 32-bit words - pushed. */ - -static Int pushArg ( ISelEnv* env, IRExpr* arg ) -{ - IRType arg_ty = typeOfIRExpr(env->type_env, arg); - if (arg_ty == Ity_I32) { - - // CAB: This right? - addInstr(env, ARMInstr_StoreW( GET_SP_REG(), iselIntExpr_AMode2(env, arg) ) ); - return 1; - } - -#if 0 - else - if (arg_ty == Ity_I64) { - HReg rHi, rLo; - iselInt64Expr(&rHi, &rLo, env, arg); - addInstr(env, X86Instr_Push(X86RMI_Reg(rHi))); - addInstr(env, X86Instr_Push(X86RMI_Reg(rLo))); - return 2; - } -#endif - ppIRExpr(arg); - vpanic("pushArg(arm): can't handle arg of this type"); +/* Set the VFP unit's rounding mode to default (round to nearest). */ +static void set_VFP_rounding_default ( ISelEnv* env ) +{ + /* mov rTmp, #DEFAULT_FPSCR + fmxr fpscr, rTmp + */ + HReg rTmp = newVRegI(env); + addInstr(env, ARMInstr_Imm32(rTmp, DEFAULT_FPSCR)); + addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, rTmp)); } -#endif - -#if 0 -/* Complete the call to a helper function, by calling the - helper and clearing the args off the stack. */ -static -void callHelperAndClearArgs ( ISelEnv* env, ARMCondCode cc, - IRCallee* cee, Int n_arg_ws ) +/* Mess with the VFP unit's rounding mode: 'mode' is an I32-typed + expression denoting a value in the range 0 .. 3, indicating a round + mode encoded as per type IRRoundingMode. Set FPSCR to have the + same rounding. +*/ +static +void set_VFP_rounding_mode ( ISelEnv* env, IRExpr* mode ) { - /* Complication. Need to decide which reg to use as the fn address - pointer, in a way that doesn't trash regparm-passed - parameters. */ - vassert(sizeof(void*) == 4); - -// CAB: cee->regparms ? + /* This isn't simple, because 'mode' carries an IR rounding + encoding, and we need to translate that to an ARMvfp one: + The IR encoding: + 00 to nearest (the default) + 10 to +infinity + 01 to -infinity + 11 to zero + The ARMvfp encoding: + 00 to nearest + 01 to +infinity + 10 to -infinity + 11 to zero + Easy enough to do; just swap the two bits. + */ + HReg irrm = iselIntExpr_R(env, mode); + HReg tL = newVRegI(env); + HReg tR = newVRegI(env); + HReg t3 = newVRegI(env); + /* tL = irrm << 1; + tR = irrm >> 1; if we're lucky, these will issue together + tL &= 2; + tR &= 1; ditto + t3 = tL | tR; + t3 <<= 22; + fmxr fpscr, t3 + */ + addInstr(env, ARMInstr_Shift(ARMsh_SHL, tL, irrm, ARMRI5_I5(1))); + addInstr(env, ARMInstr_Shift(ARMsh_SHR, tR, irrm, ARMRI5_I5(1))); + addInstr(env, ARMInstr_Alu(ARMalu_AND, tL, tL, ARMRI84_I84(2,0))); + addInstr(env, ARMInstr_Alu(ARMalu_AND, tR, tR, ARMRI84_I84(1,0))); + addInstr(env, ARMInstr_Alu(ARMalu_OR, t3, tL, ARMRI84_R(tR))); + addInstr(env, ARMInstr_Shift(ARMsh_SHL, t3, t3, ARMRI5_I5(22))); + addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, t3)); +} -// addInstr(env, X86Instr_Call( cc, (UInt)cee->addr, cee->regparms)); - ARMBranchDest* dst = ARMBranchDest_Imm( (UInt)cee->addr ); - addInstr(env, ARMInstr_BranchL(cc, dst)); - if (n_arg_ws > 0) - add_to_sp(env, 4*n_arg_ws); -} -#endif +/*---------------------------------------------------------*/ +/*--- ISEL: Function call helpers ---*/ +/*---------------------------------------------------------*/ -#if 0 /* Used only in doHelperCall. See big comment in doHelperCall re - handling of regparm args. This function figures out whether - evaluation of an expression might require use of a fixed register. - If in doubt return True (safe but suboptimal). + handling of register-parameter args. This function figures out + whether evaluation of an expression might require use of a fixed + register. If in doubt return True (safe but suboptimal). */ static Bool mightRequireFixedRegs ( IRExpr* e ) { switch (e->tag) { - case Iex_Tmp: case Iex_Const: case Iex_Get: - return False; - default: - return True; + case Iex_RdTmp: case Iex_Const: case Iex_Get: + return False; + default: + return True; } } -#endif + /* Do a complete function call. guard is a Ity_Bit expression indicating whether or not the call happens. If guard==NULL, the - call is unconditional. */ + call is unconditional. Returns True iff it managed to handle this + combination of arg/return types, else returns False. */ static -void doHelperCall ( ISelEnv* env, - Bool passBBP, +Bool doHelperCall ( ISelEnv* env, + Bool passBBP, IRExpr* guard, IRCallee* cee, IRExpr** args ) { -#if 0 ARMCondCode cc; - HReg argregs[3]; - HReg tmpregs[3]; - Bool danger; - Int not_done_yet, n_args, n_arg_ws, stack_limit, - i, argreg, argregX; - - /* Marshal args for a call, do the call, and clear the stack. - Complexities to consider: - - * if passBBP is True, %ebp (the baseblock pointer) is to be - passed as the first arg. - - * If the callee claims regparmness of 1, 2 or 3, we must pass the - first 1, 2 or 3 args in registers (EAX, EDX, and ECX - respectively). To keep things relatively simple, only args of - type I32 may be passed as regparms -- just bomb out if anything - else turns up. Clearly this depends on the front ends not - trying to pass any other types as regparms. - */ - - /* 16 Nov 2004: the regparm handling is complicated by the - following problem. - - Consider a call two a function with two regparm parameters: - f(e1,e2). We need to compute e1 into %eax and e2 into %edx. - Suppose code is first generated to compute e1 into %eax. Then, - code is generated to compute e2 into %edx. Unfortunately, if - the latter code sequence uses %eax, it will trash the value of - e1 computed by the former sequence. This could happen if (for - example) e2 itself involved a function call. In the code below, - args are evaluated right-to-left, not left-to-right, but the - principle and the problem are the same. - - One solution is to compute all regparm-bound args into vregs - first, and once they are all done, move them to the relevant - real regs. This always gives correct code, but it also gives - a bunch of vreg-to-rreg moves which are usually redundant but - are hard for the register allocator to get rid of. - - A compromise is to first examine all regparm'd argument - expressions. If they are all so simple that it is clear - they will be evaluated without use of any fixed registers, - use the old compute-directly-to-fixed-target scheme. If not, - be safe and use the via-vregs scheme. + HReg argregs[ARM_N_ARGREGS]; + HReg tmpregs[ARM_N_ARGREGS]; + Bool go_fast; + Int n_args, i, nextArgReg; + ULong target; + + vassert(ARM_N_ARGREGS == 4); + + /* Marshal args for a call and do the call. + + If passBBP is True, r8 (the baseblock pointer) is to be passed + as the first arg. + + This function only deals with a tiny set of possibilities, which + cover all helpers in practice. The restrictions are that only + arguments in registers are supported, hence only ARM_N_REGPARMS + x 32 integer bits in total can be passed. In fact the only + supported arg types are I32 and I64. + + Generating code which is both efficient and correct when + parameters are to be passed in registers is difficult, for the + reasons elaborated in detail in comments attached to + doHelperCall() in priv/host-x86/isel.c. Here, we use a variant + of the method described in those comments. + + The problem is split into two cases: the fast scheme and the + slow scheme. In the fast scheme, arguments are computed + directly into the target (real) registers. This is only safe + when we can be sure that computation of each argument will not + trash any real registers set by computation of any other + argument. + + In the slow scheme, all args are first computed into vregs, and + once they are all done, they are moved to the relevant real + regs. This always gives correct code, but it also gives a bunch + of vreg-to-rreg moves which are usually redundant but are hard + for the register allocator to get rid of. + + To decide which scheme to use, all argument expressions are + first examined. If they are all so simple that it is clear they + will be evaluated without use of any fixed registers, use the + fast scheme, else use the slow scheme. Note also that only + unconditional calls may use the fast scheme, since having to + compute a condition expression could itself trash real + registers. Note this requires being able to examine an expression and determine whether or not evaluation of it might use a fixed - register. That requires knowledge of how the rest of this - insn selector works. Currently just the following 3 are - regarded as safe -- hopefully they cover the majority of - arguments in practice: IRExpr_Tmp IRExpr_Const IRExpr_Get. + register. That requires knowledge of how the rest of this insn + selector works. Currently just the following 3 are regarded as + safe -- hopefully they cover the majority of arguments in + practice: IRExpr_Tmp IRExpr_Const IRExpr_Get. */ - vassert(cee->regparms >= 0 && cee->regparms <= 3); - - n_args = n_arg_ws = 0; - while (args[n_args]) n_args++; - not_done_yet = n_args; - if (passBBP) - not_done_yet++; + /* Note that the cee->regparms field is meaningless on ARM hosts + (since there is only one calling convention) and so we always + ignore it. */ - stack_limit = cee->regparms; - if (cee->regparms > 0 && passBBP) stack_limit--; + n_args = 0; + for (i = 0; args[i]; i++) + n_args++; - /* ------ BEGIN marshall all arguments ------ */ + argregs[0] = hregARM_R0(); + argregs[1] = hregARM_R1(); + argregs[2] = hregARM_R2(); + argregs[3] = hregARM_R3(); - /* Push (R to L) the stack-passed args, [n_args-1 .. stack_limit] */ - for (i = n_args-1; i >= stack_limit; i--) { - n_arg_ws += pushArg(env, args[i]); - not_done_yet--; - } - - /* args [stack_limit-1 .. 0] and possibly %ebp are to be passed in - registers. */ + tmpregs[0] = tmpregs[1] = tmpregs[2] = + tmpregs[3] = INVALID_HREG; - if (cee->regparms > 0) { + /* First decide which scheme (slow or fast) is to be used. First + assume the fast scheme, and select slow if any contraindications + (wow) appear. */ - /* ------ BEGIN deal with regparms ------ */ + go_fast = True; - /* deal with regparms, not forgetting %ebp if needed. */ - argregs[0] = hregX86_EAX(); - argregs[1] = hregX86_EDX(); - argregs[2] = hregX86_ECX(); - tmpregs[0] = tmpregs[1] = tmpregs[2] = INVALID_HREG; - - argreg = cee->regparms; + if (guard) { + if (guard->tag == Iex_Const + && guard->Iex.Const.con->tag == Ico_U1 + && guard->Iex.Const.con->Ico.U1 == True) { + /* unconditional */ + } else { + /* Not manifestly unconditional -- be conservative. */ + go_fast = False; + } + } - /* In keeping with big comment above, detect potential danger - and use the via-vregs scheme if needed. */ - danger = False; - for (i = stack_limit-1; i >= 0; i--) { + if (go_fast) { + for (i = 0; i < n_args; i++) { if (mightRequireFixedRegs(args[i])) { - danger = True; + go_fast = False; break; } } + } + /* At this point the scheme to use has been established. Generate + code to get the arg values into the argument rregs. If we run + out of arg regs, give up. */ - if (danger) { - - /* Move via temporaries */ - argregX = argreg; - for (i = stack_limit-1; i >= 0; i--) { + if (go_fast) { - if (0) { - vex_printf("x86 host: register param is complex: "); - ppIRExpr(args[i]); - vex_printf("\n"); - } + /* FAST SCHEME */ + nextArgReg = 0; + if (passBBP) { + addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], + hregARM_R8() )); + nextArgReg++; + } - argreg--; - vassert(argreg >= 0); - vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I32); - tmpregs[argreg] = iselIntExpr_R(env, args[i]); - not_done_yet--; + for (i = 0; i < n_args; i++) { + IRType aTy = typeOfIRExpr(env->type_env, args[i]); + if (nextArgReg >= ARM_N_ARGREGS) + return False; /* out of argregs */ + if (aTy == Ity_I32) { + addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], + iselIntExpr_R(env, args[i]) )); + nextArgReg++; } - for (i = stack_limit-1; i >= 0; i--) { - argregX--; - vassert(argregX >= 0); - addInstr( env, mk_iMOVsd_RR( tmpregs[argregX], argregs[argregX] ) ); - } - - } else { - /* It's safe to compute all regparm args directly into their - target registers. */ - for (i = stack_limit-1; i >= 0; i--) { - argreg--; - vassert(argreg >= 0); - vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I32); - addInstr(env, X86Instr_Alu32R(Xalu_MOV, - iselIntExpr_RMI(env, args[i]), - argregs[argreg])); - not_done_yet--; + else if (aTy == Ity_I64) { + /* 64-bit args must be passed in an a reg-pair of the form + n:n+1, where n is even. Hence either r0:r1 or r2:r3. + On a little-endian host, the less significant word is + passed in the lower-numbered register. */ + if (nextArgReg & 1) { + if (nextArgReg >= ARM_N_ARGREGS) + return False; /* out of argregs */ + addInstr(env, ARMInstr_Imm32( argregs[nextArgReg], 0xAA )); + nextArgReg++; + } + if (nextArgReg >= ARM_N_ARGREGS) + return False; /* out of argregs */ + HReg raHi, raLo; + iselInt64Expr(&raHi, &raLo, env, args[i]); + addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], raLo )); + nextArgReg++; + addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], raHi )); + nextArgReg++; } - - } - - /* Not forgetting %ebp if needed. */ - if (passBBP) { - vassert(argreg == 1); - addInstr(env, mk_iMOVsd_RR( hregX86_EBP(), argregs[0])); - not_done_yet--; + else + return False; /* unhandled arg type */ } - /* ------ END deal with regparms ------ */ + /* Fast scheme only applies for unconditional calls. Hence: */ + cc = ARMcc_AL; } else { - /* No regparms. Heave %ebp on the stack if needed. */ + /* SLOW SCHEME; move via temporaries */ + nextArgReg = 0; + if (passBBP) { - addInstr(env, X86Instr_Push(X86RMI_Reg(hregX86_EBP()))); - n_arg_ws++; - not_done_yet--; + /* This is pretty stupid; better to move directly to r0 + after the rest of the args are done. */ + tmpregs[nextArgReg] = newVRegI(env); + addInstr(env, mk_iMOVds_RR( tmpregs[nextArgReg], + hregARM_R8() )); + nextArgReg++; } - } - - vassert(not_done_yet == 0); - - /* ------ END marshall all arguments ------ */ - - /* Now we can compute the condition. We can't do it earlier - because the argument computations could trash the condition - codes. Be a bit clever to handle the common case where the - guard is 1:Bit. */ - cc = Xcc_ALWAYS; - if (guard) { - if (guard->tag == Iex_Const - && guard->Iex.Const.con->tag == Ico_U1 - && guard->Iex.Const.con->Ico.U1 == True) { - /* unconditional -- do nothing */ - } else { - cc = iselCondCode( env, guard ); + for (i = 0; i < n_args; i++) { + IRType aTy = typeOfIRExpr(env->type_env, args[i]); + if (nextArgReg >= ARM_N_ARGREGS) + return False; /* out of argregs */ + if (aTy == Ity_I32) { + tmpregs[nextArgReg] = iselIntExpr_R(env, args[i]); + nextArgReg++; + } + else if (aTy == Ity_I64) { + /* Same comment applies as in the Fast-scheme case. */ + if (nextArgReg & 1) + nextArgReg++; + if (nextArgReg + 1 >= ARM_N_ARGREGS) + return False; /* out of argregs */ + HReg raHi, raLo; + iselInt64Expr(&raHi, &raLo, env, args[i]); + tmpregs[nextArgReg] = raLo; + nextArgReg++; + tmpregs[nextArgReg] = raHi; + nextArgReg++; + } } - } - - /* call the helper, and get the args off the stack afterwards. */ - callHelperAndClearArgs( env, cc, cee, n_arg_ws ); -#endif -} - - - -// CAB: Do we need to deal with elemSz != 8 ? -/* Given a guest-state array descriptor, an index expression and a - bias, generate an ARMAMode holding the relevant guest state - offset. */ - -static -ARMAMode2* genGuestArrayOffset ( ISelEnv* env, IRRegArray* descr, - IRExpr* off, Int bias ) -{ - HReg tmp, tmp2, roff; - Int elemSz = sizeofIRType(descr->elemTy); - Int nElems = descr->nElems; - ARMImm12A imm12a; - - /* throw out any cases not generated by an x86 front end. In - theory there might be a day where we need to handle them -- if - we ever run non-x86-guest on x86 host. */ - - if (nElems != 8 || (elemSz != 1 && elemSz != 8)) - vpanic("genGuestArrayOffset(arm host)"); + /* Now we can compute the condition. We can't do it earlier + because the argument computations could trash the condition + codes. Be a bit clever to handle the common case where the + guard is 1:Bit. */ + cc = ARMcc_AL; + if (guard) { + if (guard->tag == Iex_Const + && guard->Iex.Const.con->tag == Ico_U1 + && guard->Iex.Const.con->Ico.U1 == True) { + /* unconditional -- do nothing */ + } else { + cc = iselCondCode( env, guard ); + } + } - /* Compute off into a reg, %off. Then return: + /* Move the args to their final destinations. */ + for (i = 0; i < nextArgReg; i++) { + if (tmpregs[i] == INVALID_HREG) { // Skip invalid regs + addInstr(env, ARMInstr_Imm32( argregs[i], 0xAA )); + continue; + } + /* None of these insns, including any spill code that might + be generated, may alter the condition codes. */ + addInstr( env, mk_iMOVds_RR( argregs[i], tmpregs[i] ) ); + } - movl %off, %tmp - addl $bias, %tmp (if bias != 0) - andl %tmp, 7 - ... base(%ebp, %tmp, shift) ... - */ - tmp = newVRegI(env); - roff = iselIntExpr_R(env, off); - addInstr(env, mk_iMOVsd_RR(roff, tmp)); - if (bias != 0) { - if ( mk_ARMImm12A( (UInt)bias, &imm12a ) ) { - addInstr(env, ARMInstr_DPInstr2(ARMalu_ADD, tmp, tmp, - ARMAMode1_I12A( imm12a ))); - } else { - HReg tmp3 = newVRegI(env); - addInstr(env, ARMInstr_Literal( tmp, (UInt)bias )); - addInstr(env, ARMInstr_DPInstr2(ARMalu_ADD, tmp, tmp, - ARMAMode1_ShlI( tmp3, 0 ))); - } } - mk_ARMImm12A( (UInt)7, &imm12a ); - addInstr(env, ARMInstr_DPInstr2(ARMalu_AND, tmp, tmp, - ARMAMode1_I12A( imm12a ))); - vassert(elemSz == 1 || elemSz == 8); - - - -// CAB: This anywhere near correct? - -// X86AMode_IRRS: Immediate + Reg1 + (Reg2 << Shift) -// return X86AMode_IRRS( descr->base, hregX86_EBP(), tmp, elemSz==8 ? 3 : 0); - - tmp2 = newVRegI(env); // tmp2 = GET_BP_REG + (tmp << 3|0) - addInstr(env, ARMInstr_DPInstr2(ARMalu_ADD, tmp2, GET_BP_REG(), - ARMAMode1_ShlI(tmp, elemSz==8 ? 3 : 0))); - return ARMAMode2_RI( tmp2, descr->base ); + /* Should be assured by checks above */ + vassert(nextArgReg <= ARM_N_ARGREGS); + + target = (HWord)Ptr_to_ULong(cee->addr); + + /* nextArgReg doles out argument registers. Since these are + assigned in the order r0, r1, r2, r3, its numeric value at this + point, which must be between 0 and 4 inclusive, is going to be + equal to the number of arg regs in use for the call. Hence bake + that number into the call (we'll need to know it when doing + register allocation, to know what regs the call reads.) + + There is a bit of a twist -- harmless but worth recording. + Suppose the arg types are (Ity_I32, Ity_I64). Then we will have + the first arg in r0 and the second in r3:r2, but r1 isn't used. + We nevertheless have nextArgReg==4 and bake that into the call + instruction. This will mean the register allocator wil believe + this insn reads r1 when in fact it doesn't. But that's + harmless; it just artificially extends the live range of r1 + unnecessarily. The best fix would be to put into the + instruction, a bitmask indicating which of r0/1/2/3 carry live + values. But that's too much hassle. */ + + /* Finally, the call itself. */ + addInstr(env, ARMInstr_Call( cc, target, nextArgReg )); + + return True; /* success */ } /*---------------------------------------------------------*/ -/*--- ISEL ... ---*/ +/*--- ISEL: Integer expressions (32/16/8 bit) ---*/ /*---------------------------------------------------------*/ -/* --------------------- AMODEs --------------------- */ +/* Select insns for an integer-typed expression, and add them to the + code list. Return a reg holding the result. This reg will be a + virtual register. THE RETURNED REG MUST NOT BE MODIFIED. If you + want to modify it, ask for a new vreg, copy it in there, and modify + the copy. The register allocator will do its best to map both + vregs to the same real register, so the copies will often disappear + later in the game. + + This should handle expressions of 32, 16 and 8-bit type. All + results are returned in a 32-bit register. For 16- and 8-bit + expressions, the upper 16/24 bits are arbitrary, so you should mask + or sign extend partial values if necessary. +*/ + +/* --------------------- AMode1 --------------------- */ -/* Return an AMode which computes the value of the specified +/* Return an AMode1 which computes the value of the specified expression, possibly also adding insns to the code list as a - result. + result. The expression may only be a 32-bit one. */ -/* ---------------- Addressing Mode 1 ---------------- */ - static Bool sane_AMode1 ( ARMAMode1* am ) { - switch (am->tag) { - default: - vpanic("sane_AMode1: unknown arm amode tag"); - } + switch (am->tag) { + case ARMam1_RI: + return + toBool( hregClass(am->ARMam1.RI.reg) == HRcInt32 + && (hregIsVirtual(am->ARMam1.RI.reg) + || am->ARMam1.RI.reg == hregARM_R8()) + && am->ARMam1.RI.simm13 >= -4095 + && am->ARMam1.RI.simm13 <= 4095 ); + case ARMam1_RRS: + return + toBool( hregClass(am->ARMam1.RRS.base) == HRcInt32 + && hregIsVirtual(am->ARMam1.RRS.base) + && hregClass(am->ARMam1.RRS.index) == HRcInt32 + && hregIsVirtual(am->ARMam1.RRS.index) + && am->ARMam1.RRS.shift >= 0 + && am->ARMam1.RRS.shift <= 3 ); + default: + vpanic("sane_AMode: unknown ARM AMode1 tag"); + } } static ARMAMode1* iselIntExpr_AMode1 ( ISelEnv* env, IRExpr* e ) { - ARMAMode1* am = iselIntExpr_AMode1_wrk(env, e); - vassert(sane_AMode1(am)); - return am; + ARMAMode1* am = iselIntExpr_AMode1_wrk(env, e); + vassert(sane_AMode1(am)); + return am; } -/* DO NOT CALL THIS DIRECTLY ! */ static ARMAMode1* iselIntExpr_AMode1_wrk ( ISelEnv* env, IRExpr* e ) { - IRType ty = typeOfIRExpr(env->type_env,e); - vassert(ty == Ity_I32); - - // ARMam1_I12A, /* Imm12A: extended (rotated) immedate */ - // ARMam1_ShlI, /* ShlI reg Imm5 */ - // ARMam1_ShrI, /* ShrI reg Imm5 */ - // ARMam1_SarI, /* SarI reg Imm5 */ - // ARMam1_ShlR, /* ShlR reg reg */ - // ARMam1_ShrR, /* ShrR reg reg */ - // ARMam1_SarR, /* SarR reg reg */ - - // ALU ops: - /* - ARMalu_And, ARMalu_Orr, ARMalu_Eor, ARMalu_Bic, // Logic - ARMalu_Sub, ARMalu_Rsb, ARMalu_Add, ARMalu_Adc, ARMalu_Sbc, ARMalu_Rsc, // Arith - ARMalu_Tst, ARMalu_Teq, ARMalu_Cmp, ARMalu_Cmn, // test - ARMalu_Mov, ARMalu_Mvn // Move - */ + IRType ty = typeOfIRExpr(env->type_env,e); + vassert(ty == Ity_I32); + + /* FIXME: add RRS matching */ + + /* {Add32,Sub32}(expr,simm13) */ + if (e->tag == Iex_Binop + && (e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Sub32) + && e->Iex.Binop.arg2->tag == Iex_Const + && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32) { + Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; + if (simm >= -4095 && simm <= 4095) { + HReg reg; + if (e->Iex.Binop.op == Iop_Sub32) + simm = -simm; + reg = iselIntExpr_R(env, e->Iex.Binop.arg1); + return ARMAMode1_RI(reg, simm); + } + } + /* Doesn't match anything in particular. Generate it into + a register and use that. */ + { + HReg reg = iselIntExpr_R(env, e); + return ARMAMode1_RI(reg, 0); + } - return NULL; } +/* --------------------- AMode2 --------------------- */ -/* ---------------- Addressing Mode 2 ---------------- */ +/* Return an AMode2 which computes the value of the specified + expression, possibly also adding insns to the code list as a + result. The expression may only be a 32-bit one. +*/ -__attribute__((unused)) static Bool sane_AMode2 ( ARMAMode2* am ) { switch (am->tag) { - default: - vpanic("sane_AMode2: unknown arm amode tag"); + case ARMam2_RI: + return + toBool( hregClass(am->ARMam2.RI.reg) == HRcInt32 + && hregIsVirtual(am->ARMam2.RI.reg) + && am->ARMam2.RI.simm9 >= -255 + && am->ARMam2.RI.simm9 <= 255 ); + case ARMam2_RR: + return + toBool( hregClass(am->ARMam2.RR.base) == HRcInt32 + && hregIsVirtual(am->ARMam2.RR.base) + && hregClass(am->ARMam2.RR.index) == HRcInt32 + && hregIsVirtual(am->ARMam2.RR.index) ); + default: + vpanic("sane_AMode: unknown ARM AMode2 tag"); } } -/* Apparently unused -static ARMAMode2* iselIntExpr_AMode2_wrk ( ISelEnv* env, IRExpr* e ) +static ARMAMode2* iselIntExpr_AMode2 ( ISelEnv* env, IRExpr* e ) { - ARMAMode2* am = iselIntExpr_AMode2_wrk(env, e); - vassert(sane_AMode2(am)); - return am; + ARMAMode2* am = iselIntExpr_AMode2_wrk(env, e); + vassert(sane_AMode2(am)); + return am; } -*/ -/* DO NOT CALL THIS DIRECTLY ! */ -static ARMAMode2* iselIntExpr_AMode2 ( ISelEnv* env, IRExpr* e ) -{ - IRType ty = typeOfIRExpr(env->type_env,e); - vassert(ty == Ity_I32); +static ARMAMode2* iselIntExpr_AMode2_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env,e); + vassert(ty == Ity_I32); + + /* FIXME: add RR matching */ + + /* {Add32,Sub32}(expr,simm8) */ + if (e->tag == Iex_Binop + && (e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Sub32) + && e->Iex.Binop.arg2->tag == Iex_Const + && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32) { + Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; + if (simm >= -255 && simm <= 255) { + HReg reg; + if (e->Iex.Binop.op == Iop_Sub32) + simm = -simm; + reg = iselIntExpr_R(env, e->Iex.Binop.arg1); + return ARMAMode2_RI(reg, simm); + } + } - // ARMam2_RI, /* Reg +/- Imm12 */ - // ARMam2_RR, /* Reg +/- Reg */ - // ARMam2_RRS, /* Reg +/- (Reg << Imm5) */ + /* Doesn't match anything in particular. Generate it into + a register and use that. */ + { + HReg reg = iselIntExpr_R(env, e); + return ARMAMode2_RI(reg, 0); + } - return NULL; } +/* --------------------- AModeV --------------------- */ -/* ---------------- Addressing Mode 3 ---------------- */ +/* Return an AModeV which computes the value of the specified + expression, possibly also adding insns to the code list as a + result. The expression may only be a 32-bit one. +*/ -static Bool sane_AMode3 ( ARMAMode3* am ) +static Bool sane_AModeV ( ARMAModeV* am ) { - switch (am->tag) { - default: - vpanic("sane_AMode3: unknown arm amode tag"); - } + return toBool( hregClass(am->reg) == HRcInt32 + && hregIsVirtual(am->reg) + && am->simm11 >= -1020 && am->simm11 <= 1020 + && 0 == (am->simm11 & 3) ); } -static ARMAMode3* iselIntExpr_AMode3 ( ISelEnv* env, IRExpr* e ) +static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e ) { - ARMAMode3* am = iselIntExpr_AMode3_wrk(env, e); - vassert(sane_AMode3(am)); - return am; + ARMAModeV* am = iselIntExpr_AModeV_wrk(env, e); + vassert(sane_AModeV(am)); + return am; } -/* DO NOT CALL THIS DIRECTLY ! */ -static ARMAMode3* iselIntExpr_AMode3_wrk ( ISelEnv* env, IRExpr* e ) -{ - IRType ty = typeOfIRExpr(env->type_env,e); - vassert(ty == Ity_I32); +static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env,e); + vassert(ty == Ity_I32); + + /* {Add32,Sub32}(expr, simm8 << 2) */ + if (e->tag == Iex_Binop + && (e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Sub32) + && e->Iex.Binop.arg2->tag == Iex_Const + && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32) { + Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; + if (simm >= -1020 && simm <= 1020 && 0 == (simm & 3)) { + HReg reg; + if (e->Iex.Binop.op == Iop_Sub32) + simm = -simm; + reg = iselIntExpr_R(env, e->Iex.Binop.arg1); + return mkARMAModeV(reg, simm); + } + } + + /* Doesn't match anything in particular. Generate it into + a register and use that. */ + { + HReg reg = iselIntExpr_R(env, e); + return mkARMAModeV(reg, 0); + } - // ARMam3_RI, /* Reg +/- Imm8 */ - // ARMam3_RR, /* Reg +/- Reg */ +} + +/* -------------------- AModeN -------------------- */ - return NULL; +static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e ) +{ + return iselIntExpr_AModeN_wrk(env, e); } +static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e ) +{ + HReg reg = iselIntExpr_R(env, e); + return mkARMAModeN_R(reg); +} -/* ---------------- Branch Destination ---------------- */ +/* --------------------- RI84 --------------------- */ -static ARMBranchDest* iselIntExpr_BD ( ISelEnv* env, IRExpr* e ) +/* Select instructions to generate 'e' into a RI84. If mayInv is + true, then the caller will also accept an I84 form that denotes + 'not e'. In this case didInv may not be NULL, and *didInv is set + to True. This complication is so as to allow generation of an RI84 + which is suitable for use in either an AND or BIC instruction, + without knowing (before this call) which one. +*/ +static ARMRI84* iselIntExpr_RI84 ( /*OUT*/Bool* didInv, Bool mayInv, + ISelEnv* env, IRExpr* e ) { - ARMBranchDest* bd = iselIntExpr_BD_wrk(env, e); - /* sanity checks ... */ - switch (bd->tag) { - case ARMbdImm: - return bd; - case ARMbdReg: - vassert(hregClass(bd->ARMbd.Reg.reg) == HRcInt32); -// vassert(hregIsVirtual(bd->ARMbd.Reg.reg)); // CAB ? - return bd; - default: - vpanic("iselIntExpr_BD: unknown arm BD tag"); + ARMRI84* ri; + if (mayInv) + vassert(didInv != NULL); + ri = iselIntExpr_RI84_wrk(didInv, mayInv, env, e); + /* sanity checks ... */ + switch (ri->tag) { + case ARMri84_I84: + return ri; + case ARMri84_R: + vassert(hregClass(ri->ARMri84.R.reg) == HRcInt32); + vassert(hregIsVirtual(ri->ARMri84.R.reg)); + return ri; + default: + vpanic("iselIntExpr_RI84: unknown arm RI84 tag"); } } /* DO NOT CALL THIS DIRECTLY ! */ -static ARMBranchDest* iselIntExpr_BD_wrk ( ISelEnv* env, IRExpr* e ) +static ARMRI84* iselIntExpr_RI84_wrk ( /*OUT*/Bool* didInv, Bool mayInv, + ISelEnv* env, IRExpr* e ) { - /* - ARMbdImm, - ARMbdReg - */ + IRType ty = typeOfIRExpr(env->type_env,e); + vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8); + + if (didInv) *didInv = False; + + /* special case: immediate */ + if (e->tag == Iex_Const) { + UInt u, u8 = 0x100, u4 = 0x10; /* both invalid */ + switch (e->Iex.Const.con->tag) { + case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; + case Ico_U16: u = 0xFFFF & (e->Iex.Const.con->Ico.U16); break; + case Ico_U8: u = 0xFF & (e->Iex.Const.con->Ico.U8); break; + default: vpanic("iselIntExpr_RI84.Iex_Const(armh)"); + } + if (fitsIn8x4(&u8, &u4, u)) { + return ARMRI84_I84( (UShort)u8, (UShort)u4 ); + } + if (mayInv && fitsIn8x4(&u8, &u4, ~u)) { + vassert(didInv); + *didInv = True; + return ARMRI84_I84( (UShort)u8, (UShort)u4 ); + } + /* else fail, fall through to default case */ + } - return NULL; + /* default case: calculate into a register and return that */ + { + HReg r = iselIntExpr_R ( env, e ); + return ARMRI84_R(r); + } } +/* --------------------- RI5 --------------------- */ + +/* Select instructions to generate 'e' into a RI5. */ + +static ARMRI5* iselIntExpr_RI5 ( ISelEnv* env, IRExpr* e ) +{ + ARMRI5* ri = iselIntExpr_RI5_wrk(env, e); + /* sanity checks ... */ + switch (ri->tag) { + case ARMri5_I5: + return ri; + case ARMri5_R: + vassert(hregClass(ri->ARMri5.R.reg) == HRcInt32); + vassert(hregIsVirtual(ri->ARMri5.R.reg)); + return ri; + default: + vpanic("iselIntExpr_RI5: unknown arm RI5 tag"); + } +} + +/* DO NOT CALL THIS DIRECTLY ! */ +static ARMRI5* iselIntExpr_RI5_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env,e); + vassert(ty == Ity_I32 || ty == Ity_I8); + + /* special case: immediate */ + if (e->tag == Iex_Const) { + UInt u; /* both invalid */ + switch (e->Iex.Const.con->tag) { + case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; + case Ico_U16: u = 0xFFFF & (e->Iex.Const.con->Ico.U16); break; + case Ico_U8: u = 0xFF & (e->Iex.Const.con->Ico.U8); break; + default: vpanic("iselIntExpr_RI5.Iex_Const(armh)"); + } + if (u >= 1 && u <= 31) { + return ARMRI5_I5(u); + } + /* else fail, fall through to default case */ + } + /* default case: calculate into a register and return that */ + { + HReg r = iselIntExpr_R ( env, e ); + return ARMRI5_R(r); + } +} -/* --------------------- CONDCODE --------------------- */ +/* ------------------- CondCode ------------------- */ /* Generate code to evaluated a bit-typed expression, returning the condition code which would correspond when the expression would @@ -706,126 +950,4765 @@ static ARMBranchDest* iselIntExpr_BD_wrk ( ISelEnv* env, IRExpr* e ) static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e ) { - /* Uh, there's nothing we can sanity check here, unfortunately. */ - return iselCondCode_wrk(env, e); + ARMCondCode cc = iselCondCode_wrk(env,e); + vassert(cc != ARMcc_NV); + return cc; } -/* DO NOT CALL THIS DIRECTLY ! */ static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) { -#if 0 - MatchInfo mi; - DECLARE_PATTERN(p_32to1); - DECLARE_PATTERN(p_1Uto32_then_32to1); -#endif + vassert(e); + vassert(typeOfIRExpr(env->type_env,e) == Ity_I1); + + /* var */ + if (e->tag == Iex_RdTmp) { + HReg rTmp = lookupIRTemp(env, e->Iex.RdTmp.tmp); + /* CmpOrTst doesn't modify rTmp; so this is OK. */ + ARMRI84* one = ARMRI84_I84(1,0); + addInstr(env, ARMInstr_CmpOrTst(False/*test*/, rTmp, one)); + return ARMcc_NE; + } + + /* Not1(e) */ + if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) { + /* Generate code for the arg, and negate the test condition */ + return 1 ^ iselCondCode(env, e->Iex.Unop.arg); + } + + /* --- patterns rooted at: 32to1 --- */ + + if (e->tag == Iex_Unop + && e->Iex.Unop.op == Iop_32to1) { + HReg rTmp = iselIntExpr_R(env, e->Iex.Unop.arg); + ARMRI84* one = ARMRI84_I84(1,0); + addInstr(env, ARMInstr_CmpOrTst(False/*test*/, rTmp, one)); + return ARMcc_NE; + } + + /* --- patterns rooted at: CmpNEZ8 --- */ - return 0; + if (e->tag == Iex_Unop + && e->Iex.Unop.op == Iop_CmpNEZ8) { + HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); + ARMRI84* xFF = ARMRI84_I84(0xFF,0); + addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r1, xFF)); + return ARMcc_NE; + } + + /* --- patterns rooted at: CmpNEZ32 --- */ + + if (e->tag == Iex_Unop + && e->Iex.Unop.op == Iop_CmpNEZ32) { + HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); + ARMRI84* zero = ARMRI84_I84(0,0); + addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, r1, zero)); + return ARMcc_NE; + } + + /* --- patterns rooted at: CmpNEZ64 --- */ + + if (e->tag == Iex_Unop + && e->Iex.Unop.op == Iop_CmpNEZ64) { + HReg tHi, tLo; + HReg tmp = newVRegI(env); + ARMRI84* zero = ARMRI84_I84(0,0); + iselInt64Expr(&tHi, &tLo, env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_Alu(ARMalu_OR, tmp, tHi, ARMRI84_R(tLo))); + addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, tmp, zero)); + return ARMcc_NE; + } + + /* --- Cmp*32*(x,y) --- */ + if (e->tag == Iex_Binop + && (e->Iex.Binop.op == Iop_CmpEQ32 + || e->Iex.Binop.op == Iop_CmpNE32 + || e->Iex.Binop.op == Iop_CmpLT32S + || e->Iex.Binop.op == Iop_CmpLT32U + || e->Iex.Binop.op == Iop_CmpLE32S + || e->Iex.Binop.op == Iop_CmpLE32U)) { + HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); + ARMRI84* argR = iselIntExpr_RI84(NULL,False, + env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL, argR)); + switch (e->Iex.Binop.op) { + case Iop_CmpEQ32: return ARMcc_EQ; + case Iop_CmpNE32: return ARMcc_NE; + case Iop_CmpLT32S: return ARMcc_LT; + case Iop_CmpLT32U: return ARMcc_LO; + case Iop_CmpLE32S: return ARMcc_LE; + case Iop_CmpLE32U: return ARMcc_LS; + default: vpanic("iselCondCode(arm): CmpXX32"); + } + } + + /* --- CasCmpEQ* --- */ + /* Ist_Cas has a dummy argument to compare with, so comparison is + always true. */ + if (e->tag == Iex_Binop + && (e->Iex.Binop.op == Iop_CasCmpEQ32 + || e->Iex.Binop.op == Iop_CasCmpEQ16 + || e->Iex.Binop.op == Iop_CasCmpEQ8)) { + return ARMcc_AL; + } + + ppIRExpr(e); + vpanic("iselCondCode"); } +/* --------------------- Reg --------------------- */ static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ) { - return iselIntExpr_R_wrk(env, e); + HReg r = iselIntExpr_R_wrk(env, e); + /* sanity checks ... */ +# if 0 + vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); +# endif + vassert(hregClass(r) == HRcInt32); + vassert(hregIsVirtual(r)); + return r; } /* DO NOT CALL THIS DIRECTLY ! */ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) { - return 0; -} - + IRType ty = typeOfIRExpr(env->type_env,e); + vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8); +// vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8); + switch (e->tag) { -/*---------------------------------------------------------*/ -/*--- ISEL: Statements ---*/ -/*---------------------------------------------------------*/ - -static void iselStmt ( ISelEnv* env, IRStmt* stmt ) -{ - if (vex_traceflags & VEX_TRACE_VCODE) { - vex_printf("\n-- "); - ppIRStmt(stmt); - vex_printf("\n"); + /* --------- TEMP --------- */ + case Iex_RdTmp: { + return lookupIRTemp(env, e->Iex.RdTmp.tmp); } - switch (stmt->tag) { - /* --------- STORE --------- */ - /* little-endian write to memory */ - case Ist_Store: { - HReg reg; - IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr); - IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); - IREndness end = stmt->Ist.Store.end; - IRTemp resSC = stmt->Ist.Store.resSC; + /* --------- LOAD --------- */ + case Iex_Load: { + HReg dst = newVRegI(env); - if (tya != Ity_I32 || end != Iend_LE || resSC != IRTemp_INVALID) - goto stmt_fail; + if (e->Iex.Load.end != Iend_LE) + goto irreducible; - reg = iselIntExpr_R(env, stmt->Ist.Store.data); + if (ty == Ity_I32) { + ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr ); + addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, dst, amode)); + return dst; + } + if (ty == Ity_I16) { + ARMAMode2* amode = iselIntExpr_AMode2 ( env, e->Iex.Load.addr ); + addInstr(env, ARMInstr_LdSt16(True/*isLoad*/, False/*!signedLoad*/, + dst, amode)); + return dst; + } + if (ty == Ity_I8) { + ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr ); + addInstr(env, ARMInstr_LdSt8U(True/*isLoad*/, dst, amode)); + return dst; + } - if (tyd == Ity_I8) { - ARMAMode2* am2 = iselIntExpr_AMode2(env, stmt->Ist.Store.addr); - addInstr(env, ARMInstr_StoreB(reg,am2)); - return; - } - if (tyd == Ity_I16) { - ARMAMode3* am3 = iselIntExpr_AMode3(env, stmt->Ist.Store.addr); - addInstr(env, ARMInstr_StoreH(reg,am3)); - return; - } - if (tyd == Ity_I32) { - ARMAMode2* am2 = iselIntExpr_AMode2(env, stmt->Ist.Store.addr); - addInstr(env, ARMInstr_StoreW(reg,am2)); - return; - } +//zz if (ty == Ity_I16) { +//zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst)); +//zz return dst; +//zz } +//zz if (ty == Ity_I8) { +//zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst)); +//zz return dst; +//zz } + break; + } + +//zz /* --------- TERNARY OP --------- */ +//zz case Iex_Triop: { +//zz /* C3210 flags following FPU partial remainder (fprem), both +//zz IEEE compliant (PREM1) and non-IEEE compliant (PREM). */ +//zz if (e->Iex.Triop.op == Iop_PRemC3210F64 +//zz || e->Iex.Triop.op == Iop_PRem1C3210F64) { +//zz HReg junk = newVRegF(env); +//zz HReg dst = newVRegI(env); +//zz HReg srcL = iselDblExpr(env, e->Iex.Triop.arg2); +//zz HReg srcR = iselDblExpr(env, e->Iex.Triop.arg3); +//zz /* XXXROUNDINGFIXME */ +//zz /* set roundingmode here */ +//zz addInstr(env, X86Instr_FpBinary( +//zz e->Iex.Binop.op==Iop_PRemC3210F64 +//zz ? Xfp_PREM : Xfp_PREM1, +//zz srcL,srcR,junk +//zz )); +//zz /* The previous pseudo-insn will have left the FPU's C3210 +//zz flags set correctly. So bag them. */ +//zz addInstr(env, X86Instr_FpStSW_AX()); +//zz addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), dst)); +//zz addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0x4700), dst)); +//zz return dst; +//zz } +//zz +//zz break; +//zz } + + /* --------- BINARY OP --------- */ + case Iex_Binop: { + + ARMAluOp aop = 0; /* invalid */ + ARMShiftOp sop = 0; /* invalid */ + + /* ADD/SUB/AND/OR/XOR */ + switch (e->Iex.Binop.op) { + case Iop_And32: { + Bool didInv = False; + HReg dst = newVRegI(env); + HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); + ARMRI84* argR = iselIntExpr_RI84(&didInv, True/*mayInv*/, + env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_Alu(didInv ? ARMalu_BIC : ARMalu_AND, + dst, argL, argR)); + return dst; + } + case Iop_Or32: aop = ARMalu_OR; goto std_binop; + case Iop_Xor32: aop = ARMalu_XOR; goto std_binop; + case Iop_Sub32: aop = ARMalu_SUB; goto std_binop; + case Iop_Add32: aop = ARMalu_ADD; goto std_binop; + std_binop: { + HReg dst = newVRegI(env); + HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); + ARMRI84* argR = iselIntExpr_RI84(NULL, False/*mayInv*/, + env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_Alu(aop, dst, argL, argR)); + return dst; + } + default: break; + } + + /* SHL/SHR/SAR */ + switch (e->Iex.Binop.op) { + case Iop_Shl32: sop = ARMsh_SHL; goto sh_binop; + case Iop_Shr32: sop = ARMsh_SHR; goto sh_binop; + case Iop_Sar32: sop = ARMsh_SAR; goto sh_binop; + sh_binop: { + HReg dst = newVRegI(env); + HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); + ARMRI5* argR = iselIntExpr_RI5(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_Shift(sop, dst, argL, argR)); + vassert(ty == Ity_I32); /* else the IR is ill-typed */ + return dst; + } + default: break; + } + + /* MUL */ + if (e->Iex.Binop.op == Iop_Mul32) { + HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg dst = newVRegI(env); + addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL)); + addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR)); + addInstr(env, ARMInstr_Mul(ARMmul_PLAIN)); + addInstr(env, mk_iMOVds_RR(dst, hregARM_R0())); + return dst; + } + + /* Handle misc other ops. */ + + if (e->Iex.Binop.op == Iop_Max32U) { + HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg dst = newVRegI(env); + addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL, + ARMRI84_R(argR))); + addInstr(env, mk_iMOVds_RR(dst, argL)); + addInstr(env, ARMInstr_CMov(ARMcc_LO, dst, ARMRI84_R(argR))); + return dst; + } + + if (e->Iex.Binop.op == Iop_CmpF64) { + HReg dL = iselDblExpr(env, e->Iex.Binop.arg1); + HReg dR = iselDblExpr(env, e->Iex.Binop.arg2); + HReg dst = newVRegI(env); + /* Do the compare (FCMPD) and set NZCV in FPSCR. Then also do + FMSTAT, so we can examine the results directly. */ + addInstr(env, ARMInstr_VCmpD(dL, dR)); + /* Create in dst, the IRCmpF64Result encoded result. */ + addInstr(env, ARMInstr_Imm32(dst, 0)); + addInstr(env, ARMInstr_CMov(ARMcc_EQ, dst, ARMRI84_I84(0x40,0))); //EQ + addInstr(env, ARMInstr_CMov(ARMcc_MI, dst, ARMRI84_I84(0x01,0))); //LT + addInstr(env, ARMInstr_CMov(ARMcc_GT, dst, ARMRI84_I84(0x00,0))); //GT + addInstr(env, ARMInstr_CMov(ARMcc_VS, dst, ARMRI84_I84(0x45,0))); //UN + return dst; + } + + if (e->Iex.Binop.op == Iop_F64toI32S + || e->Iex.Binop.op == Iop_F64toI32U) { + /* Wretched uglyness all round, due to having to deal + with rounding modes. Oh well. */ + /* FIXME: if arg1 is a constant indicating round-to-zero, + then we could skip all this arsing around with FPSCR and + simply emit FTO{S,U}IZD. */ + Bool syned = e->Iex.Binop.op == Iop_F64toI32S; + HReg valD = iselDblExpr(env, e->Iex.Binop.arg2); + set_VFP_rounding_mode(env, e->Iex.Binop.arg1); + /* FTO{S,U}ID valF, valD */ + HReg valF = newVRegF(env); + addInstr(env, ARMInstr_VCvtID(False/*!iToD*/, syned, + valF, valD)); + set_VFP_rounding_default(env); + /* VMOV dst, valF */ + HReg dst = newVRegI(env); + addInstr(env, ARMInstr_VXferS(False/*!toS*/, valF, dst)); + return dst; + } + + if (e->Iex.Binop.op == Iop_GetElem8x8 + || e->Iex.Binop.op == Iop_GetElem16x4 + || e->Iex.Binop.op == Iop_GetElem32x2) { + HReg res = newVRegI(env); + HReg arg = iselNeon64Expr(env, e->Iex.Triop.arg1); + UInt index, size; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM target supports GetElem with constant " + "second argument only\n"); + } + index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Binop.op) { + case Iop_GetElem8x8: vassert(index < 8); size = 0; break; + case Iop_GetElem16x4: vassert(index < 4); size = 1; break; + case Iop_GetElem32x2: vassert(index < 2); size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS, + mkARMNRS(ARMNRS_Reg, res, 0), + mkARMNRS(ARMNRS_Scalar, arg, index), + size, False)); + return res; + } + + if (e->Iex.Binop.op == Iop_GetElem8x16 + || e->Iex.Binop.op == Iop_GetElem16x8 + || e->Iex.Binop.op == Iop_GetElem32x4) { + HReg res = newVRegI(env); + HReg arg = iselNeonExpr(env, e->Iex.Triop.arg1); + UInt index, size; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM target supports GetElem with constant " + "second argument only\n"); + } + index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Binop.op) { + case Iop_GetElem8x16: vassert(index < 16); size = 0; break; + case Iop_GetElem16x8: vassert(index < 8); size = 1; break; + case Iop_GetElem32x4: vassert(index < 4); size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS, + mkARMNRS(ARMNRS_Reg, res, 0), + mkARMNRS(ARMNRS_Scalar, arg, index), + size, True)); + return res; + } + + /* All cases involving host-side helper calls. */ + void* fn = NULL; + switch (e->Iex.Binop.op) { + case Iop_Add16x2: + fn = &h_generic_calc_Add16x2; break; + case Iop_Sub16x2: + fn = &h_generic_calc_Sub16x2; break; + case Iop_HAdd16Ux2: + fn = &h_generic_calc_HAdd16Ux2; break; + case Iop_HAdd16Sx2: + fn = &h_generic_calc_HAdd16Sx2; break; + case Iop_HSub16Ux2: + fn = &h_generic_calc_HSub16Ux2; break; + case Iop_HSub16Sx2: + fn = &h_generic_calc_HSub16Sx2; break; + case Iop_QAdd16Sx2: + fn = &h_generic_calc_QAdd16Sx2; break; + case Iop_QSub16Sx2: + fn = &h_generic_calc_QSub16Sx2; break; + case Iop_Add8x4: + fn = &h_generic_calc_Add8x4; break; + case Iop_Sub8x4: + fn = &h_generic_calc_Sub8x4; break; + case Iop_HAdd8Ux4: + fn = &h_generic_calc_HAdd8Ux4; break; + case Iop_HAdd8Sx4: + fn = &h_generic_calc_HAdd8Sx4; break; + case Iop_HSub8Ux4: + fn = &h_generic_calc_HSub8Ux4; break; + case Iop_HSub8Sx4: + fn = &h_generic_calc_HSub8Sx4; break; + case Iop_QAdd8Sx4: + fn = &h_generic_calc_QAdd8Sx4; break; + case Iop_QAdd8Ux4: + fn = &h_generic_calc_QAdd8Ux4; break; + case Iop_QSub8Sx4: + fn = &h_generic_calc_QSub8Sx4; break; + case Iop_QSub8Ux4: + fn = &h_generic_calc_QSub8Ux4; break; + case Iop_Sad8Ux4: + fn = &h_generic_calc_Sad8Ux4; break; + default: + break; + } + + if (fn) { + HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg res = newVRegI(env); + addInstr(env, mk_iMOVds_RR(hregARM_R0(), regL)); + addInstr(env, mk_iMOVds_RR(hregARM_R1(), regR)); + addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn), 2 )); + addInstr(env, mk_iMOVds_RR(res, hregARM_R0())); + return res; + } + + break; + } + + /* --------- UNARY OP --------- */ + case Iex_Unop: { + +//zz /* 1Uto8(32to1(expr32)) */ +//zz if (e->Iex.Unop.op == Iop_1Uto8) { +//zz DECLARE_PATTERN(p_32to1_then_1Uto8); +//zz DEFINE_PATTERN(p_32to1_then_1Uto8, +//zz unop(Iop_1Uto8,unop(Iop_32to1,bind(0)))); +//zz if (matchIRExpr(&mi,p_32to1_then_1Uto8,e)) { +//zz IRExpr* expr32 = mi.bindee[0]; +//zz HReg dst = newVRegI(env); +//zz HReg src = iselIntExpr_R(env, expr32); +//zz addInstr(env, mk_iMOVsd_RR(src,dst) ); +//zz addInstr(env, X86Instr_Alu32R(Xalu_AND, +//zz X86RMI_Imm(1), dst)); +//zz return dst; +//zz } +//zz } +//zz +//zz /* 8Uto32(LDle(expr32)) */ +//zz if (e->Iex.Unop.op == Iop_8Uto32) { +//zz DECLARE_PATTERN(p_LDle8_then_8Uto32); +//zz DEFINE_PATTERN(p_LDle8_then_8Uto32, +//zz unop(Iop_8Uto32, +//zz IRExpr_Load(Iend_LE,Ity_I8,bind(0))) ); +//zz if (matchIRExpr(&mi,p_LDle8_then_8Uto32,e)) { +//zz HReg dst = newVRegI(env); +//zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); +//zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst)); +//zz return dst; +//zz } +//zz } +//zz +//zz /* 8Sto32(LDle(expr32)) */ +//zz if (e->Iex.Unop.op == Iop_8Sto32) { +//zz DECLARE_PATTERN(p_LDle8_then_8Sto32); +//zz DEFINE_PATTERN(p_LDle8_then_8Sto32, +//zz unop(Iop_8Sto32, +//zz IRExpr_Load(Iend_LE,Ity_I8,bind(0))) ); +//zz if (matchIRExpr(&mi,p_LDle8_then_8Sto32,e)) { +//zz HReg dst = newVRegI(env); +//zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); +//zz addInstr(env, X86Instr_LoadEX(1,True,amode,dst)); +//zz return dst; +//zz } +//zz } +//zz +//zz /* 16Uto32(LDle(expr32)) */ +//zz if (e->Iex.Unop.op == Iop_16Uto32) { +//zz DECLARE_PATTERN(p_LDle16_then_16Uto32); +//zz DEFINE_PATTERN(p_LDle16_then_16Uto32, +//zz unop(Iop_16Uto32, +//zz IRExpr_Load(Iend_LE,Ity_I16,bind(0))) ); +//zz if (matchIRExpr(&mi,p_LDle16_then_16Uto32,e)) { +//zz HReg dst = newVRegI(env); +//zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); +//zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst)); +//zz return dst; +//zz } +//zz } +//zz +//zz /* 8Uto32(GET:I8) */ +//zz if (e->Iex.Unop.op == Iop_8Uto32) { +//zz if (e->Iex.Unop.arg->tag == Iex_Get) { +//zz HReg dst; +//zz X86AMode* amode; +//zz vassert(e->Iex.Unop.arg->Iex.Get.ty == Ity_I8); +//zz dst = newVRegI(env); +//zz amode = X86AMode_IR(e->Iex.Unop.arg->Iex.Get.offset, +//zz hregX86_EBP()); +//zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst)); +//zz return dst; +//zz } +//zz } +//zz +//zz /* 16to32(GET:I16) */ +//zz if (e->Iex.Unop.op == Iop_16Uto32) { +//zz if (e->Iex.Unop.arg->tag == Iex_Get) { +//zz HReg dst; +//zz X86AMode* amode; +//zz vassert(e->Iex.Unop.arg->Iex.Get.ty == Ity_I16); +//zz dst = newVRegI(env); +//zz amode = X86AMode_IR(e->Iex.Unop.arg->Iex.Get.offset, +//zz hregX86_EBP()); +//zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst)); +//zz return dst; +//zz } +//zz } + + switch (e->Iex.Unop.op) { + case Iop_8Uto32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_Alu(ARMalu_AND, + dst, src, ARMRI84_I84(0xFF,0))); + return dst; + } +//zz case Iop_8Uto16: +//zz case Iop_8Uto32: +//zz case Iop_16Uto32: { +//zz HReg dst = newVRegI(env); +//zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); +//zz UInt mask = e->Iex.Unop.op==Iop_16Uto32 ? 0xFFFF : 0xFF; +//zz addInstr(env, mk_iMOVsd_RR(src,dst) ); +//zz addInstr(env, X86Instr_Alu32R(Xalu_AND, +//zz X86RMI_Imm(mask), dst)); +//zz return dst; +//zz } +//zz case Iop_8Sto16: +//zz case Iop_8Sto32: + case Iop_16Uto32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + ARMRI5* amt = ARMRI5_I5(16); + addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, src, amt)); + addInstr(env, ARMInstr_Shift(ARMsh_SHR, dst, dst, amt)); + return dst; + } + case Iop_8Sto32: + case Iop_16Sto32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + ARMRI5* amt = ARMRI5_I5(e->Iex.Unop.op==Iop_16Sto32 ? 16 : 24); + addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, src, amt)); + addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt)); + return dst; + } +//zz case Iop_Not8: +//zz case Iop_Not16: + case Iop_Not32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_Unary(ARMun_NOT, dst, src)); + return dst; + } + case Iop_64HIto32: { + HReg rHi, rLo; + iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); + return rHi; /* and abandon rLo .. poor wee thing :-) */ + } + case Iop_64to32: { + HReg rHi, rLo; + iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); + return rLo; /* similar stupid comment to the above ... */ + } + case Iop_64to8: { + HReg rHi, rLo; + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + HReg tmp = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); + rHi = tHi; + rLo = tLo; + } else { + iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); + } + return rLo; + } +//zz case Iop_16HIto8: +//zz case Iop_32HIto16: { +//zz HReg dst = newVRegI(env); +//zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); +//zz Int shift = e->Iex.Unop.op == Iop_16HIto8 ? 8 : 16; +//zz addInstr(env, mk_iMOVsd_RR(src,dst) ); +//zz addInstr(env, X86Instr_Sh32(Xsh_SHR, shift, dst)); +//zz return dst; +//zz } + case Iop_1Uto32: + case Iop_1Uto8: { + HReg dst = newVRegI(env); + ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); + addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); + return dst; + } + + case Iop_1Sto32: { + HReg dst = newVRegI(env); + ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); + ARMRI5* amt = ARMRI5_I5(31); + /* This is really rough. We could do much better here; + perhaps mvn{cond} dst, #0 as the second insn? + (same applies to 1Sto64) */ + addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); + addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); + addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt)); + addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt)); + return dst; + } + + +//zz case Iop_1Sto8: +//zz case Iop_1Sto16: +//zz case Iop_1Sto32: { +//zz /* could do better than this, but for now ... */ +//zz HReg dst = newVRegI(env); +//zz X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg); +//zz addInstr(env, X86Instr_Set32(cond,dst)); +//zz addInstr(env, X86Instr_Sh32(Xsh_SHL, 31, dst)); +//zz addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, dst)); +//zz return dst; +//zz } +//zz case Iop_Ctz32: { +//zz /* Count trailing zeroes, implemented by x86 'bsfl' */ +//zz HReg dst = newVRegI(env); +//zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); +//zz addInstr(env, X86Instr_Bsfr32(True,src,dst)); +//zz return dst; +//zz } + case Iop_Clz32: { + /* Count leading zeroes; easy on ARM. */ + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_Unary(ARMun_CLZ, dst, src)); + return dst; + } + + case Iop_CmpwNEZ32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src)); + addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src))); + addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, ARMRI5_I5(31))); + return dst; + } + + case Iop_Left32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src)); + addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src))); + return dst; + } + +//zz case Iop_V128to32: { +//zz HReg dst = newVRegI(env); +//zz HReg vec = iselVecExpr(env, e->Iex.Unop.arg); +//zz X86AMode* esp0 = X86AMode_IR(0, hregX86_ESP()); +//zz sub_from_esp(env, 16); +//zz addInstr(env, X86Instr_SseLdSt(False/*store*/, vec, esp0)); +//zz addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(esp0), dst )); +//zz add_to_esp(env, 16); +//zz return dst; +//zz } +//zz + case Iop_ReinterpF32asI32: { + HReg dst = newVRegI(env); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_VXferS(False/*!toS*/, src, dst)); + return dst; + } + +//zz +//zz case Iop_16to8: + case Iop_32to8: + case Iop_32to16: + /* These are no-ops. */ + return iselIntExpr_R(env, e->Iex.Unop.arg); + + default: + break; + } + + /* All Unop cases involving host-side helper calls. */ + void* fn = NULL; + switch (e->Iex.Unop.op) { + case Iop_CmpNEZ16x2: + fn = &h_generic_calc_CmpNEZ16x2; break; + case Iop_CmpNEZ8x4: + fn = &h_generic_calc_CmpNEZ8x4; break; + default: + break; + } + + if (fn) { + HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg); + HReg res = newVRegI(env); + addInstr(env, mk_iMOVds_RR(hregARM_R0(), arg)); + addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn), 1 )); + addInstr(env, mk_iMOVds_RR(res, hregARM_R0())); + return res; + } + + break; + } + + /* --------- GET --------- */ + case Iex_Get: { + if (ty == Ity_I32 + && 0 == (e->Iex.Get.offset & 3) + && e->Iex.Get.offset < 4096-4) { + HReg dst = newVRegI(env); + addInstr(env, ARMInstr_LdSt32( + True/*isLoad*/, + dst, + ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset))); + return dst; + } +//zz if (ty == Ity_I8 || ty == Ity_I16) { +//zz HReg dst = newVRegI(env); +//zz addInstr(env, X86Instr_LoadEX( +//zz toUChar(ty==Ity_I8 ? 1 : 2), +//zz False, +//zz X86AMode_IR(e->Iex.Get.offset,hregX86_EBP()), +//zz dst)); +//zz return dst; +//zz } + break; + } + +//zz case Iex_GetI: { +//zz X86AMode* am +//zz = genGuestArrayOffset( +//zz env, e->Iex.GetI.descr, +//zz e->Iex.GetI.ix, e->Iex.GetI.bias ); +//zz HReg dst = newVRegI(env); +//zz if (ty == Ity_I8) { +//zz addInstr(env, X86Instr_LoadEX( 1, False, am, dst )); +//zz return dst; +//zz } +//zz if (ty == Ity_I32) { +//zz addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(am), dst)); +//zz return dst; +//zz } +//zz break; +//zz } + + /* --------- CCALL --------- */ + case Iex_CCall: { + HReg dst = newVRegI(env); + vassert(ty == e->Iex.CCall.retty); + + /* be very restrictive for now. Only 32/64-bit ints allowed + for args, and 32 bits for return type. */ + if (e->Iex.CCall.retty != Ity_I32) + goto irreducible; + + /* Marshal args, do the call, clear stack. */ + Bool ok = doHelperCall( env, False, + NULL, e->Iex.CCall.cee, e->Iex.CCall.args ); + if (ok) { + addInstr(env, mk_iMOVds_RR(dst, hregARM_R0())); + return dst; + } + /* else fall through; will hit the irreducible: label */ + } + + /* --------- LITERAL --------- */ + /* 32 literals */ + case Iex_Const: { + UInt u = 0; + HReg dst = newVRegI(env); + switch (e->Iex.Const.con->tag) { + case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; + case Ico_U16: u = 0xFFFF & (e->Iex.Const.con->Ico.U16); break; + case Ico_U8: u = 0xFF & (e->Iex.Const.con->Ico.U8); break; + default: ppIRExpr(e); vpanic("iselIntExpr_R.Iex_Const(arm)"); + } + addInstr(env, ARMInstr_Imm32(dst, u)); + return dst; + } + + /* --------- MULTIPLEX --------- */ + case Iex_Mux0X: { + IRExpr* cond = e->Iex.Mux0X.cond; + + /* Mux0X( 32to8(1Uto32(ccexpr)), expr0, exprX ) */ + if (ty == Ity_I32 + && cond->tag == Iex_Unop + && cond->Iex.Unop.op == Iop_32to8 + && cond->Iex.Unop.arg->tag == Iex_Unop + && cond->Iex.Unop.arg->Iex.Unop.op == Iop_1Uto32) { + ARMCondCode cc; + HReg rX = iselIntExpr_R(env, e->Iex.Mux0X.exprX); + ARMRI84* r0 = iselIntExpr_RI84(NULL, False, env, e->Iex.Mux0X.expr0); + HReg dst = newVRegI(env); + addInstr(env, mk_iMOVds_RR(dst, rX)); + cc = iselCondCode(env, cond->Iex.Unop.arg->Iex.Unop.arg); + addInstr(env, ARMInstr_CMov(cc ^ 1, dst, r0)); + return dst; + } + + /* Mux0X(cond, expr0, exprX) (general case) */ + if (ty == Ity_I32) { + HReg r8; + HReg rX = iselIntExpr_R(env, e->Iex.Mux0X.exprX); + ARMRI84* r0 = iselIntExpr_RI84(NULL, False, env, e->Iex.Mux0X.expr0); + HReg dst = newVRegI(env); + addInstr(env, mk_iMOVds_RR(dst, rX)); + r8 = iselIntExpr_R(env, cond); + addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8, + ARMRI84_I84(0xFF,0))); + addInstr(env, ARMInstr_CMov(ARMcc_EQ, dst, r0)); + return dst; + } + break; + } + + default: + break; + } /* switch (e->tag) */ + + /* We get here if no pattern matched. */ + irreducible: + ppIRExpr(e); + vpanic("iselIntExpr_R: cannot reduce tree"); +} + + +/* -------------------- 64-bit -------------------- */ + +/* Compute a 64-bit value into a register pair, which is returned as + the first two parameters. As with iselIntExpr_R, these may be + either real or virtual regs; in any case they must not be changed + by subsequent code emitted by the caller. */ + +static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) +{ + iselInt64Expr_wrk(rHi, rLo, env, e); +# if 0 + vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); +# endif + vassert(hregClass(*rHi) == HRcInt32); + vassert(hregIsVirtual(*rHi)); + vassert(hregClass(*rLo) == HRcInt32); + vassert(hregIsVirtual(*rLo)); +} + +/* DO NOT CALL THIS DIRECTLY ! */ +static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) +{ + vassert(e); + vassert(typeOfIRExpr(env->type_env,e) == Ity_I64); + + /* 64-bit literal */ + if (e->tag == Iex_Const) { + ULong w64 = e->Iex.Const.con->Ico.U64; + UInt wHi = toUInt(w64 >> 32); + UInt wLo = toUInt(w64); + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + vassert(e->Iex.Const.con->tag == Ico_U64); + addInstr(env, ARMInstr_Imm32(tHi, wHi)); + addInstr(env, ARMInstr_Imm32(tLo, wLo)); + *rHi = tHi; + *rLo = tLo; + return; + } + + /* read 64-bit IRTemp */ + if (e->tag == Iex_RdTmp) { + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + HReg tmp = iselNeon64Expr(env, e); + addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); + *rHi = tHi; + *rLo = tLo; + } else { + lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp); + } + return; + } + + /* 64-bit load */ + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { + HReg tLo, tHi, rA; + vassert(e->Iex.Load.ty == Ity_I64); + rA = iselIntExpr_R(env, e->Iex.Load.addr); + tHi = newVRegI(env); + tLo = newVRegI(env); + addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tHi, ARMAMode1_RI(rA, 4))); + addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tLo, ARMAMode1_RI(rA, 0))); + *rHi = tHi; + *rLo = tLo; + return; + } + + /* 64-bit GET */ + if (e->tag == Iex_Get) { + ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 0); + ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 4); + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tHi, am4)); + addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tLo, am0)); + *rHi = tHi; + *rLo = tLo; + return; + } + + /* --------- BINARY ops --------- */ + if (e->tag == Iex_Binop) { + switch (e->Iex.Binop.op) { + + /* 32 x 32 -> 64 multiply */ + case Iop_MullS32: + case Iop_MullU32: { + HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + ARMMulOp mop = e->Iex.Binop.op == Iop_MullS32 + ? ARMmul_SX : ARMmul_ZX; + addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL)); + addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR)); + addInstr(env, ARMInstr_Mul(mop)); + addInstr(env, mk_iMOVds_RR(tHi, hregARM_R1())); + addInstr(env, mk_iMOVds_RR(tLo, hregARM_R0())); + *rHi = tHi; + *rLo = tLo; + return; + } + + case Iop_Or64: { + HReg xLo, xHi, yLo, yHi; + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); + iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, xHi, ARMRI84_R(yHi))); + addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, xLo, ARMRI84_R(yLo))); + *rHi = tHi; + *rLo = tLo; + return; + } + + case Iop_Add64: { + HReg xLo, xHi, yLo, yHi; + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); + iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_Alu(ARMalu_ADDS, tLo, xLo, ARMRI84_R(yLo))); + addInstr(env, ARMInstr_Alu(ARMalu_ADC, tHi, xHi, ARMRI84_R(yHi))); + *rHi = tHi; + *rLo = tLo; + return; + } + + /* 32HLto64(e1,e2) */ + case Iop_32HLto64: { + *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); + *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); + return; + } + + default: + break; + } + } + + /* --------- UNARY ops --------- */ + if (e->tag == Iex_Unop) { + switch (e->Iex.Unop.op) { + + /* ReinterpF64asI64 */ + case Iop_ReinterpF64asI64: { + HReg dstHi = newVRegI(env); + HReg dstLo = newVRegI(env); + HReg src = iselDblExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_VXferD(False/*!toD*/, src, dstHi, dstLo)); + *rHi = dstHi; + *rLo = dstLo; + return; + } + + /* Left64(e) */ + case Iop_Left64: { + HReg yLo, yHi; + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + HReg zero = newVRegI(env); + /* yHi:yLo = arg */ + iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg); + /* zero = 0 */ + addInstr(env, ARMInstr_Imm32(zero, 0)); + /* tLo = 0 - yLo, and set carry */ + addInstr(env, ARMInstr_Alu(ARMalu_SUBS, + tLo, zero, ARMRI84_R(yLo))); + /* tHi = 0 - yHi - carry */ + addInstr(env, ARMInstr_Alu(ARMalu_SBC, + tHi, zero, ARMRI84_R(yHi))); + /* So now we have tHi:tLo = -arg. To finish off, or 'arg' + back in, so as to give the final result + tHi:tLo = arg | -arg. */ + addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, tHi, ARMRI84_R(yHi))); + addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, tLo, ARMRI84_R(yLo))); + *rHi = tHi; + *rLo = tLo; + return; + } + + /* CmpwNEZ64(e) */ + case Iop_CmpwNEZ64: { + HReg srcLo, srcHi; + HReg tmp1 = newVRegI(env); + HReg tmp2 = newVRegI(env); + /* srcHi:srcLo = arg */ + iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg); + /* tmp1 = srcHi | srcLo */ + addInstr(env, ARMInstr_Alu(ARMalu_OR, + tmp1, srcHi, ARMRI84_R(srcLo))); + /* tmp2 = (tmp1 | -tmp1) >>s 31 */ + addInstr(env, ARMInstr_Unary(ARMun_NEG, tmp2, tmp1)); + addInstr(env, ARMInstr_Alu(ARMalu_OR, + tmp2, tmp2, ARMRI84_R(tmp1))); + addInstr(env, ARMInstr_Shift(ARMsh_SAR, + tmp2, tmp2, ARMRI5_I5(31))); + *rHi = tmp2; + *rLo = tmp2; + return; + } + + case Iop_1Sto64: { + HReg dst = newVRegI(env); + ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); + ARMRI5* amt = ARMRI5_I5(31); + /* This is really rough. We could do much better here; + perhaps mvn{cond} dst, #0 as the second insn? + (same applies to 1Sto32) */ + addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); + addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); + addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt)); + addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt)); + *rHi = dst; + *rLo = dst; + return; + } + + default: + break; + } + } /* if (e->tag == Iex_Unop) */ + + /* --------- MULTIPLEX --------- */ + if (e->tag == Iex_Mux0X) { + IRType ty8; + HReg r8, rXhi, rXlo, r0hi, r0lo, dstHi, dstLo; + ty8 = typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond); + vassert(ty8 == Ity_I8); + iselInt64Expr(&rXhi, &rXlo, env, e->Iex.Mux0X.exprX); + iselInt64Expr(&r0hi, &r0lo, env, e->Iex.Mux0X.expr0); + dstHi = newVRegI(env); + dstLo = newVRegI(env); + addInstr(env, mk_iMOVds_RR(dstHi, rXhi)); + addInstr(env, mk_iMOVds_RR(dstLo, rXlo)); + r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond); + addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8, + ARMRI84_I84(0xFF,0))); + addInstr(env, ARMInstr_CMov(ARMcc_EQ, dstHi, ARMRI84_R(r0hi))); + addInstr(env, ARMInstr_CMov(ARMcc_EQ, dstLo, ARMRI84_R(r0lo))); + *rHi = dstHi; + *rLo = dstLo; + return; + } + + /* It is convenient sometimes to call iselInt64Expr even when we + have NEON support (e.g. in do_helper_call we need 64-bit + arguments as 2 x 32 regs). */ + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + HReg tHi = newVRegI(env); + HReg tLo = newVRegI(env); + HReg tmp = iselNeon64Expr(env, e); + addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); + *rHi = tHi; + *rLo = tLo; + return ; + } + + ppIRExpr(e); + vpanic("iselInt64Expr"); +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Vector (NEON) expressions (64 or 128 bit) ---*/ +/*---------------------------------------------------------*/ + +static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e ) +{ + HReg r = iselNeon64Expr_wrk( env, e ); + vassert(hregClass(r) == HRcFlt64); + vassert(hregIsVirtual(r)); + return r; +} + +/* DO NOT CALL THIS DIRECTLY */ +static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env, e); + MatchInfo mi; + vassert(e); + vassert(ty == Ity_I64); + + if (e->tag == Iex_RdTmp) { + return lookupIRTemp(env, e->Iex.RdTmp.tmp); + } + + if (e->tag == Iex_Const) { + HReg rLo, rHi; + HReg res = newVRegD(env); + iselInt64Expr(&rHi, &rLo, env, e); + addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); + return res; + } + + /* 64-bit load */ + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { + HReg res = newVRegD(env); + ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr); + vassert(ty == Ity_I64); + addInstr(env, ARMInstr_NLdStD(True, res, am)); + return res; + } + + /* 64-bit GET */ + if (e->tag == Iex_Get) { + HReg addr = newVRegI(env); + HReg res = newVRegD(env); + vassert(ty == Ity_I64); + addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset)); + addInstr(env, ARMInstr_NLdStD(True, res, mkARMAModeN_R(addr))); + return res; + } + + /* --------- BINARY ops --------- */ + if (e->tag == Iex_Binop) { + switch (e->Iex.Binop.op) { + + /* 32 x 32 -> 64 multiply */ + case Iop_MullS32: + case Iop_MullU32: { + HReg rLo, rHi; + HReg res = newVRegD(env); + iselInt64Expr(&rHi, &rLo, env, e); + addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); + return res; + } + + case Iop_And64: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VAND, + res, argL, argR, 4, False)); + return res; + } + case Iop_Or64: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VORR, + res, argL, argR, 4, False)); + return res; + } + case Iop_Xor64: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VXOR, + res, argL, argR, 4, False)); + return res; + } + + /* 32HLto64(e1,e2) */ + case Iop_32HLto64: { + HReg rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg res = newVRegD(env); + addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); + return res; + } + + case Iop_Add8x8: + case Iop_Add16x4: + case Iop_Add32x2: + case Iop_Add64: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Add8x8: size = 0; break; + case Iop_Add16x4: size = 1; break; + case Iop_Add32x2: size = 2; break; + case Iop_Add64: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VADD, + res, argL, argR, size, False)); + return res; + } + case Iop_Add32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP, + res, argL, argR, size, False)); + return res; + } + case Iop_Recps32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS, + res, argL, argR, size, False)); + return res; + } + case Iop_Rsqrts32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS, + res, argL, argR, size, False)); + return res; + } + case Iop_InterleaveOddLanes8x8: + case Iop_InterleaveOddLanes16x4: + case Iop_InterleaveLO32x2: + case Iop_InterleaveEvenLanes8x8: + case Iop_InterleaveEvenLanes16x4: + case Iop_InterleaveHI32x2: { + HReg tmp = newVRegD(env); + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + UInt is_lo; + switch (e->Iex.Binop.op) { + case Iop_InterleaveOddLanes8x8: is_lo = 1; size = 0; break; + case Iop_InterleaveEvenLanes8x8: is_lo = 0; size = 0; break; + case Iop_InterleaveOddLanes16x4: is_lo = 1; size = 1; break; + case Iop_InterleaveEvenLanes16x4: is_lo = 0; size = 1; break; + case Iop_InterleaveLO32x2: is_lo = 1; size = 2; break; + case Iop_InterleaveHI32x2: is_lo = 0; size = 2; break; + default: vassert(0); + } + if (is_lo) { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argL, 4, False)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argR, 4, False)); + addInstr(env, ARMInstr_NDual(ARMneon_TRN, + res, tmp, size, False)); + } else { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argR, 4, False)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argL, 4, False)); + addInstr(env, ARMInstr_NDual(ARMneon_TRN, + tmp, res, size, False)); + } + return res; + } + case Iop_InterleaveHI8x8: + case Iop_InterleaveHI16x4: + case Iop_InterleaveLO8x8: + case Iop_InterleaveLO16x4: { + HReg tmp = newVRegD(env); + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + UInt is_lo; + switch (e->Iex.Binop.op) { + case Iop_InterleaveHI8x8: is_lo = 1; size = 0; break; + case Iop_InterleaveLO8x8: is_lo = 0; size = 0; break; + case Iop_InterleaveHI16x4: is_lo = 1; size = 1; break; + case Iop_InterleaveLO16x4: is_lo = 0; size = 1; break; + default: vassert(0); + } + if (is_lo) { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argL, 4, False)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argR, 4, False)); + addInstr(env, ARMInstr_NDual(ARMneon_ZIP, + res, tmp, size, False)); + } else { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argR, 4, False)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argL, 4, False)); + addInstr(env, ARMInstr_NDual(ARMneon_ZIP, + tmp, res, size, False)); + } + return res; + } + case Iop_CatOddLanes8x8: + case Iop_CatOddLanes16x4: + case Iop_CatEvenLanes8x8: + case Iop_CatEvenLanes16x4: { + HReg tmp = newVRegD(env); + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + UInt is_lo; + switch (e->Iex.Binop.op) { + case Iop_CatOddLanes8x8: is_lo = 1; size = 0; break; + case Iop_CatEvenLanes8x8: is_lo = 0; size = 0; break; + case Iop_CatOddLanes16x4: is_lo = 1; size = 1; break; + case Iop_CatEvenLanes16x4: is_lo = 0; size = 1; break; + default: vassert(0); + } + if (is_lo) { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argL, 4, False)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argR, 4, False)); + addInstr(env, ARMInstr_NDual(ARMneon_UZP, + res, tmp, size, False)); + } else { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argR, 4, False)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argL, 4, False)); + addInstr(env, ARMInstr_NDual(ARMneon_UZP, + tmp, res, size, False)); + } + return res; + } + case Iop_QAdd8Ux8: + case Iop_QAdd16Ux4: + case Iop_QAdd32Ux2: + case Iop_QAdd64Ux1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QAdd8Ux8: size = 0; break; + case Iop_QAdd16Ux4: size = 1; break; + case Iop_QAdd32Ux2: size = 2; break; + case Iop_QAdd64Ux1: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU, + res, argL, argR, size, False)); + return res; + } + case Iop_QAdd8Sx8: + case Iop_QAdd16Sx4: + case Iop_QAdd32Sx2: + case Iop_QAdd64Sx1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QAdd8Sx8: size = 0; break; + case Iop_QAdd16Sx4: size = 1; break; + case Iop_QAdd32Sx2: size = 2; break; + case Iop_QAdd64Sx1: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS, + res, argL, argR, size, False)); + return res; + } + case Iop_Sub8x8: + case Iop_Sub16x4: + case Iop_Sub32x2: + case Iop_Sub64: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Sub8x8: size = 0; break; + case Iop_Sub16x4: size = 1; break; + case Iop_Sub32x2: size = 2; break; + case Iop_Sub64: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, + res, argL, argR, size, False)); + return res; + } + case Iop_Sub32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP, + res, argL, argR, size, False)); + return res; + } + case Iop_QSub8Ux8: + case Iop_QSub16Ux4: + case Iop_QSub32Ux2: + case Iop_QSub64Ux1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QSub8Ux8: size = 0; break; + case Iop_QSub16Ux4: size = 1; break; + case Iop_QSub32Ux2: size = 2; break; + case Iop_QSub64Ux1: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU, + res, argL, argR, size, False)); + return res; + } + case Iop_QSub8Sx8: + case Iop_QSub16Sx4: + case Iop_QSub32Sx2: + case Iop_QSub64Sx1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QSub8Sx8: size = 0; break; + case Iop_QSub16Sx4: size = 1; break; + case Iop_QSub32Sx2: size = 2; break; + case Iop_QSub64Sx1: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS, + res, argL, argR, size, False)); + return res; + } + case Iop_Max8Ux8: + case Iop_Max16Ux4: + case Iop_Max32Ux2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Max8Ux8: size = 0; break; + case Iop_Max16Ux4: size = 1; break; + case Iop_Max32Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU, + res, argL, argR, size, False)); + return res; + } + case Iop_Max8Sx8: + case Iop_Max16Sx4: + case Iop_Max32Sx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Max8Sx8: size = 0; break; + case Iop_Max16Sx4: size = 1; break; + case Iop_Max32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS, + res, argL, argR, size, False)); + return res; + } + case Iop_Min8Ux8: + case Iop_Min16Ux4: + case Iop_Min32Ux2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Min8Ux8: size = 0; break; + case Iop_Min16Ux4: size = 1; break; + case Iop_Min32Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMINU, + res, argL, argR, size, False)); + return res; + } + case Iop_Min8Sx8: + case Iop_Min16Sx4: + case Iop_Min32Sx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Min8Sx8: size = 0; break; + case Iop_Min16Sx4: size = 1; break; + case Iop_Min32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMINS, + res, argL, argR, size, False)); + return res; + } + case Iop_Sar8x8: + case Iop_Sar16x4: + case Iop_Sar32x2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + HReg argR2 = newVRegD(env); + HReg zero = newVRegD(env); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Sar8x8: size = 0; break; + case Iop_Sar16x4: size = 1; break; + case Iop_Sar32x2: size = 2; break; + case Iop_Sar64: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); + addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, + argR2, zero, argR, size, False)); + addInstr(env, ARMInstr_NShift(ARMneon_VSAL, + res, argL, argR2, size, False)); + return res; + } + case Iop_Sal8x8: + case Iop_Sal16x4: + case Iop_Sal32x2: + case Iop_Sal64x1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Sal8x8: size = 0; break; + case Iop_Sal16x4: size = 1; break; + case Iop_Sal32x2: size = 2; break; + case Iop_Sal64x1: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NShift(ARMneon_VSAL, + res, argL, argR, size, False)); + return res; + } + case Iop_Shr8x8: + case Iop_Shr16x4: + case Iop_Shr32x2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + HReg argR2 = newVRegD(env); + HReg zero = newVRegD(env); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Shr8x8: size = 0; break; + case Iop_Shr16x4: size = 1; break; + case Iop_Shr32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); + addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, + argR2, zero, argR, size, False)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + res, argL, argR2, size, False)); + return res; + } + case Iop_Shl8x8: + case Iop_Shl16x4: + case Iop_Shl32x2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Shl8x8: size = 0; break; + case Iop_Shl16x4: size = 1; break; + case Iop_Shl32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + res, argL, argR, size, False)); + return res; + } + case Iop_QShl8x8: + case Iop_QShl16x4: + case Iop_QShl32x2: + case Iop_QShl64x1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QShl8x8: size = 0; break; + case Iop_QShl16x4: size = 1; break; + case Iop_QShl32x2: size = 2; break; + case Iop_QShl64x1: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NShift(ARMneon_VQSHL, + res, argL, argR, size, False)); + return res; + } + case Iop_QSal8x8: + case Iop_QSal16x4: + case Iop_QSal32x2: + case Iop_QSal64x1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QSal8x8: size = 0; break; + case Iop_QSal16x4: size = 1; break; + case Iop_QSal32x2: size = 2; break; + case Iop_QSal64x1: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NShift(ARMneon_VQSAL, + res, argL, argR, size, False)); + return res; + } + case Iop_QShlN8x8: + case Iop_QShlN16x4: + case Iop_QShlN32x2: + case Iop_QShlN64x1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + UInt size, imm; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM taget supports Iop_QShlNAxB with constant " + "second argument only\n"); + } + imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Binop.op) { + case Iop_QShlN8x8: size = 8 | imm; break; + case Iop_QShlN16x4: size = 16 | imm; break; + case Iop_QShlN32x2: size = 32 | imm; break; + case Iop_QShlN64x1: size = 64 | imm; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU, + res, argL, size, False)); + return res; + } + case Iop_QShlN8Sx8: + case Iop_QShlN16Sx4: + case Iop_QShlN32Sx2: + case Iop_QShlN64Sx1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + UInt size, imm; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM taget supports Iop_QShlNAxB with constant " + "second argument only\n"); + } + imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Binop.op) { + case Iop_QShlN8Sx8: size = 8 | imm; break; + case Iop_QShlN16Sx4: size = 16 | imm; break; + case Iop_QShlN32Sx2: size = 32 | imm; break; + case Iop_QShlN64Sx1: size = 64 | imm; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS, + res, argL, size, False)); + return res; + } + case Iop_QSalN8x8: + case Iop_QSalN16x4: + case Iop_QSalN32x2: + case Iop_QSalN64x1: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + UInt size, imm; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM taget supports Iop_QShlNAxB with constant " + "second argument only\n"); + } + imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Binop.op) { + case Iop_QSalN8x8: size = 8 | imm; break; + case Iop_QSalN16x4: size = 16 | imm; break; + case Iop_QSalN32x2: size = 32 | imm; break; + case Iop_QSalN64x1: size = 64 | imm; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, + res, argL, size, False)); + return res; + } + case Iop_ShrN8x8: + case Iop_ShrN16x4: + case Iop_ShrN32x2: + case Iop_Shr64: { + HReg res = newVRegD(env); + HReg tmp = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg argR2 = newVRegI(env); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_ShrN8x8: size = 0; break; + case Iop_ShrN16x4: size = 1; break; + case Iop_ShrN32x2: size = 2; break; + case Iop_Shr64: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); + addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + res, argL, tmp, size, False)); + return res; + } + case Iop_ShlN8x8: + case Iop_ShlN16x4: + case Iop_ShlN32x2: + case Iop_Shl64: { + HReg res = newVRegD(env); + HReg tmp = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_ShlN8x8: size = 0; break; + case Iop_ShlN16x4: size = 1; break; + case Iop_ShlN32x2: size = 2; break; + case Iop_Shl64: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR, 0, False)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + res, argL, tmp, size, False)); + return res; + } + case Iop_SarN8x8: + case Iop_SarN16x4: + case Iop_SarN32x2: + case Iop_Sar64: { + HReg res = newVRegD(env); + HReg tmp = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg argR2 = newVRegI(env); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_SarN8x8: size = 0; break; + case Iop_SarN16x4: size = 1; break; + case Iop_SarN32x2: size = 2; break; + case Iop_Sar64: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); + addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False)); + addInstr(env, ARMInstr_NShift(ARMneon_VSAL, + res, argL, tmp, size, False)); + return res; + } + case Iop_CmpGT8Ux8: + case Iop_CmpGT16Ux4: + case Iop_CmpGT32Ux2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_CmpGT8Ux8: size = 0; break; + case Iop_CmpGT16Ux4: size = 1; break; + case Iop_CmpGT32Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU, + res, argL, argR, size, False)); + return res; + } + case Iop_CmpGT8Sx8: + case Iop_CmpGT16Sx4: + case Iop_CmpGT32Sx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_CmpGT8Sx8: size = 0; break; + case Iop_CmpGT16Sx4: size = 1; break; + case Iop_CmpGT32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS, + res, argL, argR, size, False)); + return res; + } + case Iop_CmpEQ8x8: + case Iop_CmpEQ16x4: + case Iop_CmpEQ32x2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_CmpEQ8x8: size = 0; break; + case Iop_CmpEQ16x4: size = 1; break; + case Iop_CmpEQ32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ, + res, argL, argR, size, False)); + return res; + } + case Iop_Mul8x8: + case Iop_Mul16x4: + case Iop_Mul32x2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Mul8x8: size = 0; break; + case Iop_Mul16x4: size = 1; break; + case Iop_Mul32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMUL, + res, argL, argR, size, False)); + return res; + } + case Iop_Mul32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP, + res, argL, argR, size, False)); + return res; + } + case Iop_QDMulHi16Sx4: + case Iop_QDMulHi32Sx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_QDMulHi16Sx4: size = 1; break; + case Iop_QDMulHi32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH, + res, argL, argR, size, False)); + return res; + } + + case Iop_QRDMulHi16Sx4: + case Iop_QRDMulHi32Sx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_QRDMulHi16Sx4: size = 1; break; + case Iop_QRDMulHi32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH, + res, argL, argR, size, False)); + return res; + } + + case Iop_PwAdd8x8: + case Iop_PwAdd16x4: + case Iop_PwAdd32x2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwAdd8x8: size = 0; break; + case Iop_PwAdd16x4: size = 1; break; + case Iop_PwAdd32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VPADD, + res, argL, argR, size, False)); + return res; + } + case Iop_PwAdd32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VPADDFP, + res, argL, argR, size, False)); + return res; + } + case Iop_PwMin8Ux8: + case Iop_PwMin16Ux4: + case Iop_PwMin32Ux2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwMin8Ux8: size = 0; break; + case Iop_PwMin16Ux4: size = 1; break; + case Iop_PwMin32Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VPMINU, + res, argL, argR, size, False)); + return res; + } + case Iop_PwMin8Sx8: + case Iop_PwMin16Sx4: + case Iop_PwMin32Sx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwMin8Sx8: size = 0; break; + case Iop_PwMin16Sx4: size = 1; break; + case Iop_PwMin32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VPMINS, + res, argL, argR, size, False)); + return res; + } + case Iop_PwMax8Ux8: + case Iop_PwMax16Ux4: + case Iop_PwMax32Ux2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwMax8Ux8: size = 0; break; + case Iop_PwMax16Ux4: size = 1; break; + case Iop_PwMax32Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXU, + res, argL, argR, size, False)); + return res; + } + case Iop_PwMax8Sx8: + case Iop_PwMax16Sx4: + case Iop_PwMax32Sx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwMax8Sx8: size = 0; break; + case Iop_PwMax16Sx4: size = 1; break; + case Iop_PwMax32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXS, + res, argL, argR, size, False)); + return res; + } + case Iop_Perm8x8: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VTBL, + res, argL, argR, 0, False)); + return res; + } + case Iop_PolynomialMul8x8: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VMULP, + res, argL, argR, size, False)); + return res; + } + case Iop_Max32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF, + res, argL, argR, 2, False)); + return res; + } + case Iop_Min32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VMINF, + res, argL, argR, 2, False)); + return res; + } + case Iop_PwMax32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF, + res, argL, argR, 2, False)); + return res; + } + case Iop_PwMin32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF, + res, argL, argR, 2, False)); + return res; + } + case Iop_CmpGT32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF, + res, argL, argR, 2, False)); + return res; + } + case Iop_CmpGE32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF, + res, argL, argR, 2, False)); + return res; + } + case Iop_CmpEQ32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF, + res, argL, argR, 2, False)); + return res; + } + case Iop_F32ToFixed32Ux2_RZ: + case Iop_F32ToFixed32Sx2_RZ: + case Iop_Fixed32UToF32x2_RN: + case Iop_Fixed32SToF32x2_RN: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1); + ARMNeonUnOp op; + UInt imm6; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM supports FP <-> Fixed conversion with constant " + "second argument less than 33 only\n"); + } + imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + vassert(imm6 <= 32 && imm6 > 0); + imm6 = 64 - imm6; + switch(e->Iex.Binop.op) { + case Iop_F32ToFixed32Ux2_RZ: op = ARMneon_VCVTFtoFixedU; break; + case Iop_F32ToFixed32Sx2_RZ: op = ARMneon_VCVTFtoFixedS; break; + case Iop_Fixed32UToF32x2_RN: op = ARMneon_VCVTFixedUtoF; break; + case Iop_Fixed32SToF32x2_RN: op = ARMneon_VCVTFixedStoF; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False)); + return res; + } + /* + FIXME: is this here or not? + case Iop_VDup8x8: + case Iop_VDup16x4: + case Iop_VDup32x2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + UInt index; + UInt imm4; + UInt size = 0; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM supports Iop_VDup with constant " + "second argument less than 16 only\n"); + } + index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch(e->Iex.Binop.op) { + case Iop_VDup8x8: imm4 = (index << 1) + 1; break; + case Iop_VDup16x4: imm4 = (index << 2) + 2; break; + case Iop_VDup32x2: imm4 = (index << 3) + 4; break; + default: vassert(0); + } + if (imm4 >= 16) { + vpanic("ARM supports Iop_VDup with constant " + "second argument less than 16 only\n"); + } + addInstr(env, ARMInstr_NUnary(ARMneon_VDUP, + res, argL, imm4, False)); + return res; + } + */ + default: + break; + } + } + + /* --------- UNARY ops --------- */ + if (e->tag == Iex_Unop) { + switch (e->Iex.Unop.op) { + + /* ReinterpF64asI64 */ + case Iop_ReinterpF64asI64: + /* Left64(e) */ + case Iop_Left64: + /* CmpwNEZ64(e) */ + //case Iop_CmpwNEZ64: + case Iop_1Sto64: { + HReg rLo, rHi; + HReg res = newVRegD(env); + iselInt64Expr(&rHi, &rLo, env, e); + addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); + return res; + } + case Iop_Not64: { + DECLARE_PATTERN(p_veqz_8x8); + DECLARE_PATTERN(p_veqz_16x4); + DECLARE_PATTERN(p_veqz_32x2); + DECLARE_PATTERN(p_vcge_8sx8); + DECLARE_PATTERN(p_vcge_16sx4); + DECLARE_PATTERN(p_vcge_32sx2); + DECLARE_PATTERN(p_vcge_8ux8); + DECLARE_PATTERN(p_vcge_16ux4); + DECLARE_PATTERN(p_vcge_32ux2); + DEFINE_PATTERN(p_veqz_8x8, + unop(Iop_Not64, unop(Iop_CmpNEZ8x8, bind(0)))); + DEFINE_PATTERN(p_veqz_16x4, + unop(Iop_Not64, unop(Iop_CmpNEZ16x4, bind(0)))); + DEFINE_PATTERN(p_veqz_32x2, + unop(Iop_Not64, unop(Iop_CmpNEZ32x2, bind(0)))); + DEFINE_PATTERN(p_vcge_8sx8, + unop(Iop_Not64, binop(Iop_CmpGT8Sx8, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_16sx4, + unop(Iop_Not64, binop(Iop_CmpGT16Sx4, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_32sx2, + unop(Iop_Not64, binop(Iop_CmpGT32Sx2, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_8ux8, + unop(Iop_Not64, binop(Iop_CmpGT8Ux8, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_16ux4, + unop(Iop_Not64, binop(Iop_CmpGT16Ux4, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_32ux2, + unop(Iop_Not64, binop(Iop_CmpGT32Ux2, bind(1), bind(0)))); + if (matchIRExpr(&mi, p_veqz_8x8, e)) { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, False)); + return res; + } else if (matchIRExpr(&mi, p_veqz_16x4, e)) { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, False)); + return res; + } else if (matchIRExpr(&mi, p_veqz_32x2, e)) { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, False)); + return res; + } else if (matchIRExpr(&mi, p_vcge_8sx8, e)) { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, mi.bindee[0]); + HReg argR = iselNeon64Expr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, + res, argL, argR, 0, False)); + return res; + } else if (matchIRExpr(&mi, p_vcge_16sx4, e)) { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, mi.bindee[0]); + HReg argR = iselNeon64Expr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, + res, argL, argR, 1, False)); + return res; + } else if (matchIRExpr(&mi, p_vcge_32sx2, e)) { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, mi.bindee[0]); + HReg argR = iselNeon64Expr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, + res, argL, argR, 2, False)); + return res; + } else if (matchIRExpr(&mi, p_vcge_8ux8, e)) { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, mi.bindee[0]); + HReg argR = iselNeon64Expr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, + res, argL, argR, 0, False)); + return res; + } else if (matchIRExpr(&mi, p_vcge_16ux4, e)) { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, mi.bindee[0]); + HReg argR = iselNeon64Expr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, + res, argL, argR, 1, False)); + return res; + } else if (matchIRExpr(&mi, p_vcge_32ux2, e)) { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, mi.bindee[0]); + HReg argR = iselNeon64Expr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, + res, argL, argR, 2, False)); + return res; + } else { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, False)); + return res; + } + } + case Iop_Dup8x8: + case Iop_Dup16x4: + case Iop_Dup32x2: { + HReg res, arg; + UInt size; + DECLARE_PATTERN(p_vdup_8x8); + DECLARE_PATTERN(p_vdup_16x4); + DECLARE_PATTERN(p_vdup_32x2); + DEFINE_PATTERN(p_vdup_8x8, + unop(Iop_Dup8x8, binop(Iop_GetElem8x8, bind(0), bind(1)))); + DEFINE_PATTERN(p_vdup_16x4, + unop(Iop_Dup16x4, binop(Iop_GetElem16x4, bind(0), bind(1)))); + DEFINE_PATTERN(p_vdup_32x2, + unop(Iop_Dup32x2, binop(Iop_GetElem32x2, bind(0), bind(1)))); + if (matchIRExpr(&mi, p_vdup_8x8, e)) { + UInt index; + UInt imm4; + if (mi.bindee[1]->tag == Iex_Const && + typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { + index = mi.bindee[1]->Iex.Const.con->Ico.U8; + imm4 = (index << 1) + 1; + if (index < 8) { + res = newVRegD(env); + arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnaryS( + ARMneon_VDUP, + mkARMNRS(ARMNRS_Reg, res, 0), + mkARMNRS(ARMNRS_Scalar, arg, index), + imm4, False + )); + return res; + } + } + } else if (matchIRExpr(&mi, p_vdup_16x4, e)) { + UInt index; + UInt imm4; + if (mi.bindee[1]->tag == Iex_Const && + typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { + index = mi.bindee[1]->Iex.Const.con->Ico.U8; + imm4 = (index << 2) + 2; + if (index < 4) { + res = newVRegD(env); + arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnaryS( + ARMneon_VDUP, + mkARMNRS(ARMNRS_Reg, res, 0), + mkARMNRS(ARMNRS_Scalar, arg, index), + imm4, False + )); + return res; + } + } + } else if (matchIRExpr(&mi, p_vdup_32x2, e)) { + UInt index; + UInt imm4; + if (mi.bindee[1]->tag == Iex_Const && + typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { + index = mi.bindee[1]->Iex.Const.con->Ico.U8; + imm4 = (index << 3) + 4; + if (index < 2) { + res = newVRegD(env); + arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnaryS( + ARMneon_VDUP, + mkARMNRS(ARMNRS_Reg, res, 0), + mkARMNRS(ARMNRS_Scalar, arg, index), + imm4, False + )); + return res; + } + } + } + arg = iselIntExpr_R(env, e->Iex.Unop.arg); + res = newVRegD(env); + switch (e->Iex.Unop.op) { + case Iop_Dup8x8: size = 0; break; + case Iop_Dup16x4: size = 1; break; + case Iop_Dup32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, False)); + return res; + } + case Iop_Abs8x8: + case Iop_Abs16x4: + case Iop_Abs32x2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Abs8x8: size = 0; break; + case Iop_Abs16x4: size = 1; break; + case Iop_Abs32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, False)); + return res; + } + case Iop_Reverse64_8x8: + case Iop_Reverse64_16x4: + case Iop_Reverse64_32x2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Reverse64_8x8: size = 0; break; + case Iop_Reverse64_16x4: size = 1; break; + case Iop_Reverse64_32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_REV64, + res, arg, size, False)); + return res; + } + case Iop_Reverse32_8x8: + case Iop_Reverse32_16x4: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Reverse32_8x8: size = 0; break; + case Iop_Reverse32_16x4: size = 1; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_REV32, + res, arg, size, False)); + return res; + } + case Iop_Reverse16_8x8: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + addInstr(env, ARMInstr_NUnary(ARMneon_REV16, + res, arg, size, False)); + return res; + } + case Iop_CmpwNEZ64: { + HReg x_lsh = newVRegD(env); + HReg x_rsh = newVRegD(env); + HReg lsh_amt = newVRegD(env); + HReg rsh_amt = newVRegD(env); + HReg zero = newVRegD(env); + HReg tmp = newVRegD(env); + HReg tmp2 = newVRegD(env); + HReg res = newVRegD(env); + HReg x = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, False)); + addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, False)); + addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32))); + addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0))); + addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, + rsh_amt, zero, lsh_amt, 2, False)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + x_lsh, x, lsh_amt, 3, False)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + x_rsh, x, rsh_amt, 3, False)); + addInstr(env, ARMInstr_NBinary(ARMneon_VORR, + tmp, x_lsh, x_rsh, 0, False)); + addInstr(env, ARMInstr_NBinary(ARMneon_VORR, + res, tmp, x, 0, False)); + return res; + } + case Iop_CmpNEZ8x8: + case Iop_CmpNEZ16x4: + case Iop_CmpNEZ32x2: { + HReg res = newVRegD(env); + HReg tmp = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size; + switch (e->Iex.Unop.op) { + case Iop_CmpNEZ8x8: size = 0; break; + case Iop_CmpNEZ16x4: size = 1; break; + case Iop_CmpNEZ32x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, False)); + addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, False)); + return res; + } + case Iop_Shorten16x8: + case Iop_Shorten32x4: + case Iop_Shorten64x2: { + HReg res = newVRegD(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Shorten16x8: size = 0; break; + case Iop_Shorten32x4: size = 1; break; + case Iop_Shorten64x2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_COPYN, + res, arg, size, False)); + return res; + } + case Iop_QShortenS16Sx8: + case Iop_QShortenS32Sx4: + case Iop_QShortenS64Sx2: { + HReg res = newVRegD(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_QShortenS16Sx8: size = 0; break; + case Iop_QShortenS32Sx4: size = 1; break; + case Iop_QShortenS64Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNSS, + res, arg, size, False)); + return res; + } + case Iop_QShortenU16Sx8: + case Iop_QShortenU32Sx4: + case Iop_QShortenU64Sx2: { + HReg res = newVRegD(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_QShortenU16Sx8: size = 0; break; + case Iop_QShortenU32Sx4: size = 1; break; + case Iop_QShortenU64Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUS, + res, arg, size, False)); + return res; + } + case Iop_QShortenU16Ux8: + case Iop_QShortenU32Ux4: + case Iop_QShortenU64Ux2: { + HReg res = newVRegD(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_QShortenU16Ux8: size = 0; break; + case Iop_QShortenU32Ux4: size = 1; break; + case Iop_QShortenU64Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUU, + res, arg, size, False)); + return res; + } + case Iop_PwAddL8Sx8: + case Iop_PwAddL16Sx4: + case Iop_PwAddL32Sx2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwAddL8Sx8: size = 0; break; + case Iop_PwAddL16Sx4: size = 1; break; + case Iop_PwAddL32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS, + res, arg, size, False)); + return res; + } + case Iop_PwAddL8Ux8: + case Iop_PwAddL16Ux4: + case Iop_PwAddL32Ux2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwAddL8Ux8: size = 0; break; + case Iop_PwAddL16Ux4: size = 1; break; + case Iop_PwAddL32Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU, + res, arg, size, False)); + return res; + } + case Iop_Cnt8x8: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + addInstr(env, ARMInstr_NUnary(ARMneon_CNT, + res, arg, size, False)); + return res; + } + case Iop_Clz8Sx8: + case Iop_Clz16Sx4: + case Iop_Clz32Sx2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Clz8Sx8: size = 0; break; + case Iop_Clz16Sx4: size = 1; break; + case Iop_Clz32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, + res, arg, size, False)); + return res; + } + case Iop_Cls8Sx8: + case Iop_Cls16Sx4: + case Iop_Cls32Sx2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Cls8Sx8: size = 0; break; + case Iop_Cls16Sx4: size = 1; break; + case Iop_Cls32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_CLS, + res, arg, size, False)); + return res; + } + case Iop_FtoI32Sx2_RZ: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS, + res, arg, 2, False)); + return res; + } + case Iop_FtoI32Ux2_RZ: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU, + res, arg, 2, False)); + return res; + } + case Iop_I32StoFx2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF, + res, arg, 2, False)); + return res; + } + case Iop_I32UtoFx2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF, + res, arg, 2, False)); + return res; + } + case Iop_F32toF16x4: { + HReg res = newVRegD(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF32toF16, + res, arg, 2, False)); + return res; + } + case Iop_Recip32Fx2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF, + res, argL, 0, False)); + return res; + } + case Iop_Recip32x2: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP, + res, argL, 0, False)); + return res; + } + case Iop_Abs32Fx2: { + DECLARE_PATTERN(p_vabd_32fx2); + DEFINE_PATTERN(p_vabd_32fx2, + unop(Iop_Abs32Fx2, + binop(Iop_Sub32Fx2, + bind(0), + bind(1)))); + if (matchIRExpr(&mi, p_vabd_32fx2, e)) { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, mi.bindee[0]); + HReg argR = iselNeon64Expr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP, + res, argL, argR, 0, False)); + return res; + } else { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP, + res, arg, 0, False)); + return res; + } + } + case Iop_Rsqrte32Fx2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP, + res, arg, 0, False)); + return res; + } + case Iop_Rsqrte32x2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE, + res, arg, 0, False)); + return res; + } + case Iop_Neg32Fx2: { + HReg res = newVRegD(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF, + res, arg, 0, False)); + return res; + } + default: + break; + } + } /* if (e->tag == Iex_Unop) */ + + if (e->tag == Iex_Triop) { + switch (e->Iex.Triop.op) { + case Iop_Extract64: { + HReg res = newVRegD(env); + HReg argL = iselNeon64Expr(env, e->Iex.Triop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Triop.arg2); + UInt imm4; + if (e->Iex.Triop.arg3->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Triop.arg3) != Ity_I8) { + vpanic("ARM target supports Iop_Extract64 with constant " + "third argument less than 16 only\n"); + } + imm4 = e->Iex.Triop.arg3->Iex.Const.con->Ico.U8; + if (imm4 >= 8) { + vpanic("ARM target supports Iop_Extract64 with constant " + "third argument less than 16 only\n"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VEXT, + res, argL, argR, imm4, False)); + return res; + } + case Iop_SetElem8x8: + case Iop_SetElem16x4: + case Iop_SetElem32x2: { + HReg res = newVRegD(env); + HReg dreg = iselNeon64Expr(env, e->Iex.Triop.arg1); + HReg arg = iselIntExpr_R(env, e->Iex.Triop.arg3); + UInt index, size; + if (e->Iex.Triop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Triop.arg2) != Ity_I8) { + vpanic("ARM target supports SetElem with constant " + "second argument only\n"); + } + index = e->Iex.Triop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Triop.op) { + case Iop_SetElem8x8: vassert(index < 8); size = 0; break; + case Iop_SetElem16x4: vassert(index < 4); size = 1; break; + case Iop_SetElem32x2: vassert(index < 2); size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, res, dreg, 4, False)); + addInstr(env, ARMInstr_NUnaryS(ARMneon_SETELEM, + mkARMNRS(ARMNRS_Scalar, res, index), + mkARMNRS(ARMNRS_Reg, arg, 0), + size, False)); + return res; + } + default: + break; + } + } + + /* --------- MULTIPLEX --------- */ + if (e->tag == Iex_Mux0X) { + HReg rLo, rHi; + HReg res = newVRegD(env); + iselInt64Expr(&rHi, &rLo, env, e); + addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); + return res; + } + + ppIRExpr(e); + vpanic("iselNeon64Expr"); +} + +static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e ) +{ + HReg r = iselNeonExpr_wrk( env, e ); + vassert(hregClass(r) == HRcVec128); + vassert(hregIsVirtual(r)); + return r; +} + +/* DO NOT CALL THIS DIRECTLY */ +static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env, e); + MatchInfo mi; + vassert(e); + vassert(ty == Ity_V128); + + if (e->tag == Iex_RdTmp) { + return lookupIRTemp(env, e->Iex.RdTmp.tmp); + } + + if (e->tag == Iex_Const) { + /* At the moment there should be no 128-bit constants in IR for ARM + generated during disassemble. They are represented as Iop_64HLtoV128 + binary operation and are handled among binary ops. */ + /* But zero can be created by valgrind internal optimizer */ + if (e->Iex.Const.con->Ico.V128 == 0) { + HReg res = newVRegV(env); + addInstr(env, ARMInstr_NeonImm(res, ARMNImm_TI(0, 0))); + return res; + } + ppIRExpr(e); + vpanic("128-bit constant is not implemented"); + } + + if (e->tag == Iex_Load) { + HReg res = newVRegV(env); + ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr); + vassert(ty == Ity_V128); + addInstr(env, ARMInstr_NLdStQ(True, res, am)); + return res; + } + + if (e->tag == Iex_Get) { + HReg addr = newVRegI(env); + HReg res = newVRegV(env); + vassert(ty == Ity_V128); + addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset)); + addInstr(env, ARMInstr_NLdStQ(True, res, mkARMAModeN_R(addr))); + return res; + } + + if (e->tag == Iex_Unop) { + switch (e->Iex.Unop.op) { + case Iop_NotV128: { + DECLARE_PATTERN(p_veqz_8x16); + DECLARE_PATTERN(p_veqz_16x8); + DECLARE_PATTERN(p_veqz_32x4); + DECLARE_PATTERN(p_vcge_8sx16); + DECLARE_PATTERN(p_vcge_16sx8); + DECLARE_PATTERN(p_vcge_32sx4); + DECLARE_PATTERN(p_vcge_8ux16); + DECLARE_PATTERN(p_vcge_16ux8); + DECLARE_PATTERN(p_vcge_32ux4); + DEFINE_PATTERN(p_veqz_8x16, + unop(Iop_NotV128, unop(Iop_CmpNEZ8x16, bind(0)))); + DEFINE_PATTERN(p_veqz_16x8, + unop(Iop_NotV128, unop(Iop_CmpNEZ16x8, bind(0)))); + DEFINE_PATTERN(p_veqz_32x4, + unop(Iop_NotV128, unop(Iop_CmpNEZ32x4, bind(0)))); + DEFINE_PATTERN(p_vcge_8sx16, + unop(Iop_NotV128, binop(Iop_CmpGT8Sx16, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_16sx8, + unop(Iop_NotV128, binop(Iop_CmpGT16Sx8, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_32sx4, + unop(Iop_NotV128, binop(Iop_CmpGT32Sx4, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_8ux16, + unop(Iop_NotV128, binop(Iop_CmpGT8Ux16, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_16ux8, + unop(Iop_NotV128, binop(Iop_CmpGT16Ux8, bind(1), bind(0)))); + DEFINE_PATTERN(p_vcge_32ux4, + unop(Iop_NotV128, binop(Iop_CmpGT32Ux4, bind(1), bind(0)))); + if (matchIRExpr(&mi, p_veqz_8x16, e)) { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, True)); + return res; + } else if (matchIRExpr(&mi, p_veqz_16x8, e)) { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, True)); + return res; + } else if (matchIRExpr(&mi, p_veqz_32x4, e)) { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, True)); + return res; + } else if (matchIRExpr(&mi, p_vcge_8sx16, e)) { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, mi.bindee[0]); + HReg argR = iselNeonExpr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, + res, argL, argR, 0, True)); + return res; + } else if (matchIRExpr(&mi, p_vcge_16sx8, e)) { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, mi.bindee[0]); + HReg argR = iselNeonExpr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, + res, argL, argR, 1, True)); + return res; + } else if (matchIRExpr(&mi, p_vcge_32sx4, e)) { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, mi.bindee[0]); + HReg argR = iselNeonExpr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, + res, argL, argR, 2, True)); + return res; + } else if (matchIRExpr(&mi, p_vcge_8ux16, e)) { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, mi.bindee[0]); + HReg argR = iselNeonExpr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, + res, argL, argR, 0, True)); + return res; + } else if (matchIRExpr(&mi, p_vcge_16ux8, e)) { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, mi.bindee[0]); + HReg argR = iselNeonExpr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, + res, argL, argR, 1, True)); + return res; + } else if (matchIRExpr(&mi, p_vcge_32ux4, e)) { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, mi.bindee[0]); + HReg argR = iselNeonExpr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, + res, argL, argR, 2, True)); + return res; + } else { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, True)); + return res; + } + } + case Iop_Dup8x16: + case Iop_Dup16x8: + case Iop_Dup32x4: { + HReg res, arg; + UInt size; + DECLARE_PATTERN(p_vdup_8x16); + DECLARE_PATTERN(p_vdup_16x8); + DECLARE_PATTERN(p_vdup_32x4); + DEFINE_PATTERN(p_vdup_8x16, + unop(Iop_Dup8x16, binop(Iop_GetElem8x8, bind(0), bind(1)))); + DEFINE_PATTERN(p_vdup_16x8, + unop(Iop_Dup16x8, binop(Iop_GetElem16x4, bind(0), bind(1)))); + DEFINE_PATTERN(p_vdup_32x4, + unop(Iop_Dup32x4, binop(Iop_GetElem32x2, bind(0), bind(1)))); + if (matchIRExpr(&mi, p_vdup_8x16, e)) { + UInt index; + UInt imm4; + if (mi.bindee[1]->tag == Iex_Const && + typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { + index = mi.bindee[1]->Iex.Const.con->Ico.U8; + imm4 = (index << 1) + 1; + if (index < 8) { + res = newVRegV(env); + arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnaryS( + ARMneon_VDUP, + mkARMNRS(ARMNRS_Reg, res, 0), + mkARMNRS(ARMNRS_Scalar, arg, index), + imm4, True + )); + return res; + } + } + } else if (matchIRExpr(&mi, p_vdup_16x8, e)) { + UInt index; + UInt imm4; + if (mi.bindee[1]->tag == Iex_Const && + typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { + index = mi.bindee[1]->Iex.Const.con->Ico.U8; + imm4 = (index << 2) + 2; + if (index < 4) { + res = newVRegV(env); + arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnaryS( + ARMneon_VDUP, + mkARMNRS(ARMNRS_Reg, res, 0), + mkARMNRS(ARMNRS_Scalar, arg, index), + imm4, True + )); + return res; + } + } + } else if (matchIRExpr(&mi, p_vdup_32x4, e)) { + UInt index; + UInt imm4; + if (mi.bindee[1]->tag == Iex_Const && + typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { + index = mi.bindee[1]->Iex.Const.con->Ico.U8; + imm4 = (index << 3) + 4; + if (index < 2) { + res = newVRegV(env); + arg = iselNeon64Expr(env, mi.bindee[0]); + addInstr(env, ARMInstr_NUnaryS( + ARMneon_VDUP, + mkARMNRS(ARMNRS_Reg, res, 0), + mkARMNRS(ARMNRS_Scalar, arg, index), + imm4, True + )); + return res; + } + } + } + arg = iselIntExpr_R(env, e->Iex.Unop.arg); + res = newVRegV(env); + switch (e->Iex.Unop.op) { + case Iop_Dup8x16: size = 0; break; + case Iop_Dup16x8: size = 1; break; + case Iop_Dup32x4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, True)); + return res; + } + case Iop_Abs8x16: + case Iop_Abs16x8: + case Iop_Abs32x4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Abs8x16: size = 0; break; + case Iop_Abs16x8: size = 1; break; + case Iop_Abs32x4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, True)); + return res; + } + case Iop_Reverse64_8x16: + case Iop_Reverse64_16x8: + case Iop_Reverse64_32x4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Reverse64_8x16: size = 0; break; + case Iop_Reverse64_16x8: size = 1; break; + case Iop_Reverse64_32x4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_REV64, + res, arg, size, True)); + return res; + } + case Iop_Reverse32_8x16: + case Iop_Reverse32_16x8: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Reverse32_8x16: size = 0; break; + case Iop_Reverse32_16x8: size = 1; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_REV32, + res, arg, size, True)); + return res; + } + case Iop_Reverse16_8x16: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + addInstr(env, ARMInstr_NUnary(ARMneon_REV16, + res, arg, size, True)); + return res; + } + case Iop_CmpNEZ64x2: { + HReg x_lsh = newVRegV(env); + HReg x_rsh = newVRegV(env); + HReg lsh_amt = newVRegV(env); + HReg rsh_amt = newVRegV(env); + HReg zero = newVRegV(env); + HReg tmp = newVRegV(env); + HReg tmp2 = newVRegV(env); + HReg res = newVRegV(env); + HReg x = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, True)); + addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, True)); + addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32))); + addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0))); + addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, + rsh_amt, zero, lsh_amt, 2, True)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + x_lsh, x, lsh_amt, 3, True)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + x_rsh, x, rsh_amt, 3, True)); + addInstr(env, ARMInstr_NBinary(ARMneon_VORR, + tmp, x_lsh, x_rsh, 0, True)); + addInstr(env, ARMInstr_NBinary(ARMneon_VORR, + res, tmp, x, 0, True)); + return res; + } + case Iop_CmpNEZ8x16: + case Iop_CmpNEZ16x8: + case Iop_CmpNEZ32x4: { + HReg res = newVRegV(env); + HReg tmp = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size; + switch (e->Iex.Unop.op) { + case Iop_CmpNEZ8x16: size = 0; break; + case Iop_CmpNEZ16x8: size = 1; break; + case Iop_CmpNEZ32x4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, True)); + addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, True)); + return res; + } + case Iop_Longen8Ux8: + case Iop_Longen16Ux4: + case Iop_Longen32Ux2: { + HReg res = newVRegV(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size; + switch (e->Iex.Unop.op) { + case Iop_Longen8Ux8: size = 0; break; + case Iop_Longen16Ux4: size = 1; break; + case Iop_Longen32Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_COPYLU, + res, arg, size, True)); + return res; + } + case Iop_Longen8Sx8: + case Iop_Longen16Sx4: + case Iop_Longen32Sx2: { + HReg res = newVRegV(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + UInt size; + switch (e->Iex.Unop.op) { + case Iop_Longen8Sx8: size = 0; break; + case Iop_Longen16Sx4: size = 1; break; + case Iop_Longen32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_COPYLS, + res, arg, size, True)); + return res; + } + case Iop_PwAddL8Sx16: + case Iop_PwAddL16Sx8: + case Iop_PwAddL32Sx4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwAddL8Sx16: size = 0; break; + case Iop_PwAddL16Sx8: size = 1; break; + case Iop_PwAddL32Sx4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS, + res, arg, size, True)); + return res; + } + case Iop_PwAddL8Ux16: + case Iop_PwAddL16Ux8: + case Iop_PwAddL32Ux4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwAddL8Ux16: size = 0; break; + case Iop_PwAddL16Ux8: size = 1; break; + case Iop_PwAddL32Ux4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU, + res, arg, size, True)); + return res; + } + case Iop_Cnt8x16: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + addInstr(env, ARMInstr_NUnary(ARMneon_CNT, res, arg, size, True)); + return res; + } + case Iop_Clz8Sx16: + case Iop_Clz16Sx8: + case Iop_Clz32Sx4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Clz8Sx16: size = 0; break; + case Iop_Clz16Sx8: size = 1; break; + case Iop_Clz32Sx4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, res, arg, size, True)); + return res; + } + case Iop_Cls8Sx16: + case Iop_Cls16Sx8: + case Iop_Cls32Sx4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Cls8Sx16: size = 0; break; + case Iop_Cls16Sx8: size = 1; break; + case Iop_Cls32Sx4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True)); + return res; + } + case Iop_FtoI32Sx4_RZ: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS, + res, arg, 2, True)); + return res; + } + case Iop_FtoI32Ux4_RZ: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU, + res, arg, 2, True)); + return res; + } + case Iop_I32StoFx4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF, + res, arg, 2, True)); + return res; + } + case Iop_I32UtoFx4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF, + res, arg, 2, True)); + return res; + } + case Iop_F16toF32x4: { + HReg res = newVRegV(env); + HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF16toF32, + res, arg, 2, True)); + return res; + } + case Iop_Recip32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF, + res, argL, 0, True)); + return res; + } + case Iop_Recip32x4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP, + res, argL, 0, True)); + return res; + } + case Iop_Abs32Fx4: { + DECLARE_PATTERN(p_vabd_32fx4); + DEFINE_PATTERN(p_vabd_32fx4, + unop(Iop_Abs32Fx4, + binop(Iop_Sub32Fx4, + bind(0), + bind(1)))); + if (matchIRExpr(&mi, p_vabd_32fx4, e)) { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, mi.bindee[0]); + HReg argR = iselNeonExpr(env, mi.bindee[1]); + addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP, + res, argL, argR, 0, True)); + return res; + } else { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP, + res, argL, 0, True)); + return res; + } + } + case Iop_Rsqrte32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP, + res, argL, 0, True)); + return res; + } + case Iop_Rsqrte32x4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE, + res, argL, 0, True)); + return res; + } + case Iop_Neg32Fx4: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF, + res, arg, 0, True)); + return res; + } + /* ... */ + default: + break; + } + } + + if (e->tag == Iex_Binop) { + switch (e->Iex.Binop.op) { + case Iop_64HLtoV128: + /* Try to match into single "VMOV reg, imm" instruction */ + if (e->Iex.Binop.arg1->tag == Iex_Const && + e->Iex.Binop.arg2->tag == Iex_Const && + typeOfIRExpr(env->type_env, e->Iex.Binop.arg1) == Ity_I64 && + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) == Ity_I64 && + e->Iex.Binop.arg1->Iex.Const.con->Ico.U64 == + e->Iex.Binop.arg2->Iex.Const.con->Ico.U64) { + ULong imm64 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U64; + ARMNImm *imm = Imm64_to_ARMNImm(imm64); + if (imm) { + HReg res = newVRegV(env); + addInstr(env, ARMInstr_NeonImm(res, imm)); + return res; + } + if ((imm64 >> 32) == 0LL && + (imm = Imm64_to_ARMNImm(imm64 | (imm64 << 32))) != NULL) { + HReg tmp1 = newVRegV(env); + HReg tmp2 = newVRegV(env); + HReg res = newVRegV(env); + if (imm->type < 10) { + addInstr(env, ARMInstr_NeonImm(tmp1, ARMNImm_TI(9,0x0f))); + addInstr(env, ARMInstr_NeonImm(tmp2, imm)); + addInstr(env, ARMInstr_NBinary(ARMneon_VAND, + res, tmp1, tmp2, 4, True)); + return res; + } + } + if ((imm64 & 0xFFFFFFFFLL) == 0LL && + (imm = Imm64_to_ARMNImm(imm64 | (imm64 >> 32))) != NULL) { + HReg tmp1 = newVRegV(env); + HReg tmp2 = newVRegV(env); + HReg res = newVRegV(env); + if (imm->type < 10) { + addInstr(env, ARMInstr_NeonImm(tmp1, ARMNImm_TI(9,0xf0))); + addInstr(env, ARMInstr_NeonImm(tmp2, imm)); + addInstr(env, ARMInstr_NBinary(ARMneon_VAND, + res, tmp1, tmp2, 4, True)); + return res; + } + } + } + /* Does not match "VMOV Reg, Imm" form */ + goto neon_expr_bad; + case Iop_AndV128: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VAND, + res, argL, argR, 4, True)); + return res; + } + case Iop_OrV128: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VORR, + res, argL, argR, 4, True)); + return res; + } + case Iop_XorV128: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VXOR, + res, argL, argR, 4, True)); + return res; + } + case Iop_Add8x16: + case Iop_Add16x8: + case Iop_Add32x4: + case Iop_Add64x2: { + /* + FIXME: remove this if not used + DECLARE_PATTERN(p_vrhadd_32sx4); + ULong one = (1LL << 32) | 1LL; + DEFINE_PATTERN(p_vrhadd_32sx4, + binop(Iop_Add32x4, + binop(Iop_Add32x4, + binop(Iop_SarN32x4, + bind(0), + mkU8(1)), + binop(Iop_SarN32x4, + bind(1), + mkU8(1))), + binop(Iop_SarN32x4, + binop(Iop_Add32x4, + binop(Iop_Add32x4, + binop(Iop_AndV128, + bind(0), + mkU128(one)), + binop(Iop_AndV128, + bind(1), + mkU128(one))), + mkU128(one)), + mkU8(1)))); + */ + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Add8x16: size = 0; break; + case Iop_Add16x8: size = 1; break; + case Iop_Add32x4: size = 2; break; + case Iop_Add64x2: size = 3; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VADD"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VADD, + res, argL, argR, size, True)); + return res; + } + case Iop_Add32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP, + res, argL, argR, size, True)); + return res; + } + case Iop_Recps32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS, + res, argL, argR, size, True)); + return res; + } + case Iop_Rsqrts32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS, + res, argL, argR, size, True)); + return res; + } + case Iop_InterleaveEvenLanes8x16: + case Iop_InterleaveEvenLanes16x8: + case Iop_InterleaveEvenLanes32x4: + case Iop_InterleaveOddLanes8x16: + case Iop_InterleaveOddLanes16x8: + case Iop_InterleaveOddLanes32x4: { + HReg tmp = newVRegV(env); + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + UInt is_lo; + switch (e->Iex.Binop.op) { + case Iop_InterleaveEvenLanes8x16: is_lo = 0; size = 0; break; + case Iop_InterleaveOddLanes8x16: is_lo = 1; size = 0; break; + case Iop_InterleaveEvenLanes16x8: is_lo = 0; size = 1; break; + case Iop_InterleaveOddLanes16x8: is_lo = 1; size = 1; break; + case Iop_InterleaveEvenLanes32x4: is_lo = 0; size = 2; break; + case Iop_InterleaveOddLanes32x4: is_lo = 1; size = 2; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VTRN"); + } + if (is_lo) { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argL, 4, True)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argR, 4, True)); + addInstr(env, ARMInstr_NDual(ARMneon_TRN, + res, tmp, size, True)); + } else { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argR, 4, True)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argL, 4, True)); + addInstr(env, ARMInstr_NDual(ARMneon_TRN, + tmp, res, size, True)); + } + return res; + } + case Iop_InterleaveHI8x16: + case Iop_InterleaveHI16x8: + case Iop_InterleaveHI32x4: + case Iop_InterleaveLO8x16: + case Iop_InterleaveLO16x8: + case Iop_InterleaveLO32x4: { + HReg tmp = newVRegV(env); + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + UInt is_lo; + switch (e->Iex.Binop.op) { + case Iop_InterleaveHI8x16: is_lo = 1; size = 0; break; + case Iop_InterleaveLO8x16: is_lo = 0; size = 0; break; + case Iop_InterleaveHI16x8: is_lo = 1; size = 1; break; + case Iop_InterleaveLO16x8: is_lo = 0; size = 1; break; + case Iop_InterleaveHI32x4: is_lo = 1; size = 2; break; + case Iop_InterleaveLO32x4: is_lo = 0; size = 2; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VZIP"); + } + if (is_lo) { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argL, 4, True)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argR, 4, True)); + addInstr(env, ARMInstr_NDual(ARMneon_ZIP, + res, tmp, size, True)); + } else { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argR, 4, True)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argL, 4, True)); + addInstr(env, ARMInstr_NDual(ARMneon_ZIP, + tmp, res, size, True)); + } + return res; + } + case Iop_CatOddLanes8x16: + case Iop_CatOddLanes16x8: + case Iop_CatOddLanes32x4: + case Iop_CatEvenLanes8x16: + case Iop_CatEvenLanes16x8: + case Iop_CatEvenLanes32x4: { + HReg tmp = newVRegV(env); + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + UInt is_lo; + switch (e->Iex.Binop.op) { + case Iop_CatOddLanes8x16: is_lo = 1; size = 0; break; + case Iop_CatEvenLanes8x16: is_lo = 0; size = 0; break; + case Iop_CatOddLanes16x8: is_lo = 1; size = 1; break; + case Iop_CatEvenLanes16x8: is_lo = 0; size = 1; break; + case Iop_CatOddLanes32x4: is_lo = 1; size = 2; break; + case Iop_CatEvenLanes32x4: is_lo = 0; size = 2; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VUZP"); + } + if (is_lo) { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argL, 4, True)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argR, 4, True)); + addInstr(env, ARMInstr_NDual(ARMneon_UZP, + res, tmp, size, True)); + } else { + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + tmp, argR, 4, True)); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, + res, argL, 4, True)); + addInstr(env, ARMInstr_NDual(ARMneon_UZP, + tmp, res, size, True)); + } + return res; + } + case Iop_QAdd8Ux16: + case Iop_QAdd16Ux8: + case Iop_QAdd32Ux4: + case Iop_QAdd64Ux2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QAdd8Ux16: size = 0; break; + case Iop_QAdd16Ux8: size = 1; break; + case Iop_QAdd32Ux4: size = 2; break; + case Iop_QAdd64Ux2: size = 3; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VQADDU"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU, + res, argL, argR, size, True)); + return res; + } + case Iop_QAdd8Sx16: + case Iop_QAdd16Sx8: + case Iop_QAdd32Sx4: + case Iop_QAdd64Sx2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QAdd8Sx16: size = 0; break; + case Iop_QAdd16Sx8: size = 1; break; + case Iop_QAdd32Sx4: size = 2; break; + case Iop_QAdd64Sx2: size = 3; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VQADDS"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS, + res, argL, argR, size, True)); + return res; + } + case Iop_Sub8x16: + case Iop_Sub16x8: + case Iop_Sub32x4: + case Iop_Sub64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Sub8x16: size = 0; break; + case Iop_Sub16x8: size = 1; break; + case Iop_Sub32x4: size = 2; break; + case Iop_Sub64x2: size = 3; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VSUB"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, + res, argL, argR, size, True)); + return res; + } + case Iop_Sub32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP, + res, argL, argR, size, True)); + return res; + } + case Iop_QSub8Ux16: + case Iop_QSub16Ux8: + case Iop_QSub32Ux4: + case Iop_QSub64Ux2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QSub8Ux16: size = 0; break; + case Iop_QSub16Ux8: size = 1; break; + case Iop_QSub32Ux4: size = 2; break; + case Iop_QSub64Ux2: size = 3; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VQSUBU"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU, + res, argL, argR, size, True)); + return res; + } + case Iop_QSub8Sx16: + case Iop_QSub16Sx8: + case Iop_QSub32Sx4: + case Iop_QSub64Sx2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QSub8Sx16: size = 0; break; + case Iop_QSub16Sx8: size = 1; break; + case Iop_QSub32Sx4: size = 2; break; + case Iop_QSub64Sx2: size = 3; break; + default: + ppIROp(e->Iex.Binop.op); + vpanic("Illegal element size in VQSUBS"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS, + res, argL, argR, size, True)); + return res; + } + case Iop_Max8Ux16: + case Iop_Max16Ux8: + case Iop_Max32Ux4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Max8Ux16: size = 0; break; + case Iop_Max16Ux8: size = 1; break; + case Iop_Max32Ux4: size = 2; break; + default: vpanic("Illegal element size in VMAXU"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU, + res, argL, argR, size, True)); + return res; + } + case Iop_Max8Sx16: + case Iop_Max16Sx8: + case Iop_Max32Sx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Max8Sx16: size = 0; break; + case Iop_Max16Sx8: size = 1; break; + case Iop_Max32Sx4: size = 2; break; + default: vpanic("Illegal element size in VMAXU"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS, + res, argL, argR, size, True)); + return res; + } + case Iop_Min8Ux16: + case Iop_Min16Ux8: + case Iop_Min32Ux4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Min8Ux16: size = 0; break; + case Iop_Min16Ux8: size = 1; break; + case Iop_Min32Ux4: size = 2; break; + default: vpanic("Illegal element size in VMAXU"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMINU, + res, argL, argR, size, True)); + return res; + } + case Iop_Min8Sx16: + case Iop_Min16Sx8: + case Iop_Min32Sx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Min8Sx16: size = 0; break; + case Iop_Min16Sx8: size = 1; break; + case Iop_Min32Sx4: size = 2; break; + default: vpanic("Illegal element size in VMAXU"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMINS, + res, argL, argR, size, True)); + return res; + } + case Iop_Sar8x16: + case Iop_Sar16x8: + case Iop_Sar32x4: + case Iop_Sar64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + HReg argR2 = newVRegV(env); + HReg zero = newVRegV(env); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Sar8x16: size = 0; break; + case Iop_Sar16x8: size = 1; break; + case Iop_Sar32x4: size = 2; break; + case Iop_Sar64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); + addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, + argR2, zero, argR, size, True)); + addInstr(env, ARMInstr_NShift(ARMneon_VSAL, + res, argL, argR2, size, True)); + return res; + } + case Iop_Sal8x16: + case Iop_Sal16x8: + case Iop_Sal32x4: + case Iop_Sal64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Sal8x16: size = 0; break; + case Iop_Sal16x8: size = 1; break; + case Iop_Sal32x4: size = 2; break; + case Iop_Sal64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NShift(ARMneon_VSAL, + res, argL, argR, size, True)); + return res; + } + case Iop_Shr8x16: + case Iop_Shr16x8: + case Iop_Shr32x4: + case Iop_Shr64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + HReg argR2 = newVRegV(env); + HReg zero = newVRegV(env); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Shr8x16: size = 0; break; + case Iop_Shr16x8: size = 1; break; + case Iop_Shr32x4: size = 2; break; + case Iop_Shr64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); + addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, + argR2, zero, argR, size, True)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + res, argL, argR2, size, True)); + return res; + } + case Iop_Shl8x16: + case Iop_Shl16x8: + case Iop_Shl32x4: + case Iop_Shl64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_Shl8x16: size = 0; break; + case Iop_Shl16x8: size = 1; break; + case Iop_Shl32x4: size = 2; break; + case Iop_Shl64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + res, argL, argR, size, True)); + return res; + } + case Iop_QShl8x16: + case Iop_QShl16x8: + case Iop_QShl32x4: + case Iop_QShl64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QShl8x16: size = 0; break; + case Iop_QShl16x8: size = 1; break; + case Iop_QShl32x4: size = 2; break; + case Iop_QShl64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NShift(ARMneon_VQSHL, + res, argL, argR, size, True)); + return res; + } + case Iop_QSal8x16: + case Iop_QSal16x8: + case Iop_QSal32x4: + case Iop_QSal64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_QSal8x16: size = 0; break; + case Iop_QSal16x8: size = 1; break; + case Iop_QSal32x4: size = 2; break; + case Iop_QSal64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NShift(ARMneon_VQSAL, + res, argL, argR, size, True)); + return res; + } + case Iop_QShlN8x16: + case Iop_QShlN16x8: + case Iop_QShlN32x4: + case Iop_QShlN64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + UInt size, imm; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM taget supports Iop_QShlNAxB with constant " + "second argument only\n"); + } + imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Binop.op) { + case Iop_QShlN8x16: size = 8 | imm; break; + case Iop_QShlN16x8: size = 16 | imm; break; + case Iop_QShlN32x4: size = 32 | imm; break; + case Iop_QShlN64x2: size = 64 | imm; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU, + res, argL, size, True)); + return res; + } + case Iop_QShlN8Sx16: + case Iop_QShlN16Sx8: + case Iop_QShlN32Sx4: + case Iop_QShlN64Sx2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + UInt size, imm; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM taget supports Iop_QShlNASxB with constant " + "second argument only\n"); + } + imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Binop.op) { + case Iop_QShlN8Sx16: size = 8 | imm; break; + case Iop_QShlN16Sx8: size = 16 | imm; break; + case Iop_QShlN32Sx4: size = 32 | imm; break; + case Iop_QShlN64Sx2: size = 64 | imm; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS, + res, argL, size, True)); + return res; + } + case Iop_QSalN8x16: + case Iop_QSalN16x8: + case Iop_QSalN32x4: + case Iop_QSalN64x2: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + UInt size, imm; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM taget supports Iop_QShlNAxB with constant " + "second argument only\n"); + } + imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch (e->Iex.Binop.op) { + case Iop_QSalN8x16: size = 8 | imm; break; + case Iop_QSalN16x8: size = 16 | imm; break; + case Iop_QSalN32x4: size = 32 | imm; break; + case Iop_QSalN64x2: size = 64 | imm; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, + res, argL, size, True)); + return res; + } + case Iop_ShrN8x16: + case Iop_ShrN16x8: + case Iop_ShrN32x4: + case Iop_ShrN64x2: { + HReg res = newVRegV(env); + HReg tmp = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg argR2 = newVRegI(env); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_ShrN8x16: size = 0; break; + case Iop_ShrN16x8: size = 1; break; + case Iop_ShrN32x4: size = 2; break; + case Iop_ShrN64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); + addInstr(env, ARMInstr_NUnary(ARMneon_DUP, + tmp, argR2, 0, True)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + res, argL, tmp, size, True)); + return res; + } + case Iop_ShlN8x16: + case Iop_ShlN16x8: + case Iop_ShlN32x4: + case Iop_ShlN64x2: { + HReg res = newVRegV(env); + HReg tmp = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_ShlN8x16: size = 0; break; + case Iop_ShlN16x8: size = 1; break; + case Iop_ShlN32x4: size = 2; break; + case Iop_ShlN64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR, 0, True)); + addInstr(env, ARMInstr_NShift(ARMneon_VSHL, + res, argL, tmp, size, True)); + return res; + } + case Iop_SarN8x16: + case Iop_SarN16x8: + case Iop_SarN32x4: + case Iop_SarN64x2: { + HReg res = newVRegV(env); + HReg tmp = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); + HReg argR2 = newVRegI(env); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_SarN8x16: size = 0; break; + case Iop_SarN16x8: size = 1; break; + case Iop_SarN32x4: size = 2; break; + case Iop_SarN64x2: size = 3; break; + default: vassert(0); + } + addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); + addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, True)); + addInstr(env, ARMInstr_NShift(ARMneon_VSAL, + res, argL, tmp, size, True)); + return res; + } + case Iop_CmpGT8Ux16: + case Iop_CmpGT16Ux8: + case Iop_CmpGT32Ux4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_CmpGT8Ux16: size = 0; break; + case Iop_CmpGT16Ux8: size = 1; break; + case Iop_CmpGT32Ux4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU, + res, argL, argR, size, True)); + return res; + } + case Iop_CmpGT8Sx16: + case Iop_CmpGT16Sx8: + case Iop_CmpGT32Sx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_CmpGT8Sx16: size = 0; break; + case Iop_CmpGT16Sx8: size = 1; break; + case Iop_CmpGT32Sx4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS, + res, argL, argR, size, True)); + return res; + } + case Iop_CmpEQ8x16: + case Iop_CmpEQ16x8: + case Iop_CmpEQ32x4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size; + switch (e->Iex.Binop.op) { + case Iop_CmpEQ8x16: size = 0; break; + case Iop_CmpEQ16x8: size = 1; break; + case Iop_CmpEQ32x4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ, + res, argL, argR, size, True)); + return res; + } + case Iop_Mul8x16: + case Iop_Mul16x8: + case Iop_Mul32x4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Mul8x16: size = 0; break; + case Iop_Mul16x8: size = 1; break; + case Iop_Mul32x4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMUL, + res, argL, argR, size, True)); + return res; + } + case Iop_Mul32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP, + res, argL, argR, size, True)); + return res; + } + case Iop_Mull8Ux8: + case Iop_Mull16Ux4: + case Iop_Mull32Ux2: { + HReg res = newVRegV(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Mull8Ux8: size = 0; break; + case Iop_Mull16Ux4: size = 1; break; + case Iop_Mull32Ux2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMULLU, + res, argL, argR, size, True)); + return res; + } + + case Iop_Mull8Sx8: + case Iop_Mull16Sx4: + case Iop_Mull32Sx2: { + HReg res = newVRegV(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_Mull8Sx8: size = 0; break; + case Iop_Mull16Sx4: size = 1; break; + case Iop_Mull32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VMULLS, + res, argL, argR, size, True)); + return res; + } + + case Iop_QDMulHi16Sx8: + case Iop_QDMulHi32Sx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_QDMulHi16Sx8: size = 1; break; + case Iop_QDMulHi32Sx4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH, + res, argL, argR, size, True)); + return res; + } + + case Iop_QRDMulHi16Sx8: + case Iop_QRDMulHi32Sx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_QRDMulHi16Sx8: size = 1; break; + case Iop_QRDMulHi32Sx4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH, + res, argL, argR, size, True)); + return res; + } + + case Iop_QDMulLong16Sx4: + case Iop_QDMulLong32Sx2: { + HReg res = newVRegV(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_QDMulLong16Sx4: size = 1; break; + case Iop_QDMulLong32Sx2: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULL, + res, argL, argR, size, True)); + return res; + } + case Iop_PolynomialMul8x16: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VMULP, + res, argL, argR, size, True)); + return res; + } + case Iop_Max32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF, + res, argL, argR, 2, True)); + return res; + } + case Iop_Min32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VMINF, + res, argL, argR, 2, True)); + return res; + } + case Iop_PwMax32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF, + res, argL, argR, 2, True)); + return res; + } + case Iop_PwMin32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF, + res, argL, argR, 2, True)); + return res; + } + case Iop_CmpGT32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF, + res, argL, argR, 2, True)); + return res; + } + case Iop_CmpGE32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF, + res, argL, argR, 2, True)); + return res; + } + case Iop_CmpEQ32Fx4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF, + res, argL, argR, 2, True)); + return res; + } + + case Iop_PolynomialMull8x8: { + HReg res = newVRegV(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); + UInt size = 0; + addInstr(env, ARMInstr_NBinary(ARMneon_VMULLP, + res, argL, argR, size, True)); + return res; + } + case Iop_F32ToFixed32Ux4_RZ: + case Iop_F32ToFixed32Sx4_RZ: + case Iop_Fixed32UToF32x4_RN: + case Iop_Fixed32SToF32x4_RN: { + HReg res = newVRegV(env); + HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1); + ARMNeonUnOp op; + UInt imm6; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM supports FP <-> Fixed conversion with constant " + "second argument less than 33 only\n"); + } + imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + vassert(imm6 <= 32 && imm6 > 0); + imm6 = 64 - imm6; + switch(e->Iex.Binop.op) { + case Iop_F32ToFixed32Ux4_RZ: op = ARMneon_VCVTFtoFixedU; break; + case Iop_F32ToFixed32Sx4_RZ: op = ARMneon_VCVTFtoFixedS; break; + case Iop_Fixed32UToF32x4_RN: op = ARMneon_VCVTFixedUtoF; break; + case Iop_Fixed32SToF32x4_RN: op = ARMneon_VCVTFixedStoF; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True)); + return res; + } + /* + FIXME remove if not used + case Iop_VDup8x16: + case Iop_VDup16x8: + case Iop_VDup32x4: { + HReg res = newVRegV(env); + HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); + UInt imm4; + UInt index; + if (e->Iex.Binop.arg2->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { + vpanic("ARM supports Iop_VDup with constant " + "second argument less than 16 only\n"); + } + index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; + switch(e->Iex.Binop.op) { + case Iop_VDup8x16: imm4 = (index << 1) + 1; break; + case Iop_VDup16x8: imm4 = (index << 2) + 2; break; + case Iop_VDup32x4: imm4 = (index << 3) + 4; break; + default: vassert(0); + } + if (imm4 >= 16) { + vpanic("ARM supports Iop_VDup with constant " + "second argument less than 16 only\n"); + } + addInstr(env, ARMInstr_NUnary(ARMneon_VDUP, + res, argL, imm4, True)); + return res; + } + */ + case Iop_PwAdd8x16: + case Iop_PwAdd16x8: + case Iop_PwAdd32x4: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); + UInt size = 0; + switch(e->Iex.Binop.op) { + case Iop_PwAdd8x16: size = 0; break; + case Iop_PwAdd16x8: size = 1; break; + case Iop_PwAdd32x4: size = 2; break; + default: vassert(0); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VPADD, + res, argL, argR, size, True)); + return res; + } + /* ... */ + default: + break; + } + } + + if (e->tag == Iex_Triop) { + switch (e->Iex.Triop.op) { + case Iop_ExtractV128: { + HReg res = newVRegV(env); + HReg argL = iselNeonExpr(env, e->Iex.Triop.arg1); + HReg argR = iselNeonExpr(env, e->Iex.Triop.arg2); + UInt imm4; + if (e->Iex.Triop.arg3->tag != Iex_Const || + typeOfIRExpr(env->type_env, e->Iex.Triop.arg3) != Ity_I8) { + vpanic("ARM target supports Iop_ExtractV128 with constant " + "third argument less than 16 only\n"); + } + imm4 = e->Iex.Triop.arg3->Iex.Const.con->Ico.U8; + if (imm4 >= 16) { + vpanic("ARM target supports Iop_ExtractV128 with constant " + "third argument less than 16 only\n"); + } + addInstr(env, ARMInstr_NBinary(ARMneon_VEXT, + res, argL, argR, imm4, True)); + return res; + } + default: + break; + } + } + + if (e->tag == Iex_Mux0X) { + HReg r8; + HReg rX = iselNeonExpr(env, e->Iex.Mux0X.exprX); + HReg r0 = iselNeonExpr(env, e->Iex.Mux0X.expr0); + HReg dst = newVRegV(env); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, rX, 4, True)); + r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond); + addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8, + ARMRI84_I84(0xFF,0))); + addInstr(env, ARMInstr_NCMovQ(ARMcc_EQ, dst, r0)); + return dst; + } + + neon_expr_bad: + ppIRExpr(e); + vpanic("iselNeonExpr_wrk"); +} + +/*---------------------------------------------------------*/ +/*--- ISEL: Floating point expressions (64 bit) ---*/ +/*---------------------------------------------------------*/ + +/* Compute a 64-bit floating point value into a register, the identity + of which is returned. As with iselIntExpr_R, the reg may be either + real or virtual; in any case it must not be changed by subsequent + code emitted by the caller. */ + +static HReg iselDblExpr ( ISelEnv* env, IRExpr* e ) +{ + HReg r = iselDblExpr_wrk( env, e ); +# if 0 + vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); +# endif + vassert(hregClass(r) == HRcFlt64); + vassert(hregIsVirtual(r)); + return r; +} + +/* DO NOT CALL THIS DIRECTLY */ +static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env,e); + vassert(e); + vassert(ty == Ity_F64); + + if (e->tag == Iex_RdTmp) { + return lookupIRTemp(env, e->Iex.RdTmp.tmp); + } + + if (e->tag == Iex_Const) { + /* Just handle the zero case. */ + IRConst* con = e->Iex.Const.con; + if (con->tag == Ico_F64i && con->Ico.F64i == 0ULL) { + HReg z32 = newVRegI(env); + HReg dst = newVRegD(env); + addInstr(env, ARMInstr_Imm32(z32, 0)); + addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, z32, z32)); + return dst; + } + } + + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { + ARMAModeV* am; + HReg res = newVRegD(env); + vassert(e->Iex.Load.ty == Ity_F64); + am = iselIntExpr_AModeV(env, e->Iex.Load.addr); + addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am)); + return res; + } + + if (e->tag == Iex_Get) { + // XXX This won't work if offset > 1020 or is not 0 % 4. + // In which case we'll have to generate more longwinded code. + ARMAModeV* am = mkARMAModeV(hregARM_R8(), e->Iex.Get.offset); + HReg res = newVRegD(env); + addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am)); + return res; + } + + if (e->tag == Iex_Unop) { + switch (e->Iex.Unop.op) { + case Iop_ReinterpI64asF64: { + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + return iselNeon64Expr(env, e->Iex.Unop.arg); + } else { + HReg srcHi, srcLo; + HReg dst = newVRegD(env); + iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, srcHi, srcLo)); + return dst; + } + } + case Iop_NegF64: { + HReg src = iselDblExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegD(env); + addInstr(env, ARMInstr_VUnaryD(ARMvfpu_NEG, dst, src)); + return dst; + } + case Iop_AbsF64: { + HReg src = iselDblExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegD(env); + addInstr(env, ARMInstr_VUnaryD(ARMvfpu_ABS, dst, src)); + return dst; + } + case Iop_F32toF64: { + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegD(env); + addInstr(env, ARMInstr_VCvtSD(True/*sToD*/, dst, src)); + return dst; + } + case Iop_I32UtoF64: + case Iop_I32StoF64: { + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + HReg f32 = newVRegF(env); + HReg dst = newVRegD(env); + Bool syned = e->Iex.Unop.op == Iop_I32StoF64; + /* VMOV f32, src */ + addInstr(env, ARMInstr_VXferS(True/*toS*/, f32, src)); + /* FSITOD dst, f32 */ + addInstr(env, ARMInstr_VCvtID(True/*iToD*/, syned, + dst, f32)); + return dst; + } + default: + break; + } + } + + if (e->tag == Iex_Binop) { + switch (e->Iex.Binop.op) { + case Iop_SqrtF64: { + /* first arg is rounding mode; we ignore it. */ + HReg src = iselDblExpr(env, e->Iex.Binop.arg2); + HReg dst = newVRegD(env); + addInstr(env, ARMInstr_VUnaryD(ARMvfpu_SQRT, dst, src)); + return dst; + } + default: + break; + } + } + + if (e->tag == Iex_Triop) { + switch (e->Iex.Triop.op) { + case Iop_DivF64: + case Iop_MulF64: + case Iop_AddF64: + case Iop_SubF64: { + ARMVfpOp op = 0; /*INVALID*/ + HReg argL = iselDblExpr(env, e->Iex.Triop.arg2); + HReg argR = iselDblExpr(env, e->Iex.Triop.arg3); + HReg dst = newVRegD(env); + switch (e->Iex.Triop.op) { + case Iop_DivF64: op = ARMvfp_DIV; break; + case Iop_MulF64: op = ARMvfp_MUL; break; + case Iop_AddF64: op = ARMvfp_ADD; break; + case Iop_SubF64: op = ARMvfp_SUB; break; + default: vassert(0); + } + addInstr(env, ARMInstr_VAluD(op, dst, argL, argR)); + return dst; + } + default: + break; + } + } + + if (e->tag == Iex_Mux0X) { + if (ty == Ity_F64 + && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) { + HReg r8; + HReg rX = iselDblExpr(env, e->Iex.Mux0X.exprX); + HReg r0 = iselDblExpr(env, e->Iex.Mux0X.expr0); + HReg dst = newVRegD(env); + addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, rX)); + r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond); + addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8, + ARMRI84_I84(0xFF,0))); + addInstr(env, ARMInstr_VCMovD(ARMcc_EQ, dst, r0)); + return dst; + } + } + + ppIRExpr(e); + vpanic("iselDblExpr_wrk"); +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Floating point expressions (32 bit) ---*/ +/*---------------------------------------------------------*/ + +/* Compute a 64-bit floating point value into a register, the identity + of which is returned. As with iselIntExpr_R, the reg may be either + real or virtual; in any case it must not be changed by subsequent + code emitted by the caller. */ + +static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ) +{ + HReg r = iselFltExpr_wrk( env, e ); +# if 0 + vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); +# endif + vassert(hregClass(r) == HRcFlt32); + vassert(hregIsVirtual(r)); + return r; +} + +/* DO NOT CALL THIS DIRECTLY */ +static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env,e); + vassert(e); + vassert(ty == Ity_F32); + + if (e->tag == Iex_RdTmp) { + return lookupIRTemp(env, e->Iex.RdTmp.tmp); + } + + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { + ARMAModeV* am; + HReg res = newVRegF(env); + vassert(e->Iex.Load.ty == Ity_F32); + am = iselIntExpr_AModeV(env, e->Iex.Load.addr); + addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am)); + return res; + } + + if (e->tag == Iex_Get) { + // XXX This won't work if offset > 1020 or is not 0 % 4. + // In which case we'll have to generate more longwinded code. + ARMAModeV* am = mkARMAModeV(hregARM_R8(), e->Iex.Get.offset); + HReg res = newVRegF(env); + addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am)); + return res; + } + + if (e->tag == Iex_Unop) { + switch (e->Iex.Unop.op) { + case Iop_ReinterpI32asF32: { + HReg dst = newVRegF(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, ARMInstr_VXferS(True/*toS*/, dst, src)); + return dst; + } + case Iop_NegF32: { + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegF(env); + addInstr(env, ARMInstr_VUnaryS(ARMvfpu_NEG, dst, src)); + return dst; + } + case Iop_AbsF32: { + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegF(env); + addInstr(env, ARMInstr_VUnaryS(ARMvfpu_ABS, dst, src)); + return dst; + } + default: + break; + } + } + + if (e->tag == Iex_Binop) { + switch (e->Iex.Binop.op) { + case Iop_SqrtF32: { + /* first arg is rounding mode; we ignore it. */ + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + HReg dst = newVRegF(env); + addInstr(env, ARMInstr_VUnaryS(ARMvfpu_SQRT, dst, src)); + return dst; + } + case Iop_F64toF32: { + HReg valD = iselDblExpr(env, e->Iex.Binop.arg2); + set_VFP_rounding_mode(env, e->Iex.Binop.arg1); + HReg valS = newVRegF(env); + /* FCVTSD valS, valD */ + addInstr(env, ARMInstr_VCvtSD(False/*!sToD*/, valS, valD)); + set_VFP_rounding_default(env); + return valS; + } + default: + break; + } + } + + if (e->tag == Iex_Triop) { + switch (e->Iex.Triop.op) { + case Iop_DivF32: + case Iop_MulF32: + case Iop_AddF32: + case Iop_SubF32: { + ARMVfpOp op = 0; /*INVALID*/ + HReg argL = iselFltExpr(env, e->Iex.Triop.arg2); + HReg argR = iselFltExpr(env, e->Iex.Triop.arg3); + HReg dst = newVRegF(env); + switch (e->Iex.Triop.op) { + case Iop_DivF32: op = ARMvfp_DIV; break; + case Iop_MulF32: op = ARMvfp_MUL; break; + case Iop_AddF32: op = ARMvfp_ADD; break; + case Iop_SubF32: op = ARMvfp_SUB; break; + default: vassert(0); + } + addInstr(env, ARMInstr_VAluS(op, dst, argL, argR)); + return dst; + } + default: + break; + } + } + + if (e->tag == Iex_Mux0X) { + if (ty == Ity_F32 + && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) { + HReg r8; + HReg rX = iselFltExpr(env, e->Iex.Mux0X.exprX); + HReg r0 = iselFltExpr(env, e->Iex.Mux0X.expr0); + HReg dst = newVRegF(env); + addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, rX)); + r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond); + addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8, + ARMRI84_I84(0xFF,0))); + addInstr(env, ARMInstr_VCMovS(ARMcc_EQ, dst, r0)); + return dst; + } + } + + ppIRExpr(e); + vpanic("iselFltExpr_wrk"); +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Statements ---*/ +/*---------------------------------------------------------*/ + +static void iselStmt ( ISelEnv* env, IRStmt* stmt ) +{ + if (vex_traceflags & VEX_TRACE_VCODE) { + vex_printf("\n-- "); + ppIRStmt(stmt); + vex_printf("\n"); + } + switch (stmt->tag) { + + /* --------- STORE --------- */ + /* little-endian write to memory */ + case Ist_Store: { + IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr); + IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); + IREndness end = stmt->Ist.Store.end; + + if (tya != Ity_I32 || end != Iend_LE) + goto stmt_fail; + + if (tyd == Ity_I32) { + HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); + ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr); + addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rD, am)); + return; + } + if (tyd == Ity_I16) { + HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); + ARMAMode2* am = iselIntExpr_AMode2(env, stmt->Ist.Store.addr); + addInstr(env, ARMInstr_LdSt16(False/*!isLoad*/, + False/*!isSignedLoad*/, rD, am)); + return; + } + if (tyd == Ity_I8) { + HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); + ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr); + addInstr(env, ARMInstr_LdSt8U(False/*!isLoad*/, rD, am)); + return; + } + if (tyd == Ity_I64) { + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + HReg dD = iselNeon64Expr(env, stmt->Ist.Store.data); + ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr); + addInstr(env, ARMInstr_NLdStD(False, dD, am)); + } else { + HReg rDhi, rDlo, rA; + iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data); + rA = iselIntExpr_R(env, stmt->Ist.Store.addr); + addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDhi, + ARMAMode1_RI(rA,4))); + addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDlo, + ARMAMode1_RI(rA,0))); + } + return; + } + if (tyd == Ity_F64) { + HReg dD = iselDblExpr(env, stmt->Ist.Store.data); + ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr); + addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, dD, am)); + return; + } + if (tyd == Ity_F32) { + HReg fD = iselFltExpr(env, stmt->Ist.Store.data); + ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr); + addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, fD, am)); + return; + } + if (tyd == Ity_V128) { + HReg qD = iselNeonExpr(env, stmt->Ist.Store.data); + ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr); + addInstr(env, ARMInstr_NLdStQ(False, qD, am)); + return; + } + + break; } /* --------- PUT --------- */ /* write guest state, fixed offset */ case Ist_Put: { IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Put.data); - HReg reg = iselIntExpr_R(env, stmt->Ist.Put.data); - // CAB: This anywhere near right?! if (tyd == Ity_I32) { - ARMAMode2* am2 = ARMAMode2_RI(GET_BP_REG(), stmt->Ist.Put.offset); - addInstr(env, ARMInstr_StoreW(reg, am2)); - return; + HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); + ARMAMode1* am = ARMAMode1_RI(hregARM_R8(), stmt->Ist.Put.offset); + addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rD, am)); + return; } - if (tyd == Ity_I16) { - ARMAMode3* am3 = ARMAMode3_RI(GET_BP_REG(), stmt->Ist.Put.offset); - addInstr(env, ARMInstr_StoreH(reg, am3)); - return; + if (tyd == Ity_I64) { + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + HReg addr = newVRegI(env); + HReg qD = iselNeon64Expr(env, stmt->Ist.Put.data); + addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), + stmt->Ist.Put.offset)); + addInstr(env, ARMInstr_NLdStD(False, qD, mkARMAModeN_R(addr))); + } else { + HReg rDhi, rDlo; + ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(), + stmt->Ist.Put.offset + 0); + ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), + stmt->Ist.Put.offset + 4); + iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data); + addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDhi, am4)); + addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDlo, am0)); + } + return; } - if (tyd == Ity_I8) { - ARMAMode2* am2 = ARMAMode2_RI(GET_BP_REG(), stmt->Ist.Put.offset); - addInstr(env, ARMInstr_StoreB(reg, am2)); - return; + if (tyd == Ity_F64) { + // XXX This won't work if offset > 1020 or is not 0 % 4. + // In which case we'll have to generate more longwinded code. + ARMAModeV* am = mkARMAModeV(hregARM_R8(), stmt->Ist.Put.offset); + HReg rD = iselDblExpr(env, stmt->Ist.Put.data); + addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, rD, am)); + return; } -// CAB: Ity_I32, Ity_I16 ? - break; - } - - /* --------- Indexed PUT --------- */ - /* write guest state, run-time offset */ - case Ist_PutI: { - ARMAMode2* am2 - = genGuestArrayOffset( - env, stmt->Ist.PutI.descr, - stmt->Ist.PutI.ix, stmt->Ist.PutI.bias ); - - IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.PutI.data); - - if (tyd == Ity_I8) { - HReg reg = iselIntExpr_R(env, stmt->Ist.PutI.data); - addInstr(env, ARMInstr_StoreB(reg, am2)); - return; + if (tyd == Ity_F32) { + // XXX This won't work if offset > 1020 or is not 0 % 4. + // In which case we'll have to generate more longwinded code. + ARMAModeV* am = mkARMAModeV(hregARM_R8(), stmt->Ist.Put.offset); + HReg rD = iselFltExpr(env, stmt->Ist.Put.data); + addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, rD, am)); + return; + } + if (tyd == Ity_V128) { + HReg addr = newVRegI(env); + HReg qD = iselNeonExpr(env, stmt->Ist.Put.data); + addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), + stmt->Ist.Put.offset)); + addInstr(env, ARMInstr_NLdStQ(False, qD, mkARMAModeN_R(addr))); + return; } -// CAB: Ity_I32, Ity_I16 ? break; } +//zz /* --------- Indexed PUT --------- */ +//zz /* write guest state, run-time offset */ +//zz case Ist_PutI: { +//zz ARMAMode2* am2 +//zz = genGuestArrayOffset( +//zz env, stmt->Ist.PutI.descr, +//zz stmt->Ist.PutI.ix, stmt->Ist.PutI.bias ); +//zz +//zz IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.PutI.data); +//zz +//zz if (tyd == Ity_I8) { +//zz HReg reg = iselIntExpr_R(env, stmt->Ist.PutI.data); +//zz addInstr(env, ARMInstr_StoreB(reg, am2)); +//zz return; +//zz } +//zz// CAB: Ity_I32, Ity_I16 ? +//zz break; +//zz } + /* --------- TMP --------- */ /* assign value to temporary */ case Ist_WrTmp: { @@ -833,23 +5716,60 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) IRType ty = typeOfIRTemp(env->type_env, tmp); if (ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8) { - ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.WrTmp.data); + ARMRI84* ri84 = iselIntExpr_RI84(NULL, False, + env, stmt->Ist.WrTmp.data); + HReg dst = lookupIRTemp(env, tmp); + addInstr(env, ARMInstr_Mov(dst,ri84)); + return; + } + if (ty == Ity_I1) { + HReg dst = lookupIRTemp(env, tmp); + ARMCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data); + addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); + addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); + return; + } + if (ty == Ity_I64) { + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + HReg src = iselNeon64Expr(env, stmt->Ist.WrTmp.data); + HReg dst = lookupIRTemp(env, tmp); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, src, 4, False)); + } else { + HReg rHi, rLo, dstHi, dstLo; + iselInt64Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data); + lookupIRTemp64( &dstHi, &dstLo, env, tmp); + addInstr(env, mk_iMOVds_RR(dstHi, rHi) ); + addInstr(env, mk_iMOVds_RR(dstLo, rLo) ); + } + return; + } + if (ty == Ity_F64) { + HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data); HReg dst = lookupIRTemp(env, tmp); - addInstr(env, ARMInstr_DPInstr1(ARMalu_MOV,dst,am)); + addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, src)); + return; + } + if (ty == Ity_F32) { + HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data); + HReg dst = lookupIRTemp(env, tmp); + addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, src)); + return; + } + if (ty == Ity_V128) { + HReg src = iselNeonExpr(env, stmt->Ist.WrTmp.data); + HReg dst = lookupIRTemp(env, tmp); + addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, src, 4, True)); return; } - -// CAB: Ity_I1 ? - break; } /* --------- Call to DIRTY helper --------- */ /* call complex ("dirty") helper function */ case Ist_Dirty: { - //IRType retty; - IRDirty* d = stmt->Ist.Dirty.details; - Bool passBBP = False; + IRType retty; + IRDirty* d = stmt->Ist.Dirty.details; + Bool passBBP = False; if (d->nFxState == 0) vassert(!d->needsBBP); @@ -857,43 +5777,127 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) passBBP = toBool(d->nFxState > 0 && d->needsBBP); /* Marshal args, do the call, clear stack. */ - doHelperCall( env, passBBP, d->guard, d->cee, d->args ); + Bool ok = doHelperCall( env, passBBP, d->guard, d->cee, d->args ); + if (!ok) + break; /* will go to stmt_fail: */ /* Now figure out what to do with the returned value, if any. */ if (d->tmp == IRTemp_INVALID) - /* No return value. Nothing to do. */ - return; - - //retty = typeOfIRTemp(env->type_env, d->tmp); - -// CAB: ? if (retty == Ity_I64) { + /* No return value. Nothing to do. */ + return; -#if 0 + retty = typeOfIRTemp(env->type_env, d->tmp); + + if (retty == Ity_I64) { + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + HReg tmp = lookupIRTemp(env, d->tmp); + addInstr(env, ARMInstr_VXferD(True, tmp, hregARM_R1(), + hregARM_R0())); + } else { + HReg dstHi, dstLo; + /* The returned value is in r1:r0. Park it in the + register-pair associated with tmp. */ + lookupIRTemp64( &dstHi, &dstLo, env, d->tmp); + addInstr(env, mk_iMOVds_RR(dstHi, hregARM_R1()) ); + addInstr(env, mk_iMOVds_RR(dstLo, hregARM_R0()) ); + } + return; + } if (retty == Ity_I32 || retty == Ity_I16 || retty == Ity_I8) { - /* The returned value is in %eax. Park it in the register + /* The returned value is in r0. Park it in the register associated with tmp. */ HReg dst = lookupIRTemp(env, d->tmp); - addInstr(env, mk_iMOVsd_RR(hregX86_EAX(),dst) ); + addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()) ); return; } -#endif + + break; + } + + /* --------- Load Linked and Store Conditional --------- */ + case Ist_LLSC: { + if (stmt->Ist.LLSC.storedata == NULL) { + /* LL */ + IRTemp res = stmt->Ist.LLSC.result; + IRType ty = typeOfIRTemp(env->type_env, res); + if (ty == Ity_I32 || ty == Ity_I8) { + Int szB = 0; + HReg r_dst = lookupIRTemp(env, res); + HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr); + switch (ty) { + case Ity_I8: szB = 1; break; + case Ity_I32: szB = 4; break; + default: vassert(0); + } + addInstr(env, mk_iMOVds_RR(hregARM_R1(), raddr)); + addInstr(env, ARMInstr_LdrEX(szB)); + addInstr(env, mk_iMOVds_RR(r_dst, hregARM_R0())); + return; + } + /* else fall thru; is unhandled */ + } else { + /* SC */ + IRTemp res = stmt->Ist.LLSC.result; + IRType ty = typeOfIRTemp(env->type_env, res); + IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.storedata); + vassert(ty == Ity_I1); + if (tyd == Ity_I32 || tyd == Ity_I8) { + Int szB = 0; + HReg r_res = lookupIRTemp(env, res); + HReg rD = iselIntExpr_R(env, stmt->Ist.LLSC.storedata); + HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr); + ARMRI84* one = ARMRI84_I84(1,0); + switch (tyd) { + case Ity_I8: szB = 1; break; + case Ity_I32: szB = 4; break; + default: vassert(0); + } + addInstr(env, mk_iMOVds_RR(hregARM_R1(), rD)); + addInstr(env, mk_iMOVds_RR(hregARM_R2(), rA)); + addInstr(env, ARMInstr_StrEX(szB)); + /* now r0 is 1 if failed, 0 if success. Change to IR + conventions (0 is fail, 1 is success). Also transfer + result to r_res. */ + addInstr(env, ARMInstr_Alu(ARMalu_XOR, r_res, hregARM_R0(), one)); + /* And be conservative -- mask off all but the lowest bit */ + addInstr(env, ARMInstr_Alu(ARMalu_AND, r_res, r_res, one)); + return; + } + /* else fall thru; is unhandled */ + } break; } + /* --------- MEM FENCE --------- */ + case Ist_MBE: + switch (stmt->Ist.MBE.event) { + case Imbe_Fence: + addInstr(env,ARMInstr_MFence()); + return; + default: + break; + } + break; + + /* --------- INSTR MARK --------- */ + /* Doesn't generate any executable code ... */ + case Ist_IMark: + return; + + /* --------- NO-OP --------- */ + case Ist_NoOp: + return; + /* --------- EXIT --------- */ - /* conditional exit from BB */ case Ist_Exit: { - ARMBranchDest* dst; + HReg gnext; ARMCondCode cc; if (stmt->Ist.Exit.dst->tag != Ico_U32) vpanic("isel_arm: Ist_Exit: dst is not a 32-bit value"); - - // CAB: Where does jumpkind fit in ? - // stmt->Ist.Exit.jk - - dst = iselIntExpr_BD(env, IRExpr_Const(stmt->Ist.Exit.dst)); - cc = iselCondCode(env,stmt->Ist.Exit.guard); - addInstr(env, ARMInstr_Branch(cc, dst)); + gnext = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); + cc = iselCondCode(env, stmt->Ist.Exit.guard); + addInstr(env, mk_iMOVds_RR(hregARM_R14(), env->savedLR)); + addInstr(env, ARMInstr_Goto(stmt->Ist.Exit.jk, cc, gnext)); return; } @@ -911,19 +5915,17 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk ) { - ARMBranchDest* bd; - if (vex_traceflags & VEX_TRACE_VCODE) { - vex_printf("\n-- goto {"); - ppIRJumpKind(jk); - vex_printf("} "); - ppIRExpr(next); - vex_printf("\n"); - } - bd = iselIntExpr_BD(env, next); - - // CAB: jk ? - - addInstr( env, ARMInstr_Branch(ARMccAL, bd) ); + HReg rDst; + if (vex_traceflags & VEX_TRACE_VCODE) { + vex_printf("\n-- goto {"); + ppIRJumpKind(jk); + vex_printf("} "); + ppIRExpr(next); + vex_printf("\n"); + } + rDst = iselIntExpr_R(env, next); + addInstr(env, mk_iMOVds_RR(hregARM_R14(), env->savedLR)); + addInstr(env, ARMInstr_Goto(jk, ARMcc_AL, rDst)); } @@ -933,46 +5935,87 @@ static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk ) /* Translate an entire SB to arm code. */ -HInstrArray* iselSB_ARM ( IRSB* bb ) +HInstrArray* iselSB_ARM ( IRSB* bb, VexArch arch_host, + VexArchInfo* archinfo_host, + VexAbiInfo* vbi/*UNUSED*/ ) { - Int i, j; + Int i, j; + HReg hreg, hregHI; + ISelEnv* env; + UInt hwcaps_host = archinfo_host->hwcaps; + Bool neon = False; + static UInt counter = 0; - /* Make up an initial environment to use. */ - ISelEnv* env = LibVEX_Alloc(sizeof(ISelEnv)); - env->vreg_ctr = 0; + /* sanity ... */ + vassert(arch_host == VexArchARM); - /* Set up output code array. */ - env->code = newHInstrArray(); - - /* Copy BB's type env. */ - env->type_env = bb->tyenv; - - /* Make up an IRTemp -> virtual HReg mapping. This doesn't - change as we go along. */ - env->n_vregmap = bb->tyenv->types_used; - env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg)); - - /* For each IR temporary, allocate a 32bit virtual register. */ - j = 0; - for (i = 0; i < env->n_vregmap; i++) { - env->vregmap[i] = mkHReg(j++, HRcInt32, True); - } - env->vreg_ctr = j; - - /* Ok, finally we can iterate over the statements. */ - for (i = 0; i < bb->stmts_used; i++) - if (bb->stmts[i]) - iselStmt(env,bb->stmts[i]); + /* hwcaps should not change from one ISEL call to another. */ + arm_hwcaps = hwcaps_host; + + /* Make up an initial environment to use. */ + env = LibVEX_Alloc(sizeof(ISelEnv)); + env->vreg_ctr = 0; + + /* Set up output code array. */ + env->code = newHInstrArray(); - iselNext(env,bb->next,bb->jumpkind); + /* Copy BB's type env. */ + env->type_env = bb->tyenv; + + /* Make up an IRTemp -> virtual HReg mapping. This doesn't + change as we go along. */ + env->n_vregmap = bb->tyenv->types_used; + env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg)); + env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg)); + + /* For each IR temporary, allocate a suitably-kinded virtual + register. */ + j = 0; + for (i = 0; i < env->n_vregmap; i++) { + hregHI = hreg = INVALID_HREG; + switch (bb->tyenv->types[i]) { + case Ity_I1: + case Ity_I8: + case Ity_I16: + case Ity_I32: hreg = mkHReg(j++, HRcInt32, True); break; + case Ity_I64: + if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) { + hreg = mkHReg(j++, HRcFlt64, True); + neon = True; + } else { + hregHI = mkHReg(j++, HRcInt32, True); + hreg = mkHReg(j++, HRcInt32, True); + } + break; + case Ity_F32: hreg = mkHReg(j++, HRcFlt32, True); break; + case Ity_F64: hreg = mkHReg(j++, HRcFlt64, True); break; + case Ity_V128: hreg = mkHReg(j++, HRcVec128, True); + neon = True; break; + default: ppIRType(bb->tyenv->types[i]); + vpanic("iselBB: IRTemp type"); + } + env->vregmap[i] = hreg; + env->vregmapHI[i] = hregHI; + } + env->vreg_ctr = j; - /* record the number of vregs we used. */ - env->code->n_vregs = env->vreg_ctr; - return env->code; -} + /* Keep a copy of the link reg, since any call to a helper function + will trash it, and we can't get back to the dispatcher once that + happens. */ + env->savedLR = newVRegI(env); + addInstr(env, mk_iMOVds_RR(env->savedLR, hregARM_R14())); + /* Ok, finally we can iterate over the statements. */ + for (i = 0; i < bb->stmts_used; i++) + iselStmt(env,bb->stmts[i]); + iselNext(env,bb->next,bb->jumpkind); + /* record the number of vregs we used. */ + env->code->n_vregs = env->vreg_ctr; + counter++; + return env->code; +} /*---------------------------------------------------------------*/ diff --git a/VEX/priv/host_generic_reg_alloc2.c b/VEX/priv/host_generic_reg_alloc2.c index fc420aa..48303ff 100644 --- a/VEX/priv/host_generic_reg_alloc2.c +++ b/VEX/priv/host_generic_reg_alloc2.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_reg_alloc2.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_reg_alloc2.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -334,13 +323,15 @@ HInstrArray* doRegisterAllocation ( /* Apply a reg-reg mapping to an insn. */ void (*mapRegs) ( HRegRemap*, HInstr*, Bool ), - /* Return an insn to spill/restore a real reg to a spill slot byte - offset. Also (optionally) a 'directReload' function, which + /* Return one, or, if we're unlucky, two insn(s) to spill/restore a + real reg to a spill slot byte offset. The two leading HInstr** + args are out parameters, through which the generated insns are + returned. Also (optionally) a 'directReload' function, which attempts to replace a given instruction by one which reads directly from a specified spill slot. May be NULL, in which case the optimisation is not attempted. */ - HInstr* (*genSpill) ( HReg, Int, Bool ), - HInstr* (*genReload) ( HReg, Int, Bool ), + void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ), + void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ), HInstr* (*directReload) ( HInstr*, HReg, Short ), Int guest_sizeB, @@ -830,7 +821,7 @@ HInstrArray* doRegisterAllocation ( } /* The spill slots are 64 bits in size. As per the comment on - definition of HRegClass in h_generic_regs.h, that means, to + definition of HRegClass in host_generic_regs.h, that means, to spill a vreg of class Flt64 or Vec128, we'll need to find two adjacent spill slots to use. Note, this logic needs to kept in sync with the size info on the definition of HRegClass. */ @@ -1157,9 +1148,15 @@ HInstrArray* doRegisterAllocation ( if (vreg_lrs[m].dead_before > ii) { vassert(vreg_lrs[m].reg_class != HRcINVALID); if ((!eq_spill_opt) || !rreg_state[k].eq_spill_slot) { - EMIT_INSTR( (*genSpill)( rreg_state[k].rreg, - vreg_lrs[m].spill_offset, - mode64 ) ); + HInstr* spill1 = NULL; + HInstr* spill2 = NULL; + (*genSpill)( &spill1, &spill2, rreg_state[k].rreg, + vreg_lrs[m].spill_offset, mode64 ); + vassert(spill1 || spill2); /* can't both be NULL */ + if (spill1) + EMIT_INSTR(spill1); + if (spill2) + EMIT_INSTR(spill2); } rreg_state[k].eq_spill_slot = True; } @@ -1199,7 +1196,7 @@ HInstrArray* doRegisterAllocation ( in a spill slot, and this is last use of that vreg, see if we can convert the instruction into one reads directly from the spill slot. This is clearly only possible for x86 and amd64 - targets, since ppc is a load-store architecture. If + targets, since ppc and arm load-store architectures. If successful, replace instrs_in->arr[ii] with this new instruction, and recompute its reg usage, so that the change is invisible to the standard-case handling that follows. */ @@ -1332,9 +1329,15 @@ HInstrArray* doRegisterAllocation ( indeed needed. */ if (reg_usage.mode[j] != HRmWrite) { vassert(vreg_lrs[m].reg_class != HRcINVALID); - EMIT_INSTR( (*genReload)( rreg_state[k].rreg, - vreg_lrs[m].spill_offset, - mode64 ) ); + HInstr* reload1 = NULL; + HInstr* reload2 = NULL; + (*genReload)( &reload1, &reload2, rreg_state[k].rreg, + vreg_lrs[m].spill_offset, mode64 ); + vassert(reload1 || reload2); /* can't both be NULL */ + if (reload1) + EMIT_INSTR(reload1); + if (reload2) + EMIT_INSTR(reload2); /* This rreg is read or modified by the instruction. If it's merely read we can claim it now equals the spill slot, but not so if it is modified. */ @@ -1409,9 +1412,15 @@ HInstrArray* doRegisterAllocation ( vassert(vreg_lrs[m].dead_before > ii); vassert(vreg_lrs[m].reg_class != HRcINVALID); if ((!eq_spill_opt) || !rreg_state[spillee].eq_spill_slot) { - EMIT_INSTR( (*genSpill)( rreg_state[spillee].rreg, - vreg_lrs[m].spill_offset, - mode64 ) ); + HInstr* spill1 = NULL; + HInstr* spill2 = NULL; + (*genSpill)( &spill1, &spill2, rreg_state[spillee].rreg, + vreg_lrs[m].spill_offset, mode64 ); + vassert(spill1 || spill2); /* can't both be NULL */ + if (spill1) + EMIT_INSTR(spill1); + if (spill2) + EMIT_INSTR(spill2); } /* Update the rreg_state to reflect the new assignment for this @@ -1429,9 +1438,15 @@ HInstrArray* doRegisterAllocation ( written), we have to generate a reload for it. */ if (reg_usage.mode[j] != HRmWrite) { vassert(vreg_lrs[m].reg_class != HRcINVALID); - EMIT_INSTR( (*genReload)( rreg_state[spillee].rreg, - vreg_lrs[m].spill_offset, - mode64 ) ); + HInstr* reload1 = NULL; + HInstr* reload2 = NULL; + (*genReload)( &reload1, &reload2, rreg_state[spillee].rreg, + vreg_lrs[m].spill_offset, mode64 ); + vassert(reload1 || reload2); /* can't both be NULL */ + if (reload1) + EMIT_INSTR(reload1); + if (reload2) + EMIT_INSTR(reload2); /* This rreg is read or modified by the instruction. If it's merely read we can claim it now equals the spill slot, but not so if it is modified. */ diff --git a/VEX/priv/host_generic_regs.c b/VEX/priv/host_generic_regs.c index f38746b..e36b4dc 100644 --- a/VEX/priv/host_generic_regs.c +++ b/VEX/priv/host_generic_regs.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_generic_regs.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_generic_regs.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -56,6 +45,7 @@ void ppHRegClass ( HRegClass hrc ) switch (hrc) { case HRcInt32: vex_printf("HRcInt32"); break; case HRcInt64: vex_printf("HRcInt64"); break; + case HRcFlt32: vex_printf("HRcFlt32"); break; case HRcFlt64: vex_printf("HRcFlt64"); break; case HRcVec64: vex_printf("HRcVec64"); break; case HRcVec128: vex_printf("HRcVec128"); break; @@ -71,7 +61,8 @@ void ppHReg ( HReg r ) switch (hregClass(r)) { case HRcInt32: vex_printf("%%%sr%d", maybe_v, regNo); return; case HRcInt64: vex_printf("%%%sR%d", maybe_v, regNo); return; - case HRcFlt64: vex_printf("%%%sF%d", maybe_v, regNo); return; + case HRcFlt32: vex_printf("%%%sF%d", maybe_v, regNo); return; + case HRcFlt64: vex_printf("%%%sD%d", maybe_v, regNo); return; case HRcVec64: vex_printf("%%%sv%d", maybe_v, regNo); return; case HRcVec128: vex_printf("%%%sV%d", maybe_v, regNo); return; default: vpanic("ppHReg"); diff --git a/VEX/priv/host_generic_regs.h b/VEX/priv/host_generic_regs.h index 845f7f0..1c6826c 100644 --- a/VEX/priv/host_generic_regs.h +++ b/VEX/priv/host_generic_regs.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_generic_regs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_generic_regs.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -74,9 +63,9 @@ Note further that since the class field is never 1111b, no valid register can have the value INVALID_HREG. - There are currently 5 register classes: + There are currently 6 register classes: - int32 int64 float64 simd64 simd128 + int32 int64 float32 float64 simd64 simd128 */ typedef UInt HReg; @@ -87,23 +76,27 @@ typedef UInt HReg; available on any specific host. For example on x86, the available classes are: Int32, Flt64, Vec128 only. - IMPORTANT NOTE: reg_alloc2.c needs how much space is needed to spill - each class of register. It has the following knowledge hardwired in: + IMPORTANT NOTE: host_generic_reg_alloc2.c needs how much space is + needed to spill each class of register. It allocates the following + amount of space: - HRcInt32 32 bits + HRcInt32 64 bits HRcInt64 64 bits - HRcFlt64 80 bits (on x86 these are spilled by fstpt/fldt) + HRcFlt32 64 bits + HRcFlt64 128 bits (on x86 these are spilled by fstpt/fldt and + so won't fit in a 64-bit slot) HRcVec64 64 bits HRcVec128 128 bits If you add another regclass, you must remember to update - reg_alloc2.c accordingly. + host_generic_reg_alloc2.c accordingly. */ typedef enum { HRcINVALID=1, /* NOT A VALID REGISTER CLASS */ - HRcInt32=4, /* 32-bit int */ - HRcInt64=5, /* 64-bit int */ + HRcInt32=3, /* 32-bit int */ + HRcInt64=4, /* 64-bit int */ + HRcFlt32=5, /* 32-bit float */ HRcFlt64=6, /* 64-bit float */ HRcVec64=7, /* 64-bit SIMD */ HRcVec128=8 /* 128-bit SIMD */ @@ -265,10 +258,10 @@ HInstrArray* doRegisterAllocation ( /* Apply a reg-reg mapping to an insn. */ void (*mapRegs) (HRegRemap*, HInstr*, Bool), - /* Return an insn to spill/restore a real reg to a spill slot + /* Return insn(s) to spill/restore a real reg to a spill slot offset. And optionally a function to do direct reloads. */ - HInstr* (*genSpill) ( HReg, Int, Bool ), - HInstr* (*genReload) ( HReg, Int, Bool ), + void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ), + void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ), HInstr* (*directReload) ( HInstr*, HReg, Short ), Int guest_sizeB, diff --git a/VEX/priv/host_generic_simd128.c b/VEX/priv/host_generic_simd128.c new file mode 100644 index 0000000..8ed5166 --- /dev/null +++ b/VEX/priv/host_generic_simd128.c @@ -0,0 +1,220 @@ + +/*---------------------------------------------------------------*/ +/*--- begin host_generic_simd128.c ---*/ +/*---------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2010-2010 OpenWorks GbR + info@open-works.net + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +/* Generic helper functions for doing 128-bit SIMD arithmetic in cases + where the instruction selectors cannot generate code in-line. + These are purely back-end entities and cannot be seen/referenced + from IR. */ + +#include "libvex_basictypes.h" +#include "host_generic_simd128.h" + + +/* Primitive helpers always take args of the real type (signed vs + unsigned) but return an unsigned result, so there's no conversion + weirdness when stuffing results back in the V128 union fields, + which are all unsigned. */ + +static inline UInt mul32 ( Int xx, Int yy ) +{ + Int t = ((Int)xx) * ((Int)yy); + return toUInt(t); +} + +static inline UInt max32S ( Int xx, Int yy ) +{ + return toUInt((xx > yy) ? xx : yy); +} + +static inline UInt min32S ( Int xx, Int yy ) +{ + return toUInt((xx < yy) ? xx : yy); +} + +static inline UInt max32U ( UInt xx, UInt yy ) +{ + return toUInt((xx > yy) ? xx : yy); +} + +static inline UInt min32U ( UInt xx, UInt yy ) +{ + return toUInt((xx < yy) ? xx : yy); +} + +static inline UShort max16U ( UShort xx, UShort yy ) +{ + return toUShort((xx > yy) ? xx : yy); +} + +static inline UShort min16U ( UShort xx, UShort yy ) +{ + return toUShort((xx < yy) ? xx : yy); +} + +static inline UChar max8S ( Char xx, Char yy ) +{ + return toUChar((xx > yy) ? xx : yy); +} + +static inline UChar min8S ( Char xx, Char yy ) +{ + return toUChar((xx < yy) ? xx : yy); +} + +static inline ULong cmpGT64S ( Long xx, Long yy ) +{ + return (((Long)xx) > ((Long)yy)) + ? 0xFFFFFFFFFFFFFFFFULL : 0ULL; +} + +void h_generic_calc_Mul32x4 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w32[0] = mul32(argL->w32[0], argR->w32[0]); + res->w32[1] = mul32(argL->w32[1], argR->w32[1]); + res->w32[2] = mul32(argL->w32[2], argR->w32[2]); + res->w32[3] = mul32(argL->w32[3], argR->w32[3]); +} + +void h_generic_calc_Max32Sx4 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w32[0] = max32S(argL->w32[0], argR->w32[0]); + res->w32[1] = max32S(argL->w32[1], argR->w32[1]); + res->w32[2] = max32S(argL->w32[2], argR->w32[2]); + res->w32[3] = max32S(argL->w32[3], argR->w32[3]); +} + +void h_generic_calc_Min32Sx4 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w32[0] = min32S(argL->w32[0], argR->w32[0]); + res->w32[1] = min32S(argL->w32[1], argR->w32[1]); + res->w32[2] = min32S(argL->w32[2], argR->w32[2]); + res->w32[3] = min32S(argL->w32[3], argR->w32[3]); +} + +void h_generic_calc_Max32Ux4 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w32[0] = max32U(argL->w32[0], argR->w32[0]); + res->w32[1] = max32U(argL->w32[1], argR->w32[1]); + res->w32[2] = max32U(argL->w32[2], argR->w32[2]); + res->w32[3] = max32U(argL->w32[3], argR->w32[3]); +} + +void h_generic_calc_Min32Ux4 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w32[0] = min32U(argL->w32[0], argR->w32[0]); + res->w32[1] = min32U(argL->w32[1], argR->w32[1]); + res->w32[2] = min32U(argL->w32[2], argR->w32[2]); + res->w32[3] = min32U(argL->w32[3], argR->w32[3]); +} + +void h_generic_calc_Max16Ux8 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w16[0] = max16U(argL->w16[0], argR->w16[0]); + res->w16[1] = max16U(argL->w16[1], argR->w16[1]); + res->w16[2] = max16U(argL->w16[2], argR->w16[2]); + res->w16[3] = max16U(argL->w16[3], argR->w16[3]); + res->w16[4] = max16U(argL->w16[4], argR->w16[4]); + res->w16[5] = max16U(argL->w16[5], argR->w16[5]); + res->w16[6] = max16U(argL->w16[6], argR->w16[6]); + res->w16[7] = max16U(argL->w16[7], argR->w16[7]); +} + +void h_generic_calc_Min16Ux8 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w16[0] = min16U(argL->w16[0], argR->w16[0]); + res->w16[1] = min16U(argL->w16[1], argR->w16[1]); + res->w16[2] = min16U(argL->w16[2], argR->w16[2]); + res->w16[3] = min16U(argL->w16[3], argR->w16[3]); + res->w16[4] = min16U(argL->w16[4], argR->w16[4]); + res->w16[5] = min16U(argL->w16[5], argR->w16[5]); + res->w16[6] = min16U(argL->w16[6], argR->w16[6]); + res->w16[7] = min16U(argL->w16[7], argR->w16[7]); +} + +void h_generic_calc_Max8Sx16 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w8[ 0] = max8S(argL->w8[ 0], argR->w8[ 0]); + res->w8[ 1] = max8S(argL->w8[ 1], argR->w8[ 1]); + res->w8[ 2] = max8S(argL->w8[ 2], argR->w8[ 2]); + res->w8[ 3] = max8S(argL->w8[ 3], argR->w8[ 3]); + res->w8[ 4] = max8S(argL->w8[ 4], argR->w8[ 4]); + res->w8[ 5] = max8S(argL->w8[ 5], argR->w8[ 5]); + res->w8[ 6] = max8S(argL->w8[ 6], argR->w8[ 6]); + res->w8[ 7] = max8S(argL->w8[ 7], argR->w8[ 7]); + res->w8[ 8] = max8S(argL->w8[ 8], argR->w8[ 8]); + res->w8[ 9] = max8S(argL->w8[ 9], argR->w8[ 9]); + res->w8[10] = max8S(argL->w8[10], argR->w8[10]); + res->w8[11] = max8S(argL->w8[11], argR->w8[11]); + res->w8[12] = max8S(argL->w8[12], argR->w8[12]); + res->w8[13] = max8S(argL->w8[13], argR->w8[13]); + res->w8[14] = max8S(argL->w8[14], argR->w8[14]); + res->w8[15] = max8S(argL->w8[15], argR->w8[15]); +} + +void h_generic_calc_Min8Sx16 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w8[ 0] = min8S(argL->w8[ 0], argR->w8[ 0]); + res->w8[ 1] = min8S(argL->w8[ 1], argR->w8[ 1]); + res->w8[ 2] = min8S(argL->w8[ 2], argR->w8[ 2]); + res->w8[ 3] = min8S(argL->w8[ 3], argR->w8[ 3]); + res->w8[ 4] = min8S(argL->w8[ 4], argR->w8[ 4]); + res->w8[ 5] = min8S(argL->w8[ 5], argR->w8[ 5]); + res->w8[ 6] = min8S(argL->w8[ 6], argR->w8[ 6]); + res->w8[ 7] = min8S(argL->w8[ 7], argR->w8[ 7]); + res->w8[ 8] = min8S(argL->w8[ 8], argR->w8[ 8]); + res->w8[ 9] = min8S(argL->w8[ 9], argR->w8[ 9]); + res->w8[10] = min8S(argL->w8[10], argR->w8[10]); + res->w8[11] = min8S(argL->w8[11], argR->w8[11]); + res->w8[12] = min8S(argL->w8[12], argR->w8[12]); + res->w8[13] = min8S(argL->w8[13], argR->w8[13]); + res->w8[14] = min8S(argL->w8[14], argR->w8[14]); + res->w8[15] = min8S(argL->w8[15], argR->w8[15]); +} + +void h_generic_calc_CmpGT64Sx2 ( /*OUT*/V128* res, + V128* argL, V128* argR ) +{ + res->w64[0] = cmpGT64S(argL->w64[0], argR->w64[0]); + res->w64[1] = cmpGT64S(argL->w64[1], argR->w64[1]); +} + + +/*---------------------------------------------------------------*/ +/*--- end host_generic_simd128.c ---*/ +/*---------------------------------------------------------------*/ diff --git a/VEX/priv/host_generic_simd128.h b/VEX/priv/host_generic_simd128.h new file mode 100644 index 0000000..53850cb --- /dev/null +++ b/VEX/priv/host_generic_simd128.h @@ -0,0 +1,67 @@ + +/*---------------------------------------------------------------*/ +/*--- begin host_generic_simd128.h ---*/ +/*---------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2010-2010 OpenWorks GbR + info@open-works.net + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +/* Generic helper functions for doing 128-bit SIMD arithmetic in cases + where the instruction selectors cannot generate code in-line. + These are purely back-end entities and cannot be seen/referenced + as clean helper functions from IR. + + These will get called from generated code and therefore should be + well behaved -- no floating point or mmx insns, just straight + integer code. + + Each function implements the correspondingly-named IR primop. +*/ + +#ifndef __VEX_HOST_GENERIC_SIMD128_H +#define __VEX_HOST_GENERIC_SIMD128_H + +#include "libvex_basictypes.h" + +/* DO NOT MAKE THESE INTO REGPARM FNS! THIS WILL BREAK CALLING + SEQUENCES GENERATED BY host-x86/isel.c. */ + +extern void h_generic_calc_Mul32x4 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_Max32Sx4 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_Min32Sx4 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_Max32Ux4 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_Min32Ux4 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_Max16Ux8 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_Min16Ux8 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_Max8Sx16 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_Min8Sx16 ( /*OUT*/V128*, V128*, V128* ); +extern void h_generic_calc_CmpGT64Sx2 ( /*OUT*/V128*, V128*, V128* ); + + +#endif /* ndef __VEX_HOST_GENERIC_SIMD128_H */ + +/*---------------------------------------------------------------*/ +/*--- end host_generic_simd128.h ---*/ +/*---------------------------------------------------------------*/ diff --git a/VEX/priv/host_generic_simd64.c b/VEX/priv/host_generic_simd64.c index 506c142..03d6d2f 100644 --- a/VEX/priv/host_generic_simd64.c +++ b/VEX/priv/host_generic_simd64.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_generic_simd64.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_generic_simd64.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -101,7 +90,7 @@ static inline UShort sel16x4_0 ( ULong w64 ) { static inline ULong mk8x8 ( UChar w7, UChar w6, UChar w5, UChar w4, UChar w3, UChar w2, - UChar w1, UChar w0 ) { + UChar w1, UChar w0 ) { UInt hi32 = (((UInt)w7) << 24) | (((UInt)w6) << 16) | (((UInt)w5) << 8) | (((UInt)w4) << 0); UInt lo32 = (((UInt)w3) << 24) | (((UInt)w2) << 16) @@ -386,6 +375,77 @@ static inline UChar min8U ( UChar xx, UChar yy ) return toUChar((xx < yy) ? xx : yy); } +static inline UShort hadd16U ( UShort xx, UShort yy ) +{ + UInt xxi = (UInt)xx; + UInt yyi = (UInt)yy; + UInt r = (xxi + yyi) >> 1; + return (UShort)r; +} + +static inline Short hadd16S ( Short xx, Short yy ) +{ + Int xxi = (Int)xx; + Int yyi = (Int)yy; + Int r = (xxi + yyi) >> 1; + return (Short)r; +} + +static inline UShort hsub16U ( UShort xx, UShort yy ) +{ + UInt xxi = (UInt)xx; + UInt yyi = (UInt)yy; + UInt r = (xxi - yyi) >> 1; + return (UShort)r; +} + +static inline Short hsub16S ( Short xx, Short yy ) +{ + Int xxi = (Int)xx; + Int yyi = (Int)yy; + Int r = (xxi - yyi) >> 1; + return (Short)r; +} + +static inline UChar hadd8U ( UChar xx, UChar yy ) +{ + UInt xxi = (UInt)xx; + UInt yyi = (UInt)yy; + UInt r = (xxi + yyi) >> 1; + return (UChar)r; +} + +static inline Char hadd8S ( Char xx, Char yy ) +{ + Int xxi = (Int)xx; + Int yyi = (Int)yy; + Int r = (xxi + yyi) >> 1; + return (Char)r; +} + +static inline UChar hsub8U ( UChar xx, UChar yy ) +{ + UInt xxi = (UInt)xx; + UInt yyi = (UInt)yy; + UInt r = (xxi - yyi) >> 1; + return (UChar)r; +} + +static inline Char hsub8S ( Char xx, Char yy ) +{ + Int xxi = (Int)xx; + Int yyi = (Int)yy; + Int r = (xxi - yyi) >> 1; + return (Char)r; +} + +static inline UInt absdiff8U ( UChar xx, UChar yy ) +{ + UInt xxu = (UChar)xx; + UInt yyu = (UChar)yy; + return xxu >= yyu ? xxu - yyu : yyu - xxu; +} + /* ----------------------------------------------------- */ /* Start of the externally visible functions. These simply implement the corresponding IR primops. */ @@ -1041,6 +1101,236 @@ ULong h_generic_calc_Min8Ux8 ( ULong xx, ULong yy ) ); } +/* ------------ SOME 32-bit SIMD HELPERS TOO ------------ */ + +/* Tuple/select functions for 16x2 vectors. */ +static inline UInt mk16x2 ( UShort w1, UShort w2 ) { + return (((UInt)w1) << 16) | ((UInt)w2); +} + +static inline UShort sel16x2_1 ( UInt w32 ) { + return 0xFFFF & (UShort)(w32 >> 16); +} +static inline UShort sel16x2_0 ( UInt w32 ) { + return 0xFFFF & (UShort)(w32); +} + +static inline UInt mk8x4 ( UChar w3, UChar w2, + UChar w1, UChar w0 ) { + UInt w32 = (((UInt)w3) << 24) | (((UInt)w2) << 16) + | (((UInt)w1) << 8) | (((UInt)w0) << 0); + return w32; +} + +static inline UChar sel8x4_3 ( UInt w32 ) { + return toUChar(0xFF & (w32 >> 24)); +} +static inline UChar sel8x4_2 ( UInt w32 ) { + return toUChar(0xFF & (w32 >> 16)); +} +static inline UChar sel8x4_1 ( UInt w32 ) { + return toUChar(0xFF & (w32 >> 8)); +} +static inline UChar sel8x4_0 ( UInt w32 ) { + return toUChar(0xFF & (w32 >> 0)); +} + + +/* ----------------------------------------------------- */ +/* More externally visible functions. These simply + implement the corresponding IR primops. */ +/* ----------------------------------------------------- */ + +/* ------ 16x2 ------ */ + +UInt h_generic_calc_Add16x2 ( UInt xx, UInt yy ) +{ + return mk16x2( sel16x2_1(xx) + sel16x2_1(yy), + sel16x2_0(xx) + sel16x2_0(yy) ); +} + +UInt h_generic_calc_Sub16x2 ( UInt xx, UInt yy ) +{ + return mk16x2( sel16x2_1(xx) - sel16x2_1(yy), + sel16x2_0(xx) - sel16x2_0(yy) ); +} + +UInt h_generic_calc_HAdd16Ux2 ( UInt xx, UInt yy ) +{ + return mk16x2( hadd16U( sel16x2_1(xx), sel16x2_1(yy) ), + hadd16U( sel16x2_0(xx), sel16x2_0(yy) ) ); +} + +UInt h_generic_calc_HAdd16Sx2 ( UInt xx, UInt yy ) +{ + return mk16x2( hadd16S( sel16x2_1(xx), sel16x2_1(yy) ), + hadd16S( sel16x2_0(xx), sel16x2_0(yy) ) ); +} + +UInt h_generic_calc_HSub16Ux2 ( UInt xx, UInt yy ) +{ + return mk16x2( hsub16U( sel16x2_1(xx), sel16x2_1(yy) ), + hsub16U( sel16x2_0(xx), sel16x2_0(yy) ) ); +} + +UInt h_generic_calc_HSub16Sx2 ( UInt xx, UInt yy ) +{ + return mk16x2( hsub16S( sel16x2_1(xx), sel16x2_1(yy) ), + hsub16S( sel16x2_0(xx), sel16x2_0(yy) ) ); +} + +UInt h_generic_calc_QAdd16Ux2 ( UInt xx, UInt yy ) +{ + return mk16x2( qadd16U( sel16x2_1(xx), sel16x2_1(yy) ), + qadd16U( sel16x2_0(xx), sel16x2_0(yy) ) ); +} + +UInt h_generic_calc_QAdd16Sx2 ( UInt xx, UInt yy ) +{ + return mk16x2( qadd16S( sel16x2_1(xx), sel16x2_1(yy) ), + qadd16S( sel16x2_0(xx), sel16x2_0(yy) ) ); +} + +UInt h_generic_calc_QSub16Ux2 ( UInt xx, UInt yy ) +{ + return mk16x2( qsub16U( sel16x2_1(xx), sel16x2_1(yy) ), + qsub16U( sel16x2_0(xx), sel16x2_0(yy) ) ); +} + +UInt h_generic_calc_QSub16Sx2 ( UInt xx, UInt yy ) +{ + return mk16x2( qsub16S( sel16x2_1(xx), sel16x2_1(yy) ), + qsub16S( sel16x2_0(xx), sel16x2_0(yy) ) ); +} + +/* ------ 8x4 ------ */ + +UInt h_generic_calc_Add8x4 ( UInt xx, UInt yy ) +{ + return mk8x4( + sel8x4_3(xx) + sel8x4_3(yy), + sel8x4_2(xx) + sel8x4_2(yy), + sel8x4_1(xx) + sel8x4_1(yy), + sel8x4_0(xx) + sel8x4_0(yy) + ); +} + +UInt h_generic_calc_Sub8x4 ( UInt xx, UInt yy ) +{ + return mk8x4( + sel8x4_3(xx) - sel8x4_3(yy), + sel8x4_2(xx) - sel8x4_2(yy), + sel8x4_1(xx) - sel8x4_1(yy), + sel8x4_0(xx) - sel8x4_0(yy) + ); +} + +UInt h_generic_calc_HAdd8Ux4 ( UInt xx, UInt yy ) +{ + return mk8x4( + hadd8U( sel8x4_3(xx), sel8x4_3(yy) ), + hadd8U( sel8x4_2(xx), sel8x4_2(yy) ), + hadd8U( sel8x4_1(xx), sel8x4_1(yy) ), + hadd8U( sel8x4_0(xx), sel8x4_0(yy) ) + ); +} + +UInt h_generic_calc_HAdd8Sx4 ( UInt xx, UInt yy ) +{ + return mk8x4( + hadd8S( sel8x4_3(xx), sel8x4_3(yy) ), + hadd8S( sel8x4_2(xx), sel8x4_2(yy) ), + hadd8S( sel8x4_1(xx), sel8x4_1(yy) ), + hadd8S( sel8x4_0(xx), sel8x4_0(yy) ) + ); +} + +UInt h_generic_calc_HSub8Ux4 ( UInt xx, UInt yy ) +{ + return mk8x4( + hsub8U( sel8x4_3(xx), sel8x4_3(yy) ), + hsub8U( sel8x4_2(xx), sel8x4_2(yy) ), + hsub8U( sel8x4_1(xx), sel8x4_1(yy) ), + hsub8U( sel8x4_0(xx), sel8x4_0(yy) ) + ); +} + +UInt h_generic_calc_HSub8Sx4 ( UInt xx, UInt yy ) +{ + return mk8x4( + hsub8S( sel8x4_3(xx), sel8x4_3(yy) ), + hsub8S( sel8x4_2(xx), sel8x4_2(yy) ), + hsub8S( sel8x4_1(xx), sel8x4_1(yy) ), + hsub8S( sel8x4_0(xx), sel8x4_0(yy) ) + ); +} + +UInt h_generic_calc_QAdd8Ux4 ( UInt xx, UInt yy ) +{ + return mk8x4( + qadd8U( sel8x4_3(xx), sel8x4_3(yy) ), + qadd8U( sel8x4_2(xx), sel8x4_2(yy) ), + qadd8U( sel8x4_1(xx), sel8x4_1(yy) ), + qadd8U( sel8x4_0(xx), sel8x4_0(yy) ) + ); +} + +UInt h_generic_calc_QAdd8Sx4 ( UInt xx, UInt yy ) +{ + return mk8x4( + qadd8S( sel8x4_3(xx), sel8x4_3(yy) ), + qadd8S( sel8x4_2(xx), sel8x4_2(yy) ), + qadd8S( sel8x4_1(xx), sel8x4_1(yy) ), + qadd8S( sel8x4_0(xx), sel8x4_0(yy) ) + ); +} + +UInt h_generic_calc_QSub8Ux4 ( UInt xx, UInt yy ) +{ + return mk8x4( + qsub8U( sel8x4_3(xx), sel8x4_3(yy) ), + qsub8U( sel8x4_2(xx), sel8x4_2(yy) ), + qsub8U( sel8x4_1(xx), sel8x4_1(yy) ), + qsub8U( sel8x4_0(xx), sel8x4_0(yy) ) + ); +} + +UInt h_generic_calc_QSub8Sx4 ( UInt xx, UInt yy ) +{ + return mk8x4( + qsub8S( sel8x4_3(xx), sel8x4_3(yy) ), + qsub8S( sel8x4_2(xx), sel8x4_2(yy) ), + qsub8S( sel8x4_1(xx), sel8x4_1(yy) ), + qsub8S( sel8x4_0(xx), sel8x4_0(yy) ) + ); +} + +UInt h_generic_calc_CmpNEZ16x2 ( UInt xx ) +{ + return mk16x2( + cmpnez16( sel16x2_1(xx) ), + cmpnez16( sel16x2_0(xx) ) + ); +} + +UInt h_generic_calc_CmpNEZ8x4 ( UInt xx ) +{ + return mk8x4( + cmpnez8( sel8x4_3(xx) ), + cmpnez8( sel8x4_2(xx) ), + cmpnez8( sel8x4_1(xx) ), + cmpnez8( sel8x4_0(xx) ) + ); +} + +UInt h_generic_calc_Sad8Ux4 ( UInt xx, UInt yy ) +{ + return absdiff8U( sel8x4_3(xx), sel8x4_3(yy) ) + + absdiff8U( sel8x4_2(xx), sel8x4_2(yy) ) + + absdiff8U( sel8x4_1(xx), sel8x4_1(yy) ) + + absdiff8U( sel8x4_0(xx), sel8x4_0(yy) ); +} + /*---------------------------------------------------------------*/ /*--- end host_generic_simd64.c ---*/ diff --git a/VEX/priv/host_generic_simd64.h b/VEX/priv/host_generic_simd64.h index 7c1ce61..e854fc7 100644 --- a/VEX/priv/host_generic_simd64.h +++ b/VEX/priv/host_generic_simd64.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_generic_simd64.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_generic_simd64.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -132,6 +121,38 @@ extern ULong h_generic_calc_Max8Ux8 ( ULong, ULong ); extern ULong h_generic_calc_Min16Sx4 ( ULong, ULong ); extern ULong h_generic_calc_Min8Ux8 ( ULong, ULong ); +/* 32-bit SIMD HELPERS */ + +extern UInt h_generic_calc_Add16x2 ( UInt, UInt ); +extern UInt h_generic_calc_Sub16x2 ( UInt, UInt ); + +extern UInt h_generic_calc_HAdd16Ux2 ( UInt, UInt ); +extern UInt h_generic_calc_HAdd16Sx2 ( UInt, UInt ); +extern UInt h_generic_calc_HSub16Ux2 ( UInt, UInt ); +extern UInt h_generic_calc_HSub16Sx2 ( UInt, UInt ); + +extern UInt h_generic_calc_QAdd16Ux2 ( UInt, UInt ); +extern UInt h_generic_calc_QAdd16Sx2 ( UInt, UInt ); +extern UInt h_generic_calc_QSub16Ux2 ( UInt, UInt ); +extern UInt h_generic_calc_QSub16Sx2 ( UInt, UInt ); + +extern UInt h_generic_calc_Add8x4 ( UInt, UInt ); +extern UInt h_generic_calc_Sub8x4 ( UInt, UInt ); + +extern UInt h_generic_calc_HAdd8Ux4 ( UInt, UInt ); +extern UInt h_generic_calc_HAdd8Sx4 ( UInt, UInt ); +extern UInt h_generic_calc_HSub8Ux4 ( UInt, UInt ); +extern UInt h_generic_calc_HSub8Sx4 ( UInt, UInt ); + +extern UInt h_generic_calc_QAdd8Ux4 ( UInt, UInt ); +extern UInt h_generic_calc_QAdd8Sx4 ( UInt, UInt ); +extern UInt h_generic_calc_QSub8Ux4 ( UInt, UInt ); +extern UInt h_generic_calc_QSub8Sx4 ( UInt, UInt ); + +extern UInt h_generic_calc_Sad8Ux4 ( UInt, UInt ); + +extern UInt h_generic_calc_CmpNEZ16x2 ( UInt ); +extern UInt h_generic_calc_CmpNEZ8x4 ( UInt ); #endif /* ndef __VEX_HOST_GENERIC_SIMD64_H */ diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c index 1b8d103..54fd2fd 100644 --- a/VEX/priv/host_ppc_defs.c +++ b/VEX/priv/host_ppc_defs.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_ppc_defs.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_ppc_defs.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -2148,51 +2137,63 @@ Bool isMove_PPCInstr ( PPCInstr* i, HReg* src, HReg* dst ) /* Generate ppc spill/reload instructions under the direction of the register allocator. Note it's critical these don't write the condition codes. */ -PPCInstr* genSpill_PPC ( HReg rreg, UShort offsetB, Bool mode64 ) + +void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) { PPCAMode* am; vassert(!hregIsVirtual(rreg)); + *i1 = *i2 = NULL; am = PPCAMode_IR( offsetB, GuestStatePtr(mode64) ); - switch (hregClass(rreg)) { - case HRcInt64: - vassert(mode64); - return PPCInstr_Store( 8, am, rreg, mode64 ); - case HRcInt32: - vassert(!mode64); - return PPCInstr_Store( 4, am, rreg, mode64 ); - case HRcFlt64: - return PPCInstr_FpLdSt ( False/*store*/, 8, rreg, am ); - case HRcVec128: - // XXX: GPR30 used as spill register to kludge AltiVec AMode_IR - return PPCInstr_AvLdSt ( False/*store*/, 16, rreg, am ); - default: - ppHRegClass(hregClass(rreg)); - vpanic("genSpill_PPC: unimplemented regclass"); + case HRcInt64: + vassert(mode64); + *i1 = PPCInstr_Store( 8, am, rreg, mode64 ); + return; + case HRcInt32: + vassert(!mode64); + *i1 = PPCInstr_Store( 4, am, rreg, mode64 ); + return; + case HRcFlt64: + *i1 = PPCInstr_FpLdSt ( False/*store*/, 8, rreg, am ); + return; + case HRcVec128: + // XXX: GPR30 used as spill register to kludge AltiVec + // AMode_IR + *i1 = PPCInstr_AvLdSt ( False/*store*/, 16, rreg, am ); + return; + default: + ppHRegClass(hregClass(rreg)); + vpanic("genSpill_PPC: unimplemented regclass"); } } -PPCInstr* genReload_PPC ( HReg rreg, UShort offsetB, Bool mode64 ) +void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) { PPCAMode* am; vassert(!hregIsVirtual(rreg)); + *i1 = *i2 = NULL; am = PPCAMode_IR( offsetB, GuestStatePtr(mode64) ); - switch (hregClass(rreg)) { - case HRcInt64: - vassert(mode64); - return PPCInstr_Load( 8, rreg, am, mode64 ); - case HRcInt32: - vassert(!mode64); - return PPCInstr_Load( 4, rreg, am, mode64 ); - case HRcFlt64: - return PPCInstr_FpLdSt ( True/*load*/, 8, rreg, am ); - case HRcVec128: - // XXX: GPR30 used as spill register to kludge AltiVec AMode_IR - return PPCInstr_AvLdSt ( True/*load*/, 16, rreg, am ); - default: - ppHRegClass(hregClass(rreg)); - vpanic("genReload_PPC: unimplemented regclass"); + case HRcInt64: + vassert(mode64); + *i1 = PPCInstr_Load( 8, rreg, am, mode64 ); + return; + case HRcInt32: + vassert(!mode64); + *i1 = PPCInstr_Load( 4, rreg, am, mode64 ); + return; + case HRcFlt64: + *i1 = PPCInstr_FpLdSt ( True/*load*/, 8, rreg, am ); + return; + case HRcVec128: + // XXX: GPR30 used as spill register to kludge AltiVec AMode_IR + *i1 = PPCInstr_AvLdSt ( True/*load*/, 16, rreg, am ); + return; + default: + ppHRegClass(hregClass(rreg)); + vpanic("genReload_PPC: unimplemented regclass"); } } diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h index 7d8f3e1..accfd58 100644 --- a/VEX/priv/host_ppc_defs.h +++ b/VEX/priv/host_ppc_defs.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_ppc_defs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_ppc_defs.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -854,8 +843,12 @@ extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); extern Bool isMove_PPCInstr ( PPCInstr*, HReg*, HReg* ); extern Int emit_PPCInstr ( UChar* buf, Int nbuf, PPCInstr*, Bool mode64, void* dispatch ); -extern PPCInstr* genSpill_PPC ( HReg rreg, UShort offsetB, Bool mode64 ); -extern PPCInstr* genReload_PPC ( HReg rreg, UShort offsetB, Bool mode64 ); + +extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ); +extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ); + extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 ); extern HInstrArray* iselSB_PPC ( IRSB*, VexArch, VexArchInfo*, diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index 131e8fe..4ae18f3 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_ppc_isel.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_ppc_isel.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -1169,32 +1158,14 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e ) /* --------- LOAD --------- */ case Iex_Load: { - HReg r_dst; - + HReg r_dst; + PPCAMode* am_addr; if (e->Iex.Load.end != Iend_BE) goto irreducible; - - r_dst = newVRegI(env); - - if (e->Iex.Load.isLL) { - /* lwarx or ldarx. Be simple; force address into a register. */ - HReg r_addr = iselWordExpr_R( env, e->Iex.Load.addr ); - if (ty == Ity_I32) { - addInstr(env, PPCInstr_LoadL( 4, r_dst, r_addr, mode64 )); - } - else if (ty == Ity_I64 && mode64) { - addInstr(env, PPCInstr_LoadL( 8, r_dst, r_addr, mode64 )); - } - else - goto irreducible; - } else { - /* Normal load; use whatever amodes we can. */ - PPCAMode* am_addr - = iselWordExpr_AMode( env, e->Iex.Load.addr, ty/*of xfer*/ ); - addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)), - r_dst, am_addr, mode64 )); - } - + r_dst = newVRegI(env); + am_addr = iselWordExpr_AMode( env, e->Iex.Load.addr, ty/*of xfer*/ ); + addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)), + r_dst, am_addr, mode64 )); return r_dst; /*NOTREACHED*/ } @@ -1475,7 +1446,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e ) return r_ccIR; } - if (e->Iex.Binop.op == Iop_F64toI32) { + if (e->Iex.Binop.op == Iop_F64toI32S) { /* This works in both mode64 and mode32. */ HReg r1 = StackFramePtr(env->mode64); PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); @@ -1503,7 +1474,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e ) return idst; } - if (e->Iex.Binop.op == Iop_F64toI64) { + if (e->Iex.Binop.op == Iop_F64toI64S) { if (mode64) { HReg r1 = StackFramePtr(env->mode64); PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); @@ -1551,7 +1522,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e ) DECLARE_PATTERN(p_LDbe16_then_16Uto32); DEFINE_PATTERN(p_LDbe16_then_16Uto32, unop(Iop_16Uto32, - IRExpr_Load(False,Iend_BE,Ity_I16,bind(0))) ); + IRExpr_Load(Iend_BE,Ity_I16,bind(0))) ); if (matchIRExpr(&mi,p_LDbe16_then_16Uto32,e)) { HReg r_dst = newVRegI(env); PPCAMode* amode @@ -2609,7 +2580,7 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, vassert(typeOfIRExpr(env->type_env,e) == Ity_I64); /* 64-bit load */ - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { HReg tLo = newVRegI(env); HReg tHi = newVRegI(env); HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr); @@ -2750,8 +2721,8 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2); return; - /* F64toI64 */ - case Iop_F64toI64: { + /* F64toI64S */ + case Iop_F64toI64S: { HReg tLo = newVRegI(env); HReg tHi = newVRegI(env); HReg r1 = StackFramePtr(env->mode64); @@ -2967,7 +2938,7 @@ static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) return lookupIRTemp(env, e->Iex.RdTmp.tmp); } - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { PPCAMode* am_addr; HReg r_dst = newVRegF(env); vassert(e->Iex.Load.ty == Ity_F32); @@ -3115,7 +3086,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) } /* --------- LOAD --------- */ - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { HReg r_dst = newVRegF(env); PPCAMode* am_addr; vassert(e->Iex.Load.ty == Ity_F64); @@ -3204,7 +3175,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) return r_dst; } - if (e->Iex.Binop.op == Iop_I64toF64) { + if (e->Iex.Binop.op == Iop_I64StoF64) { if (mode64) { HReg fdst = newVRegF(env); HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2); @@ -3366,7 +3337,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { PPCAMode* am_addr; HReg v_dst = newVRegV(env); vassert(e->Iex.Load.ty == Ity_V128); @@ -3770,7 +3741,6 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr); IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); IREndness end = stmt->Ist.Store.end; - IRTemp resSC = stmt->Ist.Store.resSC; if (end != Iend_BE) goto stmt_fail; @@ -3779,34 +3749,6 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) if (mode64 && (tya != Ity_I64)) goto stmt_fail; - if (resSC != IRTemp_INVALID) { - /* deal with store-conditional */ - HReg r_res = lookupIRTemp(env, resSC); - HReg r_a = iselWordExpr_R(env, stmt->Ist.Store.addr); - HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data); - HReg r_tmp = newVRegI(env); - if (tyd == Ity_I32 || (tyd == Ity_I64 && mode64)) { - addInstr(env, PPCInstr_StoreC( tyd==Ity_I32 ? 4 : 8, - r_a, r_src, mode64 )); - addInstr(env, PPCInstr_MfCR( r_tmp )); - addInstr(env, PPCInstr_Shft( - Pshft_SHR, - env->mode64 ? False : True/*F:64-bit, T:32-bit shift*/, - r_tmp, r_tmp, - PPCRH_Imm(False/*unsigned*/, 29))); - /* Probably unnecessary, since the IR dest type is Ity_I1, - and so we are entitled to leave whatever junk we like - drifting round in the upper 31 or 63 bits of r_res. - However, for the sake of conservativeness .. */ - addInstr(env, PPCInstr_Alu( - Palu_AND, - r_res, r_tmp, - PPCRH_Imm(False/*signed*/, 1))); - return; - } - goto stmt_fail; - } - if (tyd == Ity_I8 || tyd == Ity_I16 || tyd == Ity_I32 || (mode64 && (tyd == Ity_I64))) { PPCAMode* am_addr @@ -3979,6 +3921,67 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) break; } + /* --------- Load Linked or Store Conditional --------- */ + case Ist_LLSC: { + IRTemp res = stmt->Ist.LLSC.result; + IRType tyRes = typeOfIRTemp(env->type_env, res); + IRType tyAddr = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.addr); + + if (stmt->Ist.LLSC.end != Iend_BE) + goto stmt_fail; + if (!mode64 && (tyAddr != Ity_I32)) + goto stmt_fail; + if (mode64 && (tyAddr != Ity_I64)) + goto stmt_fail; + + if (stmt->Ist.LLSC.storedata == NULL) { + /* LL */ + HReg r_addr = iselWordExpr_R( env, stmt->Ist.LLSC.addr ); + HReg r_dst = lookupIRTemp(env, res); + if (tyRes == Ity_I32) { + addInstr(env, PPCInstr_LoadL( 4, r_dst, r_addr, mode64 )); + return; + } + if (tyRes == Ity_I64 && mode64) { + addInstr(env, PPCInstr_LoadL( 8, r_dst, r_addr, mode64 )); + return; + } + /* fallthru */; + } else { + /* SC */ + HReg r_res = lookupIRTemp(env, res); /* :: Ity_I1 */ + HReg r_a = iselWordExpr_R(env, stmt->Ist.LLSC.addr); + HReg r_src = iselWordExpr_R(env, stmt->Ist.LLSC.storedata); + HReg r_tmp = newVRegI(env); + IRType tyData = typeOfIRExpr(env->type_env, + stmt->Ist.LLSC.storedata); + vassert(tyRes == Ity_I1); + if (tyData == Ity_I32 || (tyData == Ity_I64 && mode64)) { + addInstr(env, PPCInstr_StoreC( tyData==Ity_I32 ? 4 : 8, + r_a, r_src, mode64 )); + addInstr(env, PPCInstr_MfCR( r_tmp )); + addInstr(env, PPCInstr_Shft( + Pshft_SHR, + env->mode64 ? False : True + /*F:64-bit, T:32-bit shift*/, + r_tmp, r_tmp, + PPCRH_Imm(False/*unsigned*/, 29))); + /* Probably unnecessary, since the IR dest type is Ity_I1, + and so we are entitled to leave whatever junk we like + drifting round in the upper 31 or 63 bits of r_res. + However, for the sake of conservativeness .. */ + addInstr(env, PPCInstr_Alu( + Palu_AND, + r_res, r_tmp, + PPCRH_Imm(False/*signed*/, 1))); + return; + } + /* fallthru */ + } + goto stmt_fail; + /*NOTREACHED*/ + } + /* --------- Call to DIRTY helper --------- */ case Ist_Dirty: { IRType retty; diff --git a/VEX/priv/host_x86_defs.c b/VEX/priv/host_x86_defs.c index 6fa4125..9a6d651 100644 --- a/VEX/priv/host_x86_defs.c +++ b/VEX/priv/host_x86_defs.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_x86_defs.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_x86_defs.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -714,8 +703,10 @@ X86Instr* X86Instr_MFence ( UInt hwcaps ) { X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); i->tag = Xin_MFence; i->Xin.MFence.hwcaps = hwcaps; - vassert(0 == (hwcaps & ~(VEX_HWCAPS_X86_SSE1|VEX_HWCAPS_X86_SSE2 - |VEX_HWCAPS_X86_SSE3))); + vassert(0 == (hwcaps & ~(VEX_HWCAPS_X86_SSE1 + |VEX_HWCAPS_X86_SSE2 + |VEX_HWCAPS_X86_SSE3 + |VEX_HWCAPS_X86_LZCNT))); return i; } X86Instr* X86Instr_ACAS ( X86AMode* addr, UChar sz ) { @@ -1620,41 +1611,50 @@ Bool isMove_X86Instr ( X86Instr* i, HReg* src, HReg* dst ) register allocator. Note it's critical these don't write the condition codes. */ -X86Instr* genSpill_X86 ( HReg rreg, Int offsetB, Bool mode64 ) +void genSpill_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) { X86AMode* am; vassert(offsetB >= 0); vassert(!hregIsVirtual(rreg)); vassert(mode64 == False); + *i1 = *i2 = NULL; am = X86AMode_IR(offsetB, hregX86_EBP()); - switch (hregClass(rreg)) { case HRcInt32: - return X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am ); + *i1 = X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am ); + return; case HRcFlt64: - return X86Instr_FpLdSt ( False/*store*/, 10, rreg, am ); + *i1 = X86Instr_FpLdSt ( False/*store*/, 10, rreg, am ); + return; case HRcVec128: - return X86Instr_SseLdSt ( False/*store*/, rreg, am ); + *i1 = X86Instr_SseLdSt ( False/*store*/, rreg, am ); + return; default: ppHRegClass(hregClass(rreg)); vpanic("genSpill_X86: unimplemented regclass"); } } -X86Instr* genReload_X86 ( HReg rreg, Int offsetB, Bool mode64 ) +void genReload_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) { X86AMode* am; vassert(offsetB >= 0); vassert(!hregIsVirtual(rreg)); vassert(mode64 == False); + *i1 = *i2 = NULL; am = X86AMode_IR(offsetB, hregX86_EBP()); switch (hregClass(rreg)) { case HRcInt32: - return X86Instr_Alu32R ( Xalu_MOV, X86RMI_Mem(am), rreg ); + *i1 = X86Instr_Alu32R ( Xalu_MOV, X86RMI_Mem(am), rreg ); + return; case HRcFlt64: - return X86Instr_FpLdSt ( True/*load*/, 10, rreg, am ); + *i1 = X86Instr_FpLdSt ( True/*load*/, 10, rreg, am ); + return; case HRcVec128: - return X86Instr_SseLdSt ( True/*load*/, rreg, am ); + *i1 = X86Instr_SseLdSt ( True/*load*/, rreg, am ); + return; default: ppHRegClass(hregClass(rreg)); vpanic("genReload_X86: unimplemented regclass"); diff --git a/VEX/priv/host_x86_defs.h b/VEX/priv/host_x86_defs.h index 1f4441a..fde700a 100644 --- a/VEX/priv/host_x86_defs.h +++ b/VEX/priv/host_x86_defs.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_x86_defs.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_x86_defs.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -685,8 +674,12 @@ extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool ); extern Bool isMove_X86Instr ( X86Instr*, HReg*, HReg* ); extern Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr*, Bool, void* dispatch ); -extern X86Instr* genSpill_X86 ( HReg rreg, Int offset, Bool ); -extern X86Instr* genReload_X86 ( HReg rreg, Int offset, Bool ); + +extern void genSpill_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offset, Bool ); +extern void genReload_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, + HReg rreg, Int offset, Bool ); + extern X86Instr* directReload_X86 ( X86Instr* i, HReg vreg, Short spill_off ); extern void getAllocableRegs_X86 ( Int*, HReg** ); diff --git a/VEX/priv/host_x86_isel.c b/VEX/priv/host_x86_isel.c index 899a5c3..fc5cf05 100644 --- a/VEX/priv/host_x86_isel.c +++ b/VEX/priv/host_x86_isel.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (host_x86_isel.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin host_x86_isel.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -763,8 +752,6 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) /* We can't handle big-endian loads, nor load-linked. */ if (e->Iex.Load.end != Iend_LE) goto irreducible; - if (e->Iex.Load.isLL) - goto irreducible; if (ty == Ity_I32) { addInstr(env, X86Instr_Alu32R(Xalu_MOV, @@ -1000,8 +987,9 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) return dst; } - if (e->Iex.Binop.op == Iop_F64toI32 || e->Iex.Binop.op == Iop_F64toI16) { - Int sz = e->Iex.Binop.op == Iop_F64toI16 ? 2 : 4; + if (e->Iex.Binop.op == Iop_F64toI32S + || e->Iex.Binop.op == Iop_F64toI16S) { + Int sz = e->Iex.Binop.op == Iop_F64toI16S ? 2 : 4; HReg rf = iselDblExpr(env, e->Iex.Binop.arg2); HReg dst = newVRegI(env); @@ -1069,7 +1057,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) DECLARE_PATTERN(p_LDle8_then_8Uto32); DEFINE_PATTERN(p_LDle8_then_8Uto32, unop(Iop_8Uto32, - IRExpr_Load(False,Iend_LE,Ity_I8,bind(0))) ); + IRExpr_Load(Iend_LE,Ity_I8,bind(0))) ); if (matchIRExpr(&mi,p_LDle8_then_8Uto32,e)) { HReg dst = newVRegI(env); X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); @@ -1083,7 +1071,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) DECLARE_PATTERN(p_LDle8_then_8Sto32); DEFINE_PATTERN(p_LDle8_then_8Sto32, unop(Iop_8Sto32, - IRExpr_Load(False,Iend_LE,Ity_I8,bind(0))) ); + IRExpr_Load(Iend_LE,Ity_I8,bind(0))) ); if (matchIRExpr(&mi,p_LDle8_then_8Sto32,e)) { HReg dst = newVRegI(env); X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); @@ -1097,7 +1085,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) DECLARE_PATTERN(p_LDle16_then_16Uto32); DEFINE_PATTERN(p_LDle16_then_16Uto32, unop(Iop_16Uto32, - IRExpr_Load(False,Iend_LE,Ity_I16,bind(0))) ); + IRExpr_Load(Iend_LE,Ity_I16,bind(0))) ); if (matchIRExpr(&mi,p_LDle16_then_16Uto32,e)) { HReg dst = newVRegI(env); X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] ); @@ -1536,7 +1524,7 @@ static X86RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, IRExpr* e ) /* special case: 32-bit load from memory */ if (e->tag == Iex_Load && ty == Ity_I32 - && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + && e->Iex.Load.end == Iend_LE) { X86AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr); return X86RMI_Mem(am); } @@ -1955,7 +1943,7 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) } /* 64-bit load */ - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { HReg tLo, tHi; X86AMode *am0, *am4; vassert(e->Iex.Load.ty == Ity_I64); @@ -2262,7 +2250,7 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) /* Sigh, this is an almost exact copy of the F64 -> I32/I16 case. Unfortunately I see no easy way to avoid the duplication. */ - case Iop_F64toI64: { + case Iop_F64toI64S: { HReg rf = iselDblExpr(env, e->Iex.Binop.arg2); HReg tLo = newVRegI(env); HReg tHi = newVRegI(env); @@ -2500,6 +2488,20 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) return; } + /* 16Uto64(e) */ + case Iop_16Uto64: { + HReg tLo = newVRegI(env); + HReg tHi = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, mk_iMOVsd_RR(src,tLo)); + addInstr(env, X86Instr_Alu32R(Xalu_AND, + X86RMI_Imm(0xFFFF), tLo)); + addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tHi)); + *rHi = tHi; + *rLo = tLo; + return; + } + /* V128{HI}to64 */ case Iop_V128HIto64: case Iop_V128to64: { @@ -2743,7 +2745,7 @@ static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) return lookupIRTemp(env, e->Iex.RdTmp.tmp); } - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { X86AMode* am; HReg res = newVRegF(env); vassert(e->Iex.Load.ty == Ity_F32); @@ -2788,6 +2790,25 @@ static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } + if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_RoundF32toInt) { + HReg rf = iselFltExpr(env, e->Iex.Binop.arg2); + HReg dst = newVRegF(env); + + /* rf now holds the value to be rounded. The first thing to do + is set the FPU's rounding mode accordingly. */ + + /* Set host rounding mode */ + set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); + + /* grndint %rf, %dst */ + addInstr(env, X86Instr_FpUnary(Xfp_ROUND, rf, dst)); + + /* Restore default FPU rounding. */ + set_FPU_rounding_default( env ); + + return dst; + } + ppIRExpr(e); vpanic("iselFltExpr_wrk"); } @@ -2867,7 +2888,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) return freg; } - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { X86AMode* am; HReg res = newVRegF(env); vassert(e->Iex.Load.ty == Ity_F64); @@ -2942,7 +2963,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } - if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_I64toF64) { + if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_I64StoF64) { HReg dst = newVRegF(env); HReg rHi,rLo; iselInt64Expr( &rHi, &rLo, env, e->Iex.Binop.arg2); @@ -3005,7 +3026,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) if (e->tag == Iex_Unop) { switch (e->Iex.Unop.op) { - case Iop_I32toF64: { + case Iop_I32StoF64: { HReg dst = newVRegF(env); HReg ri = iselIntExpr_R(env, e->Iex.Unop.arg); addInstr(env, X86Instr_Push(X86RMI_Reg(ri))); @@ -3119,7 +3140,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } - if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE && !e->Iex.Load.isLL) { + if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { HReg dst = newVRegV(env); X86AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr); addInstr(env, X86Instr_SseLdSt( True/*load*/, dst, am )); @@ -3140,7 +3161,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) DECLARE_PATTERN(p_zwiden_load64); DEFINE_PATTERN(p_zwiden_load64, unop(Iop_64UtoV128, - IRExpr_Load(False,Iend_LE,Ity_I64,bind(0)))); + IRExpr_Load(Iend_LE,Ity_I64,bind(0)))); if (matchIRExpr(&mi, p_zwiden_load64, e)) { X86AMode* am = iselIntExpr_AMode(env, mi.bindee[0]); HReg dst = newVRegV(env); @@ -3608,9 +3629,8 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr); IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); IREndness end = stmt->Ist.Store.end; - IRTemp resSC = stmt->Ist.Store.resSC; - if (tya != Ity_I32 || end != Iend_LE || resSC != IRTemp_INVALID) + if (tya != Ity_I32 || end != Iend_LE) goto stmt_fail; if (tyd == Ity_I32) { @@ -3994,9 +4014,11 @@ HInstrArray* iselSB_X86 ( IRSB* bb, VexArch arch_host, /* sanity ... */ vassert(arch_host == VexArchX86); - vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_X86_SSE1 - |VEX_HWCAPS_X86_SSE2 - |VEX_HWCAPS_X86_SSE3))); + vassert(0 == (hwcaps_host + & ~(VEX_HWCAPS_X86_SSE1 + | VEX_HWCAPS_X86_SSE2 + | VEX_HWCAPS_X86_SSE3 + | VEX_HWCAPS_X86_LZCNT))); /* Make up an initial environment to use. */ env = LibVEX_Alloc(sizeof(ISelEnv)); diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index 971370d..f78db10 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (ir_defs.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin ir_defs.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -257,6 +246,10 @@ void ppIROp ( IROp op ) case Iop_SubF64r32: vex_printf("SubF64r32"); return; case Iop_MulF64r32: vex_printf("MulF64r32"); return; case Iop_DivF64r32: vex_printf("DivF64r32"); return; + case Iop_AddF32: vex_printf("AddF32"); return; + case Iop_SubF32: vex_printf("SubF32"); return; + case Iop_MulF32: vex_printf("MulF32"); return; + case Iop_DivF32: vex_printf("DivF32"); return; case Iop_ScaleF64: vex_printf("ScaleF64"); return; case Iop_AtanF64: vex_printf("AtanF64"); return; @@ -267,9 +260,11 @@ void ppIROp ( IROp op ) case Iop_PRem1F64: vex_printf("PRem1F64"); return; case Iop_PRem1C3210F64: vex_printf("PRem1C3210F64"); return; case Iop_NegF64: vex_printf("NegF64"); return; + case Iop_AbsF64: vex_printf("AbsF64"); return; + case Iop_NegF32: vex_printf("NegF32"); return; + case Iop_AbsF32: vex_printf("AbsF32"); return; case Iop_SqrtF64: vex_printf("SqrtF64"); return; - - case Iop_AbsF64: vex_printf("AbsF64"); return; + case Iop_SqrtF32: vex_printf("SqrtF32"); return; case Iop_SinF64: vex_printf("SinF64"); return; case Iop_CosF64: vex_printf("CosF64"); return; case Iop_TanF64: vex_printf("TanF64"); return; @@ -289,20 +284,51 @@ void ppIROp ( IROp op ) case Iop_TruncF64asF32: vex_printf("TruncF64asF32"); return; case Iop_CalcFPRF: vex_printf("CalcFPRF"); return; + case Iop_Add16x2: vex_printf("Add16x2"); return; + case Iop_Sub16x2: vex_printf("Sub16x2"); return; + case Iop_QAdd16Sx2: vex_printf("QAdd16Sx2"); return; + case Iop_QAdd16Ux2: vex_printf("QAdd16Ux2"); return; + case Iop_QSub16Sx2: vex_printf("QSub16Sx2"); return; + case Iop_QSub16Ux2: vex_printf("QSub16Ux2"); return; + case Iop_HAdd16Ux2: vex_printf("HAdd16Ux2"); return; + case Iop_HAdd16Sx2: vex_printf("HAdd16Sx2"); return; + case Iop_HSub16Ux2: vex_printf("HSub16Ux2"); return; + case Iop_HSub16Sx2: vex_printf("HSub16Sx2"); return; + + case Iop_Add8x4: vex_printf("Add8x4"); return; + case Iop_Sub8x4: vex_printf("Sub8x4"); return; + case Iop_QAdd8Sx4: vex_printf("QAdd8Sx4"); return; + case Iop_QAdd8Ux4: vex_printf("QAdd8Ux4"); return; + case Iop_QSub8Sx4: vex_printf("QSub8Sx4"); return; + case Iop_QSub8Ux4: vex_printf("QSub8Ux4"); return; + case Iop_HAdd8Ux4: vex_printf("HAdd8Ux4"); return; + case Iop_HAdd8Sx4: vex_printf("HAdd8Sx4"); return; + case Iop_HSub8Ux4: vex_printf("HSub8Ux4"); return; + case Iop_HSub8Sx4: vex_printf("HSub8Sx4"); return; + case Iop_Sad8Ux4: vex_printf("Sad8Ux4"); return; + + case Iop_CmpNEZ16x2: vex_printf("CmpNEZ16x2"); return; + case Iop_CmpNEZ8x4: vex_printf("CmpNEZ8x4"); return; + case Iop_CmpF64: vex_printf("CmpF64"); return; - case Iop_F64toI16: vex_printf("F64toI16"); return; - case Iop_F64toI32: vex_printf("F64toI32"); return; - case Iop_F64toI64: vex_printf("F64toI64"); return; + case Iop_F64toI16S: vex_printf("F64toI16S"); return; + case Iop_F64toI32S: vex_printf("F64toI32S"); return; + case Iop_F64toI64S: vex_printf("F64toI64S"); return; + + case Iop_F64toI32U: vex_printf("F64toI32U"); return; - case Iop_I16toF64: vex_printf("I16toF64"); return; - case Iop_I32toF64: vex_printf("I32toF64"); return; - case Iop_I64toF64: vex_printf("I64toF64"); return; + case Iop_I16StoF64: vex_printf("I16StoF64"); return; + case Iop_I32StoF64: vex_printf("I32StoF64"); return; + case Iop_I64StoF64: vex_printf("I64StoF64"); return; + + case Iop_I32UtoF64: vex_printf("I32UtoF64"); return; case Iop_F32toF64: vex_printf("F32toF64"); return; case Iop_F64toF32: vex_printf("F64toF32"); return; case Iop_RoundF64toInt: vex_printf("RoundF64toInt"); return; + case Iop_RoundF32toInt: vex_printf("RoundF32toInt"); return; case Iop_RoundF64toF32: vex_printf("RoundF64toF32"); return; case Iop_ReinterpF64asI64: vex_printf("ReinterpF64asI64"); return; @@ -313,47 +339,125 @@ void ppIROp ( IROp op ) case Iop_I32UtoFx4: vex_printf("I32UtoFx4"); return; case Iop_I32StoFx4: vex_printf("I32StoFx4"); return; + case Iop_F32toF16x4: vex_printf("F32toF16x4"); return; + case Iop_F16toF32x4: vex_printf("F16toF32x4"); return; + + case Iop_Rsqrte32Fx4: vex_printf("VRsqrte32Fx4"); return; + case Iop_Rsqrte32x4: vex_printf("VRsqrte32x4"); return; + case Iop_Rsqrte32Fx2: vex_printf("VRsqrte32Fx2"); return; + case Iop_Rsqrte32x2: vex_printf("VRsqrte32x2"); return; + case Iop_QFtoI32Ux4_RZ: vex_printf("QFtoI32Ux4_RZ"); return; case Iop_QFtoI32Sx4_RZ: vex_printf("QFtoI32Sx4_RZ"); return; + case Iop_FtoI32Ux4_RZ: vex_printf("FtoI32Ux4_RZ"); return; + case Iop_FtoI32Sx4_RZ: vex_printf("FtoI32Sx4_RZ"); return; + + case Iop_I32UtoFx2: vex_printf("I32UtoFx2"); return; + case Iop_I32StoFx2: vex_printf("I32StoFx2"); return; + + case Iop_FtoI32Ux2_RZ: vex_printf("FtoI32Ux2_RZ"); return; + case Iop_FtoI32Sx2_RZ: vex_printf("FtoI32Sx2_RZ"); return; + case Iop_RoundF32x4_RM: vex_printf("RoundF32x4_RM"); return; case Iop_RoundF32x4_RP: vex_printf("RoundF32x4_RP"); return; case Iop_RoundF32x4_RN: vex_printf("RoundF32x4_RN"); return; case Iop_RoundF32x4_RZ: vex_printf("RoundF32x4_RZ"); return; + case Iop_Abs8x8: vex_printf("Abs8x8"); return; + case Iop_Abs16x4: vex_printf("Abs16x4"); return; + case Iop_Abs32x2: vex_printf("Abs32x2"); return; case Iop_Add8x8: vex_printf("Add8x8"); return; case Iop_Add16x4: vex_printf("Add16x4"); return; case Iop_Add32x2: vex_printf("Add32x2"); return; case Iop_QAdd8Ux8: vex_printf("QAdd8Ux8"); return; case Iop_QAdd16Ux4: vex_printf("QAdd16Ux4"); return; + case Iop_QAdd32Ux2: vex_printf("QAdd32Ux2"); return; + case Iop_QAdd64Ux1: vex_printf("QAdd64Ux1"); return; case Iop_QAdd8Sx8: vex_printf("QAdd8Sx8"); return; case Iop_QAdd16Sx4: vex_printf("QAdd16Sx4"); return; + case Iop_QAdd32Sx2: vex_printf("QAdd32Sx2"); return; + case Iop_QAdd64Sx1: vex_printf("QAdd64Sx1"); return; + case Iop_PwAdd8x8: vex_printf("PwAdd8x8"); return; + case Iop_PwAdd16x4: vex_printf("PwAdd16x4"); return; + case Iop_PwAdd32x2: vex_printf("PwAdd32x2"); return; + case Iop_PwAdd32Fx2: vex_printf("PwAdd32Fx2"); return; + case Iop_PwAddL8Ux8: vex_printf("PwAddL8Ux8"); return; + case Iop_PwAddL16Ux4: vex_printf("PwAddL16Ux4"); return; + case Iop_PwAddL32Ux2: vex_printf("PwAddL32Ux2"); return; + case Iop_PwAddL8Sx8: vex_printf("PwAddL8Sx8"); return; + case Iop_PwAddL16Sx4: vex_printf("PwAddL16Sx4"); return; + case Iop_PwAddL32Sx2: vex_printf("PwAddL32Sx2"); return; case Iop_Sub8x8: vex_printf("Sub8x8"); return; case Iop_Sub16x4: vex_printf("Sub16x4"); return; case Iop_Sub32x2: vex_printf("Sub32x2"); return; case Iop_QSub8Ux8: vex_printf("QSub8Ux8"); return; case Iop_QSub16Ux4: vex_printf("QSub16Ux4"); return; + case Iop_QSub32Ux2: vex_printf("QSub32Ux2"); return; + case Iop_QSub64Ux1: vex_printf("QSub64Ux1"); return; case Iop_QSub8Sx8: vex_printf("QSub8Sx8"); return; case Iop_QSub16Sx4: vex_printf("QSub16Sx4"); return; + case Iop_QSub32Sx2: vex_printf("QSub32Sx2"); return; + case Iop_QSub64Sx1: vex_printf("QSub64Sx1"); return; + case Iop_Mul8x8: vex_printf("Mul8x8"); return; case Iop_Mul16x4: vex_printf("Mul16x4"); return; case Iop_Mul32x2: vex_printf("Mul32x2"); return; + case Iop_Mul32Fx2: vex_printf("Mul32Fx2"); return; + case Iop_PolynomialMul8x8: vex_printf("PolynomialMul8x8"); return; case Iop_MulHi16Ux4: vex_printf("MulHi16Ux4"); return; case Iop_MulHi16Sx4: vex_printf("MulHi16Sx4"); return; + case Iop_QDMulHi16Sx4: vex_printf("QDMulHi16Sx4"); return; + case Iop_QDMulHi32Sx2: vex_printf("QDMulHi32Sx2"); return; + case Iop_QRDMulHi16Sx4: vex_printf("QRDMulHi16Sx4"); return; + case Iop_QRDMulHi32Sx2: vex_printf("QRDMulHi32Sx2"); return; + case Iop_QDMulLong16Sx4: vex_printf("QDMulLong16Sx4"); return; + case Iop_QDMulLong32Sx2: vex_printf("QDMulLong32Sx2"); return; case Iop_Avg8Ux8: vex_printf("Avg8Ux8"); return; case Iop_Avg16Ux4: vex_printf("Avg16Ux4"); return; + case Iop_Max8Sx8: vex_printf("Max8Sx8"); return; case Iop_Max16Sx4: vex_printf("Max16Sx4"); return; + case Iop_Max32Sx2: vex_printf("Max32Sx2"); return; case Iop_Max8Ux8: vex_printf("Max8Ux8"); return; + case Iop_Max16Ux4: vex_printf("Max16Ux4"); return; + case Iop_Max32Ux2: vex_printf("Max32Ux2"); return; + case Iop_Min8Sx8: vex_printf("Min8Sx8"); return; case Iop_Min16Sx4: vex_printf("Min16Sx4"); return; + case Iop_Min32Sx2: vex_printf("Min32Sx2"); return; case Iop_Min8Ux8: vex_printf("Min8Ux8"); return; + case Iop_Min16Ux4: vex_printf("Min16Ux4"); return; + case Iop_Min32Ux2: vex_printf("Min32Ux2"); return; + case Iop_PwMax8Sx8: vex_printf("PwMax8Sx8"); return; + case Iop_PwMax16Sx4: vex_printf("PwMax16Sx4"); return; + case Iop_PwMax32Sx2: vex_printf("PwMax32Sx2"); return; + case Iop_PwMax8Ux8: vex_printf("PwMax8Ux8"); return; + case Iop_PwMax16Ux4: vex_printf("PwMax16Ux4"); return; + case Iop_PwMax32Ux2: vex_printf("PwMax32Ux2"); return; + case Iop_PwMin8Sx8: vex_printf("PwMin8Sx8"); return; + case Iop_PwMin16Sx4: vex_printf("PwMin16Sx4"); return; + case Iop_PwMin32Sx2: vex_printf("PwMin32Sx2"); return; + case Iop_PwMin8Ux8: vex_printf("PwMin8Ux8"); return; + case Iop_PwMin16Ux4: vex_printf("PwMin16Ux4"); return; + case Iop_PwMin32Ux2: vex_printf("PwMin32Ux2"); return; case Iop_CmpEQ8x8: vex_printf("CmpEQ8x8"); return; case Iop_CmpEQ16x4: vex_printf("CmpEQ16x4"); return; case Iop_CmpEQ32x2: vex_printf("CmpEQ32x2"); return; + case Iop_CmpGT8Ux8: vex_printf("CmpGT8Ux8"); return; + case Iop_CmpGT16Ux4: vex_printf("CmpGT16Ux4"); return; + case Iop_CmpGT32Ux2: vex_printf("CmpGT32Ux2"); return; case Iop_CmpGT8Sx8: vex_printf("CmpGT8Sx8"); return; case Iop_CmpGT16Sx4: vex_printf("CmpGT16Sx4"); return; case Iop_CmpGT32Sx2: vex_printf("CmpGT32Sx2"); return; + case Iop_Cnt8x8: vex_printf("Cnt8x8"); return; + case Iop_Clz8Sx8: vex_printf("Clz8Sx8"); return; + case Iop_Clz16Sx4: vex_printf("Clz16Sx4"); return; + case Iop_Clz32Sx2: vex_printf("Clz32Sx2"); return; + case Iop_Cls8Sx8: vex_printf("Cls8Sx8"); return; + case Iop_Cls16Sx4: vex_printf("Cls16Sx4"); return; + case Iop_Cls32Sx2: vex_printf("Cls32Sx2"); return; case Iop_ShlN8x8: vex_printf("ShlN8x8"); return; case Iop_ShlN16x4: vex_printf("ShlN16x4"); return; case Iop_ShlN32x2: vex_printf("ShlN32x2"); return; + case Iop_ShrN8x8: vex_printf("ShrN8x8"); return; case Iop_ShrN16x4: vex_printf("ShrN16x4"); return; case Iop_ShrN32x2: vex_printf("ShrN32x2"); return; case Iop_SarN8x8: vex_printf("SarN8x8"); return; @@ -368,15 +472,62 @@ void ppIROp ( IROp op ) case Iop_InterleaveLO8x8: vex_printf("InterleaveLO8x8"); return; case Iop_InterleaveLO16x4: vex_printf("InterleaveLO16x4"); return; case Iop_InterleaveLO32x2: vex_printf("InterleaveLO32x2"); return; + case Iop_CatOddLanes8x8: vex_printf("CatOddLanes8x8"); return; case Iop_CatOddLanes16x4: vex_printf("CatOddLanes16x4"); return; + case Iop_CatEvenLanes8x8: vex_printf("CatEvenLanes8x8"); return; case Iop_CatEvenLanes16x4: vex_printf("CatEvenLanes16x4"); return; + case Iop_InterleaveOddLanes8x8: vex_printf("InterleaveOddLanes8x8"); return; + case Iop_InterleaveOddLanes16x4: vex_printf("InterleaveOddLanes16x4"); return; + case Iop_InterleaveEvenLanes8x8: vex_printf("InterleaveEvenLanes8x8"); return; + case Iop_InterleaveEvenLanes16x4: vex_printf("InterleaveEvenLanes16x4"); return; + case Iop_Shl8x8: vex_printf("Shl8x8"); return; + case Iop_Shl16x4: vex_printf("Shl16x4"); return; + case Iop_Shl32x2: vex_printf("Shl32x2"); return; + case Iop_Shr8x8: vex_printf("Shr8x8"); return; + case Iop_Shr16x4: vex_printf("Shr16x4"); return; + case Iop_Shr32x2: vex_printf("Shr32x2"); return; + case Iop_QShl8x8: vex_printf("QShl8x8"); return; + case Iop_QShl16x4: vex_printf("QShl16x4"); return; + case Iop_QShl32x2: vex_printf("QShl32x2"); return; + case Iop_QShl64x1: vex_printf("QShl64x1"); return; + case Iop_QSal8x8: vex_printf("QSal8x8"); return; + case Iop_QSal16x4: vex_printf("QSal16x4"); return; + case Iop_QSal32x2: vex_printf("QSal32x2"); return; + case Iop_QSal64x1: vex_printf("QSal64x1"); return; + case Iop_QShlN8x8: vex_printf("QShlN8x8"); return; + case Iop_QShlN16x4: vex_printf("QShlN16x4"); return; + case Iop_QShlN32x2: vex_printf("QShlN32x2"); return; + case Iop_QShlN64x1: vex_printf("QShlN64x1"); return; + case Iop_QShlN8Sx8: vex_printf("QShlN8Sx8"); return; + case Iop_QShlN16Sx4: vex_printf("QShlN16Sx4"); return; + case Iop_QShlN32Sx2: vex_printf("QShlN32Sx2"); return; + case Iop_QShlN64Sx1: vex_printf("QShlN64Sx1"); return; + case Iop_QSalN8x8: vex_printf("QSalN8x8"); return; + case Iop_QSalN16x4: vex_printf("QSalN16x4"); return; + case Iop_QSalN32x2: vex_printf("QSalN32x2"); return; + case Iop_QSalN64x1: vex_printf("QSalN64x1"); return; + case Iop_Sar8x8: vex_printf("Sar8x8"); return; + case Iop_Sar16x4: vex_printf("Sar16x4"); return; + case Iop_Sar32x2: vex_printf("Sar32x2"); return; + case Iop_Sal8x8: vex_printf("Sal8x8"); return; + case Iop_Sal16x4: vex_printf("Sal16x4"); return; + case Iop_Sal32x2: vex_printf("Sal32x2"); return; + case Iop_Sal64x1: vex_printf("Sal64x1"); return; case Iop_Perm8x8: vex_printf("Perm8x8"); return; + case Iop_Reverse16_8x8: vex_printf("Reverse16_8x8"); return; + case Iop_Reverse32_8x8: vex_printf("Reverse32_8x8"); return; + case Iop_Reverse32_16x4: vex_printf("Reverse32_16x4"); return; + case Iop_Reverse64_8x8: vex_printf("Reverse64_8x8"); return; + case Iop_Reverse64_16x4: vex_printf("Reverse64_16x4"); return; + case Iop_Reverse64_32x2: vex_printf("Reverse64_32x2"); return; + case Iop_Abs32Fx2: vex_printf("Abs32Fx2"); return; case Iop_CmpNEZ32x2: vex_printf("CmpNEZ32x2"); return; case Iop_CmpNEZ16x4: vex_printf("CmpNEZ16x4"); return; case Iop_CmpNEZ8x8: vex_printf("CmpNEZ8x8"); return; case Iop_Add32Fx4: vex_printf("Add32Fx4"); return; + case Iop_Add32Fx2: vex_printf("Add32Fx2"); return; case Iop_Add32F0x4: vex_printf("Add32F0x4"); return; case Iop_Add64Fx2: vex_printf("Add64Fx2"); return; case Iop_Add64F0x2: vex_printf("Add64F0x2"); return; @@ -387,11 +538,17 @@ void ppIROp ( IROp op ) case Iop_Div64F0x2: vex_printf("Div64F0x2"); return; case Iop_Max32Fx4: vex_printf("Max32Fx4"); return; + case Iop_Max32Fx2: vex_printf("Max32Fx2"); return; + case Iop_PwMax32Fx4: vex_printf("PwMax32Fx4"); return; + case Iop_PwMax32Fx2: vex_printf("PwMax32Fx2"); return; case Iop_Max32F0x4: vex_printf("Max32F0x4"); return; case Iop_Max64Fx2: vex_printf("Max64Fx2"); return; case Iop_Max64F0x2: vex_printf("Max64F0x2"); return; case Iop_Min32Fx4: vex_printf("Min32Fx4"); return; + case Iop_Min32Fx2: vex_printf("Min32Fx2"); return; + case Iop_PwMin32Fx4: vex_printf("PwMin32Fx4"); return; + case Iop_PwMin32Fx2: vex_printf("PwMin32Fx2"); return; case Iop_Min32F0x4: vex_printf("Min32F0x4"); return; case Iop_Min64Fx2: vex_printf("Min64Fx2"); return; case Iop_Min64F0x2: vex_printf("Min64F0x2"); return; @@ -401,10 +558,18 @@ void ppIROp ( IROp op ) case Iop_Mul64Fx2: vex_printf("Mul64Fx2"); return; case Iop_Mul64F0x2: vex_printf("Mul64F0x2"); return; + case Iop_Recip32x2: vex_printf("Recip32x2"); return; + case Iop_Recip32Fx2: vex_printf("Recip32Fx2"); return; case Iop_Recip32Fx4: vex_printf("Recip32Fx4"); return; + case Iop_Recip32x4: vex_printf("Recip32x4"); return; case Iop_Recip32F0x4: vex_printf("Recip32F0x4"); return; case Iop_Recip64Fx2: vex_printf("Recip64Fx2"); return; case Iop_Recip64F0x2: vex_printf("Recip64F0x2"); return; + case Iop_Recps32Fx2: vex_printf("VRecps32Fx2"); return; + case Iop_Recps32Fx4: vex_printf("VRecps32Fx4"); return; + case Iop_Abs32Fx4: vex_printf("Abs32Fx4"); return; + case Iop_Rsqrts32Fx4: vex_printf("VRsqrts32Fx4"); return; + case Iop_Rsqrts32Fx2: vex_printf("VRsqrts32Fx2"); return; case Iop_RSqrt32Fx4: vex_printf("RSqrt32Fx4"); return; case Iop_RSqrt32F0x4: vex_printf("RSqrt32F0x4"); return; @@ -417,6 +582,7 @@ void ppIROp ( IROp op ) case Iop_Sqrt64F0x2: vex_printf("Sqrt64F0x2"); return; case Iop_Sub32Fx4: vex_printf("Sub32Fx4"); return; + case Iop_Sub32Fx2: vex_printf("Sub32Fx2"); return; case Iop_Sub32F0x4: vex_printf("Sub32F0x4"); return; case Iop_Sub64Fx2: vex_printf("Sub64Fx2"); return; case Iop_Sub64F0x2: vex_printf("Sub64F0x2"); return; @@ -431,6 +597,9 @@ void ppIROp ( IROp op ) case Iop_CmpLT64Fx2: vex_printf("CmpLT64Fx2"); return; case Iop_CmpLE64Fx2: vex_printf("CmpLE64Fx2"); return; case Iop_CmpUN64Fx2: vex_printf("CmpUN64Fx2"); return; + case Iop_CmpGT32Fx2: vex_printf("CmpGT32Fx2"); return; + case Iop_CmpEQ32Fx2: vex_printf("CmpEQ32Fx2"); return; + case Iop_CmpGE32Fx2: vex_printf("CmpGE32Fx2"); return; case Iop_CmpEQ32F0x4: vex_printf("CmpEQ32F0x4"); return; case Iop_CmpLT32F0x4: vex_printf("CmpLT32F0x4"); return; @@ -441,6 +610,9 @@ void ppIROp ( IROp op ) case Iop_CmpLE64F0x2: vex_printf("CmpLE64F0x2"); return; case Iop_CmpUN64F0x2: vex_printf("CmpUN64F0x2"); return; + case Iop_Neg32Fx4: vex_printf("Neg32Fx4"); return; + case Iop_Neg32Fx2: vex_printf("Neg32Fx2"); return; + case Iop_V128to64: vex_printf("V128to64"); return; case Iop_V128HIto64: vex_printf("V128HIto64"); return; case Iop_64HLtoV128: vex_printf("64HLtoV128"); return; @@ -455,6 +627,9 @@ void ppIROp ( IROp op ) case Iop_Dup8x16: vex_printf("Dup8x16"); return; case Iop_Dup16x8: vex_printf("Dup16x8"); return; case Iop_Dup32x4: vex_printf("Dup32x4"); return; + case Iop_Dup8x8: vex_printf("Dup8x8"); return; + case Iop_Dup16x4: vex_printf("Dup16x4"); return; + case Iop_Dup32x2: vex_printf("Dup32x2"); return; case Iop_NotV128: vex_printf("NotV128"); return; case Iop_AndV128: vex_printf("AndV128"); return; @@ -466,6 +641,10 @@ void ppIROp ( IROp op ) case Iop_CmpNEZ32x4: vex_printf("CmpNEZ32x4"); return; case Iop_CmpNEZ64x2: vex_printf("CmpNEZ64x2"); return; + case Iop_Abs8x16: vex_printf("Abs8x16"); return; + case Iop_Abs16x8: vex_printf("Abs16x8"); return; + case Iop_Abs32x4: vex_printf("Abs32x4"); return; + case Iop_Add8x16: vex_printf("Add8x16"); return; case Iop_Add16x8: vex_printf("Add16x8"); return; case Iop_Add32x4: vex_printf("Add32x4"); return; @@ -476,6 +655,17 @@ void ppIROp ( IROp op ) case Iop_QAdd8Sx16: vex_printf("QAdd8Sx16"); return; case Iop_QAdd16Sx8: vex_printf("QAdd16Sx8"); return; case Iop_QAdd32Sx4: vex_printf("QAdd32Sx4"); return; + case Iop_QAdd64Ux2: vex_printf("QAdd64Ux2"); return; + case Iop_QAdd64Sx2: vex_printf("QAdd64Sx2"); return; + case Iop_PwAdd8x16: vex_printf("PwAdd8x16"); return; + case Iop_PwAdd16x8: vex_printf("PwAdd16x8"); return; + case Iop_PwAdd32x4: vex_printf("PwAdd32x4"); return; + case Iop_PwAddL8Ux16: vex_printf("PwAddL8Ux16"); return; + case Iop_PwAddL16Ux8: vex_printf("PwAddL16Ux8"); return; + case Iop_PwAddL32Ux4: vex_printf("PwAddL32Ux4"); return; + case Iop_PwAddL8Sx16: vex_printf("PwAddL8Sx16"); return; + case Iop_PwAddL16Sx8: vex_printf("PwAddL16Sx8"); return; + case Iop_PwAddL32Sx4: vex_printf("PwAddL32Sx4"); return; case Iop_Sub8x16: vex_printf("Sub8x16"); return; case Iop_Sub16x8: vex_printf("Sub16x8"); return; @@ -487,12 +677,28 @@ void ppIROp ( IROp op ) case Iop_QSub8Sx16: vex_printf("QSub8Sx16"); return; case Iop_QSub16Sx8: vex_printf("QSub16Sx8"); return; case Iop_QSub32Sx4: vex_printf("QSub32Sx4"); return; + case Iop_QSub64Ux2: vex_printf("QSub64Ux2"); return; + case Iop_QSub64Sx2: vex_printf("QSub64Sx2"); return; + case Iop_Mul8x16: vex_printf("Mul8x16"); return; case Iop_Mul16x8: vex_printf("Mul16x8"); return; + case Iop_Mul32x4: vex_printf("Mul32x4"); return; + case Iop_Mull8Ux8: vex_printf("Mull8Ux8"); return; + case Iop_Mull8Sx8: vex_printf("Mull8Sx8"); return; + case Iop_Mull16Ux4: vex_printf("Mull16Ux4"); return; + case Iop_Mull16Sx4: vex_printf("Mull16Sx4"); return; + case Iop_Mull32Ux2: vex_printf("Mull32Ux2"); return; + case Iop_Mull32Sx2: vex_printf("Mull32Sx2"); return; + case Iop_PolynomialMul8x16: vex_printf("PolynomialMul8x16"); return; + case Iop_PolynomialMull8x8: vex_printf("PolynomialMull8x8"); return; case Iop_MulHi16Ux8: vex_printf("MulHi16Ux8"); return; case Iop_MulHi32Ux4: vex_printf("MulHi32Ux4"); return; case Iop_MulHi16Sx8: vex_printf("MulHi16Sx8"); return; case Iop_MulHi32Sx4: vex_printf("MulHi32Sx4"); return; + case Iop_QDMulHi16Sx8: vex_printf("QDMulHi16Sx8"); return; + case Iop_QDMulHi32Sx4: vex_printf("QDMulHi32Sx4"); return; + case Iop_QRDMulHi16Sx8: vex_printf("QRDMulHi16Sx8"); return; + case Iop_QRDMulHi32Sx4: vex_printf("QRDMulHi32Sx4"); return; case Iop_MullEven8Ux16: vex_printf("MullEven8Ux16"); return; case Iop_MullEven16Ux8: vex_printf("MullEven16Ux8"); return; @@ -526,10 +732,19 @@ void ppIROp ( IROp op ) case Iop_CmpGT8Sx16: vex_printf("CmpGT8Sx16"); return; case Iop_CmpGT16Sx8: vex_printf("CmpGT16Sx8"); return; case Iop_CmpGT32Sx4: vex_printf("CmpGT32Sx4"); return; + case Iop_CmpGT64Sx2: vex_printf("CmpGT64Sx2"); return; case Iop_CmpGT8Ux16: vex_printf("CmpGT8Ux16"); return; case Iop_CmpGT16Ux8: vex_printf("CmpGT16Ux8"); return; case Iop_CmpGT32Ux4: vex_printf("CmpGT32Ux4"); return; + case Iop_Cnt8x16: vex_printf("Cnt8x16"); return; + case Iop_Clz8Sx16: vex_printf("Clz8Sx16"); return; + case Iop_Clz16Sx8: vex_printf("Clz16Sx8"); return; + case Iop_Clz32Sx4: vex_printf("Clz32Sx4"); return; + case Iop_Cls8Sx16: vex_printf("Cls8Sx16"); return; + case Iop_Cls16Sx8: vex_printf("Cls16Sx8"); return; + case Iop_Cls32Sx4: vex_printf("Cls32Sx4"); return; + case Iop_ShlV128: vex_printf("ShlV128"); return; case Iop_ShrV128: vex_printf("ShrV128"); return; @@ -544,16 +759,44 @@ void ppIROp ( IROp op ) case Iop_SarN8x16: vex_printf("SarN8x16"); return; case Iop_SarN16x8: vex_printf("SarN16x8"); return; case Iop_SarN32x4: vex_printf("SarN32x4"); return; + case Iop_SarN64x2: vex_printf("SarN64x2"); return; case Iop_Shl8x16: vex_printf("Shl8x16"); return; case Iop_Shl16x8: vex_printf("Shl16x8"); return; case Iop_Shl32x4: vex_printf("Shl32x4"); return; + case Iop_Shl64x2: vex_printf("Shl64x2"); return; + case Iop_QSal8x16: vex_printf("QSal8x16"); return; + case Iop_QSal16x8: vex_printf("QSal16x8"); return; + case Iop_QSal32x4: vex_printf("QSal32x4"); return; + case Iop_QSal64x2: vex_printf("QSal64x2"); return; + case Iop_QShl8x16: vex_printf("QShl8x16"); return; + case Iop_QShl16x8: vex_printf("QShl16x8"); return; + case Iop_QShl32x4: vex_printf("QShl32x4"); return; + case Iop_QShl64x2: vex_printf("QShl64x2"); return; + case Iop_QSalN8x16: vex_printf("QSalN8x16"); return; + case Iop_QSalN16x8: vex_printf("QSalN16x8"); return; + case Iop_QSalN32x4: vex_printf("QSalN32x4"); return; + case Iop_QSalN64x2: vex_printf("QSalN64x2"); return; + case Iop_QShlN8x16: vex_printf("QShlN8x16"); return; + case Iop_QShlN16x8: vex_printf("QShlN16x8"); return; + case Iop_QShlN32x4: vex_printf("QShlN32x4"); return; + case Iop_QShlN64x2: vex_printf("QShlN64x2"); return; + case Iop_QShlN8Sx16: vex_printf("QShlN8Sx16"); return; + case Iop_QShlN16Sx8: vex_printf("QShlN16Sx8"); return; + case Iop_QShlN32Sx4: vex_printf("QShlN32Sx4"); return; + case Iop_QShlN64Sx2: vex_printf("QShlN64Sx2"); return; case Iop_Shr8x16: vex_printf("Shr8x16"); return; case Iop_Shr16x8: vex_printf("Shr16x8"); return; case Iop_Shr32x4: vex_printf("Shr32x4"); return; + case Iop_Shr64x2: vex_printf("Shr64x2"); return; case Iop_Sar8x16: vex_printf("Sar8x16"); return; case Iop_Sar16x8: vex_printf("Sar16x8"); return; case Iop_Sar32x4: vex_printf("Sar32x4"); return; + case Iop_Sar64x2: vex_printf("Sar64x2"); return; + case Iop_Sal8x16: vex_printf("Sal8x16"); return; + case Iop_Sal16x8: vex_printf("Sal16x8"); return; + case Iop_Sal32x4: vex_printf("Sal32x4"); return; + case Iop_Sal64x2: vex_printf("Sal64x2"); return; case Iop_Rol8x16: vex_printf("Rol8x16"); return; case Iop_Rol16x8: vex_printf("Rol16x8"); return; case Iop_Rol32x4: vex_printf("Rol32x4"); return; @@ -564,6 +807,24 @@ void ppIROp ( IROp op ) case Iop_QNarrow32Ux4: vex_printf("QNarrow32Ux4"); return; case Iop_QNarrow16Sx8: vex_printf("QNarrow16Sx8"); return; case Iop_QNarrow32Sx4: vex_printf("QNarrow32Sx4"); return; + case Iop_Shorten16x8: vex_printf("Shorten16x8"); return; + case Iop_Shorten32x4: vex_printf("Shorten32x4"); return; + case Iop_Shorten64x2: vex_printf("Shorten64x2"); return; + case Iop_QShortenU16Ux8: vex_printf("QShortenU16Ux8"); return; + case Iop_QShortenU32Ux4: vex_printf("QShortenU32Ux4"); return; + case Iop_QShortenU64Ux2: vex_printf("QShortenU64Ux2"); return; + case Iop_QShortenS16Sx8: vex_printf("QShortenS16Sx8"); return; + case Iop_QShortenS32Sx4: vex_printf("QShortenS32Sx4"); return; + case Iop_QShortenS64Sx2: vex_printf("QShortenS64Sx2"); return; + case Iop_QShortenU16Sx8: vex_printf("QShortenU16Sx8"); return; + case Iop_QShortenU32Sx4: vex_printf("QShortenU32Sx4"); return; + case Iop_QShortenU64Sx2: vex_printf("QShortenU64Sx2"); return; + case Iop_Longen8Ux8: vex_printf("Longen8Ux8"); return; + case Iop_Longen16Ux4: vex_printf("Longen16Ux4"); return; + case Iop_Longen32Ux2: vex_printf("Longen32Ux2"); return; + case Iop_Longen8Sx8: vex_printf("Longen8Sx8"); return; + case Iop_Longen16Sx4: vex_printf("Longen16Sx4"); return; + case Iop_Longen32Sx2: vex_printf("Longen32Sx2"); return; case Iop_InterleaveHI8x16: vex_printf("InterleaveHI8x16"); return; case Iop_InterleaveHI16x8: vex_printf("InterleaveHI16x8"); return; @@ -574,7 +835,51 @@ void ppIROp ( IROp op ) case Iop_InterleaveLO32x4: vex_printf("InterleaveLO32x4"); return; case Iop_InterleaveLO64x2: vex_printf("InterleaveLO64x2"); return; + case Iop_CatOddLanes8x16: vex_printf("CatOddLanes8x16"); return; + case Iop_CatOddLanes16x8: vex_printf("CatOddLanes16x8"); return; + case Iop_CatOddLanes32x4: vex_printf("CatOddLanes32x4"); return; + case Iop_CatEvenLanes8x16: vex_printf("CatEvenLanes8x16"); return; + case Iop_CatEvenLanes16x8: vex_printf("CatEvenLanes16x8"); return; + case Iop_CatEvenLanes32x4: vex_printf("CatEvenLanes32x4"); return; + + case Iop_InterleaveOddLanes8x16: vex_printf("InterleaveOddLanes8x16"); return; + case Iop_InterleaveOddLanes16x8: vex_printf("InterleaveOddLanes16x8"); return; + case Iop_InterleaveOddLanes32x4: vex_printf("InterleaveOddLanes32x4"); return; + case Iop_InterleaveEvenLanes8x16: vex_printf("InterleaveEvenLanes8x16"); return; + case Iop_InterleaveEvenLanes16x8: vex_printf("InterleaveEvenLanes16x8"); return; + case Iop_InterleaveEvenLanes32x4: vex_printf("InterleaveEvenLanes32x4"); return; + + case Iop_GetElem8x16: vex_printf("GetElem8x16"); return; + case Iop_GetElem16x8: vex_printf("GetElem16x8"); return; + case Iop_GetElem32x4: vex_printf("GetElem32x4"); return; + case Iop_GetElem64x2: vex_printf("GetElem64x2"); return; + + case Iop_GetElem8x8: vex_printf("GetElem8x8"); return; + case Iop_GetElem16x4: vex_printf("GetElem16x4"); return; + case Iop_GetElem32x2: vex_printf("GetElem32x2"); return; + case Iop_SetElem8x8: vex_printf("SetElem8x8"); return; + case Iop_SetElem16x4: vex_printf("SetElem16x4"); return; + case Iop_SetElem32x2: vex_printf("SetElem32x2"); return; + + case Iop_Extract64: vex_printf("Extract64"); return; + case Iop_ExtractV128: vex_printf("ExtractV128"); return; + case Iop_Perm8x16: vex_printf("Perm8x16"); return; + case Iop_Reverse16_8x16: vex_printf("Reverse16_8x16"); return; + case Iop_Reverse32_8x16: vex_printf("Reverse32_8x16"); return; + case Iop_Reverse32_16x8: vex_printf("Reverse32_16x8"); return; + case Iop_Reverse64_8x16: vex_printf("Reverse64_8x16"); return; + case Iop_Reverse64_16x8: vex_printf("Reverse64_16x8"); return; + case Iop_Reverse64_32x4: vex_printf("Reverse64_32x4"); return; + + case Iop_F32ToFixed32Ux4_RZ: vex_printf("F32ToFixed32Ux4_RZ"); return; + case Iop_F32ToFixed32Sx4_RZ: vex_printf("F32ToFixed32Sx4_RZ"); return; + case Iop_Fixed32UToF32x4_RN: vex_printf("Fixed32UToF32x4_RN"); return; + case Iop_Fixed32SToF32x4_RN: vex_printf("Fixed32SToF32x4_RN"); return; + case Iop_F32ToFixed32Ux2_RZ: vex_printf("F32ToFixed32Ux2_RZ"); return; + case Iop_F32ToFixed32Sx2_RZ: vex_printf("F32ToFixed32Sx2_RZ"); return; + case Iop_Fixed32UToF32x2_RN: vex_printf("Fixed32UToF32x2_RN"); return; + case Iop_Fixed32SToF32x2_RN: vex_printf("Fixed32SToF32x2_RN"); return; default: vpanic("ppIROp(1)"); } @@ -648,8 +953,7 @@ void ppIRExpr ( IRExpr* e ) vex_printf( ")" ); break; case Iex_Load: - vex_printf( "LD%s%s:", e->Iex.Load.end==Iend_LE ? "le" : "be", - e->Iex.Load.isLL ? "-LL" : "" ); + vex_printf( "LD%s:", e->Iex.Load.end==Iend_LE ? "le" : "be" ); ppIRType(e->Iex.Load.ty); vex_printf( "(" ); ppIRExpr(e->Iex.Load.addr); @@ -829,20 +1133,31 @@ void ppIRStmt ( IRStmt* s ) ppIRExpr(s->Ist.WrTmp.data); break; case Ist_Store: - if (s->Ist.Store.resSC != IRTemp_INVALID) { - ppIRTemp(s->Ist.Store.resSC); - vex_printf( " = SC( " ); - } vex_printf( "ST%s(", s->Ist.Store.end==Iend_LE ? "le" : "be" ); ppIRExpr(s->Ist.Store.addr); vex_printf( ") = "); ppIRExpr(s->Ist.Store.data); - if (s->Ist.Store.resSC != IRTemp_INVALID) - vex_printf( " )" ); break; case Ist_CAS: ppIRCAS(s->Ist.CAS.details); break; + case Ist_LLSC: + if (s->Ist.LLSC.storedata == NULL) { + ppIRTemp(s->Ist.LLSC.result); + vex_printf(" = LD%s-Linked(", + s->Ist.LLSC.end==Iend_LE ? "le" : "be"); + ppIRExpr(s->Ist.LLSC.addr); + vex_printf(")"); + } else { + ppIRTemp(s->Ist.LLSC.result); + vex_printf(" = ( ST%s-Cond(", + s->Ist.LLSC.end==Iend_LE ? "le" : "be"); + ppIRExpr(s->Ist.LLSC.addr); + vex_printf(") = "); + ppIRExpr(s->Ist.LLSC.storedata); + vex_printf(" )"); + } + break; case Ist_Dirty: ppIRDirty(s->Ist.Dirty.details); break; @@ -1061,10 +1376,9 @@ IRExpr* IRExpr_Unop ( IROp op, IRExpr* arg ) { e->Iex.Unop.arg = arg; return e; } -IRExpr* IRExpr_Load ( Bool isLL, IREndness end, IRType ty, IRExpr* addr ) { +IRExpr* IRExpr_Load ( IREndness end, IRType ty, IRExpr* addr ) { IRExpr* e = LibVEX_Alloc(sizeof(IRExpr)); e->tag = Iex_Load; - e->Iex.Load.isLL = isLL; e->Iex.Load.end = end; e->Iex.Load.ty = ty; e->Iex.Load.addr = addr; @@ -1171,6 +1485,21 @@ IRExpr** mkIRExprVec_7 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3, vec[7] = NULL; return vec; } +IRExpr** mkIRExprVec_8 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3, + IRExpr* arg4, IRExpr* arg5, IRExpr* arg6, + IRExpr* arg7, IRExpr* arg8 ) { + IRExpr** vec = LibVEX_Alloc(9 * sizeof(IRExpr*)); + vec[0] = arg1; + vec[1] = arg2; + vec[2] = arg3; + vec[3] = arg4; + vec[4] = arg5; + vec[5] = arg6; + vec[6] = arg7; + vec[7] = arg8; + vec[8] = NULL; + return vec; +} /* Constructors -- IRDirty */ @@ -1257,14 +1586,12 @@ IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data ) { s->Ist.WrTmp.data = data; return s; } -IRStmt* IRStmt_Store ( IREndness end, - IRTemp resSC, IRExpr* addr, IRExpr* data ) { - IRStmt* s = LibVEX_Alloc(sizeof(IRStmt)); - s->tag = Ist_Store; - s->Ist.Store.end = end; - s->Ist.Store.resSC = resSC; - s->Ist.Store.addr = addr; - s->Ist.Store.data = data; +IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data ) { + IRStmt* s = LibVEX_Alloc(sizeof(IRStmt)); + s->tag = Ist_Store; + s->Ist.Store.end = end; + s->Ist.Store.addr = addr; + s->Ist.Store.data = data; vassert(end == Iend_LE || end == Iend_BE); return s; } @@ -1274,6 +1601,16 @@ IRStmt* IRStmt_CAS ( IRCAS* cas ) { s->Ist.CAS.details = cas; return s; } +IRStmt* IRStmt_LLSC ( IREndness end, + IRTemp result, IRExpr* addr, IRExpr* storedata ) { + IRStmt* s = LibVEX_Alloc(sizeof(IRStmt)); + s->tag = Ist_LLSC; + s->Ist.LLSC.end = end; + s->Ist.LLSC.result = result; + s->Ist.LLSC.addr = addr; + s->Ist.LLSC.storedata = storedata; + return s; +} IRStmt* IRStmt_Dirty ( IRDirty* d ) { IRStmt* s = LibVEX_Alloc(sizeof(IRStmt)); @@ -1418,8 +1755,7 @@ IRExpr* deepCopyIRExpr ( IRExpr* e ) return IRExpr_Unop(e->Iex.Unop.op, deepCopyIRExpr(e->Iex.Unop.arg)); case Iex_Load: - return IRExpr_Load(e->Iex.Load.isLL, - e->Iex.Load.end, + return IRExpr_Load(e->Iex.Load.end, e->Iex.Load.ty, deepCopyIRExpr(e->Iex.Load.addr)); case Iex_Const: @@ -1490,11 +1826,17 @@ IRStmt* deepCopyIRStmt ( IRStmt* s ) deepCopyIRExpr(s->Ist.WrTmp.data)); case Ist_Store: return IRStmt_Store(s->Ist.Store.end, - s->Ist.Store.resSC, deepCopyIRExpr(s->Ist.Store.addr), deepCopyIRExpr(s->Ist.Store.data)); case Ist_CAS: return IRStmt_CAS(deepCopyIRCAS(s->Ist.CAS.details)); + case Ist_LLSC: + return IRStmt_LLSC(s->Ist.LLSC.end, + s->Ist.LLSC.result, + deepCopyIRExpr(s->Ist.LLSC.addr), + s->Ist.LLSC.storedata + ? deepCopyIRExpr(s->Ist.LLSC.storedata) + : NULL); case Ist_Dirty: return IRStmt_Dirty(deepCopyIRDirty(s->Ist.Dirty.details)); case Ist_MBE: @@ -1593,6 +1935,17 @@ void typeOfPrimop ( IROp op, case Iop_Add32: case Iop_Sub32: case Iop_Mul32: case Iop_Or32: case Iop_And32: case Iop_Xor32: case Iop_Max32U: + case Iop_Add16x2: case Iop_Sub16x2: + case Iop_QAdd16Sx2: case Iop_QAdd16Ux2: + case Iop_QSub16Sx2: case Iop_QSub16Ux2: + case Iop_HAdd16Ux2: case Iop_HAdd16Sx2: + case Iop_HSub16Ux2: case Iop_HSub16Sx2: + case Iop_Add8x4: case Iop_Sub8x4: + case Iop_QAdd8Sx4: case Iop_QAdd8Ux4: + case Iop_QSub8Sx4: case Iop_QSub8Ux4: + case Iop_HAdd8Ux4: case Iop_HAdd8Sx4: + case Iop_HSub8Ux4: case Iop_HSub8Sx4: + case Iop_Sad8Ux4: BINARY(Ity_I32,Ity_I32, Ity_I32); case Iop_Add64: case Iop_Sub64: case Iop_Mul64: @@ -1601,29 +1954,67 @@ void typeOfPrimop ( IROp op, case Iop_CmpORD64S: case Iop_Avg8Ux8: case Iop_Avg16Ux4: case Iop_Add8x8: case Iop_Add16x4: case Iop_Add32x2: + case Iop_Add32Fx2: case Iop_Sub32Fx2: case Iop_CmpEQ8x8: case Iop_CmpEQ16x4: case Iop_CmpEQ32x2: case Iop_CmpGT8Sx8: case Iop_CmpGT16Sx4: case Iop_CmpGT32Sx2: + case Iop_CmpGT8Ux8: case Iop_CmpGT16Ux4: case Iop_CmpGT32Ux2: + case Iop_CmpGT32Fx2: case Iop_CmpEQ32Fx2: case Iop_CmpGE32Fx2: case Iop_InterleaveHI8x8: case Iop_InterleaveLO8x8: case Iop_InterleaveHI16x4: case Iop_InterleaveLO16x4: case Iop_InterleaveHI32x2: case Iop_InterleaveLO32x2: + case Iop_CatOddLanes8x8: case Iop_CatEvenLanes8x8: case Iop_CatOddLanes16x4: case Iop_CatEvenLanes16x4: + case Iop_InterleaveOddLanes8x8: case Iop_InterleaveEvenLanes8x8: + case Iop_InterleaveOddLanes16x4: case Iop_InterleaveEvenLanes16x4: case Iop_Perm8x8: - case Iop_Max8Ux8: case Iop_Max16Sx4: - case Iop_Min8Ux8: case Iop_Min16Sx4: - case Iop_Mul16x4: case Iop_Mul32x2: + case Iop_Max8Ux8: case Iop_Max16Ux4: case Iop_Max32Ux2: + case Iop_Max8Sx8: case Iop_Max16Sx4: case Iop_Max32Sx2: + case Iop_Max32Fx2: case Iop_Min32Fx2: + case Iop_PwMax32Fx2: case Iop_PwMin32Fx2: + case Iop_Min8Ux8: case Iop_Min16Ux4: case Iop_Min32Ux2: + case Iop_Min8Sx8: case Iop_Min16Sx4: case Iop_Min32Sx2: + case Iop_PwMax8Ux8: case Iop_PwMax16Ux4: case Iop_PwMax32Ux2: + case Iop_PwMax8Sx8: case Iop_PwMax16Sx4: case Iop_PwMax32Sx2: + case Iop_PwMin8Ux8: case Iop_PwMin16Ux4: case Iop_PwMin32Ux2: + case Iop_PwMin8Sx8: case Iop_PwMin16Sx4: case Iop_PwMin32Sx2: + case Iop_Mul8x8: case Iop_Mul16x4: case Iop_Mul32x2: + case Iop_Mul32Fx2: + case Iop_PolynomialMul8x8: case Iop_MulHi16Sx4: case Iop_MulHi16Ux4: + case Iop_QDMulHi16Sx4: case Iop_QDMulHi32Sx2: + case Iop_QRDMulHi16Sx4: case Iop_QRDMulHi32Sx2: case Iop_QAdd8Sx8: case Iop_QAdd16Sx4: + case Iop_QAdd32Sx2: case Iop_QAdd64Sx1: case Iop_QAdd8Ux8: case Iop_QAdd16Ux4: + case Iop_QAdd32Ux2: case Iop_QAdd64Ux1: + case Iop_PwAdd8x8: case Iop_PwAdd16x4: case Iop_PwAdd32x2: + case Iop_PwAdd32Fx2: case Iop_QNarrow32Sx2: case Iop_QNarrow16Sx4: case Iop_QNarrow16Ux4: case Iop_Sub8x8: case Iop_Sub16x4: case Iop_Sub32x2: case Iop_QSub8Sx8: case Iop_QSub16Sx4: + case Iop_QSub32Sx2: case Iop_QSub64Sx1: case Iop_QSub8Ux8: case Iop_QSub16Ux4: + case Iop_QSub32Ux2: case Iop_QSub64Ux1: + case Iop_Shl8x8: case Iop_Shl16x4: case Iop_Shl32x2: + case Iop_Shr8x8: case Iop_Shr16x4: case Iop_Shr32x2: + case Iop_Sar8x8: case Iop_Sar16x4: case Iop_Sar32x2: + case Iop_Sal8x8: case Iop_Sal16x4: case Iop_Sal32x2: case Iop_Sal64x1: + case Iop_QShl8x8: case Iop_QShl16x4: case Iop_QShl32x2: case Iop_QShl64x1: + case Iop_QSal8x8: case Iop_QSal16x4: case Iop_QSal32x2: case Iop_QSal64x1: + case Iop_Recps32Fx2: + case Iop_Rsqrts32Fx2: BINARY(Ity_I64,Ity_I64, Ity_I64); case Iop_ShlN32x2: case Iop_ShlN16x4: case Iop_ShlN8x8: - case Iop_ShrN32x2: case Iop_ShrN16x4: + case Iop_ShrN32x2: case Iop_ShrN16x4: case Iop_ShrN8x8: case Iop_SarN32x2: case Iop_SarN16x4: case Iop_SarN8x8: + case Iop_QShlN8x8: case Iop_QShlN16x4: + case Iop_QShlN32x2: case Iop_QShlN64x1: + case Iop_QShlN8Sx8: case Iop_QShlN16Sx4: + case Iop_QShlN32Sx2: case Iop_QShlN64Sx1: + case Iop_QSalN8x8: case Iop_QSalN16x4: + case Iop_QSalN32x2: case Iop_QSalN64x1: BINARY(Ity_I64,Ity_I8, Ity_I64); case Iop_Shl8: case Iop_Shr8: case Iop_Sar8: @@ -1640,10 +2031,27 @@ void typeOfPrimop ( IROp op, case Iop_Not16: UNARY(Ity_I16, Ity_I16); case Iop_Not32: + case Iop_CmpNEZ16x2: case Iop_CmpNEZ8x4: UNARY(Ity_I32, Ity_I32); case Iop_Not64: case Iop_CmpNEZ32x2: case Iop_CmpNEZ16x4: case Iop_CmpNEZ8x8: + case Iop_Cnt8x8: + case Iop_Clz8Sx8: case Iop_Clz16Sx4: case Iop_Clz32Sx2: + case Iop_Cls8Sx8: case Iop_Cls16Sx4: case Iop_Cls32Sx2: + case Iop_PwAddL8Ux8: case Iop_PwAddL16Ux4: case Iop_PwAddL32Ux2: + case Iop_PwAddL8Sx8: case Iop_PwAddL16Sx4: case Iop_PwAddL32Sx2: + case Iop_Reverse64_8x8: case Iop_Reverse64_16x4: case Iop_Reverse64_32x2: + case Iop_Reverse32_8x8: case Iop_Reverse32_16x4: + case Iop_Reverse16_8x8: + case Iop_FtoI32Sx2_RZ: case Iop_FtoI32Ux2_RZ: + case Iop_I32StoFx2: case Iop_I32UtoFx2: + case Iop_Recip32x2: case Iop_Recip32Fx2: + case Iop_Abs32Fx2: + case Iop_Rsqrte32Fx2: + case Iop_Rsqrte32x2: + case Iop_Neg32Fx2: + case Iop_Abs8x8: case Iop_Abs16x4: case Iop_Abs32x2: UNARY(Ity_I64, Ity_I64); case Iop_CmpEQ8: case Iop_CmpNE8: @@ -1758,23 +2166,38 @@ void typeOfPrimop ( IROp op, case Iop_MulF64r32: case Iop_DivF64r32: TERNARY(ity_RMode,Ity_F64,Ity_F64, Ity_F64); + case Iop_AddF32: case Iop_SubF32: + case Iop_MulF32: case Iop_DivF32: + TERNARY(ity_RMode,Ity_F32,Ity_F32, Ity_F32); + case Iop_NegF64: case Iop_AbsF64: UNARY(Ity_F64, Ity_F64); + case Iop_NegF32: case Iop_AbsF32: + UNARY(Ity_F32, Ity_F32); + case Iop_SqrtF64: case Iop_SqrtF64r32: BINARY(ity_RMode,Ity_F64, Ity_F64); + case Iop_SqrtF32: + case Iop_RoundF32toInt: + BINARY(ity_RMode,Ity_F32, Ity_F32); + case Iop_CmpF64: BINARY(Ity_F64,Ity_F64, Ity_I32); - case Iop_F64toI16: BINARY(ity_RMode,Ity_F64, Ity_I16); - case Iop_F64toI32: BINARY(ity_RMode,Ity_F64, Ity_I32); - case Iop_F64toI64: BINARY(ity_RMode,Ity_F64, Ity_I64); + case Iop_F64toI16S: BINARY(ity_RMode,Ity_F64, Ity_I16); + case Iop_F64toI32S: BINARY(ity_RMode,Ity_F64, Ity_I32); + case Iop_F64toI64S: BINARY(ity_RMode,Ity_F64, Ity_I64); + + case Iop_F64toI32U: BINARY(ity_RMode,Ity_F64, Ity_I32); - case Iop_I16toF64: UNARY(Ity_I16, Ity_F64); - case Iop_I32toF64: UNARY(Ity_I32, Ity_F64); - case Iop_I64toF64: BINARY(ity_RMode,Ity_I64, Ity_F64); + case Iop_I16StoF64: UNARY(Ity_I16, Ity_F64); + case Iop_I32StoF64: UNARY(Ity_I32, Ity_F64); + case Iop_I64StoF64: BINARY(ity_RMode,Ity_I64, Ity_F64); + + case Iop_I32UtoF64: UNARY(Ity_I32, Ity_F64); case Iop_F32toF64: UNARY(Ity_F32, Ity_F64); case Iop_F64toF32: BINARY(ity_RMode,Ity_F64, Ity_F32); @@ -1814,16 +2237,31 @@ void typeOfPrimop ( IROp op, case Iop_I32StoFx4: case Iop_QFtoI32Ux4_RZ: case Iop_QFtoI32Sx4_RZ: + case Iop_FtoI32Ux4_RZ: + case Iop_FtoI32Sx4_RZ: case Iop_RoundF32x4_RM: case Iop_RoundF32x4_RP: case Iop_RoundF32x4_RN: case Iop_RoundF32x4_RZ: + case Iop_Abs32Fx4: + case Iop_Rsqrte32Fx4: + case Iop_Rsqrte32x4: UNARY(Ity_V128, Ity_V128); case Iop_64HLtoV128: BINARY(Ity_I64,Ity_I64, Ity_V128); - case Iop_V128to64: case Iop_V128HIto64: + case Iop_V128to64: case Iop_V128HIto64: + case Iop_Shorten16x8: case Iop_Shorten32x4: case Iop_Shorten64x2: + case Iop_QShortenU16Ux8: case Iop_QShortenU32Ux4: case Iop_QShortenU64Ux2: + case Iop_QShortenS16Sx8: case Iop_QShortenS32Sx4: case Iop_QShortenS64Sx2: + case Iop_QShortenU16Sx8: case Iop_QShortenU32Sx4: case Iop_QShortenU64Sx2: + case Iop_F32toF16x4: UNARY(Ity_V128, Ity_I64); + case Iop_Longen8Ux8: case Iop_Longen16Ux4: case Iop_Longen32Ux2: + case Iop_Longen8Sx8: case Iop_Longen16Sx4: case Iop_Longen32Sx2: + case Iop_F16toF32x4: + UNARY(Ity_I64, Ity_V128); + case Iop_V128to32: UNARY(Ity_V128, Ity_I32); case Iop_32UtoV128: UNARY(Ity_I32, Ity_V128); case Iop_64UtoV128: UNARY(Ity_I64, Ity_V128); @@ -1833,6 +2271,9 @@ void typeOfPrimop ( IROp op, case Iop_Dup8x16: UNARY(Ity_I8, Ity_V128); case Iop_Dup16x8: UNARY(Ity_I16, Ity_V128); case Iop_Dup32x4: UNARY(Ity_I32, Ity_V128); + case Iop_Dup8x8: UNARY(Ity_I8, Ity_I64); + case Iop_Dup16x4: UNARY(Ity_I16, Ity_I64); + case Iop_Dup32x2: UNARY(Ity_I32, Ity_I64); case Iop_CmpEQ32Fx4: case Iop_CmpLT32Fx4: case Iop_CmpEQ64Fx2: case Iop_CmpLT64Fx2: @@ -1848,6 +2289,7 @@ void typeOfPrimop ( IROp op, case Iop_Div32Fx4: case Iop_Div32F0x4: case Iop_Div64Fx2: case Iop_Div64F0x2: case Iop_Max32Fx4: case Iop_Max32F0x4: + case Iop_PwMax32Fx4: case Iop_PwMin32Fx4: case Iop_Max64Fx2: case Iop_Max64F0x2: case Iop_Min32Fx4: case Iop_Min32F0x4: case Iop_Min64Fx2: case Iop_Min64F0x2: @@ -1858,15 +2300,23 @@ void typeOfPrimop ( IROp op, case Iop_AndV128: case Iop_OrV128: case Iop_XorV128: case Iop_Add8x16: case Iop_Add16x8: case Iop_Add32x4: case Iop_Add64x2: - case Iop_QAdd8Ux16: case Iop_QAdd16Ux8: case Iop_QAdd32Ux4: - case Iop_QAdd8Sx16: case Iop_QAdd16Sx8: case Iop_QAdd32Sx4: + case Iop_QAdd8Ux16: case Iop_QAdd16Ux8: + case Iop_QAdd32Ux4: //case Iop_QAdd64Ux2: + case Iop_QAdd8Sx16: case Iop_QAdd16Sx8: + case Iop_QAdd32Sx4: case Iop_QAdd64Sx2: + case Iop_PwAdd8x16: case Iop_PwAdd16x8: case Iop_PwAdd32x4: case Iop_Sub8x16: case Iop_Sub16x8: case Iop_Sub32x4: case Iop_Sub64x2: - case Iop_QSub8Ux16: case Iop_QSub16Ux8: case Iop_QSub32Ux4: - case Iop_QSub8Sx16: case Iop_QSub16Sx8: case Iop_QSub32Sx4: - case Iop_Mul16x8: + case Iop_QSub8Ux16: case Iop_QSub16Ux8: + case Iop_QSub32Ux4: //case Iop_QSub64Ux2: + case Iop_QSub8Sx16: case Iop_QSub16Sx8: + case Iop_QSub32Sx4: case Iop_QSub64Sx2: + case Iop_Mul8x16: case Iop_Mul16x8: case Iop_Mul32x4: + case Iop_PolynomialMul8x16: case Iop_MulHi16Ux8: case Iop_MulHi32Ux4: case Iop_MulHi16Sx8: case Iop_MulHi32Sx4: + case Iop_QDMulHi16Sx8: case Iop_QDMulHi32Sx4: + case Iop_QRDMulHi16Sx8: case Iop_QRDMulHi32Sx4: case Iop_MullEven8Ux16: case Iop_MullEven16Ux8: case Iop_MullEven8Sx16: case Iop_MullEven16Sx8: case Iop_Avg8Ux16: case Iop_Avg16Ux8: case Iop_Avg32Ux4: @@ -1877,23 +2327,42 @@ void typeOfPrimop ( IROp op, case Iop_Min8Ux16: case Iop_Min16Ux8: case Iop_Min32Ux4: case Iop_CmpEQ8x16: case Iop_CmpEQ16x8: case Iop_CmpEQ32x4: case Iop_CmpGT8Sx16: case Iop_CmpGT16Sx8: case Iop_CmpGT32Sx4: + case Iop_CmpGT64Sx2: case Iop_CmpGT8Ux16: case Iop_CmpGT16Ux8: case Iop_CmpGT32Ux4: - case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4: - case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4: - case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4: + case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4: case Iop_Shl64x2: + case Iop_QShl8x16: case Iop_QShl16x8: case Iop_QShl32x4: case Iop_QShl64x2: + case Iop_QSal8x16: case Iop_QSal16x8: case Iop_QSal32x4: case Iop_QSal64x2: + case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4: case Iop_Shr64x2: + case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4: case Iop_Sar64x2: + case Iop_Sal8x16: case Iop_Sal16x8: case Iop_Sal32x4: case Iop_Sal64x2: case Iop_Rol8x16: case Iop_Rol16x8: case Iop_Rol32x4: case Iop_QNarrow16Ux8: case Iop_QNarrow32Ux4: case Iop_QNarrow16Sx8: case Iop_QNarrow32Sx4: case Iop_Narrow16x8: case Iop_Narrow32x4: case Iop_InterleaveHI8x16: case Iop_InterleaveHI16x8: case Iop_InterleaveHI32x4: case Iop_InterleaveHI64x2: - case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8: + case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8: case Iop_InterleaveLO32x4: case Iop_InterleaveLO64x2: + case Iop_CatOddLanes8x16: case Iop_CatEvenLanes8x16: + case Iop_CatOddLanes16x8: case Iop_CatEvenLanes16x8: + case Iop_CatOddLanes32x4: case Iop_CatEvenLanes32x4: + case Iop_InterleaveOddLanes8x16: case Iop_InterleaveEvenLanes8x16: + case Iop_InterleaveOddLanes16x8: case Iop_InterleaveEvenLanes16x8: + case Iop_InterleaveOddLanes32x4: case Iop_InterleaveEvenLanes32x4: case Iop_Perm8x16: + case Iop_Recps32Fx4: + case Iop_Rsqrts32Fx4: BINARY(Ity_V128,Ity_V128, Ity_V128); + case Iop_PolynomialMull8x8: + case Iop_Mull8Ux8: case Iop_Mull8Sx8: + case Iop_Mull16Ux4: case Iop_Mull16Sx4: + case Iop_Mull32Ux2: case Iop_Mull32Sx2: + BINARY(Ity_I64, Ity_I64, Ity_V128); + case Iop_NotV128: case Iop_Recip32Fx4: case Iop_Recip32F0x4: + case Iop_Recip32x4: case Iop_Recip64Fx2: case Iop_Recip64F0x2: case Iop_RSqrt32Fx4: case Iop_RSqrt32F0x4: case Iop_RSqrt64Fx2: case Iop_RSqrt64F0x2: @@ -1901,6 +2370,16 @@ void typeOfPrimop ( IROp op, case Iop_Sqrt64Fx2: case Iop_Sqrt64F0x2: case Iop_CmpNEZ8x16: case Iop_CmpNEZ16x8: case Iop_CmpNEZ32x4: case Iop_CmpNEZ64x2: + case Iop_Cnt8x16: + case Iop_Clz8Sx16: case Iop_Clz16Sx8: case Iop_Clz32Sx4: + case Iop_Cls8Sx16: case Iop_Cls16Sx8: case Iop_Cls32Sx4: + case Iop_PwAddL8Ux16: case Iop_PwAddL16Ux8: case Iop_PwAddL32Ux4: + case Iop_PwAddL8Sx16: case Iop_PwAddL16Sx8: case Iop_PwAddL32Sx4: + case Iop_Reverse64_8x16: case Iop_Reverse64_16x8: case Iop_Reverse64_32x4: + case Iop_Reverse32_8x16: case Iop_Reverse32_16x8: + case Iop_Reverse16_8x16: + case Iop_Neg32Fx4: + case Iop_Abs8x16: case Iop_Abs16x8: case Iop_Abs32x4: UNARY(Ity_V128, Ity_V128); case Iop_ShlV128: case Iop_ShrV128: @@ -1908,9 +2387,57 @@ void typeOfPrimop ( IROp op, case Iop_ShlN32x4: case Iop_ShlN64x2: case Iop_ShrN8x16: case Iop_ShrN16x8: case Iop_ShrN32x4: case Iop_ShrN64x2: - case Iop_SarN8x16: case Iop_SarN16x8: case Iop_SarN32x4: + case Iop_SarN8x16: case Iop_SarN16x8: + case Iop_SarN32x4: case Iop_SarN64x2: + case Iop_QShlN8x16: case Iop_QShlN16x8: + case Iop_QShlN32x4: case Iop_QShlN64x2: + case Iop_QShlN8Sx16: case Iop_QShlN16Sx8: + case Iop_QShlN32Sx4: case Iop_QShlN64Sx2: + case Iop_QSalN8x16: case Iop_QSalN16x8: + case Iop_QSalN32x4: case Iop_QSalN64x2: BINARY(Ity_V128,Ity_I8, Ity_V128); + case Iop_F32ToFixed32Ux4_RZ: + case Iop_F32ToFixed32Sx4_RZ: + case Iop_Fixed32UToF32x4_RN: + case Iop_Fixed32SToF32x4_RN: + BINARY(Ity_V128, Ity_I8, Ity_V128); + + case Iop_F32ToFixed32Ux2_RZ: + case Iop_F32ToFixed32Sx2_RZ: + case Iop_Fixed32UToF32x2_RN: + case Iop_Fixed32SToF32x2_RN: + BINARY(Ity_I64, Ity_I8, Ity_I64); + + case Iop_GetElem8x16: + BINARY(Ity_V128, Ity_I8, Ity_I8); + case Iop_GetElem16x8: + BINARY(Ity_V128, Ity_I8, Ity_I16); + case Iop_GetElem32x4: + BINARY(Ity_V128, Ity_I8, Ity_I32); + case Iop_GetElem64x2: + BINARY(Ity_V128, Ity_I8, Ity_I64); + case Iop_GetElem8x8: + BINARY(Ity_I64, Ity_I8, Ity_I8); + case Iop_GetElem16x4: + BINARY(Ity_I64, Ity_I8, Ity_I16); + case Iop_GetElem32x2: + BINARY(Ity_I64, Ity_I8, Ity_I32); + case Iop_SetElem8x8: + TERNARY(Ity_I64, Ity_I8, Ity_I8, Ity_I64); + case Iop_SetElem16x4: + TERNARY(Ity_I64, Ity_I8, Ity_I16, Ity_I64); + case Iop_SetElem32x2: + TERNARY(Ity_I64, Ity_I8, Ity_I32, Ity_I64); + + case Iop_Extract64: + TERNARY(Ity_I64, Ity_I64, Ity_I8, Ity_I64); + case Iop_ExtractV128: + TERNARY(Ity_V128, Ity_V128, Ity_I8, Ity_V128); + + case Iop_QDMulLong16Sx4: case Iop_QDMulLong32Sx2: + BINARY(Ity_I64, Ity_I64, Ity_V128); + default: ppIROp(op); vpanic("typeOfPrimop"); @@ -2138,6 +2665,10 @@ Bool isFlatIRStmt ( IRStmt* st ) && isIRAtom(cas->expdLo) && (cas->dataHi ? isIRAtom(cas->dataHi) : True) && isIRAtom(cas->dataLo) ); + case Ist_LLSC: + return toBool( isIRAtom(st->Ist.LLSC.addr) + && (st->Ist.LLSC.storedata + ? isIRAtom(st->Ist.LLSC.storedata) : True) ); case Ist_Dirty: di = st->Ist.Dirty.details; if (!isIRAtom(di->guard)) @@ -2329,6 +2860,11 @@ void useBeforeDef_Stmt ( IRSB* bb, IRStmt* stmt, Int* def_counts ) useBeforeDef_Expr(bb,stmt,cas->dataHi,def_counts); useBeforeDef_Expr(bb,stmt,cas->dataLo,def_counts); break; + case Ist_LLSC: + useBeforeDef_Expr(bb,stmt,stmt->Ist.LLSC.addr,def_counts); + if (stmt->Ist.LLSC.storedata != NULL) + useBeforeDef_Expr(bb,stmt,stmt->Ist.LLSC.storedata,def_counts); + break; case Ist_Dirty: d = stmt->Ist.Dirty.details; for (i = 0; d->args[i] != NULL; i++) @@ -2606,9 +3142,6 @@ void tcStmt ( IRSB* bb, IRStmt* stmt, IRType gWordTy ) sanityCheckFail(bb,stmt,"IRStmt.Store.data: cannot Store :: Ity_I1"); if (stmt->Ist.Store.end != Iend_LE && stmt->Ist.Store.end != Iend_BE) sanityCheckFail(bb,stmt,"Ist.Store.end: bogus endianness"); - if (stmt->Ist.Store.resSC != IRTemp_INVALID - && typeOfIRTemp(tyenv, stmt->Ist.Store.resSC) != Ity_I1) - sanityCheckFail(bb,stmt,"Ist.Store.resSC: not :: Ity_I1"); break; case Ist_CAS: cas = stmt->Ist.CAS.details; @@ -2660,6 +3193,28 @@ void tcStmt ( IRSB* bb, IRStmt* stmt, IRType gWordTy ) bad_cas: sanityCheckFail(bb,stmt,"IRStmt.CAS: ill-formed"); break; + case Ist_LLSC: { + IRType tyRes; + if (typeOfIRExpr(tyenv, stmt->Ist.LLSC.addr) != gWordTy) + sanityCheckFail(bb,stmt,"IRStmt.LLSC.addr: not :: guest word type"); + if (stmt->Ist.LLSC.end != Iend_LE && stmt->Ist.LLSC.end != Iend_BE) + sanityCheckFail(bb,stmt,"Ist.LLSC.end: bogus endianness"); + tyRes = typeOfIRTemp(tyenv, stmt->Ist.LLSC.result); + if (stmt->Ist.LLSC.storedata == NULL) { + /* it's a LL */ + if (tyRes != Ity_I64 && tyRes != Ity_I32 && tyRes != Ity_I8) + sanityCheckFail(bb,stmt,"Ist.LLSC(LL).result :: bogus"); + } else { + /* it's a SC */ + if (tyRes != Ity_I1) + sanityCheckFail(bb,stmt,"Ist.LLSC(SC).result: not :: Ity_I1"); + tyData = typeOfIRExpr(tyenv, stmt->Ist.LLSC.storedata); + if (tyData != Ity_I64 && tyData != Ity_I32 && tyData != Ity_I8) + sanityCheckFail(bb,stmt, + "Ist.LLSC(SC).result :: storedata bogus"); + } + break; + } case Ist_Dirty: /* Mostly check for various kinds of ill-formed dirty calls. */ d = stmt->Ist.Dirty.details; @@ -2790,17 +3345,6 @@ void sanityCheckIRSB ( IRSB* bb, HChar* caller, "IRStmt.Tmp: destination tmp is assigned more than once"); break; case Ist_Store: - if (stmt->Ist.Store.resSC != IRTemp_INVALID) { - IRTemp resSC = stmt->Ist.Store.resSC; - if (resSC < 0 || resSC >= n_temps) - sanityCheckFail(bb, stmt, - "IRStmt.Store.resSC: destination tmp is out of range"); - def_counts[resSC]++; - if (def_counts[resSC] > 1) - sanityCheckFail(bb, stmt, - "IRStmt.Store.resSC: destination tmp " - "is assigned more than once"); - } break; case Ist_Dirty: if (stmt->Ist.Dirty.details->tmp != IRTemp_INVALID) { @@ -2816,7 +3360,6 @@ void sanityCheckIRSB ( IRSB* bb, HChar* caller, break; case Ist_CAS: cas = stmt->Ist.CAS.details; - if (cas->oldHi != IRTemp_INVALID) { if (cas->oldHi < 0 || cas->oldHi >= n_temps) sanityCheckFail(bb, stmt, @@ -2827,16 +3370,25 @@ void sanityCheckIRSB ( IRSB* bb, HChar* caller, "IRStmt.CAS: destination tmpHi is assigned more than once"); } if (cas->oldLo < 0 || cas->oldLo >= n_temps) - sanityCheckFail(bb, stmt, - "IRStmt.CAS: destination tmpLo is out of range"); - def_counts[cas->oldLo]++; - if (def_counts[cas->oldLo] > 1) - sanityCheckFail(bb, stmt, - "IRStmt.CAS: destination tmpLo is assigned more than once"); - break; + sanityCheckFail(bb, stmt, + "IRStmt.CAS: destination tmpLo is out of range"); + def_counts[cas->oldLo]++; + if (def_counts[cas->oldLo] > 1) + sanityCheckFail(bb, stmt, + "IRStmt.CAS: destination tmpLo is assigned more than once"); + break; + case Ist_LLSC: + if (stmt->Ist.LLSC.result < 0 || stmt->Ist.LLSC.result >= n_temps) + sanityCheckFail(bb, stmt, + "IRStmt.LLSC: destination tmp is out of range"); + def_counts[stmt->Ist.LLSC.result]++; + if (def_counts[stmt->Ist.LLSC.result] > 1) + sanityCheckFail(bb, stmt, + "IRStmt.LLSC: destination tmp is assigned more than once"); + break; default: - /* explicitly handle the rest, so as to keep gcc quiet */ - break; + /* explicitly handle the rest, so as to keep gcc quiet */ + break; } } @@ -2884,6 +3436,7 @@ Int sizeofIRType ( IRType ty ) case Ity_I16: return 2; case Ity_I32: return 4; case Ity_I64: return 8; + case Ity_I128: return 16; case Ity_F32: return 4; case Ity_F64: return 8; case Ity_V128: return 16; diff --git a/VEX/priv/ir_match.c b/VEX/priv/ir_match.c index 20a9f3c..fc32f2e 100644 --- a/VEX/priv/ir_match.c +++ b/VEX/priv/ir_match.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (ir_match.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin ir_match.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -90,7 +79,6 @@ Bool matchWrk ( MatchInfo* mi, IRExpr* p/*attern*/, IRExpr* e/*xpr*/ ) return True; case Iex_Load: if (e->tag != Iex_Load) return False; - if (p->Iex.Load.isLL != e->Iex.Load.isLL) return False; if (p->Iex.Load.end != e->Iex.Load.end) return False; if (p->Iex.Load.ty != e->Iex.Load.ty) return False; if (!matchWrk(mi, p->Iex.Load.addr, e->Iex.Load.addr)) diff --git a/VEX/priv/ir_match.h b/VEX/priv/ir_match.h index 7267968..5755505 100644 --- a/VEX/priv/ir_match.h +++ b/VEX/priv/ir_match.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (ir_match.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin ir_match.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c index 840b12d..4730680 100644 --- a/VEX/priv/ir_opt.c +++ b/VEX/priv/ir_opt.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (ir_opt.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin ir_opt.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -334,8 +323,7 @@ static IRExpr* flatten_Expr ( IRSB* bb, IRExpr* ex ) case Iex_Load: t1 = newIRTemp(bb->tyenv, ty); addStmtToIRSB(bb, IRStmt_WrTmp(t1, - IRExpr_Load(ex->Iex.Load.isLL, - ex->Iex.Load.end, + IRExpr_Load(ex->Iex.Load.end, ex->Iex.Load.ty, flatten_Expr(bb, ex->Iex.Load.addr)))); return IRExpr_RdTmp(t1); @@ -426,8 +414,7 @@ static void flatten_Stmt ( IRSB* bb, IRStmt* st ) case Ist_Store: e1 = flatten_Expr(bb, st->Ist.Store.addr); e2 = flatten_Expr(bb, st->Ist.Store.data); - addStmtToIRSB(bb, IRStmt_Store(st->Ist.Store.end, - st->Ist.Store.resSC, e1,e2)); + addStmtToIRSB(bb, IRStmt_Store(st->Ist.Store.end, e1,e2)); break; case Ist_CAS: cas = st->Ist.CAS.details; @@ -440,6 +427,14 @@ static void flatten_Stmt ( IRSB* bb, IRStmt* st ) e1, e2, e3, e4, e5 ); addStmtToIRSB(bb, IRStmt_CAS(cas2)); break; + case Ist_LLSC: + e1 = flatten_Expr(bb, st->Ist.LLSC.addr); + e2 = st->Ist.LLSC.storedata + ? flatten_Expr(bb, st->Ist.LLSC.storedata) + : NULL; + addStmtToIRSB(bb, IRStmt_LLSC(st->Ist.LLSC.end, + st->Ist.LLSC.result, e1, e2)); + break; case Ist_Dirty: d = st->Ist.Dirty.details; d2 = emptyIRDirty(); @@ -724,7 +719,7 @@ static void handle_gets_Stmt ( enough do a lot better if needed. */ /* Probably also overly-conservative, but also dump everything if we hit a memory bus event (fence, lock, unlock). Ditto - AbiHints and CASs. */ + AbiHints, CASs, LLs and SCs. */ case Ist_AbiHint: vassert(isIRAtom(st->Ist.AbiHint.base)); vassert(isIRAtom(st->Ist.AbiHint.nia)); @@ -732,6 +727,7 @@ static void handle_gets_Stmt ( case Ist_MBE: case Ist_Dirty: case Ist_CAS: + case Ist_LLSC: for (j = 0; j < env->used; j++) env->inuse[j] = False; break; @@ -897,6 +893,30 @@ static Bool sameIRTemps ( IRExpr* e1, IRExpr* e2 ) && e1->Iex.RdTmp.tmp == e2->Iex.RdTmp.tmp ); } +static Bool sameIcoU32s ( IRExpr* e1, IRExpr* e2 ) +{ + return toBool( e1->tag == Iex_Const + && e2->tag == Iex_Const + && e1->Iex.Const.con->tag == Ico_U32 + && e2->Iex.Const.con->tag == Ico_U32 + && e1->Iex.Const.con->Ico.U32 + == e2->Iex.Const.con->Ico.U32 ); +} + +/* Are both expressions either the same IRTemp or IRConst-U32s ? If + in doubt, say No. */ +static Bool sameIRTempsOrIcoU32s ( IRExpr* e1, IRExpr* e2 ) +{ + switch (e1->tag) { + case Iex_RdTmp: + return sameIRTemps(e1, e2); + case Iex_Const: + return sameIcoU32s(e1, e2); + default: + return False; + } +} + static Bool notBool ( Bool b ) { if (b == True) return False; @@ -906,15 +926,33 @@ static Bool notBool ( Bool b ) /* Make a zero which has the same type as the result of the given primop. */ -static IRExpr* mkZeroForXor ( IROp op ) +static IRExpr* mkZeroOfPrimopResultType ( IROp op ) { switch (op) { case Iop_Xor8: return IRExpr_Const(IRConst_U8(0)); case Iop_Xor16: return IRExpr_Const(IRConst_U16(0)); + case Iop_Sub32: case Iop_Xor32: return IRExpr_Const(IRConst_U32(0)); + case Iop_Sub64: case Iop_Xor64: return IRExpr_Const(IRConst_U64(0)); case Iop_XorV128: return IRExpr_Const(IRConst_V128(0)); - default: vpanic("mkZeroForXor: bad primop"); + default: vpanic("mkZeroOfPrimopResultType: bad primop"); + } +} + +/* Make a value containing all 1-bits, which has the same type as the + result of the given primop. */ +static IRExpr* mkOnesOfPrimopResultType ( IROp op ) +{ + switch (op) { + case Iop_CmpEQ64: + return IRExpr_Const(IRConst_U1(toBool(1))); + case Iop_CmpEQ8x8: + return IRExpr_Const(IRConst_U64(0xFFFFFFFFFFFFFFFFULL)); + case Iop_CmpEQ8x16: + return IRExpr_Const(IRConst_V128(0xFFFF)); + default: + vpanic("mkOnesOfPrimopResultType: bad primop"); } } @@ -1058,7 +1096,13 @@ static IRExpr* fold_Expr ( IRExpr* e ) 0xFFFFFFFFULL & e->Iex.Unop.arg->Iex.Const.con->Ico.U32)); break; - + case Iop_32Sto64: { + /* signed */ Long s64 = e->Iex.Unop.arg->Iex.Const.con->Ico.U32; + s64 <<= 32; + s64 >>= 32; + e2 = IRExpr_Const(IRConst_U64((ULong)s64)); + break; + } case Iop_CmpNEZ8: e2 = IRExpr_Const(IRConst_U1(toBool( 0 != @@ -1541,46 +1585,77 @@ static IRExpr* fold_Expr ( IRExpr* e ) e2 = e->Iex.Binop.arg2; } else - /* Or8/16/32/64(t,t) ==> t, for some IRTemp t */ + /* Or8/16/32/64/V128(t,t) ==> t, for some IRTemp t */ /* And8/16/32/64(t,t) ==> t, for some IRTemp t */ /* Max32U(t,t) ==> t, for some IRTemp t */ - if ( (e->Iex.Binop.op == Iop_And64 - || e->Iex.Binop.op == Iop_And32 - || e->Iex.Binop.op == Iop_And16 - || e->Iex.Binop.op == Iop_And8 - || e->Iex.Binop.op == Iop_Or64 - || e->Iex.Binop.op == Iop_Or32 - || e->Iex.Binop.op == Iop_Or16 - || e->Iex.Binop.op == Iop_Or8 - || e->Iex.Binop.op == Iop_Max32U) - && sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) { - e2 = e->Iex.Binop.arg1; + switch (e->Iex.Binop.op) { + case Iop_And64: case Iop_And32: + case Iop_And16: case Iop_And8: + case Iop_Or64: case Iop_Or32: + case Iop_Or16: case Iop_Or8: case Iop_OrV128: + case Iop_Max32U: + if (sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) + e2 = e->Iex.Binop.arg1; + break; + default: + break; } /* Xor8/16/32/64/V128(t,t) ==> 0, for some IRTemp t */ - if ( (e->Iex.Binop.op == Iop_Xor64 - || e->Iex.Binop.op == Iop_Xor32 - || e->Iex.Binop.op == Iop_Xor16 - || e->Iex.Binop.op == Iop_Xor8 - || e->Iex.Binop.op == Iop_XorV128) - && sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) { - e2 = mkZeroForXor(e->Iex.Binop.op); + /* Sub32/64(t,t) ==> 0, for some IRTemp t */ + switch (e->Iex.Binop.op) { + case Iop_Xor64: case Iop_Xor32: + case Iop_Xor16: case Iop_Xor8: + case Iop_XorV128: + case Iop_Sub64: case Iop_Sub32: + if (sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) + e2 = mkZeroOfPrimopResultType(e->Iex.Binop.op); + break; + default: + break; + } + + switch (e->Iex.Binop.op) { + case Iop_CmpEQ64: + case Iop_CmpEQ8x8: + case Iop_CmpEQ8x16: + if (sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) + e2 = mkOnesOfPrimopResultType(e->Iex.Binop.op); + break; + default: + break; } } } /* Mux0X */ - if (e->tag == Iex_Mux0X - && e->Iex.Mux0X.cond->tag == Iex_Const) { - Bool zero; - /* assured us by the IR type rules */ - vassert(e->Iex.Mux0X.cond->Iex.Const.con->tag == Ico_U8); - zero = toBool(0 == (0xFF & e->Iex.Mux0X.cond - ->Iex.Const.con->Ico.U8)); - e2 = zero ? e->Iex.Mux0X.expr0 : e->Iex.Mux0X.exprX; + if (e->tag == Iex_Mux0X) { + /* is the discriminant is a constant? */ + if (e->Iex.Mux0X.cond->tag == Iex_Const) { + Bool zero; + /* assured us by the IR type rules */ + vassert(e->Iex.Mux0X.cond->Iex.Const.con->tag == Ico_U8); + zero = toBool(0 == (0xFF & e->Iex.Mux0X.cond + ->Iex.Const.con->Ico.U8)); + e2 = zero ? e->Iex.Mux0X.expr0 : e->Iex.Mux0X.exprX; + } + else + /* are the arms identical? (pretty weedy test) */ + if (sameIRTempsOrIcoU32s(e->Iex.Mux0X.expr0, + e->Iex.Mux0X.exprX)) { + e2 = e->Iex.Mux0X.expr0; + } } + /* Show cases where we've found but not folded 'op(t,t)'. */ + if (0 && e == e2 && e->tag == Iex_Binop + && sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) { + vex_printf("IDENT: "); + ppIRExpr(e); vex_printf("\n"); + } + + /* Show the overall results of folding. */ if (DEBUG_IROPT && e2 != e) { vex_printf("FOLD: "); ppIRExpr(e); vex_printf(" -> "); @@ -1674,7 +1749,6 @@ static IRExpr* subst_Expr ( IRExpr** env, IRExpr* ex ) case Iex_Load: vassert(isIRAtom(ex->Iex.Load.addr)); return IRExpr_Load( - ex->Iex.Load.isLL, ex->Iex.Load.end, ex->Iex.Load.ty, subst_Expr(env, ex->Iex.Load.addr) @@ -1763,7 +1837,6 @@ static IRStmt* subst_and_fold_Stmt ( IRExpr** env, IRStmt* st ) vassert(isIRAtom(st->Ist.Store.data)); return IRStmt_Store( st->Ist.Store.end, - st->Ist.Store.resSC, fold_Expr(subst_Expr(env, st->Ist.Store.addr)), fold_Expr(subst_Expr(env, st->Ist.Store.data)) ); @@ -1787,6 +1860,19 @@ static IRStmt* subst_and_fold_Stmt ( IRExpr** env, IRStmt* st ) return IRStmt_CAS(cas2); } + case Ist_LLSC: + vassert(isIRAtom(st->Ist.LLSC.addr)); + if (st->Ist.LLSC.storedata) + vassert(isIRAtom(st->Ist.LLSC.storedata)); + return IRStmt_LLSC( + st->Ist.LLSC.end, + st->Ist.LLSC.result, + fold_Expr(subst_Expr(env, st->Ist.LLSC.addr)), + st->Ist.LLSC.storedata + ? fold_Expr(subst_Expr(env, st->Ist.LLSC.storedata)) + : NULL + ); + case Ist_Dirty: { Int i; IRDirty *d, *d2; @@ -2022,6 +2108,11 @@ static void addUses_Stmt ( Bool* set, IRStmt* st ) addUses_Expr(set, cas->dataHi); addUses_Expr(set, cas->dataLo); return; + case Ist_LLSC: + addUses_Expr(set, st->Ist.LLSC.addr); + if (st->Ist.LLSC.storedata) + addUses_Expr(set, st->Ist.LLSC.storedata); + return; case Ist_Dirty: d = st->Ist.Dirty.details; if (d->mFx != Ifx_None) @@ -2149,8 +2240,10 @@ static Bool isOneU1 ( IRExpr* e ) /*---------------------------------------------------------------*/ static -IRSB* spec_helpers_BB ( IRSB* bb, - IRExpr* (*specHelper) ( HChar*, IRExpr**) ) +IRSB* spec_helpers_BB( + IRSB* bb, + IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int) + ) { Int i; IRStmt* st; @@ -2165,7 +2258,8 @@ IRSB* spec_helpers_BB ( IRSB* bb, continue; ex = (*specHelper)( st->Ist.WrTmp.data->Iex.CCall.cee->name, - st->Ist.WrTmp.data->Iex.CCall.args ); + st->Ist.WrTmp.data->Iex.CCall.args, + &bb->stmts[0], i ); if (!ex) /* the front end can't think of a suitable replacement */ continue; @@ -2608,7 +2702,8 @@ static Bool do_cse_BB ( IRSB* bb ) to do the no-overlap assessments needed for Put/PutI. */ switch (st->tag) { - case Ist_Dirty: case Ist_Store: case Ist_MBE: case Ist_CAS: + case Ist_Dirty: case Ist_Store: case Ist_MBE: + case Ist_CAS: case Ist_LLSC: paranoia = 2; break; case Ist_Put: case Ist_PutI: paranoia = 1; break; @@ -3299,8 +3394,6 @@ static void deltaIRStmt ( IRStmt* st, Int delta ) deltaIRExpr(st->Ist.Exit.guard, delta); break; case Ist_Store: - if (st->Ist.Store.resSC != IRTemp_INVALID) - st->Ist.Store.resSC += delta; deltaIRExpr(st->Ist.Store.addr, delta); deltaIRExpr(st->Ist.Store.data, delta); break; @@ -3316,6 +3409,12 @@ static void deltaIRStmt ( IRStmt* st, Int delta ) deltaIRExpr(st->Ist.CAS.details->dataHi, delta); deltaIRExpr(st->Ist.CAS.details->dataLo, delta); break; + case Ist_LLSC: + st->Ist.LLSC.result += delta; + deltaIRExpr(st->Ist.LLSC.addr, delta); + if (st->Ist.LLSC.storedata) + deltaIRExpr(st->Ist.LLSC.storedata, delta); + break; case Ist_Dirty: d = st->Ist.Dirty.details; deltaIRExpr(d->guard, delta); @@ -3780,6 +3879,11 @@ static void aoccCount_Stmt ( UShort* uses, IRStmt* st ) aoccCount_Expr(uses, cas->dataHi); aoccCount_Expr(uses, cas->dataLo); return; + case Ist_LLSC: + aoccCount_Expr(uses, st->Ist.LLSC.addr); + if (st->Ist.LLSC.storedata) + aoccCount_Expr(uses, st->Ist.LLSC.storedata); + return; case Ist_Dirty: d = st->Ist.Dirty.details; if (d->mFx != Ifx_None) @@ -3905,6 +4009,38 @@ static IRExpr* fold_IRExpr_Unop ( IROp op, IRExpr* aa ) if (is_Unop(aa, Iop_CmpwNEZ64)) return IRExpr_Unop( Iop_CmpNEZ64, aa->Iex.Unop.arg ); break; + case Iop_64to32: + /* 64to32( 32Uto64 ( x )) --> x */ + if (is_Unop(aa, Iop_32Uto64)) + return aa->Iex.Unop.arg; + /* 64to32( 8Uto64 ( x )) --> 8Uto32(x) */ + if (is_Unop(aa, Iop_8Uto64)) + return IRExpr_Unop(Iop_8Uto32, aa->Iex.Unop.arg); + break; + + case Iop_32Uto64: + /* 32Uto64( 8Uto32( x )) --> 8Uto64(x) */ + if (is_Unop(aa, Iop_8Uto32)) + return IRExpr_Unop(Iop_8Uto64, aa->Iex.Unop.arg); + /* 32Uto64( 16Uto32( x )) --> 16Uto64(x) */ + if (is_Unop(aa, Iop_16Uto32)) + return IRExpr_Unop(Iop_16Uto64, aa->Iex.Unop.arg); + break; + + case Iop_1Sto32: + /* 1Sto32( CmpNEZ8( 32to8( 1Uto32( CmpNEZ32( x ))))) -> CmpwNEZ32(x) */ + if (is_Unop(aa, Iop_CmpNEZ8) + && is_Unop(aa->Iex.Unop.arg, Iop_32to8) + && is_Unop(aa->Iex.Unop.arg->Iex.Unop.arg, Iop_1Uto32) + && is_Unop(aa->Iex.Unop.arg->Iex.Unop.arg->Iex.Unop.arg, + Iop_CmpNEZ32)) { + return IRExpr_Unop( Iop_CmpwNEZ32, + aa->Iex.Unop.arg->Iex.Unop.arg + ->Iex.Unop.arg->Iex.Unop.arg); + } + break; + + default: break; } @@ -3966,7 +4102,6 @@ static IRExpr* atbSubst_Expr ( ATmpInfo* env, IRExpr* e ) ); case Iex_Load: return IRExpr_Load( - e->Iex.Load.isLL, e->Iex.Load.end, e->Iex.Load.ty, atbSubst_Expr(env, e->Iex.Load.addr) @@ -4003,7 +4138,6 @@ static IRStmt* atbSubst_Stmt ( ATmpInfo* env, IRStmt* st ) case Ist_Store: return IRStmt_Store( st->Ist.Store.end, - st->Ist.Store.resSC, atbSubst_Expr(env, st->Ist.Store.addr), atbSubst_Expr(env, st->Ist.Store.data) ); @@ -4048,6 +4182,14 @@ static IRStmt* atbSubst_Stmt ( ATmpInfo* env, IRStmt* st ) atbSubst_Expr(env, cas->dataLo) ); return IRStmt_CAS(cas2); + case Ist_LLSC: + return IRStmt_LLSC( + st->Ist.LLSC.end, + st->Ist.LLSC.result, + atbSubst_Expr(env, st->Ist.LLSC.addr), + st->Ist.LLSC.storedata + ? atbSubst_Expr(env, st->Ist.LLSC.storedata) : NULL + ); case Ist_Dirty: d = st->Ist.Dirty.details; d2 = emptyIRDirty(); @@ -4189,15 +4331,13 @@ static IRStmt* atbSubst_Stmt ( ATmpInfo* env, IRStmt* st ) /* be True if this stmt writes memory or might do (==> we don't want to reorder other loads or stores relative to it). Also, - a load-linked falls under this classification, since we + both LL and SC fall under this classification, since we really ought to be conservative and not reorder any other - memory transactions relative to it. */ + memory transactions relative to them. */ stmtStores = toBool( st->tag == Ist_Store - || (st->tag == Ist_WrTmp - && st->Ist.WrTmp.data->tag == Iex_Load - && st->Ist.WrTmp.data->Iex.Load.isLL) - || st->tag == Ist_Dirty ); + || st->tag == Ist_Dirty + || st->tag == Ist_LLSC ); for (k = A_NENV-1; k >= 0; k--) { if (env[k].bindee == NULL) @@ -4277,7 +4417,7 @@ static Bool iropt_verbose = False; /* True; */ static IRSB* cheap_transformations ( IRSB* bb, - IRExpr* (*specHelper) (HChar*, IRExpr**), + IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int), Bool (*preciseMemExnsFn)(Int,Int) ) { @@ -4388,6 +4528,11 @@ static void considerExpensives ( /*OUT*/Bool* hasGetIorPutI, vassert(cas->dataHi == NULL || isIRAtom(cas->dataHi)); vassert(isIRAtom(cas->dataLo)); break; + case Ist_LLSC: + vassert(isIRAtom(st->Ist.LLSC.addr)); + if (st->Ist.LLSC.storedata) + vassert(isIRAtom(st->Ist.LLSC.storedata)); + break; case Ist_Dirty: d = st->Ist.Dirty.details; vassert(isIRAtom(d->guard)); @@ -4406,7 +4551,7 @@ static void considerExpensives ( /*OUT*/Bool* hasGetIorPutI, default: bad: ppIRStmt(st); - vpanic("hasGetIorPutI"); + vpanic("considerExpensives"); } } } @@ -4423,10 +4568,13 @@ static void considerExpensives ( /*OUT*/Bool* hasGetIorPutI, */ -IRSB* do_iropt_BB ( IRSB* bb0, - IRExpr* (*specHelper) (HChar*, IRExpr**), - Bool (*preciseMemExnsFn)(Int,Int), - Addr64 guest_addr ) +IRSB* do_iropt_BB( + IRSB* bb0, + IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int), + Bool (*preciseMemExnsFn)(Int,Int), + Addr64 guest_addr, + VexArch guest_arch + ) { static Int n_total = 0; static Int n_expensive = 0; @@ -4457,6 +4605,15 @@ IRSB* do_iropt_BB ( IRSB* bb0, bb = cheap_transformations( bb, specHelper, preciseMemExnsFn ); + if (guest_arch == VexArchARM) { + /* Translating Thumb2 code produces a lot of chaff. We have to + work extra hard to get rid of it. */ + bb = cprop_BB(bb); + bb = spec_helpers_BB ( bb, specHelper ); + redundant_put_removal_BB ( bb, preciseMemExnsFn ); + do_deadcode_BB( bb ); + } + if (vex_control.iropt_level > 1) { /* Peer at what we have, to decide how much more effort to throw diff --git a/VEX/priv/ir_opt.h b/VEX/priv/ir_opt.h index 1b3ca25..ecdb146 100644 --- a/VEX/priv/ir_opt.h +++ b/VEX/priv/ir_opt.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (ir_opt.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin ir_opt.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -54,10 +43,13 @@ /* Top level optimiser entry point. Returns a new BB. Operates under the control of the global "vex_control" struct. */ extern -IRSB* do_iropt_BB ( IRSB* bb, - IRExpr* (*specHelper) (HChar*, IRExpr**), - Bool (*preciseMemExnsFn)(Int,Int), - Addr64 guest_addr ); +IRSB* do_iropt_BB( + IRSB* bb, + IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int), + Bool (*preciseMemExnsFn)(Int,Int), + Addr64 guest_addr, + VexArch guest_arch + ); /* Do a constant folding/propagation pass. */ extern diff --git a/VEX/priv/main_globals.c b/VEX/priv/main_globals.c index d011042..716fa75 100644 --- a/VEX/priv/main_globals.c +++ b/VEX/priv/main_globals.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (main_globals.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin main_globals.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/priv/main_globals.h b/VEX/priv/main_globals.h index 7e53016..5b561a3 100644 --- a/VEX/priv/main_globals.h +++ b/VEX/priv/main_globals.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (main_globals.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin main_globals.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index e14f4cc..1e80972 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (main_main.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin main_main.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -60,6 +49,7 @@ #include "host_x86_defs.h" #include "host_amd64_defs.h" #include "host_ppc_defs.h" +#include "host_arm_defs.h" #include "guest_generic_bb_to_IR.h" #include "guest_x86_defs.h" @@ -67,6 +57,8 @@ #include "guest_arm_defs.h" #include "guest_ppc_defs.h" +#include "host_generic_simd128.h" + /* This file contains the top level interface to the library. */ @@ -88,6 +80,7 @@ void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) vcon->iropt_unroll_thresh = 120; vcon->guest_max_insns = 60; vcon->guest_chase_thresh = 10; + vcon->guest_chase_cond = False; } @@ -127,6 +120,8 @@ void LibVEX_Init ( vassert(vcon->guest_max_insns <= 100); vassert(vcon->guest_chase_thresh >= 0); vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); + vassert(vcon->guest_chase_cond == True + || vcon->guest_chase_cond == False); /* Check that Vex has been built with sizes of basic types as stated in priv/libvex_basictypes.h. Failure of any of these is @@ -148,6 +143,7 @@ void LibVEX_Init ( vassert(4 == sizeof(Addr32)); vassert(8 == sizeof(Addr64)); vassert(16 == sizeof(U128)); + vassert(16 == sizeof(V128)); vassert(sizeof(void*) == 4 || sizeof(void*) == 8); vassert(sizeof(void*) == sizeof(int*)); @@ -179,15 +175,15 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) Bool (*isMove) ( HInstr*, HReg*, HReg* ); void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ); void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); - HInstr* (*genSpill) ( HReg, Int, Bool ); - HInstr* (*genReload) ( HReg, Int, Bool ); + void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); + void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); HInstr* (*directReload) ( HInstr*, HReg, Short ); void (*ppInstr) ( HInstr*, Bool ); void (*ppReg) ( HReg ); HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*, VexAbiInfo* ); Int (*emit) ( UChar*, Int, HInstr*, Bool, void* ); - IRExpr* (*specHelper) ( HChar*, IRExpr** ); + IRExpr* (*specHelper) ( HChar*, IRExpr**, IRStmt**, Int ); Bool (*preciseMemExnsFn) ( Int, Int ); DisOneInstrFn disInstrFn; @@ -242,10 +238,13 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) getAllocableRegs_X86 ( &n_available_real_regs, &available_real_regs ); isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; - getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_X86Instr; + getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) + getRegUsage_X86Instr; mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr; - genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_X86; - genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_X86; + genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) + genSpill_X86; + genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) + genReload_X86; directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86; ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; ppReg = (void(*)(HReg)) ppHRegX86; @@ -262,10 +261,13 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) getAllocableRegs_AMD64 ( &n_available_real_regs, &available_real_regs ); isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; - getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_AMD64Instr; + getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) + getRegUsage_AMD64Instr; mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr; - genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_AMD64; - genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_AMD64; + genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) + genSpill_AMD64; + genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) + genReload_AMD64; ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; ppReg = (void(*)(HReg)) ppHRegAMD64; iselSB = iselSB_AMD64; @@ -283,8 +285,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPCInstr; mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPCInstr; - genSpill = (HInstr*(*)(HReg,Int,Bool)) genSpill_PPC; - genReload = (HInstr*(*)(HReg,Int,Bool)) genReload_PPC; + genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; + genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr; ppReg = (void(*)(HReg)) ppHRegPPC; iselSB = iselSB_PPC; @@ -302,8 +304,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPCInstr; mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPCInstr; - genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_PPC; - genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_PPC; + genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; + genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr; ppReg = (void(*)(HReg)) ppHRegPPC; iselSB = iselSB_PPC; @@ -314,8 +316,27 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ break; + case VexArchARM: + mode64 = False; + getAllocableRegs_ARM ( &n_available_real_regs, + &available_real_regs ); + isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARMInstr; + getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_ARMInstr; + mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_ARMInstr; + genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_ARM; + genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_ARM; + ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr; + ppReg = (void(*)(HReg)) ppHRegARM; + iselSB = iselSB_ARM; + emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_ARMInstr; + host_is_bigendian = False; + host_word_type = Ity_I32; + vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); + vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ + break; + default: - vpanic("LibVEX_Translate: unsupported target insn set"); + vpanic("LibVEX_Translate: unsupported host insn set"); } @@ -331,7 +352,7 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestX86State) % 8); + vassert(0 == sizeof(VexGuestX86State) % 16); vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4); vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); @@ -347,24 +368,12 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestAMD64State) % 8); + vassert(0 == sizeof(VexGuestAMD64State) % 16); vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); break; - case VexArchARM: - preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; - disInstrFn = NULL; /* HACK */ - specHelper = guest_arm_spechelper; - guest_sizeB = sizeof(VexGuestARMState); - guest_word_type = Ity_I32; - guest_layout = &armGuest_layout; - offB_TISTART = 0; /* hack ... arm has bitrot */ - offB_TILEN = 0; /* hack ... arm has bitrot */ - vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); - break; - case VexArchPPC32: preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; disInstrFn = disInstr_PPC; @@ -375,7 +384,7 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestPPC32State) % 8); + vassert(0 == sizeof(VexGuestPPC32State) % 16); vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); @@ -398,6 +407,22 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); break; + case VexArchARM: + preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; + disInstrFn = disInstr_ARM; + specHelper = guest_arm_spechelper; + guest_sizeB = sizeof(VexGuestARMState); + guest_word_type = Ity_I32; + guest_layout = &armGuest_layout; + offB_TISTART = offsetof(VexGuestARMState,guest_TISTART); + offB_TILEN = offsetof(VexGuestARMState,guest_TILEN); + vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); + vassert(0 == sizeof(VexGuestARMState) % 16); + vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4); + vassert(sizeof( ((VexGuestARMState*)0)->guest_TILEN ) == 4); + vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); + break; + default: vpanic("LibVEX_Translate: unsupported guest insn set"); } @@ -476,7 +501,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) /* Clean it up, hopefully a lot. */ irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, - vta->guest_bytes_addr ); + vta->guest_bytes_addr, + vta->arch_guest ); sanityCheckIRSB( irsb, "after initial iropt", True/*must be flat*/, guest_word_type ); @@ -706,6 +732,9 @@ void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) { vai->hwcaps = 0; vai->ppc_cache_line_szB = 0; + vai->ppc_dcbz_szB = 0; + vai->ppc_dcbzl_szB = 0; + } /* Write default settings info *vbi. */ @@ -729,32 +758,53 @@ void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) static HChar* show_hwcaps_x86 ( UInt hwcaps ) { /* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */ - if (hwcaps == 0) - return "x86-sse0"; - if (hwcaps == VEX_HWCAPS_X86_SSE1) - return "x86-sse1"; - if (hwcaps == (VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2)) - return "x86-sse1-sse2"; - if (hwcaps == (VEX_HWCAPS_X86_SSE1 - | VEX_HWCAPS_X86_SSE2 | VEX_HWCAPS_X86_SSE3)) - return "x86-sse1-sse2-sse3"; - - return NULL; + switch (hwcaps) { + case 0: + return "x86-sse0"; + case VEX_HWCAPS_X86_SSE1: + return "x86-sse1"; + case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2: + return "x86-sse1-sse2"; + case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 + | VEX_HWCAPS_X86_LZCNT: + return "x86-sse1-sse2-lzcnt"; + case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 + | VEX_HWCAPS_X86_SSE3: + return "x86-sse1-sse2-sse3"; + case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 + | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT: + return "x86-sse1-sse2-sse3-lzcnt"; + default: + return NULL; + } } static HChar* show_hwcaps_amd64 ( UInt hwcaps ) { /* SSE3 and CX16 are orthogonal and > baseline, although we really don't expect to come across anything which can do SSE3 but can't - do CX16. Still, we can handle that case. */ - const UInt SSE3 = VEX_HWCAPS_AMD64_SSE3; - const UInt CX16 = VEX_HWCAPS_AMD64_CX16; - UInt c = hwcaps; - if (c == 0) return "amd64-sse2"; - if (c == SSE3) return "amd64-sse3"; - if (c == CX16) return "amd64-sse2-cx16"; - if (c == (SSE3|CX16)) return "amd64-sse3-cx16"; - return NULL; + do CX16. Still, we can handle that case. LZCNT is similarly + orthogonal. */ + switch (hwcaps) { + case 0: + return "amd64-sse2"; + case VEX_HWCAPS_AMD64_SSE3: + return "amd64-sse3"; + case VEX_HWCAPS_AMD64_CX16: + return "amd64-sse2-cx16"; + case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16: + return "amd64-sse3-cx16"; + case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_LZCNT: + return "amd64-sse3-lzcnt"; + case VEX_HWCAPS_AMD64_CX16 | VEX_HWCAPS_AMD64_LZCNT: + return "amd64-sse2-cx16-lzcnt"; + case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16 + | VEX_HWCAPS_AMD64_LZCNT: + return "amd64-sse3-cx16-lzcnt"; + + default: + return NULL; + } } static HChar* show_hwcaps_ppc32 ( UInt hwcaps ) @@ -799,7 +849,41 @@ static HChar* show_hwcaps_ppc64 ( UInt hwcaps ) static HChar* show_hwcaps_arm ( UInt hwcaps ) { - if (hwcaps == 0) return "arm-baseline"; + Bool N = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0); + Bool vfp = ((hwcaps & (VEX_HWCAPS_ARM_VFP | + VEX_HWCAPS_ARM_VFP2 | VEX_HWCAPS_ARM_VFP3)) != 0); + switch (VEX_ARM_ARCHLEVEL(hwcaps)) { + case 5: + if (N) + return NULL; + if (vfp) + return "ARMv5-vfp"; + else + return "ARMv5"; + return NULL; + case 6: + if (N) + return NULL; + if (vfp) + return "ARMv6-vfp"; + else + return "ARMv6"; + return NULL; + case 7: + if (vfp) { + if (N) + return "ARMv7-vfp-neon"; + else + return "ARMv7-vfp"; + } else { + if (N) + return "ARMv7-neon"; + else + return "ARMv7"; + } + default: + return NULL; + } return NULL; } diff --git a/VEX/priv/main_util.c b/VEX/priv/main_util.c index 0bba6d4..d12380e 100644 --- a/VEX/priv/main_util.c +++ b/VEX/priv/main_util.c @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (main_util.c) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin main_util.c ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -62,7 +51,7 @@ MByte/sec. Once the size increases enough to fall out of the cache into memory, the rate falls by about a factor of 3. */ -#define N_TEMPORARY_BYTES 4000000 +#define N_TEMPORARY_BYTES 5000000 static HChar temporary[N_TEMPORARY_BYTES] __attribute__((aligned(8))); static HChar* temporary_first = &temporary[0]; @@ -192,6 +181,16 @@ void vexSetAllocModeTEMP_and_clear ( void ) mode = VexAllocModeTEMP; temporary_curr = &temporary[0]; private_LibVEX_alloc_curr = &temporary[0]; + + /* Set to (1) and change the fill byte to 0x00 or 0xFF to test for + any potential bugs due to using uninitialised memory in the main + VEX storage area. */ + if (0) { + Int i; + for (i = 0; i < N_TEMPORARY_BYTES; i++) + temporary[i] = 0x00; + } + vexAllocSanityCheck(); } diff --git a/VEX/priv/main_util.h b/VEX/priv/main_util.h index 0552828..1392b4b 100644 --- a/VEX/priv/main_util.h +++ b/VEX/priv/main_util.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (main_util.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin main_util.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index c86f565..a9e9bce 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -80,31 +69,40 @@ typedef /* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE), with cmpxchg8b. */ -#define VEX_HWCAPS_X86_SSE1 (1<<1) /* SSE1 support (Pentium III) */ -#define VEX_HWCAPS_X86_SSE2 (1<<2) /* SSE2 support (Pentium 4) */ -#define VEX_HWCAPS_X86_SSE3 (1<<3) /* SSE3 support (>= Prescott) */ +#define VEX_HWCAPS_X86_SSE1 (1<<1) /* SSE1 support (Pentium III) */ +#define VEX_HWCAPS_X86_SSE2 (1<<2) /* SSE2 support (Pentium 4) */ +#define VEX_HWCAPS_X86_SSE3 (1<<3) /* SSE3 support (>= Prescott) */ +#define VEX_HWCAPS_X86_LZCNT (1<<4) /* SSE4a LZCNT insn */ /* amd64: baseline capability is SSE2, with cmpxchg8b but not cmpxchg16b. */ -#define VEX_HWCAPS_AMD64_SSE3 (1<<4) /* SSE3 support */ -#define VEX_HWCAPS_AMD64_CX16 (1<<5) /* cmpxchg16b support */ +#define VEX_HWCAPS_AMD64_SSE3 (1<<5) /* SSE3 support */ +#define VEX_HWCAPS_AMD64_CX16 (1<<6) /* cmpxchg16b support */ +#define VEX_HWCAPS_AMD64_LZCNT (1<<7) /* SSE4a LZCNT insn */ /* ppc32: baseline capability is integer only */ -#define VEX_HWCAPS_PPC32_F (1<<6) /* basic (non-optional) FP */ -#define VEX_HWCAPS_PPC32_V (1<<7) /* Altivec (VMX) */ -#define VEX_HWCAPS_PPC32_FX (1<<8) /* FP extns (fsqrt, fsqrts) */ -#define VEX_HWCAPS_PPC32_GX (1<<9) /* Graphics extns - (fres,frsqrte,fsel,stfiwx) */ +#define VEX_HWCAPS_PPC32_F (1<<8) /* basic (non-optional) FP */ +#define VEX_HWCAPS_PPC32_V (1<<9) /* Altivec (VMX) */ +#define VEX_HWCAPS_PPC32_FX (1<<10) /* FP extns (fsqrt, fsqrts) */ +#define VEX_HWCAPS_PPC32_GX (1<<11) /* Graphics extns + (fres,frsqrte,fsel,stfiwx) */ /* ppc64: baseline capability is integer and basic FP insns */ -#define VEX_HWCAPS_PPC64_V (1<<10) /* Altivec (VMX) */ -#define VEX_HWCAPS_PPC64_FX (1<<11) /* FP extns (fsqrt, fsqrts) */ -#define VEX_HWCAPS_PPC64_GX (1<<12) /* Graphics extns - (fres,frsqrte,fsel,stfiwx) */ +#define VEX_HWCAPS_PPC64_V (1<<12) /* Altivec (VMX) */ +#define VEX_HWCAPS_PPC64_FX (1<<13) /* FP extns (fsqrt, fsqrts) */ +#define VEX_HWCAPS_PPC64_GX (1<<14) /* Graphics extns + (fres,frsqrte,fsel,stfiwx) */ /* arm: baseline capability is ARMv4 */ -/* No extra capabilities */ +/* Bits 5:0 - architecture level (e.g. 5 for v5, 6 for v6 etc) */ +#define VEX_HWCAPS_ARM_VFP (1<<6) /* VFP extension */ +#define VEX_HWCAPS_ARM_VFP2 (1<<7) /* VFPv2 */ +#define VEX_HWCAPS_ARM_VFP3 (1<<8) /* VFPv3 */ +/* Bits 15:10 reserved for (possible) future VFP revisions */ +#define VEX_HWCAPS_ARM_NEON (1<<16) /* Advanced SIMD also known as NEON */ +/* Get an ARM architecure level from HWCAPS */ +#define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f) /* These return statically allocated strings. */ @@ -122,6 +120,10 @@ typedef UInt hwcaps; /* PPC32/PPC64 only: size of cache line */ Int ppc_cache_line_szB; + /* PPC32/PPC64 only: sizes zeroed by the dcbz/dcbzl instructions + * (bug#135264) */ + UInt ppc_dcbz_szB; + UInt ppc_dcbzl_szB; /* 0 means unsupported (SIGILL) */ } VexArchInfo; @@ -265,6 +267,9 @@ typedef far, the front end(s) will attempt to chase into its successor. A setting of zero disables chasing. */ Int guest_chase_thresh; + /* EXPERIMENTAL: chase across conditional branches? Not all + front ends honour this. Default: NO. */ + Bool guest_chase_cond; } VexControl; diff --git a/VEX/pub/libvex_basictypes.h b/VEX/pub/libvex_basictypes.h index 1848700..a945913 100644 --- a/VEX/pub/libvex_basictypes.h +++ b/VEX/pub/libvex_basictypes.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_basictypes.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_basictypes.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -73,7 +62,17 @@ typedef signed long long int Long; /* Always 128 bits. */ typedef UInt U128[4]; +/* A union for doing 128-bit vector primitives conveniently. */ +typedef + union { + UChar w8[16]; + UShort w16[8]; + UInt w32[4]; + ULong w64[2]; + } + V128; +/* Floating point. */ typedef float Float; /* IEEE754 single-precision (32-bit) value */ typedef double Double; /* IEEE754 double-precision (64-bit) value */ @@ -144,6 +143,8 @@ typedef unsigned long HWord; # define VEX_HOST_WORDSIZE 8 #elif defined(__powerpc__) && !defined(__powerpc64__) # define VEX_HOST_WORDSIZE 4 +#elif defined(__arm__) +# define VEX_HOST_WORDSIZE 4 #elif defined(_AIX) && !defined(__64BIT__) # define VEX_HOST_WORDSIZE 4 diff --git a/VEX/pub/libvex_emwarn.h b/VEX/pub/libvex_emwarn.h index eadd6e4..0bf263f 100644 --- a/VEX/pub/libvex_emwarn.h +++ b/VEX/pub/libvex_emwarn.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_emwarn.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_emwarn.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/pub/libvex_guest_amd64.h b/VEX/pub/libvex_guest_amd64.h index 74a0887..c37e6c8 100644 --- a/VEX/pub/libvex_guest_amd64.h +++ b/VEX/pub/libvex_guest_amd64.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_guest_amd64.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_guest_amd64.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -87,22 +76,25 @@ typedef /* The D flag is stored here, encoded as either -1 or +1 */ /* 160 */ ULong guest_DFLAG; /* 168 */ ULong guest_RIP; + /* Bit 18 (AC) of eflags stored here, as either 0 or 1. */ + /* ... */ ULong guest_ACFLAG; + /* Bit 21 (ID) of eflags stored here, as either 0 or 1. */ + /* 176 */ ULong guest_IDFLAG; /* Probably a lot more stuff too. D,ID flags 16 128-bit SSE registers all the old x87 FPU gunk - segment registers - */ - - /* Bit 21 (ID) of eflags stored here, as either 0 or 1. */ - /* 176 */ ULong guest_IDFLAG; + segment registers */ /* HACK to make tls on amd64-linux work. %fs only ever seems to hold zero, and so guest_FS_ZERO holds the 64-bit offset associated with a %fs value of zero. */ /* 184 */ ULong guest_FS_ZERO; - /* XMM registers */ + /* XMM registers. Note that these must be allocated + consecutively in order that the SSE4.2 PCMP{E,I}STR{I,M} + helpers can treat them as an array. XMM16 is a fake reg used + as an intermediary in handling aforementioned insns. */ /* 192 */ULong guest_SSEROUND; /* 200 */U128 guest_XMM0; U128 guest_XMM1; @@ -120,6 +112,7 @@ typedef U128 guest_XMM13; U128 guest_XMM14; U128 guest_XMM15; + U128 guest_XMM16; /* FPU */ /* Note. Setting guest_FTOP to be ULong messes up the @@ -168,7 +161,7 @@ typedef ULong guest_IP_AT_SYSCALL; /* Padding to make it have an 16-aligned size */ - /* ULong padding; */ + ULong padding; } VexGuestAMD64State; diff --git a/VEX/pub/libvex_guest_arm.h b/VEX/pub/libvex_guest_arm.h index 885f8be..d7b47e0 100644 --- a/VEX/pub/libvex_guest_arm.h +++ b/VEX/pub/libvex_guest_arm.h @@ -1,47 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_guest_arm.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_guest_arm.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. - - Neither the names of the U.S. Department of Energy nor the - University of California nor the names of its contributors may be - used to endorse or promote products derived from this software - without prior written permission. + The GNU General Public License is contained in the file COPYING. */ #ifndef __LIBVEX_PUB_GUEST_ARM_H @@ -55,48 +39,162 @@ /*--- Vex's representation of the ARM CPU state. ---*/ /*---------------------------------------------------------------*/ -/* R13 traditionally used as the stack pointer ? */ - typedef struct { - UInt guest_R0; - UInt guest_R1; - UInt guest_R2; - UInt guest_R3; - UInt guest_R4; - UInt guest_R5; - UInt guest_R6; - UInt guest_R7; - UInt guest_R8; - UInt guest_R9; - UInt guest_R10; - UInt guest_R11; - UInt guest_R12; - - /* aka the stack pointer */ - UInt guest_R13; - - /* aka the link register */ - UInt guest_R14; - - /* Program counter. */ - UInt guest_R15; - - /* System call number copied in here from swi insn literal - field. */ - UInt guest_SYSCALLNO; - - /* 3-word thunk used to calculate N(sign) Z(zero) C(carry, + /* 0 */ + UInt guest_R0; + UInt guest_R1; + UInt guest_R2; + UInt guest_R3; + UInt guest_R4; + UInt guest_R5; + UInt guest_R6; + UInt guest_R7; + UInt guest_R8; + UInt guest_R9; + UInt guest_R10; + UInt guest_R11; + UInt guest_R12; + UInt guest_R13; /* stack pointer */ + UInt guest_R14; /* link register */ + UInt guest_R15T; + /* program counter[31:1] ++ [T], encoding both the current + instruction address and the ARM vs Thumb state of the + machine. T==1 is Thumb, T==0 is ARM. Hence values of the + form X--(31)--X1 denote a Thumb instruction at location + X--(31)--X0, values of the form X--(30)--X00 denote an ARM + instruction at precisely that address, and values of the form + X--(30)--10 are invalid since they would imply an ARM + instruction at a non-4-aligned address. */ + + /* 4-word thunk used to calculate N(sign) Z(zero) C(carry, unsigned overflow) and V(signed overflow) flags. */ - UInt guest_CC_OP; - UInt guest_CC_DEP1; - UInt guest_CC_DEP2; - + /* 64 */ + UInt guest_CC_OP; + UInt guest_CC_DEP1; + UInt guest_CC_DEP2; + UInt guest_CC_NDEP; + + /* A 32-bit value which is used to compute the APSR.Q (sticky + saturation) flag, when necessary. If the value stored here + is zero, APSR.Q is currently zero. If it is any other value, + APSR.Q is currently one. */ + UInt guest_QFLAG32; + + /* 32-bit values to represent APSR.GE0 .. GE3. Same + zero-vs-nonzero scheme as for QFLAG32. */ + UInt guest_GEFLAG0; + UInt guest_GEFLAG1; + UInt guest_GEFLAG2; + UInt guest_GEFLAG3; + + /* Various pseudo-regs mandated by Vex or Valgrind. */ /* Emulation warnings */ - UInt guest_EMWARN; - - /* Padding to make it have an 8-aligned size */ - UInt padding; + UInt guest_EMWARN; + + /* For clflush: record start and length of area to invalidate */ + UInt guest_TISTART; + UInt guest_TILEN; + + /* Used to record the unredirected guest address at the start of + a translation whose start has been redirected. By reading + this pseudo-register shortly afterwards, the translation can + find out what the corresponding no-redirection address was. + Note, this is only set for wrap-style redirects, not for + replace-style ones. */ + UInt guest_NRADDR; + + /* Needed for Darwin (but mandated for all guest architectures): + program counter at the last syscall insn (int 0x80/81/82, + sysenter, syscall, svc). Used when backing up to restart a + syscall that has been interrupted by a signal. */ + /* 116 */ + UInt guest_IP_AT_SYSCALL; + + /* VFP state. D0 .. D15 must be 8-aligned. */ + /* 120 -- I guess there's 4 bytes of padding just prior to this? */ + ULong guest_D0; + ULong guest_D1; + ULong guest_D2; + ULong guest_D3; + ULong guest_D4; + ULong guest_D5; + ULong guest_D6; + ULong guest_D7; + ULong guest_D8; + ULong guest_D9; + ULong guest_D10; + ULong guest_D11; + ULong guest_D12; + ULong guest_D13; + ULong guest_D14; + ULong guest_D15; + ULong guest_D16; + ULong guest_D17; + ULong guest_D18; + ULong guest_D19; + ULong guest_D20; + ULong guest_D21; + ULong guest_D22; + ULong guest_D23; + ULong guest_D24; + ULong guest_D25; + ULong guest_D26; + ULong guest_D27; + ULong guest_D28; + ULong guest_D29; + ULong guest_D30; + ULong guest_D31; + UInt guest_FPSCR; + + /* Not a town in Cornwall, but instead the TPIDRURO, on of the + Thread ID registers present in CP15 (the system control + coprocessor), register set "c13", register 3 (the User + Read-only Thread ID Register). arm-linux apparently uses it + to hold the TLS pointer for the thread. It's read-only in + user space. On Linux it is set in user space by various + thread-related syscalls. */ + UInt guest_TPIDRURO; + + /* Representation of the Thumb IT state. ITSTATE is a 32-bit + value with 4 8-bit lanes. [7:0] pertain to the next insn to + execute, [15:8] for the one after that, etc. The per-insn + update to ITSTATE is to unsignedly shift it right 8 bits, + hence introducing a zero byte for the furthest ahead + instruction. As per the next para, a zero byte denotes the + condition ALWAYS. + + Each byte lane has one of the two following formats: + + cccc 0001 for an insn which is part of an IT block. cccc is + the guarding condition (standard ARM condition + code) XORd with 0xE, so as to cause 'cccc == 0' + to encode the condition ALWAYS. + + 0000 0000 for an insn which is not part of an IT block. + + If the bottom 4 bits are zero then the top 4 must be too. + + Given the byte lane for an instruction, the guarding + condition for the instruction is (((lane >> 4) & 0xF) ^ 0xE). + This is not as stupid as it sounds, because the front end + elides the shift. And the am-I-in-an-IT-block check is + (lane != 0). + + In the case where (by whatever means) we know at JIT time + that an instruction is not in an IT block, we can prefix its + IR with assignments ITSTATE = 0 and hence have iropt fold out + the testing code. + + The condition "is outside or last in IT block" corresponds + to the top 24 bits of ITSTATE being zero. + */ + UInt guest_ITSTATE; + + /* Padding to make it have an 16-aligned size */ + UInt padding1; + UInt padding2; + UInt padding3; } VexGuestARMState; @@ -115,7 +213,7 @@ void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state ); /* Calculate the ARM flag state from the saved data. */ extern -UInt LibVEX_GuestARM_get_flags ( /*IN*/VexGuestARMState* vex_state ); +UInt LibVEX_GuestARM_get_cpsr ( /*IN*/VexGuestARMState* vex_state ); #endif /* ndef __LIBVEX_PUB_GUEST_ARM_H */ diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h index 485ffdf..3353319 100644 --- a/VEX/pub/libvex_guest_ppc32.h +++ b/VEX/pub/libvex_guest_ppc32.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_guest_ppc32.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_guest_ppc32.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h index 1ae2e15..e2afcbb 100644 --- a/VEX/pub/libvex_guest_ppc64.h +++ b/VEX/pub/libvex_guest_ppc64.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_guest_ppc64.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_guest_ppc64.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/pub/libvex_guest_x86.h b/VEX/pub/libvex_guest_x86.h index 2614c83..0c61604 100644 --- a/VEX/pub/libvex_guest_x86.h +++ b/VEX/pub/libvex_guest_x86.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_guest_x86.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_guest_x86.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index 3310f89..95042aa 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_ir.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_ir.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be @@ -531,6 +520,9 @@ typedef /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */ Iop_AddF64, Iop_SubF64, Iop_MulF64, Iop_DivF64, + /* :: IRRoundingMode(I32) x F32 x F32 -> F32 */ + Iop_AddF32, Iop_SubF32, Iop_MulF32, Iop_DivF32, + /* Variants of the above which produce a 64-bit result but which round their result to a IEEE float range first. */ /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */ @@ -540,10 +532,16 @@ typedef /* :: F64 -> F64 */ Iop_NegF64, Iop_AbsF64, + /* :: F32 -> F32 */ + Iop_NegF32, Iop_AbsF32, + /* Unary operations, with rounding. */ /* :: IRRoundingMode(I32) x F64 -> F64 */ Iop_SqrtF64, Iop_SqrtF64r32, + /* :: IRRoundingMode(I32) x F32 -> F32 */ + Iop_SqrtF32, + /* Comparison, yielding GT/LT/EQ/UN(ordered), as per the following: 0x45 Unordered 0x01 LT @@ -552,13 +550,15 @@ typedef This just happens to be the Intel encoding. The values are recorded in the type IRCmpF64Result. */ + /* :: F64 x F64 -> IRCmpF64Result(I32) */ Iop_CmpF64, /* --- Int to/from FP conversions. --- */ - /* For the most part, these take a first argument :: Ity_I32 - (as IRRoundingMode) which is an indication of the rounding - mode to use, as per the following encoding: + /* For the most part, these take a first argument :: Ity_I32 (as + IRRoundingMode) which is an indication of the rounding mode + to use, as per the following encoding ("the standard + encoding"): 00b to nearest (the default) 01b to -infinity 10b to +infinity @@ -570,25 +570,43 @@ typedef 10b to +infinity 11b to -infinity Any PPC -> IR front end will have to translate these PPC - encodings to the standard encodings. + encodings, as encoded in the guest state, to the standard + encodings, to pass to the primops. + For reference only, the ARM VFP encoding is: + 00b to nearest + 01b to +infinity + 10b to -infinity + 11b to zero + Again, this will have to be converted to the standard encoding + to pass to primops. If one of these conversions gets an out-of-range condition, or a NaN, as an argument, the result is host-defined. On x86 - the "integer indefinite" value 0x80..00 is produced. - On PPC it is either 0x80..00 or 0x7F..FF depending on the sign - of the argument. + the "integer indefinite" value 0x80..00 is produced. On PPC + it is either 0x80..00 or 0x7F..FF depending on the sign of + the argument. + + On ARMvfp, when converting to a signed integer result, the + overflow result is 0x80..00 for negative args and 0x7F..FF + for positive args. For unsigned integer results it is + 0x00..00 and 0xFF..FF respectively. Rounding is required whenever the destination type cannot represent exactly all values of the source type. */ - Iop_F64toI16, /* IRRoundingMode(I32) x F64 -> I16 */ - Iop_F64toI32, /* IRRoundingMode(I32) x F64 -> I32 */ - Iop_F64toI64, /* IRRoundingMode(I32) x F64 -> I64 */ + Iop_F64toI16S, /* IRRoundingMode(I32) x F64 -> signed I16 */ + Iop_F64toI32S, /* IRRoundingMode(I32) x F64 -> signed I32 */ + Iop_F64toI64S, /* IRRoundingMode(I32) x F64 -> signed I64 */ + + Iop_F64toI32U, /* IRRoundingMode(I32) x F64 -> unsigned I32 */ - Iop_I16toF64, /* I16 -> F64 */ - Iop_I32toF64, /* I32 -> F64 */ - Iop_I64toF64, /* IRRoundingMode(I32) x I64 -> F64 */ + Iop_I16StoF64, /* signed I16 -> F64 */ + Iop_I32StoF64, /* signed I32 -> F64 */ + Iop_I64StoF64, /* IRRoundingMode(I32) x signed I64 -> F64 */ + Iop_I32UtoF64, /* unsigned I32 -> F64 */ + + /* Conversion between floating point formats */ Iop_F32toF64, /* F32 -> F64 */ Iop_F64toF32, /* IRRoundingMode(I32) x F64 -> F32 */ @@ -621,6 +639,8 @@ typedef Iop_2xm1F64, /* (2^arg - 1.0) */ Iop_RoundF64toInt, /* F64 value to nearest integral value (still as F64) */ + Iop_RoundF32toInt, /* F32 value to nearest integral value (still + as F32) */ /* --- guest ppc32/64 specifics, not mandated by 754. --- */ @@ -655,6 +675,78 @@ typedef Iop_CalcFPRF, /* Calc 5 fpscr[FPRF] bits (Class, <, =, >, Unord) from FP result */ + /* ------------------ 32-bit SIMD Integer ------------------ */ + + /* 16x2 add/sub, also signed/unsigned saturating variants */ + Iop_Add16x2, Iop_Sub16x2, + Iop_QAdd16Sx2, Iop_QAdd16Ux2, + Iop_QSub16Sx2, Iop_QSub16Ux2, + + /* 16x2 signed/unsigned halving add/sub. For each lane, these + compute bits 16:1 of (eg) sx(argL) + sx(argR), + or zx(argL) - zx(argR) etc. */ + Iop_HAdd16Ux2, Iop_HAdd16Sx2, + Iop_HSub16Ux2, Iop_HSub16Sx2, + + /* 8x4 add/sub, also signed/unsigned saturating variants */ + Iop_Add8x4, Iop_Sub8x4, + Iop_QAdd8Sx4, Iop_QAdd8Ux4, + Iop_QSub8Sx4, Iop_QSub8Ux4, + + /* 8x4 signed/unsigned halving add/sub. For each lane, these + compute bits 8:1 of (eg) sx(argL) + sx(argR), + or zx(argL) - zx(argR) etc. */ + Iop_HAdd8Ux4, Iop_HAdd8Sx4, + Iop_HSub8Ux4, Iop_HSub8Sx4, + + /* 8x4 sum of absolute unsigned differences. */ + Iop_Sad8Ux4, + + /* MISC (vector integer cmp != 0) */ + Iop_CmpNEZ16x2, Iop_CmpNEZ8x4, + + /* ------------------ 64-bit SIMD FP ------------------------ */ + + /* Convertion to/from int */ + Iop_I32UtoFx2, Iop_I32StoFx2, /* I32x4 -> F32x4 */ + Iop_FtoI32Ux2_RZ, Iop_FtoI32Sx2_RZ, /* F32x4 -> I32x4 */ + /* Fixed32 format is floating-point number with fixed number of fraction + bits. The number of fraction bits is passed as a second argument of + type I8. */ + Iop_F32ToFixed32Ux2_RZ, Iop_F32ToFixed32Sx2_RZ, /* fp -> fixed-point */ + Iop_Fixed32UToF32x2_RN, Iop_Fixed32SToF32x2_RN, /* fixed-point -> fp */ + + /* Binary operations */ + Iop_Max32Fx2, Iop_Min32Fx2, + /* Pairwise Min and Max. See integer pairwise operations for more + details. */ + Iop_PwMax32Fx2, Iop_PwMin32Fx2, + /* Note: For the following compares, the arm front-end assumes a + nan in a lane of either argument returns zero for that lane. */ + Iop_CmpEQ32Fx2, Iop_CmpGT32Fx2, Iop_CmpGE32Fx2, + + /* Vector Reciprocal Estimate finds an approximate reciprocal of each + element in the operand vector, and places the results in the destination + vector. */ + Iop_Recip32Fx2, + + /* Vector Reciprocal Step computes (2.0 - arg1 * arg2). + Note, that if one of the arguments is zero and another one is infinity + of arbitrary sign the result of the operation is 2.0. */ + Iop_Recps32Fx2, + + /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal + square root of each element in the operand vector. */ + Iop_Rsqrte32Fx2, + + /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0. + Note, that of one of the arguments is zero and another one is infiinty + of arbitrary sign the result of the operation is 1.5. */ + Iop_Rsqrts32Fx2, + + /* Unary */ + Iop_Neg32Fx2, Iop_Abs32Fx2, + /* ------------------ 64-bit SIMD Integer. ------------------ */ /* MISC (vector integer cmp != 0) */ @@ -662,54 +754,142 @@ typedef /* ADDITION (normal / unsigned sat / signed sat) */ Iop_Add8x8, Iop_Add16x4, Iop_Add32x2, - Iop_QAdd8Ux8, Iop_QAdd16Ux4, - Iop_QAdd8Sx8, Iop_QAdd16Sx4, + Iop_QAdd8Ux8, Iop_QAdd16Ux4, Iop_QAdd32Ux2, Iop_QAdd64Ux1, + Iop_QAdd8Sx8, Iop_QAdd16Sx4, Iop_QAdd32Sx2, Iop_QAdd64Sx1, + + /* PAIRWISE operations */ + /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) = + [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */ + Iop_PwAdd8x8, Iop_PwAdd16x4, Iop_PwAdd32x2, + Iop_PwMax8Sx8, Iop_PwMax16Sx4, Iop_PwMax32Sx2, + Iop_PwMax8Ux8, Iop_PwMax16Ux4, Iop_PwMax32Ux2, + Iop_PwMin8Sx8, Iop_PwMin16Sx4, Iop_PwMin32Sx2, + Iop_PwMin8Ux8, Iop_PwMin16Ux4, Iop_PwMin32Ux2, + /* Longening variant is unary. The resulting vector contains two times + less elements than operand, but they are two times wider. + Example: + Iop_PAddL16Ux4( [a,b,c,d] ) = [a+b,c+d] + where a+b and c+d are unsigned 32-bit values. */ + Iop_PwAddL8Ux8, Iop_PwAddL16Ux4, Iop_PwAddL32Ux2, + Iop_PwAddL8Sx8, Iop_PwAddL16Sx4, Iop_PwAddL32Sx2, /* SUBTRACTION (normal / unsigned sat / signed sat) */ Iop_Sub8x8, Iop_Sub16x4, Iop_Sub32x2, - Iop_QSub8Ux8, Iop_QSub16Ux4, - Iop_QSub8Sx8, Iop_QSub16Sx4, + Iop_QSub8Ux8, Iop_QSub16Ux4, Iop_QSub32Ux2, Iop_QSub64Ux1, + Iop_QSub8Sx8, Iop_QSub16Sx4, Iop_QSub32Sx2, Iop_QSub64Sx1, - /* MULTIPLICATION (normal / high half of signed/unsigned) */ - Iop_Mul16x4, Iop_Mul32x2, + /* ABSOLUTE VALUE */ + Iop_Abs8x8, Iop_Abs16x4, Iop_Abs32x2, + + /* MULTIPLICATION (normal / high half of signed/unsigned / plynomial ) */ + Iop_Mul8x8, Iop_Mul16x4, Iop_Mul32x2, + Iop_Mul32Fx2, Iop_MulHi16Ux4, Iop_MulHi16Sx4, + /* Plynomial multiplication treats it's arguments as coefficients of + polynoms over {0, 1}. */ + Iop_PolynomialMul8x8, + + /* Vector Saturating Doubling Multiply Returning High Half and + Vector Saturating Rounding Doubling Multiply Returning High Half */ + /* These IROp's multiply corresponding elements in two vectors, double + the results, and place the most significant half of the final results + in the destination vector. The results are truncated or rounded. If + any of the results overflow, they are saturated. */ + Iop_QDMulHi16Sx4, Iop_QDMulHi32Sx2, + Iop_QRDMulHi16Sx4, Iop_QRDMulHi32Sx2, /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */ Iop_Avg8Ux8, Iop_Avg16Ux4, /* MIN/MAX */ - Iop_Max16Sx4, - Iop_Max8Ux8, - Iop_Min16Sx4, - Iop_Min8Ux8, + Iop_Max8Sx8, Iop_Max16Sx4, Iop_Max32Sx2, + Iop_Max8Ux8, Iop_Max16Ux4, Iop_Max32Ux2, + Iop_Min8Sx8, Iop_Min16Sx4, Iop_Min32Sx2, + Iop_Min8Ux8, Iop_Min16Ux4, Iop_Min32Ux2, /* COMPARISON */ Iop_CmpEQ8x8, Iop_CmpEQ16x4, Iop_CmpEQ32x2, + Iop_CmpGT8Ux8, Iop_CmpGT16Ux4, Iop_CmpGT32Ux2, Iop_CmpGT8Sx8, Iop_CmpGT16Sx4, Iop_CmpGT32Sx2, + /* COUNT ones / leading zeroes / leading sign bits (not including topmost + bit) */ + Iop_Cnt8x8, + Iop_Clz8Sx8, Iop_Clz16Sx4, Iop_Clz32Sx2, + Iop_Cls8Sx8, Iop_Cls16Sx4, Iop_Cls32Sx2, + + /* VECTOR x VECTOR SHIFT / ROTATE */ + Iop_Shl8x8, Iop_Shl16x4, Iop_Shl32x2, + Iop_Shr8x8, Iop_Shr16x4, Iop_Shr32x2, + Iop_Sar8x8, Iop_Sar16x4, Iop_Sar32x2, + Iop_Sal8x8, Iop_Sal16x4, Iop_Sal32x2, Iop_Sal64x1, + /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */ Iop_ShlN8x8, Iop_ShlN16x4, Iop_ShlN32x2, - Iop_ShrN16x4, Iop_ShrN32x2, + Iop_ShrN8x8, Iop_ShrN16x4, Iop_ShrN32x2, Iop_SarN8x8, Iop_SarN16x4, Iop_SarN32x2, + /* VECTOR x VECTOR SATURATING SHIFT */ + Iop_QShl8x8, Iop_QShl16x4, Iop_QShl32x2, Iop_QShl64x1, + Iop_QSal8x8, Iop_QSal16x4, Iop_QSal32x2, Iop_QSal64x1, + /* VECTOR x INTEGER SATURATING SHIFT */ + Iop_QShlN8Sx8, Iop_QShlN16Sx4, Iop_QShlN32Sx2, Iop_QShlN64Sx1, + Iop_QShlN8x8, Iop_QShlN16x4, Iop_QShlN32x2, Iop_QShlN64x1, + Iop_QSalN8x8, Iop_QSalN16x4, Iop_QSalN32x2, Iop_QSalN64x1, + /* NARROWING -- narrow 2xI64 into 1xI64, hi half from left arg */ Iop_QNarrow16Ux4, Iop_QNarrow16Sx4, Iop_QNarrow32Sx2, - /* INTERLEAVING -- interleave lanes from low or high halves of + /* INTERLEAVING */ + /* Interleave lanes from low or high halves of operands. Most-significant result lane is from the left arg. */ Iop_InterleaveHI8x8, Iop_InterleaveHI16x4, Iop_InterleaveHI32x2, Iop_InterleaveLO8x8, Iop_InterleaveLO16x4, Iop_InterleaveLO32x2, + /* Interleave odd/even lanes of operands. Most-significant result lane + is from the left arg. Note that Interleave{Odd,Even}Lanes32x2 are + identical to Interleave{HI,LO}32x2 and so are omitted.*/ + Iop_InterleaveOddLanes8x8, Iop_InterleaveEvenLanes8x8, + Iop_InterleaveOddLanes16x4, Iop_InterleaveEvenLanes16x4, + /* CONCATENATION -- build a new value by concatenating either the even or odd lanes of both operands. Note that Cat{Odd,Even}Lanes32x2 are identical to Interleave{HI,LO}32x2 and so are omitted. */ - Iop_CatOddLanes16x4, Iop_CatEvenLanes16x4, + Iop_CatOddLanes8x8, Iop_CatOddLanes16x4, + Iop_CatEvenLanes8x8, Iop_CatEvenLanes16x4, + + /* GET / SET elements of VECTOR + GET is binop (I64, I8) -> I + SET is triop (I64, I8, I) -> I64 */ + /* Note: the arm back-end handles only constant second argument */ + Iop_GetElem8x8, Iop_GetElem16x4, Iop_GetElem32x2, + Iop_SetElem8x8, Iop_SetElem16x4, Iop_SetElem32x2, + + /* DUPLICATING -- copy value to all lanes */ + Iop_Dup8x8, Iop_Dup16x4, Iop_Dup32x2, + + /* EXTRACT -- copy 8-arg3 highest bytes from arg1 to 8-arg3 lowest bytes + of result and arg3 lowest bytes of arg2 to arg3 highest bytes of + result. + It is a triop: (I64, I64, I8) -> I64 */ + /* Note: the arm back-end handles only constant third argumnet. */ + Iop_Extract64, + + /* REVERSE the order of elements in each Half-words, Words, + Double-words */ + /* Examples: + Reverse16_8x8([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g] + Reverse32_8x8([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e] + Reverse64_8x8([a,b,c,d,e,f,g,h]) = [h,g,f,e,d,c,b,a] */ + Iop_Reverse16_8x8, + Iop_Reverse32_8x8, Iop_Reverse32_16x4, + Iop_Reverse64_8x8, Iop_Reverse64_16x4, Iop_Reverse64_32x2, /* PERMUTING -- copy src bytes to dst, as indexed by control vector bytes: @@ -718,6 +898,10 @@ typedef is undefined. */ Iop_Perm8x8, + /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate + See floating-point equiwalents for details. */ + Iop_Recip32x2, Iop_Rsqrte32x2, + /* ------------------ 128-bit SIMD FP. ------------------ */ /* --- 32x4 vector FP --- */ @@ -725,22 +909,59 @@ typedef /* binary */ Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4, Iop_Max32Fx4, Iop_Min32Fx4, - /* Note: For the following compares, the ppc front-end assumes a + Iop_Add32Fx2, Iop_Sub32Fx2, + /* Note: For the following compares, the ppc and arm front-ends assume a nan in a lane of either argument returns zero for that lane. */ - Iop_CmpEQ32Fx4, Iop_CmpLT32Fx4, Iop_CmpLE32Fx4, Iop_CmpUN32Fx4, + Iop_CmpEQ32Fx4, Iop_CmpLT32Fx4, Iop_CmpLE32Fx4, Iop_CmpUN32Fx4, Iop_CmpGT32Fx4, Iop_CmpGE32Fx4, + /* Vector Absolute */ + Iop_Abs32Fx4, + + /* Pairwise Max and Min. See integer pairwise operations for details. */ + Iop_PwMax32Fx4, Iop_PwMin32Fx4, + /* unary */ - Iop_Recip32Fx4, Iop_Sqrt32Fx4, Iop_RSqrt32Fx4, + Iop_Sqrt32Fx4, Iop_RSqrt32Fx4, + Iop_Neg32Fx4, + + /* Vector Reciprocal Estimate finds an approximate reciprocal of each + element in the operand vector, and places the results in the destination + vector. */ + Iop_Recip32Fx4, + + /* Vector Reciprocal Step computes (2.0 - arg1 * arg2). + Note, that if one of the arguments is zero and another one is infinity + of arbitrary sign the result of the operation is 2.0. */ + Iop_Recps32Fx4, + + /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal + square root of each element in the operand vector. */ + Iop_Rsqrte32Fx4, + + /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0. + Note, that of one of the arguments is zero and another one is infiinty + of arbitrary sign the result of the operation is 1.5. */ + Iop_Rsqrts32Fx4, + /* --- Int to/from FP conversion --- */ /* Unlike the standard fp conversions, these irops take no rounding mode argument. Instead the irop trailers _R{M,P,N,Z} indicate the mode: {-inf, +inf, nearest, zero} respectively. */ - Iop_I32UtoFx4, Iop_I32StoFx4, /* I32x4 -> F32x4 */ - Iop_QFtoI32Ux4_RZ, Iop_QFtoI32Sx4_RZ, /* F32x4 -> I32x4 */ + Iop_I32UtoFx4, Iop_I32StoFx4, /* I32x4 -> F32x4 */ + Iop_FtoI32Ux4_RZ, Iop_FtoI32Sx4_RZ, /* F32x4 -> I32x4 */ + Iop_QFtoI32Ux4_RZ, Iop_QFtoI32Sx4_RZ, /* F32x4 -> I32x4 (with saturation) */ Iop_RoundF32x4_RM, Iop_RoundF32x4_RP, /* round to fp integer */ Iop_RoundF32x4_RN, Iop_RoundF32x4_RZ, /* round to fp integer */ + /* Fixed32 format is floating-point number with fixed number of fraction + bits. The number of fraction bits is passed as a second argument of + type I8. */ + Iop_F32ToFixed32Ux4_RZ, Iop_F32ToFixed32Sx4_RZ, /* fp -> fixed-point */ + Iop_Fixed32UToF32x4_RN, Iop_Fixed32SToF32x4_RN, /* fixed-point -> fp */ + + /* --- Single to/from half conversion --- */ + Iop_F32toF16x4, Iop_F16toF32x4, /* F32x4 <-> F16x4 */ /* --- 32x4 lowest-lane-only scalar FP --- */ @@ -806,22 +1027,56 @@ typedef Iop_CmpNEZ8x16, Iop_CmpNEZ16x8, Iop_CmpNEZ32x4, Iop_CmpNEZ64x2, /* ADDITION (normal / unsigned sat / signed sat) */ - Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_Add64x2, - Iop_QAdd8Ux16, Iop_QAdd16Ux8, Iop_QAdd32Ux4, - Iop_QAdd8Sx16, Iop_QAdd16Sx8, Iop_QAdd32Sx4, + Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_Add64x2, + Iop_QAdd8Ux16, Iop_QAdd16Ux8, Iop_QAdd32Ux4, Iop_QAdd64Ux2, + Iop_QAdd8Sx16, Iop_QAdd16Sx8, Iop_QAdd32Sx4, Iop_QAdd64Sx2, /* SUBTRACTION (normal / unsigned sat / signed sat) */ - Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2, - Iop_QSub8Ux16, Iop_QSub16Ux8, Iop_QSub32Ux4, - Iop_QSub8Sx16, Iop_QSub16Sx8, Iop_QSub32Sx4, + Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2, + Iop_QSub8Ux16, Iop_QSub16Ux8, Iop_QSub32Ux4, Iop_QSub64Ux2, + Iop_QSub8Sx16, Iop_QSub16Sx8, Iop_QSub32Sx4, Iop_QSub64Sx2, /* MULTIPLICATION (normal / high half of signed/unsigned) */ - Iop_Mul16x8, - Iop_MulHi16Ux8, Iop_MulHi32Ux4, - Iop_MulHi16Sx8, Iop_MulHi32Sx4, + Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4, + Iop_MulHi16Ux8, Iop_MulHi32Ux4, + Iop_MulHi16Sx8, Iop_MulHi32Sx4, /* (widening signed/unsigned of even lanes, with lowest lane=zero) */ Iop_MullEven8Ux16, Iop_MullEven16Ux8, Iop_MullEven8Sx16, Iop_MullEven16Sx8, + /* FIXME: document these */ + Iop_Mull8Ux8, Iop_Mull8Sx8, + Iop_Mull16Ux4, Iop_Mull16Sx4, + Iop_Mull32Ux2, Iop_Mull32Sx2, + /* Vector Saturating Doubling Multiply Returning High Half and + Vector Saturating Rounding Doubling Multiply Returning High Half */ + /* These IROp's multiply corresponding elements in two vectors, double + the results, and place the most significant half of the final results + in the destination vector. The results are truncated or rounded. If + any of the results overflow, they are saturated. */ + Iop_QDMulHi16Sx8, Iop_QDMulHi32Sx4, + Iop_QRDMulHi16Sx8, Iop_QRDMulHi32Sx4, + /* Doubling saturating multiplication (long) (I64, I64) -> V128 */ + Iop_QDMulLong16Sx4, Iop_QDMulLong32Sx2, + /* Plynomial multiplication treats it's arguments as coefficients of + polynoms over {0, 1}. */ + Iop_PolynomialMul8x16, /* (V128, V128) -> V128 */ + Iop_PolynomialMull8x8, /* (I64, I64) -> V128 */ + + /* PAIRWISE operations */ + /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) = + [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */ + Iop_PwAdd8x16, Iop_PwAdd16x8, Iop_PwAdd32x4, + Iop_PwAdd32Fx2, + /* Longening variant is unary. The resulting vector contains two times + less elements than operand, but they are two times wider. + Example: + Iop_PwAddL16Ux4( [a,b,c,d] ) = [a+b,c+d] + where a+b and c+d are unsigned 32-bit values. */ + Iop_PwAddL8Ux16, Iop_PwAddL16Ux8, Iop_PwAddL32Ux4, + Iop_PwAddL8Sx16, Iop_PwAddL16Sx8, Iop_PwAddL32Sx4, + + /* ABSOLUTE VALUE */ + Iop_Abs8x16, Iop_Abs16x8, Iop_Abs32x4, /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */ Iop_Avg8Ux16, Iop_Avg16Ux8, Iop_Avg32Ux4, @@ -835,43 +1090,113 @@ typedef /* COMPARISON */ Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4, - Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, + Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2, Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4, + /* COUNT ones / leading zeroes / leading sign bits (not including topmost + bit) */ + Iop_Cnt8x16, + Iop_Clz8Sx16, Iop_Clz16Sx8, Iop_Clz32Sx4, + Iop_Cls8Sx16, Iop_Cls16Sx8, Iop_Cls32Sx4, + /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */ Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2, Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2, - Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, + Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2, /* VECTOR x VECTOR SHIFT / ROTATE */ - Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4, - Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4, - Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4, + Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4, Iop_Shl64x2, + Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4, Iop_Shr64x2, + Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4, Iop_Sar64x2, + Iop_Sal8x16, Iop_Sal16x8, Iop_Sal32x4, Iop_Sal64x2, Iop_Rol8x16, Iop_Rol16x8, Iop_Rol32x4, + /* VECTOR x VECTOR SATURATING SHIFT */ + Iop_QShl8x16, Iop_QShl16x8, Iop_QShl32x4, Iop_QShl64x2, + Iop_QSal8x16, Iop_QSal16x8, Iop_QSal32x4, Iop_QSal64x2, + /* VECTOR x INTEGER SATURATING SHIFT */ + Iop_QShlN8Sx16, Iop_QShlN16Sx8, Iop_QShlN32Sx4, Iop_QShlN64Sx2, + Iop_QShlN8x16, Iop_QShlN16x8, Iop_QShlN32x4, Iop_QShlN64x2, + Iop_QSalN8x16, Iop_QSalN16x8, Iop_QSalN32x4, Iop_QSalN64x2, + /* NARROWING -- narrow 2xV128 into 1xV128, hi half from left arg */ /* Note: the 16{U,S} and 32{U,S} are the pre-narrow lane widths. */ Iop_QNarrow16Ux8, Iop_QNarrow32Ux4, Iop_QNarrow16Sx8, Iop_QNarrow32Sx4, Iop_Narrow16x8, Iop_Narrow32x4, - - /* INTERLEAVING -- interleave lanes from low or high halves of + /* Shortening V128->I64, lo half from each element */ + Iop_Shorten16x8, Iop_Shorten32x4, Iop_Shorten64x2, + /* Saturating shortening from signed source to signed/unsigned destination */ + Iop_QShortenS16Sx8, Iop_QShortenS32Sx4, Iop_QShortenS64Sx2, + Iop_QShortenU16Sx8, Iop_QShortenU32Sx4, Iop_QShortenU64Sx2, + /* Saturating shortening from unsigned source to unsigned destination */ + Iop_QShortenU16Ux8, Iop_QShortenU32Ux4, Iop_QShortenU64Ux2, + + /* WIDENING */ + /* Longening --- sign or zero extends each element of the argument + vector to the twice original size. The resulting vector consists of + the same number of elements but each element and the vector itself + are two times wider. + All operations are I64->V128. + Example + Iop_Longen32Sx2( [a, b] ) = [c, d] + where c = Iop_32Sto64(a) and d = Iop_32Sto64(b) */ + Iop_Longen8Ux8, Iop_Longen16Ux4, Iop_Longen32Ux2, + Iop_Longen8Sx8, Iop_Longen16Sx4, Iop_Longen32Sx2, + + /* INTERLEAVING */ + /* Interleave lanes from low or high halves of operands. Most-significant result lane is from the left arg. */ Iop_InterleaveHI8x16, Iop_InterleaveHI16x8, Iop_InterleaveHI32x4, Iop_InterleaveHI64x2, - Iop_InterleaveLO8x16, Iop_InterleaveLO16x8, + Iop_InterleaveLO8x16, Iop_InterleaveLO16x8, Iop_InterleaveLO32x4, Iop_InterleaveLO64x2, + /* Interleave odd/even lanes of operands. Most-significant result lane + is from the left arg. */ + Iop_InterleaveOddLanes8x16, Iop_InterleaveEvenLanes8x16, + Iop_InterleaveOddLanes16x8, Iop_InterleaveEvenLanes16x8, + Iop_InterleaveOddLanes32x4, Iop_InterleaveEvenLanes32x4, + + /* CONCATENATION -- build a new value by concatenating either + the even or odd lanes of both operands. */ + Iop_CatOddLanes8x16, Iop_CatOddLanes16x8, Iop_CatOddLanes32x4, + Iop_CatEvenLanes8x16, Iop_CatEvenLanes16x8, Iop_CatEvenLanes32x4, + + /* GET elements of VECTOR + GET is binop (V128, I8) -> I */ + /* Note: the arm back-end handles only constant second argument. */ + Iop_GetElem8x16, Iop_GetElem16x8, Iop_GetElem32x4, Iop_GetElem64x2, /* DUPLICATING -- copy value to all lanes */ - Iop_Dup8x16, Iop_Dup16x8, Iop_Dup32x4, + Iop_Dup8x16, Iop_Dup16x8, Iop_Dup32x4, + + /* EXTRACT -- copy 16-arg3 highest bytes from arg1 to 16-arg3 lowest bytes + of result and arg3 lowest bytes of arg2 to arg3 highest bytes of + result. + It is a triop: (V128, V128, I8) -> V128 */ + /* Note: the ARM back end handles only constant arg3 in this operation. */ + Iop_ExtractV128, + + /* REVERSE the order of elements in each Half-words, Words, + Double-words */ + /* Examples: + Reverse32_16x8([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g] + Reverse64_16x8([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e] */ + Iop_Reverse16_8x16, + Iop_Reverse32_8x16, Iop_Reverse32_16x8, + Iop_Reverse64_8x16, Iop_Reverse64_16x8, Iop_Reverse64_32x4, /* PERMUTING -- copy src bytes to dst, as indexed by control vector bytes: for i in 0 .. 15 . result[i] = argL[ argR[i] ] argR[i] values may only be in the range 0 .. 15, else behaviour is undefined. */ - Iop_Perm8x16 + Iop_Perm8x16, + + /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate + See floating-point equiwalents for details. */ + Iop_Recip32x4, Iop_Rsqrte32x4 } IROp; @@ -1044,20 +1369,13 @@ struct _IRExpr { IRExpr* arg; /* operand */ } Unop; - /* A load from memory. If .isLL is True then this load also - lodges a reservation (ppc-style lwarx/ldarx operation). If - .isLL is True, then also, the address must be naturally - aligned - any misaligned addresses should be caught by a - dominating IR check and side exit. This alignment - restriction exists because on at least some LL/SC platforms - (ppc), lwarx etc will trap w/ SIGBUS on misaligned addresses, - and we have to actually generate lwarx on the host, and we - don't want it trapping on the host. - + /* A load from memory -- a normal load, not a load-linked. + Load-Linkeds (and Store-Conditionals) are instead represented + by IRStmt.LLSC since Load-Linkeds have side effects and so + are not semantically valid IRExpr's. ppIRExpr output: LD:(), eg. LDle:I32(t1) */ struct { - Bool isLL; /* True iff load makes a reservation */ IREndness end; /* Endian-ness of the load */ IRType ty; /* Type of the loaded value */ IRExpr* addr; /* Address being loaded from */ @@ -1141,8 +1459,7 @@ extern IRExpr* IRExpr_Triop ( IROp op, IRExpr* arg1, IRExpr* arg2, IRExpr* arg3 ); extern IRExpr* IRExpr_Binop ( IROp op, IRExpr* arg1, IRExpr* arg2 ); extern IRExpr* IRExpr_Unop ( IROp op, IRExpr* arg ); -extern IRExpr* IRExpr_Load ( Bool isLL, IREndness end, - IRType ty, IRExpr* addr ); +extern IRExpr* IRExpr_Load ( IREndness end, IRType ty, IRExpr* addr ); extern IRExpr* IRExpr_Const ( IRConst* con ); extern IRExpr* IRExpr_CCall ( IRCallee* cee, IRType retty, IRExpr** args ); extern IRExpr* IRExpr_Mux0X ( IRExpr* cond, IRExpr* expr0, IRExpr* exprX ); @@ -1166,6 +1483,8 @@ extern IRExpr** mkIRExprVec_6 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*, IRExpr*, IRExpr* ); extern IRExpr** mkIRExprVec_7 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*, IRExpr*, IRExpr*, IRExpr* ); +extern IRExpr** mkIRExprVec_8 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*, + IRExpr*, IRExpr*, IRExpr*, IRExpr*); /* IRExpr copiers: - shallowCopy: shallow-copy (ie. create a new vector that shares the @@ -1241,7 +1560,7 @@ typedef Ijk_SigBUS, /* current instruction synths SIGBUS */ /* Unfortunately, various guest-dependent syscall kinds. They all mean: do a syscall before continuing. */ - Ijk_Sys_syscall, /* amd64 'syscall', ppc 'sc' */ + Ijk_Sys_syscall, /* amd64 'syscall', ppc 'sc', arm 'svc #0' */ Ijk_Sys_int32, /* amd64/x86 'int $0x20' */ Ijk_Sys_int128, /* amd64/x86 'int $0x80' */ Ijk_Sys_int129, /* amd64/x86 'int $0x81' */ @@ -1483,6 +1802,7 @@ typedef Ist_WrTmp, Ist_Store, Ist_CAS, + Ist_LLSC, Ist_Dirty, Ist_MBE, /* META (maybe) */ Ist_Exit @@ -1578,28 +1898,13 @@ typedef IRExpr* data; /* Expression (RHS of assignment) */ } WrTmp; - /* Write a value to memory. Normally scRes is - IRTemp_INVALID, denoting a normal store. If scRes is not - IRTemp_INVALID, then this is a store-conditional, which - may fail or succeed depending on the outcome of a - previously lodged reservation on this address. scRes is - written 1 if the store succeeds and 0 if it fails, and - must have type Ity_I1. - - If scRes is not IRTemp_INVALID, then also, the address - must be naturally aligned - any misaligned addresses - should be caught by a dominating IR check and side exit. - This alignment restriction exists because on at least some - LL/SC platforms (ppc), stwcx. etc will trap w/ SIGBUS on - misaligned addresses, and we have to actually generate - stwcx. on the host, and we don't want it trapping on the - host. - + /* Write a value to memory. This is a normal store, not a + Store-Conditional. To represent a Store-Conditional, + instead use IRStmt.LLSC. ppIRStmt output: ST() = , eg. STle(t1) = t2 */ struct { IREndness end; /* Endianness of the store */ - IRTemp resSC; /* result of SC goes here (1 == success) */ IRExpr* addr; /* store address */ IRExpr* data; /* value to write */ } Store; @@ -1622,6 +1927,57 @@ typedef IRCAS* details; } CAS; + /* Either Load-Linked or Store-Conditional, depending on + STOREDATA. + + If STOREDATA is NULL then this is a Load-Linked, meaning + that data is loaded from memory as normal, but a + 'reservation' for the address is also lodged in the + hardware. + + result = Load-Linked(addr, end) + + The data transfer type is the type of RESULT (I32, I64, + etc). ppIRStmt output: + + result = LD-Linked(), eg. LDbe-Linked(t1) + + If STOREDATA is not NULL then this is a Store-Conditional, + hence: + + result = Store-Conditional(addr, storedata, end) + + The data transfer type is the type of STOREDATA and RESULT + has type Ity_I1. The store may fail or succeed depending + on the state of a previously lodged reservation on this + address. RESULT is written 1 if the store succeeds and 0 + if it fails. eg ppIRStmt output: + + result = ( ST-Cond() = ) + eg t3 = ( STbe-Cond(t1, t2) ) + + In all cases, the address must be naturally aligned for + the transfer type -- any misaligned addresses should be + caught by a dominating IR check and side exit. This + alignment restriction exists because on at least some + LL/SC platforms (ppc), stwcx. etc will trap w/ SIGBUS on + misaligned addresses, and we have to actually generate + stwcx. on the host, and we don't want it trapping on the + host. + + Summary of rules for transfer type: + STOREDATA == NULL (LL): + transfer type = type of RESULT + STOREDATA != NULL (SC): + transfer type = type of STOREDATA, and RESULT :: Ity_I1 + */ + struct { + IREndness end; + IRTemp result; + IRExpr* addr; + IRExpr* storedata; /* NULL => LL, non-NULL => SC */ + } LLSC; + /* Call (possibly conditionally) a C function that has side effects (ie. is "dirty"). See the comments above the IRDirty type declaration for more information. @@ -1668,9 +2024,10 @@ extern IRStmt* IRStmt_Put ( Int off, IRExpr* data ); extern IRStmt* IRStmt_PutI ( IRRegArray* descr, IRExpr* ix, Int bias, IRExpr* data ); extern IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data ); -extern IRStmt* IRStmt_Store ( IREndness end, - IRTemp resSC, IRExpr* addr, IRExpr* data ); +extern IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data ); extern IRStmt* IRStmt_CAS ( IRCAS* details ); +extern IRStmt* IRStmt_LLSC ( IREndness end, IRTemp result, + IRExpr* addr, IRExpr* storedata ); extern IRStmt* IRStmt_Dirty ( IRDirty* details ); extern IRStmt* IRStmt_MBE ( IRMBusEvent event ); extern IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* dst ); diff --git a/VEX/pub/libvex_trc_values.h b/VEX/pub/libvex_trc_values.h index 8430358..248fb31 100644 --- a/VEX/pub/libvex_trc_values.h +++ b/VEX/pub/libvex_trc_values.h @@ -1,42 +1,31 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (libvex_trc_values.h) is ---*/ -/*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin libvex_trc_values.h ---*/ /*---------------------------------------------------------------*/ /* - This file is part of LibVEX, a library for dynamic binary - instrumentation and translation. + This file is part of Valgrind, a dynamic binary instrumentation + framework. - Copyright (C) 2004-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net - This library is made available under a dual licensing scheme. + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. - If you link LibVEX against other code all of which is itself - licensed under the GNU General Public License, version 2 dated June - 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL - v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL - is missing, you can obtain a copy of the GPL v2 from the Free - Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - For any other uses of LibVEX, you must first obtain a commercial - license from OpenWorks LLP. Please contact info@open-works.co.uk - for information about commercial licensing. - - This software is provided by OpenWorks LLP "as is" and any express - or implied warranties, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose - are disclaimed. In no event shall OpenWorks LLP be liable for any - direct, indirect, incidental, special, exemplary, or consequential - damages (including, but not limited to, procurement of substitute - goods or services; loss of use, data, or profits; or business - interruption) however caused and on any theory of liability, - whether in contract, strict liability, or tort (including - negligence or otherwise) arising in any way out of the use of this - software, even if advised of the possibility of such damage. + The GNU General Public License is contained in the file COPYING. Neither the names of the U.S. Department of Energy nor the University of California nor the names of its contributors may be diff --git a/VEX/test_main.c b/VEX/test_main.c index 16c1973..2fc41a6 100644 --- a/VEX/test_main.c +++ b/VEX/test_main.c @@ -1,11 +1,38 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (test_main.c) is ---*/ -/*--- Copyright (C) 2005 OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin test_main.c ---*/ /*---------------------------------------------------------------*/ +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2004-2010 OpenWorks LLP + info@open-works.net + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. + + The GNU General Public License is contained in the file COPYING. + + Neither the names of the U.S. Department of Energy nor the + University of California nor the names of its contributors may be + used to endorse or promote products derived from this software + without prior written permission. +*/ + #include #include #include @@ -436,7 +463,7 @@ static void MC_helperc_value_check4_fail( void ) { } This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -1620,13 +1647,21 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, return binary16Ix8(mce, vatom1, vatom2); case Iop_Sub32x4: + case Iop_QSub32Sx4: + case Iop_QSub32Ux4: case Iop_CmpGT32Sx4: case Iop_CmpEQ32x4: case Iop_Add32x4: + case Iop_QAdd32Ux4: + case Iop_QAdd32Sx4: return binary32Ix4(mce, vatom1, vatom2); case Iop_Sub64x2: + case Iop_QSub64Ux2: + case Iop_QSub64Sx2: case Iop_Add64x2: + case Iop_QAdd64Ux2: + case Iop_QAdd64Sx2: return binary64Ix2(mce, vatom1, vatom2); case Iop_QNarrow32Sx4: @@ -2662,5 +2697,5 @@ IRSB* mc_instrument ( void* closureV, #endif /* UNUSED */ /*--------------------------------------------------------------------*/ -/*--- end mc_translate.c ---*/ +/*--- end test_main.c ---*/ /*--------------------------------------------------------------------*/ diff --git a/VEX/unused/dispatch.c b/VEX/unused/dispatch.c index a005821..d5fc6f3 100644 --- a/VEX/unused/dispatch.c +++ b/VEX/unused/dispatch.c @@ -1,9 +1,6 @@ /*---------------------------------------------------------------*/ -/*--- ---*/ -/*--- This file (dispatch.c) is ---*/ -/*--- Copyright (C) 2004 OpenWorks LLP. All rights reserved. ---*/ -/*--- ---*/ +/*--- begin dispatch.c ---*/ /*---------------------------------------------------------------*/ #include "basictypes.h" diff --git a/VEX/useful/cpuid.c b/VEX/useful/cpuid.c new file mode 100644 index 0000000..30d88f2 --- /dev/null +++ b/VEX/useful/cpuid.c @@ -0,0 +1,72 @@ + +#include + +typedef unsigned int UInt; +typedef unsigned long long int ULong; + +void cpuid ( UInt* eax, UInt* ebx, UInt* ecx, UInt* edx, + UInt index, UInt ecx_in ) +{ + UInt a,b,c,d; + asm volatile ("cpuid" + : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ + : "0" (index), "2"(ecx_in) ); + *eax = a; *ebx = b; *ecx = c; *edx = d; + printf("%08x %08x -> %08x %08x %08x %08x\n", + index,ecx_in, a,b,c,d ); +} + +int main ( void ) +{ + UInt eax, ebx, ecx, edx; + UInt maxidx, maxextidx, i,ecx_in; + + printf("\n"); + cpuid(&eax,&ebx,&ecx,&edx, 0,0); + maxidx = eax; + for (i = 1; i <= maxidx +2; i++) { + + cpuid(&eax,&ebx,&ecx,&edx, i,0); + + if (i == 4) { + printf("\n"); + for (ecx_in = 1; ecx_in < 10; ecx_in++) { + cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in); + } + printf("\n"); + } + + if (i == 0xb) { + printf("\n"); + for (ecx_in = 1; ecx_in < 10; ecx_in++) { + cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in); + } + printf("\n"); + } + + if (i == 0xd) { + printf("\n"); + for (ecx_in = 1; ecx_in < 5; ecx_in++) { + cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in); + } + printf("\n"); + } + + + } + + printf("\n"); + + cpuid(&eax,&ebx,&ecx,&edx, 0x80000000,0); + maxextidx = eax; + for (i = 0x80000001; i <= maxextidx +2; i++) { + cpuid(&eax,&ebx,&ecx,&edx, i,0); + } + + printf("invalid\n"); + cpuid(&eax,&ebx,&ecx,&edx, 1234,0); + cpuid(&eax,&ebx,&ecx,&edx, 0x800004d3,0); + + + return 0; +} diff --git a/auxprogs/Makefile.am b/auxprogs/Makefile.am index 38a643e..1563f4b 100644 --- a/auxprogs/Makefile.am +++ b/auxprogs/Makefile.am @@ -29,4 +29,6 @@ valgrind_listener_CPPFLAGS = $(AM_CPPFLAGS_PRI) -I$(top_srcdir)/coregrind valgrind_listener_CFLAGS = $(AM_CFLAGS_PRI) valgrind_listener_CCASFLAGS = $(AM_CCASFLAGS_PRI) valgrind_listener_LDFLAGS = $(AM_CFLAGS_PRI) - +if VGCONF_PLATFORMS_INCLUDE_X86_DARWIN +valgrind_listener_LDFLAGS += -Wl,-read_only_relocs -Wl,suppress +endif diff --git a/auxprogs/change-copyright-year b/auxprogs/change-copyright-year index 83ce7b0..4901df4 100755 --- a/auxprogs/change-copyright-year +++ b/auxprogs/change-copyright-year @@ -19,7 +19,7 @@ # change them. for i in `find . -name '*.[chS]' -type f -not -path '*.svn\/*'` ; do echo $i - perl -p -e 's/Copyright \(C\) 200([0-9])-2008/Copyright (C) 200$1-2009/' < $i > tmp.$$ + perl -p -e 's/Copyright \(C\) 200([0-9])-2009/Copyright (C) 200$1-2010/' < $i > tmp.$$ mv tmp.$$ $i done diff --git a/auxprogs/dump_insn_ppc.sh b/auxprogs/dump_insn_ppc.sh old mode 100644 new mode 100755 diff --git a/auxprogs/gsl16test b/auxprogs/gsl16test index 333a060..7abc34c 100755 --- a/auxprogs/gsl16test +++ b/auxprogs/gsl16test @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # Do an automated test which involves building and regtesting version # 1.6 of the GNU Scientific Library (gsl). This has proven to be a diff --git a/auxprogs/gsl19test b/auxprogs/gsl19test old mode 100644 new mode 100755 index 0491347..4b1d140 --- a/auxprogs/gsl19test +++ b/auxprogs/gsl19test @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # Do an automated test which involves building and regtesting version # 1.9 of the GNU Scientific Library (gsl). This has proven to be a diff --git a/auxprogs/posixtestsuite-1.5.1-diff-results b/auxprogs/posixtestsuite-1.5.1-diff-results old mode 100644 new mode 100755 diff --git a/auxprogs/valgrind-listener.c b/auxprogs/valgrind-listener.c index 4667288..ac47b6a 100644 --- a/auxprogs/valgrind-listener.c +++ b/auxprogs/valgrind-listener.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -32,6 +32,16 @@ /*---------------------------------------------------------------*/ +/* Include valgrind headers before system headers to avoid problems + with the system headers #defining things which are used as names + of structure members in vki headers. */ + +#include "pub_core_basics.h" +#include "pub_core_libcassert.h" // For VG_BUGS_TO +#include "pub_core_vki.h" // Avoids warnings from + // pub_core_libcfile.h +#include "pub_core_libcfile.h" // For VG_CLO_DEFAULT_LOGPORT + #include #include #include @@ -44,12 +54,6 @@ #include #include -#include "pub_core_basics.h" -#include "pub_core_libcassert.h" // For VG_BUGS_TO -#include "pub_core_vki.h" // Avoids warnings from - // pub_core_libcfile.h -#include "pub_core_libcfile.h" // For VG_CLO_DEFAULT_LOGPORT - /*---------------------------------------------------------------*/ diff --git a/cachegrind/Makefile.am b/cachegrind/Makefile.am index 94df249..8168081 100644 --- a/cachegrind/Makefile.am +++ b/cachegrind/Makefile.am @@ -8,7 +8,7 @@ EXTRA_DIST = \ # Headers, etc #---------------------------------------------------------------------------- -bin_SCRIPTS = cg_annotate +bin_SCRIPTS = cg_annotate cg_diff noinst_HEADERS = \ cg_arch.h \ @@ -26,6 +26,9 @@ cg_merge_CPPFLAGS = $(AM_CPPFLAGS_PRI) cg_merge_CFLAGS = $(AM_CFLAGS_PRI) cg_merge_CCASFLAGS = $(AM_CCASFLAGS_PRI) cg_merge_LDFLAGS = $(AM_CFLAGS_PRI) +if VGCONF_PLATFORMS_INCLUDE_X86_DARWIN +cg_merge_LDFLAGS += -Wl,-read_only_relocs -Wl,suppress +endif #---------------------------------------------------------------------------- # cachegrind- @@ -40,7 +43,8 @@ CACHEGRIND_SOURCES_COMMON = \ cg_main.c \ cg-x86-amd64.c \ cg-ppc32.c \ - cg-ppc64.c + cg-ppc64.c \ + cg-arm.c cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ $(CACHEGRIND_SOURCES_COMMON) @@ -54,6 +58,13 @@ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ $(CACHEGRIND_SOURCES_COMMON) @@ -67,6 +78,12 @@ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif diff --git a/cachegrind/cg-arm.c b/cachegrind/cg-arm.c new file mode 100644 index 0000000..28edb57 --- /dev/null +++ b/cachegrind/cg-arm.c @@ -0,0 +1,59 @@ + +/*--------------------------------------------------------------------*/ +/*--- ARM-specific definitions. cg-arm.c ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Cachegrind, a Valgrind tool for cache + profiling programs. + + Copyright (C) 2005-2010 Johan Bjork + jbjoerk@gmail.com + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#if defined(VGA_arm) + +#include "pub_tool_basics.h" +#include "pub_tool_libcbase.h" +#include "pub_tool_libcassert.h" +#include "pub_tool_libcprint.h" + +#include "cg_arch.h" + +void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, + Bool all_caches_clo_defined) +{ + // Set caches to default (for Cortex-A8 ?) + *I1c = (cache_t) { 16384, 4, 64 }; + *D1c = (cache_t) { 16384, 4, 64 }; + *LLc = (cache_t) { 262144, 8, 64 }; + + if (!all_caches_clo_defined) { + VG_(message)(Vg_DebugMsg, + "Warning: Cannot auto-detect cache config on ARM, using one " + "or more defaults\n"); + } +} + +#endif // #if defined(VGA_arm) + +/*--------------------------------------------------------------------*/ +/*--- end cg-arm.c ---*/ +/*--------------------------------------------------------------------*/ diff --git a/cachegrind/cg-ppc32.c b/cachegrind/cg-ppc32.c index 5f9f3a9..ea6d2cd 100644 --- a/cachegrind/cg-ppc32.c +++ b/cachegrind/cg-ppc32.c @@ -7,7 +7,7 @@ This file is part of Cachegrind, a Valgrind tool for cache profiling programs. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -37,13 +37,13 @@ #include "cg_arch.h" -void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, +void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, Bool all_caches_clo_defined) { // Set caches to default. *I1c = (cache_t) { 65536, 2, 64 }; *D1c = (cache_t) { 65536, 2, 64 }; - *L2c = (cache_t) { 262144, 8, 64 }; + *LLc = (cache_t) { 262144, 8, 64 }; // Warn if config not completely specified from cmd line. Note that // this message is slightly different from the one we give on x86/AMD64 @@ -57,7 +57,7 @@ void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, // if (!all_caches_clo_defined) { VG_(dmsg)("Warning: Cannot auto-detect cache config on PPC32, using one " - "or more defaults \n"); + "or more defaults\n"); } } diff --git a/cachegrind/cg-ppc64.c b/cachegrind/cg-ppc64.c index 76d18c7..bb05cee 100644 --- a/cachegrind/cg-ppc64.c +++ b/cachegrind/cg-ppc64.c @@ -7,7 +7,7 @@ This file is part of Cachegrind, a Valgrind tool for cache profiling programs. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -37,13 +37,13 @@ #include "cg_arch.h" -void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, +void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, Bool all_caches_clo_defined) { // Set caches to default. *I1c = (cache_t) { 65536, 2, 64 }; *D1c = (cache_t) { 65536, 2, 64 }; - *L2c = (cache_t) { 262144, 8, 64 }; + *LLc = (cache_t) { 262144, 8, 64 }; // Warn if config not completely specified from cmd line. Note that // this message is slightly different from the one we give on x86/AMD64 @@ -57,7 +57,7 @@ void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, // if (!all_caches_clo_defined) { VG_(dmsg)("Warning: Cannot auto-detect cache config on PPC64, using one " - "or more defaults \n"); + "or more defaults\n"); } } diff --git a/cachegrind/cg-x86-amd64.c b/cachegrind/cg-x86-amd64.c index b94ea14..6794319 100644 --- a/cachegrind/cg-x86-amd64.c +++ b/cachegrind/cg-x86-amd64.c @@ -7,7 +7,7 @@ This file is part of Cachegrind, a Valgrind tool for cache profiling programs. - Copyright (C) 2002-2009 Nicholas Nethercote + Copyright (C) 2002-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -38,7 +38,7 @@ #include "cg_arch.h" -// All CPUID info taken from sandpile.org/a32/cpuid.htm */ +// All CPUID info taken from sandpile.org/ia32/cpuid.htm */ // Probably only works for Intel and AMD chips, and probably only for some of // them. @@ -54,9 +54,12 @@ static void micro_ops_warn(Int actual_size, Int used_size, Int line_size) * array of pre-defined configurations for various parts of the memory * hierarchy. * According to Intel Processor Identification, App Note 485. + * + * If a L3 cache is found, then data for it rather than the L2 + * is returned via *LLc. */ static -Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) +Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* LLc) { Int cpuid1_eax; Int cpuid1_ignore; @@ -65,6 +68,14 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) UChar info[16]; Int i, trials; Bool L2_found = False; + /* If we see L3 cache info, copy it into L3c. Then, at the end, + copy it into *LLc. Hence if a L3 cache is specified, *LLc will + eventually contain a description of it rather than the L2 cache. + The use of the L3c intermediary makes this process independent + of the order in which the cache specifications appear in + info[]. */ + Bool L3_found = False; + cache_t L3c = { 0, 0, 0 }; if (level < 2) { VG_(dmsg)("warning: CPUID level < 2 for Intel processor (%d)\n", level); @@ -97,15 +108,17 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) /* TLB info, ignore */ case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: - case 0x4f: case 0x50: case 0x51: case 0x52: + case 0x4f: case 0x50: case 0x51: case 0x52: case 0x55: case 0x56: case 0x57: case 0x59: - case 0x5b: case 0x5c: case 0x5d: - case 0xb0: case 0xb1: + case 0x5a: case 0x5b: case 0x5c: case 0x5d: + case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xba: case 0xc0: + case 0xca: break; case 0x06: *I1c = (cache_t) { 8, 4, 32 }; break; case 0x08: *I1c = (cache_t) { 16, 4, 32 }; break; + case 0x09: *I1c = (cache_t) { 32, 4, 64 }; break; case 0x30: *I1c = (cache_t) { 32, 8, 64 }; break; case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break; @@ -119,14 +132,39 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) case 0x90: case 0x96: case 0x9b: VG_(tool_panic)("IA-64 cache detected?!"); - case 0x22: case 0x23: case 0x25: case 0x29: - case 0x46: case 0x47: case 0x4a: case 0x4b: case 0x4c: case 0x4d: - VG_(dmsg)("warning: L3 cache detected but ignored\n"); - break; + /* L3 cache info. */ + case 0x22: L3c = (cache_t) { 512, 4, 64 }; L3_found = True; break; + case 0x23: L3c = (cache_t) { 1024, 8, 64 }; L3_found = True; break; + case 0x25: L3c = (cache_t) { 2048, 8, 64 }; L3_found = True; break; + case 0x29: L3c = (cache_t) { 4096, 8, 64 }; L3_found = True; break; + case 0x46: L3c = (cache_t) { 4096, 4, 64 }; L3_found = True; break; + case 0x47: L3c = (cache_t) { 8192, 8, 64 }; L3_found = True; break; + case 0x4a: L3c = (cache_t) { 6144, 12, 64 }; L3_found = True; break; + case 0x4b: L3c = (cache_t) { 8192, 16, 64 }; L3_found = True; break; + case 0x4c: L3c = (cache_t) { 12288, 12, 64 }; L3_found = True; break; + case 0x4d: L3c = (cache_t) { 16384, 16, 64 }; L3_found = True; break; + case 0xd0: L3c = (cache_t) { 512, 4, 64 }; L3_found = True; break; + case 0xd1: L3c = (cache_t) { 1024, 4, 64 }; L3_found = True; break; + case 0xd2: L3c = (cache_t) { 2048, 4, 64 }; L3_found = True; break; + case 0xd6: L3c = (cache_t) { 1024, 8, 64 }; L3_found = True; break; + case 0xd7: L3c = (cache_t) { 2048, 8, 64 }; L3_found = True; break; + case 0xd8: L3c = (cache_t) { 4096, 8, 64 }; L3_found = True; break; + case 0xdc: L3c = (cache_t) { 1536, 12, 64 }; L3_found = True; break; + case 0xdd: L3c = (cache_t) { 3072, 12, 64 }; L3_found = True; break; + case 0xde: L3c = (cache_t) { 6144, 12, 64 }; L3_found = True; break; + case 0xe2: L3c = (cache_t) { 2048, 16, 64 }; L3_found = True; break; + case 0xe3: L3c = (cache_t) { 4096, 16, 64 }; L3_found = True; break; + case 0xe4: L3c = (cache_t) { 8192, 16, 64 }; L3_found = True; break; + case 0xea: L3c = (cache_t) { 12288, 24, 64 }; L3_found = True; break; + case 0xeb: L3c = (cache_t) { 18432, 24, 64 }; L3_found = True; break; + case 0xec: L3c = (cache_t) { 24576, 24, 64 }; L3_found = True; break; + + /* Described as "MLC" in Intel documentation */ + case 0x21: *LLc = (cache_t) { 256, 8, 64 }; L2_found = True; break; /* These are sectored, whatever that means */ - case 0x39: *L2c = (cache_t) { 128, 4, 64 }; L2_found = True; break; - case 0x3c: *L2c = (cache_t) { 256, 4, 64 }; L2_found = True; break; + case 0x39: *LLc = (cache_t) { 128, 4, 64 }; L2_found = True; break; + case 0x3c: *LLc = (cache_t) { 256, 4, 64 }; L2_found = True; break; /* If a P6 core, this means "no L2 cache". If a P4 core, this means "no L3 cache". @@ -135,20 +173,21 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) case 0x40: break; - case 0x41: *L2c = (cache_t) { 128, 4, 32 }; L2_found = True; break; - case 0x42: *L2c = (cache_t) { 256, 4, 32 }; L2_found = True; break; - case 0x43: *L2c = (cache_t) { 512, 4, 32 }; L2_found = True; break; - case 0x44: *L2c = (cache_t) { 1024, 4, 32 }; L2_found = True; break; - case 0x45: *L2c = (cache_t) { 2048, 4, 32 }; L2_found = True; break; - case 0x48: *L2c = (cache_t) { 3072,12, 64 }; L2_found = True; break; + case 0x41: *LLc = (cache_t) { 128, 4, 32 }; L2_found = True; break; + case 0x42: *LLc = (cache_t) { 256, 4, 32 }; L2_found = True; break; + case 0x43: *LLc = (cache_t) { 512, 4, 32 }; L2_found = True; break; + case 0x44: *LLc = (cache_t) { 1024, 4, 32 }; L2_found = True; break; + case 0x45: *LLc = (cache_t) { 2048, 4, 32 }; L2_found = True; break; + case 0x48: *LLc = (cache_t) { 3072, 12, 64 }; L2_found = True; break; + case 0x4e: *LLc = (cache_t) { 6144, 24, 64 }; L2_found = True; break; case 0x49: - if ((family == 15) && (model == 6)) - /* On Xeon MP (family F, model 6), this is for L3 */ - VG_(dmsg)("warning: L3 cache detected but ignored\n"); - else - *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True; - break; - case 0x4e: *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; break; + if (family == 15 && model == 6) { + /* On Xeon MP (family F, model 6), this is for L3 */ + L3c = (cache_t) { 4096, 16, 64 }; L3_found = True; + } else { + *LLc = (cache_t) { 4096, 16, 64 }; L2_found = True; + } + break; /* These are sectored, whatever that means */ case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */ @@ -174,24 +213,25 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) micro_ops_warn(32, 32, 32); break; + /* not sectored, whatever that might mean */ + case 0x78: *LLc = (cache_t) { 1024, 4, 64 }; L2_found = True; break; + /* These are sectored, whatever that means */ - case 0x79: *L2c = (cache_t) { 128, 8, 64 }; L2_found = True; break; - case 0x7a: *L2c = (cache_t) { 256, 8, 64 }; L2_found = True; break; - case 0x7b: *L2c = (cache_t) { 512, 8, 64 }; L2_found = True; break; - case 0x7c: *L2c = (cache_t) { 1024, 8, 64 }; L2_found = True; break; - case 0x7d: *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True; break; - case 0x7e: *L2c = (cache_t) { 256, 8, 128 }; L2_found = True; break; - - case 0x7f: *L2c = (cache_t) { 512, 2, 64 }; L2_found = True; break; - case 0x80: *L2c = (cache_t) { 512, 8, 64 }; L2_found = True; break; - - case 0x81: *L2c = (cache_t) { 128, 8, 32 }; L2_found = True; break; - case 0x82: *L2c = (cache_t) { 256, 8, 32 }; L2_found = True; break; - case 0x83: *L2c = (cache_t) { 512, 8, 32 }; L2_found = True; break; - case 0x84: *L2c = (cache_t) { 1024, 8, 32 }; L2_found = True; break; - case 0x85: *L2c = (cache_t) { 2048, 8, 32 }; L2_found = True; break; - case 0x86: *L2c = (cache_t) { 512, 4, 64 }; L2_found = True; break; - case 0x87: *L2c = (cache_t) { 1024, 8, 64 }; L2_found = True; break; + case 0x79: *LLc = (cache_t) { 128, 8, 64 }; L2_found = True; break; + case 0x7a: *LLc = (cache_t) { 256, 8, 64 }; L2_found = True; break; + case 0x7b: *LLc = (cache_t) { 512, 8, 64 }; L2_found = True; break; + case 0x7c: *LLc = (cache_t) { 1024, 8, 64 }; L2_found = True; break; + case 0x7d: *LLc = (cache_t) { 2048, 8, 64 }; L2_found = True; break; + case 0x7e: *LLc = (cache_t) { 256, 8, 128 }; L2_found = True; break; + case 0x7f: *LLc = (cache_t) { 512, 2, 64 }; L2_found = True; break; + case 0x80: *LLc = (cache_t) { 512, 8, 64 }; L2_found = True; break; + case 0x81: *LLc = (cache_t) { 128, 8, 32 }; L2_found = True; break; + case 0x82: *LLc = (cache_t) { 256, 8, 32 }; L2_found = True; break; + case 0x83: *LLc = (cache_t) { 512, 8, 32 }; L2_found = True; break; + case 0x84: *LLc = (cache_t) { 1024, 8, 32 }; L2_found = True; break; + case 0x85: *LLc = (cache_t) { 2048, 8, 32 }; L2_found = True; break; + case 0x86: *LLc = (cache_t) { 512, 4, 64 }; L2_found = True; break; + case 0x87: *LLc = (cache_t) { 1024, 8, 64 }; L2_found = True; break; /* Ignore prefetch information */ case 0xf0: case 0xf1: @@ -204,8 +244,15 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) } } + /* If we found a L3 cache, throw away the L2 data and use the L3's instead. */ + if (L3_found) { + VG_(dmsg)("warning: L3 cache found, using its data for the LL simulation.\n"); + *LLc = L3c; + L2_found = True; + } + if (!L2_found) - VG_(dmsg)("warning: L2 cache not installed, ignore L2 results.\n"); + VG_(dmsg)("warning: L2 cache not installed, ignore LL results.\n"); return 0; } @@ -232,14 +279,37 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) * 0x630) have a bug and misreport their L2 size as 1KB (it's really 64KB), * so we detect that. * - * Returns 0 on success, non-zero on failure. + * Returns 0 on success, non-zero on failure. As with the Intel code + * above, if a L3 cache is found, then data for it rather than the L2 + * is returned via *LLc. */ + +/* A small helper */ +static Int decode_AMD_cache_L2_L3_assoc ( Int bits_15_12 ) +{ + /* Decode a L2/L3 associativity indication. It is encoded + differently from the I1/D1 associativity. Returns 1 + (direct-map) as a safe but suboptimal result for unknown + encodings. */ + switch (bits_15_12 & 0xF) { + case 1: return 1; case 2: return 2; + case 4: return 4; case 6: return 8; + case 8: return 16; case 0xA: return 32; + case 0xB: return 48; case 0xC: return 64; + case 0xD: return 96; case 0xE: return 128; + case 0xF: /* fully associative */ + case 0: /* L2/L3 cache or TLB is disabled */ + default: + return 1; + } +} + static -Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c) +Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* LLc) { UInt ext_level; UInt dummy, model; - UInt I1i, D1i, L2i; + UInt I1i, D1i, L2i, L3i; VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy); @@ -250,7 +320,7 @@ Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c) } VG_(cpuid)(0x80000005, &dummy, &dummy, &D1i, &I1i); - VG_(cpuid)(0x80000006, &dummy, &dummy, &L2i, &dummy); + VG_(cpuid)(0x80000006, &dummy, &dummy, &L2i, &L3i); VG_(cpuid)(0x1, &model, &dummy, &dummy, &dummy); @@ -268,15 +338,26 @@ Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c) I1c->assoc = (I1i >> 16) & 0xff; I1c->line_size = (I1i >> 0) & 0xff; - L2c->size = (L2i >> 16) & 0xffff; /* Nb: different bits used for L2 */ - L2c->assoc = (L2i >> 12) & 0xf; - L2c->line_size = (L2i >> 0) & 0xff; + LLc->size = (L2i >> 16) & 0xffff; /* Nb: different bits used for L2 */ + LLc->assoc = decode_AMD_cache_L2_L3_assoc((L2i >> 12) & 0xf); + LLc->line_size = (L2i >> 0) & 0xff; + + if (((L3i >> 18) & 0x3fff) > 0) { + /* There's an L3 cache. Replace *LLc contents with this info. */ + /* NB: the test in the if is "if L3 size > 0 ". I don't know if + this is the right way to test presence-vs-absence of L3. I + can't see any guidance on this in the AMD documentation. */ + LLc->size = ((L3i >> 18) & 0x3fff) * 512; + LLc->assoc = decode_AMD_cache_L2_L3_assoc((L3i >> 12) & 0xf); + LLc->line_size = (L3i >> 0) & 0xff; + VG_(dmsg)("warning: L3 cache found, using its data for the L2 simulation.\n"); + } return 0; } static -Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c) +Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* LLc) { Int level, ret; Char vendor_id[13]; @@ -297,10 +378,10 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c) /* Only handling Intel and AMD chips... no Cyrix, Transmeta, etc */ if (0 == VG_(strcmp)(vendor_id, "GenuineIntel")) { - ret = Intel_cache_info(level, I1c, D1c, L2c); + ret = Intel_cache_info(level, I1c, D1c, LLc); } else if (0 == VG_(strcmp)(vendor_id, "AuthenticAMD")) { - ret = AMD_cache_info(I1c, D1c, L2c); + ret = AMD_cache_info(I1c, D1c, LLc); } else if (0 == VG_(strcmp)(vendor_id, "CentaurHauls")) { /* Total kludge. Pretend to be a VIA Nehemiah. */ @@ -310,9 +391,9 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c) I1c->size = 64; I1c->assoc = 4; I1c->line_size = 16; - L2c->size = 64; - L2c->assoc = 16; - L2c->line_size = 16; + LLc->size = 64; + LLc->assoc = 16; + LLc->line_size = 16; ret = 0; } else { @@ -323,13 +404,13 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c) /* Successful! Convert sizes from KB to bytes */ I1c->size *= 1024; D1c->size *= 1024; - L2c->size *= 1024; + LLc->size *= 1024; return ret; } -void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, +void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, Bool all_caches_clo_defined) { Int res; @@ -337,10 +418,10 @@ void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, // Set caches to default. *I1c = (cache_t) { 65536, 2, 64 }; *D1c = (cache_t) { 65536, 2, 64 }; - *L2c = (cache_t) { 262144, 8, 64 }; + *LLc = (cache_t) { 262144, 8, 64 }; // Then replace with any info we can get from CPUID. - res = get_caches_from_CPUID(I1c, D1c, L2c); + res = get_caches_from_CPUID(I1c, D1c, LLc); // Warn if CPUID failed and config not completely specified from cmd line. if (res != 0 && !all_caches_clo_defined) { diff --git a/cachegrind/cg_annotate.in b/cachegrind/cg_annotate.in index 29d9426..9dc9565 100644 --- a/cachegrind/cg_annotate.in +++ b/cachegrind/cg_annotate.in @@ -84,7 +84,7 @@ my %fn_totals; # Individual CCs, organised by filename and line_num for easy annotation. # hash(filename => hash(line_num => CC array)) -my %all_ind_CCs; +my %allCCs; # Files chosen for annotation on the command line. # key = basename (trimmed of any directory), value = full filename @@ -120,7 +120,7 @@ my @sort_order; # handled this proportion of all the events thresholded. my @thresholds; -my $default_threshold = 99; +my $default_threshold = 0.1; my $single_threshold = $default_threshold; @@ -149,8 +149,8 @@ usage: cg_annotate [options] cachegrind-out-file [source-files...] --version show version --show=A,B,C only show figures for events A,B,C [all] --sort=A,B,C sort columns by events A,B,C [event column order] - --threshold=<0--100> percentage of counts (of primary sort event) we - are interested in [$default_threshold%] + --threshold=<0--20> a function is shown if it accounts for more than x% of + the counts of the primary sort event [$default_threshold] --auto=yes|no annotate all source files containing functions that helped reach the event count threshold [no] --context=N print N lines of context before and after @@ -168,6 +168,12 @@ END # Used in various places of output. my $fancy = '-' x 80 . "\n"; +sub safe_div($$) +{ + my ($x, $y) = @_; + return ($y == 0 ? 0 : $x / $y); +} + #----------------------------------------------------------------------------- # Argument and option handling #----------------------------------------------------------------------------- @@ -211,7 +217,7 @@ sub process_cmd_line() # --threshold=X (tolerates a trailing '%') } elsif ($arg =~ /^--threshold=([\d\.]+)%?$/) { $single_threshold = $1; - ($1 >= 0 && $1 <= 100) or die($usage); + ($1 >= 0 && $1 <= 20) or die($usage); # --auto=yes|no } elsif ($arg =~ /^--auto=yes$/) { @@ -371,64 +377,61 @@ sub read_input_file() # the primary sort event, and 0% for the rest. if (not @thresholds) { foreach my $e (@sort_order) { - push(@thresholds, 0); + push(@thresholds, 100); } $thresholds[0] = $single_threshold; } - my $curr_file; - my $curr_fn; - my $curr_name; + my $currFileName; + my $currFileFuncName; - my $curr_fn_CC = []; - my $curr_file_ind_CCs = {}; # hash(line_num => CC) + my $currFuncCC; + my $currFileCCs = {}; # hash(line_num => CC) # Read body of input file. while () { s/#.*$//; # remove comments - if (s/^(\d+)\s+//) { - my $line_num = $1; + if (s/^(-?\d+)\s+//) { + my $lineNum = $1; my $CC = line_to_CC($_); - add_array_a_to_b($CC, $curr_fn_CC); + defined($currFuncCC) || die; + add_array_a_to_b($CC, $currFuncCC); - # If curr_file is selected, add CC to curr_file list. We look for + # If currFileName is selected, add CC to currFileName list. We look for # full filename matches; or, if auto-annotating, we have to # remember everything -- we won't know until the end what's needed. - if ($auto_annotate || defined $user_ann_files{$curr_file}) { - my $tmp = $curr_file_ind_CCs->{$line_num}; - $tmp = [] unless defined $tmp; - add_array_a_to_b($CC, $tmp); - $curr_file_ind_CCs->{$line_num} = $tmp; + defined($currFileCCs) || die; + if ($auto_annotate || defined $user_ann_files{$currFileName}) { + my $currLineCC = $currFileCCs->{$lineNum}; + if (not defined $currLineCC) { + $currLineCC = []; + $currFileCCs->{$lineNum} = $currLineCC; + } + add_array_a_to_b($CC, $currLineCC); } } elsif (s/^fn=(.*)$//) { - # Commit result from previous function - $fn_totals{$curr_name} = $curr_fn_CC if (defined $curr_name); - - # Setup new one - $curr_fn = $1; - $curr_name = "$curr_file:$curr_fn"; - $curr_fn_CC = $fn_totals{$curr_name}; - $curr_fn_CC = [] unless (defined $curr_fn_CC); + $currFileFuncName = "$currFileName:$1"; + $currFuncCC = $fn_totals{$currFileFuncName}; + if (not defined $currFuncCC) { + $currFuncCC = []; + $fn_totals{$currFileFuncName} = $currFuncCC; + } } elsif (s/^fl=(.*)$//) { - $all_ind_CCs{$curr_file} = $curr_file_ind_CCs - if (defined $curr_file); - - $curr_file = $1; - $curr_file_ind_CCs = $all_ind_CCs{$curr_file}; - $curr_file_ind_CCs = {} unless (defined $curr_file_ind_CCs); + $currFileName = $1; + $currFileCCs = $allCCs{$currFileName}; + if (not defined $currFileCCs) { + $currFileCCs = {}; + $allCCs{$currFileName} = $currFileCCs; + } + # Assume that a "fn=" line is followed by a "fl=" line. + $currFileFuncName = undef; } elsif (s/^\s*$//) { # blank, do nothing } elsif (s/^summary:\s+//) { - # Finish up handling final filename/fn_name counts - $fn_totals{"$curr_file:$curr_fn"} = $curr_fn_CC - if (defined $curr_file && defined $curr_fn); - $all_ind_CCs{$curr_file} = - $curr_file_ind_CCs if (defined $curr_file); - $summary_CC = line_to_CC($_); (scalar(@$summary_CC) == @events) or die("Line $.: summary event and total event mismatch\n"); @@ -497,7 +500,7 @@ sub mycmp ($$) $x = -1 unless defined $x; $y = -1 unless defined $y; - my $cmp = $y <=> $x; # reverse sort + my $cmp = abs($y) <=> abs($x); # reverse sort of absolute size if (0 != $cmp) { return $cmp; } @@ -508,7 +511,7 @@ sub mycmp ($$) sub commify ($) { my ($val) = @_; - 1 while ($val =~ s/^(\d+)(\d{3})/$1,$2/); + 1 while ($val =~ s/^(-?\d+)(\d{3})/$1,$2/); return $val; } @@ -614,16 +617,18 @@ sub print_summary_and_fn_totals () # Print functions, stopping when the threshold has been reached. foreach my $fn_name (@fn_fullnames) { + my $fn_CC = $fn_totals{$fn_name}; + # Stop when we've reached all the thresholds - my $reached_all_thresholds = 1; + my $any_thresholds_exceeded = 0; foreach my $i (0 .. scalar @thresholds - 1) { - my $prop = $curr_totals[$i] * 100 / $summary_CC->[$sort_order[$i]]; - $reached_all_thresholds &&= ($prop >= $thresholds[$i]); + my $prop = safe_div(abs($fn_CC->[$sort_order[$i]] * 100), + abs($summary_CC->[$sort_order[$i]])); + $any_thresholds_exceeded ||= ($prop >= $thresholds[$i]); } - last if $reached_all_thresholds; + last if not $any_thresholds_exceeded; # Print function results - my $fn_CC = $fn_totals{$fn_name}; print_CC($fn_CC, $fn_CC_col_widths); print(" $fn_name\n"); @@ -761,7 +766,7 @@ sub annotate_ann_files($) print("$fancy"); # Get file's CCs - my $src_file_CCs = $all_ind_CCs{$src_file}; + my $src_file_CCs = $allCCs{$src_file}; if (!defined $src_file_CCs) { print(" No information has been collected for $src_file\n\n"); next LOOP; @@ -877,7 +882,8 @@ sub annotate_ann_files($) foreach (my $i = 0; $i < @$summary_CC; $i++) { $percent_printed_CC->[$i] = sprintf("%.0f", - $printed_totals_CC->[$i] / $summary_CC->[$i] * 100); + 100 * safe_div(abs($printed_totals_CC->[$i]), + abs($summary_CC->[$i]))); } my $pp_CC_col_widths = compute_CC_col_widths($percent_printed_CC); print($fancy); diff --git a/cachegrind/cg_arch.h b/cachegrind/cg_arch.h index 9090908..23f1a2c 100644 --- a/cachegrind/cg_arch.h +++ b/cachegrind/cg_arch.h @@ -7,7 +7,7 @@ This file is part of Cachegrind, a Valgrind tool for cache profiling programs. - Copyright (C) 2002-2009 Nicholas Nethercote + Copyright (C) 2002-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -33,14 +33,14 @@ // For cache simulation typedef struct { - int size; // bytes - int assoc; - int line_size; // bytes + Int size; // bytes + Int assoc; + Int line_size; // bytes } cache_t; -// Gives the configuration of I1, D1 and L2 caches. They get overridden +// Gives the configuration of I1, D1 and LL caches. They get overridden // by any cache configurations specified on the command line. -void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, +void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, Bool all_caches_clo_defined); #endif // __CG_ARCH_H diff --git a/cachegrind/cg_branchpred.c b/cachegrind/cg_branchpred.c index e19a3d3..4eb6982 100644 --- a/cachegrind/cg_branchpred.c +++ b/cachegrind/cg_branchpred.c @@ -7,7 +7,7 @@ This file is part of Cachegrind, a Valgrind tool for cache profiling programs. - Copyright (C) 2002-2009 Nicholas Nethercote + Copyright (C) 2002-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -44,7 +44,7 @@ /* How many bits at the bottom of an instruction address are guaranteed to be zero? */ -#if defined(VGA_ppc32) || defined(VGA_ppc64) +#if defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm) # define N_IADDR_LO_ZERO_BITS 2 #elif defined(VGA_x86) || defined(VGA_amd64) # define N_IADDR_LO_ZERO_BITS 0 diff --git a/cachegrind/cg_diff.in b/cachegrind/cg_diff.in new file mode 100755 index 0000000..951066e --- /dev/null +++ b/cachegrind/cg_diff.in @@ -0,0 +1,328 @@ +#! @PERL@ + +##--------------------------------------------------------------------## +##--- Cachegrind's differencer. cg_diff.in ---## +##--------------------------------------------------------------------## + +# This file is part of Cachegrind, a Valgrind tool for cache +# profiling programs. +# +# Copyright (C) 2002-2010 Nicholas Nethercote +# njn@valgrind.org +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of the +# License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA +# 02111-1307, USA. +# +# The GNU General Public License is contained in the file COPYING. + +#---------------------------------------------------------------------------- +# This is a very cut-down and modified version of cg_annotate. +#---------------------------------------------------------------------------- + +use warnings; +use strict; + +#---------------------------------------------------------------------------- +# Global variables +#---------------------------------------------------------------------------- + +# Version number +my $version = "@VERSION@"; + +# Usage message. +my $usage = < + + options for the user, with defaults in [ ], are: + -h --help show this message + -v --version show version + --mod-filename= a Perl search-and-replace expression that is applied + to filenames, eg. --mod-filename='s/prog[0-9]/projN/' + + cg_diff is Copyright (C) 2010-2010 Nicholas Nethercote. + and licensed under the GNU General Public License, version 2. + Bug reports, feedback, admiration, abuse, etc, to: njn\@valgrind.org. + +END +; + +# --mod-filename expression +my $mod_filename = undef; + +#----------------------------------------------------------------------------- +# Argument and option handling +#----------------------------------------------------------------------------- +sub process_cmd_line() +{ + my ($file1, $file2) = (undef, undef); + + for my $arg (@ARGV) { + + if ($arg =~ /^-/) { + # --version + if ($arg =~ /^-v$|^--version$/) { + die("cg_diff-$version\n"); + + } elsif ($arg =~ /^--mod-filename=(.*)/) { + $mod_filename = $1; + + } else { # -h and --help fall under this case + die($usage); + } + + } elsif (not defined($file1)) { + $file1 = $arg; + + } elsif (not defined($file2)) { + $file2 = $arg; + + } else { + die($usage); + } + } + + # Must have specified two input files. + if (not defined $file1 or not defined $file2) { + die($usage); + } + + return ($file1, $file2); +} + +#----------------------------------------------------------------------------- +# Reading of input file +#----------------------------------------------------------------------------- +sub max ($$) +{ + my ($x, $y) = @_; + return ($x > $y ? $x : $y); +} + +# Add the two arrays; any '.' entries are ignored. Two tricky things: +# 1. If $a2->[$i] is undefined, it defaults to 0 which is what we want; we turn +# off warnings to allow this. This makes things about 10% faster than +# checking for definedness ourselves. +# 2. We don't add an undefined count or a ".", even though it's value is 0, +# because we don't want to make an $a2->[$i] that is undef become 0 +# unnecessarily. +sub add_array_a_to_b ($$) +{ + my ($a, $b) = @_; + + my $n = max(scalar @$a, scalar @$b); + $^W = 0; + foreach my $i (0 .. $n-1) { + $b->[$i] += $a->[$i] if (defined $a->[$i] && "." ne $a->[$i]); + } + $^W = 1; +} + +sub sub_array_b_from_a ($$) +{ + my ($a, $b) = @_; + + my $n = max(scalar @$a, scalar @$b); + $^W = 0; + foreach my $i (0 .. $n-1) { + $a->[$i] -= $b->[$i]; # XXX: doesn't handle '.' entries + } + $^W = 1; +} + +# Add each event count to the CC array. '.' counts become undef, as do +# missing entries (implicitly). +sub line_to_CC ($$) +{ + my ($line, $numEvents) = @_; + + my @CC = (split /\s+/, $line); + (@CC <= $numEvents) or die("Line $.: too many event counts\n"); + return \@CC; +} + +sub read_input_file($) +{ + my ($input_file) = @_; + + open(INPUTFILE, "< $input_file") + || die "Cannot open $input_file for reading\n"; + + # Read "desc:" lines. + my $desc; + my $line; + while ($line = ) { + if ($line =~ s/desc:\s+//) { + $desc .= $line; + } else { + last; + } + } + + # Read "cmd:" line (Nb: will already be in $line from "desc:" loop above). + ($line =~ s/^cmd:\s+//) or die("Line $.: missing command line\n"); + my $cmd = $line; + chomp($cmd); # Remove newline + + # Read "events:" line. We make a temporary hash in which the Nth event's + # value is N, which is useful for handling --show/--sort options below. + $line = ; + (defined $line && $line =~ s/^events:\s+//) + or die("Line $.: missing events line\n"); + my @events = split(/\s+/, $line); + my $numEvents = scalar @events; + + my $currFileName; + my $currFileFuncName; + + my %CCs; # hash("$filename#$funcname" => CC array) + my $currCC = undef; # CC array + + my $summaryCC; + + # Read body of input file. + while () { + s/#.*$//; # remove comments + if (s/^(\d+)\s+//) { + my $CC = line_to_CC($_, $numEvents); + defined($currCC) || die; + add_array_a_to_b($CC, $currCC); + + } elsif (s/^fn=(.*)$//) { + defined($currFileName) || die; + $currFileFuncName = "$currFileName#$1"; + $currCC = $CCs{$currFileFuncName}; + if (not defined $currCC) { + $currCC = []; + $CCs{$currFileFuncName} = $currCC; + } + + } elsif (s/^fl=(.*)$//) { + $currFileName = $1; + if (defined $mod_filename) { + eval "\$currFileName =~ $mod_filename"; + } + # Assume that a "fn=" line is followed by a "fl=" line. + $currFileFuncName = undef; + + } elsif (s/^\s*$//) { + # blank, do nothing + + } elsif (s/^summary:\s+//) { + $summaryCC = line_to_CC($_, $numEvents); + (scalar(@$summaryCC) == @events) + or die("Line $.: summary event and total event mismatch\n"); + + } else { + warn("WARNING: line $. malformed, ignoring\n"); + } + } + + # Check if summary line was present + if (not defined $summaryCC) { + die("missing final summary line, aborting\n"); + } + + close(INPUTFILE); + + return ($cmd, \@events, \%CCs, $summaryCC); +} + +#---------------------------------------------------------------------------- +# "main()" +#---------------------------------------------------------------------------- +# Commands seen in the files. Need not match. +my $cmd1; +my $cmd2; + +# Events seen in the files. They must match. +my $events1; +my $events2; + +# Individual CCs, organised by filename/funcname/line_num. +# hashref("$filename#$funcname", CC array) +my $CCs1; +my $CCs2; + +# Total counts for summary (an arrayref). +my $summaryCC1; +my $summaryCC2; + +#---------------------------------------------------------------------------- +# Read the input files +#---------------------------------------------------------------------------- +my ($file1, $file2) = process_cmd_line(); +($cmd1, $events1, $CCs1, $summaryCC1) = read_input_file($file1); +($cmd2, $events2, $CCs2, $summaryCC2) = read_input_file($file2); + +#---------------------------------------------------------------------------- +# Check the events match +#---------------------------------------------------------------------------- +my $n = max(scalar @$events1, scalar @$events2); +$^W = 0; # turn off warnings, because we might hit undefs +foreach my $i (0 .. $n-1) { + ($events1->[$i] eq $events2->[$i]) || die "events don't match, aborting\n"; +} +$^W = 1; + +#---------------------------------------------------------------------------- +# Do the subtraction: CCs2 -= CCs1 +#---------------------------------------------------------------------------- +while (my ($filefuncname, $CC1) = each(%$CCs1)) { + my $CC2 = $CCs2->{$filefuncname}; + if (not defined $CC2) { + $CC2 = []; + sub_array_b_from_a($CC2, $CC1); # CC2 -= CC1 + $CCs2->{$filefuncname} = $CC2; + } else { + sub_array_b_from_a($CC2, $CC1); # CC2 -= CC1 + } +} +sub_array_b_from_a($summaryCC2, $summaryCC1); + +#---------------------------------------------------------------------------- +# Print the result, in CCs2 +#---------------------------------------------------------------------------- +print("desc: Files compared: $file1; $file2\n"); +print("cmd: $cmd1; $cmd2\n"); +print("events: "); +for my $e (@$events1) { + print(" $e"); +} +print("\n"); + +while (my ($filefuncname, $CC) = each(%$CCs2)) { + + my @x = split(/#/, $filefuncname); + (scalar @x == 2) || die; + + print("fl=$x[0]\n"); + print("fn=$x[1]\n"); + + print("0"); + foreach my $n (@$CC) { + print(" $n"); + } + print("\n"); +} + +print("summary:"); +foreach my $n (@$summaryCC2) { + print(" $n"); +} +print("\n"); + +##--------------------------------------------------------------------## +##--- end ---## +##--------------------------------------------------------------------## diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c index b8c0a62..ecdd706 100644 --- a/cachegrind/cg_main.c +++ b/cachegrind/cg_main.c @@ -8,7 +8,7 @@ This file is part of Cachegrind, a Valgrind tool for cache profiling programs. - Copyright (C) 2002-2009 Nicholas Nethercote + Copyright (C) 2002-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -77,7 +77,7 @@ typedef struct { ULong a; /* total # memory accesses of this kind */ ULong m1; /* misses in the first level cache */ - ULong m2; /* misses in the second level cache */ + ULong mL; /* misses in the second level cache */ } CacheCC; @@ -268,13 +268,13 @@ static LineCC* get_lineCC(Addr origAddr) lineCC->loc.line = loc.line; lineCC->Ir.a = 0; lineCC->Ir.m1 = 0; - lineCC->Ir.m2 = 0; + lineCC->Ir.mL = 0; lineCC->Dr.a = 0; lineCC->Dr.m1 = 0; - lineCC->Dr.m2 = 0; + lineCC->Dr.mL = 0; lineCC->Dw.a = 0; lineCC->Dw.m1 = 0; - lineCC->Dw.m2 = 0; + lineCC->Dw.mL = 0; lineCC->Bc.b = 0; lineCC->Bc.mp = 0; lineCC->Bi.b = 0; @@ -289,13 +289,37 @@ static LineCC* get_lineCC(Addr origAddr) /*--- Cache simulation functions ---*/ /*------------------------------------------------------------*/ +// Only used with --cache-sim=no. +static VG_REGPARM(1) +void log_1I(InstrInfo* n) +{ + n->parent->Ir.a++; +} + +// Only used with --cache-sim=no. +static VG_REGPARM(2) +void log_2I(InstrInfo* n, InstrInfo* n2) +{ + n->parent->Ir.a++; + n2->parent->Ir.a++; +} + +// Only used with --cache-sim=no. +static VG_REGPARM(3) +void log_3I(InstrInfo* n, InstrInfo* n2, InstrInfo* n3) +{ + n->parent->Ir.a++; + n2->parent->Ir.a++; + n3->parent->Ir.a++; +} + static VG_REGPARM(1) void log_1I_0D_cache_access(InstrInfo* n) { //VG_(printf)("1I_0D : CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n", // n, n->instr_addr, n->instr_len); cachesim_I1_doref(n->instr_addr, n->instr_len, - &n->parent->Ir.m1, &n->parent->Ir.m2); + &n->parent->Ir.m1, &n->parent->Ir.mL); n->parent->Ir.a++; } @@ -307,10 +331,10 @@ void log_2I_0D_cache_access(InstrInfo* n, InstrInfo* n2) // n, n->instr_addr, n->instr_len, // n2, n2->instr_addr, n2->instr_len); cachesim_I1_doref(n->instr_addr, n->instr_len, - &n->parent->Ir.m1, &n->parent->Ir.m2); + &n->parent->Ir.m1, &n->parent->Ir.mL); n->parent->Ir.a++; cachesim_I1_doref(n2->instr_addr, n2->instr_len, - &n2->parent->Ir.m1, &n2->parent->Ir.m2); + &n2->parent->Ir.m1, &n2->parent->Ir.mL); n2->parent->Ir.a++; } @@ -324,13 +348,13 @@ void log_3I_0D_cache_access(InstrInfo* n, InstrInfo* n2, InstrInfo* n3) // n2, n2->instr_addr, n2->instr_len, // n3, n3->instr_addr, n3->instr_len); cachesim_I1_doref(n->instr_addr, n->instr_len, - &n->parent->Ir.m1, &n->parent->Ir.m2); + &n->parent->Ir.m1, &n->parent->Ir.mL); n->parent->Ir.a++; cachesim_I1_doref(n2->instr_addr, n2->instr_len, - &n2->parent->Ir.m1, &n2->parent->Ir.m2); + &n2->parent->Ir.m1, &n2->parent->Ir.mL); n2->parent->Ir.a++; cachesim_I1_doref(n3->instr_addr, n3->instr_len, - &n3->parent->Ir.m1, &n3->parent->Ir.m2); + &n3->parent->Ir.m1, &n3->parent->Ir.mL); n3->parent->Ir.a++; } @@ -341,11 +365,11 @@ void log_1I_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size) // " daddr=0x%010lx, dsize=%lu\n", // n, n->instr_addr, n->instr_len, data_addr, data_size); cachesim_I1_doref(n->instr_addr, n->instr_len, - &n->parent->Ir.m1, &n->parent->Ir.m2); + &n->parent->Ir.m1, &n->parent->Ir.mL); n->parent->Ir.a++; cachesim_D1_doref(data_addr, data_size, - &n->parent->Dr.m1, &n->parent->Dr.m2); + &n->parent->Dr.m1, &n->parent->Dr.mL); n->parent->Dr.a++; } @@ -356,11 +380,11 @@ void log_1I_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size) // " daddr=0x%010lx, dsize=%lu\n", // n, n->instr_addr, n->instr_len, data_addr, data_size); cachesim_I1_doref(n->instr_addr, n->instr_len, - &n->parent->Ir.m1, &n->parent->Ir.m2); + &n->parent->Ir.m1, &n->parent->Ir.mL); n->parent->Ir.a++; cachesim_D1_doref(data_addr, data_size, - &n->parent->Dw.m1, &n->parent->Dw.m2); + &n->parent->Dw.m1, &n->parent->Dw.mL); n->parent->Dw.a++; } @@ -370,7 +394,7 @@ void log_0I_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size) //VG_(printf)("0I_1Dr: CCaddr=0x%010lx, daddr=0x%010lx, dsize=%lu\n", // n, data_addr, data_size); cachesim_D1_doref(data_addr, data_size, - &n->parent->Dr.m1, &n->parent->Dr.m2); + &n->parent->Dr.m1, &n->parent->Dr.mL); n->parent->Dr.a++; } @@ -380,7 +404,7 @@ void log_0I_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size) //VG_(printf)("0I_1Dw: CCaddr=0x%010lx, daddr=0x%010lx, dsize=%lu\n", // n, data_addr, data_size); cachesim_D1_doref(data_addr, data_size, - &n->parent->Dw.m1, &n->parent->Dw.m2); + &n->parent->Dw.m1, &n->parent->Dw.mL); n->parent->Dw.a++; } @@ -708,8 +732,13 @@ static void flushEvents ( CgState* cgs ) else if (ev2 && ev3 && ev2->tag == Ev_Ir && ev3->tag == Ev_Ir) { - helperName = "log_3I_0D_cache_access"; - helperAddr = &log_3I_0D_cache_access; + if (clo_cache_sim) { + helperName = "log_3I_0D_cache_access"; + helperAddr = &log_3I_0D_cache_access; + } else { + helperName = "log_3I"; + helperAddr = &log_3I; + } argv = mkIRExprVec_3( i_node_expr, mkIRExpr_HWord( (HWord)ev2->inode ), mkIRExpr_HWord( (HWord)ev3->inode ) ); @@ -719,8 +748,13 @@ static void flushEvents ( CgState* cgs ) /* Merge an Ir with one following Ir. */ else if (ev2 && ev2->tag == Ev_Ir) { - helperName = "log_2I_0D_cache_access"; - helperAddr = &log_2I_0D_cache_access; + if (clo_cache_sim) { + helperName = "log_2I_0D_cache_access"; + helperAddr = &log_2I_0D_cache_access; + } else { + helperName = "log_2I"; + helperAddr = &log_2I; + } argv = mkIRExprVec_2( i_node_expr, mkIRExpr_HWord( (HWord)ev2->inode ) ); regparms = 2; @@ -728,8 +762,13 @@ static void flushEvents ( CgState* cgs ) } /* No merging possible; emit as-is. */ else { - helperName = "log_1I_0D_cache_access"; - helperAddr = &log_1I_0D_cache_access; + if (clo_cache_sim) { + helperName = "log_1I_0D_cache_access"; + helperAddr = &log_1I_0D_cache_access; + } else { + helperName = "log_1I"; + helperAddr = &log_1I; + } argv = mkIRExprVec_1( i_node_expr ); regparms = 1; i++; @@ -1053,60 +1092,82 @@ IRSB* cg_instrument ( VgCallbackClosure* closure, break; } - case Ist_Exit: { - /* Stuff to widen the guard expression to a host word, so - we can pass it to the branch predictor simulation - functions easily. */ - Bool inverted; - Addr64 nia, sea; - IRConst* dst; - IROp tyW = hWordTy; - IROp widen = tyW==Ity_I32 ? Iop_1Uto32 : Iop_1Uto64; - IROp opXOR = tyW==Ity_I32 ? Iop_Xor32 : Iop_Xor64; - IRTemp guard1 = newIRTemp(cgs.sbOut->tyenv, Ity_I1); - IRTemp guardW = newIRTemp(cgs.sbOut->tyenv, tyW); - IRTemp guard = newIRTemp(cgs.sbOut->tyenv, tyW); - IRExpr* one = tyW==Ity_I32 ? IRExpr_Const(IRConst_U32(1)) - : IRExpr_Const(IRConst_U64(1)); - - /* First we need to figure out whether the side exit got - inverted by the ir optimiser. To do that, figure out - the next (fallthrough) instruction's address and the - side exit address and see if they are the same. */ - nia = cia + (Addr64)isize; - if (tyW == Ity_I32) - nia &= 0xFFFFFFFFULL; - - /* Side exit address */ - dst = st->Ist.Exit.dst; - if (tyW == Ity_I32) { - tl_assert(dst->tag == Ico_U32); - sea = (Addr64)(UInt)dst->Ico.U32; + case Ist_LLSC: { + IRType dataTy; + if (st->Ist.LLSC.storedata == NULL) { + /* LL */ + dataTy = typeOfIRTemp(tyenv, st->Ist.LLSC.result); + addEvent_Dr( &cgs, curr_inode, + sizeofIRType(dataTy), st->Ist.LLSC.addr ); } else { - tl_assert(tyW == Ity_I64); - tl_assert(dst->tag == Ico_U64); - sea = dst->Ico.U64; + /* SC */ + dataTy = typeOfIRExpr(tyenv, st->Ist.LLSC.storedata); + addEvent_Dw( &cgs, curr_inode, + sizeofIRType(dataTy), st->Ist.LLSC.addr ); } + break; + } - inverted = nia == sea; - - /* Widen the guard expression. */ - addStmtToIRSB( cgs.sbOut, - IRStmt_WrTmp( guard1, st->Ist.Exit.guard )); - addStmtToIRSB( cgs.sbOut, - IRStmt_WrTmp( guardW, - IRExpr_Unop(widen, - IRExpr_RdTmp(guard1))) ); - /* If the exit is inverted, invert the sense of the guard. */ - addStmtToIRSB( - cgs.sbOut, - IRStmt_WrTmp( - guard, - inverted ? IRExpr_Binop(opXOR, IRExpr_RdTmp(guardW), one) - : IRExpr_RdTmp(guardW) - )); - /* And post the event. */ - addEvent_Bc( &cgs, curr_inode, IRExpr_RdTmp(guard) ); + case Ist_Exit: { + // call branch predictor only if this is a branch in guest code + if ( (st->Ist.Exit.jk == Ijk_Boring) || + (st->Ist.Exit.jk == Ijk_Call) || + (st->Ist.Exit.jk == Ijk_Ret) ) + { + /* Stuff to widen the guard expression to a host word, so + we can pass it to the branch predictor simulation + functions easily. */ + Bool inverted; + Addr64 nia, sea; + IRConst* dst; + IRType tyW = hWordTy; + IROp widen = tyW==Ity_I32 ? Iop_1Uto32 : Iop_1Uto64; + IROp opXOR = tyW==Ity_I32 ? Iop_Xor32 : Iop_Xor64; + IRTemp guard1 = newIRTemp(cgs.sbOut->tyenv, Ity_I1); + IRTemp guardW = newIRTemp(cgs.sbOut->tyenv, tyW); + IRTemp guard = newIRTemp(cgs.sbOut->tyenv, tyW); + IRExpr* one = tyW==Ity_I32 ? IRExpr_Const(IRConst_U32(1)) + : IRExpr_Const(IRConst_U64(1)); + + /* First we need to figure out whether the side exit got + inverted by the ir optimiser. To do that, figure out + the next (fallthrough) instruction's address and the + side exit address and see if they are the same. */ + nia = cia + (Addr64)isize; + if (tyW == Ity_I32) + nia &= 0xFFFFFFFFULL; + + /* Side exit address */ + dst = st->Ist.Exit.dst; + if (tyW == Ity_I32) { + tl_assert(dst->tag == Ico_U32); + sea = (Addr64)(UInt)dst->Ico.U32; + } else { + tl_assert(tyW == Ity_I64); + tl_assert(dst->tag == Ico_U64); + sea = dst->Ico.U64; + } + + inverted = nia == sea; + + /* Widen the guard expression. */ + addStmtToIRSB( cgs.sbOut, + IRStmt_WrTmp( guard1, st->Ist.Exit.guard )); + addStmtToIRSB( cgs.sbOut, + IRStmt_WrTmp( guardW, + IRExpr_Unop(widen, + IRExpr_RdTmp(guard1))) ); + /* If the exit is inverted, invert the sense of the guard. */ + addStmtToIRSB( + cgs.sbOut, + IRStmt_WrTmp( + guard, + inverted ? IRExpr_Binop(opXOR, IRExpr_RdTmp(guardW), one) + : IRExpr_RdTmp(guardW) + )); + /* And post the event. */ + addEvent_Bc( &cgs, curr_inode, IRExpr_RdTmp(guard) ); + } /* We may never reach the next statement, so need to flush all outstanding transactions now. */ @@ -1131,7 +1192,7 @@ IRSB* cg_instrument ( VgCallbackClosure* closure, /* Deal with branches to unknown destinations. Except ignore ones which are function returns as we assume the return stack predictor never mispredicts. */ - if (sbIn->jumpkind == Ijk_Boring) { + if ((sbIn->jumpkind == Ijk_Boring) || (sbIn->jumpkind == Ijk_Call)) { if (0) { ppIRExpr( sbIn->next ); VG_(printf)("\n"); } switch (sbIn->next->tag) { case Iex_Const: @@ -1173,74 +1234,71 @@ IRSB* cg_instrument ( VgCallbackClosure* closure, static cache_t clo_I1_cache = UNDEFINED_CACHE; static cache_t clo_D1_cache = UNDEFINED_CACHE; -static cache_t clo_L2_cache = UNDEFINED_CACHE; +static cache_t clo_LL_cache = UNDEFINED_CACHE; -/* Checks cache config is ok; makes it so if not. */ -static -void check_cache(cache_t* cache, Char *name) +// Checks cache config is ok. Returns NULL if ok, or a pointer to an error +// string otherwise. +static Char* check_cache(cache_t* cache) { - /* Simulator requires line size and set count to be powers of two */ - if (( cache->size % (cache->line_size * cache->assoc) != 0) || - (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) { - VG_(umsg)("error: %s set count not a power of two; aborting.\n", name); - VG_(exit)(1); + // Simulator requires set count to be a power of two. + if ((cache->size % (cache->line_size * cache->assoc) != 0) || + (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) + { + return "Cache set count is not a power of two.\n"; } + // Simulator requires line size to be a power of two. if (-1 == VG_(log2)(cache->line_size)) { - VG_(umsg)("error: %s line size of %dB not a power of two; aborting.\n", - name, cache->line_size); - VG_(exit)(1); + return "Cache line size is not a power of two.\n"; } // Then check line size >= 16 -- any smaller and a single instruction could // straddle three cache lines, which breaks a simulation assertion and is // stupid anyway. if (cache->line_size < MIN_LINE_SIZE) { - VG_(umsg)("error: %s line size of %dB too small; aborting.\n", - name, cache->line_size); - VG_(exit)(1); + return "Cache line size is too small.\n"; } /* Then check cache size > line size (causes seg faults if not). */ if (cache->size <= cache->line_size) { - VG_(umsg)("error: %s cache size of %dB <= line size of %dB; aborting.\n", - name, cache->size, cache->line_size); - VG_(exit)(1); + return "Cache size <= line size.\n"; } /* Then check assoc <= (size / line size) (seg faults otherwise). */ if (cache->assoc > (cache->size / cache->line_size)) { - VG_(umsg)("warning: %s associativity > (size / line size); aborting.\n", - name); - VG_(exit)(1); + return "Cache associativity > (size / line size).\n"; } + + return NULL; } static -void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c) +void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* LLc) { #define DEFINED(L) (-1 != L.size || -1 != L.assoc || -1 != L.line_size) - Int n_clos = 0; + Char* checkRes; // Count how many were defined on the command line. - if (DEFINED(clo_I1_cache)) { n_clos++; } - if (DEFINED(clo_D1_cache)) { n_clos++; } - if (DEFINED(clo_L2_cache)) { n_clos++; } + Bool all_caches_clo_defined = + (DEFINED(clo_I1_cache) && + DEFINED(clo_D1_cache) && + DEFINED(clo_LL_cache)); // Set the cache config (using auto-detection, if supported by the - // architecture) - VG_(configure_caches)( I1c, D1c, L2c, (3 == n_clos) ); + // architecture). + VG_(configure_caches)( I1c, D1c, LLc, all_caches_clo_defined ); + + // Check the default/auto-detected values. + checkRes = check_cache(I1c); tl_assert(!checkRes); + checkRes = check_cache(D1c); tl_assert(!checkRes); + checkRes = check_cache(LLc); tl_assert(!checkRes); - // Then replace with any defined on the command line. + // Then replace with any defined on the command line. (Already checked in + // parse_cache_opt().) if (DEFINED(clo_I1_cache)) { *I1c = clo_I1_cache; } if (DEFINED(clo_D1_cache)) { *D1c = clo_D1_cache; } - if (DEFINED(clo_L2_cache)) { *L2c = clo_L2_cache; } - - // Then check values and fix if not acceptable. - check_cache(I1c, "I1"); - check_cache(D1c, "D1"); - check_cache(L2c, "L2"); + if (DEFINED(clo_LL_cache)) { *LLc = clo_LL_cache; } if (VG_(clo_verbosity) >= 2) { VG_(umsg)("Cache configuration used:\n"); @@ -1248,8 +1306,8 @@ void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c) I1c->size, I1c->assoc, I1c->line_size); VG_(umsg)(" D1: %dB, %d-way, %dB lines\n", D1c->size, D1c->assoc, D1c->line_size); - VG_(umsg)(" L2: %dB, %d-way, %dB lines\n", - L2c->size, L2c->assoc, L2c->line_size); + VG_(umsg)(" LL: %dB, %d-way, %dB lines\n", + LLc->size, LLc->assoc, LLc->line_size); } #undef CMD_LINE_DEFINED } @@ -1296,12 +1354,12 @@ static void fprint_CC_table_and_calc_totals(void) VG_(free)(cachegrind_out_file); } - // "desc:" lines (giving I1/D1/L2 cache configuration). The spaces after + // "desc:" lines (giving I1/D1/LL cache configuration). The spaces after // the 2nd colon makes cg_annotate's output look nicer. VG_(sprintf)(buf, "desc: I1 cache: %s\n" "desc: D1 cache: %s\n" - "desc: L2 cache: %s\n", - I1.desc_line, D1.desc_line, L2.desc_line); + "desc: LL cache: %s\n", + I1.desc_line, D1.desc_line, LL.desc_line); VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); // "cmd:" line @@ -1321,19 +1379,20 @@ static void fprint_CC_table_and_calc_totals(void) } // "events:" line if (clo_cache_sim && clo_branch_sim) { - VG_(sprintf)(buf, "\nevents: Ir I1mr I2mr Dr D1mr D2mr Dw D1mw D2mw " + VG_(sprintf)(buf, "\nevents: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw " "Bc Bcm Bi Bim\n"); } else if (clo_cache_sim && !clo_branch_sim) { - VG_(sprintf)(buf, "\nevents: Ir I1mr I2mr Dr D1mr D2mr Dw D1mw D2mw " + VG_(sprintf)(buf, "\nevents: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw " "\n"); } else if (!clo_cache_sim && clo_branch_sim) { VG_(sprintf)(buf, "\nevents: Ir " "Bc Bcm Bi Bim\n"); } - else - tl_assert(0); /* can't happen */ + else { + VG_(sprintf)(buf, "\nevents: Ir\n"); + } VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); @@ -1371,9 +1430,9 @@ static void fprint_CC_table_and_calc_totals(void) " %llu %llu %llu" " %llu %llu %llu %llu\n", lineCC->loc.line, - lineCC->Ir.a, lineCC->Ir.m1, lineCC->Ir.m2, - lineCC->Dr.a, lineCC->Dr.m1, lineCC->Dr.m2, - lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.m2, + lineCC->Ir.a, lineCC->Ir.m1, lineCC->Ir.mL, + lineCC->Dr.a, lineCC->Dr.m1, lineCC->Dr.mL, + lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.mL, lineCC->Bc.b, lineCC->Bc.mp, lineCC->Bi.b, lineCC->Bi.mp); } @@ -1382,9 +1441,9 @@ static void fprint_CC_table_and_calc_totals(void) " %llu %llu %llu" " %llu %llu %llu\n", lineCC->loc.line, - lineCC->Ir.a, lineCC->Ir.m1, lineCC->Ir.m2, - lineCC->Dr.a, lineCC->Dr.m1, lineCC->Dr.m2, - lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.m2); + lineCC->Ir.a, lineCC->Ir.m1, lineCC->Ir.mL, + lineCC->Dr.a, lineCC->Dr.m1, lineCC->Dr.mL, + lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.mL); } else if (!clo_cache_sim && clo_branch_sim) { VG_(sprintf)(buf, "%u %llu" @@ -1394,21 +1453,24 @@ static void fprint_CC_table_and_calc_totals(void) lineCC->Bc.b, lineCC->Bc.mp, lineCC->Bi.b, lineCC->Bi.mp); } - else - tl_assert(0); + else { + VG_(sprintf)(buf, "%u %llu\n", + lineCC->loc.line, + lineCC->Ir.a); + } VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); // Update summary stats Ir_total.a += lineCC->Ir.a; Ir_total.m1 += lineCC->Ir.m1; - Ir_total.m2 += lineCC->Ir.m2; + Ir_total.mL += lineCC->Ir.mL; Dr_total.a += lineCC->Dr.a; Dr_total.m1 += lineCC->Dr.m1; - Dr_total.m2 += lineCC->Dr.m2; + Dr_total.mL += lineCC->Dr.mL; Dw_total.a += lineCC->Dw.a; Dw_total.m1 += lineCC->Dw.m1; - Dw_total.m2 += lineCC->Dw.m2; + Dw_total.mL += lineCC->Dw.mL; Bc_total.b += lineCC->Bc.b; Bc_total.mp += lineCC->Bc.mp; Bi_total.b += lineCC->Bi.b; @@ -1425,9 +1487,9 @@ static void fprint_CC_table_and_calc_totals(void) " %llu %llu %llu" " %llu %llu %llu" " %llu %llu %llu %llu\n", - Ir_total.a, Ir_total.m1, Ir_total.m2, - Dr_total.a, Dr_total.m1, Dr_total.m2, - Dw_total.a, Dw_total.m1, Dw_total.m2, + Ir_total.a, Ir_total.m1, Ir_total.mL, + Dr_total.a, Dr_total.m1, Dr_total.mL, + Dw_total.a, Dw_total.m1, Dw_total.mL, Bc_total.b, Bc_total.mp, Bi_total.b, Bi_total.mp); } @@ -1436,9 +1498,9 @@ static void fprint_CC_table_and_calc_totals(void) " %llu %llu %llu" " %llu %llu %llu" " %llu %llu %llu\n", - Ir_total.a, Ir_total.m1, Ir_total.m2, - Dr_total.a, Dr_total.m1, Dr_total.m2, - Dw_total.a, Dw_total.m1, Dw_total.m2); + Ir_total.a, Ir_total.m1, Ir_total.mL, + Dr_total.a, Dr_total.m1, Dr_total.mL, + Dw_total.a, Dw_total.m1, Dw_total.mL); } else if (!clo_cache_sim && clo_branch_sim) { VG_(sprintf)(buf, "summary:" @@ -1448,8 +1510,11 @@ static void fprint_CC_table_and_calc_totals(void) Bc_total.b, Bc_total.mp, Bi_total.b, Bi_total.mp); } - else - tl_assert(0); + else { + VG_(sprintf)(buf, "summary:" + " %llu\n", + Ir_total.a); + } VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); VG_(close)(fd); @@ -1472,14 +1537,10 @@ static void cg_fini(Int exitcode) CacheCC D_total; BranchCC B_total; - ULong L2_total_m, L2_total_mr, L2_total_mw, - L2_total, L2_total_r, L2_total_w; + ULong LL_total_m, LL_total_mr, LL_total_mw, + LL_total, LL_total_r, LL_total_w; Int l1, l2, l3; - /* Running with both cache and branch simulation disabled is not - allowed (checked during command line option processing). */ - tl_assert(clo_cache_sim || clo_branch_sim); - fprint_CC_table_and_calc_totals(); if (VG_(clo_verbosity) == 0) @@ -1504,21 +1565,21 @@ static void cg_fini(Int exitcode) miss numbers */ if (clo_cache_sim) { VG_(umsg)(fmt, "I1 misses: ", Ir_total.m1); - VG_(umsg)(fmt, "L2i misses: ", Ir_total.m2); + VG_(umsg)(fmt, "LLi misses: ", Ir_total.mL); if (0 == Ir_total.a) Ir_total.a = 1; VG_(percentify)(Ir_total.m1, Ir_total.a, 2, l1+1, buf1); VG_(umsg)("I1 miss rate: %s\n", buf1); - VG_(percentify)(Ir_total.m2, Ir_total.a, 2, l1+1, buf1); - VG_(umsg)("L2i miss rate: %s\n", buf1); + VG_(percentify)(Ir_total.mL, Ir_total.a, 2, l1+1, buf1); + VG_(umsg)("LLi miss rate: %s\n", buf1); VG_(umsg)("\n"); /* D cache results. Use the D_refs.rd and D_refs.wr values to * determine the width of columns 2 & 3. */ D_total.a = Dr_total.a + Dw_total.a; D_total.m1 = Dr_total.m1 + Dw_total.m1; - D_total.m2 = Dr_total.m2 + Dw_total.m2; + D_total.mL = Dr_total.mL + Dw_total.mL; /* Make format string, getting width right for numbers */ VG_(sprintf)(fmt, "%%s %%,%dllu (%%,%dllu rd + %%,%dllu wr)\n", @@ -1528,8 +1589,8 @@ static void cg_fini(Int exitcode) D_total.a, Dr_total.a, Dw_total.a); VG_(umsg)(fmt, "D1 misses: ", D_total.m1, Dr_total.m1, Dw_total.m1); - VG_(umsg)(fmt, "L2d misses: ", - D_total.m2, Dr_total.m2, Dw_total.m2); + VG_(umsg)(fmt, "LLd misses: ", + D_total.mL, Dr_total.mL, Dw_total.mL); if (0 == D_total.a) D_total.a = 1; if (0 == Dr_total.a) Dr_total.a = 1; @@ -1539,30 +1600,30 @@ static void cg_fini(Int exitcode) VG_(percentify)(Dw_total.m1, Dw_total.a, 1, l3+1, buf3); VG_(umsg)("D1 miss rate: %s (%s + %s )\n", buf1, buf2,buf3); - VG_(percentify)( D_total.m2, D_total.a, 1, l1+1, buf1); - VG_(percentify)(Dr_total.m2, Dr_total.a, 1, l2+1, buf2); - VG_(percentify)(Dw_total.m2, Dw_total.a, 1, l3+1, buf3); - VG_(umsg)("L2d miss rate: %s (%s + %s )\n", buf1, buf2,buf3); + VG_(percentify)( D_total.mL, D_total.a, 1, l1+1, buf1); + VG_(percentify)(Dr_total.mL, Dr_total.a, 1, l2+1, buf2); + VG_(percentify)(Dw_total.mL, Dw_total.a, 1, l3+1, buf3); + VG_(umsg)("LLd miss rate: %s (%s + %s )\n", buf1, buf2,buf3); VG_(umsg)("\n"); - /* L2 overall results */ + /* LL overall results */ - L2_total = Dr_total.m1 + Dw_total.m1 + Ir_total.m1; - L2_total_r = Dr_total.m1 + Ir_total.m1; - L2_total_w = Dw_total.m1; - VG_(umsg)(fmt, "L2 refs: ", - L2_total, L2_total_r, L2_total_w); + LL_total = Dr_total.m1 + Dw_total.m1 + Ir_total.m1; + LL_total_r = Dr_total.m1 + Ir_total.m1; + LL_total_w = Dw_total.m1; + VG_(umsg)(fmt, "LL refs: ", + LL_total, LL_total_r, LL_total_w); - L2_total_m = Dr_total.m2 + Dw_total.m2 + Ir_total.m2; - L2_total_mr = Dr_total.m2 + Ir_total.m2; - L2_total_mw = Dw_total.m2; - VG_(umsg)(fmt, "L2 misses: ", - L2_total_m, L2_total_mr, L2_total_mw); + LL_total_m = Dr_total.mL + Dw_total.mL + Ir_total.mL; + LL_total_mr = Dr_total.mL + Ir_total.mL; + LL_total_mw = Dw_total.mL; + VG_(umsg)(fmt, "LL misses: ", + LL_total_m, LL_total_mr, LL_total_mw); - VG_(percentify)(L2_total_m, (Ir_total.a + D_total.a), 1, l1+1, buf1); - VG_(percentify)(L2_total_mr, (Ir_total.a + Dr_total.a), 1, l2+1, buf2); - VG_(percentify)(L2_total_mw, Dw_total.a, 1, l3+1, buf3); - VG_(umsg)("L2 miss rate: %s (%s + %s )\n", buf1, buf2,buf3); + VG_(percentify)(LL_total_m, (Ir_total.a + D_total.a), 1, l1+1, buf1); + VG_(percentify)(LL_total_mr, (Ir_total.a + Dr_total.a), 1, l2+1, buf2); + VG_(percentify)(LL_total_mw, Dw_total.a, 1, l3+1, buf3); + VG_(umsg)("LL miss rate: %s (%s + %s )\n", buf1, buf2,buf3); } /* If branch profiling is enabled, show branch overall results. */ @@ -1655,13 +1716,14 @@ void cg_discard_superblock_info ( Addr64 orig_addr64, VexGuestExtents vge ) /*--- Command line processing ---*/ /*--------------------------------------------------------------------*/ -static void parse_cache_opt ( cache_t* cache, Char* opt ) +static void parse_cache_opt ( cache_t* cache, Char* opt, Char* optval ) { Long i1, i2, i3; Char* endptr; + Char* checkRes; // Option argument looks like "65536,2,64". Extract them. - i1 = VG_(strtoll10)(opt, &endptr); if (*endptr != ',') goto bad; + i1 = VG_(strtoll10)(optval, &endptr); if (*endptr != ',') goto bad; i2 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != ',') goto bad; i3 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != '\0') goto bad; @@ -1673,14 +1735,20 @@ static void parse_cache_opt ( cache_t* cache, Char* opt ) if (cache->assoc != i2) goto overflow; if (cache->line_size != i3) goto overflow; + checkRes = check_cache(cache); + if (checkRes) { + VG_(fmsg)("%s", checkRes); + goto bad; + } + return; - overflow: - VG_(umsg)("one of the cache parameters was too large and overflowed\n"); bad: - // XXX: this omits the "--I1/D1/L2=" part from the message, but that's - // not a big deal. - VG_(err_bad_option)(opt); + VG_(fmsg_bad_option)(opt, ""); + + overflow: + VG_(fmsg_bad_option)(opt, + "One of the cache parameters was too large and overflowed.\n"); } static Bool cg_process_cmd_line_option(Char* arg) @@ -1689,11 +1757,12 @@ static Bool cg_process_cmd_line_option(Char* arg) // 5 is length of "--I1=" if VG_STR_CLO(arg, "--I1", tmp_str) - parse_cache_opt(&clo_I1_cache, tmp_str); + parse_cache_opt(&clo_I1_cache, arg, tmp_str); else if VG_STR_CLO(arg, "--D1", tmp_str) - parse_cache_opt(&clo_D1_cache, tmp_str); - else if VG_STR_CLO(arg, "--L2", tmp_str) - parse_cache_opt(&clo_L2_cache, tmp_str); + parse_cache_opt(&clo_D1_cache, arg, tmp_str); + else if (VG_STR_CLO(arg, "--L2", tmp_str) || // for backwards compatibility + VG_STR_CLO(arg, "--LL", tmp_str)) + parse_cache_opt(&clo_LL_cache, arg, tmp_str); else if VG_STR_CLO( arg, "--cachegrind-out-file", clo_cachegrind_out_file) {} else if VG_BOOL_CLO(arg, "--cache-sim", clo_cache_sim) {} @@ -1709,7 +1778,7 @@ static void cg_print_usage(void) VG_(printf)( " --I1=,, set I1 cache manually\n" " --D1=,, set D1 cache manually\n" -" --L2=,, set L2 cache manually\n" +" --LL=,, set LL cache manually\n" " --cache-sim=yes|no [yes] collect cache stats?\n" " --branch-sim=yes|no [no] collect branch prediction stats?\n" " --cachegrind-out-file= output file name [cachegrind.out.%%p]\n" @@ -1735,7 +1804,7 @@ static void cg_pre_clo_init(void) VG_(details_version) (NULL); VG_(details_description) ("a cache and branch-prediction profiler"); VG_(details_copyright_author)( - "Copyright (C) 2002-2009, and GNU GPL'd, by Nicholas Nethercote et al."); + "Copyright (C) 2002-2010, and GNU GPL'd, by Nicholas Nethercote et al."); VG_(details_bug_reports_to) (VG_BUGS_TO); VG_(details_avg_translation_sizeB) ( 500 ); @@ -1751,15 +1820,7 @@ static void cg_pre_clo_init(void) static void cg_post_clo_init(void) { - cache_t I1c, D1c, L2c; - - /* Can't disable both cache and branch profiling */ - if ((!clo_cache_sim) && (!clo_branch_sim)) { - VG_(umsg)("ERROR: --cache-sim=no --branch-sim=no is not allowed.\n"); - VG_(umsg)("You must select cache profiling, " - "or branch profiling, or both.\n"); - VG_(exit)(2); - } + cache_t I1c, D1c, LLc; CC_table = VG_(OSetGen_Create)(offsetof(LineCC, loc), @@ -1777,11 +1838,11 @@ static void cg_post_clo_init(void) VG_(malloc), "cg.main.cpci.3", VG_(free)); - configure_caches(&I1c, &D1c, &L2c); + configure_caches(&I1c, &D1c, &LLc); cachesim_I1_initcache(I1c); cachesim_D1_initcache(D1c); - cachesim_L2_initcache(L2c); + cachesim_LL_initcache(LLc); } VG_DETERMINE_INTERFACE_VERSION(cg_pre_clo_init) diff --git a/cachegrind/cg_merge.c b/cachegrind/cg_merge.c index 1d8ad41..94cc347 100644 --- a/cachegrind/cg_merge.c +++ b/cachegrind/cg_merge.c @@ -8,7 +8,7 @@ This file is part of Cachegrind, a Valgrind tool for cache profiling programs. - Copyright (C) 2002-2009 Nicholas Nethercote + Copyright (C) 2002-2010 Nicholas Nethercote njn@valgrind.org AVL tree code derived from diff --git a/cachegrind/cg_sim.c b/cachegrind/cg_sim.c index 57abdfc..0b8a1d7 100644 --- a/cachegrind/cg_sim.c +++ b/cachegrind/cg_sim.c @@ -7,7 +7,7 @@ This file is part of Cachegrind, a Valgrind tool for cache profiling programs. - Copyright (C) 2002-2009 Nicholas Nethercote + Copyright (C) 2002-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -96,7 +96,7 @@ static void cachesim_##L##_initcache(cache_t config) \ /* bigger than its usual limit. Inlining gains around 5--10% speedup. */ \ __attribute__((always_inline)) \ static __inline__ \ -void cachesim_##L##_doref(Addr a, UChar size, ULong* m1, ULong *m2) \ +void cachesim_##L##_doref(Addr a, UChar size, ULong* m1, ULong *mL) \ { \ UInt set1 = ( a >> L.line_size_bits) & (L.sets_min_1); \ UInt set2 = ((a+size-1) >> L.line_size_bits) & (L.sets_min_1); \ @@ -188,9 +188,9 @@ miss_treatment: \ return; \ } -CACHESIM(L2, (*m2)++ ); -CACHESIM(I1, { (*m1)++; cachesim_L2_doref(a, size, m1, m2); } ); -CACHESIM(D1, { (*m1)++; cachesim_L2_doref(a, size, m1, m2); } ); +CACHESIM(LL, (*mL)++ ); +CACHESIM(I1, { (*m1)++; cachesim_LL_doref(a, size, m1, mL); } ); +CACHESIM(D1, { (*m1)++; cachesim_LL_doref(a, size, m1, mL); } ); /*--------------------------------------------------------------------*/ /*--- end cg_sim.c ---*/ diff --git a/cachegrind/docs/cg-manual.xml b/cachegrind/docs/cg-manual.xml index e8ab23d..b5a820b 100644 --- a/cachegrind/docs/cg-manual.xml +++ b/cachegrind/docs/cg-manual.xml @@ -16,33 +16,45 @@ Valgrind command line. Cachegrind simulates how your program interacts with a machine's cache hierarchy and (optionally) branch predictor. It simulates a machine with -independent first level instruction and data caches (I1 and D1), backed by a -unified second level cache (L2). This configuration is used by almost all -modern machines. +independent first-level instruction and data caches (I1 and D1), backed by a +unified second-level cache (L2). This exactly matches the configuration of +many modern machines. + +However, some modern machines have three levels of cache. For these +machines (in the cases where Cachegrind can auto-detect the cache +configuration) Cachegrind simulates the first-level and third-level caches. +The reason for this choice is that the L3 cache has the most influence on +runtime, as it masks accesses to main memory. Furthermore, the L1 caches +often have low associativity, so simulating them can detect cases where the +code interacts badly with this cache (eg. traversing a matrix column-wise +with the row length being a power of 2). + +Therefore, Cachegrind always refers to the I1, D1 and LL (last-level) +caches. -It gathers the following statistics (abbreviations used for each statistic +Cachegrind gathers the following statistics (abbreviations used for each statistic is given in parentheses): I cache reads (Ir, which equals the number of instructions executed), I1 cache read misses (I1mr) and - L2 cache instruction read misses (I1mr). + LL cache instruction read misses (ILmr). D cache reads (Dr, which equals the number of memory reads), D1 cache read misses (D1mr), and - L2 cache data read misses (D2mr). + LL cache data read misses (DLmr). D cache writes (Dw, which equals the number of memory writes), D1 cache write misses (D1mw), and - L2 cache data write misses (D2mw). + LL cache data write misses (DLmw). @@ -59,10 +71,10 @@ is given in parentheses): Note that D1 total accesses is given by D1mr + -D1mw, and that L2 total -accesses is given by I2mr + -D2mr + -D2mw. +D1mw, and that LL total +accesses is given by ILmr + +DLmr + +DLmw. These statistics are presented for the entire program and for each @@ -70,7 +82,7 @@ function in the program. You can also annotate each line of source code in the program with the counts that were caused directly by it. On a modern machine, an L1 miss will typically cost -around 10 cycles, an L2 miss can cost as much as 200 +around 10 cycles, an LL miss can cost as much as 200 cycles, and a mispredicted branch costs in the region of 10 to 30 cycles. Detailed cache and branch profiling can be very useful for understanding how your program interacts with the machine and thus how @@ -98,8 +110,10 @@ be normally run. Then, you need to run Cachegrind itself to gather the profiling information, and then run cg_annotate to get a detailed presentation of that information. As an optional intermediate step, you can use cg_merge to sum -together the outputs of multiple Cachegrind runs, into a single file which -you then use as the input for cg_annotate. +together the outputs of multiple Cachegrind runs into a single file which +you then use as the input for cg_annotate. Alternatively, you can use +cg_diff to difference the outputs of two Cachegrind runs into a signel file +which you then use as the input for cg_annotate. @@ -116,24 +130,24 @@ summary statistics that look like this will be printed: +==31751== LL misses: 23,360 ( 4,262 rd + 19,098 wr) +==31751== LL miss rate: 0.0% ( 0.0% + 0.4%)]]> Cache accesses for instruction fetches are summarised first, giving the number of fetches made (this is the number of instructions executed, which can be useful to know in its own -right), the number of I1 misses, and the number of L2 instruction -(L2i) misses. +right), the number of I1 misses, and the number of LL instruction +(LLi) misses. Cache accesses for data follow. The information is similar to that of the instruction fetches, except that the values are @@ -142,12 +156,12 @@ also shown split between reads and writes (note each row's wr values add up to the row's total). -Combined instruction and data figures for the L2 cache -follow that. Note that the L2 miss rate is computed relative to the total +Combined instruction and data figures for the LL cache +follow that. Note that the LL miss rate is computed relative to the total number of memory accesses, not the number of L1 misses. I.e. it is -(I2mr + D2mr + D2mw) / (Ir + Dr + Dw) +(ILmr + DLmr + DLmw) / (Ir + Dr + Dw) not -(I2mr + D2mr + D2mw) / (I1mr + D1mr + D1mw) +(ILmr + DLmr + DLmw) / (I1mr + D1mr + D1mw) Branch prediction statistics are not collected by default. @@ -206,11 +220,11 @@ wide if possible, as the output lines can be quite long. -------------------------------------------------------------------------------- I1 cache: 65536 B, 64 B, 2-way associative D1 cache: 65536 B, 64 B, 2-way associative -L2 cache: 262144 B, 64 B, 8-way associative +LL cache: 262144 B, 64 B, 8-way associative Command: concord vg_to_ucode.c -Events recorded: Ir I1mr I2mr Dr D1mr D2mr Dw D1mw D2mw -Events shown: Ir I1mr I2mr Dr D1mr D2mr Dw D1mw D2mw -Event sort order: Ir I1mr I2mr Dr D1mr D2mr Dw D1mw D2mw +Events recorded: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +Events shown: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +Event sort order: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw Threshold: 99% Chosen for annotation: Auto-annotation: off @@ -222,7 +236,7 @@ Auto-annotation: off - I1 cache, D1 cache, L2 cache: cache configuration. So + I1 cache, D1 cache, LL cache: cache configuration. So you know the configuration with which these results were obtained. @@ -298,7 +312,7 @@ program: @@ -310,7 +324,7 @@ These are similar to the summary provided when Cachegrind finishes running. Events: lines of all the inputs are identical, so as to ensure that the addition of costs makes sense. For example, it would be nonsensical for it to add a number indicating -D1 read references to a number from a different file indicating L2 +D1 read references to a number from a different file indicating LL write misses. @@ -697,6 +711,85 @@ fail these checks. + +Differencing Profiles with cg_diff + + +cg_diff is a simple program which +reads two profile files, as created by Cachegrind, finds the difference +between them, and writes the results into another file in the same format. +You can then examine the merged results using +cg_annotate <filename>, as +described above. This is very useful if you want to measure how a change to +a program affected its performance. + + + +cg_diff is invoked as follows: + + + + + +It reads and checks file1, then read +and checks file2, then computes the +difference (effectively file1 - +file2). The final results are written to +standard output. + + +Costs are summed on a per-function basis. Per-line costs are not summed, +because doing so is too difficult. For example, consider differencing two +profiles, one from a single-file program A, and one from the same program A +where a single blank line was inserted at the top of the file. Every single +per-line count has changed. In comparison, the per-function counts have not +changed. The per-function count differences are still very useful for +determining differences between programs. Note that because the result is +the difference of two profiles, many of the counts will be negative; this +indicates that the counts for the relevant function are fewer in the second +version than those in the first version. + + +cg_diff does not attempt to check +that the input files come from runs of the same executable. It will +happily merge together profile files from completely unrelated +programs. It does however check that the +Events: lines of all the inputs are +identical, so as to ensure that the addition of costs makes sense. +For example, it would be nonsensical for it to add a number indicating +D1 read references to a number from a different file indicating LL +write misses. + + +A number of other syntax and sanity checks are done whilst reading the +inputs. cg_diff will stop and +attempt to print a helpful error message if any of the input files +fail these checks. + + +Sometimes you will want to compare Cachegrind profiles of two versions of a +program that you have sitting side-by-side. For example, you might have +version1/prog.c and +version2/prog.c, where the second is +slightly different to the first. A straight comparison of the two will not +be useful -- because functions are qualified with filenames, a function +f will be listed as +version1/prog.c:f for the first version but +version2/prog.c:f for the second +version. + + +When this happens, you can use the option. +Its argument is a Perl search-and-replace expression that will be applied +to all the filenames in both Cachegrind output files. It can be used to +remove minor differences in filenames. For example, the option + will suffice for +this case. + + + + @@ -729,12 +822,12 @@ fail these checks. - + - + - Specify the size, associativity and line size of the level 2 + Specify the size, associativity and line size of the last-level cache. @@ -822,9 +915,9 @@ fail these checks. order). Default is to use all present in the cachegrind.out.<pid> file (and use the order in the file). Useful if you want to concentrate on, for - example, I cache misses (), or data - read misses (), or L2 data misses - (). Best used in conjunction with + example, I cache misses (), or data + read misses (), or LL data misses + (). Best used in conjunction with . @@ -842,21 +935,21 @@ fail these checks. - + Sets the threshold for the function-by-function - summary. Functions are shown that account for more than X% - of the primary sort event. If auto-annotating, also affects - which files are annotated. + summary. A function is shown if it accounts for more than X% + of the counts for the primary sort event. If auto-annotating, also + affects which files are annotated. Note: thresholds can be set for more than one of the events by appending any events for the option with a colon and a number (no spaces, though). E.g. if you want to see - the functions that cover 99% of L2 read misses and 99% of L2 + each function that covers more than 1% of LL read misses or 1% of LL write misses, use this option: - + @@ -900,6 +993,49 @@ fail these checks. + +cg_diff Command-line Options + + + + + + + + + + Show the help message. + + + + + + + + + Show the version number. + + + + + + + + + Specifies a Perl search-and-replace expression that is applied + to all filenames. Useful for removing minor differences in paths + between two different versions of a program that are sitting in + different directories. + + + + + + + + + + @@ -935,13 +1071,13 @@ information, but they can still be very useful for identifying bottlenecks. -After that, we have found that L2 misses are typically a much bigger source +After that, we have found that LL misses are typically a much bigger source of slow-downs than L1 misses. So it's worth looking for any snippets of -code with high D2mr or -D2mw counts. (You can use - with cg_annotate to focus just on -D2mr counts, for example.) If you find any, it's still +code with high DLmr or +DLmw counts. (You can use + with cg_annotate to focus just on +DLmr counts, for example.) If you find any, it's still not always easy to work out how to improve things. You need to have a reasonable understanding of how caches work, the principles of locality, and your program's data access patterns. Improving things may require @@ -1029,12 +1165,12 @@ follows: - Inclusive L2 cache: the L2 cache typically replicates all + Inclusive LL cache: the LL cache typically replicates all the entries of the L1 caches, because fetching into L1 involves - fetching into L2 first (this does not guarantee strict inclusiveness, - as lines evicted from L2 still could reside in L1). This is + fetching into LL first (this does not guarantee strict inclusiveness, + as lines evicted from LL still could reside in L1). This is standard on Pentium chips, but AMD Opterons, Athlons and Durons - use an exclusive L2 cache that only holds + use an exclusive LL cache that only holds blocks evicted from L1. Ditto most modern VIA CPUs. @@ -1048,10 +1184,10 @@ early incarnation that doesn't give any cache information, then Cachegrind will fall back to using a default configuration (that of a model 3/4 Athlon). Cachegrind will tell you if this happens. You can manually specify one, two or all three levels -(I1/D1/L2) of the cache from the command line using the +(I1/D1/LL) of the cache from the command line using the , and - options. + options. For cache parameters to be valid for simulation, the number of sets (with associativity being the number of cache lines in each set) has to be a power of two. @@ -1062,7 +1198,7 @@ determine the cache configuration, so you will need to specify it with the , and - options. + options. Other noteworthy behaviour: diff --git a/cachegrind/tests/chdir.stderr.exp b/cachegrind/tests/chdir.stderr.exp index 8eaf654..e8084c1 100644 --- a/cachegrind/tests/chdir.stderr.exp +++ b/cachegrind/tests/chdir.stderr.exp @@ -2,16 +2,16 @@ I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/cachegrind/tests/dlclose.stderr.exp b/cachegrind/tests/dlclose.stderr.exp index 8eaf654..e8084c1 100644 --- a/cachegrind/tests/dlclose.stderr.exp +++ b/cachegrind/tests/dlclose.stderr.exp @@ -2,16 +2,16 @@ I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/cachegrind/tests/filter_stderr b/cachegrind/tests/filter_stderr index 6ec44bf..9209dd5 100755 --- a/cachegrind/tests/filter_stderr +++ b/cachegrind/tests/filter_stderr @@ -7,14 +7,15 @@ $dir/../../tests/filter_stderr_basic | # Remove "Cachegrind, ..." line and the following copyright line. sed "/^Cachegrind, a cache and branch-prediction profiler/ , /./ d" | -# Remove numbers from I/D/L2 "refs:" lines -perl -p -e 's/((I|D|L2) *refs:)[ 0-9,()+rdw]*$/\1/' | +# Remove numbers from I/D/LL "refs:" lines +perl -p -e 's/((I|D|LL) *refs:)[ 0-9,()+rdw]*$/\1/' | -# Remove numbers from I1/D1/L2/L2i/L2d "misses:" and "miss rates:" lines -perl -p -e 's/((I1|D1|L2|L2i|L2d) *(misses|miss rate):)[ 0-9,()+rdw%\.]*$/\1/' | +# Remove numbers from I1/D1/LL/LLi/LLd "misses:" and "miss rates:" lines +perl -p -e 's/((I1|D1|LL|LLi|LLd) *(misses|miss rate):)[ 0-9,()+rdw%\.]*$/\1/' | # Remove CPUID warnings lines for P4s and other machines sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" | sed "/Simulating a 16 KB I-cache with 32 B lines/d" | -sed "/warning: L3 cache detected but ignored/d" | -sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d" +sed "/warning: L3 cache found, using its data for the LL simulation./d" | +sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d" | +sed "/Warning: Cannot auto-detect cache config on ARM, using one or more defaults/d" diff --git a/cachegrind/tests/notpower2.stderr.exp b/cachegrind/tests/notpower2.stderr.exp index 8eaf654..e8084c1 100644 --- a/cachegrind/tests/notpower2.stderr.exp +++ b/cachegrind/tests/notpower2.stderr.exp @@ -2,16 +2,16 @@ I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/cachegrind/tests/notpower2.vgtest b/cachegrind/tests/notpower2.vgtest index 132cfe5..21caffe 100644 --- a/cachegrind/tests/notpower2.vgtest +++ b/cachegrind/tests/notpower2.vgtest @@ -1,3 +1,3 @@ prog: ../../tests/true -vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 +vgopts: --I1=32768,8,64 --D1=24576,6,64 --LL=3145728,12,64 cleanup: rm cachegrind.out.* diff --git a/cachegrind/tests/wrap5.stderr.exp b/cachegrind/tests/wrap5.stderr.exp index 8eaf654..e8084c1 100644 --- a/cachegrind/tests/wrap5.stderr.exp +++ b/cachegrind/tests/wrap5.stderr.exp @@ -2,16 +2,16 @@ I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/cachegrind/tests/x86/fpu-28-108.stderr.exp b/cachegrind/tests/x86/fpu-28-108.stderr.exp index 8eaf654..e8084c1 100644 --- a/cachegrind/tests/x86/fpu-28-108.stderr.exp +++ b/cachegrind/tests/x86/fpu-28-108.stderr.exp @@ -2,16 +2,16 @@ I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/Makefile.am b/callgrind/Makefile.am index a580e52..74f3597 100644 --- a/callgrind/Makefile.am +++ b/callgrind/Makefile.am @@ -48,8 +48,9 @@ CALLGRIND_SOURCES_COMMON = \ threads.c \ ../cachegrind/cg-x86-amd64.c \ ../cachegrind/cg-ppc32.c \ - ../cachegrind/cg-ppc64.c - + ../cachegrind/cg-ppc64.c \ + ../cachegrind/cg-arm.c + CALLGRIND_CFLAGS_COMMON = -I$(top_srcdir)/cachegrind callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ @@ -64,6 +65,13 @@ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ $(CALLGRIND_SOURCES_COMMON) @@ -77,5 +85,11 @@ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif diff --git a/callgrind/bb.c b/callgrind/bb.c index 7bea5b3..6deafb0 100644 --- a/callgrind/bb.c +++ b/callgrind/bb.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/callgrind/bbcc.c b/callgrind/bbcc.c index 7917c25..24862a8 100644 --- a/callgrind/bbcc.c +++ b/callgrind/bbcc.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -580,6 +580,7 @@ void CLG_(setup_bbcc)(BB* bb) if (last_bb) { passed = CLG_(current_state).jmps_passed; + CLG_ASSERT(passed <= last_bb->cjmp_count); if (passed == last_bb->cjmp_count) { jmpkind = last_bb->jmpkind; @@ -599,9 +600,9 @@ void CLG_(setup_bbcc)(BB* bb) last_bbcc->ecounter_sum++; last_bbcc->jmp[passed].ecounter++; if (!CLG_(clo).simulate_cache) { - /* update Ir cost */ - int instr_count = last_bb->jmp[passed].instr+1; - CLG_(current_state).cost[CLG_(sets).off_full_Ir] += instr_count; + /* update Ir cost */ + UInt instr_count = last_bb->jmp[passed].instr+1; + CLG_(current_state).cost[ fullOffset(EG_IR) ] += instr_count; } } @@ -864,6 +865,9 @@ void CLG_(setup_bbcc)(BB* bb) } CLG_(current_state).bbcc = bbcc; + // needed for log_* handlers called in this BB + CLG_(bb_base) = bb->obj->offset + bb->offset; + CLG_(cost_base) = bbcc->cost; CLG_DEBUGIF(1) { VG_(printf)(" "); @@ -878,7 +882,5 @@ void CLG_(setup_bbcc)(BB* bb) CLG_(print_cxt)(-8, CLG_(current_state).cxt, bbcc->rec_index); CLG_DEBUG(3,"\n"); - (*CLG_(cachesim).after_bbsetup)(); - CLG_(stat).bb_executions++; } diff --git a/callgrind/callgrind.h b/callgrind/callgrind.h index 18d7981..d36b6f4 100644 --- a/callgrind/callgrind.h +++ b/callgrind/callgrind.h @@ -13,7 +13,7 @@ This file is part of callgrind, a valgrind tool for cache simulation and call tree tracing. - Copyright (C) 2003-2009 Josef Weidendorfer. All rights reserved. + Copyright (C) 2003-2010 Josef Weidendorfer. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions diff --git a/callgrind/callstack.c b/callgrind/callstack.c index 70495e1..24087f5 100644 --- a/callgrind/callstack.c +++ b/callgrind/callstack.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/callgrind/clo.c b/callgrind/clo.c index a6aaba4..fc99b0d 100644 --- a/callgrind/clo.c +++ b/callgrind/clo.c @@ -2,7 +2,7 @@ This file is part of Callgrind, a Valgrind tool for call graph profiling programs. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This tool is derived from and contains lot of code from Cachegrind Copyright (C) 2002 Nicholas Nethercote (njn@valgrind.org) @@ -525,8 +525,13 @@ Bool CLG_(process_cmd_line_option)(Char* arg) else if VG_BOOL_CLO(arg, "--collect-alloc", CLG_(clo).collect_alloc) {} else if VG_BOOL_CLO(arg, "--collect-systime", CLG_(clo).collect_systime) {} + else if VG_BOOL_CLO(arg, "--collect-bus", CLG_(clo).collect_bus) {} + /* for option compatibility with cachegrind */ + else if VG_BOOL_CLO(arg, "--cache-sim", CLG_(clo).simulate_cache) {} + /* compatibility alias, deprecated option */ else if VG_BOOL_CLO(arg, "--simulate-cache", CLG_(clo).simulate_cache) {} - + /* for option compatibility with cachegrind */ + else if VG_BOOL_CLO(arg, "--branch-sim", CLG_(clo).simulate_branch) {} else { Bool isCachesimOption = (*CLG_(cachesim).parse_opt)(arg); @@ -572,6 +577,7 @@ void CLG_(print_usage)(void) " --collect-atstart=no|yes Collect at process/thread start [yes]\n" " --toggle-collect= Toggle collection on enter/leave function\n" " --collect-jumps=no|yes Collect jumps? [no]\n" +" --collect-bus=no|yes Collect global bus events? [no]\n" #if CLG_EXPERIMENTAL " --collect-alloc=no|yes Collect memory allocation info? [no]\n" #endif @@ -589,6 +595,9 @@ void CLG_(print_usage)(void) #if CLG_EXPERIMENTAL " --fn-group= Put function into separation group \n" #endif +"\n simulation options:\n" +" --branch-sim=no|yes Do branch prediction simulation [no]\n" +" --cache-sim=no|yes Do cache simulation [no]\n" ); (*CLG_(cachesim).print_opts)(); @@ -639,6 +648,7 @@ void CLG_(set_clo_defaults)(void) CLG_(clo).collect_jumps = False; CLG_(clo).collect_alloc = False; CLG_(clo).collect_systime = False; + CLG_(clo).collect_bus = False; CLG_(clo).skip_plt = True; CLG_(clo).separate_callers = 0; @@ -648,6 +658,7 @@ void CLG_(set_clo_defaults)(void) /* Instrumentation */ CLG_(clo).instrument_atstart = True; CLG_(clo).simulate_cache = False; + CLG_(clo).simulate_branch = False; /* Call graph */ CLG_(clo).pop_on_jump = False; diff --git a/callgrind/command.c b/callgrind/command.c index e9b40c2..1c68cd3 100644 --- a/callgrind/command.c +++ b/callgrind/command.c @@ -2,7 +2,7 @@ This file is part of Callgrind, a Valgrind tool for call graph profiling programs. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This tool is derived from and contains lot of code from Cachegrind Copyright (C) 2002 Nicholas Nethercote (njn@valgrind.org) diff --git a/callgrind/context.c b/callgrind/context.c index eb478fd..92b4056 100644 --- a/callgrind/context.c +++ b/callgrind/context.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/callgrind/costs.c b/callgrind/costs.c index 2626ab9..2381044 100644 --- a/callgrind/costs.c +++ b/callgrind/costs.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/callgrind/debug.c b/callgrind/debug.c index ab4fdb5..966aa74 100644 --- a/callgrind/debug.c +++ b/callgrind/debug.c @@ -2,7 +2,7 @@ This file is part of Callgrind, a Valgrind tool for call graph profiling programs. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This tool is derived from and contains lot of code from Cachegrind Copyright (C) 2002 Nicholas Nethercote (njn@valgrind.org) @@ -137,40 +137,46 @@ void CLG_(print_bbcc)(int s, BBCC* bbcc) void CLG_(print_eventset)(int s, EventSet* es) { - int i; + int i, j; + UInt mask; + EventGroup* eg; - if (s<0) { - s = -s; - print_indent(s); - } + if (s<0) { + s = -s; + print_indent(s); + } - if (!es) { - VG_(printf)("(EventSet not set)\n"); - return; - } + if (!es) { + VG_(printf)("(EventSet not set)\n"); + return; + } - VG_(printf)("%5s (Size/Cap %d/%d): ", - es->name, es->size, es->capacity); - - if (es->size == 0) - VG_(printf)("-"); - else { - for(i=0; i< es->size; i++) { - if (i>0) { - VG_(printf)(" "); - if (es->e[i-1].nextTop == i) - VG_(printf)("| "); - } - VG_(printf)("%s", es->e[i].type->name); + VG_(printf)("EventSet %d (%d groups, size %d):", + es->mask, es->count, es->size); + + if (es->count == 0) { + VG_(printf)("-\n"); + return; } - } - VG_(printf)("\n"); + + for(i=0, mask=1; imask & mask)==0) continue; + eg = CLG_(get_event_group)(i); + if (!eg) continue; + VG_(printf)(" (%d: %s", i, eg->name[0]); + for(j=1; jsize; j++) + VG_(printf)(" %s", eg->name[j]); + VG_(printf)(")"); + } + VG_(printf)("\n"); } void CLG_(print_cost)(int s, EventSet* es, ULong* c) { - Int i, pos; + Int i, j, pos, off; + UInt mask; + EventGroup* eg; if (s<0) { s = -s; @@ -182,29 +188,36 @@ void CLG_(print_cost)(int s, EventSet* es, ULong* c) return; } if (!c) { - VG_(printf)("Cost (Null, EventSet %s)\n", es->name); + VG_(printf)("Cost (Null, EventSet %d)\n", es->mask); return; } if (es->size == 0) { - VG_(printf)("Cost (Nothing, EventSet %s with len 0)\n", es->name); + VG_(printf)("Cost (Nothing, EventSet with len 0)\n"); return; } pos = s; - pos += VG_(printf)("Cost %s [%p]: %s %llu", es->name, c, es->e[0].type->name, c[0]); - - i = 1; - while(isize) { - if (pos > 70) { - VG_(printf)(",\n"); - print_indent(s+5); - pos = s+5; - } - else - pos += VG_(printf)(", "); - pos += VG_(printf)("%s %llu", es->e[i].type->name, c[i]); - i++; + pos += VG_(printf)("Cost [%p]: ", c); + off = 0; + for(i=0, mask=1; imask & mask)==0) continue; + eg = CLG_(get_event_group)(i); + if (!eg) continue; + for(j=0; jsize; j++) { + + if (off>0) { + if (pos > 70) { + VG_(printf)(",\n"); + print_indent(s+5); + pos = s+5; + } + else + pos += VG_(printf)(", "); + } + + pos += VG_(printf)("%s %llu", eg->name[j], c[off++]); + } } VG_(printf)("\n"); } @@ -213,13 +226,13 @@ void CLG_(print_cost)(int s, EventSet* es, ULong* c) void CLG_(print_short_jcc)(jCC* jcc) { if (jcc) - VG_(printf)("%#lx => %#lx [%llu/%llu,%llu,%llu]", + VG_(printf)("%#lx => %#lx [calls %llu/Ir %llu, Dr %llu, Dw %llu]", bb_jmpaddr(jcc->from->bb), bb_addr(jcc->to->bb), jcc->call_counter, - jcc->cost ? jcc->cost[CLG_(sets).off_full_Ir]:0, - jcc->cost ? jcc->cost[CLG_(sets).off_full_Dr]:0, - jcc->cost ? jcc->cost[CLG_(sets).off_full_Dw]:0); + jcc->cost ? jcc->cost[fullOffset(EG_IR)]:0, + jcc->cost ? jcc->cost[fullOffset(EG_DR)]:0, + jcc->cost ? jcc->cost[fullOffset(EG_DW)]:0); else VG_(printf)("[Skipped JCC]"); } diff --git a/callgrind/docs/cl-format.xml b/callgrind/docs/cl-format.xml index 97b3543..7fce318 100644 --- a/callgrind/docs/cl-format.xml +++ b/callgrind/docs/cl-format.xml @@ -414,7 +414,7 @@ for "Ir and "Dr". This specifies various information for this dump. For some types, the semantic is defined, but any description type is allowed. Unknown types should be ignored. - There are the types "I1 cache", "D1 cache", "L2 cache", which + There are the types "I1 cache", "D1 cache", "LL cache", which specify parameters used for the cache simulator. These are the only types originally used by Cachegrind. Additionally, Callgrind uses the following types: "Timerange" gives a rough range of the basic @@ -457,7 +457,7 @@ for "Ir and "Dr". I1mr: Instruction Level 1 read cache miss - I2mr: Instruction Level 2 read cache miss + ILmr: Instruction last-level read cache miss ... diff --git a/callgrind/docs/cl-manual.xml b/callgrind/docs/cl-manual.xml index 7e43bfa..3f8330e 100644 --- a/callgrind/docs/cl-manual.xml +++ b/callgrind/docs/cl-manual.xml @@ -4,7 +4,7 @@ [ %vg-entities; ]> -Callgrind: a call-graph generating cache profiler +Callgrind: a call-graph generating cache and branch prediction profiler To use this tool, you must specify @@ -14,14 +14,14 @@ Valgrind command line. Overview -Callgrind is a profiling tool that can -construct a call graph for a program's run. +Callgrind is a profiling tool that records the call history among +functions in a program's run as a call-graph. By default, the collected data consists of the number of instructions executed, their relationship to source lines, the caller/callee relationship between functions, and the numbers of such calls. -Optionally, a cache simulator (similar to Cachegrind) can produce -further information about the memory access behavior of the application. +Optionally, cache simulation and/or branch prediction (similar to Cachegrind) +can produce further information about the runtime behavior of an application. The profile data is written out to a file at program @@ -175,10 +175,10 @@ on heuristics to detect calls and returns. results in this case. If you are additionally interested in measuring the - cache behavior of your - program, use Callgrind with the option - - However, expect a further slow down approximately by a factor of 2. + cache behavior of your program, use Callgrind with the option + . For + branch prediction simulation, use . + Expect a further slow down approximately by a factor of 2. If the program section you want to profile is somewhere in the middle of the run, it is beneficial to @@ -353,10 +353,27 @@ callgrind.out.pid.part-threa start event collection a few million instructions after you have enabled instrumentation. - + + Counting global bus events + + For access to shared data among threads in a multithreaded + code, synchronization is required to avoid raced conditions. + Synchronization primitives are usually implemented via atomic instructions. + However, excessive use of such instructions can lead to performance + issues. + + To enable analysis of this problem, Callgrind optionally can count + the number of atomic instructions executed. More precisely, for x86/x86_64, + these are instructions using a lock prefix. For architectures supporting + LL/SC, these are the number of SC instructions executed. For both, the term + "global bus events" is used. + The short name of the event type used for global bus events is "Ge". + To count global bus events, use . + + Avoiding cycles @@ -762,6 +779,16 @@ Also see . + + + + + + This specifies whether the number of global bus events executed + should be collected. The event type "Ge" is used for these events. + + + @@ -890,36 +917,68 @@ Also see . + -Cache simulation options + xreflabel="Simulation options"> +Simulation options - - + + - + Specify if you want to do full cache simulation. By default, - only instruction read accesses will be profiled. + only instruction read accesses will be counted ("Ir"). + With cache simulation, further event counters are enabled: + Cache misses on instruction reads ("I1mr"/"ILmr"), + data read accesses ("Dr") and related cache misses ("D1mr"/"DLmr"), + data write accesses ("Dw") and related cache misses ("D1mw"/"DLmw"). + For more information, see . + + + + + + + Specify if you want to do branch prediction simulation. + Further event counters are enabled: Number of executed conditional + branches and related predictor misses ("Bc"/"Bcm"), executed indirect + jumps and related misses of the jump address predictor ("Bi"/"Bim"). + + + + + + + + + + +Cache simulation options + + + + Specify whether write-back behavior should be simulated, allowing - to distinguish L2 caches misses with and without write backs. + to distinguish LL caches misses with and without write backs. The cache model of Cachegrind/Callgrind does not specify write-through vs. write-back behavior, and this also is not relevant for the number of generated miss counts. However, with explicit write-back simulation it can be decided whether a miss triggers not only the loading of a new cache line, but also if a write back of a dirty cache line had to take - place before. The new dirty miss events are I2dmr, D2dmr, and D2dmw, + place before. The new dirty miss events are ILdmr, DLdmr, and DLdmw, for misses because of instruction read, data read, and data write, respectively. As they produce two memory transactions, they should account for a doubled time estimation in relation to a normal miss. @@ -957,13 +1016,13 @@ Also see . bad access behavior). The new counters are defined in a way such that worse behavior results in higher cost. AcCost1 and AcCost2 are counters showing bad temporal locality - for L1 and L2 caches, respectively. This is done by summing up + for L1 and LL caches, respectively. This is done by summing up reciprocal values of the numbers of accesses of each cache line, multiplied by 1000 (as only integer costs are allowed). E.g. for a given source line with 5 read accesses, a value of 5000 AcCost means that for every access, a new cache line was loaded and directly evicted afterwards without further accesses. Similarly, SpLoss1/2 - shows bad spatial locality for L1 and L2 caches, respectively. It + shows bad spatial locality for L1 and LL caches, respectively. It gives the spatial loss count of bytes which were loaded into cache but never accessed. It pinpoints at code accessing data in a way such that cache space is wasted. This hints @@ -1000,12 +1059,12 @@ Also see . - + - + - Specify the size, associativity and line size of the level 2 + Specify the size, associativity and line size of the last-level cache. diff --git a/callgrind/dump.c b/callgrind/dump.c index 58b3953..9bfaaab 100644 --- a/callgrind/dump.c +++ b/callgrind/dump.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -55,7 +55,7 @@ EventMapping* CLG_(dumpmap) = 0; * print_fn_pos, fprint_apos, fprint_fcost, fprint_jcc, * fprint_fcc_ln, dump_run_info, dump_state_info */ -static Char outbuf[FILENAME_LEN + FN_NAME_LEN + OBJ_NAME_LEN]; +static Char outbuf[FILENAME_LEN + FN_NAME_LEN + OBJ_NAME_LEN + COSTS_LEN]; Int CLG_(get_dump_counter)(void) { diff --git a/callgrind/events.c b/callgrind/events.c index e0595c2..fb5a77a 100644 --- a/callgrind/events.c +++ b/callgrind/events.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -28,550 +28,534 @@ #include "global.h" -#define MAX_EVENTTYPE 20 +/* This should be 2**MAX_EVENTGROUP_COUNT */ +#define MAX_EVENTSET_COUNT 1024 -static EventType eventtype[MAX_EVENTTYPE]; -static Int eventtype_count = 0; +static EventGroup* eventGroup[MAX_EVENTGROUP_COUNT]; +static EventSet* eventSetTable[MAX_EVENTSET_COUNT]; +static Bool eventSets_initialized = 0; -EventType* CLG_(register_eventtype)(Char* name) +static +void initialize_event_sets(void) { - EventType* et; + Int i; - if (eventtype_count == MAX_EVENTTYPE) { - VG_(printf)("\nMore than %d event types used!\n" - "Increase MAX_EVENTTYPE in ct_events.c and recomile this tool!\n", - MAX_EVENTTYPE); - VG_(tool_panic)("Too many event types requested."); - } + if (eventSets_initialized) return; - et = &(eventtype[eventtype_count]); - et->id = eventtype_count; - et->name = (UChar*) VG_(strdup)("cl.events.re.1", name); - et->description = 0; + for(i=0; i< MAX_EVENTGROUP_COUNT; i++) + eventGroup[i] = 0; - eventtype_count++; - - return et; -} + for(i=0; i< MAX_EVENTSET_COUNT; i++) + eventSetTable[i] = 0; + eventSets_initialized = 1; + } -EventType* CLG_(get_eventtype)(Char* name) +static +EventGroup* new_event_group(int id, int n) { - Int i; + EventGroup* eg; + + initialize_event_sets(); - for(i=0;i=0 && idsize = n; + eventGroup[id] = eg; + return eg; } -EventType* CLG_(get_eventtype_byindex)(Int id) +EventGroup* CLG_(register_event_group) (int id, Char* n1) { - if ((id >= 0) && (id < eventtype_count)) - return eventtype+id; - return 0; + EventGroup* eg = new_event_group(id, 1); + eg->name[0] = n1; + + return eg; } -/* Allocate space for an event set */ -EventSet* CLG_(get_eventset)(Char* n, Int capacity) +EventGroup* CLG_(register_event_group2)(int id, Char* n1, Char* n2) { - EventSet* es; + EventGroup* eg = new_event_group(id, 2); + eg->name[0] = n1; + eg->name[1] = n2; - es = (EventSet*) CLG_MALLOC("cl.events.geSet.1", - sizeof(EventSet) + - capacity * sizeof(EventSetEntry)); - es->capacity = capacity; - es->size = 0; - es->name = n; - - return es; + return eg; } -/* Incorporate a event type into a set, get start offset */ -Int CLG_(add_eventtype)(EventSet* es, EventType* t) +EventGroup* CLG_(register_event_group3)(int id, Char* n1, Char* n2, Char* n3) { - Int offset = es->size; - if (es->capacity - offset < 1) return -1; - - es->size++; - es->e[offset].type = t; - es->e[offset].nextTop = es->size; + EventGroup* eg = new_event_group(id, 3); + eg->name[0] = n1; + eg->name[1] = n2; + eg->name[2] = n3; - return offset; + return eg; } -/* Incorporate one event set into another, get start offset */ -Int CLG_(add_eventset)(EventSet* dst, EventSet* src) +EventGroup* CLG_(register_event_group4)(int id, + Char* n1, Char* n2, Char* n3, Char* n4) { - Int offset = dst->size, i; - if (!src || (src->size == 0)) return offset; + EventGroup* eg = new_event_group(id, 4); + eg->name[0] = n1; + eg->name[1] = n2; + eg->name[2] = n3; + eg->name[3] = n4; - if (dst->capacity - offset < src->size) return -1; - - for(i=0;isize;i++) { - dst->e[offset+i].type = src->e[i].type; - dst->e[offset+i].nextTop = src->e[i].nextTop + offset; - } - dst->size += src->size; + return eg; +} - return offset; +EventGroup* CLG_(get_event_group)(int id) +{ + CLG_ASSERT(id>=0 && idsize; + EventSet* es; + Int i, count, offset; - if (es->capacity - offset < 2) return -1; + if (mask >= MAX_EVENTSET_COUNT) return 0; - es->size += 2; - es->e[offset].type = e1; - es->e[offset].nextTop = es->size; - es->e[offset+1].type = e2; - es->e[offset+1].nextTop = es->size; - - return offset; + initialize_event_sets(); + if (eventSetTable[mask]) return eventSetTable[mask]; + + es = (EventSet*) CLG_MALLOC("cl.events.eventset.1", sizeof(EventSet)); + es->mask = mask; + + offset = 0; + count = 0; + for(i=0;ioffset[i] = offset; + if ( ((mask & (1u<size; + count++; + } + es->size = offset; + es->count = count; + + eventSetTable[mask] = es; + return es; } -/* Incorporate 3 event types into a set, with third < second < first */ -Int CLG_(add_dep_event3)(EventSet* es, - EventType* e1, EventType* e2, EventType* e3) +EventSet* CLG_(get_event_set)(Int id) { - Int offset = es->size; + CLG_ASSERT(id>=0 && idcapacity - offset < 3) return -1; +EventSet* CLG_(get_event_set2)(Int id1, Int id2) +{ + CLG_ASSERT(id1>=0 && id1=0 && id2size += 3; - es->e[offset].type = e1; - es->e[offset].nextTop = es->size; - es->e[offset+1].type = e2; - es->e[offset+1].nextTop = es->size; - es->e[offset+2].type = e3; - es->e[offset+2].nextTop = es->size; - - return offset; +EventSet* CLG_(get_event_set3)(Int id1, Int id2, Int id3) +{ + CLG_ASSERT(id1>=0 && id1=0 && id2=0 && id3size; + CLG_ASSERT(id>=0 && idmask | (1u << id)); +} - if (es->capacity - offset < 4) return -1; +EventSet* CLG_(add_event_group2)(EventSet* es, Int id1, Int id2) +{ + CLG_ASSERT(id1>=0 && id1=0 && id2mask | (1u << id1) | (1u << id2)); +} - es->size += 4; - es->e[offset].type = e1; - es->e[offset].nextTop = es->size; - es->e[offset+1].type = e2; - es->e[offset+1].nextTop = es->size; - es->e[offset+2].type = e3; - es->e[offset+2].nextTop = es->size; - es->e[offset+3].type = e4; - es->e[offset+3].nextTop = es->size; - - return offset; +EventSet* CLG_(add_event_set)(EventSet* es1, EventSet* es2) +{ + if (!es1) es1 = eventset_from_mask(0); + if (!es2) es2 = eventset_from_mask(0); + return eventset_from_mask(es1->mask | es2->mask); } -/* Returns number of characters written */ Int CLG_(sprint_eventset)(Char* buf, EventSet* es) { - Int i, pos = 0; - - for(i=0; i< es->size; i++) { - if (pos>0) buf[pos++] = ' '; - pos += VG_(sprintf)(buf + pos, "%s", es->e[i].type->name); - } - buf[pos] = 0; + Int i, j, pos; + UInt mask; + EventGroup* eg; + + + CLG_ASSERT(es->size >0); + pos = 0; + for(i=0, mask=1; imask & mask)==0) continue; + if (eventGroup[i] ==0) continue; + + eg = eventGroup[i]; + for(j=0; jsize; j++) { + if (pos>0) buf[pos++] = ' '; + pos += VG_(sprintf)(buf + pos, "%s", eg->name[j]); + } + } + buf[pos] = 0; - return pos; + return pos; } + /* Get cost array for an event set */ ULong* CLG_(get_eventset_cost)(EventSet* es) { - return CLG_(get_costarray)(es->capacity); + return CLG_(get_costarray)(es->size); } /* Set all costs of an event set to zero */ void CLG_(init_cost)(EventSet* es, ULong* cost) { - Int i; + Int i; - if (!cost) return; + if (!cost) return; - for(i=0;icapacity;i++) - cost[i] = 0; + for(i=0; isize; i++) + cost[i] = 0; } /* Set all costs of an event set to zero */ void CLG_(init_cost_lz)(EventSet* es, ULong** cost) { - Int i; + Int i; - CLG_ASSERT(cost != 0); - if (!(*cost)) - *cost = CLG_(get_eventset_cost)(es); + CLG_ASSERT(cost != 0); + if (!(*cost)) + *cost = CLG_(get_eventset_cost)(es); - for(i=0;icapacity;i++) - (*cost)[i] = 0; + for(i=0; isize; i++) + (*cost)[i] = 0; } void CLG_(zero_cost)(EventSet* es, ULong* cost) { - Int i; + Int i; - if (!cost) return; + if (!cost) return; - for(i=0;isize;i++) - cost[i] = 0; + for(i=0;isize;i++) + cost[i] = 0; } Bool CLG_(is_zero_cost)(EventSet* es, ULong* cost) { - Int i = 0; + Int i; - if (!cost) return True; + if (!cost) return True; - while(isize) { - if (cost[i] != 0) return False; - i = es->e[i].nextTop; - } - return True; + for(i=0; isize; i++) + if (cost[i] != 0) return False; + + return True; } Bool CLG_(is_equal_cost)(EventSet* es, ULong* c1, ULong* c2) { - Int i = 0; + Int i; - if (!c1) return CLG_(is_zero_cost)(es,c2); - if (!c2) return CLG_(is_zero_cost)(es,c1); + if (!c1) return CLG_(is_zero_cost)(es, c2); + if (!c2) return CLG_(is_zero_cost)(es, c1); - while(isize) { - if (c1[i] != c2[i]) return False; - if (c1[i] == 0) - i = es->e[i].nextTop; - else - i++; - } - return True; + for(i=0; isize; i++) + if (c1[i] != c2[i]) return False; + + return True; } void CLG_(copy_cost)(EventSet* es, ULong* dst, ULong* src) { - Int i; + Int i; - if (!src) { - CLG_(zero_cost)(es, dst); - return; - } - CLG_ASSERT(dst != 0); + if (!src) { + CLG_(zero_cost)(es, dst); + return; + } + CLG_ASSERT(dst != 0); - for(i=0;isize;i++) - dst[i] = src[i]; + for(i=0;isize;i++) + dst[i] = src[i]; } void CLG_(copy_cost_lz)(EventSet* es, ULong** pdst, ULong* src) { - Int i; - ULong* dst; + Int i; + ULong* dst; - CLG_ASSERT(pdst != 0); + CLG_ASSERT(pdst != 0); - if (!src) { - CLG_(zero_cost)(es, *pdst); - return; - } - dst = *pdst; - if (!dst) - dst = *pdst = CLG_(get_eventset_cost)(es); + if (!src) { + CLG_(zero_cost)(es, *pdst); + return; + } + dst = *pdst; + if (!dst) + dst = *pdst = CLG_(get_eventset_cost)(es); - for(i=0;isize;i++) - dst[i] = src[i]; + for(i=0;isize;i++) + dst[i] = src[i]; } void CLG_(add_cost)(EventSet* es, ULong* dst, ULong* src) { - Int i = 0; + Int i; - if (!src) return; - CLG_ASSERT(dst != 0); + if (!src) return; + CLG_ASSERT(dst != 0); - while(isize) { - if (src[i] == 0) - i = es->e[i].nextTop; - else { - dst[i] += src[i]; - i++; - } - } + for(i=0; isize; i++) + dst[i] += src[i]; } void CLG_(add_cost_lz)(EventSet* es, ULong** pdst, ULong* src) { - Int i; - ULong* dst; - - if (!src) return; - CLG_ASSERT(pdst != 0); - - dst = *pdst; - if (!dst) { - dst = *pdst = CLG_(get_eventset_cost)(es); - CLG_(copy_cost)(es,dst,src); - return; - } - - i = 0; - while(isize) { - if (src[i] == 0) - i = es->e[i].nextTop; - else { - dst[i] += src[i]; - i++; + Int i; + ULong* dst; + + if (!src) return; + CLG_ASSERT(pdst != 0); + + dst = *pdst; + if (!dst) { + dst = *pdst = CLG_(get_eventset_cost)(es); + CLG_(copy_cost)(es, dst, src); + return; } - } + + for(i=0; isize; i++) + dst[i] += src[i]; } /* Adds src to dst and zeros src. Returns false if nothing changed */ Bool CLG_(add_and_zero_cost)(EventSet* es, ULong* dst, ULong* src) { - Int i = 0, j = 0; - - CLG_DEBUGIF(6) { - CLG_DEBUG(6, " add_and_zero_cost(%s, dst %p, src %p)\n", es->name, dst, src); - CLG_(print_cost)(-5, es, src); - } + Int i; + Bool is_nonzero = False; - if (!es || !src) return False; + CLG_ASSERT((es != 0) && (dst != 0)); + if (!src) return False; - while(isize) { - if (src[i] == 0) - i = es->e[i].nextTop; - else { - dst[i] += src[i]; - src[i] = 0; - i++; - j++; + for(i=0; isize; i++) { + if (src[i]==0) continue; + dst[i] += src[i]; + src[i] = 0; + is_nonzero = True; } - } - return (j>0); + return is_nonzero; } /* Adds src to dst and zeros src. Returns false if nothing changed */ -Bool CLG_(add_and_zero_cost_lz)(EventSet* es, ULong** pdst, ULong* src) -{ - Int i; - ULong* dst; - - if (!src) return False; - - i = 0; - while(1) { - if (i >= es->size) return False; - if (src[i] != 0) break; - i = es->e[i].nextTop; - } - - CLG_ASSERT(pdst != 0); - dst = *pdst; - if (!dst) { - dst = *pdst = CLG_(get_eventset_cost)(es); - CLG_(copy_cost)(es,dst,src); - CLG_(zero_cost)(es,src); - return True; - } - - dst[i] += src[i]; - src[i] = 0; - i++; - - while(isize) { - if (src[i] == 0) - i = es->e[i].nextTop; - else { - dst[i] += src[i]; - src[i] = 0; +Bool CLG_(add_and_zero_cost2)(EventSet* esDst, ULong* dst, + EventSet* esSrc, ULong* src) +{ + Int i,j; + Bool is_nonzero = False; + UInt mask; + EventGroup *eg; + ULong *egDst, *egSrc; + + CLG_ASSERT((esDst != 0) && (dst != 0) && (esSrc != 0)); + if (!src) return False; + + for(i=0, mask=1; imask & mask)==0) continue; + if (eventGroup[i] ==0) continue; + + /* if src has a subset, dst must have, too */ + CLG_ASSERT((esDst->mask & mask)>0); + eg = eventGroup[i]; + egSrc = src + esSrc->offset[i]; + egDst = dst + esDst->offset[i]; + for(j=0; jsize; j++) { + if (egSrc[j]==0) continue; + egDst[j] += egSrc[j]; + egSrc[j] = 0; + is_nonzero = True; + } } - } - return True; + return is_nonzero; } + + /* Adds difference of new and old to dst, and set old to new. * Returns false if nothing changed */ Bool CLG_(add_diff_cost)(EventSet* es, ULong* dst, ULong* old, ULong* new_cost) { - Int i = 0, j = 0; + Int i; + Bool is_nonzero = False; - while(isize) { - if (new_cost[i] == old[i]) - i = es->e[i].nextTop; - else { - dst[i] += new_cost[i] - old[i]; - old[i] = new_cost[i]; - i++; - j++; + CLG_ASSERT((es != 0) && (dst != 0)); + CLG_ASSERT(old && new_cost); + + for(i=0; isize; i++) { + if (new_cost[i] == old[i]) continue; + dst[i] += new_cost[i] - old[i]; + old[i] = new_cost[i]; + is_nonzero = True; } - } - return (j>0); + return is_nonzero; } -/* Adds difference of new and old to dst, and set old to new. - * Returns false if nothing changed */ -Bool CLG_(add_diff_cost_lz)(EventSet* es, ULong** pdst, - ULong* old, ULong* new_cost) -{ - Int i; - ULong* dst; - - if (!old && !new_cost) return False; - CLG_ASSERT(old && new_cost); - - i = 0; - while(1) { - if (i >= es->size) return False; - if (old[i] != new_cost[i]) break; - i = es->e[i].nextTop; - } - - CLG_ASSERT(pdst != 0); - dst = *pdst; - if (!dst) { - dst = *pdst = CLG_(get_eventset_cost)(es); - CLG_(zero_cost)(es,dst); - } - - dst[i] += new_cost[i] - old[i]; - old[i] = new_cost[i]; - i++; - - while(isize) { - if (new_cost[i] == old[i]) - i = es->e[i].nextTop; - else { - dst[i] += new_cost[i] - old[i]; - old[i] = new_cost[i]; - i++; +Bool CLG_(add_diff_cost_lz)(EventSet* es, ULong** pdst, ULong* old, ULong* new_cost) +{ + Int i; + ULong* dst; + Bool is_nonzero = False; + + CLG_ASSERT((es != 0) && (pdst != 0)); + CLG_ASSERT(old && new_cost); + + dst = *pdst; + if (!dst) { + dst = *pdst = CLG_(get_eventset_cost)(es); + CLG_(zero_cost)(es, dst); } - } - return True; + for(i=0; isize; i++) { + if (new_cost[i] == old[i]) continue; + dst[i] += new_cost[i] - old[i]; + old[i] = new_cost[i]; + is_nonzero = True; + } + + return is_nonzero; } + /* Returns number of characters written */ Int CLG_(sprint_cost)(Char* buf, EventSet* es, ULong* c) { - Int i, pos, skipped = 0; + Int i, pos, skipped = 0; - if (!c || es->size==0) return 0; + if (!c || es->size==0) return 0; - /* At least one entry */ - pos = VG_(sprintf)(buf, "%llu", c[0]); - i = 1; - - while(isize) { - if (c[i] == 0) { - skipped += es->e[i].nextTop - i; - i = es->e[i].nextTop; - } - else { - while(skipped>0) { + /* At least one entry */ + pos = VG_(sprintf)(buf, "%llu", c[0]); + for(i=1; isize; i++) { + if (c[i] == 0) { + skipped++; + continue; + } + while(skipped>0) { + buf[pos++] = ' '; + buf[pos++] = '0'; + skipped--; + } buf[pos++] = ' '; - buf[pos++] = '0'; - skipped--; - } - buf[pos++] = ' '; - pos += VG_(sprintf)(buf+pos, "%llu", c[i]); - i++; + pos += VG_(sprintf)(buf+pos, "%llu", c[i]); } - } - return pos; + return pos; } /* Allocate space for an event mapping */ EventMapping* CLG_(get_eventmapping)(EventSet* es) { - EventMapping* em; + EventMapping* em; - CLG_ASSERT(es != 0); + CLG_ASSERT(es != 0); - em = (EventMapping*) CLG_MALLOC("cl.events.geMapping.1", - sizeof(EventMapping) + - es->capacity * sizeof(Int)); - em->capacity = es->capacity; - em->size = 0; - em->set = es; + em = (EventMapping*) CLG_MALLOC("cl.events.geMapping.1", + sizeof(EventMapping) + + sizeof(struct EventMappingEntry) * + es->size); + em->capacity = es->size; + em->size = 0; + em->es = es; - return em; + return em; } void CLG_(append_event)(EventMapping* em, Char* n) { - Int i; - - CLG_ASSERT(em != 0); - - for(i=0; iset->size; i++) - if (VG_(strcmp)(n, em->set->e[i].type->name)==0) - break; - - if (i == em->set->size) return; - - CLG_ASSERT(em->capacity > em->size); - - em->index[em->size] = i; - em->size++; + Int i, j, offset = 0; + UInt mask; + EventGroup* eg; + + CLG_ASSERT(em != 0); + for(i=0, mask=1; ies->mask & mask)==0) continue; + if (eventGroup[i] ==0) continue; + + eg = eventGroup[i]; + for(j=0; jsize; j++, offset++) { + if (VG_(strcmp)(n, eg->name[j])!=0) + continue; + + CLG_ASSERT(em->capacity > em->size); + em->entry[em->size].group = i; + em->entry[em->size].index = j; + em->entry[em->size].offset = offset; + em->size++; + return; + } + } } /* Returns number of characters written */ Int CLG_(sprint_eventmapping)(Char* buf, EventMapping* em) { - Int i, pos = 0; + Int i, pos = 0; + EventGroup* eg; - CLG_ASSERT(em != 0); + CLG_ASSERT(em != 0); - for(i=0; i< em->size; i++) { - if (pos>0) buf[pos++] = ' '; - pos += VG_(sprintf)(buf + pos, "%s", em->set->e[em->index[i]].type->name); - } - buf[pos] = 0; + for(i=0; i< em->size; i++) { + if (pos>0) buf[pos++] = ' '; + eg = eventGroup[em->entry[i].group]; + CLG_ASSERT(eg != 0); + pos += VG_(sprintf)(buf + pos, "%s", eg->name[em->entry[i].index]); + } + buf[pos] = 0; - return pos; + return pos; } /* Returns number of characters written */ Int CLG_(sprint_mappingcost)(Char* buf, EventMapping* em, ULong* c) { - Int i, pos, skipped = 0; + Int i, pos, skipped = 0; - if (!c || em->size==0) return 0; + if (!c || em->size==0) return 0; /* At least one entry */ - pos = VG_(sprintf)(buf, "%llu", c[em->index[0]]); - i = 1; - - while(isize) { - if (c[em->index[i]] == 0) { - skipped++; - i++; - } - else { - while(skipped>0) { + pos = VG_(sprintf)(buf, "%llu", c[em->entry[0].offset]); + + for(i=1; isize; i++) { + if (c[em->entry[i].offset] == 0) { + skipped++; + continue; + } + while(skipped>0) { + buf[pos++] = ' '; + buf[pos++] = '0'; + skipped--; + } buf[pos++] = ' '; - buf[pos++] = '0'; - skipped--; - } - buf[pos++] = ' '; - pos += VG_(sprintf)(buf+pos, "%llu", c[em->index[i]]); - i++; + pos += VG_(sprintf)(buf+pos, "%llu", c[em->entry[i].offset]); } - } - return pos; + return pos; } diff --git a/callgrind/events.h b/callgrind/events.h index c3ddbe3..d892ccb 100644 --- a/callgrind/events.h +++ b/callgrind/events.h @@ -1,86 +1,90 @@ /*--------------------------------------------------------------------*/ /*--- Callgrind ---*/ /*--- events.h ---*/ -/*--- (C) 2004-2005, Josef Weidendorfer ---*/ /*--------------------------------------------------------------------*/ +/* + This file is part of Callgrind, a Valgrind tool for call tracing. + + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ /* Abstractions for 64-bit cost lists (events.h) */ -#ifndef CG_EVENTS -#define CG_EVENTS +#ifndef CLG_EVENTS +#define CLG_EVENTS #include "pub_tool_basics.h" #define CLG_(str) VGAPPEND(vgCallgrind_,str) -/* An event type */ -typedef struct _EventType EventType; -struct _EventType { - Char* name; - Char* description; - Int id; -}; +/* Event groups consist of one or more named event types. + * Event sets are constructed from such event groups. + * + * Event groups have to be registered globally with a unique ID + * before they can be used in an event set. + * A group can appear at most once in a event set. + */ -EventType* CLG_(register_eventtype)(Char*); -EventType* CLG_(get_eventtype)(Char*); -EventType* CLG_(get_eventtype_byindex)(Int id); +#define MAX_EVENTGROUP_COUNT 10 -/* An event set is a ordered list of event types, which comes down - * to some description for ordered lists of costs. - * Often, costs of 2 event types are related, e.g. one is always smaller - * than the other. This is useful to speed up arithmetics on cost lists: - * Each event type in the set has a . All indexes before are - * promised to hold smaller values than the current. - */ -typedef struct _EventSetEntry EventSetEntry; -struct _EventSetEntry { - EventType* type; - Int nextTop; -}; -typedef struct _EventSet EventSet; -struct _EventSet { - Char* name; - Int size; - Int capacity; - EventSetEntry e[0]; +typedef struct _EventGroup EventGroup; +struct _EventGroup { + Int size; + Char* name[0]; }; +/* return 0 if event group can not be registered */ +EventGroup* CLG_(register_event_group) (int id, Char*); +EventGroup* CLG_(register_event_group2)(int id, Char*, Char*); +EventGroup* CLG_(register_event_group3)(int id, Char*, Char*, Char*); +EventGroup* CLG_(register_event_group4)(int id, Char*, Char*, Char*, Char*); +EventGroup* CLG_(get_event_group)(int id); -/* Some events out of an event set. - * Used to print out part of an EventSet, or in another order. - */ -typedef struct _EventMapping EventMapping; -struct _EventMapping { - EventSet* set; - Int size; - Int capacity; - Int index[0]; -}; +/* Event sets are defined by event groups they consist of. */ - -/* Allocate space for an event set */ -EventSet* CLG_(get_eventset)(Char* n, Int capacity); -/* Incorporate a event type into a set, get start offset */ -Int CLG_(add_eventtype)(EventSet* dst, EventType*); -/* Incorporate event types into a set, with ... < second < first */ -Int CLG_(add_dep_event2)(EventSet* dst, EventType* e1, EventType* e2); -Int CLG_(add_dep_event3)(EventSet* dst, - EventType* e1, EventType* e2, EventType* e3); -Int CLG_(add_dep_event4)(EventSet* dst, - EventType* e1, EventType* e2, EventType* e3, - EventType* e4); -/* Incorporate one event set into another, get start offset */ -Int CLG_(add_eventset)(EventSet* dst, EventSet* src); -/* Returns number of characters written */ +typedef struct _EventSet EventSet; +struct _EventSet { + /* if subset with ID x is in the set, then bit x is set */ + UInt mask; + Int count; + Int size; + Int offset[MAX_EVENTGROUP_COUNT]; + }; + +/* Same event set is returned when requesting same event groups */ +EventSet* CLG_(get_event_set)(Int id); +EventSet* CLG_(get_event_set2)(Int id1, Int id2); +EventSet* CLG_(get_event_set3)(Int id1, Int id2, Int id3); +EventSet* CLG_(add_event_group)(EventSet*, Int id); +EventSet* CLG_(add_event_group2)(EventSet*, Int id1, Int id2); +EventSet* CLG_(add_event_set)(EventSet*, EventSet*); +/* Writes event names into buf. Returns number of characters written */ Int CLG_(sprint_eventset)(Char* buf, EventSet*); -/* Allocate cost array for an event set */ -ULong* CLG_(get_eventset_cost)(EventSet*); + /* Operations on costs. A cost pointer of 0 means zero cost. - * Functions ending in _lz allocate costs lazy if needed + * Functions ending in _lz allocate cost arrays only when needed */ -/* Set costs according full capacity of event set to 0 */ +ULong* CLG_(get_eventset_cost)(EventSet*); +/* Set costs of event set to 0 */ void CLG_(init_cost)(EventSet*,ULong*); /* This always allocates counter and sets them to 0 */ void CLG_(init_cost_lz)(EventSet*,ULong**); @@ -94,7 +98,7 @@ void CLG_(add_cost)(EventSet*,ULong* dst, ULong* src); void CLG_(add_cost_lz)(EventSet*,ULong** pdst, ULong* src); /* Adds src to dst and zeros src. Returns false if nothing changed */ Bool CLG_(add_and_zero_cost)(EventSet*,ULong* dst, ULong* src); -Bool CLG_(add_and_zero_cost_lz)(EventSet*,ULong** pdst, ULong* src); +Bool CLG_(add_and_zero_cost2)(EventSet*,ULong* dst,EventSet*,ULong* src); /* Adds difference of new and old to to dst, and set old to new. * Returns false if nothing changed */ Bool CLG_(add_diff_cost)(EventSet*,ULong* dst, ULong* old, ULong* new_cost); @@ -102,6 +106,22 @@ Bool CLG_(add_diff_cost_lz)(EventSet*,ULong** pdst, ULong* old, ULong* new_cost) /* Returns number of characters written */ Int CLG_(sprint_cost)(Char* buf, EventSet*, ULong*); +/* EventMapping: An ordered subset of events from an event set. + * This is used to print out part of an EventSet, or in another order. + */ +struct EventMappingEntry { + Int group; + Int index; + Int offset; +}; +typedef struct _EventMapping EventMapping; +struct _EventMapping { + EventSet* es; + Int size; + Int capacity; + struct EventMappingEntry entry[0]; +}; + /* Allocate space for an event mapping */ EventMapping* CLG_(get_eventmapping)(EventSet*); void CLG_(append_event)(EventMapping*, Char*); @@ -110,4 +130,4 @@ Int CLG_(sprint_eventmapping)(Char* buf, EventMapping*); /* Returns number of characters written */ Int CLG_(sprint_mappingcost)(Char* buf, EventMapping*, ULong*); -#endif /* CG_EVENTS */ +#endif /* CLG_EVENTS */ diff --git a/callgrind/fn.c b/callgrind/fn.c index 6ed6f60..288a7f4 100644 --- a/callgrind/fn.c +++ b/callgrind/fn.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/callgrind/global.h b/callgrind/global.h index 367f2d7..bfb5a48 100644 --- a/callgrind/global.h +++ b/callgrind/global.h @@ -87,9 +87,12 @@ struct _CommandLineOptions { Bool collect_alloc; /* Collect size of allocated memory */ Bool collect_systime; /* Collect time for system calls */ + Bool collect_bus; /* Collect global bus events */ + /* Instrument options */ Bool instrument_atstart; /* Instrument at start? */ Bool simulate_cache; /* Call into cache simulator ? */ + Bool simulate_branch; /* Call into branch prediction simulator ? */ /* Call graph generation */ Bool pop_on_jump; /* Handle a jump between functions as ret+call */ @@ -115,9 +118,10 @@ struct _CommandLineOptions { #define FILENAME_LEN 256 #define FN_NAME_LEN 4096 /* for C++ code :-) */ #define OBJ_NAME_LEN 256 +#define COSTS_LEN 512 /* at least 17x 64bit values */ #define BUF_LEN 512 #define COMMIFY_BUF_LEN 128 -#define RESULTS_BUF_LEN 128 +#define RESULTS_BUF_LEN 256 #define LINE_BUF_LEN 64 @@ -650,9 +654,8 @@ struct cachesim_if void (*post_clo_init)(void); void (*clear)(void); void (*getdesc)(Char* buf); - void (*printstat)(void); + void (*printstat)(Int,Int,Int); void (*add_icost)(SimCost, BBCC*, InstrInfo*, ULong); - void (*after_bbsetup)(void); void (*finish)(void); void (*log_1I0D)(InstrInfo*) VG_REGPARM(1); @@ -671,6 +674,28 @@ struct cachesim_if Char *log_0I1Dr_name, *log_0I1Dw_name; }; +// set by setup_bbcc at start of every BB, and needed by log_* helpers +extern Addr CLG_(bb_base); +extern ULong* CLG_(cost_base); + +// Event groups +#define EG_USE 0 +#define EG_IR 1 +#define EG_DR 2 +#define EG_DW 3 +#define EG_BC 4 +#define EG_BI 5 +#define EG_BUS 6 +#define EG_ALLOC 7 +#define EG_SYS 8 + +struct event_sets { + EventSet *base, *full; +}; +extern struct event_sets CLG_(sets); + +#define fullOffset(group) (CLG_(sets).full->offset[group]) + /*------------------------------------------------------------*/ /*--- Functions ---*/ @@ -685,20 +710,8 @@ void CLG_(print_usage)(void); void CLG_(print_debug_usage)(void); /* from sim.c */ -struct event_sets { - EventSet *Use, *Ir, *Dr, *Dw; - EventSet *UIr, *UIrDr, *UIrDrDw, *UIrDw, *UIrDwDr; - EventSet *full; - - /* offsets into eventsets */ - Int off_full_Ir, off_full_Dr, off_full_Dw; - Int off_full_alloc, off_full_systime; -}; - -extern struct event_sets CLG_(sets); extern struct cachesim_if CLG_(cachesim); - -void CLG_(init_eventsets)(Int user); +void CLG_(init_eventsets)(void); /* from main.c */ Bool CLG_(get_debug_info)(Addr, Char filename[FILENAME_LEN], diff --git a/callgrind/jumps.c b/callgrind/jumps.c index 668eda8..fc306af 100644 --- a/callgrind/jumps.c +++ b/callgrind/jumps.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/callgrind/main.c b/callgrind/main.c index fa6a90e..4223ddf 100644 --- a/callgrind/main.c +++ b/callgrind/main.c @@ -8,10 +8,10 @@ This file is part of Callgrind, a Valgrind tool for call graph profiling programs. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This tool is derived from and contains code from Cachegrind - Copyright (C) 2002-2009 Nicholas Nethercote (njn@valgrind.org) + Copyright (C) 2002-2010 Nicholas Nethercote (njn@valgrind.org) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -37,6 +37,8 @@ #include +#include "cg_branchpred.c" + /*------------------------------------------------------------*/ /*--- Global variables ---*/ /*------------------------------------------------------------*/ @@ -94,6 +96,97 @@ static void CLG_(init_statistics)(Statistics* s) } +/*------------------------------------------------------------*/ +/*--- Simple callbacks (not cache similator) ---*/ +/*------------------------------------------------------------*/ + +VG_REGPARM(1) +static void log_global_event(InstrInfo* ii) +{ + ULong* cost_Bus; + + CLG_DEBUG(6, "log_global_event: Ir %#lx/%u\n", + CLG_(bb_base) + ii->instr_offset, ii->instr_size); + + if (!CLG_(current_state).collect) return; + + CLG_ASSERT( (ii->eventset->mask & (1u<0 ); + + CLG_(current_state).cost[ fullOffset(EG_BUS) ]++; + + if (CLG_(current_state).nonskipped) + cost_Bus = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BUS); + else + cost_Bus = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BUS]; + cost_Bus[0]++; +} + + +/* For branches, we consult two different predictors, one which + predicts taken/untaken for conditional branches, and the other + which predicts the branch target address for indirect branches + (jump-to-register style ones). */ + +static VG_REGPARM(2) +void log_cond_branch(InstrInfo* ii, Word taken) +{ + Bool miss; + Int fullOffset_Bc; + ULong* cost_Bc; + + CLG_DEBUG(6, "log_cond_branch: Ir %#lx, taken %lu\n", + CLG_(bb_base) + ii->instr_offset, taken); + + miss = 1 & do_cond_branch_predict(CLG_(bb_base) + ii->instr_offset, taken); + + if (!CLG_(current_state).collect) return; + + CLG_ASSERT( (ii->eventset->mask & (1u<0 ); + + if (CLG_(current_state).nonskipped) + cost_Bc = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BC); + else + cost_Bc = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BC]; + + fullOffset_Bc = fullOffset(EG_BC); + CLG_(current_state).cost[ fullOffset_Bc ]++; + cost_Bc[0]++; + if (miss) { + CLG_(current_state).cost[ fullOffset_Bc+1 ]++; + cost_Bc[1]++; + } +} + +static VG_REGPARM(2) +void log_ind_branch(InstrInfo* ii, UWord actual_dst) +{ + Bool miss; + Int fullOffset_Bi; + ULong* cost_Bi; + + CLG_DEBUG(6, "log_ind_branch: Ir %#lx, dst %#lx\n", + CLG_(bb_base) + ii->instr_offset, actual_dst); + + miss = 1 & do_ind_branch_predict(CLG_(bb_base) + ii->instr_offset, actual_dst); + + if (!CLG_(current_state).collect) return; + + CLG_ASSERT( (ii->eventset->mask & (1u<0 ); + + if (CLG_(current_state).nonskipped) + cost_Bi = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BI); + else + cost_Bi = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BI]; + + fullOffset_Bi = fullOffset(EG_BI); + CLG_(current_state).cost[ fullOffset_Bi ]++; + cost_Bi[0]++; + if (miss) { + CLG_(current_state).cost[ fullOffset_Bi+1 ]++; + cost_Bi[1]++; + } +} + /*------------------------------------------------------------*/ /*--- Instrumentation structures and event queue handling ---*/ /*------------------------------------------------------------*/ @@ -137,6 +230,9 @@ typedef Ev_Dr, // Data read Ev_Dw, // Data write Ev_Dm, // Data modify (read then write) + Ev_Bc, // branch conditional + Ev_Bi, // branch indirect (to unknown destination) + Ev_G // Global bus event } EventTag; @@ -159,6 +255,14 @@ typedef IRAtom* ea; Int szB; } Dm; + struct { + IRAtom* taken; /* :: Ity_I1 */ + } Bc; + struct { + IRAtom* dst; + } Bi; + struct { + } G; } Ev; } Event; @@ -242,6 +346,19 @@ static void showEvent ( Event* ev ) ppIRExpr(ev->Ev.Dm.ea); VG_(printf)("\n"); break; + case Ev_Bc: + VG_(printf)("Bc %p GA=", ev->inode); + ppIRExpr(ev->Ev.Bc.taken); + VG_(printf)("\n"); + break; + case Ev_Bi: + VG_(printf)("Bi %p DST=", ev->inode); + ppIRExpr(ev->Ev.Bi.dst); + VG_(printf)("\n"); + break; + case Ev_G: + VG_(printf)("G %p\n", ev->inode); + break; default: tl_assert(0); break; @@ -273,34 +390,33 @@ static void flushEvents ( ClgState* clgs ) case Ev_Ir: // Ir event always is first for a guest instruction CLG_ASSERT(ev->inode->eventset == 0); - ev->inode->eventset = CLG_(sets).UIr; + ev->inode->eventset = CLG_(sets).base; break; case Ev_Dr: - // extend event set by Dr counter - if ((ev->inode->eventset == CLG_(sets).UIrDr) || - (ev->inode->eventset == CLG_(sets).UIrDrDw) || - (ev->inode->eventset == CLG_(sets).UIrDwDr)) - break; - if (ev->inode->eventset == CLG_(sets).UIrDw) { - ev->inode->eventset = CLG_(sets).UIrDwDr; - break; - } - CLG_ASSERT(ev->inode->eventset == CLG_(sets).UIr); - ev->inode->eventset = CLG_(sets).UIrDr; + // extend event set by Dr counters + ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset, + EG_DR); break; case Ev_Dw: case Ev_Dm: - // extend event set by Dw counter - if ((ev->inode->eventset == CLG_(sets).UIrDw) || - (ev->inode->eventset == CLG_(sets).UIrDwDr) || - (ev->inode->eventset == CLG_(sets).UIrDrDw)) - break; - if (ev->inode->eventset == CLG_(sets).UIrDr) { - ev->inode->eventset = CLG_(sets).UIrDrDw; - break; - } - CLG_ASSERT(ev->inode->eventset == CLG_(sets).UIr); - ev->inode->eventset = CLG_(sets).UIrDw; + // extend event set by Dw counters + ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset, + EG_DW); + break; + case Ev_Bc: + // extend event set by Bc counters + ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset, + EG_BC); + break; + case Ev_Bi: + // extend event set by Bi counters + ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset, + EG_BI); + break; + case Ev_G: + // extend event set by Bus counter + ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset, + EG_BUS); break; default: tl_assert(0); @@ -417,6 +533,30 @@ static void flushEvents ( ClgState* clgs ) regparms = 3; inew = i+1; break; + case Ev_Bc: + /* Conditional branch */ + helperName = "log_cond_branch"; + helperAddr = &log_cond_branch; + argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bc.taken ); + regparms = 2; + inew = i+1; + break; + case Ev_Bi: + /* Branch to an unknown destination */ + helperName = "log_ind_branch"; + helperAddr = &log_ind_branch; + argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bi.dst ); + regparms = 2; + inew = i+1; + break; + case Ev_G: + /* Global bus event (CAS, LOCK-prefix, LL-SC, etc) */ + helperName = "log_global_event"; + helperAddr = &log_global_event; + argv = mkIRExprVec_1( i_node_expr ); + regparms = 1; + inew = i+1; + break; default: tl_assert(0); } @@ -521,6 +661,62 @@ void addEvent_Dw ( ClgState* clgs, InstrInfo* inode, Int datasize, IRAtom* ea ) clgs->events_used++; } +static +void addEvent_Bc ( ClgState* clgs, InstrInfo* inode, IRAtom* guard ) +{ + Event* evt; + tl_assert(isIRAtom(guard)); + tl_assert(typeOfIRExpr(clgs->sbOut->tyenv, guard) + == (sizeof(HWord)==4 ? Ity_I32 : Ity_I64)); + if (!CLG_(clo).simulate_branch) return; + + if (clgs->events_used == N_EVENTS) + flushEvents(clgs); + tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS); + evt = &clgs->events[clgs->events_used]; + init_Event(evt); + evt->tag = Ev_Bc; + evt->inode = inode; + evt->Ev.Bc.taken = guard; + clgs->events_used++; +} + +static +void addEvent_Bi ( ClgState* clgs, InstrInfo* inode, IRAtom* whereTo ) +{ + Event* evt; + tl_assert(isIRAtom(whereTo)); + tl_assert(typeOfIRExpr(clgs->sbOut->tyenv, whereTo) + == (sizeof(HWord)==4 ? Ity_I32 : Ity_I64)); + if (!CLG_(clo).simulate_branch) return; + + if (clgs->events_used == N_EVENTS) + flushEvents(clgs); + tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS); + evt = &clgs->events[clgs->events_used]; + init_Event(evt); + evt->tag = Ev_Bi; + evt->inode = inode; + evt->Ev.Bi.dst = whereTo; + clgs->events_used++; +} + +static +void addEvent_G ( ClgState* clgs, InstrInfo* inode ) +{ + Event* evt; + if (!CLG_(clo).collect_bus) return; + + if (clgs->events_used == N_EVENTS) + flushEvents(clgs); + tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS); + evt = &clgs->events[clgs->events_used]; + init_Event(evt); + evt->tag = Ev_G; + evt->inode = inode; + clgs->events_used++; +} + /* Initialise or check (if already seen before) an InstrInfo for next insn. We only can set instr_offset/instr_size here. The required event set and resulting cost offset depend on events (Ir/Dr/Dw/Dm) in guest @@ -657,14 +853,8 @@ void CLG_(collectBlockInfo)(IRSB* sbIn, static void addConstMemStoreStmt( IRSB* bbOut, UWord addr, UInt val, IRType hWordTy) { - /* JRS 2009june01: re IRTemp_INVALID, am assuming that this - function is used only to create instrumentation, and not to - copy/reconstruct IRStmt_Stores that were in the incoming IR - superblock. If that is not a correct assumption, then things - will break badly on PowerPC, esp w/ threaded apps. */ addStmtToIRSB( bbOut, IRStmt_Store(CLGEndness, - IRTemp_INVALID, IRExpr_Const(hWordTy == Ity_I32 ? IRConst_U32( addr ) : IRConst_U64( addr )), @@ -717,6 +907,7 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure, Int i, isize; IRStmt* st; Addr origAddr; + Addr64 cia; /* address of current insn */ InstrInfo* curr_inode = NULL; ClgState clgs; UInt cJumps = 0; @@ -753,6 +944,8 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure, CLG_ASSERT(Ist_IMark == st->tag); origAddr = (Addr)st->Ist.IMark.addr; + cia = st->Ist.IMark.addr; + isize = st->Ist.IMark.len; CLG_ASSERT(origAddr == st->Ist.IMark.addr); // XXX: check no overflow /* Get BB struct (creating if necessary). @@ -783,8 +976,9 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure, break; case Ist_IMark: { - CLG_ASSERT(clgs.instr_offset == (Addr)st->Ist.IMark.addr - origAddr); - isize = st->Ist.IMark.len; + cia = st->Ist.IMark.addr; + isize = st->Ist.IMark.len; + CLG_ASSERT(clgs.instr_offset == (Addr)cia - origAddr); // If Vex fails to decode an instruction, the size will be zero. // Pretend otherwise. if (isize == 0) isize = VG_MIN_INSTR_SZB; @@ -862,11 +1056,90 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure, dataSize *= 2; /* since this is a doubleword-cas */ addEvent_Dr( &clgs, curr_inode, dataSize, cas->addr ); addEvent_Dw( &clgs, curr_inode, dataSize, cas->addr ); + addEvent_G( &clgs, curr_inode ); + break; + } + + case Ist_LLSC: { + IRType dataTy; + if (st->Ist.LLSC.storedata == NULL) { + /* LL */ + dataTy = typeOfIRTemp(sbIn->tyenv, st->Ist.LLSC.result); + addEvent_Dr( &clgs, curr_inode, + sizeofIRType(dataTy), st->Ist.LLSC.addr ); + } else { + /* SC */ + dataTy = typeOfIRExpr(sbIn->tyenv, st->Ist.LLSC.storedata); + addEvent_Dw( &clgs, curr_inode, + sizeofIRType(dataTy), st->Ist.LLSC.addr ); + /* I don't know whether the global-bus-lock cost should + be attributed to the LL or the SC, but it doesn't + really matter since they always have to be used in + pairs anyway. Hence put it (quite arbitrarily) on + the SC. */ + addEvent_G( &clgs, curr_inode ); + } break; } - - case Ist_Exit: { - UInt jmps_passed; + + case Ist_Exit: { + Bool guest_exit, inverted; + + /* VEX code generation sometimes inverts conditional branches. + * As Callgrind counts (conditional) jumps, it has to correct + * inversions. The heuristic is the following: + * (1) Callgrind switches off SB chasing and unrolling, and + * therefore it assumes that a candidate for inversion only is + * the last conditional branch in an SB. + * (2) inversion is assumed if the branch jumps to the address of + * the next guest instruction in memory. + * This heuristic is precalculated in CLG_(collectBlockInfo)(). + * + * Branching behavior is also used for branch prediction. Note that + * above heuristic is different from what Cachegrind does. + * Cachegrind uses (2) for all branches. + */ + if (cJumps+1 == clgs.bb->cjmp_count) + inverted = clgs.bb->cjmp_inverted; + else + inverted = False; + + // call branch predictor only if this is a branch in guest code + guest_exit = (st->Ist.Exit.jk == Ijk_Boring) || + (st->Ist.Exit.jk == Ijk_Call) || + (st->Ist.Exit.jk == Ijk_Ret); + + if (guest_exit) { + /* Stuff to widen the guard expression to a host word, so + we can pass it to the branch predictor simulation + functions easily. */ + IRType tyW = hWordTy; + IROp widen = tyW==Ity_I32 ? Iop_1Uto32 : Iop_1Uto64; + IROp opXOR = tyW==Ity_I32 ? Iop_Xor32 : Iop_Xor64; + IRTemp guard1 = newIRTemp(clgs.sbOut->tyenv, Ity_I1); + IRTemp guardW = newIRTemp(clgs.sbOut->tyenv, tyW); + IRTemp guard = newIRTemp(clgs.sbOut->tyenv, tyW); + IRExpr* one = tyW==Ity_I32 ? IRExpr_Const(IRConst_U32(1)) + : IRExpr_Const(IRConst_U64(1)); + + /* Widen the guard expression. */ + addStmtToIRSB( clgs.sbOut, + IRStmt_WrTmp( guard1, st->Ist.Exit.guard )); + addStmtToIRSB( clgs.sbOut, + IRStmt_WrTmp( guardW, + IRExpr_Unop(widen, + IRExpr_RdTmp(guard1))) ); + /* If the exit is inverted, invert the sense of the guard. */ + addStmtToIRSB( + clgs.sbOut, + IRStmt_WrTmp( + guard, + inverted ? IRExpr_Binop(opXOR, IRExpr_RdTmp(guardW), one) + : IRExpr_RdTmp(guardW) + )); + /* And post the event. */ + addEvent_Bc( &clgs, curr_inode, IRExpr_RdTmp(guard) ); + } /* We may never reach the next statement, so need to flush all outstanding transactions now. */ @@ -881,12 +1154,9 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure, /* Update global variable jmps_passed before the jump * A correction is needed if VEX inverted the last jump condition */ - jmps_passed = cJumps; - if ((cJumps+1 == clgs.bb->cjmp_count) && clgs.bb->cjmp_inverted) - jmps_passed++; addConstMemStoreStmt( clgs.sbOut, (UWord) &CLG_(current_state).jmps_passed, - jmps_passed, hWordTy); + inverted ? cJumps+1 : cJumps, hWordTy); cJumps++; break; @@ -907,6 +1177,26 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure, } } + /* Deal with branches to unknown destinations. Except ignore ones + which are function returns as we assume the return stack + predictor never mispredicts. */ + if ((sbIn->jumpkind == Ijk_Boring) || (sbIn->jumpkind == Ijk_Call)) { + if (0) { ppIRExpr( sbIn->next ); VG_(printf)("\n"); } + switch (sbIn->next->tag) { + case Iex_Const: + break; /* boring - branch to known address */ + case Iex_RdTmp: + /* looks like an indirect branch (branch to unknown) */ + addEvent_Bi( &clgs, curr_inode, sbIn->next ); + break; + default: + /* shouldn't happen - if the incoming IR is properly + flattened, should only have tmp and const cases to + consider. */ + tl_assert(0); + } + } + /* At the end of the bb. Flush outstandings. */ flushEvents( &clgs ); @@ -1151,7 +1441,7 @@ void CLG_(post_syscalltime)(ThreadId tid, UInt syscallno, { if (CLG_(clo).collect_systime && CLG_(current_state).bbcc) { - Int o = CLG_(sets).off_full_systime; + Int o; #if CLG_MICROSYSTIME struct vki_timeval tv_now; ULong diff; @@ -1161,11 +1451,12 @@ void CLG_(post_syscalltime)(ThreadId tid, UInt syscallno, #else UInt diff = VG_(read_millisecond_timer)() - syscalltime[tid]; #endif - + + /* offset o is for "SysCount", o+1 for "SysTime" */ + o = fullOffset(EG_SYS); + CLG_ASSERT(o>=0); CLG_DEBUG(0," Time (Off %d) for Syscall %d: %ull\n", o, syscallno, diff); - if (o<0) return; - CLG_(current_state).cost[o] ++; CLG_(current_state).cost[o+1] += diff; if (!CLG_(current_state).bbcc->skipped) @@ -1176,10 +1467,61 @@ void CLG_(post_syscalltime)(ThreadId tid, UInt syscallno, } } +static UInt ULong_width(ULong n) +{ + UInt w = 0; + while (n > 0) { + n = n / 10; + w++; + } + if (w == 0) w = 1; + return w + (w-1)/3; // add space for commas +} + +static +void branchsim_printstat(int l1, int l2, int l3) +{ + static Char buf1[128], buf2[128], buf3[128], fmt[128]; + FullCost total; + ULong Bc_total_b, Bc_total_mp, Bi_total_b, Bi_total_mp; + ULong B_total_b, B_total_mp; + + total = CLG_(total_cost); + Bc_total_b = total[ fullOffset(EG_BC) ]; + Bc_total_mp = total[ fullOffset(EG_BC)+1 ]; + Bi_total_b = total[ fullOffset(EG_BI) ]; + Bi_total_mp = total[ fullOffset(EG_BI)+1 ]; + + /* Make format string, getting width right for numbers */ + VG_(sprintf)(fmt, "%%s %%,%dllu (%%,%dllu cond + %%,%dllu ind)\n", + l1, l2, l3); + + if (0 == Bc_total_b) Bc_total_b = 1; + if (0 == Bi_total_b) Bi_total_b = 1; + B_total_b = Bc_total_b + Bi_total_b; + B_total_mp = Bc_total_mp + Bi_total_mp; + + VG_(umsg)("\n"); + VG_(umsg)(fmt, "Branches: ", + B_total_b, Bc_total_b, Bi_total_b); + + VG_(umsg)(fmt, "Mispredicts: ", + B_total_mp, Bc_total_mp, Bi_total_mp); + + VG_(percentify)(B_total_mp, B_total_b, 1, l1+1, buf1); + VG_(percentify)(Bc_total_mp, Bc_total_b, 1, l2+1, buf2); + VG_(percentify)(Bi_total_mp, Bi_total_b, 1, l3+1, buf3); + + VG_(umsg)("Mispred rate: %s (%s + %s )\n", buf1, buf2,buf3); +} + + static void finish(void) { - char buf[RESULTS_BUF_LEN]; + Char buf[32+COSTS_LEN], fmt[128]; + Int l1, l2, l3; + FullCost total; CLG_DEBUG(0, "finish()\n"); @@ -1274,8 +1616,33 @@ void finish(void) VG_(message)(Vg_UserMsg, "Collected : %s\n", buf); VG_(message)(Vg_UserMsg, "\n"); - // if (CLG_(clo).simulate_cache) - (*CLG_(cachesim).printstat)(); + /* determine value widths for statistics */ + total = CLG_(total_cost); + l1 = ULong_width( total[fullOffset(EG_IR)] ); + l2 = l3 = 0; + if (CLG_(clo).simulate_cache) { + l2 = ULong_width( total[fullOffset(EG_DR)] ); + l3 = ULong_width( total[fullOffset(EG_DW)] ); + } + if (CLG_(clo).simulate_branch) { + int l2b = ULong_width( total[fullOffset(EG_BC)] ); + int l3b = ULong_width( total[fullOffset(EG_BI)] ); + if (l2b > l2) l2 = l2b; + if (l3b > l3) l3 = l3b; + } + + /* Make format string, getting width right for numbers */ + VG_(sprintf)(fmt, "%%s %%,%dllu\n", l1); + + /* Always print this */ + VG_(umsg)(fmt, "I refs: ", total[fullOffset(EG_IR)] ); + + if (CLG_(clo).simulate_cache) + (*CLG_(cachesim).printstat)(l1, l2, l3); + + if (CLG_(clo).simulate_branch) + branchsim_printstat(l1, l2, l3); + } @@ -1323,7 +1690,7 @@ void CLG_(post_clo_init)(void) (*CLG_(cachesim).post_clo_init)(); - CLG_(init_eventsets)(0); + CLG_(init_eventsets)(); CLG_(init_statistics)(& CLG_(stat)); CLG_(init_cost_lz)( CLG_(sets).full, &CLG_(total_cost) ); @@ -1349,7 +1716,7 @@ void CLG_(pre_clo_init)(void) VG_(details_name) ("Callgrind"); VG_(details_version) (NULL); VG_(details_description) ("a call-graph generating cache profiler"); - VG_(details_copyright_author)("Copyright (C) 2002-2009, and GNU GPL'd, " + VG_(details_copyright_author)("Copyright (C) 2002-2010, and GNU GPL'd, " "by Josef Weidendorfer et al."); VG_(details_bug_reports_to) (VG_BUGS_TO); VG_(details_avg_translation_sizeB) ( 500 ); diff --git a/callgrind/sim.c b/callgrind/sim.c index a84ee5a..2b8cbe4 100644 --- a/callgrind/sim.c +++ b/callgrind/sim.c @@ -1,4 +1,3 @@ - /*--------------------------------------------------------------------*/ /*--- Cache simulation. ---*/ /*--- sim.c ---*/ @@ -8,10 +7,10 @@ This file is part of Callgrind, a Valgrind tool for call graph profiling programs. - Copyright (C) 2003-2005, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2003-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This tool is derived from and contains code from Cachegrind - Copyright (C) 2002-2009 Nicholas Nethercote (njn@valgrind.org) + Copyright (C) 2002-2010 Nicholas Nethercote (njn@valgrind.org) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -92,7 +91,7 @@ typedef struct { * States of flat caches in our model. * We use a 2-level hierarchy, */ -static cache_t2 I1, D1, L2; +static cache_t2 I1, D1, LL; /* Lower bits of cache tags are used as flags for a cache line */ #define CACHELINE_FLAGMASK (MIN_LINE_SIZE-1) @@ -105,25 +104,15 @@ static Bool clo_simulate_hwpref = False; static Bool clo_simulate_sectors = False; static Bool clo_collect_cacheuse = False; -/* Following global vars are setup before by - * setup_bbcc()/cachesim_after_bbsetup(): +/* Following global vars are setup before by setup_bbcc(): * - * - Addr bb_base (instruction start address of original BB) - * - ULong* cost_base (start of cost array for BB) - * - BBCC* nonskipped (only != 0 when in a function not skipped) + * - Addr CLG_(bb_base) (instruction start address of original BB) + * - ULong* CLG_(cost_base) (start of cost array for BB) */ -/* Offset to events in event set, used in log_* functions - * : offset where basic set is found - */ -static Int off_UIr_Ir; -static Int off_UIrDr_Ir, off_UIrDr_Dr; -static Int off_UIrDrDw_Ir, off_UIrDrDw_Dr, off_UIrDrDw_Dw; -static Int off_UIrDw_Ir, off_UIrDw_Dw; -static Int off_UIrDwDr_Ir, off_UIrDwDr_Dr, off_UIrDwDr_Dw; - -static Addr bb_base; -static ULong* cost_base; +Addr CLG_(bb_base); +ULong* CLG_(cost_base); + static InstrInfo* current_ii; /* Cache use offsets */ @@ -134,8 +123,8 @@ static Int off_I1_AcCost = 0; static Int off_I1_SpLoss = 1; static Int off_D1_AcCost = 0; static Int off_D1_SpLoss = 1; -static Int off_L2_AcCost = 2; -static Int off_L2_SpLoss = 3; +static Int off_LL_AcCost = 2; +static Int off_LL_SpLoss = 3; /* Cache access types */ typedef enum { Read = 0, Write = CACHELINE_DIRTY } RefType; @@ -146,7 +135,7 @@ typedef enum { Hit = 0, Miss, MissDirty } CacheResult; /* Result of a reference into a hierarchical cache model */ typedef enum { L1_Hit, - L2_Hit, + LL_Hit, MemAccess, WriteBackMemAccess } CacheModelResult; @@ -242,7 +231,7 @@ static void print_cache(cache_t2* c) /*------------------------------------------------------------*/ /* - * Simple model: L1 & L2 Write Through + * Simple model: L1 & LL Write Through * Does not distinguish among read and write references * * Simulator functions: @@ -316,7 +305,7 @@ static CacheModelResult cachesim_I1_ref(Addr a, UChar size) { if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit; - if ( cachesim_ref( &L2, a, size) == Hit ) return L2_Hit; + if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit; return MemAccess; } @@ -324,7 +313,7 @@ static CacheModelResult cachesim_D1_ref(Addr a, UChar size) { if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit; - if ( cachesim_ref( &L2, a, size) == Hit ) return L2_Hit; + if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit; return MemAccess; } @@ -334,7 +323,7 @@ CacheModelResult cachesim_D1_ref(Addr a, UChar size) /*------------------------------------------------------------*/ /* - * More complex model: L1 Write-through, L2 Write-back + * More complex model: L1 Write-through, LL Write-back * This needs to distinguish among read and write references. * * Simulator functions: @@ -423,8 +412,8 @@ static CacheModelResult cachesim_I1_Read(Addr a, UChar size) { if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit; - switch( cachesim_ref_wb( &L2, Read, a, size) ) { - case Hit: return L2_Hit; + switch( cachesim_ref_wb( &LL, Read, a, size) ) { + case Hit: return LL_Hit; case Miss: return MemAccess; default: break; } @@ -435,8 +424,8 @@ static CacheModelResult cachesim_D1_Read(Addr a, UChar size) { if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit; - switch( cachesim_ref_wb( &L2, Read, a, size) ) { - case Hit: return L2_Hit; + switch( cachesim_ref_wb( &LL, Read, a, size) ) { + case Hit: return LL_Hit; case Miss: return MemAccess; default: break; } @@ -448,14 +437,14 @@ CacheModelResult cachesim_D1_Write(Addr a, UChar size) { if ( cachesim_ref( &D1, a, size) == Hit ) { /* Even for a L1 hit, the write-trough L1 passes - * the write to the L2 to make the L2 line dirty. + * the write to the LL to make the LL line dirty. * But this causes no latency, so return the hit. */ - cachesim_ref_wb( &L2, Write, a, size); + cachesim_ref_wb( &LL, Write, a, size); return L1_Hit; } - switch( cachesim_ref_wb( &L2, Write, a, size) ) { - case Hit: return L2_Hit; + switch( cachesim_ref_wb( &LL, Write, a, size) ) { + case Hit: return LL_Hit; case Miss: return MemAccess; default: break; } @@ -490,10 +479,10 @@ void prefetch_clear(void) * One stream can be detected per 4k page. */ static __inline__ -void prefetch_L2_doref(Addr a) +void prefetch_LL_doref(Addr a) { UInt stream = (a >> PF_PAGEBITS) % PF_STREAMS; - UInt block = ( a >> L2.line_size_bits); + UInt block = ( a >> LL.line_size_bits); if (block != pf_lastblock[stream]) { if (pf_seqblocks[stream] == 0) { @@ -505,7 +494,7 @@ void prefetch_L2_doref(Addr a) pf_seqblocks[stream]++; if (pf_seqblocks[stream] >= 2) { prefetch_up++; - cachesim_ref(&L2, a + 5 * L2.line_size,1); + cachesim_ref(&LL, a + 5 * LL.line_size,1); } } else pf_seqblocks[stream] = 0; @@ -515,7 +504,7 @@ void prefetch_L2_doref(Addr a) pf_seqblocks[stream]--; if (pf_seqblocks[stream] <= -2) { prefetch_down++; - cachesim_ref(&L2, a - 5 * L2.line_size,1); + cachesim_ref(&LL, a - 5 * LL.line_size,1); } } else pf_seqblocks[stream] = 0; @@ -530,8 +519,8 @@ static CacheModelResult prefetch_I1_ref(Addr a, UChar size) { if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit; - prefetch_L2_doref(a); - if ( cachesim_ref( &L2, a, size) == Hit ) return L2_Hit; + prefetch_LL_doref(a); + if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit; return MemAccess; } @@ -539,8 +528,8 @@ static CacheModelResult prefetch_D1_ref(Addr a, UChar size) { if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit; - prefetch_L2_doref(a); - if ( cachesim_ref( &L2, a, size) == Hit ) return L2_Hit; + prefetch_LL_doref(a); + if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit; return MemAccess; } @@ -551,9 +540,9 @@ static CacheModelResult prefetch_I1_Read(Addr a, UChar size) { if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit; - prefetch_L2_doref(a); - switch( cachesim_ref_wb( &L2, Read, a, size) ) { - case Hit: return L2_Hit; + prefetch_LL_doref(a); + switch( cachesim_ref_wb( &LL, Read, a, size) ) { + case Hit: return LL_Hit; case Miss: return MemAccess; default: break; } @@ -564,9 +553,9 @@ static CacheModelResult prefetch_D1_Read(Addr a, UChar size) { if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit; - prefetch_L2_doref(a); - switch( cachesim_ref_wb( &L2, Read, a, size) ) { - case Hit: return L2_Hit; + prefetch_LL_doref(a); + switch( cachesim_ref_wb( &LL, Read, a, size) ) { + case Hit: return LL_Hit; case Miss: return MemAccess; default: break; } @@ -576,17 +565,17 @@ CacheModelResult prefetch_D1_Read(Addr a, UChar size) static CacheModelResult prefetch_D1_Write(Addr a, UChar size) { - prefetch_L2_doref(a); + prefetch_LL_doref(a); if ( cachesim_ref( &D1, a, size) == Hit ) { /* Even for a L1 hit, the write-trough L1 passes - * the write to the L2 to make the L2 line dirty. + * the write to the LL to make the LL line dirty. * But this causes no latency, so return the hit. */ - cachesim_ref_wb( &L2, Write, a, size); + cachesim_ref_wb( &LL, Write, a, size); return L1_Hit; } - switch( cachesim_ref_wb( &L2, Write, a, size) ) { - case Hit: return L2_Hit; + switch( cachesim_ref_wb( &LL, Write, a, size) ) { + case Hit: return LL_Hit; case Miss: return MemAccess; default: break; } @@ -747,7 +736,7 @@ static CacheModelResult cacheuse##_##L##_doRead(Addr a, UChar size) \ /* Second case: word straddles two lines. */ \ /* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \ } else if (((set1 + 1) & (L.sets-1)) == set2) { \ - Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:L2 miss */ \ + Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:LL miss */ \ set = &(L.tags[set1 * L.assoc]); \ use_mask = L.line_start_mask[a & L.line_size_mask]; \ if (tag == (set[0] & L.tag_mask)) { \ @@ -820,7 +809,7 @@ block2: \ idx = (set2 * L.assoc) + tmp_tag; \ miss2 = update_##L##_use(&L, idx, \ use_mask, (a+size-1) &~ L.line_size_mask); \ - return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:L2_Hit; \ + return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:LL_Hit; \ \ } else { \ VG_(printf)("addr: %#lx size: %u sets: %d %d", a, size, set1, set2); \ @@ -848,14 +837,14 @@ static __inline__ unsigned int countBits(unsigned int bits) return c; } -static void update_L2_use(int idx, Addr memline) +static void update_LL_use(int idx, Addr memline) { - line_loaded* loaded = &(L2.loaded[idx]); - line_use* use = &(L2.use[idx]); - int i = ((32 - countBits(use->mask)) * L2.line_size)>>5; + line_loaded* loaded = &(LL.loaded[idx]); + line_use* use = &(LL.use[idx]); + int i = ((32 - countBits(use->mask)) * LL.line_size)>>5; - CLG_DEBUG(2, " L2.miss [%d]: at %#lx accessing memline %#lx\n", - idx, bb_base + current_ii->instr_offset, memline); + CLG_DEBUG(2, " LL.miss [%d]: at %#lx accessing memline %#lx\n", + idx, CLG_(bb_base) + current_ii->instr_offset, memline); if (use->count>0) { CLG_DEBUG(2, " old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n", use->count, i, use->mask, loaded->memline, loaded->iaddr); @@ -863,8 +852,8 @@ static void update_L2_use(int idx, Addr memline) CLG_(current_state).collect, loaded->use_base); if (CLG_(current_state).collect && loaded->use_base) { - (loaded->use_base)[off_L2_AcCost] += 1000 / use->count; - (loaded->use_base)[off_L2_SpLoss] += i; + (loaded->use_base)[off_LL_AcCost] += 1000 / use->count; + (loaded->use_base)[off_LL_SpLoss] += i; } } @@ -872,60 +861,60 @@ static void update_L2_use(int idx, Addr memline) use->mask = 0; loaded->memline = memline; - loaded->iaddr = bb_base + current_ii->instr_offset; + loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; loaded->use_base = (CLG_(current_state).nonskipped) ? CLG_(current_state).nonskipped->skipped : - cost_base + current_ii->cost_offset; + CLG_(cost_base) + current_ii->cost_offset; } static -CacheModelResult cacheuse_L2_access(Addr memline, line_loaded* l1_loaded) +CacheModelResult cacheuse_LL_access(Addr memline, line_loaded* l1_loaded) { - UInt setNo = (memline >> L2.line_size_bits) & (L2.sets_min_1); - UWord* set = &(L2.tags[setNo * L2.assoc]); - UWord tag = memline & L2.tag_mask; + UInt setNo = (memline >> LL.line_size_bits) & (LL.sets_min_1); + UWord* set = &(LL.tags[setNo * LL.assoc]); + UWord tag = memline & LL.tag_mask; int i, j, idx; UWord tmp_tag; - CLG_DEBUG(6,"L2.Acc(Memline %#lx): Set %d\n", memline, setNo); + CLG_DEBUG(6,"LL.Acc(Memline %#lx): Set %d\n", memline, setNo); - if (tag == (set[0] & L2.tag_mask)) { - idx = (setNo * L2.assoc) + (set[0] & ~L2.tag_mask); - l1_loaded->dep_use = &(L2.use[idx]); + if (tag == (set[0] & LL.tag_mask)) { + idx = (setNo * LL.assoc) + (set[0] & ~LL.tag_mask); + l1_loaded->dep_use = &(LL.use[idx]); CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): => %08x, count %d\n", - idx, L2.loaded[idx].memline, L2.loaded[idx].iaddr, - L2.use[idx].mask, L2.use[idx].count); - return L2_Hit; + idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr, + LL.use[idx].mask, LL.use[idx].count); + return LL_Hit; } - for (i = 1; i < L2.assoc; i++) { - if (tag == (set[i] & L2.tag_mask)) { + for (i = 1; i < LL.assoc; i++) { + if (tag == (set[i] & LL.tag_mask)) { tmp_tag = set[i]; for (j = i; j > 0; j--) { set[j] = set[j - 1]; } set[0] = tmp_tag; - idx = (setNo * L2.assoc) + (tmp_tag & ~L2.tag_mask); - l1_loaded->dep_use = &(L2.use[idx]); + idx = (setNo * LL.assoc) + (tmp_tag & ~LL.tag_mask); + l1_loaded->dep_use = &(LL.use[idx]); CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n", - i, idx, L2.loaded[idx].memline, L2.loaded[idx].iaddr, - L2.use[idx].mask, L2.use[idx].count); - return L2_Hit; + i, idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr, + LL.use[idx].mask, LL.use[idx].count); + return LL_Hit; } } /* A miss; install this tag as MRU, shuffle rest down. */ - tmp_tag = set[L2.assoc - 1] & ~L2.tag_mask; - for (j = L2.assoc - 1; j > 0; j--) { + tmp_tag = set[LL.assoc - 1] & ~LL.tag_mask; + for (j = LL.assoc - 1; j > 0; j--) { set[j] = set[j - 1]; } set[0] = tag | tmp_tag; - idx = (setNo * L2.assoc) + tmp_tag; - l1_loaded->dep_use = &(L2.use[idx]); + idx = (setNo * LL.assoc) + tmp_tag; + l1_loaded->dep_use = &(LL.use[idx]); - update_L2_use(idx, memline); + update_LL_use(idx, memline); return MemAccess; } @@ -943,18 +932,18 @@ static CacheModelResult update##_##L##_use(cache_t2* cache, int idx, \ int c = ((32 - countBits(use->mask)) * cache->line_size)>>5; \ \ CLG_DEBUG(2, " %s.miss [%d]: at %#lx accessing memline %#lx (mask %08x)\n", \ - cache->name, idx, bb_base + current_ii->instr_offset, memline, mask); \ + cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \ if (use->count>0) { \ CLG_DEBUG(2, " old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",\ use->count, c, use->mask, loaded->memline, loaded->iaddr); \ CLG_DEBUG(2, " collect: %d, use_base %p\n", \ CLG_(current_state).collect, loaded->use_base); \ \ - if (CLG_(current_state).collect && loaded->use_base) { \ + if (CLG_(current_state).collect && loaded->use_base) { \ (loaded->use_base)[off_##L##_AcCost] += 1000 / use->count; \ (loaded->use_base)[off_##L##_SpLoss] += c; \ \ - /* FIXME (?): L1/L2 line sizes must be equal ! */ \ + /* FIXME (?): L1/LL line sizes must be equal ! */ \ loaded->dep_use->mask |= use->mask; \ loaded->dep_use->count += use->count; \ } \ @@ -963,13 +952,13 @@ static CacheModelResult update##_##L##_use(cache_t2* cache, int idx, \ use->count = 1; \ use->mask = mask; \ loaded->memline = memline; \ - loaded->iaddr = bb_base + current_ii->instr_offset; \ - loaded->use_base = (CLG_(current_state).nonskipped) ? \ - CLG_(current_state).nonskipped->skipped : \ - cost_base + current_ii->cost_offset; \ + loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; \ + loaded->use_base = (CLG_(current_state).nonskipped) ? \ + CLG_(current_state).nonskipped->skipped : \ + CLG_(cost_base) + current_ii->cost_offset; \ \ - if (memline == 0) return L2_Hit; \ - return cacheuse_L2_access(memline, loaded); \ + if (memline == 0) return LL_Hit; \ + return cacheuse_LL_access(memline, loaded); \ } UPDATE_USE(I1); @@ -987,9 +976,9 @@ void cacheuse_finish(void) if (!CLG_(current_state).collect) return; - bb_base = 0; + CLG_(bb_base) = 0; current_ii = ⅈ - cost_base = 0; + CLG_(cost_base) = 0; /* update usage counters */ if (I1.use) @@ -1002,10 +991,10 @@ void cacheuse_finish(void) if (D1.loaded[i].use_base) update_D1_use( &D1, i, 0,0); - if (L2.use) - for (i = 0; i < L2.sets * L2.assoc; i++) - if (L2.loaded[i].use_base) - update_L2_use(i, 0); + if (LL.use) + for (i = 0; i < LL.sets * LL.assoc; i++) + if (LL.loaded[i].use_base) + update_LL_use(i, 0); } @@ -1031,7 +1020,7 @@ void inc_costs(CacheModelResult r, ULong* c1, ULong* c2) c2[2]++; // fall through - case L2_Hit: + case LL_Hit: c1[1]++; c2[1]++; // fall through @@ -1047,9 +1036,9 @@ Char* cacheRes(CacheModelResult r) { switch(r) { case L1_Hit: return "L1 Hit "; - case L2_Hit: return "L2 Hit "; - case MemAccess: return "L2 Miss"; - case WriteBackMemAccess: return "L2 Miss (dirty)"; + case LL_Hit: return "LL Hit "; + case MemAccess: return "LL Miss"; + case WriteBackMemAccess: return "LL Miss (dirty)"; default: tl_assert(0); } @@ -1062,21 +1051,21 @@ static void log_1I0D(InstrInfo* ii) CacheModelResult IrRes; current_ii = ii; - IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size); + IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); CLG_DEBUG(6, "log_1I0D: Ir %#lx/%u => %s\n", - bb_base + ii->instr_offset, ii->instr_size, cacheRes(IrRes)); + CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes)); if (CLG_(current_state).collect) { ULong* cost_Ir; if (CLG_(current_state).nonskipped) - cost_Ir = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Ir; + cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); else - cost_Ir = cost_base + ii->cost_offset + off_UIr_Ir; + cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; inc_costs(IrRes, cost_Ir, - CLG_(current_state).cost + CLG_(sets).off_full_Ir ); + CLG_(current_state).cost + fullOffset(EG_IR) ); } } @@ -1087,27 +1076,30 @@ static void log_2I0D(InstrInfo* ii1, InstrInfo* ii2) ULong *global_cost_Ir; current_ii = ii1; - Ir1Res = (*simulator.I1_Read)(bb_base + ii1->instr_offset, ii1->instr_size); + Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); current_ii = ii2; - Ir2Res = (*simulator.I1_Read)(bb_base + ii2->instr_offset, ii2->instr_size); + Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); CLG_DEBUG(6, "log_2I0D: Ir1 %#lx/%u => %s, Ir2 %#lx/%u => %s\n", - bb_base + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), - bb_base + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) ); + CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), + CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) ); if (!CLG_(current_state).collect) return; - global_cost_Ir = CLG_(current_state).cost + CLG_(sets).off_full_Ir; + global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR); if (CLG_(current_state).nonskipped) { - ULong* skipped_cost_Ir = CLG_(current_state).nonskipped->skipped + - CLG_(sets).off_full_Ir; + ULong* skipped_cost_Ir = + CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); + inc_costs(Ir1Res, global_cost_Ir, skipped_cost_Ir); inc_costs(Ir2Res, global_cost_Ir, skipped_cost_Ir); return; } - inc_costs(Ir1Res, global_cost_Ir, cost_base + ii1->cost_offset + off_UIr_Ir); - inc_costs(Ir2Res, global_cost_Ir, cost_base + ii2->cost_offset + off_UIr_Ir); + inc_costs(Ir1Res, global_cost_Ir, + CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]); + inc_costs(Ir2Res, global_cost_Ir, + CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]); } VG_REGPARM(3) @@ -1117,32 +1109,35 @@ static void log_3I0D(InstrInfo* ii1, InstrInfo* ii2, InstrInfo* ii3) ULong *global_cost_Ir; current_ii = ii1; - Ir1Res = (*simulator.I1_Read)(bb_base + ii1->instr_offset, ii1->instr_size); + Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size); current_ii = ii2; - Ir2Res = (*simulator.I1_Read)(bb_base + ii2->instr_offset, ii2->instr_size); + Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size); current_ii = ii3; - Ir3Res = (*simulator.I1_Read)(bb_base + ii3->instr_offset, ii3->instr_size); + Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size); CLG_DEBUG(6, "log_3I0D: Ir1 %#lx/%u => %s, Ir2 %#lx/%u => %s, Ir3 %#lx/%u => %s\n", - bb_base + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), - bb_base + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res), - bb_base + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) ); + CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res), + CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res), + CLG_(bb_base) + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) ); if (!CLG_(current_state).collect) return; - global_cost_Ir = CLG_(current_state).cost + CLG_(sets).off_full_Ir; + global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR); if (CLG_(current_state).nonskipped) { - ULong* skipped_cost_Ir = CLG_(current_state).nonskipped->skipped + - CLG_(sets).off_full_Ir; + ULong* skipped_cost_Ir = + CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); inc_costs(Ir1Res, global_cost_Ir, skipped_cost_Ir); inc_costs(Ir2Res, global_cost_Ir, skipped_cost_Ir); inc_costs(Ir3Res, global_cost_Ir, skipped_cost_Ir); return; } - inc_costs(Ir1Res, global_cost_Ir, cost_base + ii1->cost_offset + off_UIr_Ir); - inc_costs(Ir2Res, global_cost_Ir, cost_base + ii2->cost_offset + off_UIr_Ir); - inc_costs(Ir3Res, global_cost_Ir, cost_base + ii3->cost_offset + off_UIr_Ir); + inc_costs(Ir1Res, global_cost_Ir, + CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]); + inc_costs(Ir2Res, global_cost_Ir, + CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]); + inc_costs(Ir3Res, global_cost_Ir, + CLG_(cost_base) + ii3->cost_offset + ii3->eventset->offset[EG_IR]); } /* Instruction doing a read access */ @@ -1153,32 +1148,29 @@ static void log_1I1Dr(InstrInfo* ii, Addr data_addr, Word data_size) CacheModelResult IrRes, DrRes; current_ii = ii; - IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size); + IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); DrRes = (*simulator.D1_Read)(data_addr, data_size); CLG_DEBUG(6, "log_1I1Dr: Ir %#lx/%u => %s, Dr %#lx/%lu => %s\n", - bb_base + ii->instr_offset, ii->instr_size, cacheRes(IrRes), + CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes), data_addr, data_size, cacheRes(DrRes)); if (CLG_(current_state).collect) { ULong *cost_Ir, *cost_Dr; if (CLG_(current_state).nonskipped) { - cost_Ir = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Ir; - cost_Dr = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Dr; + cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); + cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR); } else { - // event set must be UIrDr or extension - CLG_ASSERT((ii->eventset == CLG_(sets).UIrDr) || - (ii->eventset == CLG_(sets).UIrDrDw)); - cost_Ir = cost_base + ii->cost_offset + off_UIrDr_Ir; - cost_Dr = cost_base + ii->cost_offset + off_UIrDr_Dr; + cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; + cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR]; } inc_costs(IrRes, cost_Ir, - CLG_(current_state).cost + CLG_(sets).off_full_Ir ); + CLG_(current_state).cost + fullOffset(EG_IR) ); inc_costs(DrRes, cost_Dr, - CLG_(current_state).cost + CLG_(sets).off_full_Dr ); + CLG_(current_state).cost + fullOffset(EG_DR) ); } } @@ -1197,21 +1189,13 @@ static void log_0I1Dr(InstrInfo* ii, Addr data_addr, Word data_size) if (CLG_(current_state).collect) { ULong *cost_Dr; - if (CLG_(current_state).nonskipped) { - cost_Dr = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Dr; - } - else { - Int off_Dr; - if (ii->eventset == CLG_(sets).UIrDr) off_Dr = off_UIrDr_Dr; - else if (ii->eventset == CLG_(sets).UIrDrDw) off_Dr = off_UIrDrDw_Dr; - else if (ii->eventset == CLG_(sets).UIrDwDr) off_Dr = off_UIrDwDr_Dr; - else CLG_ASSERT(0); - - cost_Dr = cost_base + ii->cost_offset + off_Dr; - } + if (CLG_(current_state).nonskipped) + cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR); + else + cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR]; inc_costs(DrRes, cost_Dr, - CLG_(current_state).cost + CLG_(sets).off_full_Dr ); + CLG_(current_state).cost + fullOffset(EG_DR) ); } } @@ -1224,33 +1208,29 @@ static void log_1I1Dw(InstrInfo* ii, Addr data_addr, Word data_size) CacheModelResult IrRes, DwRes; current_ii = ii; - IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size); + IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size); DwRes = (*simulator.D1_Write)(data_addr, data_size); CLG_DEBUG(6, "log_1I1Dw: Ir %#lx/%u => %s, Dw %#lx/%lu => %s\n", - bb_base + ii->instr_offset, ii->instr_size, cacheRes(IrRes), + CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes), data_addr, data_size, cacheRes(DwRes)); if (CLG_(current_state).collect) { ULong *cost_Ir, *cost_Dw; if (CLG_(current_state).nonskipped) { - cost_Ir = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Ir; - cost_Dw = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Dw; + cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR); + cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW); } else { - // This helper is called when a Dr event follows Ir; - // Event set must be UIrDw or extension - CLG_ASSERT((ii->eventset == CLG_(sets).UIrDw) || - (ii->eventset == CLG_(sets).UIrDwDr)); - cost_Ir = cost_base + ii->cost_offset + off_UIrDw_Ir; - cost_Dw = cost_base + ii->cost_offset + off_UIrDw_Dw; + cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR]; + cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW]; } inc_costs(IrRes, cost_Ir, - CLG_(current_state).cost + CLG_(sets).off_full_Ir ); + CLG_(current_state).cost + fullOffset(EG_IR) ); inc_costs(DwRes, cost_Dw, - CLG_(current_state).cost + CLG_(sets).off_full_Dw ); + CLG_(current_state).cost + fullOffset(EG_DW) ); } } @@ -1268,21 +1248,13 @@ static void log_0I1Dw(InstrInfo* ii, Addr data_addr, Word data_size) if (CLG_(current_state).collect) { ULong *cost_Dw; - if (CLG_(current_state).nonskipped) { - cost_Dw = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Dw; - } - else { - Int off_Dw; - if (ii->eventset == CLG_(sets).UIrDw) off_Dw = off_UIrDw_Dw; - else if (ii->eventset == CLG_(sets).UIrDwDr) off_Dw = off_UIrDwDr_Dw; - else if (ii->eventset == CLG_(sets).UIrDrDw) off_Dw = off_UIrDrDw_Dw; - else CLG_ASSERT(0); - - cost_Dw = cost_base + ii->cost_offset + off_Dw; - } + if (CLG_(current_state).nonskipped) + cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW); + else + cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW]; inc_costs(DwRes, cost_Dw, - CLG_(current_state).cost + CLG_(sets).off_full_Dw ); + CLG_(current_state).cost + fullOffset(EG_DW) ); } } @@ -1296,88 +1268,79 @@ static void log_0I1Dw(InstrInfo* ii, Addr data_addr, Word data_size) static cache_t clo_I1_cache = UNDEFINED_CACHE; static cache_t clo_D1_cache = UNDEFINED_CACHE; -static cache_t clo_L2_cache = UNDEFINED_CACHE; +static cache_t clo_LL_cache = UNDEFINED_CACHE; -/* Checks cache config is ok; makes it so if not. */ -static -void check_cache(cache_t* cache, Char *name) +// Checks cache config is ok. Returns NULL if ok, or a pointer to an error +// string otherwise. +static Char* check_cache(cache_t* cache) { - /* Simulator requires line size and set count to be powers of two */ + // Simulator requires line size and set count to be powers of two. if (( cache->size % (cache->line_size * cache->assoc) != 0) || - (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) { - VG_(message)(Vg_UserMsg, - "error: %s set count not a power of two; aborting.\n", - name); + (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) + { + return "Cache set count is not a power of two.\n"; } + // Simulator requires line size to be a power of two. if (-1 == VG_(log2)(cache->line_size)) { - VG_(message)(Vg_UserMsg, - "error: %s line size of %dB not a power of two; aborting.\n", - name, cache->line_size); - VG_(exit)(1); + return "Cache line size is not a power of two.\n"; } // Then check line size >= 16 -- any smaller and a single instruction could // straddle three cache lines, which breaks a simulation assertion and is // stupid anyway. if (cache->line_size < MIN_LINE_SIZE) { - VG_(message)(Vg_UserMsg, - "error: %s line size of %dB too small; aborting.\n", - name, cache->line_size); - VG_(exit)(1); + return "Cache line size is too small.\n"; } /* Then check cache size > line size (causes seg faults if not). */ if (cache->size <= cache->line_size) { - VG_(message)(Vg_UserMsg, - "error: %s cache size of %dB <= line size of %dB; aborting.\n", - name, cache->size, cache->line_size); - VG_(exit)(1); + return "Cache size <= line size.\n"; } /* Then check assoc <= (size / line size) (seg faults otherwise). */ if (cache->assoc > (cache->size / cache->line_size)) { - VG_(message)(Vg_UserMsg, - "warning: %s associativity > (size / line size); aborting.\n", name); - VG_(exit)(1); + return "Cache associativity > (size / line size).\n"; } + + return NULL; } static -void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c) +void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* LLc) { #define DEFINED(L) (-1 != L.size || -1 != L.assoc || -1 != L.line_size) - Int n_clos = 0; + Char* checkRes; - // Count how many were defined on the command line. - if (DEFINED(clo_I1_cache)) { n_clos++; } - if (DEFINED(clo_D1_cache)) { n_clos++; } - if (DEFINED(clo_L2_cache)) { n_clos++; } + Bool all_caches_clo_defined = + (DEFINED(clo_I1_cache) && + DEFINED(clo_D1_cache) && + DEFINED(clo_LL_cache)); // Set the cache config (using auto-detection, if supported by the - // architecture) - VG_(configure_caches)( I1c, D1c, L2c, (3 == n_clos) ); + // architecture). + VG_(configure_caches)( I1c, D1c, LLc, all_caches_clo_defined ); + + // Check the default/auto-detected values. + checkRes = check_cache(I1c); tl_assert(!checkRes); + checkRes = check_cache(D1c); tl_assert(!checkRes); + checkRes = check_cache(LLc); tl_assert(!checkRes); // Then replace with any defined on the command line. if (DEFINED(clo_I1_cache)) { *I1c = clo_I1_cache; } if (DEFINED(clo_D1_cache)) { *D1c = clo_D1_cache; } - if (DEFINED(clo_L2_cache)) { *L2c = clo_L2_cache; } - - // Then check values and fix if not acceptable. - check_cache(I1c, "I1"); - check_cache(D1c, "D1"); - check_cache(L2c, "L2"); + if (DEFINED(clo_LL_cache)) { *LLc = clo_LL_cache; } if (VG_(clo_verbosity) > 1) { - VG_(message)(Vg_UserMsg, "Cache configuration used:\n"); - VG_(message)(Vg_UserMsg, " I1: %dB, %d-way, %dB lines\n", - I1c->size, I1c->assoc, I1c->line_size); - VG_(message)(Vg_UserMsg, " D1: %dB, %d-way, %dB lines\n", - D1c->size, D1c->assoc, D1c->line_size); - VG_(message)(Vg_UserMsg, " L2: %dB, %d-way, %dB lines\n", - L2c->size, L2c->assoc, L2c->line_size); + VG_(umsg)("Cache configuration used:\n"); + VG_(umsg)(" I1: %dB, %d-way, %dB lines\n", + I1c->size, I1c->assoc, I1c->line_size); + VG_(umsg)(" D1: %dB, %d-way, %dB lines\n", + D1c->size, D1c->assoc, D1c->line_size); + VG_(umsg)(" LL: %dB, %d-way, %dB lines\n", + LLc->size, LLc->assoc, LLc->line_size); } #undef CMD_LINE_DEFINED } @@ -1387,7 +1350,7 @@ void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c) static void cachesim_post_clo_init(void) { /* Cache configurations. */ - cache_t I1c, D1c, L2c; + cache_t I1c, D1c, LLc; /* Initialize access handlers */ if (!CLG_(clo).simulate_cache) { @@ -1411,15 +1374,15 @@ static void cachesim_post_clo_init(void) } /* Configuration of caches only needed with real cache simulation */ - configure_caches(&I1c, &D1c, &L2c); + configure_caches(&I1c, &D1c, &LLc); I1.name = "I1"; D1.name = "D1"; - L2.name = "L2"; + LL.name = "LL"; cachesim_initcache(I1c, &I1); cachesim_initcache(D1c, &D1); - cachesim_initcache(L2c, &L2); + cachesim_initcache(LLc, &LL); /* the other cache simulators use the standard helpers * with dispatching via simulator struct */ @@ -1500,7 +1463,7 @@ void cachesim_clear(void) { cachesim_clearcache(&I1); cachesim_clearcache(&D1); - cachesim_clearcache(&L2); + cachesim_clearcache(&LL); prefetch_clear(); } @@ -1511,15 +1474,14 @@ static void cachesim_getdesc(Char* buf) Int p; p = VG_(sprintf)(buf, "\ndesc: I1 cache: %s\n", I1.desc_line); p += VG_(sprintf)(buf+p, "desc: D1 cache: %s\n", D1.desc_line); - VG_(sprintf)(buf+p, "desc: L2 cache: %s\n", L2.desc_line); + VG_(sprintf)(buf+p, "desc: LL cache: %s\n", LL.desc_line); } static void cachesim_print_opts(void) { VG_(printf)( -"\n cache simulator options:\n" -" --simulate-cache=no|yes Do cache simulation [no]\n" +"\n cache simulator options (does cache simulation if used):\n" " --simulate-wb=no|yes Count write-back events [no]\n" " --simulate-hwpref=no|yes Simulate hardware prefetch [no]\n" #if CLG_EXPERIMENTAL @@ -1528,17 +1490,19 @@ void cachesim_print_opts(void) " --cacheuse=no|yes Collect cache block use [no]\n" " --I1=,, set I1 cache manually\n" " --D1=,, set D1 cache manually\n" -" --L2=,, set L2 cache manually\n" +" --LL=,, set LL cache manually\n" ); } -static void parse_opt ( cache_t* cache, char* opt ) +static void parse_opt ( cache_t* cache, + char* opt, Char* optval, UChar kind ) { Long i1, i2, i3; Char* endptr; + Char* checkRes; // Option argument looks like "65536,2,64". Extract them. - i1 = VG_(strtoll10)(opt, &endptr); if (*endptr != ',') goto bad; + i1 = VG_(strtoll10)(optval, &endptr); if (*endptr != ',') goto bad; i2 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != ',') goto bad; i3 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != '\0') goto bad; @@ -1550,15 +1514,20 @@ static void parse_opt ( cache_t* cache, char* opt ) if (cache->assoc != i2) goto overflow; if (cache->line_size != i3) goto overflow; + checkRes = check_cache(cache); + if (checkRes) { + VG_(fmsg)("%s", checkRes); + goto bad; + } + return; - overflow: - VG_(message)(Vg_UserMsg, - "one of the cache parameters was too large and overflowed\n"); bad: - // XXX: this omits the "--I1/D1/L2=" part from the message, but that's - // not a big deal. - VG_(err_bad_option)(opt); + VG_(fmsg_bad_option)(opt, ""); + + overflow: + VG_(fmsg_bad_option)(opt, + "One of the cache parameters was too large and overflowed.\n"); } /* Check for command line option for cache configuration. @@ -1582,11 +1551,12 @@ static Bool cachesim_parse_opt(Char* arg) } else if VG_STR_CLO(arg, "--I1", tmp_str) - parse_opt(&clo_I1_cache, tmp_str); + parse_opt(&clo_I1_cache, arg, tmp_str, 'i'); else if VG_STR_CLO(arg, "--D1", tmp_str) - parse_opt(&clo_D1_cache, tmp_str); - else if VG_STR_CLO(arg, "--L2", tmp_str) - parse_opt(&clo_L2_cache, tmp_str); + parse_opt(&clo_D1_cache, arg, tmp_str, '1'); + else if (VG_STR_CLO(arg, "--L2", tmp_str) || // for backwards compatibility + VG_STR_CLO(arg, "--LL", tmp_str)) + parse_opt(&clo_LL_cache, arg, tmp_str, '2'); else return False; @@ -1642,15 +1612,14 @@ void percentify(Int n, Int ex, Int field_width, char buf[]) } static -void cachesim_printstat(void) +void cachesim_printstat(Int l1, Int l2, Int l3) { FullCost total = CLG_(total_cost), D_total = 0; - ULong L2_total_m, L2_total_mr, L2_total_mw, - L2_total, L2_total_r, L2_total_w; + ULong LL_total_m, LL_total_mr, LL_total_mw, + LL_total, LL_total_r, LL_total_w; char buf1[RESULTS_BUF_LEN], buf2[RESULTS_BUF_LEN], buf3[RESULTS_BUF_LEN]; - Int l1, l2, l3; Int p; if ((VG_(clo_verbosity) >1) && clo_simulate_hwpref) { @@ -1661,31 +1630,24 @@ void cachesim_printstat(void) VG_(message)(Vg_DebugMsg, "\n"); } - /* I cache results. Use the I_refs value to determine the first column - * width. */ - l1 = commify(total[CLG_(sets).off_full_Ir], 0, buf1); - VG_(message)(Vg_UserMsg, "I refs: %s\n", buf1); - - if (!CLG_(clo).simulate_cache) return; - - commify(total[CLG_(sets).off_full_Ir +1], l1, buf1); + commify(total[fullOffset(EG_IR) +1], l1, buf1); VG_(message)(Vg_UserMsg, "I1 misses: %s\n", buf1); - commify(total[CLG_(sets).off_full_Ir +2], l1, buf1); - VG_(message)(Vg_UserMsg, "L2i misses: %s\n", buf1); + commify(total[fullOffset(EG_IR) +2], l1, buf1); + VG_(message)(Vg_UserMsg, "LLi misses: %s\n", buf1); p = 100; - if (0 == total[CLG_(sets).off_full_Ir]) - total[CLG_(sets).off_full_Ir] = 1; + if (0 == total[fullOffset(EG_IR)]) + total[fullOffset(EG_IR)] = 1; - percentify(total[CLG_(sets).off_full_Ir+1] * 100 * p / - total[CLG_(sets).off_full_Ir], p, l1+1, buf1); + percentify(total[fullOffset(EG_IR)+1] * 100 * p / + total[fullOffset(EG_IR)], p, l1+1, buf1); VG_(message)(Vg_UserMsg, "I1 miss rate: %s\n", buf1); - percentify(total[CLG_(sets).off_full_Ir+2] * 100 * p / - total[CLG_(sets).off_full_Ir], p, l1+1, buf1); - VG_(message)(Vg_UserMsg, "L2i miss rate: %s\n", buf1); + percentify(total[fullOffset(EG_IR)+2] * 100 * p / + total[fullOffset(EG_IR)], p, l1+1, buf1); + VG_(message)(Vg_UserMsg, "LLi miss rate: %s\n", buf1); VG_(message)(Vg_UserMsg, "\n"); /* D cache results. @@ -1694,90 +1656,91 @@ void cachesim_printstat(void) D_total = CLG_(get_eventset_cost)( CLG_(sets).full ); CLG_(init_cost)( CLG_(sets).full, D_total); - CLG_(copy_cost)( CLG_(sets).Dr, D_total, total + CLG_(sets).off_full_Dr ); - CLG_(add_cost) ( CLG_(sets).Dw, D_total, total + CLG_(sets).off_full_Dw ); + // we only use the first 3 values of D_total, adding up Dr and Dw costs + CLG_(copy_cost)( CLG_(get_event_set)(EG_DR), D_total, total + fullOffset(EG_DR) ); + CLG_(add_cost) ( CLG_(get_event_set)(EG_DW), D_total, total + fullOffset(EG_DW) ); commify( D_total[0], l1, buf1); - l2 = commify(total[CLG_(sets).off_full_Dr], 0, buf2); - l3 = commify(total[CLG_(sets).off_full_Dw], 0, buf3); + commify(total[fullOffset(EG_DR)], l2, buf2); + commify(total[fullOffset(EG_DW)], l3, buf3); VG_(message)(Vg_UserMsg, "D refs: %s (%s rd + %s wr)\n", buf1, buf2, buf3); commify( D_total[1], l1, buf1); - commify(total[CLG_(sets).off_full_Dr+1], l2, buf2); - commify(total[CLG_(sets).off_full_Dw+1], l3, buf3); + commify(total[fullOffset(EG_DR)+1], l2, buf2); + commify(total[fullOffset(EG_DW)+1], l3, buf3); VG_(message)(Vg_UserMsg, "D1 misses: %s (%s rd + %s wr)\n", buf1, buf2, buf3); commify( D_total[2], l1, buf1); - commify(total[CLG_(sets).off_full_Dr+2], l2, buf2); - commify(total[CLG_(sets).off_full_Dw+2], l3, buf3); - VG_(message)(Vg_UserMsg, "L2d misses: %s (%s rd + %s wr)\n", + commify(total[fullOffset(EG_DR)+2], l2, buf2); + commify(total[fullOffset(EG_DW)+2], l3, buf3); + VG_(message)(Vg_UserMsg, "LLd misses: %s (%s rd + %s wr)\n", buf1, buf2, buf3); p = 10; if (0 == D_total[0]) D_total[0] = 1; - if (0 == total[CLG_(sets).off_full_Dr]) total[CLG_(sets).off_full_Dr] = 1; - if (0 == total[CLG_(sets).off_full_Dw]) total[CLG_(sets).off_full_Dw] = 1; + if (0 == total[fullOffset(EG_DR)]) total[fullOffset(EG_DR)] = 1; + if (0 == total[fullOffset(EG_DW)]) total[fullOffset(EG_DW)] = 1; percentify( D_total[1] * 100 * p / D_total[0], p, l1+1, buf1); - percentify(total[CLG_(sets).off_full_Dr+1] * 100 * p / - total[CLG_(sets).off_full_Dr], p, l2+1, buf2); - percentify(total[CLG_(sets).off_full_Dw+1] * 100 * p / - total[CLG_(sets).off_full_Dw], p, l3+1, buf3); + percentify(total[fullOffset(EG_DR)+1] * 100 * p / + total[fullOffset(EG_DR)], p, l2+1, buf2); + percentify(total[fullOffset(EG_DW)+1] * 100 * p / + total[fullOffset(EG_DW)], p, l3+1, buf3); VG_(message)(Vg_UserMsg, "D1 miss rate: %s (%s + %s )\n", buf1, buf2,buf3); percentify( D_total[2] * 100 * p / D_total[0], p, l1+1, buf1); - percentify(total[CLG_(sets).off_full_Dr+2] * 100 * p / - total[CLG_(sets).off_full_Dr], p, l2+1, buf2); - percentify(total[CLG_(sets).off_full_Dw+2] * 100 * p / - total[CLG_(sets).off_full_Dw], p, l3+1, buf3); - VG_(message)(Vg_UserMsg, "L2d miss rate: %s (%s + %s )\n", + percentify(total[fullOffset(EG_DR)+2] * 100 * p / + total[fullOffset(EG_DR)], p, l2+1, buf2); + percentify(total[fullOffset(EG_DW)+2] * 100 * p / + total[fullOffset(EG_DW)], p, l3+1, buf3); + VG_(message)(Vg_UserMsg, "LLd miss rate: %s (%s + %s )\n", buf1, buf2,buf3); VG_(message)(Vg_UserMsg, "\n"); - /* L2 overall results */ + /* LL overall results */ - L2_total = - total[CLG_(sets).off_full_Dr +1] + - total[CLG_(sets).off_full_Dw +1] + - total[CLG_(sets).off_full_Ir +1]; - L2_total_r = - total[CLG_(sets).off_full_Dr +1] + - total[CLG_(sets).off_full_Ir +1]; - L2_total_w = total[CLG_(sets).off_full_Dw +1]; - commify(L2_total, l1, buf1); - commify(L2_total_r, l2, buf2); - commify(L2_total_w, l3, buf3); - VG_(message)(Vg_UserMsg, "L2 refs: %s (%s rd + %s wr)\n", + LL_total = + total[fullOffset(EG_DR) +1] + + total[fullOffset(EG_DW) +1] + + total[fullOffset(EG_IR) +1]; + LL_total_r = + total[fullOffset(EG_DR) +1] + + total[fullOffset(EG_IR) +1]; + LL_total_w = total[fullOffset(EG_DW) +1]; + commify(LL_total, l1, buf1); + commify(LL_total_r, l2, buf2); + commify(LL_total_w, l3, buf3); + VG_(message)(Vg_UserMsg, "LL refs: %s (%s rd + %s wr)\n", buf1, buf2, buf3); - L2_total_m = - total[CLG_(sets).off_full_Dr +2] + - total[CLG_(sets).off_full_Dw +2] + - total[CLG_(sets).off_full_Ir +2]; - L2_total_mr = - total[CLG_(sets).off_full_Dr +2] + - total[CLG_(sets).off_full_Ir +2]; - L2_total_mw = total[CLG_(sets).off_full_Dw +2]; - commify(L2_total_m, l1, buf1); - commify(L2_total_mr, l2, buf2); - commify(L2_total_mw, l3, buf3); - VG_(message)(Vg_UserMsg, "L2 misses: %s (%s rd + %s wr)\n", + LL_total_m = + total[fullOffset(EG_DR) +2] + + total[fullOffset(EG_DW) +2] + + total[fullOffset(EG_IR) +2]; + LL_total_mr = + total[fullOffset(EG_DR) +2] + + total[fullOffset(EG_IR) +2]; + LL_total_mw = total[fullOffset(EG_DW) +2]; + commify(LL_total_m, l1, buf1); + commify(LL_total_mr, l2, buf2); + commify(LL_total_mw, l3, buf3); + VG_(message)(Vg_UserMsg, "LL misses: %s (%s rd + %s wr)\n", buf1, buf2, buf3); - percentify(L2_total_m * 100 * p / - (total[CLG_(sets).off_full_Ir] + D_total[0]), p, l1+1, buf1); - percentify(L2_total_mr * 100 * p / - (total[CLG_(sets).off_full_Ir] + total[CLG_(sets).off_full_Dr]), + percentify(LL_total_m * 100 * p / + (total[fullOffset(EG_IR)] + D_total[0]), p, l1+1, buf1); + percentify(LL_total_mr * 100 * p / + (total[fullOffset(EG_IR)] + total[fullOffset(EG_DR)]), p, l2+1, buf2); - percentify(L2_total_mw * 100 * p / - total[CLG_(sets).off_full_Dw], p, l3+1, buf3); - VG_(message)(Vg_UserMsg, "L2 miss rate: %s (%s + %s )\n", + percentify(LL_total_mw * 100 * p / + total[fullOffset(EG_DW)], p, l3+1, buf3); + VG_(message)(Vg_UserMsg, "LL miss rate: %s (%s + %s )\n", buf1, buf2,buf3); } @@ -1788,251 +1751,96 @@ void cachesim_printstat(void) struct event_sets CLG_(sets); -void CLG_(init_eventsets)(Int max_user) +void CLG_(init_eventsets)() { - EventType * e1, *e2, *e3, *e4; - // Basic event sets from which others are composed - EventSet *Use, *Ir, *Dr, *Dw; - // Compositions of basic sets used for per-instruction counters - EventSet *UIr, *UIrDr, *UIrDrDw, *UIrDw, *UIrDwDr; - // Composition used for global counters and aggregation - EventSet *full; - int sizeOfUseIr; - - // the "Use" events types only are used with "cacheuse" simulation - Use = CLG_(get_eventset)("Use", 4); - if (clo_collect_cacheuse) { - /* if TUse is 0, there was never a load, and no loss, too */ - e1 = CLG_(register_eventtype)("AcCost1"); - CLG_(add_eventtype)(Use, e1); - e1 = CLG_(register_eventtype)("SpLoss1"); - CLG_(add_eventtype)(Use, e1); - e1 = CLG_(register_eventtype)("AcCost2"); - CLG_(add_eventtype)(Use, e1); - e1 = CLG_(register_eventtype)("SpLoss2"); - CLG_(add_eventtype)(Use, e1); - } - - Ir = CLG_(get_eventset)("Ir", 4); - Dr = CLG_(get_eventset)("Dr", 4); - Dw = CLG_(get_eventset)("Dw", 4); - if (CLG_(clo).simulate_cache) { - e1 = CLG_(register_eventtype)("Ir"); - e2 = CLG_(register_eventtype)("I1mr"); - e3 = CLG_(register_eventtype)("I2mr"); - if (clo_simulate_writeback) { - e4 = CLG_(register_eventtype)("I2dmr"); - CLG_(add_dep_event4)(Ir, e1,e2,e3,e4); - } - else - CLG_(add_dep_event3)(Ir, e1,e2,e3); - - e1 = CLG_(register_eventtype)("Dr"); - e2 = CLG_(register_eventtype)("D1mr"); - e3 = CLG_(register_eventtype)("D2mr"); - if (clo_simulate_writeback) { - e4 = CLG_(register_eventtype)("D2dmr"); - CLG_(add_dep_event4)(Dr, e1,e2,e3,e4); + // Event groups from which the event sets are composed + // the "Use" group only is used with "cacheuse" simulation + if (clo_collect_cacheuse) + CLG_(register_event_group4)(EG_USE, + "AcCost1", "SpLoss1", "AcCost2", "SpLoss2"); + + if (!CLG_(clo).simulate_cache) + CLG_(register_event_group)(EG_IR, "Ir"); + else if (!clo_simulate_writeback) { + CLG_(register_event_group3)(EG_IR, "Ir", "I1mr", "ILmr"); + CLG_(register_event_group3)(EG_DR, "Dr", "D1mr", "DLmr"); + CLG_(register_event_group3)(EG_DW, "Dw", "D1mw", "DLmw"); } - else - CLG_(add_dep_event3)(Dr, e1,e2,e3); - - e1 = CLG_(register_eventtype)("Dw"); - e2 = CLG_(register_eventtype)("D1mw"); - e3 = CLG_(register_eventtype)("D2mw"); - if (clo_simulate_writeback) { - e4 = CLG_(register_eventtype)("D2dmw"); - CLG_(add_dep_event4)(Dw, e1,e2,e3,e4); + else { // clo_simulate_writeback + CLG_(register_event_group4)(EG_IR, "Ir", "I1mr", "ILmr", "ILdmr"); + CLG_(register_event_group4)(EG_DR, "Dr", "D1mr", "DLmr", "DLdmr"); + CLG_(register_event_group4)(EG_DW, "Dw", "D1mw", "DLmw", "DLdmw"); } - else - CLG_(add_dep_event3)(Dw, e1,e2,e3); - } - else { - e1 = CLG_(register_eventtype)("Ir"); - CLG_(add_eventtype)(Ir, e1); - } - - // Self cost event sets per guest instruction (U used only for cacheUse). - // Each basic event set only appears once, as eg. multiple different Dr's - // in one guest instruction are counted in the same counter. - - sizeOfUseIr = Use->size + Ir->size; - UIr = CLG_(get_eventset)("UIr", sizeOfUseIr); - CLG_(add_eventset)(UIr, Use); - off_UIr_Ir = CLG_(add_eventset)(UIr, Ir); - - UIrDr = CLG_(get_eventset)("UIrDr", sizeOfUseIr + Dr->size); - CLG_(add_eventset)(UIrDr, Use); - off_UIrDr_Ir = CLG_(add_eventset)(UIrDr, Ir); - off_UIrDr_Dr = CLG_(add_eventset)(UIrDr, Dr); - - UIrDrDw = CLG_(get_eventset)("IrDrDw", sizeOfUseIr + Dr->size + Dw->size); - CLG_(add_eventset)(UIrDrDw, Use); - off_UIrDrDw_Ir = CLG_(add_eventset)(UIrDrDw, Ir); - off_UIrDrDw_Dr = CLG_(add_eventset)(UIrDrDw, Dr); - off_UIrDrDw_Dw = CLG_(add_eventset)(UIrDrDw, Dw); - - UIrDw = CLG_(get_eventset)("UIrDw", sizeOfUseIr + Dw->size); - CLG_(add_eventset)(UIrDw, Use); - off_UIrDw_Ir = CLG_(add_eventset)(UIrDw, Ir); - off_UIrDw_Dw = CLG_(add_eventset)(UIrDw, Dw); - - UIrDwDr = CLG_(get_eventset)("IrDwDr", sizeOfUseIr + Dw->size + Dr->size); - CLG_(add_eventset)(UIrDwDr, Use); - off_UIrDwDr_Ir = CLG_(add_eventset)(UIrDrDw, Ir); - off_UIrDwDr_Dw = CLG_(add_eventset)(UIrDrDw, Dw); - off_UIrDwDr_Dr = CLG_(add_eventset)(UIrDrDw, Dr); - - - // the "full" event set is used as global counter and for aggregation - if (CLG_(clo).collect_alloc) max_user += 2; - if (CLG_(clo).collect_systime) max_user += 2; - full = CLG_(get_eventset)("full", - sizeOfUseIr + Dr->size + Dw->size + max_user); - CLG_(add_eventset)(full, Use); - CLG_(sets).off_full_Ir = CLG_(add_eventset)(full, Ir); - CLG_(sets).off_full_Dr = CLG_(add_eventset)(full, Dr); - CLG_(sets).off_full_Dw = CLG_(add_eventset)(full, Dw); - if (CLG_(clo).collect_alloc) { - e1 = CLG_(register_eventtype)("allocCount"); - e2 = CLG_(register_eventtype)("allocSize"); - CLG_(sets).off_full_alloc = CLG_(add_dep_event2)(full, e1,e2); - } - if (CLG_(clo).collect_systime) { - e1 = CLG_(register_eventtype)("sysCount"); - e2 = CLG_(register_eventtype)("sysTime"); - CLG_(sets).off_full_systime = CLG_(add_dep_event2)(full, e1,e2); - } + if (CLG_(clo).simulate_branch) { + CLG_(register_event_group2)(EG_BC, "Bc", "Bcm"); + CLG_(register_event_group2)(EG_BI, "Bi", "Bim"); + } - CLG_(sets).Use = Use; - CLG_(sets).Ir = Ir; - CLG_(sets).Dr = Dr; - CLG_(sets).Dw = Dw; - CLG_(sets).UIr = UIr; - CLG_(sets).UIrDr = UIrDr; - CLG_(sets).UIrDrDw = UIrDrDw; - CLG_(sets).UIrDw = UIrDw; - CLG_(sets).UIrDwDr = UIrDwDr; - CLG_(sets).full = full; - - - CLG_DEBUGIF(1) { - CLG_DEBUG(1, "EventSets:\n"); - CLG_(print_eventset)(-2, Use); - CLG_(print_eventset)(-2, Ir); - CLG_(print_eventset)(-2, Dr); - CLG_(print_eventset)(-2, Dw); - CLG_(print_eventset)(-2, full); - } + if (CLG_(clo).collect_bus) + CLG_(register_event_group)(EG_BUS, "Ge"); - /* Not-existing events are silently ignored */ - CLG_(dumpmap) = CLG_(get_eventmapping)(full); - CLG_(append_event)(CLG_(dumpmap), "Ir"); - CLG_(append_event)(CLG_(dumpmap), "Dr"); - CLG_(append_event)(CLG_(dumpmap), "Dw"); - CLG_(append_event)(CLG_(dumpmap), "I1mr"); - CLG_(append_event)(CLG_(dumpmap), "D1mr"); - CLG_(append_event)(CLG_(dumpmap), "D1mw"); - CLG_(append_event)(CLG_(dumpmap), "I2mr"); - CLG_(append_event)(CLG_(dumpmap), "D2mr"); - CLG_(append_event)(CLG_(dumpmap), "D2mw"); - CLG_(append_event)(CLG_(dumpmap), "I2dmr"); - CLG_(append_event)(CLG_(dumpmap), "D2dmr"); - CLG_(append_event)(CLG_(dumpmap), "D2dmw"); - CLG_(append_event)(CLG_(dumpmap), "AcCost1"); - CLG_(append_event)(CLG_(dumpmap), "SpLoss1"); - CLG_(append_event)(CLG_(dumpmap), "AcCost2"); - CLG_(append_event)(CLG_(dumpmap), "SpLoss2"); - CLG_(append_event)(CLG_(dumpmap), "allocCount"); - CLG_(append_event)(CLG_(dumpmap), "allocSize"); - CLG_(append_event)(CLG_(dumpmap), "sysCount"); - CLG_(append_event)(CLG_(dumpmap), "sysTime"); + if (CLG_(clo).collect_alloc) + CLG_(register_event_group2)(EG_ALLOC, "allocCount", "allocSize"); -} + if (CLG_(clo).collect_systime) + CLG_(register_event_group2)(EG_SYS, "sysCount", "sysTime"); + // event set used as base for instruction self cost + CLG_(sets).base = CLG_(get_event_set2)(EG_USE, EG_IR); + // event set comprising all event groups, used for inclusive cost + CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).base, EG_DR, EG_DW); + CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_BC, EG_BI); + CLG_(sets).full = CLG_(add_event_group) (CLG_(sets).full, EG_BUS); + CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_ALLOC, EG_SYS); -static -void add_and_zero_Dx(EventSet* es, SimCost dst, ULong* cost) -{ - /* if eventset use is defined, it is always first (hardcoded!) */ - CLG_(add_and_zero_cost)( CLG_(sets).Use, dst, cost); + CLG_DEBUGIF(1) { + CLG_DEBUG(1, "EventSets:\n"); + CLG_(print_eventset)(-2, CLG_(sets).base); + CLG_(print_eventset)(-2, CLG_(sets).full); + } - if (es == CLG_(sets).UIr) { - CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir, - cost + off_UIr_Ir); - } - else if (es == CLG_(sets).UIrDr) { - CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir, - cost + off_UIrDr_Ir); - CLG_(add_and_zero_cost)( CLG_(sets).Dr, dst + CLG_(sets).off_full_Dr, - cost + off_UIrDr_Dr); - } - else if (es == CLG_(sets).UIrDrDw) { - CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir, - cost + off_UIrDrDw_Ir); - CLG_(add_and_zero_cost)( CLG_(sets).Dr, dst + CLG_(sets).off_full_Dr, - cost + off_UIrDrDw_Dr); - CLG_(add_and_zero_cost)( CLG_(sets).Dw, dst + CLG_(sets).off_full_Dw, - cost + off_UIrDrDw_Dw); - } - else if (es == CLG_(sets).UIrDw) { - CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir, - cost + off_UIrDw_Ir); - CLG_(add_and_zero_cost)( CLG_(sets).Dw, dst + CLG_(sets).off_full_Dw, - cost + off_UIrDw_Dw); - } - else if (es == CLG_(sets).UIrDwDr) { - CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir, - cost + off_UIrDwDr_Ir); - CLG_(add_and_zero_cost)( CLG_(sets).Dw, dst + CLG_(sets).off_full_Dw, - cost + off_UIrDwDr_Dw); - CLG_(add_and_zero_cost)( CLG_(sets).Dr, dst + CLG_(sets).off_full_Dr, - cost + off_UIrDwDr_Dr); - } - else CLG_ASSERT(0); + /* Not-existing events are silently ignored */ + CLG_(dumpmap) = CLG_(get_eventmapping)(CLG_(sets).full); + CLG_(append_event)(CLG_(dumpmap), "Ir"); + CLG_(append_event)(CLG_(dumpmap), "Dr"); + CLG_(append_event)(CLG_(dumpmap), "Dw"); + CLG_(append_event)(CLG_(dumpmap), "I1mr"); + CLG_(append_event)(CLG_(dumpmap), "D1mr"); + CLG_(append_event)(CLG_(dumpmap), "D1mw"); + CLG_(append_event)(CLG_(dumpmap), "ILmr"); + CLG_(append_event)(CLG_(dumpmap), "DLmr"); + CLG_(append_event)(CLG_(dumpmap), "DLmw"); + CLG_(append_event)(CLG_(dumpmap), "ILdmr"); + CLG_(append_event)(CLG_(dumpmap), "DLdmr"); + CLG_(append_event)(CLG_(dumpmap), "DLdmw"); + CLG_(append_event)(CLG_(dumpmap), "Bc"); + CLG_(append_event)(CLG_(dumpmap), "Bcm"); + CLG_(append_event)(CLG_(dumpmap), "Bi"); + CLG_(append_event)(CLG_(dumpmap), "Bim"); + CLG_(append_event)(CLG_(dumpmap), "AcCost1"); + CLG_(append_event)(CLG_(dumpmap), "SpLoss1"); + CLG_(append_event)(CLG_(dumpmap), "AcCost2"); + CLG_(append_event)(CLG_(dumpmap), "SpLoss2"); + CLG_(append_event)(CLG_(dumpmap), "Ge"); + CLG_(append_event)(CLG_(dumpmap), "allocCount"); + CLG_(append_event)(CLG_(dumpmap), "allocSize"); + CLG_(append_event)(CLG_(dumpmap), "sysCount"); + CLG_(append_event)(CLG_(dumpmap), "sysTime"); } + /* this is called at dump time for every instruction executed */ static void cachesim_add_icost(SimCost cost, BBCC* bbcc, InstrInfo* ii, ULong exe_count) { - if (!CLG_(clo).simulate_cache) - cost[CLG_(sets).off_full_Ir] += exe_count; - else { - -#if 0 -/* There is always a trivial case where exe_count and Ir can be - * slightly different because ecounter is updated when executing - * the next BB. E.g. for last BB executed, or when toggling collection - */ - /* FIXME: Hardcoded that each eventset has Ir as first */ - if ((bbcc->cost + ii->cost_offset)[0] != exe_count) { - VG_(printf)("==> Ir %llu, exe %llu\n", - (bbcc->cost + ii->cost_offset)[0], exe_count); - CLG_(print_bbcc_cost)(-2, bbcc); - //CLG_ASSERT((bbcc->cost + ii->cost_offset)[0] == exe_count); - } -#endif + if (!CLG_(clo).simulate_cache) + cost[ fullOffset(EG_IR) ] += exe_count; - add_and_zero_Dx(ii->eventset, cost, - bbcc->cost + ii->cost_offset); - } -} - -static -void cachesim_after_bbsetup(void) -{ - BBCC* bbcc = CLG_(current_state).bbcc; - - if (CLG_(clo).simulate_cache) { - BB* bb = bbcc->bb; - - /* only needed if log_* functions are called */ - bb_base = bb->obj->offset + bb->offset; - cost_base = bbcc->cost; - } + if (ii->eventset) + CLG_(add_and_zero_cost2)( CLG_(sets).full, cost, + ii->eventset, bbcc->cost + ii->cost_offset); } static @@ -2054,7 +1862,6 @@ struct cachesim_if CLG_(cachesim) = { .getdesc = cachesim_getdesc, .printstat = cachesim_printstat, .add_icost = cachesim_add_icost, - .after_bbsetup = cachesim_after_bbsetup, .finish = cachesim_finish, /* these will be set by cachesim_post_clo_init */ diff --git a/callgrind/tests/Makefile.am b/callgrind/tests/Makefile.am index 1f5e64e..5c58e8e 100644 --- a/callgrind/tests/Makefile.am +++ b/callgrind/tests/Makefile.am @@ -15,7 +15,8 @@ EXTRA_DIST = \ notpower2-wb.vgtest notpower2-wb.stderr.exp \ notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \ notpower2-use.vgtest notpower2-use.stderr.exp \ - threads.vgtest threads.stderr.exp + threads.vgtest threads.stderr.exp \ + threads-use.vgtest threads-use.stderr.exp check_PROGRAMS = clreq simwork threads diff --git a/callgrind/tests/filter_stderr b/callgrind/tests/filter_stderr index 1a58540..3114b47 100755 --- a/callgrind/tests/filter_stderr +++ b/callgrind/tests/filter_stderr @@ -13,14 +13,18 @@ sed "/^For interactive control,.*$/d" | # Remove numbers from "Collected" line sed "s/^\(Collected *:\)[ 0-9]*$/\1/" | -# Remove numbers from I/D/L2 "refs:" lines -perl -p -e 's/((I|D|L2) *refs:)[ 0-9,()+rdw]*$/\1/' | +# Remove numbers from I/D/LL "refs:" lines +perl -p -e 's/((I|D|LL) *refs:)[ 0-9,()+rdw]*$/\1/' | -# Remove numbers from I1/D1/L2/L2i/L2d "misses:" and "miss rates:" lines -perl -p -e 's/((I1|D1|L2|L2i|L2d) *(misses|miss rate):)[ 0-9,()+rdw%\.]*$/\1/' | +# Remove numbers from I1/D1/LL/LLi/LLd "misses:" and "miss rates:" lines +perl -p -e 's/((I1|D1|LL|LLi|LLd) *(misses|miss rate):)[ 0-9,()+rdw%\.]*$/\1/' | + +# Remove numbers from "Branches:", "Mispredicts:, and "Mispred rate:" lines +perl -p -e 's/((Branches|Mispredicts|Mispred rate):)[ 0-9,()+condi%\.]*$/\1/' | # Remove CPUID warnings lines for P4s and other machines sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" | sed "/Simulating a 16 KB I-cache with 32 B lines/d" | -sed "/warning: L3 cache detected but ignored/d" | -sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d" +sed "/warning: L3 cache found, using its data for the LL simulation./d" | +sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d" | +sed "/Warning: Cannot auto-detect cache config on ARM, using one or more defaults/d" diff --git a/callgrind/tests/notpower2-hwpref.stderr.exp b/callgrind/tests/notpower2-hwpref.stderr.exp index 0705c1c..974550a 100644 --- a/callgrind/tests/notpower2-hwpref.stderr.exp +++ b/callgrind/tests/notpower2-hwpref.stderr.exp @@ -1,20 +1,20 @@ -Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw Collected : I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/notpower2-hwpref.vgtest b/callgrind/tests/notpower2-hwpref.vgtest index 9da7dce..1be3b13 100644 --- a/callgrind/tests/notpower2-hwpref.vgtest +++ b/callgrind/tests/notpower2-hwpref.vgtest @@ -1,3 +1,3 @@ prog: ../../tests/true -vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-hwpref=yes +vgopts: --I1=32768,8,64 --D1=24576,6,64 --LL=3145728,12,64 --simulate-hwpref=yes cleanup: rm callgrind.out.* diff --git a/callgrind/tests/notpower2-use.stderr.exp b/callgrind/tests/notpower2-use.stderr.exp index ea9acc8..6d41645 100644 --- a/callgrind/tests/notpower2-use.stderr.exp +++ b/callgrind/tests/notpower2-use.stderr.exp @@ -1,20 +1,20 @@ -Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2 +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw AcCost1 SpLoss1 AcCost2 SpLoss2 Collected : I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/notpower2-use.vgtest b/callgrind/tests/notpower2-use.vgtest index b8312a7..23cec4a 100644 --- a/callgrind/tests/notpower2-use.vgtest +++ b/callgrind/tests/notpower2-use.vgtest @@ -1,3 +1,3 @@ prog: ../../tests/true -vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --cacheuse=yes +vgopts: --I1=32768,8,64 --D1=24576,6,64 --LL=3145728,12,64 --cacheuse=yes cleanup: rm callgrind.out.* diff --git a/callgrind/tests/notpower2-wb.stderr.exp b/callgrind/tests/notpower2-wb.stderr.exp index 90da3e4..461ac96 100644 --- a/callgrind/tests/notpower2-wb.stderr.exp +++ b/callgrind/tests/notpower2-wb.stderr.exp @@ -1,20 +1,20 @@ -Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw ILdmr DLdmr DLdmw Collected : I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/notpower2-wb.vgtest b/callgrind/tests/notpower2-wb.vgtest index 34a1f6b..6cd016f 100644 --- a/callgrind/tests/notpower2-wb.vgtest +++ b/callgrind/tests/notpower2-wb.vgtest @@ -1,3 +1,3 @@ prog: ../../tests/true -vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 --simulate-wb=yes +vgopts: --I1=32768,8,64 --D1=24576,6,64 --LL=3145728,12,64 --simulate-wb=yes cleanup: rm callgrind.out.* diff --git a/callgrind/tests/notpower2.stderr.exp b/callgrind/tests/notpower2.stderr.exp index 0705c1c..974550a 100644 --- a/callgrind/tests/notpower2.stderr.exp +++ b/callgrind/tests/notpower2.stderr.exp @@ -1,20 +1,20 @@ -Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw Collected : I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/notpower2.vgtest b/callgrind/tests/notpower2.vgtest index 73823d7..83b9946 100644 --- a/callgrind/tests/notpower2.vgtest +++ b/callgrind/tests/notpower2.vgtest @@ -1,3 +1,3 @@ prog: ../../tests/true -vgopts: --I1=32768,8,64 --D1=24576,6,64 --L2=3145728,12,64 +vgopts: --I1=32768,8,64 --D1=24576,6,64 --LL=3145728,12,64 cleanup: rm callgrind.out.* diff --git a/callgrind/tests/simwork-both.stderr.exp b/callgrind/tests/simwork-both.stderr.exp new file mode 100644 index 0000000..f8fb402 --- /dev/null +++ b/callgrind/tests/simwork-both.stderr.exp @@ -0,0 +1,24 @@ + + +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw Bc Bcm Bi Bim +Collected : + +I refs: +I1 misses: +LLi misses: +I1 miss rate: +LLi miss rate: + +D refs: +D1 misses: +LLd misses: +D1 miss rate: +LLd miss rate: + +LL refs: +LL misses: +LL miss rate: + +Branches: +Mispredicts: +Mispred rate: diff --git a/callgrind/tests/simwork-both.stdout.exp b/callgrind/tests/simwork-both.stdout.exp new file mode 100644 index 0000000..d4c867c --- /dev/null +++ b/callgrind/tests/simwork-both.stdout.exp @@ -0,0 +1 @@ +Sum: 1000000 diff --git a/callgrind/tests/simwork-both.vgtest b/callgrind/tests/simwork-both.vgtest new file mode 100644 index 0000000..19c3ff8 --- /dev/null +++ b/callgrind/tests/simwork-both.vgtest @@ -0,0 +1,3 @@ +prog: simwork +vgopts: --cache-sim=yes --branch-sim=yes +cleanup: rm callgrind.out.* diff --git a/callgrind/tests/simwork-branch.stderr.exp b/callgrind/tests/simwork-branch.stderr.exp new file mode 100644 index 0000000..7cda62e --- /dev/null +++ b/callgrind/tests/simwork-branch.stderr.exp @@ -0,0 +1,10 @@ + + +Events : Ir Bc Bcm Bi Bim +Collected : + +I refs: + +Branches: +Mispredicts: +Mispred rate: diff --git a/callgrind/tests/simwork-branch.stdout.exp b/callgrind/tests/simwork-branch.stdout.exp new file mode 100644 index 0000000..d4c867c --- /dev/null +++ b/callgrind/tests/simwork-branch.stdout.exp @@ -0,0 +1 @@ +Sum: 1000000 diff --git a/callgrind/tests/simwork-branch.vgtest b/callgrind/tests/simwork-branch.vgtest new file mode 100644 index 0000000..a866e1e --- /dev/null +++ b/callgrind/tests/simwork-branch.vgtest @@ -0,0 +1,3 @@ +prog: simwork +vgopts: --branch-sim=yes +cleanup: rm callgrind.out.* diff --git a/callgrind/tests/simwork-cache.stderr.exp b/callgrind/tests/simwork-cache.stderr.exp new file mode 100644 index 0000000..974550a --- /dev/null +++ b/callgrind/tests/simwork-cache.stderr.exp @@ -0,0 +1,20 @@ + + +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw +Collected : + +I refs: +I1 misses: +LLi misses: +I1 miss rate: +LLi miss rate: + +D refs: +D1 misses: +LLd misses: +D1 miss rate: +LLd miss rate: + +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/simwork-cache.stdout.exp b/callgrind/tests/simwork-cache.stdout.exp new file mode 100644 index 0000000..d4c867c --- /dev/null +++ b/callgrind/tests/simwork-cache.stdout.exp @@ -0,0 +1 @@ +Sum: 1000000 diff --git a/callgrind/tests/simwork-cache.vgtest b/callgrind/tests/simwork-cache.vgtest new file mode 100644 index 0000000..ce222c0 --- /dev/null +++ b/callgrind/tests/simwork-cache.vgtest @@ -0,0 +1,3 @@ +prog: simwork +vgopts: --cache-sim=yes +cleanup: rm callgrind.out.* diff --git a/callgrind/tests/simwork1.stderr.exp b/callgrind/tests/simwork1.stderr.exp index 0705c1c..974550a 100644 --- a/callgrind/tests/simwork1.stderr.exp +++ b/callgrind/tests/simwork1.stderr.exp @@ -1,20 +1,20 @@ -Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw Collected : I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/simwork2.stderr.exp b/callgrind/tests/simwork2.stderr.exp index 90da3e4..461ac96 100644 --- a/callgrind/tests/simwork2.stderr.exp +++ b/callgrind/tests/simwork2.stderr.exp @@ -1,20 +1,20 @@ -Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw I2dmr D2dmr D2dmw +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw ILdmr DLdmr DLdmw Collected : I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/simwork3.stderr.exp b/callgrind/tests/simwork3.stderr.exp index ea9acc8..6d41645 100644 --- a/callgrind/tests/simwork3.stderr.exp +++ b/callgrind/tests/simwork3.stderr.exp @@ -1,20 +1,20 @@ -Events : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2 +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw AcCost1 SpLoss1 AcCost2 SpLoss2 Collected : I refs: I1 misses: -L2i misses: +LLi misses: I1 miss rate: -L2i miss rate: +LLi miss rate: D refs: D1 misses: -L2d misses: +LLd misses: D1 miss rate: -L2d miss rate: +LLd miss rate: -L2 refs: -L2 misses: -L2 miss rate: +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/threads-use.stderr.exp b/callgrind/tests/threads-use.stderr.exp new file mode 100644 index 0000000..c8fd75e --- /dev/null +++ b/callgrind/tests/threads-use.stderr.exp @@ -0,0 +1,20 @@ + + +Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw AcCost1 SpLoss1 AcCost2 SpLoss2 Ge sysCount sysTime +Collected : + +I refs: +I1 misses: +LLi misses: +I1 miss rate: +LLi miss rate: + +D refs: +D1 misses: +LLd misses: +D1 miss rate: +LLd miss rate: + +LL refs: +LL misses: +LL miss rate: diff --git a/callgrind/tests/threads-use.vgtest b/callgrind/tests/threads-use.vgtest new file mode 100644 index 0000000..6299b1f --- /dev/null +++ b/callgrind/tests/threads-use.vgtest @@ -0,0 +1,3 @@ +prog: threads +vgopts: --separate-threads=yes --cacheuse=yes --collect-bus=yes --collect-systime=yes +cleanup: rm callgrind.out.* diff --git a/callgrind/tests/threads.stderr.exp b/callgrind/tests/threads.stderr.exp index d0b7820..da443cf 100644 --- a/callgrind/tests/threads.stderr.exp +++ b/callgrind/tests/threads.stderr.exp @@ -1,6 +1,6 @@ -Events : Ir +Events : Ir Ge Collected : I refs: diff --git a/callgrind/tests/threads.vgtest b/callgrind/tests/threads.vgtest index d015eeb..4ff103a 100644 --- a/callgrind/tests/threads.vgtest +++ b/callgrind/tests/threads.vgtest @@ -1,3 +1,3 @@ prog: threads -vgopts: --separate-threads=yes +vgopts: --separate-threads=yes --collect-bus=yes cleanup: rm callgrind.out.* diff --git a/callgrind/threads.c b/callgrind/threads.c index 9334667..fb8260b 100644 --- a/callgrind/threads.c +++ b/callgrind/threads.c @@ -6,7 +6,7 @@ /* This file is part of Callgrind, a Valgrind tool for call tracing. - Copyright (C) 2002-2009, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) + Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -203,7 +203,7 @@ void CLG_(pre_signal)(ThreadId tid, Int sigNum, Bool alt_stack) tid, sigNum, alt_stack ? "yes":"no"); /* switch to the thread the handler runs in */ - CLG_(run_thread)(tid); + CLG_(switch_thread)(tid); /* save current execution state */ exec_state_save(); @@ -243,7 +243,8 @@ void CLG_(post_signal)(ThreadId tid, Int sigNum) CLG_DEBUG(0, ">> post_signal(TID %d, sig %d)\n", tid, sigNum); - CLG_ASSERT(tid == CLG_(current_tid)); + /* thread switching potentially needed, eg. with instrumentation off */ + CLG_(switch_thread)(tid); CLG_ASSERT(sigNum == CLG_(current_state).sig); /* Unwind call stack of this signal handler. diff --git a/configure.in b/configure.in index 9380b32..3237b6b 100644 --- a/configure.in +++ b/configure.in @@ -8,7 +8,7 @@ ##------------------------------------------------------------## # Process this file with autoconf to produce a configure script. -AC_INIT(Valgrind, 3.5.0, valgrind-users@lists.sourceforge.net) +AC_INIT(Valgrind, 3.6.0, valgrind-users@lists.sourceforge.net) AC_CONFIG_SRCDIR(coregrind/m_main.c) AM_CONFIG_HEADER(config.h) AM_INIT_AUTOMAKE([foreign]) @@ -18,7 +18,7 @@ AM_MAINTAINER_MODE #---------------------------------------------------------------------------- # Checks for various programs. #---------------------------------------------------------------------------- -CFLAGS="-Wno-long-long" +CFLAGS="-Wno-long-long $CFLAGS" AC_PROG_LN_S AC_PROG_CC @@ -40,11 +40,18 @@ AC_PROG_CXX # ]) AC_PROG_RANLIB AC_PROG_EGREP +# provide a very basic definition for AC_PROG_SED if it's not provided by +# autoconf (as e.g. in autoconf 2.59). +m4_ifndef([AC_PROG_SED], + [AC_DEFUN([AC_PROG_SED], + [AC_ARG_VAR([SED]) + AC_CHECK_PROGS([SED],[gsed sed])])]) +AC_PROG_SED # If no AR variable was specified, look up the name of the archiver. Otherwise # do not touch the AR variable. if test "x$AR" = "x"; then - AC_PATH_PROGS([AR], [`echo $LD | sed 's/ld$/ar/'` "ar"], [ar]) + AC_PATH_PROGS([AR], [`echo $LD | $SED 's/ld$/ar/'` "ar"], [ar]) fi AC_ARG_VAR([AR],[Archiver command]) @@ -96,7 +103,7 @@ rm $tmpfile # We don't want gcc < 3.0 AC_MSG_CHECKING([for a supported version of gcc]) -[gcc_version=`${CC} --version | head -n 1 | ${SED} 's/^[^0-9]*\([0-9.]*\).*$/\1/'`] +[gcc_version=`${CC} --version | head -n 1 | $SED 's/^[^0-9]*\([0-9.]*\).*$/\1/'`] case "${gcc_version}" in 2.*) @@ -155,6 +162,11 @@ case "${host_cpu}" in esac ;; + armv7*) + AC_MSG_RESULT([ok (${host_cpu})]) + ARCH_MAX="arm" + ;; + *) AC_MSG_RESULT([no (${host_cpu})]) AC_MSG_ERROR([Unsupported host architecture. Sorry]) @@ -252,6 +264,9 @@ case "${host_os}" in *darwin*) AC_MSG_RESULT([ok (${host_os})]) VGCONF_OS="darwin" + AC_DEFINE([DARWIN_10_5], 100500, [DARWIN_VERS value for Mac OS X 10.5]) + AC_DEFINE([DARWIN_10_6], 100600, [DARWIN_VERS value for Mac OS X 10.6]) + AC_DEFINE([DARWIN_10_7], 100700, [DARWIN_VERS value for Mac OS X 10.7]) AC_MSG_CHECKING([for the kernel version]) kernel=`uname -r` @@ -259,28 +274,34 @@ case "${host_os}" in # Nb: for Darwin we set DEFAULT_SUPP here. That's because Darwin # has only one relevant version, the OS version. The `uname` check # is a good way to get that version (i.e. "Darwin 9.6.0" is Mac OS - # X 10.5.6, and "Darwin 10.x" would presumably be Mac OS X 10.6.x - # Snow Leopard and darwin10.supp), and we don't know of an macros - # similar to __GLIBC__ to get that info. + # X 10.5.6, and "Darwin 10.x" is Mac OS X 10.6.x Snow Leopard), + # and we don't know of an macros similar to __GLIBC__ to get that info. # # XXX: `uname -r` won't do the right thing for cross-compiles, but # that's not a problem yet. case "${kernel}" in 9.*) AC_MSG_RESULT([Darwin 9.x (${kernel}) / Mac OS X 10.5 Leopard]) + AC_DEFINE([DARWIN_VERS], DARWIN_10_5, [Darwin / Mac OS X version]) DEFAULT_SUPP="darwin9.supp ${DEFAULT_SUPP}" DEFAULT_SUPP="darwin9-drd.supp ${DEFAULT_SUPP}" ;; + 10.*) + AC_MSG_RESULT([Darwin 10.x (${kernel}) / Mac OS X 10.6 Snow Leopard]) + AC_DEFINE([DARWIN_VERS], DARWIN_10_6, [Darwin / Mac OS X version]) + DEFAULT_SUPP="darwin10.supp ${DEFAULT_SUPP}" + DEFAULT_SUPP="darwin10-drd.supp ${DEFAULT_SUPP}" + ;; *) AC_MSG_RESULT([unsupported (${kernel})]) - AC_MSG_ERROR([Valgrind works on Darwin 9.x (Mac OS X 10.5)]) + AC_MSG_ERROR([Valgrind works on Darwin 9.x and 10.x (Mac OS X 10.5 and 10.6)]) ;; esac ;; *) AC_MSG_RESULT([no (${host_os})]) - AC_MSG_ERROR([Valgrind is operating system specific. Sorry. Please consider doing a port.]) + AC_MSG_ERROR([Valgrind is operating system specific. Sorry.]) ;; esac @@ -351,35 +372,52 @@ AC_SUBST(VGCONF_PLATFORM_SEC_CAPS) AC_MSG_CHECKING([for a supported CPU/OS combination]) +# NB. The load address for a given platform may be specified in more +# than one place, in some cases, depending on whether we're doing a biarch, +# 32-bit only or 64-bit only build. eg see case for amd64-linux below. +# Be careful to give consistent values in all subcases. Also, all four +# valt_load_addres_{pri,sec}_{norml,inner} values must always be set, +# even if it is to "0xUNSET". +# case "$ARCH_MAX-$VGCONF_OS" in x86-linux) VGCONF_ARCH_PRI="x86" VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="X86_LINUX" VGCONF_PLATFORM_SEC_CAPS="" - valt_load_address_normal="0x38000000" - valt_load_address_inner="0x28000000" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; amd64-linux) + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" if test x$vg_cv_only64bit = xyes; then VGCONF_ARCH_PRI="amd64" VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX" VGCONF_PLATFORM_SEC_CAPS="" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" elif test x$vg_cv_only32bit = xyes; then VGCONF_ARCH_PRI="x86" VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="X86_LINUX" VGCONF_PLATFORM_SEC_CAPS="" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" else VGCONF_ARCH_PRI="amd64" VGCONF_ARCH_SEC="x86" VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX" VGCONF_PLATFORM_SEC_CAPS="X86_LINUX" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" + valt_load_address_sec_norml="0x38000000" + valt_load_address_sec_inner="0x28000000" fi - valt_load_address_normal="0x38000000" - valt_load_address_inner="0x28000000" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; ppc32-linux) @@ -387,11 +425,17 @@ case "$ARCH_MAX-$VGCONF_OS" in VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX" VGCONF_PLATFORM_SEC_CAPS="" - valt_load_address_normal="0x38000000" - valt_load_address_inner="0x28000000" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; ppc64-aix5) + valt_load_address_pri_norml="0xUNSET" + valt_load_address_pri_inner="0xUNSET" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" if test x$vg_cv_only64bit = xyes; then VGCONF_ARCH_PRI="ppc64" VGCONF_ARCH_SEC="" @@ -408,29 +452,35 @@ case "$ARCH_MAX-$VGCONF_OS" in VGCONF_PLATFORM_PRI_CAPS="PPC64_AIX5" VGCONF_PLATFORM_SEC_CAPS="PPC32_AIX5" fi - valt_load_address_normal="0x38000000" - valt_load_address_inner="0x28000000" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; ppc64-linux) + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" if test x$vg_cv_only64bit = xyes; then VGCONF_ARCH_PRI="ppc64" VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX" VGCONF_PLATFORM_SEC_CAPS="" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" elif test x$vg_cv_only32bit = xyes; then VGCONF_ARCH_PRI="ppc32" VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX" VGCONF_PLATFORM_SEC_CAPS="" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" else VGCONF_ARCH_PRI="ppc64" VGCONF_ARCH_SEC="ppc32" VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX" VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" + valt_load_address_sec_norml="0x38000000" + valt_load_address_sec_inner="0x28000000" fi - valt_load_address_normal="0x38000000" - valt_load_address_inner="0x28000000" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; x86-freebsd) @@ -438,8 +488,10 @@ case "$ARCH_MAX-$VGCONF_OS" in VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="X86_FREEBSD" VGCONF_PLATFORM_SEC_CAPS="" - valt_load_address_normal="0x38000000" - valt_load_address_inner="0x28000000" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; amd64-freebsd) @@ -460,46 +512,67 @@ case "$ARCH_MAX-$VGCONF_OS" in VGCONF_PLATFORM_SEC_CAPS="X86_FREEBSD" fi FLAG_32ON64="-B/usr/lib32" - valt_load_address_normal="0x38000000" - valt_load_address_inner="0x28000000" - AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) - ;; - x86-darwin) - VGCONF_ARCH_PRI="x86" - VGCONF_ARCH_SEC="" - VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN" - VGCONF_PLATFORM_SEC_CAPS="" - valt_load_address_normal="0x0" - valt_load_address_inner="0x0" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" + valt_load_address_sec_norml="0x38000000" + valt_load_address_sec_inner="0x28000000" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; - amd64-darwin) + # Darwin gets identified as 32-bit even when it supports 64-bit. + # (Not sure why, possibly because 'uname' returns "i386"?) Just about + # all Macs support both 32-bit and 64-bit, so we just build both. If + # someone has a really old 32-bit only machine they can (hopefully?) + # build with --enable-only32bit. See bug 243362. + x86-darwin|amd64-darwin) + ARCH_MAX="amd64" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" if test x$vg_cv_only64bit = xyes; then VGCONF_ARCH_PRI="amd64" VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN" VGCONF_PLATFORM_SEC_CAPS="" + valt_load_address_pri_norml="0x138000000" + valt_load_address_pri_inner="0x128000000" elif test x$vg_cv_only32bit = xyes; then VGCONF_ARCH_PRI="x86" VGCONF_ARCH_SEC="" VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN" VGCONF_PLATFORM_SEC_CAPS="" VGCONF_ARCH_PRI_CAPS="x86" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" else VGCONF_ARCH_PRI="amd64" VGCONF_ARCH_SEC="x86" VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN" VGCONF_PLATFORM_SEC_CAPS="X86_DARWIN" + valt_load_address_pri_norml="0x138000000" + valt_load_address_pri_inner="0x128000000" + valt_load_address_sec_norml="0x38000000" + valt_load_address_sec_inner="0x28000000" fi - valt_load_address_normal="0x0" - valt_load_address_inner="0x0" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; + arm-linux) + VGCONF_ARCH_PRI="arm" + VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX" + VGCONF_PLATFORM_SEC_CAPS="" + valt_load_address_pri_norml="0x38000000" + valt_load_address_pri_inner="0x28000000" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" + AC_MSG_RESULT([ok (${host_cpu}-${host_os})]) + ;; *) VGCONF_ARCH_PRI="unknown" VGCONF_ARCH_SEC="unknown" VGCONF_PLATFORM_PRI_CAPS="UNKNOWN" VGCONF_PLATFORM_SEC_CAPS="UNKNOWN" + valt_load_address_pri_norml="0xUNSET" + valt_load_address_pri_inner="0xUNSET" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" AC_MSG_RESULT([no (${ARCH_MAX}-${VGCONF_OS})]) AC_MSG_ERROR([Valgrind is platform specific. Sorry. Please consider doing a port.]) ;; @@ -528,6 +601,8 @@ AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC32, AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC64, test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_AIX5 ) +AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_ARM, + test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX ) # Set up VGCONF_PLATFORMS_INCLUDE_. Either one or two of these # become defined. @@ -541,6 +616,8 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX, -o x$VGCONF_PLATFORM_SEC_CAPS = xPPC32_LINUX) AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX, test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX) +AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ARM_LINUX, + test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX) AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD, test x$VGCONF_PLATFORM_PRI_CAPS = xX86_FREEBSD \ @@ -561,14 +638,15 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN, test x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_DARWIN) -# Similarly, set up VGCONF_OF_IS_. Exactly one of these becomes defined. +# Similarly, set up VGCONF_OS_IS_. Exactly one of these becomes defined. # Relies on the assumption that the primary and secondary targets are # for the same OS, so therefore only necessary to test the primary. AM_CONDITIONAL(VGCONF_OS_IS_LINUX, test x$VGCONF_PLATFORM_PRI_CAPS = xX86_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX) + -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX ) AM_CONDITIONAL(VGCONF_OS_IS_FREEBSD, test x$VGCONF_PLATFORM_PRI_CAPS = xX86_FREEBSD \ -o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_FREEBSD \ @@ -594,7 +672,8 @@ AM_CONDITIONAL(VGCONF_HAVE_PLATFORM_SEC, # Check if this should be built as an inner Valgrind, to be run within # another Valgrind. Choose the load address accordingly. -AC_SUBST(VALT_LOAD_ADDRESS) +AC_SUBST(VALT_LOAD_ADDRESS_PRI) +AC_SUBST(VALT_LOAD_ADDRESS_SEC) AC_CACHE_CHECK([for use as an inner Valgrind], vg_cv_inner, [AC_ARG_ENABLE(inner, [ --enable-inner enables self-hosting], @@ -602,9 +681,11 @@ AC_CACHE_CHECK([for use as an inner Valgrind], vg_cv_inner, [vg_cv_inner=no])]) if test "$vg_cv_inner" = yes; then AC_DEFINE([ENABLE_INNER], 1, [configured to run as an inner Valgrind]) - VALT_LOAD_ADDRESS=$valt_load_address_inner + VALT_LOAD_ADDRESS_PRI=$valt_load_address_pri_inner + VALT_LOAD_ADDRESS_SEC=$valt_load_address_sec_inner else - VALT_LOAD_ADDRESS=$valt_load_address_normal + VALT_LOAD_ADDRESS_PRI=$valt_load_address_pri_norml + VALT_LOAD_ADDRESS_SEC=$valt_load_address_sec_norml fi @@ -614,99 +695,18 @@ fi # This variable will collect the suppression files to be used. AC_SUBST(DEFAULT_SUPP) -case "$VG_OS" in - linux) -GLIBC_VERSION="" - -AC_EGREP_CPP([GLIBC_22], [ -#include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 2) - GLIBC_22 - #endif -#endif -], -GLIBC_VERSION="2.2") - -AC_EGREP_CPP([GLIBC_23], [ -#include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 3) - GLIBC_23 - #endif -#endif -], -GLIBC_VERSION="2.3") - -AC_EGREP_CPP([GLIBC_24], [ -#include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 4) - GLIBC_24 - #endif -#endif -], -GLIBC_VERSION="2.4") - -AC_EGREP_CPP([GLIBC_25], [ -#include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 5) - GLIBC_25 - #endif -#endif -], -GLIBC_VERSION="2.5") - -AC_EGREP_CPP([GLIBC_26], [ -#include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 6) - GLIBC_26 - #endif -#endif -], -GLIBC_VERSION="2.6") - -AC_EGREP_CPP([GLIBC_27], [ -#include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 7) - GLIBC_27 - #endif -#endif -], -GLIBC_VERSION="2.7") - -AC_EGREP_CPP([GLIBC_28], [ -#include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 8) - GLIBC_28 - #endif -#endif -], -GLIBC_VERSION="2.8") - -AC_EGREP_CPP([GLIBC_29], [ -#include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 9) - GLIBC_29 - #endif -#endif -], -GLIBC_VERSION="2.9") +AC_CHECK_HEADER([features.h]) -AC_EGREP_CPP([GLIBC_210], [ +if test x$ac_cv_header_features_h = xyes; then + rm -f conftest.$ac_ext + cat <<_ACEOF >conftest.$ac_ext #include -#ifdef __GNU_LIBRARY__ - #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 10) - GLIBC_210 - #endif +#if defined(__GNU_LIBRARY__) && defined(__GLIBC__) && defined(__GLIBC_MINOR__) +glibc version is: __GLIBC__ __GLIBC_MINOR__ #endif -], -GLIBC_VERSION="2.10") +_ACEOF + GLIBC_VERSION="`$CPP conftest.$ac_ext | $SED -n 's/^glibc version is: //p' | $SED 's/ /./g'`" +fi AC_EGREP_CPP([AIX5_LIBC], [ #include @@ -794,6 +794,20 @@ case "${GLIBC_VERSION}" in DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}" DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}" ;; + 2.11) + AC_MSG_RESULT(2.11 family) + AC_DEFINE([GLIBC_2_11], 1, [Define to 1 if you're using glibc 2.11.x]) + DEFAULT_SUPP="glibc-2.X.supp ${DEFAULT_SUPP}" + DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}" + DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}" + ;; + 2.12) + AC_MSG_RESULT(2.12 family) + AC_DEFINE([GLIBC_2_12], 1, [Define to 1 if you're using glibc 2.12.x]) + DEFAULT_SUPP="glibc-2.X.supp ${DEFAULT_SUPP}" + DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}" + DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}" + ;; aix5) AC_MSG_RESULT(AIX 5.1 or 5.2 or 5.3) AC_DEFINE([AIX5_LIBC], 1, [Define to 1 if you're using AIX 5.1 or 5.2 or 5.3]) @@ -806,8 +820,8 @@ case "${GLIBC_VERSION}" in ;; *) - AC_MSG_RESULT(unsupported version) - AC_MSG_ERROR([Valgrind requires glibc version 2.2 - 2.10]) + AC_MSG_RESULT([unsupported version ${GLIBC_VERSION}]) + AC_MSG_ERROR([Valgrind requires glibc version 2.2 - 2.12]) AC_MSG_ERROR([or AIX 5.1 or 5.2 or 5.3 GLIBC_VERSION]) AC_MSG_ERROR([or Darwin libc]) ;; @@ -937,40 +951,24 @@ AC_MSG_RESULT([no]) # Check whether pthread_mutex_t has a member called __m_kind. -AC_MSG_CHECKING([for pthread_mutex_t::__m_kind]) - -AC_TRY_COMPILE( -[ - #include -], [ - pthread_mutex_t m; - return m.__m_kind; -], [ -AC_MSG_RESULT([yes]) -AC_DEFINE([HAVE_PTHREAD_MUTEX_T__M_KIND], 1, - [Define to 1 if pthread_mutex_t has a member called __m_kind.]) -], [ -AC_MSG_RESULT([no]) -]) +AC_CHECK_MEMBER([pthread_mutex_t.__m_kind], + [AC_DEFINE([HAVE_PTHREAD_MUTEX_T__M_KIND], + 1, + [Define to 1 if pthread_mutex_t has a member called __m_kind.]) + ], + [], + [#include ]) # Check whether pthread_mutex_t has a member called __data.__kind. -AC_MSG_CHECKING([for pthread_mutex_t::__data.__kind]) - -AC_TRY_COMPILE( -[ -#include -], [ - pthread_mutex_t m; - return m.__data.__kind; -], [ -AC_MSG_RESULT([yes]) -AC_DEFINE([HAVE_PTHREAD_MUTEX_T__DATA__KIND], 1, - [Define to 1 if pthread_mutex_t has a member __data.__kind.]) -], [ -AC_MSG_RESULT([no]) -]) +AC_CHECK_MEMBER([pthread_mutex_t.__data.__kind], + [AC_DEFINE([HAVE_PTHREAD_MUTEX_T__DATA__KIND], + 1, + [Define to 1 if pthread_mutex_t has a member __data.__kind.]) + ], + [], + [#include ]) # does this compiler support -maltivec and does it have the include file @@ -990,6 +988,8 @@ AC_TRY_COMPILE( [ ac_have_altivec=yes AC_MSG_RESULT([yes]) +AC_DEFINE([HAS_ALTIVEC], 1, + [Define to 1 if gcc/as can do Altivec.]) ], [ ac_have_altivec=no AC_MSG_RESULT([no]) @@ -997,7 +997,6 @@ AC_MSG_RESULT([no]) CFLAGS=$safe_CFLAGS AM_CONDITIONAL([HAS_ALTIVEC], [test x$ac_have_altivec = xyes]) -AM_CONDITIONAL([HAVE_ALTIVEC_H], [test x$ac_have_altivec = xyes]) # Check for pthread_create@GLIBC2.0 @@ -1236,33 +1235,6 @@ if test x$no_pointer_sign = xyes; then fi -# does this compiler support -Wdeclaration-after-statement ? -AC_MSG_CHECKING([if gcc accepts -Wdeclaration-after-statement]) - -safe_CFLAGS=$CFLAGS -CFLAGS="-Wdeclaration-after-statement" - -AC_TRY_COMPILE(, [ - return 0; -], -[ -declaration_after_statement=yes -FLAG_WDECL_AFTER_STMT="-Wdeclaration-after-statement" -AC_MSG_RESULT([yes]) -], [ -declaration_after_statement=no -FLAG_WDECL_AFTER_STMT="" -AC_MSG_RESULT([no]) -]) -CFLAGS=$safe_CFLAGS - -AC_SUBST(FLAG_WDECL_AFTER_STMT) - -if test x$declaration_after_statement = xyes; then - CFLAGS="$CFLAGS -Wdeclaration-after-statement" -fi - - # does this compiler support -Wno-empty-body ? AC_MSG_CHECKING([if gcc accepts -Wno-empty-body]) @@ -1415,22 +1387,26 @@ AC_MSG_RESULT([no]) CFLAGS=$safe_CFLAGS -# does this compiler support __builtin_expect? -AC_MSG_CHECKING([if gcc supports __builtin_expect]) +# does the linker support -Wl,--build-id=none ? Note, it's +# important that we test indirectly via whichever C compiler +# is selected, rather than testing /usr/bin/ld or whatever +# directly. -AC_TRY_LINK(, [ -return __builtin_expect(1, 1) ? 1 : 0 -], +AC_MSG_CHECKING([if the linker accepts -Wl,--build-id=none]) + +safe_CFLAGS=$CFLAGS +CFLAGS="-Wl,--build-id=none" + +AC_LINK_IFELSE( +[AC_LANG_PROGRAM([ ], [return 0;])], [ -ac_have_builtin_expect=yes -AC_MSG_RESULT([yes]) + AC_SUBST([FLAG_NO_BUILD_ID], ["-Wl,--build-id=none"]) + AC_MSG_RESULT([yes]) ], [ -ac_have_builtin_expect=no -AC_MSG_RESULT([no]) + AC_SUBST([FLAG_NO_BUILD_ID], [""]) + AC_MSG_RESULT([no]) ]) -if test x$ac_have_builtin_expect = xyes ; then - AC_DEFINE(HAVE_BUILTIN_EXPECT, 1, [Define to 1 if gcc supports __builtin_expect.]) -fi +CFLAGS=$safe_CFLAGS # does the ppc assembler support "mtocrf" et al? @@ -1495,6 +1471,48 @@ AC_MSG_RESULT([no]) AM_CONDITIONAL(BUILD_SSSE3_TESTS, test x$ac_have_as_ssse3 = xyes) +# Note: we're really checking the assembler-level support, not gcc's ; +# C-level code might require the flag -mpclmul be passed to gcc (e.g. to +# compile code which uses wmmintrin.h). Doesn't matter since tests also +# use inline assembly directly +AC_MSG_CHECKING([if x86/amd64 assembler supports 'pclmulqdq']) +AC_TRY_COMPILE(, [ + do { + __asm__ __volatile__( + "pclmulqdq \$17,%%xmm6,%%xmm7" : : : "xmm6", "xmm7" ); } + while (0) +], +[ +ac_have_as_pclmulqdq=yes +AC_MSG_RESULT([yes]) +], [ +ac_have_as_pclmulqdq=no +AC_MSG_RESULT([no]) +]) + +AM_CONDITIONAL(BUILD_PCLMULQDQ_TESTS, test x$ac_have_as_pclmulqdq = xyes) + + +AC_MSG_CHECKING([if x86/amd64 assembler supports 'lzcnt']) + +AC_TRY_COMPILE([], [ + do { + __asm__ __volatile__("lzcnt %rax,%rax"); + } while (0) +], +[ + ac_have_as_lzcnt=yes + AC_MSG_RESULT([yes]) +], [ + ac_have_as_lzcnt=no + AC_MSG_RESULT([no]) +]) + +AM_CONDITIONAL([BUILD_LZCNT_TESTS], [test x$ac_have_as_lzcnt = xyes]) + +# XXX JRS 2010 Oct 13: what is this for? For sure, we don't need this +# when building the tool executables. I think we should get rid of it. +# # Check for TLS support in the compiler and linker if test "x${cross_compiling}" = "xno"; then # Native compilation: check whether running a program using TLS succeeds. @@ -1523,14 +1541,6 @@ AC_DEFINE([HAVE_TLS], 1, [can use __thread to define thread-local variables]) fi -#---------------------------------------------------------------------------- -# Check for /proc filesystem -#---------------------------------------------------------------------------- -AC_CHECK_FILES(/proc/self/fd /proc/self/exe /proc/self/maps, - [ AC_DEFINE([HAVE_PROC], 1, [can use /proc filesystem]) ], - []) - - #---------------------------------------------------------------------------- # Checks for C header files. #---------------------------------------------------------------------------- @@ -1590,15 +1600,17 @@ AC_CHECK_FUNCS([ \ pthread_rwlock_timedrdlock \ pthread_rwlock_timedwrlock \ pthread_spin_lock \ + pthread_yield \ + readlinkat \ semtimedop \ signalfd \ sigwaitinfo \ - syscall \ strchr \ strdup \ strpbrk \ strrchr \ strstr \ + syscall \ timerfd \ utimensat \ ]) @@ -1821,6 +1833,38 @@ if test x$ac_have_qtcore = xyes; then fi +# Test for QAtomicInt, which has been introduced in Qt 4.4. +# See also http://doc.trolltech.com/4.4/qatomicint.html. +if test x$ac_have_qtcore = xyes; then + AC_MSG_CHECKING([for Qt4 QAtomicInt]) + AC_LANG(C++) + safe_CXXFLAGS="${CXXFLAGS}" + CXXFLAGS="${QTCORE_CFLAGS} $mflag_primary" + AC_TRY_COMPILE([ + #include + ], + [ + QAtomicInt I; + I.testAndSetOrdered(0, 1); + return 0; + ], + [ + ac_have_qtcore_qatomicint=yes + AC_MSG_RESULT([yes]) + AC_DEFINE([HAVE_QTCORE_QATOMICINT], [1], [Define to 1 if the installed version of Qt4 provides QAtomicInt.]) + ], + [ + ac_have_qtcore_qatomicint=no + AC_MSG_RESULT([no]) + ]) + CXXFLAGS="${safe_CXXFLAGS}" + AC_LANG(C) +fi + +AM_CONDITIONAL([HAVE_QTCORE_QATOMICINT], [test x$ac_have_qtcore_qatomicint = xyes]) + + + # Check whether the boost library 1.35 or later has been installed. # The Boost.Threads library has undergone a major rewrite in version 1.35.0. @@ -1939,12 +1983,16 @@ AC_CONFIG_FILES([ memcheck/tests/x86/Makefile memcheck/tests/linux/Makefile memcheck/tests/darwin/Makefile + memcheck/tests/amd64-linux/Makefile memcheck/tests/x86-linux/Makefile + memcheck/tests/ppc32/Makefile + memcheck/tests/ppc64/Makefile memcheck/perf/Makefile cachegrind/Makefile cachegrind/tests/Makefile cachegrind/tests/x86/Makefile cachegrind/cg_annotate + cachegrind/cg_diff callgrind/Makefile callgrind/callgrind_annotate callgrind/callgrind_control @@ -1963,6 +2011,7 @@ AC_CONFIG_FILES([ none/tests/ppc32/Makefile none/tests/ppc64/Makefile none/tests/x86/Makefile + none/tests/arm/Makefile none/tests/linux/Makefile none/tests/darwin/Makefile none/tests/x86-linux/Makefile @@ -1977,7 +2026,16 @@ AC_CONFIG_FILES([ exp-bbv/tests/x86-linux/Makefile exp-bbv/tests/amd64-linux/Makefile exp-bbv/tests/ppc32-linux/Makefile + exp-bbv/tests/arm-linux/Makefile + exp-dhat/Makefile + exp-dhat/tests/Makefile ]) +AC_CONFIG_FILES([coregrind/link_tool_exe_linux], + [chmod +x coregrind/link_tool_exe_linux]) +AC_CONFIG_FILES([coregrind/link_tool_exe_darwin], + [chmod +x coregrind/link_tool_exe_darwin]) +AC_CONFIG_FILES([coregrind/link_tool_exe_aix5], + [chmod +x coregrind/link_tool_exe_aix5]) AC_OUTPUT cat< #include #include @@ -45,12 +55,6 @@ #include #include -#include "pub_core_debuglog.h" -#include "pub_core_vki.h" // Avoids warnings from - // pub_core_libcfile.h -#include "pub_core_libcproc.h" // For VALGRIND_LIB, VALGRIND_LAUNCHER -#include "pub_core_ume.h" - #define PATH_MAX 4096 /* POSIX refers to this a lot but I dunno @@ -116,19 +120,28 @@ static const char *select_platform(const char *clientname) ssize_t n_bytes; const char *platform = NULL; + VG_(debugLog)(2, "launcher", "selecting platform for '%s'\n", clientname); + if (strchr(clientname, '/') == NULL) clientname = find_client(clientname); + VG_(debugLog)(2, "launcher", "selecting platform for '%s'\n", clientname); + if ((fd = open(clientname, O_RDONLY)) < 0) return NULL; // barf("open(%s): %s", clientname, strerror(errno)); + VG_(debugLog)(2, "launcher", "opened '%s'\n", clientname); + n_bytes = read(fd, header, sizeof(header)); close(fd); if (n_bytes < 2) { return NULL; } + VG_(debugLog)(2, "launcher", "read %ld bytes from '%s'\n", + (long int)n_bytes, clientname); + if (header[0] == '#' && header[1] == '!') { int i = 2; char *interp = (char *)header + 2; @@ -163,6 +176,12 @@ static const char *select_platform(const char *clientname) ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { platform = "x86-linux"; } + else + if (ehdr->e_machine == EM_ARM && + (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || + ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { + platform = "arm-linux"; + } } else if (header[EI_DATA] == ELFDATA2MSB) { if (ehdr->e_machine == EM_PPC && @@ -171,6 +190,7 @@ static const char *select_platform(const char *clientname) platform = "ppc32-linux"; } } + } else if (n_bytes >= sizeof(Elf64_Ehdr) && header[EI_CLASS] == ELFCLASS64) { const Elf64_Ehdr *ehdr = (Elf64_Ehdr *)header; @@ -190,6 +210,9 @@ static const char *select_platform(const char *clientname) } } + VG_(debugLog)(2, "launcher", "selected platform '%s'\n", + platform ? platform : "unknown"); + return platform; } @@ -254,7 +277,8 @@ int main(int argc, char** argv, char** envp) if ((0==strcmp(VG_PLATFORM,"x86-linux")) || (0==strcmp(VG_PLATFORM,"amd64-linux")) || (0==strcmp(VG_PLATFORM,"ppc32-linux")) || - (0==strcmp(VG_PLATFORM,"ppc64-linux"))) + (0==strcmp(VG_PLATFORM,"ppc64-linux")) || + (0==strcmp(VG_PLATFORM,"arm-linux"))) default_platform = VG_PLATFORM; else barf("Unknown VG_PLATFORM '%s'", VG_PLATFORM); diff --git a/coregrind/link_tool_exe_aix5.in b/coregrind/link_tool_exe_aix5.in new file mode 100644 index 0000000..b909db1 --- /dev/null +++ b/coregrind/link_tool_exe_aix5.in @@ -0,0 +1,6 @@ +#! @PERL@ + +use warnings; +use strict; + +die "link_tool_exe_@VGCONF_OS@ requires implementation"; diff --git a/coregrind/link_tool_exe_darwin.in b/coregrind/link_tool_exe_darwin.in new file mode 100644 index 0000000..be1a1d9 --- /dev/null +++ b/coregrind/link_tool_exe_darwin.in @@ -0,0 +1,173 @@ +#! @PERL@ + +# This script handles linking the tool executables on Linux, +# statically and at an alternative load address. +# +# Linking statically sidesteps all sorts of complications to do with +# having two copies of the dynamic linker (valgrind's and the +# client's) coexisting in the same process. The alternative load +# address is needed because Valgrind itself will load the client at +# whatever address it specifies, which is almost invariably the +# default load address. Hence we can't allow Valgrind itself (viz, +# the tool executable) to be loaded at that address. +# +# Unfortunately there's no standard way to do 'static link at +# alternative address', so these link_tool_exe_*.in scripts handle +# the per-platform hoop-jumping. +# +# What we get passed here is: +# first arg +# the alternative load address +# all the rest of the args +# the gcc invokation to do the final link, that +# the build system would have done, left to itself +# +# We just let the script 'die' if something is wrong, rather than do +# proper error reporting. We don't expect the users to run this +# directly. It is only run as part of the build process, with +# carefully constrained inputs. +# +# +# So: what we actually do is: +# +# Look at the specified gcc invokation. Ignore all parts of it except +# the *.a, *.o and -o outfile parts. Wrap them up in a new command +# which looks (eg) as follows: +# +# (64-bit): +# +# /usr/bin/ld -static -arch x86_64 -macosx_version_min 10.5 \ +# -o memcheck-amd64-darwin -u __start -e __start \ +# -image_base 0x138000000 -stack_addr 0x13c000000 \ +# -stack_size 0x800000 \ +# memcheck_amd*.o \ +# ../coregrind/libcoregrind-amd64-darwin.a \ +# ../VEX/libvex-amd64-darwin.a +# +# (32-bit) +# +# /usr/bin/ld -static -arch i386 -macosx_version_min 10.5 \ +# -o memcheck-x86-darwin -u __start -e __start \ +# -image_base 0x38000000 -stack_addr 0x3c000000 \ +# -stack_size 0x800000 \ +# memcheck_x86*.o \ +# ../coregrind/libcoregrind-x86-darwin.a \ +# ../VEX/libvex-x86-darwin.a +# +# The addresses shown above will actually work, although "for real" we +# of course need to take it from argv[1]. In these examples the stack +# is placed 64M after the executable start. It is probably safer to +# place it 64M before the executable's start point, so the executable +# + data + bss can grow arbitrarily in future without colliding with +# the stack. +# +# There's one more twist: we need to know the word size of the +# executable for which we are linking. We need to know this because +# we must tell the linker that, by handing it either "-arch x86_64" or +# "-arch i386". Fortunately we can figure this out by scanning the +# gcc invokation, which itself must contain either "-arch x86_64" or +# "-arch i386". + +use warnings; +use strict; +# we need to be able to do 64-bit arithmetic: +use Math::BigInt; + + +# User configurable constants: how far before the exe should we +# place the stack? +my $TX_STACK_OFFSET_BEFORE_TEXT = 64 * 1024 * 1024; + +# and how big should the stack be? +my $TX_STACK_SIZE = 8 * 1024 * 1024; + + +# string -> bool +sub is_dota_or_doto($) +{ + my ($str) = @_; + if ($str =~ /.\.a$/ || $str =~ /.\.o$/) { + return 1; + } else { + return 0; + } +} + + +# expect at least: alt-load-address gcc -o foo bar.o +die "Not enough arguments" + if (($#ARGV + 1) < 5); + +my $ala = $ARGV[0]; + +# check for plausible-ish alt load address +die "Bogus alt-load address (1)" + if (length($ala) < 3 || index($ala, "0x") != 0); + +die "Bogus alt-load address (2)" + if ($ala !~ /^0x[0-9a-fA-F]+$/); + + +# get hold of the outfile name (following "-o") +my $outname = ""; + +foreach my $n (2 .. $#ARGV - 1) { + my $str = $ARGV[$n]; + if ($str eq "-o" && $outname eq "") { + $outname = $ARGV[$n + 1]; + } +} + +die "Can't find '-o outfilename' in command line" + if ($outname eq ""); + + +# get hold of the string following "-arch" +my $archstr = ""; + +foreach my $n (2 .. $#ARGV - 1) { + my $str = $ARGV[$n]; + if ($str eq "-arch" && $archstr eq "") { + $archstr = $ARGV[$n + 1]; + } +} + +die "Can't find '-arch archstr' in command line" + if ($archstr eq ""); + + +# build the command line +my $cmd = "/usr/bin/ld"; + +$cmd = "$cmd -static"; +$cmd = "$cmd -arch $archstr"; +$cmd = "$cmd -macosx_version_min 10.5"; +$cmd = "$cmd -o $outname"; +$cmd = "$cmd -u __start -e __start"; + +my $stack_addr = Math::BigInt->new( $ala ) - $TX_STACK_OFFSET_BEFORE_TEXT; +my $stack_addr_str = $stack_addr->as_hex(); +my $stack_size_str = Math::BigInt::as_hex($TX_STACK_SIZE); + +$cmd = "$cmd -image_base $ala"; +$cmd = "$cmd -stack_addr $stack_addr_str"; +$cmd = "$cmd -stack_size $stack_size_str"; + +foreach my $n (2 .. $#ARGV) { + my $str = $ARGV[$n]; + if (is_dota_or_doto($str)) { + $cmd = "$cmd $str"; + } +} + +#print "link_tool_exe_darwin: $cmd\n"; + + +# Execute the command: +my $r = system("$cmd"); + +if ($r == 0) { + exit 0; +} else { + exit 1; +} diff --git a/coregrind/link_tool_exe_linux.in b/coregrind/link_tool_exe_linux.in new file mode 100644 index 0000000..6de2562 --- /dev/null +++ b/coregrind/link_tool_exe_linux.in @@ -0,0 +1,88 @@ +#! @PERL@ + +# This script handles linking the tool executables on Linux, +# statically and at an alternative load address. +# +# Linking statically sidesteps all sorts of complications to do with +# having two copies of the dynamic linker (valgrind's and the +# client's) coexisting in the same process. The alternative load +# address is needed because Valgrind itself will load the client at +# whatever address it specifies, which is almost invariably the +# default load address. Hence we can't allow Valgrind itself (viz, +# the tool executable) to be loaded at that address. +# +# Unfortunately there's no standard way to do 'static link at +# alternative address', so these link_tool_exe_*.in scripts handle +# the per-platform hoop-jumping. +# +# What we get passed here is: +# first arg +# the alternative load address +# all the rest of the args +# the gcc invokation to do the final link, that +# the build system would have done, left to itself +# +# We just let the script 'die' if something is wrong, rather than do +# proper error reporting. We don't expect the users to run this +# directly. It is only run as part of the build process, with +# carefully constrained inputs. +# +# Linux specific complications: +# +# - need to support both old GNU ld and gold: use -Ttext= to +# set the text segment address. +# +# - need to pass --build-id=none (that is, -Wl,--build-id=none to +# gcc) if it accepts it, to ensure the linker doesn't add a +# notes section which ends up at the default load address and +# so defeats our attempts to keep that address clear for the +# client. However, older linkers don't support this flag, so it +# is tested for by configure.in and is shipped to us as part of +# argv[2 ..]. +# +# +# So: what we actually do: +# +# pass the specified command to the linker as-is, except, add +# "-static" and "-Ttext=" to it. +# + +use warnings; +use strict; + +# expect at least: alt-load-address gcc -o foo bar.o +die "Not enough arguments" + if (($#ARGV + 1) < 5); + +my $ala = $ARGV[0]; + +# check for plausible-ish alt load address +die "Bogus alt-load address" + if (length($ala) < 3 || index($ala, "0x") != 0); + +# The cc invokation to do the final link +my $cc = $ARGV[1]; + +# and the 'restargs' are argv[2 ..] + +# so, build up the complete command here: +# 'cc' -static -Ttext='ala' 'restargs' + +my $cmd="$cc -static -Wl,-Ttext=$ala"; + +# Add the rest of the parameters +foreach my $n (2 .. $#ARGV) { + $cmd = "$cmd $ARGV[$n]"; +} + +#print "link_tool_exe_linux: $cmd\n"; + + +# Execute the command: +my $r = system("$cmd"); + +if ($r == 0) { + exit 0; +} else { + exit 1; +} diff --git a/coregrind/m_aspacehl.c b/coregrind/m_aspacehl.c index 23a6545..7193116 100644 --- a/coregrind/m_aspacehl.c +++ b/coregrind/m_aspacehl.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 Julian Seward + Copyright (C) 2006-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_aspacemgr/aspacemgr-aix5.c b/coregrind/m_aspacemgr/aspacemgr-aix5.c index d07e04e..aa37709 100644 --- a/coregrind/m_aspacemgr/aspacemgr-aix5.c +++ b/coregrind/m_aspacemgr/aspacemgr-aix5.c @@ -10,7 +10,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_aspacemgr/aspacemgr-common.c b/coregrind/m_aspacemgr/aspacemgr-common.c index 03331d1..3d59965 100644 --- a/coregrind/m_aspacemgr/aspacemgr-common.c +++ b/coregrind/m_aspacemgr/aspacemgr-common.c @@ -9,7 +9,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -38,6 +38,7 @@ #include "priv_aspacemgr.h" #include "pub_core_libcassert.h" +#include "config.h" /*-----------------------------------------------------------------*/ @@ -152,7 +153,8 @@ SysRes VG_(am_do_mmap_NO_NOTIFY)( Addr start, SizeT length, UInt prot, { SysRes res; aspacem_assert(VG_IS_PAGE_ALIGNED(offset)); -# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) +# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ + || defined(VGP_arm_linux) /* mmap2 uses 4096 chunks even if actual page size is bigger. */ aspacem_assert((offset % 4096) == 0); res = VG_(do_syscall6)(__NR_mmap2, (UWord)start, length, @@ -484,15 +486,18 @@ VgStack* VG_(am_alloc_VgStack)( /*OUT*/Addr* initial_sp ) /* Figure out how many bytes of the stack's active area have not been used. Used for estimating if we are close to overflowing it. */ -Int VG_(am_get_VgStack_unused_szB)( VgStack* stack ) +SizeT VG_(am_get_VgStack_unused_szB)( VgStack* stack, SizeT limit ) { - Int i; + SizeT i; UInt* p; p = (UInt*)&stack->bytes[VG_STACK_GUARD_SZB]; - for (i = 0; i < VG_STACK_ACTIVE_SZB/sizeof(UInt); i++) + for (i = 0; i < VG_STACK_ACTIVE_SZB/sizeof(UInt); i++) { if (p[i] != 0xDEADBEEF) break; + if (i * sizeof(UInt) >= limit) + break; + } return i * sizeof(UInt); } diff --git a/coregrind/m_aspacemgr/aspacemgr-linux.c b/coregrind/m_aspacemgr/aspacemgr-linux.c index 51f492d..772c1b8 100644 --- a/coregrind/m_aspacemgr/aspacemgr-linux.c +++ b/coregrind/m_aspacemgr/aspacemgr-linux.c @@ -10,7 +10,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -40,6 +40,7 @@ ************************************************************* */ #include "priv_aspacemgr.h" +#include "config.h" /* Note: many of the exported functions implemented below are @@ -337,6 +338,22 @@ static void parse_procselfmaps ( void (*record_gap)( Addr addr, SizeT len ) ); +/* ----- Hacks to do with the "commpage" on arm-linux ----- */ +/* Not that I have anything against the commpage per se. It's just + that it's not listed in /proc/self/maps, which is a royal PITA -- + we have to fake it up, in parse_procselfmaps. + + But note also bug 254556 comment #2: this is now fixed in newer + kernels -- it is listed as a "[vectors]" entry. Presumably the + fake entry made here duplicates the [vectors] entry, and so, if at + some point in the future, we can stop supporting buggy kernels, + then this kludge can be removed entirely, since the procmap parser + below will read that entry in the normal way. */ +#if defined(VGP_arm_linux) +# define ARM_LINUX_FAKE_COMMPAGE_START 0xFFFF0000 +# define ARM_LINUX_FAKE_COMMPAGE_END1 0xFFFF1000 +#endif + /*-----------------------------------------------------------------*/ /*--- ---*/ @@ -1539,11 +1556,27 @@ static void read_maps_callback ( Addr addr, SizeT len, UInt prot, seg.kind = SkAnonV; if (dev != 0 && ino != 0) seg.kind = SkFileV; -#if defined(VGO_darwin) + +# if defined(VGO_darwin) // GrP fixme no dev/ino on darwin if (offset != 0) - seg.kind = SkFileV; -#endif + seg.kind = SkFileV; +# endif // defined(VGO_darwin) + +# if defined(VGP_arm_linux) + /* The standard handling of entries read from /proc/self/maps will + cause the faked up commpage segment to have type SkAnonV, which + is a problem because it contains code we want the client to + execute, and so later m_translate will segfault the client when + it tries to go in there. Hence change the ownership of it here + to the client (SkAnonC). The least-worst kludge I could think + of. */ + if (addr == ARM_LINUX_FAKE_COMMPAGE_START + && addr + len == ARM_LINUX_FAKE_COMMPAGE_END1 + && seg.kind == SkAnonV) + seg.kind = SkAnonC; +# endif // defined(VGP_arm_linux) + if (filename) seg.fnIdx = allocate_segname( filename ); @@ -1707,6 +1740,15 @@ Addr VG_(am_startup) ( Addr sp_at_startup ) VG_(debugLog)(2, "aspacem", "Reading /proc/self/maps\n"); parse_procselfmaps( read_maps_callback, NULL ); + /* NB: on arm-linux, parse_procselfmaps automagically kludges up + (iow, hands to its callbacks) a description of the ARM Commpage, + since that's not listed in /proc/self/maps (kernel bug IMO). We + have to fake up its existence in parse_procselfmaps and not + merely add it here as an extra segment, because doing the latter + causes sync checking to fail: we see we have an extra segment in + the segments array, which isn't listed in /proc/self/maps. + Hence we must make it appear that /proc/self/maps contained this + segment all along. Sigh. */ VG_(am_show_nsegments)(2, "With contents of /proc/self/maps"); @@ -3012,7 +3054,7 @@ Bool VG_(am_relocate_nooverlap_client)( /*OUT*/Bool* need_discard, #endif // HAVE_MREMAP -#if defined(VGO_LINUX) && HAVE_PROC +#if defined(VGO_linux) /*-----------------------------------------------------------------*/ /*--- ---*/ @@ -3023,6 +3065,8 @@ Bool VG_(am_relocate_nooverlap_client)( /*OUT*/Bool* need_discard, /*--- ---*/ /*-----------------------------------------------------------------*/ +/*------BEGIN-procmaps-parser-for-Linux--------------------------*/ + /* Size of a smallish table used to read /proc/self/map entries. */ #define M_PROCMAP_BUF 100000 @@ -3307,10 +3351,37 @@ static void parse_procselfmaps ( gapStart = endPlusOne; } +# if defined(VGP_arm_linux) + /* ARM puts code at the end of memory that contains processor + specific stuff (cmpxchg, getting the thread local storage, etc.) + This isn't specified in /proc/self/maps, so do it here. This + kludgery causes the view of memory, as presented to + record_gap/record_mapping, to actually reflect reality. IMO + (JRS, 2010-Jan-03) the fact that /proc/.../maps does not list + the commpage should be regarded as a bug in the kernel. */ + { const Addr commpage_start = ARM_LINUX_FAKE_COMMPAGE_START; + const Addr commpage_end1 = ARM_LINUX_FAKE_COMMPAGE_END1; + if (gapStart < commpage_start) { + if (record_gap) + (*record_gap)( gapStart, commpage_start - gapStart ); + if (record_mapping) + (*record_mapping)( commpage_start, commpage_end1 - commpage_start, + VKI_PROT_READ|VKI_PROT_EXEC, + 0/*dev*/, 0/*ino*/, 0/*foffset*/, + NULL); + gapStart = commpage_end1; + } + } +# endif + if (record_gap && gapStart < Addr_MAX) (*record_gap) ( gapStart, Addr_MAX - gapStart + 1 ); } +/*------END-procmaps-parser-for-Linux----------------------------*/ + +/*------BEGIN-procmaps-parser-for-Darwin-------------------------*/ + #elif defined(VGO_darwin) #include #include @@ -3375,10 +3446,11 @@ static void parse_procselfmaps ( (*record_gap)(last, (Addr)-1 - last); } -Bool css_overflowed; -ChangedSeg* css_local; -Int css_size_local; -Int css_used_local; +// Urr. So much for thread safety. +static Bool css_overflowed; +static ChangedSeg* css_local; +static Int css_size_local; +static Int css_used_local; static void add_mapping_callback(Addr addr, SizeT len, UInt prot, ULong dev, ULong ino, Off64T offset, @@ -3440,8 +3512,8 @@ static void add_mapping_callback(Addr addr, SizeT len, UInt prot, # endif if (seg_prot != prot) { if (VG_(clo_trace_syscalls)) - VG_(debugLog)(0,"aspacem","\nregion %p..%p permission " - "mismatch (kernel %x, V %x)", + VG_(debugLog)(0,"aspacem","region %p..%p permission " + "mismatch (kernel %x, V %x)\n", (void*)nsegments[i].start, (void*)(nsegments[i].end+1), prot, seg_prot); } @@ -3599,9 +3671,6 @@ static void parse_procselfmaps ( # error "Unknown OS!" #endif - -#endif // defined(VGO_linux) || defined(VGO_darwin) - /*--------------------------------------------------------------------*/ /*--- end ---*/ /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_aspacemgr/priv_aspacemgr.h b/coregrind/m_aspacemgr/priv_aspacemgr.h index 04974bb..a6d993a 100644 --- a/coregrind/m_aspacemgr/priv_aspacemgr.h +++ b/coregrind/m_aspacemgr/priv_aspacemgr.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_clientstate.c b/coregrind/m_clientstate.c index 180046e..d6dc7b2 100644 --- a/coregrind/m_clientstate.c +++ b/coregrind/m_clientstate.c @@ -9,7 +9,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -75,7 +75,7 @@ Int VG_(args_for_valgrind_noexecpass) = 0; /* The name of the client executable, as specified on the command line. */ -HChar* VG_(args_the_exename) = NULL; +const HChar* VG_(args_the_exename) = NULL; // Client's original rlimit data and rlimit stack struct vki_rlimit VG_(client_rlimit_data); diff --git a/coregrind/m_commandline.c b/coregrind/m_commandline.c index 327560a..161e571 100644 --- a/coregrind/m_commandline.c +++ b/coregrind/m_commandline.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_coredump/coredump-elf.c b/coregrind/m_coredump/coredump-elf.c index 3368feb..8b1ced8 100644 --- a/coregrind/m_coredump/coredump-elf.c +++ b/coregrind/m_coredump/coredump-elf.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -337,7 +337,6 @@ static void fill_prstatus(const ThreadState *tst, regs->rflags = LibVEX_GuestAMD64_get_rflags( &((ThreadArchState*)arch)->vex ); regs->rsp = arch->vex.guest_RSP; regs->rip = arch->vex.guest_RIP; - regs->rbx = arch->vex.guest_RBX; regs->rcx = arch->vex.guest_RCX; regs->rdx = arch->vex.guest_RDX; @@ -374,6 +373,25 @@ static void fill_prstatus(const ThreadState *tst, regs->fs = arch->vex.guest_FS; regs->gs = arch->vex.guest_GS; +#elif defined(VGP_arm_linux) + regs->ARM_r0 = arch->vex.guest_R0; + regs->ARM_r1 = arch->vex.guest_R1; + regs->ARM_r2 = arch->vex.guest_R2; + regs->ARM_r3 = arch->vex.guest_R3; + regs->ARM_r4 = arch->vex.guest_R4; + regs->ARM_r5 = arch->vex.guest_R5; + regs->ARM_r6 = arch->vex.guest_R6; + regs->ARM_r7 = arch->vex.guest_R7; + regs->ARM_r8 = arch->vex.guest_R8; + regs->ARM_r9 = arch->vex.guest_R9; + regs->ARM_r10 = arch->vex.guest_R10; + regs->ARM_fp = arch->vex.guest_R11; + regs->ARM_ip = arch->vex.guest_R12; + regs->ARM_sp = arch->vex.guest_R13; + regs->ARM_lr = arch->vex.guest_R14; + regs->ARM_pc = arch->vex.guest_R15T; + regs->ARM_cpsr = LibVEX_GuestARM_get_cpsr( &((ThreadArchState*)arch)->vex ); + #else # error Unknown ELF platform #endif @@ -444,7 +462,6 @@ static void fill_fpu(const ThreadState *tst, vki_elf_fpregset_t *fpu) # undef DO #elif defined(VGP_x86_freebsd) - #elif defined(VGP_amd64_freebsd) # define DO(n) VG_(memcpy)(fpu->xmm_space + n * 4, &arch->vex.guest_XMM##n, sizeof(arch->vex.guest_XMM##n)) @@ -452,6 +469,9 @@ static void fill_fpu(const ThreadState *tst, vki_elf_fpregset_t *fpu) DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15); # undef DO +#elif defined(VGP_arm_linux) + // umm ... + #else # error Unknown ELF platform #endif diff --git a/coregrind/m_coredump/coredump-xcoff.c b/coregrind/m_coredump/coredump-xcoff.c index 34e86a6..889e61a 100644 --- a/coregrind/m_coredump/coredump-xcoff.c +++ b/coregrind/m_coredump/coredump-xcoff.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_cpuid.S b/coregrind/m_cpuid.S index d7dcff3..42df343 100644 --- a/coregrind/m_cpuid.S +++ b/coregrind/m_cpuid.S @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -33,8 +33,9 @@ /* Bool VG_(has_cpuid)(void) */ -.globl VG_(has_cpuid) #if defined(VGA_x86) +.text +.globl VG_(has_cpuid) VG_(has_cpuid): pushl %ebp movl %esp, %ebp @@ -57,6 +58,8 @@ popl %ebp ret #elif defined(VGA_amd64) +.text +.globl VG_(has_cpuid) VG_(has_cpuid): movq $1, %rax ret @@ -66,8 +69,9 @@ void VG_(cpuid)(UInt eax, UInt* eax_ret, UInt* ebx_ret, UInt* ecx_ret, UInt* edx_ret) */ -.globl VG_(cpuid) #if defined(VGA_x86) +.text +.globl VG_(cpuid) VG_(cpuid): pushl %ebp movl %esp, %ebp @@ -107,6 +111,8 @@ popl %ebp ret #elif defined(VGA_amd64) +.text +.globl VG_(cpuid) VG_(cpuid): pushq %rbp movq %rsp, %rbp @@ -143,7 +149,7 @@ ret #endif -#if defined(VGO_linux) +#if defined(VGP_x86_linux) || defined(VGP_amd64_linux) /* Let the linker know we don't need an executable stack */ .section .note.GNU-stack,"",@progbits #endif diff --git a/coregrind/m_debugger.c b/coregrind/m_debugger.c index ec3c5b0..7d22b20 100644 --- a/coregrind/m_debugger.c +++ b/coregrind/m_debugger.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -205,6 +205,31 @@ static Int ptrace_setregs(Int pid, VexGuestArchState* vex) (void*)(long)LibVEX_GuestPPC64_get_XER(vex)); return rc; +#elif defined(VGP_arm_linux) + struct vki_user_regs_struct uregs; + VG_(memset)(&uregs, 0, sizeof(uregs)); + uregs.ARM_r0 = vex->guest_R0; + uregs.ARM_r1 = vex->guest_R1; + uregs.ARM_r2 = vex->guest_R2; + uregs.ARM_r3 = vex->guest_R3; + uregs.ARM_r4 = vex->guest_R4; + uregs.ARM_r5 = vex->guest_R5; + uregs.ARM_r6 = vex->guest_R6; + uregs.ARM_r7 = vex->guest_R7; + uregs.ARM_r8 = vex->guest_R8; + uregs.ARM_r9 = vex->guest_R9; + uregs.ARM_r10 = vex->guest_R10; + uregs.ARM_fp = vex->guest_R11; + uregs.ARM_ip = vex->guest_R12; + uregs.ARM_sp = vex->guest_R13; + uregs.ARM_lr = vex->guest_R14; + // Remove the T bit from the bottom of R15T. It will get shipped + // over in CPSR.T instead, since LibVEX_GuestARM_get_cpsr copies + // it from R15T[0]. + uregs.ARM_pc = vex->guest_R15T & 0xFFFFFFFE; + uregs.ARM_cpsr = LibVEX_GuestARM_get_cpsr(vex); + return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs); + #elif defined(VGP_ppc32_aix5) I_die_here; diff --git a/coregrind/m_debuginfo/d3basics.c b/coregrind/m_debuginfo/d3basics.c index 9c23bad..31717cf 100644 --- a/coregrind/m_debuginfo/d3basics.c +++ b/coregrind/m_debuginfo/d3basics.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks LLP + Copyright (C) 2008-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -124,6 +124,10 @@ HChar* ML_(pp_DW_TAG) ( DW_TAG tag ) case DW_TAG_imported_unit: return "DW_TAG_imported_unit"; case DW_TAG_condition: return "DW_TAG_condition"; case DW_TAG_shared_type: return "DW_TAG_shared_type"; + /* DWARF 4. */ + case DW_TAG_type_unit: return "DW_TAG_type_unit"; + case DW_TAG_rvalue_reference_type: return "DW_TAG_rvalue_reference_type"; + case DW_TAG_template_alias: return "DW_TAG_template_alias"; /* SGI/MIPS Extensions. */ case DW_TAG_MIPS_loop: return "DW_TAG_MIPS_loop"; /* HP extensions. See: @@ -172,6 +176,10 @@ HChar* ML_(pp_DW_FORM) ( DW_FORM form ) case DW_FORM_ref8: return "DW_FORM_ref8"; case DW_FORM_ref_udata: return "DW_FORM_ref_udata"; case DW_FORM_indirect: return "DW_FORM_indirect"; + case DW_FORM_sec_offset:return "DW_FORM_sec_offset"; + case DW_FORM_exprloc: return "DW_FORM_exprloc"; + case DW_FORM_flag_present:return "DW_FORM_flag_present"; + case DW_FORM_ref_sig8: return "DW_FORM_ref_sig8"; default: return "DW_FORM_???"; } } @@ -269,6 +277,13 @@ HChar* ML_(pp_DW_AT) ( DW_AT attr ) case DW_AT_elemental: return "DW_AT_elemental"; case DW_AT_pure: return "DW_AT_pure"; case DW_AT_recursive: return "DW_AT_recursive"; + /* DWARF 4 values. */ + case DW_AT_signature: return "DW_AT_signature"; + case DW_AT_main_subprogram: return "DW_AT_main_subprogram"; + case DW_AT_data_bit_offset: return "DW_AT_data_bit_offset"; + case DW_AT_const_expr: return "DW_AT_const_expr"; + case DW_AT_enum_class: return "DW_AT_enum_class"; + case DW_AT_linkage_name: return "DW_AT_linkage_name"; /* SGI/MIPS extensions. */ /* case DW_AT_MIPS_fde: return "DW_AT_MIPS_fde"; */ /* DW_AT_MIPS_fde == DW_AT_HP_unmodifiable */ @@ -387,12 +402,11 @@ static Bool get_Dwarf_Reg( /*OUT*/Addr* a, Word regno, RegSummary* regs ) if (regno == 7/*RSP*/) { *a = regs->sp; return True; } # elif defined(VGP_ppc32_linux) if (regno == 1/*SP*/) { *a = regs->sp; return True; } - if (regno == 31) return False; - vg_assert(0); # elif defined(VGP_ppc64_linux) if (regno == 1/*SP*/) { *a = regs->sp; return True; } - if (regno == 31) return False; - vg_assert(0); +# elif defined(VGP_arm_linux) + if (regno == 13) { *a = regs->sp; return True; } + if (regno == 11) { *a = regs->fp; return True; } # elif defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5) vg_assert(0); /* this function should never be called */ # else @@ -443,7 +457,7 @@ static Bool bias_address( Addr* a, const DebugInfo* di ) /* Evaluate a standard DWARF3 expression. See detailed description in - priv_d3basics.h. */ + priv_d3basics.h. Doesn't handle DW_OP_piece/DW_OP_bit_piece yet. */ GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB, GExpr* fbGX, RegSummary* regs, const DebugInfo* di, @@ -482,8 +496,8 @@ GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB, Addr stack[N_EXPR_STACK]; /* stack of addresses, as per D3 spec */ GXResult fbval, res; Addr a1; - Word sw1; - UWord uw1; + Word sw1, sw2; + UWord uw1, uw2; Bool ok; sp = -1; @@ -568,12 +582,15 @@ GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB, switch (fbval.kind) { case GXR_Failure: return fbval; /* propagate failure */ - case GXR_Value: + case GXR_Addr: a1 = fbval.word; break; /* use as-is */ case GXR_RegNo: ok = get_Dwarf_Reg( &a1, fbval.word, regs ); if (!ok) return fbval; /* propagate failure */ break; + case GXR_Value: + FAIL("evaluate_Dwarf3_Expr: DW_OP_{implicit,stack}_value " + "in DW_AT_frame_base"); default: vg_assert(0); } @@ -599,11 +616,23 @@ GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB, a1 += sw1; PUSH( a1 ); break; + case DW_OP_bregx: + if (!regs) + FAIL("evaluate_Dwarf3_Expr: DW_OP_bregx but no reg info"); + a1 = 0; + uw1 = (UWord)read_leb128U( &expr ); + if (!get_Dwarf_Reg( &a1, uw1, regs )) + FAIL("evaluate_Dwarf3_Expr: unhandled DW_OP_bregx reg value"); + sw1 = (Word)read_leb128S( &expr ); + a1 += sw1; + PUSH( a1 ); + break; /* As per comment on DW_OP_breg*, the following denote that the value in question is in a register, not in memory. So we simply return failure. (iow, the expression is malformed). */ case DW_OP_reg0 ... DW_OP_reg31: + case DW_OP_regx: FAIL("evaluate_Dwarf3_Expr: DW_OP_reg* " "whilst evaluating for a value"); break; @@ -637,6 +666,241 @@ GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB, "address not valid for client"); } break; + case DW_OP_deref_size: + POP(uw1); + uw2 = *expr++; + if (VG_(am_is_valid_for_client)( (Addr)uw1, uw2, + VKI_PROT_READ )) { + switch (uw2) { + case 1: uw1 = *(UChar*)uw1; break; + case 2: uw1 = *(UShort*)uw1; break; + case 4: uw1 = *(UInt*)uw1; break; + case 8: uw1 = *(ULong*)uw1; break; + default: + FAIL("warning: evaluate_Dwarf3_Expr: unhandled " + "DW_OP_deref_size size"); + } + PUSH(uw1); + } else { + FAIL("warning: evaluate_Dwarf3_Expr: DW_OP_deref_size: " + "address not valid for client"); + } + break; + case DW_OP_lit0 ... DW_OP_lit31: + PUSH(opcode - DW_OP_lit0); + break; + case DW_OP_const1u: + uw1 = *expr++; + PUSH(uw1); + break; + case DW_OP_const2u: + uw1 = *(UShort *)expr; + expr += 2; + PUSH(uw1); + break; + case DW_OP_const4u: + uw1 = *(UInt *)expr; + expr += 4; + PUSH(uw1); + break; + case DW_OP_const8u: + uw1 = *(ULong *)expr; + expr += 8; + PUSH(uw1); + break; + case DW_OP_constu: + uw1 = read_leb128U( &expr ); + PUSH(uw1); + break; + case DW_OP_const1s: + uw1 = *(Char *)expr; + expr++; + PUSH(uw1); + break; + case DW_OP_const2s: + uw1 = *(Short *)expr; + expr += 2; + PUSH(uw1); + break; + case DW_OP_const4s: + uw1 = *(Int *)expr; + expr += 4; + PUSH(uw1); + break; + case DW_OP_const8s: + uw1 = *(Long *)expr; + expr += 8; + PUSH(uw1); + break; + case DW_OP_consts: + uw1 = read_leb128S( &expr ); + PUSH(uw1); + break; + case DW_OP_dup: + POP(uw1); + PUSH(uw1); + PUSH(uw1); + break; + case DW_OP_drop: + POP(uw1); + break; + case DW_OP_over: + uw1 = 1; + goto do_pick; + case DW_OP_pick: + uw1 = *expr++; + do_pick: + if (sp < (Int)uw1) + FAIL("evaluate_Dwarf3_Expr: stack underflow"); + uw1 = stack[sp - uw1]; + PUSH(uw1); + break; + case DW_OP_swap: + if (sp < 1) + FAIL("evaluate_Dwarf3_Expr: stack underflow"); + uw1 = stack[sp]; + stack[sp] = stack[sp - 1]; + stack[sp - 1] = uw1; + break; + case DW_OP_rot: + if (sp < 2) + FAIL("evaluate_Dwarf3_Expr: stack underflow"); + uw1 = stack[sp]; + stack[sp] = stack[sp - 1]; + stack[sp - 1] = stack[sp - 2]; + stack[sp - 2] = uw1; + break; + case DW_OP_abs: + POP(sw1); + if (sw1 < 0) + sw1 = -sw1; + PUSH(sw1); + break; + case DW_OP_div: + POP(sw2); + if (sw2 == 0) + FAIL("evaluate_Dwarf3_Expr: division by zero"); + POP(sw1); + sw1 /= sw2; + PUSH(sw1); + break; + case DW_OP_mod: + POP(uw2); + if (uw2 == 0) + FAIL("evaluate_Dwarf3_Expr: division by zero"); + POP(uw1); + uw1 %= uw2; + PUSH(uw1); + break; +#define BINARY(name, op, s) \ + case DW_OP_##name: \ + POP(s##w2); \ + POP(s##w1); \ + s##w1 = s##w1 op s##w2; \ + PUSH(s##w1); \ + break +#define UNARY(name, op, s) \ + case DW_OP_##name: \ + POP(s##w1); \ + s##w1 = op s##w1; \ + PUSH(s##w1); \ + break + BINARY (and, &, u); + BINARY (minus, -, u); + BINARY (mul, *, u); + UNARY (neg, -, u); + UNARY (not, ~, u); + BINARY (or, |, u); + BINARY (plus, +, u); + BINARY (shl, <<, u); + BINARY (shr, >>, u); + BINARY (shra, >>, s); + BINARY (xor, ^, u); + BINARY (le, <=, s); + BINARY (lt, <, s); + BINARY (ge, >=, s); + BINARY (gt, >, s); + BINARY (ne, !=, u); + BINARY (eq, ==, u); +#undef UNARY +#undef BINARY + case DW_OP_skip: + sw1 = *(Short *)expr; + expr += 2; + if (expr + sw1 < limit - exprszB) + FAIL("evaluate_Dwarf3_Expr: DW_OP_skip before start of expr"); + if (expr + sw1 >= limit) + FAIL("evaluate_Dwarf3_Expr: DW_OP_skip after end of expr"); + expr += sw1; + break; + case DW_OP_bra: + sw1 = *(Short *)expr; + expr += 2; + if (expr + sw1 < limit - exprszB) + FAIL("evaluate_Dwarf3_Expr: DW_OP_bra before start of expr"); + if (expr + sw1 >= limit) + FAIL("evaluate_Dwarf3_Expr: DW_OP_bra after end of expr"); + POP(uw1); + if (uw1) + expr += sw1; + break; + case DW_OP_nop: + break; + case DW_OP_call_frame_cfa: + if (!regs) + FAIL("evaluate_Dwarf3_Expr: " + "DW_OP_call_frame_cfa but no reg info"); +#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) + /* Valgrind on ppc32/ppc64 currently doesn't use unwind info. */ + uw1 = *(Addr *)(regs->sp); +#else + uw1 = ML_(get_CFA)(regs->ip, regs->sp, regs->fp, 0, ~(UWord) 0); +#endif + /* we expect this to fail on arm-linux, since ML_(get_CFA) + always returns zero at present. */ + if (!uw1) + FAIL("evaluate_Dwarf3_Expr: Could not resolve " + "DW_OP_call_frame_cfa"); + PUSH(uw1); + break; + case DW_OP_implicit_value: + sw1 = (Word)read_leb128S( &expr ); + uw1 = 0; + switch (sw1) { + case 1: + uw1 = *(UChar *)expr; + expr += 1; + break; + case 2: + uw1 = *(UShort *)expr; + expr += 2; + break; + case 4: + uw1 = *(UInt *)expr; + expr += 4; + break; + case 8: + uw1 = *(ULong *)expr; + expr += 8; + break; + default: + FAIL("evaluate_Dwarf3_Expr: Unhandled " + "DW_OP_implicit_value size"); + } + if (expr != limit) + FAIL("evaluate_Dwarf3_Expr: DW_OP_implicit_value " + "does not terminate expression"); + res.word = uw1; + res.kind = GXR_Value; + return res; + case DW_OP_stack_value: + POP (uw1); + res.word = uw1; + res.kind = GXR_Value; + if (expr != limit) + FAIL("evaluate_Dwarf3_Expr: DW_OP_stack_value " + "does not terminate expression"); + break; default: if (!VG_(clo_xml)) VG_(message)(Vg_DebugMsg, @@ -650,7 +914,7 @@ GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB, vg_assert(sp >= 0 && sp < N_EXPR_STACK); res.word = stack[sp]; - res.kind = GXR_Value; + res.kind = GXR_Addr; return res; # undef POP @@ -829,12 +1093,15 @@ GXResult ML_(evaluate_trivial_GX)( GExpr* gx, const DebugInfo* di ) if (!badness) badness = "trivial GExpr denotes register (2)"; } - else { + else if (0) { VG_(printf)(" ML_(evaluate_trivial_GX): unhandled:\n "); ML_(pp_GX)( gx ); VG_(printf)("\n"); tl_assert(0); } + else + if (!badness) + badness = "non-trivial GExpr"; VG_(addToXA)( results, &thisResult ); @@ -884,7 +1151,7 @@ GXResult ML_(evaluate_trivial_GX)( GExpr* gx, const DebugInfo* di ) /* Well, we have success. All subexpressions evaluated, and they all agree. Hurrah. */ - res.kind = GXR_Value; + res.kind = GXR_Addr; res.word = (UWord)mul->ul; /* NB: narrowing from ULong */ VG_(deleteXA)( results ); return res; @@ -896,6 +1163,8 @@ void ML_(pp_GXResult) ( GXResult res ) switch (res.kind) { case GXR_Failure: VG_(printf)("GXR_Failure(%s)", (HChar*)res.word); break; + case GXR_Addr: + VG_(printf)("GXR_Addr(0x%lx)", res.word); break; case GXR_Value: VG_(printf)("GXR_Value(0x%lx)", res.word); break; case GXR_RegNo: diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c index 845e329..db4545d 100644 --- a/coregrind/m_debuginfo/debuginfo.c +++ b/coregrind/m_debuginfo/debuginfo.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -38,6 +38,7 @@ #include "pub_core_libcassert.h" #include "pub_core_libcprint.h" #include "pub_core_libcfile.h" +#include "pub_core_libcproc.h" // VG_(getenv) #include "pub_core_seqmatch.h" #include "pub_core_options.h" #include "pub_core_redir.h" // VG_(redir_notify_{new,delete}_SegInfo) @@ -609,7 +610,7 @@ ULong VG_(di_notify_mmap)( Addr a, Bool allow_SkFileV ) DebugInfo* di; ULong di_handle; SysRes fd; - Int nread; + Int nread, oflags; HChar buf1k[1024]; Bool debug = False; SysRes statres; @@ -712,7 +713,7 @@ ULong VG_(di_notify_mmap)( Addr a, Bool allow_SkFileV ) # if defined(VGA_x86) || defined(VGA_ppc32) is_rx_map = seg->hasR && seg->hasX; is_rw_map = seg->hasR && seg->hasW; -# elif defined(VGA_amd64) || defined(VGA_ppc64) +# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm) is_rx_map = seg->hasR && seg->hasX && !seg->hasW; is_rw_map = seg->hasR && seg->hasW && !seg->hasX; # else @@ -730,7 +731,11 @@ ULong VG_(di_notify_mmap)( Addr a, Bool allow_SkFileV ) /* Peer at the first few bytes of the file, to see if it is an ELF */ /* object file. Ignore the file if we do not have read permission. */ VG_(memset)(buf1k, 0, sizeof(buf1k)); - fd = VG_(open)( filename, VKI_O_RDONLY, 0 ); + oflags = VKI_O_RDONLY; +# if defined(VKI_O_LARGEFILE) + oflags |= VKI_O_LARGEFILE; +# endif + fd = VG_(open)( filename, oflags, 0 ); if (sr_isError(fd)) { if (sr_Err(fd) != VKI_EACCES) { DebugInfo fake_di; @@ -900,7 +905,7 @@ void VG_(di_notify_pdb_debuginfo)( Int fd_obj, Addr avma_obj, SizeT total_size, PtrdiffT unknown_purpose__reloc ) { - Int r, sz_exename; + Int i, r, sz_exename; ULong obj_mtime, pdb_mtime; Char exename[VKI_PATH_MAX]; Char* pdbname = NULL; @@ -943,27 +948,86 @@ void VG_(di_notify_pdb_debuginfo)( Int fd_obj, Addr avma_obj, VG_(message)(Vg_UserMsg, "LOAD_PDB_DEBUGINFO: objname: %s\n", exename); } - /* Try to find a matching PDB file from which to read debuginfo. - Windows PE files have symbol tables and line number information, - but MSVC doesn't seem to use them. */ - /* Why +5 ? Because in the worst case, we could find a dot as the - last character of pdbname, and we'd then put "pdb" right after - it, hence extending it a bit. */ - pdbname = ML_(dinfo_zalloc)("di.debuginfo.lpd1", sz_exename+5); - VG_(strcpy)(pdbname, exename); - vg_assert(pdbname[sz_exename+5-1] == 0); - dot = VG_(strrchr)(pdbname, '.'); - if (!dot) - goto out; /* there's no dot in the exe's name ?! */ - if (dot[1] == 0) - goto out; /* hmm, path ends in "." */ - - if ('A' <= dot[1] && dot[1] <= 'Z') - VG_(strcpy)(dot, ".PDB"); - else - VG_(strcpy)(dot, ".pdb"); + /* Try to get the PDB file name from the executable. */ + pdbname = ML_(find_name_of_pdb_file)(exename); + if (pdbname) { + vg_assert(VG_(strlen)(pdbname) >= 5); /* 5 = strlen("X.pdb") */ + /* So we successfully extracted a name from the PE file. But it's + likely to be of the form + e:\foo\bar\xyzzy\wibble.pdb + and we need to change it into something we can actually open + in Wine-world, which basically means turning it into + $HOME/.wine/drive_e/foo/bar/xyzzy/wibble.pdb + We also take into account $WINEPREFIX, if it is set. + For the moment, if the name isn't fully qualified, just forget it + (we'd have to root around to find where the pdb actually is) + */ + /* Change all the backslashes to forward slashes */ + for (i = 0; pdbname[i]; i++) { + if (pdbname[i] == '\\') + pdbname[i] = '/'; + } + Bool is_quald + = ('a' <= VG_(tolower)(pdbname[0]) && VG_(tolower)(pdbname[0]) <= 'z') + && pdbname[1] == ':' + && pdbname[2] == '/'; + HChar* home = VG_(getenv)("HOME"); + HChar* wpfx = VG_(getenv)("WINEPREFIX"); + if (is_quald && wpfx) { + /* Change e:/foo/bar/xyzzy/wibble.pdb + to $WINEPREFIX/drive_e/foo/bar/xyzzy/wibble.pdb + */ + Int mashedSzB = VG_(strlen)(pdbname) + VG_(strlen)(wpfx) + 50/*misc*/; + HChar* mashed = ML_(dinfo_zalloc)("di.debuginfo.dnpdi.1", mashedSzB); + VG_(sprintf)(mashed, "%s/drive_%c%s", + wpfx, pdbname[0], &pdbname[2]); + vg_assert(mashed[mashedSzB-1] == 0); + ML_(dinfo_free)(pdbname); + pdbname = mashed; + } + else if (is_quald && home && !wpfx) { + /* Change e:/foo/bar/xyzzy/wibble.pdb + to $HOME/.wine/drive_e/foo/bar/xyzzy/wibble.pdb + */ + Int mashedSzB = VG_(strlen)(pdbname) + VG_(strlen)(home) + 50/*misc*/; + HChar* mashed = ML_(dinfo_zalloc)("di.debuginfo.dnpdi.2", mashedSzB); + VG_(sprintf)(mashed, "%s/.wine/drive_%c%s", + home, pdbname[0], &pdbname[2]); + vg_assert(mashed[mashedSzB-1] == 0); + ML_(dinfo_free)(pdbname); + pdbname = mashed; + } else { + /* It's not a fully qualified path, or neither $HOME nor $WINE + are set (strange). Give up. */ + ML_(dinfo_free)(pdbname); + pdbname = NULL; + } + } - vg_assert(pdbname[sz_exename+5-1] == 0); + /* Try s/exe/pdb/ if we don't have a valid pdbname. */ + if (!pdbname) { + /* Try to find a matching PDB file from which to read debuginfo. + Windows PE files have symbol tables and line number information, + but MSVC doesn't seem to use them. */ + /* Why +5 ? Because in the worst case, we could find a dot as the + last character of pdbname, and we'd then put "pdb" right after + it, hence extending it a bit. */ + pdbname = ML_(dinfo_zalloc)("di.debuginfo.lpd1", sz_exename+5); + VG_(strcpy)(pdbname, exename); + vg_assert(pdbname[sz_exename+5-1] == 0); + dot = VG_(strrchr)(pdbname, '.'); + if (!dot) + goto out; /* there's no dot in the exe's name ?! */ + if (dot[1] == 0) + goto out; /* hmm, path ends in "." */ + + if ('A' <= dot[1] && dot[1] <= 'Z') + VG_(strcpy)(dot, ".PDB"); + else + VG_(strcpy)(dot, ".pdb"); + + vg_assert(pdbname[sz_exename+5-1] == 0); + } /* See if we can find it, and check it's in-dateness. */ sres = VG_(stat)(pdbname, &stat_buf); @@ -975,13 +1039,19 @@ void VG_(di_notify_pdb_debuginfo)( Int fd_obj, Addr avma_obj, goto out; } pdb_mtime = stat_buf.mtime; - if (pdb_mtime < obj_mtime ) { - /* PDB file is older than PE file - ignore it or we will either - (a) print wrong stack traces or more likely (b) crash. */ + + if (obj_mtime > pdb_mtime + 60ULL) { + /* PDB file is older than PE file. Really, the PDB should be + newer than the PE, but that doesn't always seem to be the + case. Allow the PDB to be up to one minute older. + Otherwise, it's probably out of date, in which case ignore it + or we will either (a) print wrong stack traces or more likely + (b) crash. + */ VG_(message)(Vg_UserMsg, - "Warning: Ignoring %s since it is older than %s\n", - pdbname, exename); - goto out; + "Warning: %s (mtime = %llu)\n" + " is older than %s (mtime = %llu)\n", + pdbname, pdb_mtime, exename, obj_mtime); } sres = VG_(open)(pdbname, VKI_O_RDONLY, 0); @@ -1177,10 +1247,13 @@ static void search_all_symtabs ( Addr ptr, /*OUT*/DebugInfo** pdi, for (di = debugInfo_list; di != NULL; di = di->next) { if (findText) { - inRange = di->text_present - && di->text_size > 0 - && di->text_avma <= ptr - && ptr < di->text_avma + di->text_size; + /* Consider any symbol in the r-x mapped area to be text. + See Comment_Regarding_Text_Range_Checks in storage.c for + details. */ + inRange = di->have_rx_map + && di->rx_map_size > 0 + && di->rx_map_avma <= ptr + && ptr < di->rx_map_avma + di->rx_map_size; } else { inRange = (di->data_present && di->data_size > 0 @@ -1399,19 +1472,19 @@ Vg_FnNameKind VG_(get_fnname_kind) ( Char* name ) return Vg_FnNameMain; } else if ( -#if defined(VGO_linux) +# if defined(VGO_linux) VG_STREQ("__libc_start_main", name) || // glibc glibness VG_STREQ("generic_start_main", name) || // Yellow Dog doggedness -#elif defined(VGO_freebsd) +# elif defined(VGO_freebsd) VG_STREQ("_start", name) || -#elif defined(VGO_aix5) +# elif defined(VGO_aix5) VG_STREQ("__start", name) || // AIX aches -#elif defined(VGO_darwin) +# elif defined(VGO_darwin) // See readmacho.c for an explanation of this. VG_STREQ("start_according_to_valgrind", name) || // Darwin, darling -#else -# error Unknown OS -#endif +# else +# error "Unknown OS" +# endif 0) { return Vg_FnNameBelowMain; @@ -1707,10 +1780,13 @@ Char* VG_(describe_IP)(Addr eip, Char* buf, Int n_buf) UInt lineno; UChar ibuf[50]; Int n = 0; + static UChar buf_fn[BUF_LEN]; static UChar buf_obj[BUF_LEN]; static UChar buf_srcloc[BUF_LEN]; static UChar buf_dirname[BUF_LEN]; + buf_fn[0] = buf_obj[0] = buf_srcloc[0] = buf_dirname[0] = 0; + Bool know_dirinfo = False; Bool know_fnname = VG_(clo_sym_offsets) ? VG_(get_fnname_w_offset) (eip, buf_fn, BUF_LEN) @@ -1722,6 +1798,11 @@ Char* VG_(describe_IP)(Addr eip, Char* buf, Int n_buf) buf_dirname, BUF_LEN, &know_dirinfo, &lineno ); + buf_fn [ sizeof(buf_fn)-1 ] = 0; + buf_obj [ sizeof(buf_obj)-1 ] = 0; + buf_srcloc [ sizeof(buf_srcloc)-1 ] = 0; + buf_dirname[ sizeof(buf_dirname)-1 ] = 0; + if (VG_(clo_xml)) { Bool human_readable = True; @@ -1792,6 +1873,32 @@ Char* VG_(describe_IP)(Addr eip, Char* buf, Int n_buf) } if (know_srcloc) { APPEND(" ("); + // Get the directory name, if any, possibly pruned, into dirname. + UChar* dirname = NULL; + if (VG_(clo_n_fullpath_after) > 0) { + Int i; + dirname = buf_dirname; + // Remove leading prefixes from the dirname. + // If user supplied --fullpath-after=foo, this will remove + // a leading string which matches '.*foo' (not greedy). + for (i = 0; i < VG_(clo_n_fullpath_after); i++) { + UChar* prefix = VG_(clo_fullpath_after)[i]; + UChar* str = VG_(strstr)(dirname, prefix); + if (str) { + dirname = str + VG_(strlen)(prefix); + break; + } + } + /* remove leading "./" */ + if (dirname[0] == '.' && dirname[1] == '/') + dirname += 2; + } + // do we have any interesting directory name to show? If so + // add it in. + if (dirname && dirname[0] != 0) { + APPEND(dirname); + APPEND("/"); + } APPEND(buf_srcloc); APPEND(":"); VG_(sprintf)(ibuf,"%d",lineno); @@ -1827,24 +1934,25 @@ Char* VG_(describe_IP)(Addr eip, Char* buf, Int n_buf) a CfiExpr into one convenient struct. */ typedef struct { - Addr ipHere; - Addr spHere; - Addr fpHere; - Addr min_accessible; - Addr max_accessible; + D3UnwindRegs* uregs; + Addr min_accessible; + Addr max_accessible; } CfiExprEvalContext; /* Evaluate the CfiExpr rooted at ix in exprs given the context eec. *ok is set to False on failure, but not to True on success. The caller must set it to True before calling. */ -static +__attribute__((noinline)) +static UWord evalCfiExpr ( XArray* exprs, Int ix, CfiExprEvalContext* eec, Bool* ok ) { UWord wL, wR; Addr a; - CfiExpr* e = VG_(indexXA)( exprs, ix ); + CfiExpr* e; + vg_assert(sizeof(Addr) == sizeof(UWord)); + e = VG_(indexXA)( exprs, ix ); switch (e->tag) { case Cex_Binop: wL = evalCfiExpr( exprs, e->Cex.Binop.ixL, eec, ok ); @@ -1861,9 +1969,19 @@ UWord evalCfiExpr ( XArray* exprs, Int ix, /*NOTREACHED*/ case Cex_CfiReg: switch (e->Cex.CfiReg.reg) { - case Creg_IP: return (Addr)eec->ipHere; - case Creg_SP: return (Addr)eec->spHere; - case Creg_FP: return (Addr)eec->fpHere; +# if defined(VGA_x86) || defined(VGA_amd64) + case Creg_IA_IP: return eec->uregs->xip; + case Creg_IA_SP: return eec->uregs->xsp; + case Creg_IA_BP: return eec->uregs->xbp; +# elif defined(VGA_arm) + case Creg_ARM_R15: return eec->uregs->r15; + case Creg_ARM_R14: return eec->uregs->r14; + case Creg_ARM_R13: return eec->uregs->r13; + case Creg_ARM_R12: return eec->uregs->r12; +# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# else +# error "Unsupported arch" +# endif default: goto unhandled; } /*NOTREACHED*/ @@ -2009,94 +2127,175 @@ static void cfsi_cache__invalidate ( void ) { } -/* The main function for DWARF2/3 CFI-based stack unwinding. - Given an IP/SP/FP triple, produce the IP/SP/FP values for the - previous frame, if possible. */ -/* Returns True if OK. If not OK, *{ip,sp,fp}P are not changed. */ -/* NOTE: this function may rearrange the order of entries in the - DebugInfo list. */ -Bool VG_(use_CF_info) ( /*MOD*/Addr* ipP, - /*MOD*/Addr* spP, - /*MOD*/Addr* fpP, - Addr min_accessible, - Addr max_accessible ) +static inline CFSICacheEnt* cfsi_cache__find ( Addr ip ) { - Bool ok; - DebugInfo* di; - DiCfSI* cfsi = NULL; - Addr cfa, ipHere, spHere, fpHere, ipPrev, spPrev, fpPrev; - - CfiExprEvalContext eec; + UWord hash = ip % N_CFSI_CACHE; + CFSICacheEnt* ce = &cfsi_cache[hash]; + static UWord n_q = 0, n_m = 0; - static UWord n_q = 0, n_m = 0; n_q++; if (0 && 0 == (n_q & 0x1FFFFF)) VG_(printf)("QQQ %lu %lu\n", n_q, n_m); - { UWord hash = (*ipP) % N_CFSI_CACHE; - CFSICacheEnt* ce = &cfsi_cache[hash]; - - if (LIKELY(ce->ip == *ipP) && LIKELY(ce->di != NULL)) { - /* found an entry in the cache .. */ - } else { - /* not found in cache. Search and update. */ - n_m++; - ce->ip = *ipP; - find_DiCfSI( &ce->di, &ce->ix, *ipP ); - } - - if (UNLIKELY(ce->di == (DebugInfo*)1)) { - /* no DiCfSI for this address */ - cfsi = NULL; - di = NULL; - } else { - /* found a DiCfSI for this address */ - di = ce->di; - cfsi = &di->cfsi[ ce->ix ]; - } - } - - if (UNLIKELY(cfsi == NULL)) - return False; /* no info. Nothing we can do. */ + if (LIKELY(ce->ip == ip) && LIKELY(ce->di != NULL)) { + /* found an entry in the cache .. */ + } else { + /* not found in cache. Search and update. */ + n_m++; + ce->ip = ip; + find_DiCfSI( &ce->di, &ce->ix, ip ); + } - if (0) { - VG_(printf)("found cfisi: "); - ML_(ppDiCfSI)(di->cfsi_exprs, cfsi); + if (UNLIKELY(ce->di == (DebugInfo*)1)) { + /* no DiCfSI for this address */ + return NULL; + } else { + /* found a DiCfSI for this address */ + return ce; } +} - ipPrev = spPrev = fpPrev = 0; - ipHere = *ipP; - spHere = *spP; - fpHere = *fpP; +inline +static Addr compute_cfa ( D3UnwindRegs* uregs, + Addr min_accessible, Addr max_accessible, + DebugInfo* di, DiCfSI* cfsi ) +{ + CfiExprEvalContext eec; + Addr cfa; + Bool ok; - /* First compute the CFA. */ + /* Compute the CFA. */ cfa = 0; switch (cfsi->cfa_how) { - case CFIC_SPREL: - cfa = cfsi->cfa_off + spHere; +# if defined(VGA_x86) || defined(VGA_amd64) + case CFIC_IA_SPREL: + cfa = cfsi->cfa_off + uregs->xsp; + break; + case CFIC_IA_BPREL: + cfa = cfsi->cfa_off + uregs->xbp; + break; +# elif defined(VGA_arm) + case CFIC_ARM_R13REL: + cfa = cfsi->cfa_off + uregs->r13; break; - case CFIC_FPREL: - cfa = cfsi->cfa_off + fpHere; + case CFIC_ARM_R12REL: + cfa = cfsi->cfa_off + uregs->r12; break; - case CFIC_EXPR: + case CFIC_ARM_R11REL: + cfa = cfsi->cfa_off + uregs->r11; + break; + case CFIC_ARM_R7REL: + cfa = cfsi->cfa_off + uregs->r7; + break; +# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# else +# error "Unsupported arch" +# endif + case CFIC_EXPR: /* available on all archs */ if (0) { VG_(printf)("CFIC_EXPR: "); ML_(ppCfiExpr)(di->cfsi_exprs, cfsi->cfa_off); VG_(printf)("\n"); } - eec.ipHere = ipHere; - eec.spHere = spHere; - eec.fpHere = fpHere; + eec.uregs = uregs; eec.min_accessible = min_accessible; eec.max_accessible = max_accessible; ok = True; cfa = evalCfiExpr(di->cfsi_exprs, cfsi->cfa_off, &eec, &ok ); - if (!ok) return False; + if (!ok) return 0; break; default: vg_assert(0); } + return cfa; +} + + +/* Get the call frame address (CFA) given an IP/SP/FP triple. */ +/* NOTE: This function may rearrange the order of entries in the + DebugInfo list. */ +Addr ML_(get_CFA) ( Addr ip, Addr sp, Addr fp, + Addr min_accessible, Addr max_accessible ) +{ + CFSICacheEnt* ce; + DebugInfo* di; + DiCfSI* cfsi; + + ce = cfsi_cache__find(ip); + + if (UNLIKELY(ce == NULL)) + return 0; /* no info. Nothing we can do. */ + + di = ce->di; + cfsi = &di->cfsi[ ce->ix ]; + + /* Temporary impedance-matching kludge so that this keeps working + on x86-linux and amd64-linux. */ +# if defined(VGA_x86) || defined(VGA_amd64) + { D3UnwindRegs uregs; + uregs.xip = ip; + uregs.xsp = sp; + uregs.xbp = fp; + return compute_cfa(&uregs, + min_accessible, max_accessible, di, cfsi); + } +# else + return 0; /* indicates failure */ +# endif +} + + +/* The main function for DWARF2/3 CFI-based stack unwinding. Given a + set of registers in UREGS, modify it to hold the register values + for the previous frame, if possible. Returns True if successful. + If not successful, *UREGS is not changed. + + For x86 and amd64, the unwound registers are: {E,R}IP, + {E,R}SP, {E,R}BP. + + For arm, the unwound registers are: R7 R11 R12 R13 R14 R15. +*/ +Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere, + Addr min_accessible, + Addr max_accessible ) +{ + Bool ok; + DebugInfo* di; + DiCfSI* cfsi = NULL; + Addr cfa, ipHere = 0; + CFSICacheEnt* ce; + CfiExprEvalContext eec; + D3UnwindRegs uregsPrev; + +# if defined(VGA_x86) || defined(VGA_amd64) + ipHere = uregsHere->xip; +# elif defined(VGA_arm) + ipHere = uregsHere->r15; +# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# else +# error "Unknown arch" +# endif + ce = cfsi_cache__find(ipHere); + + if (UNLIKELY(ce == NULL)) + return False; /* no info. Nothing we can do. */ + + di = ce->di; + cfsi = &di->cfsi[ ce->ix ]; + + if (0) { + VG_(printf)("found cfisi: "); + ML_(ppDiCfSI)(di->cfsi_exprs, cfsi); + } + + VG_(bzero_inline)(&uregsPrev, sizeof(uregsPrev)); + + /* First compute the CFA. */ + cfa = compute_cfa(uregsHere, + min_accessible, max_accessible, di, cfsi); + if (UNLIKELY(cfa == 0)) + return False; /* Now we know the CFA, use it to roll back the registers we're interested in. */ @@ -2122,9 +2321,7 @@ Bool VG_(use_CF_info) ( /*MOD*/Addr* ipP, case CFIR_EXPR: \ if (0) \ ML_(ppCfiExpr)(di->cfsi_exprs,_off); \ - eec.ipHere = ipHere; \ - eec.spHere = spHere; \ - eec.fpHere = fpHere; \ + eec.uregs = uregsHere; \ eec.min_accessible = min_accessible; \ eec.max_accessible = max_accessible; \ ok = True; \ @@ -2136,15 +2333,25 @@ Bool VG_(use_CF_info) ( /*MOD*/Addr* ipP, } \ } while (0) - COMPUTE(ipPrev, ipHere, cfsi->ra_how, cfsi->ra_off); - COMPUTE(spPrev, spHere, cfsi->sp_how, cfsi->sp_off); - COMPUTE(fpPrev, fpHere, cfsi->fp_how, cfsi->fp_off); +# if defined(VGA_x86) || defined(VGA_amd64) + COMPUTE(uregsPrev.xip, uregsHere->xip, cfsi->ra_how, cfsi->ra_off); + COMPUTE(uregsPrev.xsp, uregsHere->xsp, cfsi->sp_how, cfsi->sp_off); + COMPUTE(uregsPrev.xbp, uregsHere->xbp, cfsi->bp_how, cfsi->bp_off); +# elif defined(VGA_arm) + COMPUTE(uregsPrev.r15, uregsHere->r15, cfsi->ra_how, cfsi->ra_off); + COMPUTE(uregsPrev.r14, uregsHere->r14, cfsi->r14_how, cfsi->r14_off); + COMPUTE(uregsPrev.r13, uregsHere->r13, cfsi->r13_how, cfsi->r13_off); + COMPUTE(uregsPrev.r12, uregsHere->r12, cfsi->r12_how, cfsi->r12_off); + COMPUTE(uregsPrev.r11, uregsHere->r11, cfsi->r11_how, cfsi->r11_off); + COMPUTE(uregsPrev.r7, uregsHere->r7, cfsi->r7_how, cfsi->r7_off); +# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# else +# error "Unknown arch" +# endif # undef COMPUTE - *ipP = ipPrev; - *spP = spPrev; - *fpP = fpPrev; + *uregsHere = uregsPrev; return True; } @@ -2352,7 +2559,7 @@ static Bool data_address_is_in_var ( /*OUT*/PtrdiffT* offset, VG_(printf)("\n"); } - if (res.kind == GXR_Value + if (res.kind == GXR_Addr && res.word <= data_addr && data_addr < res.word + var_szB) { *offset = data_addr - res.word; @@ -3063,7 +3270,7 @@ void analyse_deps ( /*MOD*/XArray* /* of FrameBlock */ blocks, vg_assert(res_sp_6k.kind == res_fp_6k.kind); vg_assert(res_sp_6k.kind == res_fp_7k.kind); - if (res_sp_6k.kind == GXR_Value) { + if (res_sp_6k.kind == GXR_Addr) { StackBlock block; GXResult res; UWord sp_delta = res_sp_7k.word - res_sp_6k.word; @@ -3080,7 +3287,7 @@ void analyse_deps ( /*MOD*/XArray* /* of FrameBlock */ blocks, regs.sp = regs.fp = 0; regs.ip = ip; res = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, di ); - tl_assert(res.kind == GXR_Value); + tl_assert(res.kind == GXR_Addr); if (debug) VG_(printf)(" %5ld .. %5ld (sp) %s\n", res.word, res.word + ((UWord)mul.ul) - 1, var->name); @@ -3099,7 +3306,7 @@ void analyse_deps ( /*MOD*/XArray* /* of FrameBlock */ blocks, regs.sp = regs.fp = 0; regs.ip = ip; res = ML_(evaluate_GX)( var->gexpr, var->fbGX, ®s, di ); - tl_assert(res.kind == GXR_Value); + tl_assert(res.kind == GXR_Addr); if (debug) VG_(printf)(" %5ld .. %5ld (FP) %s\n", res.word, res.word + ((UWord)mul.ul) - 1, var->name); @@ -3314,7 +3521,7 @@ void* /* really, XArray* of GlobalBlock */ res = ML_(evaluate_trivial_GX)( var->gexpr, di ); /* Not a constant address => not interesting */ - if (res.kind != GXR_Value) { + if (res.kind != GXR_Addr) { if (0) VG_(printf)("FAIL\n"); continue; } @@ -3441,14 +3648,16 @@ void VG_(DebugInfo_syms_getidx) ( const DebugInfo *si, /*OUT*/Addr* tocptr, /*OUT*/UInt* size, /*OUT*/HChar** name, - /*OUT*/Bool* isText ) + /*OUT*/Bool* isText, + /*OUT*/Bool* isIFunc ) { vg_assert(idx >= 0 && idx < si->symtab_used); - if (avma) *avma = si->symtab[idx].addr; - if (tocptr) *tocptr = si->symtab[idx].tocptr; - if (size) *size = si->symtab[idx].size; - if (name) *name = (HChar*)si->symtab[idx].name; - if (isText) *isText = si->symtab[idx].isText; + if (avma) *avma = si->symtab[idx].addr; + if (tocptr) *tocptr = si->symtab[idx].tocptr; + if (size) *size = si->symtab[idx].size; + if (name) *name = (HChar*)si->symtab[idx].name; + if (isText) *isText = si->symtab[idx].isText; + if (isIFunc) *isIFunc = si->symtab[idx].isIFunc; } diff --git a/coregrind/m_debuginfo/misc.c b/coregrind/m_debuginfo/misc.c index ec35c36..3f94ec2 100644 --- a/coregrind/m_debuginfo/misc.c +++ b/coregrind/m_debuginfo/misc.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks LLP + Copyright (C) 2008-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_debuginfo/priv_d3basics.h b/coregrind/m_debuginfo/priv_d3basics.h index 1368e0d..b6703e9 100644 --- a/coregrind/m_debuginfo/priv_d3basics.h +++ b/coregrind/m_debuginfo/priv_d3basics.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks LLP and others; see below + Copyright (C) 2008-2010 OpenWorks LLP and others; see below info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -104,6 +104,10 @@ typedef enum DW_TAG_imported_unit = 0x3d, DW_TAG_condition = 0x3f, DW_TAG_shared_type = 0x40, + /* DWARF 4. */ + DW_TAG_type_unit = 0x41, + DW_TAG_rvalue_reference_type = 0x42, + DW_TAG_template_alias = 0x43, /* SGI/MIPS Extensions. */ DW_TAG_MIPS_loop = 0x4081, /* HP extensions. See: ftp://ftp.hp.com/pub/lang/tools/WDB/wdb-4.0.tar.gz . */ @@ -158,6 +162,8 @@ typedef enum dwarf_source_language DW_LANG_ObjC_plus_plus = 0x0011, DW_LANG_UPC = 0x0012, DW_LANG_D = 0x0013, + /* DWARF 4. */ + DW_LANG_Python = 0x0014, /* MIPS. */ DW_LANG_Mips_Assembler = 0x8001, /* UPC. */ @@ -188,7 +194,12 @@ typedef enum DW_FORM_ref4 = 0x13, DW_FORM_ref8 = 0x14, DW_FORM_ref_udata = 0x15, - DW_FORM_indirect = 0x16 + DW_FORM_indirect = 0x16, + /* DWARF 4 values. */ + DW_FORM_sec_offset = 0x17, + DW_FORM_exprloc = 0x18, + DW_FORM_flag_present = 0x19, + DW_FORM_ref_sig8 = 0x20 } DW_FORM; @@ -285,6 +296,13 @@ typedef enum DW_AT_elemental = 0x66, DW_AT_pure = 0x67, DW_AT_recursive = 0x68, + /* DWARF 4 values. */ + DW_AT_signature = 0x69, + DW_AT_main_subprogram = 0x6a, + DW_AT_data_bit_offset = 0x6b, + DW_AT_const_expr = 0x6c, + DW_AT_enum_class = 0x6d, + DW_AT_linkage_name = 0x6e, /* SGI/MIPS extensions. */ DW_AT_MIPS_fde = 0x2001, DW_AT_MIPS_loop_begin = 0x2002, @@ -354,6 +372,8 @@ typedef enum DW_ATE_signed_fixed = 0xd, DW_ATE_unsigned_fixed = 0xe, DW_ATE_decimal_float = 0xf, + /* DWARF 4. */ + DW_ATE_UTF = 0x10, /* HP extensions. */ DW_ATE_HP_float80 = 0x80, /* Floating-point (80 bit). */ DW_ATE_HP_complex_float80 = 0x81, /* Complex floating-point (80 bit). */ @@ -522,6 +542,9 @@ typedef enum DW_OP_form_tls_address = 0x9b, DW_OP_call_frame_cfa = 0x9c, DW_OP_bit_piece = 0x9d, + /* DWARF 4 extensions. */ + DW_OP_implicit_value = 0x9e, + DW_OP_stack_value = 0x9f, /* GNU extensions. */ DW_OP_GNU_push_tls_address = 0xe0, /* HP extensions. */ @@ -596,12 +619,13 @@ typedef /* This describes the result of evaluating a DWARF3 expression. GXR_Failure: failed; .word is an asciiz string summarising why + GXR_Addr: evaluated to an address of the object, in .word GXR_Value: evaluated to a value, in .word GXR_RegNo: evaluated to a DWARF3 register number, in .word */ typedef struct { - enum { GXR_Failure, GXR_Value, GXR_RegNo } kind; + enum { GXR_Failure, GXR_Addr, GXR_Value, GXR_RegNo } kind; UWord word; } GXResult; @@ -644,6 +668,10 @@ GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB, covered by the guard is also ignored. */ GXResult ML_(evaluate_trivial_GX)( GExpr* gx, const DebugInfo* di ); +/* Compute call frame address (CFA) for IP/SP/FP. */ +Addr ML_(get_CFA) ( Addr ip, Addr sp, Addr fp, + Addr min_accessible, Addr max_accessible ); + #endif /* ndef __PRIV_D3BASICS_H */ /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_debuginfo/priv_misc.h b/coregrind/m_debuginfo/priv_misc.h index fd786a5..0046da6 100644 --- a/coregrind/m_debuginfo/priv_misc.h +++ b/coregrind/m_debuginfo/priv_misc.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks LLP + Copyright (C) 2008-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_debuginfo/priv_readdwarf.h b/coregrind/m_debuginfo/priv_readdwarf.h index dc9fb99..11e7183 100644 --- a/coregrind/m_debuginfo/priv_readdwarf.h +++ b/coregrind/m_debuginfo/priv_readdwarf.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -62,7 +62,7 @@ void ML_(read_debuginfo_dwarf1) ( struct _DebugInfo* di, -------------------- */ extern void ML_(read_callframe_info_dwarf3) - ( /*OUT*/struct _DebugInfo* di, UChar* ehframe ); + ( /*OUT*/struct _DebugInfo* di, UChar* frame, SizeT frame_sz, Bool for_eh ); #endif /* ndef __PRIV_READDWARF_H */ diff --git a/coregrind/m_debuginfo/priv_readdwarf3.h b/coregrind/m_debuginfo/priv_readdwarf3.h index 277e63a..c8162e3 100644 --- a/coregrind/m_debuginfo/priv_readdwarf3.h +++ b/coregrind/m_debuginfo/priv_readdwarf3.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks LLP + Copyright (C) 2008-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_debuginfo/priv_readelf.h b/coregrind/m_debuginfo/priv_readelf.h index e0955c4..f185f66 100644 --- a/coregrind/m_debuginfo/priv_readelf.h +++ b/coregrind/m_debuginfo/priv_readelf.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_debuginfo/priv_readpdb.h b/coregrind/m_debuginfo/priv_readpdb.h index 3fb84d7..f5dc310 100644 --- a/coregrind/m_debuginfo/priv_readpdb.h +++ b/coregrind/m_debuginfo/priv_readpdb.h @@ -48,6 +48,12 @@ extern Bool ML_(read_pdb_debug_info)( ULong pdbmtime ); +/* Finds the name of the PDB file that's embedded with the specified + PE file, or NULL on failure. Caller deallocates with + ML_(dinfo_free). */ +HChar* ML_(find_name_of_pdb_file)( HChar* pename ); + + #endif /* ndef __PRIV_READPDB_H */ #endif // defined(VGO_linux) || defined(VGO_darwin) diff --git a/coregrind/m_debuginfo/priv_readstabs.h b/coregrind/m_debuginfo/priv_readstabs.h index c7a42f0..00bf297 100644 --- a/coregrind/m_debuginfo/priv_readstabs.h +++ b/coregrind/m_debuginfo/priv_readstabs.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_debuginfo/priv_readxcoff.h b/coregrind/m_debuginfo/priv_readxcoff.h index 55e6de8..d8e42b5 100644 --- a/coregrind/m_debuginfo/priv_readxcoff.h +++ b/coregrind/m_debuginfo/priv_readxcoff.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_debuginfo/priv_storage.h b/coregrind/m_debuginfo/priv_storage.h index f6e6e82..e272529 100644 --- a/coregrind/m_debuginfo/priv_storage.h +++ b/coregrind/m_debuginfo/priv_storage.h @@ -9,7 +9,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -48,15 +48,16 @@ /* A structure to hold an ELF/XCOFF symbol (very crudely). */ typedef struct { - Addr addr; /* lowest address of entity */ - Addr tocptr; /* ppc64-linux only: value that R2 should have */ - UChar *name; /* name */ + Addr addr; /* lowest address of entity */ + Addr tocptr; /* ppc64-linux only: value that R2 should have */ + UChar *name; /* name */ // XXX: this could be shrunk (on 32-bit platforms) by using 31 bits for // the size and 1 bit for the isText. If you do this, make sure that // all assignments to isText use 0 or 1 (or True or False), and that a // positive number larger than 1 is never used to represent True. - UInt size; /* size in bytes */ + UInt size; /* size in bytes */ Bool isText; + Bool isIFunc; /* symbol is an indirect function? */ } DiSym; @@ -96,55 +97,120 @@ typedef /* --------------------- CF INFO --------------------- */ -/* A structure to summarise DWARF2/3 CFA info for the code address - range [base .. base+len-1]. In short, if you know (sp,fp,ip) at - some point and ip is in the range [base .. base+len-1], it tells - you how to calculate (sp,fp) for the caller of the current frame - and also ra, the return address of the current frame. +/* DiCfSI: a structure to summarise DWARF2/3 CFA info for the code + address range [base .. base+len-1]. + + On x86 and amd64 ("IA"), if you know ({e,r}sp, {e,r}bp, {e,r}ip) at + some point and {e,r}ip is in the range [base .. base+len-1], it + tells you how to calculate ({e,r}sp, {e,r}bp) for the caller of the + current frame and also ra, the return address of the current frame. First off, calculate CFA, the Canonical Frame Address, thusly: cfa = case cfa_how of - CFIC_SPREL -> sp + cfa_off - CFIC_FPREL -> fp + cfa_off - CFIR_EXPR -> expr whose index is in cfa_off + CFIC_IA_SPREL -> {e,r}sp + cfa_off + CFIC_IA_BPREL -> {e,r}bp + cfa_off + CFIR_IA_EXPR -> expr whose index is in cfa_off - Once that is done, the previous frame's sp/fp values and this - frame's ra value can be calculated like this: + Once that is done, the previous frame's {e,r}sp/{e,r}bp values and + this frame's {e,r}ra value can be calculated like this: - old_sp/fp/ra - = case sp/fp/ra_how of + old_{e,r}sp/{e,r}bp/ra + = case {e,r}sp/{e,r}bp/ra_how of CFIR_UNKNOWN -> we don't know, sorry CFIR_SAME -> same as it was before (sp/fp only) - CFIR_CFAREL -> cfa + sp/fp/ra_off - CFIR_MEMCFAREL -> *( cfa + sp/fp/ra_off ) - CFIR_EXPR -> expr whose index is in sp/fp/ra_off -*/ + CFIR_CFAREL -> cfa + sp/bp/ra_off + CFIR_MEMCFAREL -> *( cfa + sp/bp/ra_off ) + CFIR_EXPR -> expr whose index is in sp/bp/ra_off -#define CFIC_SPREL ((UChar)1) -#define CFIC_FPREL ((UChar)2) -#define CFIC_EXPR ((UChar)3) + On ARM it's pretty much the same, except we have more registers to + keep track of: -#define CFIR_UNKNOWN ((UChar)4) -#define CFIR_SAME ((UChar)5) -#define CFIR_CFAREL ((UChar)6) -#define CFIR_MEMCFAREL ((UChar)7) -#define CFIR_EXPR ((UChar)8) + cfa = case cfa_how of + CFIC_R13REL -> r13 + cfa_off + CFIC_R12REL -> r12 + cfa_off + CFIC_R11REL -> r11 + cfa_off + CFIC_R7REL -> r7 + cfa_off + CFIR_EXPR -> expr whose index is in cfa_off + + old_r14/r13/r12/r11/r7/ra + = case r14/r13/r12/r11/r7/ra_how of + CFIR_UNKNOWN -> we don't know, sorry + CFIR_SAME -> same as it was before (r14/r13/r12/r11/r7 only) + CFIR_CFAREL -> cfa + r14/r13/r12/r11/r7/ra_off + CFIR_MEMCFAREL -> *( cfa + r14/r13/r12/r11/r7/ra_off ) + CFIR_EXPR -> expr whose index is in r14/r13/r12/r11/r7/ra_off +*/ +#define CFIC_IA_SPREL ((UChar)1) +#define CFIC_IA_BPREL ((UChar)2) +#define CFIC_IA_EXPR ((UChar)3) +#define CFIC_ARM_R13REL ((UChar)4) +#define CFIC_ARM_R12REL ((UChar)5) +#define CFIC_ARM_R11REL ((UChar)6) +#define CFIC_ARM_R7REL ((UChar)7) +#define CFIC_EXPR ((UChar)8) /* all targets */ + +#define CFIR_UNKNOWN ((UChar)64) +#define CFIR_SAME ((UChar)65) +#define CFIR_CFAREL ((UChar)66) +#define CFIR_MEMCFAREL ((UChar)67) +#define CFIR_EXPR ((UChar)68) + +#if defined(VGA_x86) || defined(VGA_amd64) typedef struct { Addr base; UInt len; - UChar cfa_how; /* a CFIC_ value */ + UChar cfa_how; /* a CFIC_IA value */ UChar ra_how; /* a CFIR_ value */ UChar sp_how; /* a CFIR_ value */ - UChar fp_how; /* a CFIR_ value */ + UChar bp_how; /* a CFIR_ value */ Int cfa_off; Int ra_off; Int sp_off; - Int fp_off; + Int bp_off; } DiCfSI; +#elif defined(VGA_arm) +typedef + struct { + Addr base; + UInt len; + UChar cfa_how; /* a CFIC_ value */ + UChar ra_how; /* a CFIR_ value */ + UChar r14_how; /* a CFIR_ value */ + UChar r13_how; /* a CFIR_ value */ + UChar r12_how; /* a CFIR_ value */ + UChar r11_how; /* a CFIR_ value */ + UChar r7_how; /* a CFIR_ value */ + Int cfa_off; + Int ra_off; + Int r14_off; + Int r13_off; + Int r12_off; + Int r11_off; + Int r7_off; + } + DiCfSI; +#elif defined(VGA_ppc32) || defined(VGA_ppc64) +/* Just have a struct with the common fields in, so that code that + processes the common fields doesn't have to be ifdef'd against + VGP_/VGA_ symbols. These are not used in any way on ppc32/64-linux + at the moment. */ +typedef + struct { + Addr base; + UInt len; + UChar cfa_how; /* a CFIC_ value */ + UChar ra_how; /* a CFIR_ value */ + Int cfa_off; + Int ra_off; + } + DiCfSI; +#else +# error "Unknown arch" +#endif typedef @@ -158,9 +224,13 @@ typedef typedef enum { - Creg_SP=0x213, - Creg_FP, - Creg_IP + Creg_IA_SP=0x213, + Creg_IA_BP, + Creg_IA_IP, + Creg_ARM_R13, + Creg_ARM_R12, + Creg_ARM_R15, + Creg_ARM_R14 } CfiReg; @@ -648,6 +718,11 @@ extern void ML_(addVar)( struct _DebugInfo* di, this after finishing adding entries to these tables. */ extern void ML_(canonicaliseTables) ( struct _DebugInfo* di ); +/* Canonicalise the call-frame-info table held by 'di', in preparation + for use. This is called by ML_(canonicaliseTables) but can also be + called on it's own to sort just this table. */ +extern void ML_(canonicaliseCFI) ( struct _DebugInfo* di ); + /* ------ Searching ------ */ /* Find a symbol-table index containing the specified pointer, or -1 diff --git a/coregrind/m_debuginfo/priv_tytypes.h b/coregrind/m_debuginfo/priv_tytypes.h index 880aa0e..97812cd 100644 --- a/coregrind/m_debuginfo/priv_tytypes.h +++ b/coregrind/m_debuginfo/priv_tytypes.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks LLP + Copyright (C) 2008-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -78,8 +78,13 @@ typedef struct { UChar* name; /* in mallocville */ UWord typeR; /* should be Te_TyXXXX */ - UChar* loc; /* location expr, in mallocville */ - UWord nLoc; /* number of bytes in .loc */ + union { + UChar* loc; /* location expr, in mallocville */ + Word offset; /* or offset from the beginning of containing + entity */ + } pos; + Word nLoc; /* number of bytes in .pos.loc if >= 0, or -1 + if .pos.offset should be used instead */ Bool isStruct; } Field; struct { diff --git a/coregrind/m_debuginfo/readdwarf.c b/coregrind/m_debuginfo/readdwarf.c index abc3e1e..53fa783 100644 --- a/coregrind/m_debuginfo/readdwarf.c +++ b/coregrind/m_debuginfo/readdwarf.c @@ -1,13 +1,13 @@ /*--------------------------------------------------------------------*/ -/*--- Read DWARF1/2/3 debug info. readdwarf.c ---*/ +/*--- Read DWARF1/2/3/4 debug info. readdwarf.c ---*/ /*--------------------------------------------------------------------*/ /* This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -37,6 +37,7 @@ #include "pub_core_libcprint.h" #include "pub_core_options.h" #include "pub_core_xarray.h" +#include "pub_core_tooliface.h" /* VG_(needs) */ #include "priv_misc.h" /* dinfo_zalloc/free/strdup */ #include "priv_d3basics.h" #include "priv_tytypes.h" @@ -138,6 +139,7 @@ typedef struct UShort li_version; ULong li_header_length; UChar li_min_insn_length; + UChar li_max_ops_per_insn; UChar li_default_is_stmt; Int li_line_base; UChar li_line_range; @@ -181,7 +183,8 @@ enum dwarf_line_number_x_ops { DW_LNE_end_sequence = 1, DW_LNE_set_address = 2, - DW_LNE_define_file = 3 + DW_LNE_define_file = 3, + DW_LNE_set_discriminator = 4 }; typedef struct @@ -198,7 +201,7 @@ typedef struct UInt column; Int is_stmt; Int basic_block; - Int end_sequence; + UChar end_sequence; } LineSMR; @@ -410,6 +413,11 @@ Word process_extended_line_op( struct _DebugInfo* di, VG_(printf)(" DWARF2-line: set_address\n"); break; + case DW_LNE_set_discriminator: + read_leb128 (data, & bytes_read, 0); + data += bytes_read; + break; + default: if (di->ddump_line) VG_(printf)("process_extended_line_op:default\n"); @@ -512,9 +520,9 @@ void read_dwarf2_lineblock ( struct _DebugInfo* di, VG_(printf)(" DWARF Version: %d\n", (Int)info.li_version); - if (info.li_version != 2 && info.li_version != 3) { + if (info.li_version != 2 && info.li_version != 3 && info.li_version != 4) { ML_(symerr)(di, True, - "Only DWARF version 2 and 3 line info " + "Only DWARF version 2, 3 and 4 line info " "is currently supported."); goto out; } @@ -532,6 +540,26 @@ void read_dwarf2_lineblock ( struct _DebugInfo* di, VG_(printf)(" Minimum Instruction Length: %d\n", (Int)info.li_min_insn_length); + /* We only support machines with one opcode per instruction + for now. If we ever want to support VLIW machines there is + code to handle multiple opcodes per instruction in the + patch attached to BZ#233595. + */ + if (info.li_version >= 4) { + info.li_max_ops_per_insn = * ((UChar *)external); + if (info.li_max_ops_per_insn != 1) { + ML_(symerr)(di, True, + "Invalid Maximum Ops Per Insn in line info."); + goto out; + } + external += 1; + if (di->ddump_line) + VG_(printf)(" Maximum Ops Per Insn: %d\n", + (Int)info.li_max_ops_per_insn); + } else { + info.li_max_ops_per_insn = 1; + } + info.li_default_is_stmt = * ((UChar *)external); external += 1; if (di->ddump_line) @@ -713,7 +741,7 @@ void read_dwarf2_lineblock ( struct _DebugInfo* di, Int advAddr; op_code -= info.li_opcode_base; - adv = (op_code / info.li_line_range) + adv = (op_code / info.li_line_range) * info.li_min_insn_length; advAddr = adv; state_machine_regs.address += adv; @@ -799,7 +827,7 @@ void read_dwarf2_lineblock ( struct _DebugInfo* di, break; case DW_LNS_advance_pc: - adv = info.li_min_insn_length + adv = info.li_min_insn_length * read_leb128 (data, & bytes_read, 0); data += bytes_read; state_machine_regs.address += adv; @@ -978,7 +1006,7 @@ void read_unitinfo_dwarf2( /*OUT*/UnitInfo* ui, blklen = read_initial_length_field( p, &ui->dw64 ); p += ui->dw64 ? 12 : 4; - /* version should be 2 */ + /* version should be 2, 3 or 4 */ ver = *((UShort*)p); p += 2; @@ -1048,6 +1076,9 @@ void read_unitinfo_dwarf2( /*OUT*/UnitInfo* ui, classes) use FORM_data8, not FORM_data4. Also, FORM_ref_addr and FORM_strp are 64-bit values, not 32-bit values. */ + /* TJH 27 Apr 10: in DWARF 4 lineptr (and loclistptr,macptr, + rangelistptr classes) use FORM_sec_offset which is 64 bits + in 64 bit DWARF and 32 bits in 32 bit DWARF. */ switch( form ) { /* Those cases extract the data properly */ case 0x05: /* FORM_data2 */ cval = *((UShort*)p); p +=2; break; @@ -1065,7 +1096,11 @@ void read_unitinfo_dwarf2( /*OUT*/UnitInfo* ui, case 0x08: /* FORM_string */ sval = (Char*)p; p += VG_(strlen)((Char*)p) + 1; break; case 0x0b: /* FORM_data1 */ cval = *p; p++; break; - + case 0x17: /* FORM_sec_offset */if (ui->dw64) { + cval = *((ULong*)p); p += 8; + } else { + cval = *((UInt*)p); p += 4; + }; break; /* TODO : Following ones just skip data - implement if you need */ case 0x01: /* FORM_addr */ p += addr_size; break; case 0x03: /* FORM_block2 */ p += *((UShort*)p) + 2; break; @@ -1084,7 +1119,10 @@ void read_unitinfo_dwarf2( /*OUT*/UnitInfo* ui, case 0x13: /* FORM_ref4 */ p += 4; break; case 0x14: /* FORM_ref8 */ p += 8; break; case 0x15: /* FORM_ref_udata */ read_leb128U( &p ); break; - + case 0x18: /* FORM_exprloc */ p += read_leb128U( &p ); break; + case 0x19: /* FORM_flag_present */break; + case 0x20: /* FORM_ref_sig8 */ p += 8; break; + default: VG_(printf)( "### unhandled dwarf2 abbrev form code 0x%x\n", form ); break; @@ -1162,9 +1200,9 @@ void ML_(read_debuginfo_dwarf3) /* version should be 2 */ ver = *((UShort*)( block_img + blklen_len )); - if ( ver != 2 && ver != 3 ) { + if ( ver != 2 && ver != 3 && ver != 4 ) { ML_(symerr)( di, True, - "Ignoring non-Dwarf2/3 block in .debug_info" ); + "Ignoring non-Dwarf2/3/4 block in .debug_info" ); continue; } @@ -1777,11 +1815,15 @@ void ML_(read_debuginfo_dwarf1) ( #elif defined(VGP_ppc32_linux) # define FP_REG 1 # define SP_REG 1 -# define RA_REG_DEFAULT 8 // CAB: What's a good default ? +# define RA_REG_DEFAULT 65 #elif defined(VGP_ppc64_linux) # define FP_REG 1 # define SP_REG 1 -# define RA_REG_DEFAULT 8 // CAB: What's a good default ? +# define RA_REG_DEFAULT 65 +#elif defined(VGP_arm_linux) +# define FP_REG 12 +# define SP_REG 13 +# define RA_REG_DEFAULT 14 //??? #elif defined(VGP_x86_darwin) # define FP_REG 5 # define SP_REG 4 @@ -1795,7 +1837,11 @@ void ML_(read_debuginfo_dwarf1) ( #endif /* the number of regs we are prepared to unwind */ -#define N_CFI_REGS 20 +#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) +# define N_CFI_REGS 72 +#else +# define N_CFI_REGS 20 +#endif /* Instructions for the automaton */ enum dwarf_cfa_primary_ops @@ -2006,6 +2052,16 @@ static void initUnwindContext ( /*OUT*/UnwindContext* ctx ) ctx->state[j].reg[i].tag = RR_Undef; /* ctx->state[j].reg[i].arg = 0; */ } +# if defined(VGA_arm) + /* All callee-saved registers (or at least the ones we are + summarising for) should start out as RR_Same, on ARM. */ + ctx->state[j].reg[11].tag = RR_Same; + /* ctx->state[j].reg[13].tag = RR_Same; */ + ctx->state[j].reg[14].tag = RR_Same; + ctx->state[j].reg[12].tag = RR_Same; + ctx->state[j].reg[7].tag = RR_Same; + /* this can't be right though: R12 (IP) isn't callee saved. */ +# endif } } @@ -2026,16 +2082,7 @@ typedef static void initCfiSI ( DiCfSI* si ) { - si->base = 0; - si->len = 0; - si->cfa_how = 0; - si->ra_how = 0; - si->sp_how = 0; - si->fp_how = 0; - si->cfa_off = 0; - si->ra_off = 0; - si->sp_off = 0; - si->fp_off = 0; + VG_(memset)(si, 0, sizeof(*si)); } @@ -2067,7 +2114,7 @@ static Bool summarise_context( /*OUT*/DiCfSI* si, if (ctx->state_sp >= N_RR_STACK) { why = 9; goto failed; } ctxs = &ctx->state[ctx->state_sp]; - /* How to generate the CFA */ + /* First, summarise the method for generating the CFA */ if (!ctxs->cfa_is_regoff) { /* it was set by DW_CFA_def_cfa_expression; try to convert */ XArray *src, *dst; @@ -2088,15 +2135,42 @@ static Bool summarise_context( /*OUT*/DiCfSI* si, si->cfa_off = conv; if (0 && debuginfo->ddump_frames) ML_(ppCfiExpr)(dst, conv); - } else + } + else if (ctxs->cfa_is_regoff && ctxs->cfa_reg == SP_REG) { - si->cfa_how = CFIC_SPREL; si->cfa_off = ctxs->cfa_off; - } else +# if defined(VGA_x86) || defined(VGA_amd64) + si->cfa_how = CFIC_IA_SPREL; +# elif defined(VGA_arm) + si->cfa_how = CFIC_ARM_R13REL; +# else + si->cfa_how = 0; /* invalid */ +# endif + } + else if (ctxs->cfa_is_regoff && ctxs->cfa_reg == FP_REG) { - si->cfa_how = CFIC_FPREL; si->cfa_off = ctxs->cfa_off; - } else { +# if defined(VGA_x86) || defined(VGA_amd64) + si->cfa_how = CFIC_IA_BPREL; +# elif defined(VGA_arm) + si->cfa_how = CFIC_ARM_R12REL; +# else + si->cfa_how = 0; /* invalid */ +# endif + } +# if defined(VGA_arm) + else + if (ctxs->cfa_is_regoff && ctxs->cfa_reg == 11/*??_REG*/) { + si->cfa_how = CFIC_ARM_R11REL; + si->cfa_off = ctxs->cfa_off; + } + else + if (ctxs->cfa_is_regoff && ctxs->cfa_reg == 7/*??_REG*/) { + si->cfa_how = CFIC_ARM_R7REL; + si->cfa_off = ctxs->cfa_off; + } +# endif + else { why = 1; goto failed; } @@ -2138,13 +2212,15 @@ static Bool summarise_context( /*OUT*/DiCfSI* si, why = 2; goto failed; /* otherwise give up */ \ } +# if defined(VGA_x86) || defined(VGA_amd64) + + /* --- entire tail of this fn specialised for x86/amd64 --- */ + SUMMARISE_HOW(si->ra_how, si->ra_off, ctxs->reg[ctx->ra_reg] ); - SUMMARISE_HOW(si->fp_how, si->fp_off, + SUMMARISE_HOW(si->bp_how, si->bp_off, ctxs->reg[FP_REG] ); -# undef SUMMARISE_HOW - /* on x86/amd64, it seems the old %{e,r}sp value before the call is always the same as the CFA. Therefore ... */ si->sp_how = CFIR_CFAREL; @@ -2153,7 +2229,7 @@ static Bool summarise_context( /*OUT*/DiCfSI* si, /* also, gcc says "Undef" for %{e,r}bp when it is unchanged. So .. */ if (ctxs->reg[FP_REG].tag == RR_Undef) - si->fp_how = CFIR_SAME; + si->bp_how = CFIR_SAME; /* knock out some obviously stupid cases */ if (si->ra_how == CFIR_SAME) @@ -2171,6 +2247,69 @@ static Bool summarise_context( /*OUT*/DiCfSI* si, return True; +# elif defined(VGA_arm) + + /* ---- entire tail of this fn specialised for arm ---- */ + + SUMMARISE_HOW(si->r14_how, si->r14_off, + ctxs->reg[14] ); + + //SUMMARISE_HOW(si->r13_how, si->r13_off, + // ctxs->reg[13] ); + + SUMMARISE_HOW(si->r12_how, si->r12_off, + ctxs->reg[FP_REG] ); + + SUMMARISE_HOW(si->r11_how, si->r11_off, + ctxs->reg[11/*FP_REG*/] ); + + SUMMARISE_HOW(si->r7_how, si->r7_off, + ctxs->reg[7] ); + + if (ctxs->reg[14/*LR*/].tag == RR_Same + && ctx->ra_reg == 14/*as we expect it always to be*/) { + /* Generate a trivial CfiExpr, which merely says "r14". First + ensure this DebugInfo has a cfsi_expr array in which to park + it. */ + if (!debuginfo->cfsi_exprs) + debuginfo->cfsi_exprs = VG_(newXA)( ML_(dinfo_zalloc), + "di.ccCt.2a", + ML_(dinfo_free), + sizeof(CfiExpr) ); + si->ra_off = ML_(CfiExpr_CfiReg)( debuginfo->cfsi_exprs, + Creg_ARM_R14); + si->ra_how = CFIR_EXPR; + } else { + /* Just summarise it in the normal way */ + SUMMARISE_HOW(si->ra_how, si->ra_off, + ctxs->reg[ctx->ra_reg] ); + } + + /* on arm, it seems the old r13 (SP) value before the call is + always the same as the CFA. Therefore ... */ + si->r13_how = CFIR_CFAREL; + si->r13_off = 0; + + /* bogus looking range? Note, we require that the difference is + representable in 32 bits. */ + if (loc_start >= ctx->loc) + { why = 4; goto failed; } + if (ctx->loc - loc_start > 10000000 /* let's say */) + { why = 5; goto failed; } + + si->base = loc_start + ctx->initloc; + si->len = (UInt)(ctx->loc - loc_start); + + return True; + + +# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# else +# error "Unknown arch" +# endif + +# undef SUMMARISE_HOW + failed: if (VG_(clo_verbosity) > 2 || debuginfo->trace_cfi) { VG_(message)(Vg_DebugMsg, @@ -2223,12 +2362,24 @@ static Int copy_convert_CfiExpr_tree ( XArray* dstxa, case Cex_DwReg: /* This is the only place where the conversion can fail. */ dwreg = src->Cex.DwReg.reg; +# if defined(VGA_x86) || defined(VGA_amd64) + if (dwreg == SP_REG) + return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_SP ); + if (dwreg == FP_REG) + return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_BP ); + if (dwreg == srcuc->ra_reg) + return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP ); /* correct? */ +# elif defined(VGA_arm) if (dwreg == SP_REG) - return ML_(CfiExpr_CfiReg)( dstxa, Creg_SP ); + return ML_(CfiExpr_CfiReg)( dstxa, Creg_ARM_R13 ); if (dwreg == FP_REG) - return ML_(CfiExpr_CfiReg)( dstxa, Creg_FP ); + return ML_(CfiExpr_CfiReg)( dstxa, Creg_ARM_R12 ); if (dwreg == srcuc->ra_reg) - return ML_(CfiExpr_CfiReg)( dstxa, Creg_IP ); /* correct? */ + return ML_(CfiExpr_CfiReg)( dstxa, Creg_ARM_R15 ); /* correct? */ +# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# else +# error "Unknown arch" +# endif /* else we must fail - can't represent the reg */ return -1; default: @@ -2273,70 +2424,110 @@ static inline Bool host_is_little_endian ( void ) static Short read_Short ( UChar* data ) { Short r = 0; - vg_assert(host_is_little_endian()); - r = data[0] - | ( ((UInt)data[1]) << 8 ); + if (host_is_little_endian()) { + r = data[0] + | ( ((UInt)data[1]) << 8 ); + } else { + r = data[1] + | ( ((UInt)data[0]) << 8 ); + } return r; } static Int read_Int ( UChar* data ) { Int r = 0; - vg_assert(host_is_little_endian()); - r = data[0] - | ( ((UInt)data[1]) << 8 ) - | ( ((UInt)data[2]) << 16 ) - | ( ((UInt)data[3]) << 24 ); + if (host_is_little_endian()) { + r = data[0] + | ( ((UInt)data[1]) << 8 ) + | ( ((UInt)data[2]) << 16 ) + | ( ((UInt)data[3]) << 24 ); + } else { + r = data[3] + | ( ((UInt)data[2]) << 8 ) + | ( ((UInt)data[1]) << 16 ) + | ( ((UInt)data[0]) << 24 ); + } return r; } static Long read_Long ( UChar* data ) { Long r = 0; - vg_assert(host_is_little_endian()); - r = data[0] - | ( ((ULong)data[1]) << 8 ) - | ( ((ULong)data[2]) << 16 ) - | ( ((ULong)data[3]) << 24 ) - | ( ((ULong)data[4]) << 32 ) - | ( ((ULong)data[5]) << 40 ) - | ( ((ULong)data[6]) << 48 ) - | ( ((ULong)data[7]) << 56 ); + if (host_is_little_endian()) { + r = data[0] + | ( ((ULong)data[1]) << 8 ) + | ( ((ULong)data[2]) << 16 ) + | ( ((ULong)data[3]) << 24 ) + | ( ((ULong)data[4]) << 32 ) + | ( ((ULong)data[5]) << 40 ) + | ( ((ULong)data[6]) << 48 ) + | ( ((ULong)data[7]) << 56 ); + } else { + r = data[7] + | ( ((ULong)data[6]) << 8 ) + | ( ((ULong)data[5]) << 16 ) + | ( ((ULong)data[4]) << 24 ) + | ( ((ULong)data[3]) << 32 ) + | ( ((ULong)data[2]) << 40 ) + | ( ((ULong)data[1]) << 48 ) + | ( ((ULong)data[0]) << 56 ); + } return r; } static UShort read_UShort ( UChar* data ) { UInt r = 0; - vg_assert(host_is_little_endian()); - r = data[0] - | ( ((UInt)data[1]) << 8 ); + if (host_is_little_endian()) { + r = data[0] + | ( ((UInt)data[1]) << 8 ); + } else { + r = data[1] + | ( ((UInt)data[0]) << 8 ); + } return r; } static UInt read_UInt ( UChar* data ) { UInt r = 0; - vg_assert(host_is_little_endian()); - r = data[0] - | ( ((UInt)data[1]) << 8 ) - | ( ((UInt)data[2]) << 16 ) - | ( ((UInt)data[3]) << 24 ); + if (host_is_little_endian()) { + r = data[0] + | ( ((UInt)data[1]) << 8 ) + | ( ((UInt)data[2]) << 16 ) + | ( ((UInt)data[3]) << 24 ); + } else { + r = data[3] + | ( ((UInt)data[2]) << 8 ) + | ( ((UInt)data[1]) << 16 ) + | ( ((UInt)data[0]) << 24 ); + } return r; } static ULong read_ULong ( UChar* data ) { ULong r = 0; - vg_assert(host_is_little_endian()); - r = data[0] - | ( ((ULong)data[1]) << 8 ) - | ( ((ULong)data[2]) << 16 ) + if (host_is_little_endian()) { + r = data[0] + | ( ((ULong)data[1]) << 8 ) + | ( ((ULong)data[2]) << 16 ) | ( ((ULong)data[3]) << 24 ) - | ( ((ULong)data[4]) << 32 ) - | ( ((ULong)data[5]) << 40 ) - | ( ((ULong)data[6]) << 48 ) + | ( ((ULong)data[4]) << 32 ) + | ( ((ULong)data[5]) << 40 ) + | ( ((ULong)data[6]) << 48 ) | ( ((ULong)data[7]) << 56 ); + } else { + r = data[7] + | ( ((ULong)data[6]) << 8 ) + | ( ((ULong)data[5]) << 16 ) + | ( ((ULong)data[4]) << 24 ) + | ( ((ULong)data[3]) << 32 ) + | ( ((ULong)data[2]) << 40 ) + | ( ((ULong)data[1]) << 48 ) + | ( ((ULong)data[0]) << 56 ); + } return r; } @@ -2710,6 +2901,7 @@ static Int run_CF_instruction ( /*MOD*/UnwindContext* ctx, ctxs = &ctx->state[ctx->state_sp]; if (hi2 == DW_CFA_advance_loc) { delta = (UInt)lo6; + delta *= ctx->code_a_f; ctx->loc += delta; if (di->ddump_frames) VG_(printf)(" DW_CFA_advance_loc: %d to %08lx\n", @@ -2767,6 +2959,7 @@ static Int run_CF_instruction ( /*MOD*/UnwindContext* ctx, break; case DW_CFA_advance_loc1: delta = (UInt)read_UChar(&instr[i]); i+= sizeof(UChar); + delta *= ctx->code_a_f; ctx->loc += delta; if (di->ddump_frames) VG_(printf)(" DW_CFA_advance_loc1: %d to %08lx\n", @@ -2774,6 +2967,7 @@ static Int run_CF_instruction ( /*MOD*/UnwindContext* ctx, break; case DW_CFA_advance_loc2: delta = (UInt)read_UShort(&instr[i]); i+= sizeof(UShort); + delta *= ctx->code_a_f; ctx->loc += delta; if (di->ddump_frames) VG_(printf)(" DW_CFA_advance_loc2: %d to %08lx\n", @@ -2781,6 +2975,7 @@ static Int run_CF_instruction ( /*MOD*/UnwindContext* ctx, break; case DW_CFA_advance_loc4: delta = (UInt)read_UInt(&instr[i]); i+= sizeof(UInt); + delta *= ctx->code_a_f; ctx->loc += delta; if (di->ddump_frames) VG_(printf)(" DW_CFA_advance_loc4: %d to %08lx\n", @@ -2923,7 +3118,7 @@ static Int run_CF_instruction ( /*MOD*/UnwindContext* ctx, ctxs->cfa_reg = reg; /* ->cfa_off unchanged */ if (di->ddump_frames) - VG_(printf)(" DW_CFA_def_cfa_reg: r%d\n", (Int)reg ); + VG_(printf)(" DW_CFA_def_cfa_register: r%d\n", (Int)reg ); break; case DW_CFA_def_cfa_offset: @@ -3441,28 +3636,38 @@ static void init_CIE ( CIE* cie ) cie->saw_z_augmentation = False; } -#define N_CIEs 2000 +#define N_CIEs 4000 static CIE the_CIEs[N_CIEs]; void ML_(read_callframe_info_dwarf3) - ( /*OUT*/struct _DebugInfo* di, UChar* ehframe_image ) + ( /*OUT*/struct _DebugInfo* di, UChar* frame_image, SizeT frame_size, + Bool for_eh ) { Int nbytes; HChar* how = NULL; Int n_CIEs = 0; - UChar* data = ehframe_image; + UChar* data = frame_image; + UWord ehframe_cfsis = 0; + Addr frame_avma = for_eh ? di->ehframe_avma : 0; # if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) - /* These targets don't use CFI-based stack unwinding. */ + /* These targets don't use CFI-based stack unwinding. */ return; # endif + /* If we are reading .debug_frame after .eh_frame has been read, only + add FDEs which weren't covered in .eh_frame. To be able to quickly + search the FDEs, the records must be sorted. */ + if ( ! for_eh && di->ehframe_size && di->cfsi_used ) { + ML_(canonicaliseCFI) ( di ); + ehframe_cfsis = di->cfsi_used; + } + if (di->trace_cfi) { VG_(printf)("\n-----------------------------------------------\n"); VG_(printf)("CFI info: szB %ld, _avma %#lx, _image %p\n", - di->ehframe_size, di->ehframe_avma, - ehframe_image ); + frame_size, frame_avma, frame_image ); VG_(printf)("CFI info: name %s\n", di->filename ); } @@ -3495,11 +3700,11 @@ void ML_(read_callframe_info_dwarf3) Bool dw64; /* Are we done? */ - if (data == ehframe_image + di->ehframe_size) + if (data == frame_image + frame_size) return; /* Overshot the end? Means something is wrong */ - if (data > ehframe_image + di->ehframe_size) { + if (data > frame_image + frame_size) { how = "overran the end of .eh_frame"; goto bad; } @@ -3509,9 +3714,9 @@ void ML_(read_callframe_info_dwarf3) ciefde_start = data; if (di->trace_cfi) - VG_(printf)("\ncie/fde.start = %p (ehframe_image + 0x%lx)\n", + VG_(printf)("\ncie/fde.start = %p (frame_image + 0x%lx)\n", ciefde_start, - ciefde_start - ehframe_image + 0UL); + ciefde_start - frame_image + 0UL); ciefde_len = (ULong) read_UInt(data); data += sizeof(UInt); if (di->trace_cfi) @@ -3524,7 +3729,7 @@ void ML_(read_callframe_info_dwarf3) if (ciefde_len == 0) { if (di->ddump_frames) VG_(printf)("%08lx ZERO terminator\n\n", - ((Addr)ciefde_start) - ((Addr)ehframe_image)); + ((Addr)ciefde_start) - ((Addr)frame_image)); return; } @@ -3550,8 +3755,10 @@ void ML_(read_callframe_info_dwarf3) if (di->trace_cfi) VG_(printf)("cie.pointer = %lld\n", cie_pointer); - /* If cie_pointer is zero, we've got a CIE; else it's an FDE. */ - if (cie_pointer == 0) { + /* If cie_pointer is zero for .eh_frame or all ones for .debug_frame, + we've got a CIE; else it's an FDE. */ + if (cie_pointer == (for_eh ? 0ULL + : dw64 ? 0xFFFFFFFFFFFFFFFFULL : 0xFFFFFFFFULL)) { Int this_CIE; UChar cie_version; @@ -3575,11 +3782,11 @@ void ML_(read_callframe_info_dwarf3) /* Record its offset. This is how we will find it again later when looking at an FDE. */ - the_CIEs[this_CIE].offset = (ULong)(ciefde_start - ehframe_image); + the_CIEs[this_CIE].offset = (ULong)(ciefde_start - frame_image); if (di->ddump_frames) VG_(printf)("%08lx %08lx %08lx CIE\n", - ((Addr)ciefde_start) - ((Addr)ehframe_image), + ((Addr)ciefde_start) - ((Addr)frame_image), (Addr)ciefde_len, (Addr)(UWord)cie_pointer ); @@ -3588,8 +3795,8 @@ void ML_(read_callframe_info_dwarf3) VG_(printf)("cie.version = %d\n", (Int)cie_version); if (di->ddump_frames) VG_(printf)(" Version: %d\n", (Int)cie_version); - if (cie_version != 1 && cie_version != 3) { - how = "unexpected CIE version (not 1 nor 3)"; + if (cie_version != 1 && cie_version != 3 && cie_version != 4) { + how = "unexpected CIE version (not 1 nor 3 nor 4)"; goto bad; } @@ -3605,6 +3812,19 @@ void ML_(read_callframe_info_dwarf3) cie_augmentation += 2; } + if (cie_version >= 4) { + if (read_UChar(data) != sizeof(Addr)) { + how = "unexpected address size"; + goto bad; + } + data += sizeof(UChar); + if (read_UChar(data) != 0) { + how = "unexpected non-zero segment size"; + goto bad; + } + data += sizeof(UChar); + } + the_CIEs[this_CIE].code_a_f = read_leb128( data, &nbytes, 0); data += nbytes; if (di->trace_cfi) @@ -3623,8 +3843,13 @@ void ML_(read_callframe_info_dwarf3) VG_(printf)(" Data alignment factor: %d\n", (Int)the_CIEs[this_CIE].data_a_f); - the_CIEs[this_CIE].ra_reg = (Int)read_UChar(data); - data += sizeof(UChar); + if (cie_version == 1) { + the_CIEs[this_CIE].ra_reg = (Int)read_UChar(data); + data += sizeof(UChar); + } else { + the_CIEs[this_CIE].ra_reg = read_leb128( data, &nbytes, 0); + data += nbytes; + } if (di->trace_cfi) VG_(printf)("cie.ra_reg = %d\n", the_CIEs[this_CIE].ra_reg); @@ -3702,7 +3927,7 @@ void ML_(read_callframe_info_dwarf3) } if (the_CIEs[this_CIE].ilen < 0 - || the_CIEs[this_CIE].ilen > di->ehframe_size) { + || the_CIEs[this_CIE].ilen > frame_size) { how = "implausible # cie initial insns"; goto bad; } @@ -3717,8 +3942,8 @@ void ML_(read_callframe_info_dwarf3) if (di->trace_cfi || di->ddump_frames) { AddressDecodingInfo adi; adi.encoding = the_CIEs[this_CIE].address_encoding; - adi.ehframe_image = ehframe_image; - adi.ehframe_avma = di->ehframe_avma; + adi.ehframe_image = frame_image; + adi.ehframe_avma = frame_avma; adi.text_bias = di->text_debug_bias; show_CF_instructions( the_CIEs[this_CIE].instrs, the_CIEs[this_CIE].ilen, &adi, @@ -3747,9 +3972,12 @@ void ML_(read_callframe_info_dwarf3) cie_pointer bytes back from here. */ /* re sizeof(UInt) / sizeof(ULong), matches XXX above. */ - look_for = (data - (dw64 ? sizeof(ULong) : sizeof(UInt)) - - ehframe_image) - - cie_pointer; + if (for_eh) + look_for = (data - (dw64 ? sizeof(ULong) : sizeof(UInt)) + - frame_image) + - cie_pointer; + else + look_for = cie_pointer; for (cie = 0; cie < n_CIEs; cie++) { if (0) VG_(printf)("look for %lld %lld\n", @@ -3764,8 +3992,8 @@ void ML_(read_callframe_info_dwarf3) } adi.encoding = the_CIEs[cie].address_encoding; - adi.ehframe_image = ehframe_image; - adi.ehframe_avma = di->ehframe_avma; + adi.ehframe_image = frame_image; + adi.ehframe_avma = frame_avma; adi.text_bias = di->text_debug_bias; fde_initloc = read_encoded_Addr(&nbytes, &adi, data); data += nbytes; @@ -3773,8 +4001,8 @@ void ML_(read_callframe_info_dwarf3) VG_(printf)("fde.initloc = %#lx\n", fde_initloc); adi.encoding = the_CIEs[cie].address_encoding & 0xf; - adi.ehframe_image = ehframe_image; - adi.ehframe_avma = di->ehframe_avma; + adi.ehframe_image = frame_image; + adi.ehframe_avma = frame_avma; adi.text_bias = di->text_debug_bias; /* WAS (incorrectly): @@ -3800,7 +4028,7 @@ void ML_(read_callframe_info_dwarf3) if (di->ddump_frames) VG_(printf)("%08lx %08lx %08lx FDE cie=%08lx pc=%08lx..%08lx\n", - ((Addr)ciefde_start) - ((Addr)ehframe_image), + ((Addr)ciefde_start) - ((Addr)frame_image), (Addr)ciefde_len, (Addr)(UWord)cie_pointer, (Addr)look_for, @@ -3827,16 +4055,43 @@ void ML_(read_callframe_info_dwarf3) VG_(printf)("fde.ilen = %d\n", (Int)fde_ilen); } - if (fde_ilen < 0 || fde_ilen > di->ehframe_size) { + if (fde_ilen < 0 || fde_ilen > frame_size) { how = "implausible # fde insns"; goto bad; } data += fde_ilen; + if (ehframe_cfsis) { + Addr a_mid_lo, a_mid_hi; + Word mid, size, + lo = 0, + hi = ehframe_cfsis-1; + while (True) { + /* current unsearched space is from lo to hi, inclusive. */ + if (lo > hi) break; /* not found */ + mid = (lo + hi) / 2; + a_mid_lo = di->cfsi[mid].base; + size = di->cfsi[mid].len; + a_mid_hi = a_mid_lo + size - 1; + vg_assert(a_mid_hi >= a_mid_lo); + if (fde_initloc + fde_arange <= a_mid_lo) { + hi = mid-1; continue; + } + if (fde_initloc > a_mid_hi) { lo = mid+1; continue; } + break; + } + + /* The range this .debug_frame FDE covers has been already + covered in .eh_frame section. Don't add it from .debug_frame + section again. */ + if (lo <= hi) + continue; + } + adi.encoding = the_CIEs[cie].address_encoding; - adi.ehframe_image = ehframe_image; - adi.ehframe_avma = di->ehframe_avma; + adi.ehframe_image = frame_image; + adi.ehframe_avma = frame_avma; adi.text_bias = di->text_debug_bias; if (di->trace_cfi) diff --git a/coregrind/m_debuginfo/readdwarf3.c b/coregrind/m_debuginfo/readdwarf3.c index bbe2c72..3600cf5 100644 --- a/coregrind/m_debuginfo/readdwarf3.c +++ b/coregrind/m_debuginfo/readdwarf3.c @@ -1,6 +1,6 @@ /*--------------------------------------------------------------------*/ -/*--- Read DWARF3 ".debug_info" sections (DIE trees). ---*/ +/*--- Read DWARF3/4 ".debug_info" sections (DIE trees). ---*/ /*--- readdwarf3.c ---*/ /*--------------------------------------------------------------------*/ @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks LLP + Copyright (C) 2008-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -220,15 +220,6 @@ static UChar* get_address_of_Cursor ( Cursor* c ) { return &c->region_start_img[ c->region_next ]; } -__attribute__((noreturn)) -static void failWith ( Cursor* c, HChar* str ) { - vg_assert(c); - vg_assert(c->barf); - c->barf(str); - /*NOTREACHED*/ - vg_assert(0); -} - /* FIXME: document assumptions on endianness for get_UShort/UInt/ULong. */ static inline UChar get_UChar ( Cursor* c ) { @@ -387,7 +378,7 @@ typedef void (*barf)( HChar* ) __attribute__((noreturn)); /* Is this 64-bit DWARF ? */ Bool is_dw64; - /* Which DWARF version ? (2 or 3) */ + /* Which DWARF version ? (2, 3 or 4) */ UShort version; /* Length of this Compilation Unit, as stated in the .unit_length :: InitialLength field of the CU Header. @@ -805,8 +796,8 @@ void parse_CU_Header ( /*OUT*/CUConst* cc, /* version */ cc->version = get_UShort( c ); - if (cc->version != 2 && cc->version != 3) - cc->barf( "parse_CU_Header: is neither DWARF2 nor DWARF3" ); + if (cc->version != 2 && cc->version != 3 && cc->version != 4) + cc->barf( "parse_CU_Header: is neither DWARF2 nor DWARF3 nor DWARF4" ); TRACE_D3(" Version: %d\n", (Int)cc->version ); /* debug_abbrev_offset */ @@ -984,11 +975,21 @@ void get_Form_contents ( /*OUT*/ULong* cts, *ctsSzB = 8; TRACE_D3("%llu", *cts); break; + case DW_FORM_sec_offset: + *cts = (ULong)get_Dwarfish_UWord( c, cc->is_dw64 ); + *ctsSzB = cc->is_dw64 ? 8 : 4; + TRACE_D3("%llu", *cts); + break; case DW_FORM_sdata: *cts = (ULong)(Long)get_SLEB128(c); *ctsSzB = 8; TRACE_D3("%lld", (Long)*cts); break; + case DW_FORM_udata: + *cts = (ULong)(Long)get_ULEB128(c); + *ctsSzB = 8; + TRACE_D3("%llu", (Long)*cts); + break; case DW_FORM_addr: /* note, this is a hack. DW_FORM_addr is defined as getting a word the size of the target machine as defined by the @@ -1055,6 +1056,22 @@ void get_Form_contents ( /*OUT*/ULong* cts, *ctsMemSzB = 1 + (ULong)VG_(strlen)(str); break; } + case DW_FORM_ref1: { + UChar u8 = get_UChar(c); + UWord res = cc->cu_start_offset + (UWord)u8; + *cts = (ULong)res; + *ctsSzB = sizeof(UWord); + TRACE_D3("<%lx>", res); + break; + } + case DW_FORM_ref2: { + UShort u16 = get_UShort(c); + UWord res = cc->cu_start_offset + (UWord)u16; + *cts = (ULong)res; + *ctsSzB = sizeof(UWord); + TRACE_D3("<%lx>", res); + break; + } case DW_FORM_ref4: { UInt u32 = get_UInt(c); UWord res = cc->cu_start_offset + (UWord)u32; @@ -1063,6 +1080,22 @@ void get_Form_contents ( /*OUT*/ULong* cts, TRACE_D3("<%lx>", res); break; } + case DW_FORM_ref8: { + ULong u64 = get_ULong(c); + UWord res = cc->cu_start_offset + (UWord)u64; + *cts = (ULong)res; + *ctsSzB = sizeof(UWord); + TRACE_D3("<%lx>", res); + break; + } + case DW_FORM_ref_udata: { + ULong u64 = get_ULEB128(c); + UWord res = cc->cu_start_offset + (UWord)u64; + *cts = (ULong)res; + *ctsSzB = sizeof(UWord); + TRACE_D3("<%lx>", res); + break; + } case DW_FORM_flag: { UChar u8 = get_UChar(c); TRACE_D3("%u", (UInt)u8); @@ -1070,6 +1103,11 @@ void get_Form_contents ( /*OUT*/ULong* cts, *ctsSzB = 1; break; } + case DW_FORM_flag_present: + TRACE_D3("1"); + *cts = 1; + *ctsSzB = 1; + break; case DW_FORM_block1: { ULong u64b; ULong u64 = (ULong)get_UChar(c); @@ -1096,6 +1134,50 @@ void get_Form_contents ( /*OUT*/ULong* cts, *ctsMemSzB = (UWord)u64; break; } + case DW_FORM_block4: { + ULong u64b; + ULong u64 = (ULong)get_UInt(c); + UChar* block = get_address_of_Cursor(c); + TRACE_D3("%llu byte block: ", u64); + for (u64b = u64; u64b > 0; u64b--) { + UChar u8 = get_UChar(c); + TRACE_D3("%x ", (UInt)u8); + } + *cts = (ULong)(UWord)block; + *ctsMemSzB = (UWord)u64; + break; + } + case DW_FORM_exprloc: + case DW_FORM_block: { + ULong u64b; + ULong u64 = (ULong)get_ULEB128(c); + UChar* block = get_address_of_Cursor(c); + TRACE_D3("%llu byte block: ", u64); + for (u64b = u64; u64b > 0; u64b--) { + UChar u8 = get_UChar(c); + TRACE_D3("%x ", (UInt)u8); + } + *cts = (ULong)(UWord)block; + *ctsMemSzB = (UWord)u64; + break; + } + case DW_FORM_ref_sig8: { + ULong u64b; + UChar* block = get_address_of_Cursor(c); + TRACE_D3("8 byte signature: "); + for (u64b = 8; u64b > 0; u64b--) { + UChar u8 = get_UChar(c); + TRACE_D3("%x ", (UInt)u8); + } + *cts = (ULong)(UWord)block; + *ctsMemSzB = 8; + break; + } + case DW_FORM_indirect: + get_Form_contents (cts, ctsSzB, ctsMemSzB, cc, c, td3, + (DW_FORM)get_ULEB128(c)); + return; + default: VG_(printf)( "get_Form_contents: unhandled %d (%s) at <%lx>\n", @@ -1322,11 +1404,13 @@ void read_filename_table( /*MOD*/D3VarParser* parser, get_Initial_Length( &is_dw64, &c, "read_filename_table: invalid initial-length field" ); version = get_UShort( &c ); - if (version != 2 && version != 3) - cc->barf("read_filename_table: Only DWARF version 2 and 3 line info " + if (version != 2 && version != 3 && version != 4) + cc->barf("read_filename_table: Only DWARF version 2, 3 and 4 line info " "is currently supported."); /*header_length = (ULong)*/ get_Dwarfish_UWord( &c, is_dw64 ); /*minimum_instruction_length = */ get_UChar( &c ); + if (version >= 4) + /*maximum_operations_per_insn = */ get_UChar( &c ); /*default_is_stmt = */ get_UChar( &c ); /*line_base = (Char)*/ get_UChar( &c ); /*line_range = */ get_UChar( &c ); @@ -2025,7 +2109,7 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents, case DW_LANG_C89: case DW_LANG_C: case DW_LANG_C_plus_plus: case DW_LANG_ObjC: case DW_LANG_ObjC_plus_plus: case DW_LANG_UPC: - case DW_LANG_Upc: + case DW_LANG_Upc: case DW_LANG_C99: parser->language = 'C'; break; case DW_LANG_Fortran77: case DW_LANG_Fortran90: case DW_LANG_Fortran95: @@ -2033,8 +2117,8 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents, case DW_LANG_Ada83: case DW_LANG_Cobol74: case DW_LANG_Cobol85: case DW_LANG_Pascal83: case DW_LANG_Modula2: case DW_LANG_Java: - case DW_LANG_C99: case DW_LANG_Ada95: - case DW_LANG_PLI: case DW_LANG_D: + case DW_LANG_Ada95: case DW_LANG_PLI: + case DW_LANG_D: case DW_LANG_Python: case DW_LANG_Mips_Assembler: parser->language = '?'; break; default: @@ -2065,6 +2149,7 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents, if (attr == DW_AT_encoding && ctsSzB > 0) { switch (cts) { case DW_ATE_unsigned: case DW_ATE_unsigned_char: + case DW_ATE_UTF: /* since DWARF4, e.g. char16_t from C++ */ case DW_ATE_boolean:/* FIXME - is this correct? */ typeE.Te.TyBase.enc = 'U'; break; case DW_ATE_signed: case DW_ATE_signed_char: @@ -2356,9 +2441,16 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents, if (attr == DW_AT_type && ctsSzB > 0) { fieldE.Te.Field.typeR = (UWord)cts; } - if (attr == DW_AT_data_member_location && ctsMemSzB > 0) { + /* There are 2 different cases for DW_AT_data_member_location. + If it is a constant class attribute, it contains byte offset + from the beginning of the containing entity. + Otherwise it is a location expression. */ + if (attr == DW_AT_data_member_location && ctsSzB > 0) { + fieldE.Te.Field.nLoc = -1; + fieldE.Te.Field.pos.offset = cts; + } else if (attr == DW_AT_data_member_location && ctsMemSzB > 0) { fieldE.Te.Field.nLoc = (UWord)ctsMemSzB; - fieldE.Te.Field.loc + fieldE.Te.Field.pos.loc = ML_(dinfo_memdup)( "di.readdwarf3.ptD.member.2", (UChar*)(UWord)cts, (SizeT)fieldE.Te.Field.nLoc ); @@ -2385,13 +2477,14 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents, vg_assert(fieldE.Te.Field.name); if (fieldE.Te.Field.typeR == D3_INVALID_CUOFF) goto bad_DIE; - if (fieldE.Te.Field.loc) { + if (fieldE.Te.Field.nLoc) { if (!parent_is_struct) { /* If this is a union type, pretend we haven't seen the data member location expression, as it is by definition redundant (it must be zero). */ - ML_(dinfo_free)(fieldE.Te.Field.loc); - fieldE.Te.Field.loc = NULL; + if (fieldE.Te.Field.nLoc > 0) + ML_(dinfo_free)(fieldE.Te.Field.pos.loc); + fieldE.Te.Field.pos.loc = NULL; fieldE.Te.Field.nLoc = 0; } /* Record this child in the parent */ @@ -2616,10 +2709,10 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents, /* For union members, Expr should be absent */ if (0) VG_(printf)("YYYY Acquire Field\n"); vg_assert(fieldE.tag == Te_Field); - vg_assert( (fieldE.Te.Field.nLoc > 0 && fieldE.Te.Field.loc != NULL) - || (fieldE.Te.Field.nLoc == 0 && fieldE.Te.Field.loc == NULL) ); + vg_assert(fieldE.Te.Field.nLoc <= 0 || fieldE.Te.Field.pos.loc != NULL); + vg_assert(fieldE.Te.Field.nLoc != 0 || fieldE.Te.Field.pos.loc == NULL); if (fieldE.Te.Field.isStruct) { - vg_assert(fieldE.Te.Field.nLoc > 0); + vg_assert(fieldE.Te.Field.nLoc != 0); } else { vg_assert(fieldE.Te.Field.nLoc == 0); } @@ -3658,8 +3751,11 @@ void new_dwarf3_reader_wrk ( key.dioff = varp->absOri; /* this is what we want to find */ found = VG_(lookupXA)( dioff_lookup_tab, &keyp, &ixFirst, &ixLast ); - if (!found) - barf("DW_AT_abstract_origin can't be resolved"); + if (!found) { + /* barf("DW_AT_abstract_origin can't be resolved"); */ + TRACE_D3(" SKIP (DW_AT_abstract_origin can't be resolved)\n\n"); + continue; + } /* If the following fails, there is more than one entry with the same dioff. Which can't happen. */ vg_assert(ixFirst == ixLast); diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c index 316e191..aa23e72 100644 --- a/coregrind/m_debuginfo/readelf.c +++ b/coregrind/m_debuginfo/readelf.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -70,7 +70,9 @@ # define ElfXX_Ehdr Elf32_Ehdr # define ElfXX_Shdr Elf32_Shdr # define ElfXX_Phdr Elf32_Phdr +# define ElfXX_Nhdr Elf32_Nhdr # define ElfXX_Sym Elf32_Sym +# define ElfXX_Off Elf32_Off # define ElfXX_Word Elf32_Word # define ElfXX_Addr Elf32_Addr # define ElfXX_Dyn Elf32_Dyn @@ -81,7 +83,9 @@ # define ElfXX_Ehdr Elf64_Ehdr # define ElfXX_Shdr Elf64_Shdr # define ElfXX_Phdr Elf64_Phdr +# define ElfXX_Nhdr Elf64_Nhdr # define ElfXX_Sym Elf64_Sym +# define ElfXX_Off Elf64_Off # define ElfXX_Word Elf64_Word # define ElfXX_Addr Elf64_Addr # define ElfXX_Dyn Elf64_Dyn @@ -214,7 +218,8 @@ Bool get_elf_symbol_info ( used on entry */ Bool* from_opd_out, /* ppc64-linux only: did we deref an .opd entry? */ - Bool* is_text_out /* is this a text symbol? */ + Bool* is_text_out, /* is this a text symbol? */ + Bool* is_ifunc /* is this a STT_GNU_IFUNC function ?*/ ) { Bool plausible; @@ -232,6 +237,7 @@ Bool get_elf_symbol_info ( *sym_size_out = (Int)sym->st_size; *sym_tocptr_out = 0; /* unknown/inapplicable */ *from_opd_out = False; + *is_ifunc = False; /* Figure out if we're interested in the symbol. Firstly, is it of the right flavour? */ @@ -243,6 +249,9 @@ Bool get_elf_symbol_info ( && (ELFXX_ST_TYPE(sym->st_info) == STT_FUNC || ELFXX_ST_TYPE(sym->st_info) == STT_OBJECT +#ifdef STT_GNU_IFUNC + || ELFXX_ST_TYPE(sym->st_info) == STT_GNU_IFUNC +#endif ); /* Work out the svma and bias for each section as it will appear in @@ -325,6 +334,14 @@ Bool get_elf_symbol_info ( *sym_avma_out += text_bias; } +# ifdef STT_GNU_IFUNC + /* Check for indirect functions. */ + if (*is_text_out + && ELFXX_ST_TYPE(sym->st_info) == STT_GNU_IFUNC) { + *is_ifunc = True; + } +# endif + # if defined(VGP_ppc64_linux) /* Allow STT_NOTYPE in the very special case where we're running on ppc64-linux and the symbol is one which the .opd-chasing hack @@ -575,7 +592,7 @@ void read_elf_symtab__normal( Char *sym_name, *sym_name_really; Int sym_size; Addr sym_tocptr; - Bool from_opd, is_text; + Bool from_opd, is_text, is_ifunc; DiSym risym; ElfXX_Sym *sym; @@ -607,13 +624,14 @@ void read_elf_symtab__normal( &sym_avma_really, &sym_size, &sym_tocptr, - &from_opd, &is_text)) { - - risym.addr = sym_avma_really; - risym.size = sym_size; - risym.name = ML_(addStr) ( di, sym_name_really, -1 ); - risym.tocptr = sym_tocptr; - risym.isText = is_text; + &from_opd, &is_text, &is_ifunc)) { + + risym.addr = sym_avma_really; + risym.size = sym_size; + risym.name = ML_(addStr) ( di, sym_name_really, -1 ); + risym.tocptr = sym_tocptr; + risym.isText = is_text; + risym.isIFunc = is_ifunc; vg_assert(risym.name != NULL); vg_assert(risym.tocptr == 0); /* has no role except on ppc64-linux */ ML_(addSym) ( di, &risym ); @@ -651,6 +669,7 @@ typedef Int size; Bool from_opd; Bool is_text; + Bool is_ifunc; } TempSym; @@ -676,7 +695,7 @@ void read_elf_symtab__ppc64_linux( Char *sym_name, *sym_name_really; Int sym_size; Addr sym_tocptr; - Bool from_opd, modify_size, modify_tocptr, is_text; + Bool from_opd, modify_size, modify_tocptr, is_text, is_ifunc; DiSym risym; ElfXX_Sym *sym; OSet *oset; @@ -718,7 +737,7 @@ void read_elf_symtab__ppc64_linux( &sym_avma_really, &sym_size, &sym_tocptr, - &from_opd, &is_text)) { + &from_opd, &is_text, &is_ifunc)) { /* Check if we've seen this (name,addr) key before. */ key.addr = sym_avma_really; @@ -790,6 +809,7 @@ void read_elf_symtab__ppc64_linux( elem->size = sym_size; elem->from_opd = from_opd; elem->is_text = is_text; + elem->is_ifunc = is_ifunc; VG_(OSetGen_Insert)(oset, elem); if (di->trace_symtab) { VG_(printf)(" to-oset [%4ld]: " @@ -813,11 +833,12 @@ void read_elf_symtab__ppc64_linux( VG_(OSetGen_ResetIter)( oset ); while ( (elem = VG_(OSetGen_Next)(oset)) ) { - risym.addr = elem->key.addr; - risym.size = elem->size; - risym.name = ML_(addStr) ( di, elem->key.name, -1 ); - risym.tocptr = elem->tocptr; - risym.isText = elem->is_text; + risym.addr = elem->key.addr; + risym.size = elem->size; + risym.name = ML_(addStr) ( di, elem->key.name, -1 ); + risym.tocptr = elem->tocptr; + risym.isText = elem->is_text; + risym.isIFunc = elem->is_ifunc; vg_assert(risym.name != NULL); ML_(addSym) ( di, &risym ); @@ -839,6 +860,56 @@ void read_elf_symtab__ppc64_linux( } +/* + * Look for a build-id in an ELF image. The build-id specification + * can be found here: + * + * http://fedoraproject.org/wiki/RolandMcGrath/BuildID + */ +static +Char *find_buildid(Addr image, UWord n_image) +{ + Char* buildid = NULL; + ElfXX_Ehdr* ehdr = (ElfXX_Ehdr*)image; + +#ifdef NT_GNU_BUILD_ID + if (n_image >= sizeof(ElfXX_Ehdr) && + ML_(is_elf_object_file)(ehdr, n_image)) { + Word i; + + for (i = 0; i < ehdr->e_phnum; i++) { + ElfXX_Phdr* phdr = (ElfXX_Phdr*)(image + ehdr->e_phoff + i * ehdr->e_phentsize); + + if (phdr->p_type == PT_NOTE) { + ElfXX_Off offset = phdr->p_offset; + + while (offset < phdr->p_offset + phdr->p_filesz) { + ElfXX_Nhdr* note = (ElfXX_Nhdr*)(image + offset); + Char* name = (Char *)note + sizeof(ElfXX_Nhdr); + UChar *desc = (UChar *)name + ((note->n_namesz + 3) & ~3); + Word j; + + if (VG_(strcmp)(name, ELF_NOTE_GNU) == 0 && + note->n_type == NT_GNU_BUILD_ID) { + buildid = ML_(dinfo_zalloc)("di.fbi.1", note->n_descsz * 2 + 1); + + for (j = 0; j < note->n_descsz; j++) { + VG_(sprintf)(buildid + VG_(strlen)(buildid), "%02x", desc[j]); + } + } + + offset = offset + sizeof(ElfXX_Nhdr) + + ((note->n_namesz + 3) & ~3) + + ((note->n_descsz + 3) & ~3); + } + } + } + } +#endif + + return buildid; +} + /* * This routine for calculating the CRC for a separate debug file * is GPLed code borrowed from GNU binutils. @@ -914,7 +985,7 @@ calc_gnu_debuglink_crc32(UInt crc, const UChar *buf, Int len) * not match the value from the main object file. */ static -Addr open_debug_file( Char* name, UInt crc, /*OUT*/UWord* size ) +Addr open_debug_file( Char* name, Char* buildid, UInt crc, /*OUT*/UWord* size ) { SysRes fd, sres; struct vg_stat stat_buf; @@ -930,8 +1001,8 @@ Addr open_debug_file( Char* name, UInt crc, /*OUT*/UWord* size ) } if (VG_(clo_verbosity) > 1) - VG_(message)(Vg_DebugMsg, "Reading debug info from %s ..\n", name); - + VG_(message)(Vg_DebugMsg, " Considering %s ..\n", name); + *size = stat_buf.size; sres = VG_(am_mmap_file_float_valgrind) @@ -942,14 +1013,34 @@ Addr open_debug_file( Char* name, UInt crc, /*OUT*/UWord* size ) if (sr_isError(sres)) return 0; - calccrc = calc_gnu_debuglink_crc32(0, (UChar*)sr_Res(sres), *size); - if (calccrc != crc) { - SysRes res = VG_(am_munmap_valgrind)(sr_Res(sres), *size); - vg_assert(!sr_isError(res)); + if (buildid) { + Char* debug_buildid = find_buildid(sr_Res(sres), *size); + if (debug_buildid == NULL || VG_(strcmp)(buildid, debug_buildid) != 0) { + SysRes res = VG_(am_munmap_valgrind)(sr_Res(sres), *size); + vg_assert(!sr_isError(res)); + if (VG_(clo_verbosity) > 1) + VG_(message)(Vg_DebugMsg, + " .. build-id mismatch (found %s wanted %s)\n", debug_buildid, buildid); + ML_(dinfo_free)(debug_buildid); + return 0; + } + ML_(dinfo_free)(debug_buildid); + if (VG_(clo_verbosity) > 1) - VG_(message)(Vg_DebugMsg, - ".. CRC mismatch (computed %08x wanted %08x)\n", calccrc, crc); - return 0; + VG_(message)(Vg_DebugMsg, " .. build-id is valid\n"); + } else { + calccrc = calc_gnu_debuglink_crc32(0, (UChar*)sr_Res(sres), *size); + if (calccrc != crc) { + SysRes res = VG_(am_munmap_valgrind)(sr_Res(sres), *size); + vg_assert(!sr_isError(res)); + if (VG_(clo_verbosity) > 1) + VG_(message)(Vg_DebugMsg, + " .. CRC mismatch (computed %08x wanted %08x)\n", calccrc, crc); + return 0; + } + + if (VG_(clo_verbosity) > 1) + VG_(message)(Vg_DebugMsg, " .. CRC is valid\n"); } return sr_Res(sres); @@ -960,29 +1051,49 @@ Addr open_debug_file( Char* name, UInt crc, /*OUT*/UWord* size ) */ static Addr find_debug_file( struct _DebugInfo* di, - Char* objpath, Char* debugname, - UInt crc, /*OUT*/UWord* size ) + Char* objpath, Char* buildid, + Char* debugname, UInt crc, + /*OUT*/UWord* size ) { - Char *objdir = ML_(dinfo_strdup)("di.fdf.1", objpath); - Char *objdirptr; - Char *debugpath; + Char *debugpath = NULL; Addr addr = 0; - - if ((objdirptr = VG_(strrchr)(objdir, '/')) != NULL) - *objdirptr = '\0'; - debugpath = ML_(dinfo_zalloc)( - "di.fdf.2", - VG_(strlen)(objdir) + VG_(strlen)(debugname) + 32); - - VG_(sprintf)(debugpath, "%s/%s", objdir, debugname); + if (buildid != NULL) { + debugpath = ML_(dinfo_zalloc)( + "di.fdf.1", + VG_(strlen)(buildid) + 33); + + VG_(sprintf)(debugpath, "/usr/lib/debug/.build-id/%c%c/%s.debug", + buildid[0], buildid[1], buildid + 2); + + if ((addr = open_debug_file(debugpath, buildid, 0, size)) == 0) { + ML_(dinfo_free)(debugpath); + debugpath = NULL; + } + } + + if (addr == 0 && debugname != NULL) { + Char *objdir = ML_(dinfo_strdup)("di.fdf.2", objpath); + Char *objdirptr; + + if ((objdirptr = VG_(strrchr)(objdir, '/')) != NULL) + *objdirptr = '\0'; - if ((addr = open_debug_file(debugpath, crc, size)) == 0) { - VG_(sprintf)(debugpath, "%s/.debug/%s", objdir, debugname); - if ((addr = open_debug_file(debugpath, crc, size)) == 0) { - VG_(sprintf)(debugpath, "/usr/lib/debug%s/%s", objdir, debugname); - addr = open_debug_file(debugpath, crc, size); + debugpath = ML_(dinfo_zalloc)( + "di.fdf.3", + VG_(strlen)(objdir) + VG_(strlen)(debugname) + 32); + + VG_(sprintf)(debugpath, "%s/%s", objdir, debugname); + + if ((addr = open_debug_file(debugpath, NULL, crc, size)) == 0) { + VG_(sprintf)(debugpath, "%s/.debug/%s", objdir, debugname); + if ((addr = open_debug_file(debugpath, NULL, crc, size)) == 0) { + VG_(sprintf)(debugpath, "/usr/lib/debug%s/%s", objdir, debugname); + addr = open_debug_file(debugpath, NULL, crc, size); + } } + + ML_(dinfo_free)(objdir); } if (addr) { @@ -991,8 +1102,7 @@ Addr find_debug_file( struct _DebugInfo* di, } ML_(dinfo_free)(debugpath); - ML_(dinfo_free)(objdir); - + return addr; } @@ -1050,6 +1160,8 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) Bool res, ok; SysRes fd, sres; Word i; + Bool dynbss_present = False; + Bool sdynbss_present = False; /* Image addresses for the ELF file we're working with. */ Addr oimage = 0; @@ -1083,6 +1195,9 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) Addr rw_svma_limit = 0; PtrdiffT rw_bias = 0; + /* Build ID */ + Char* buildid = NULL; + vg_assert(di); vg_assert(di->have_rx_map == True); vg_assert(di->have_rw_map == True); @@ -1479,8 +1594,40 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) } } + if (0 == VG_(strcmp)(name, ".dynbss")) { + if (inrw && size > 0 && !di->bss_present) { + dynbss_present = True; + di->bss_present = True; + di->bss_svma = svma; + di->bss_avma = svma + rw_bias; + di->bss_size = size; + di->bss_bias = rw_bias; + di->bss_debug_svma = svma; + di->bss_debug_bias = rw_bias; + TRACE_SYMTAB("acquiring .dynbss svma = %#lx .. %#lx\n", + di->bss_svma, + di->bss_svma + di->bss_size - 1); + TRACE_SYMTAB("acquiring .dynbss avma = %#lx .. %#lx\n", + di->bss_avma, + di->bss_avma + di->bss_size - 1); + TRACE_SYMTAB("acquiring .dynbss bias = %#lx\n", di->bss_bias); + } + } + /* Accept .bss where mapped as rw (data), even if zero-sized */ if (0 == VG_(strcmp)(name, ".bss")) { + if (inrw && size > 0 && dynbss_present) { + vg_assert(di->bss_present); + dynbss_present = False; + vg_assert(di->bss_svma + di->bss_size == svma); + di->bss_size += size; + TRACE_SYMTAB("acquiring .bss svma = %#lx .. %#lx\n", + svma, svma + size - 1); + TRACE_SYMTAB("acquiring .bss avma = %#lx .. %#lx\n", + svma + rw_bias, svma + rw_bias + size - 1); + TRACE_SYMTAB("acquiring .bss bias = %#lx\n", di->bss_bias); + } else + if (inrw && size >= 0 && !di->bss_present) { di->bss_present = True; di->bss_svma = svma; @@ -1532,8 +1679,40 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) } } + if (0 == VG_(strcmp)(name, ".sdynbss")) { + if (inrw && size >= 0 && !di->sbss_present) { + sdynbss_present = True; + di->sbss_present = True; + di->sbss_svma = svma; + di->sbss_avma = svma + rw_bias; + di->sbss_size = size; + di->sbss_bias = rw_bias; + di->sbss_debug_svma = svma; + di->sbss_debug_bias = rw_bias; + TRACE_SYMTAB("acquiring .sdynbss svma = %#lx .. %#lx\n", + di->sbss_svma, + di->sbss_svma + di->sbss_size - 1); + TRACE_SYMTAB("acquiring .sdynbss avma = %#lx .. %#lx\n", + di->sbss_avma, + di->sbss_avma + di->sbss_size - 1); + TRACE_SYMTAB("acquiring .sdynbss bias = %#lx\n", di->sbss_bias); + } + } + /* Accept .sbss where mapped as rw (data) */ if (0 == VG_(strcmp)(name, ".sbss")) { + if (inrw && size > 0 && sdynbss_present) { + vg_assert(di->sbss_present); + sdynbss_present = False; + vg_assert(di->sbss_svma + di->sbss_size == svma); + di->sbss_size += size; + TRACE_SYMTAB("acquiring .sbss svma = %#lx .. %#lx\n", + svma, svma + size - 1); + TRACE_SYMTAB("acquiring .sbss avma = %#lx .. %#lx\n", + svma + rw_bias, svma + rw_bias + size - 1); + TRACE_SYMTAB("acquiring .sbss bias = %#lx\n", di->sbss_bias); + } else + if (inrw && size > 0 && !di->sbss_present) { di->sbss_present = True; di->sbss_svma = svma; @@ -1580,7 +1759,8 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) /* PLT is different on different platforms, it seems. */ # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) || \ - defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) + defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) \ + || defined(VGP_arm_linux) /* Accept .plt where mapped as rx (code) */ if (0 == VG_(strcmp)(name, ".plt")) { if (inrx && size > 0 && !di->plt_present) { @@ -1695,6 +1875,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) UChar* debug_str_img = NULL; /* .debug_str (dwarf2) */ UChar* debug_ranges_img = NULL; /* .debug_ranges (dwarf2) */ UChar* debug_loc_img = NULL; /* .debug_loc (dwarf2) */ + UChar* debug_frame_img = NULL; /* .debug_frame (dwarf2) */ UChar* dwarf1d_img = NULL; /* .debug (dwarf1) */ UChar* dwarf1l_img = NULL; /* .line (dwarf1) */ UChar* ehframe_img = NULL; /* .eh_frame (dwarf2) */ @@ -1714,6 +1895,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) SizeT debug_str_sz = 0; SizeT debug_ranges_sz = 0; SizeT debug_loc_sz = 0; + SizeT debug_frame_sz = 0; SizeT dwarf1d_sz = 0; SizeT dwarf1l_sz = 0; SizeT ehframe_sz = 0; @@ -1771,6 +1953,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) FIND(".debug_str", debug_str_sz, debug_str_img) FIND(".debug_ranges", debug_ranges_sz, debug_ranges_img) FIND(".debug_loc", debug_loc_sz, debug_loc_img) + FIND(".debug_frame", debug_frame_sz, debug_frame_img) FIND(".debug", dwarf1d_sz, dwarf1d_img) FIND(".line", dwarf1l_sz, dwarf1l_img) @@ -1780,20 +1963,31 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) # undef FIND } - - /* Did we find a debuglink section? */ - if (debuglink_img != NULL) { - UInt crc_offset = VG_ROUNDUP(VG_(strlen)(debuglink_img)+1, 4); - UInt crc; - vg_assert(crc_offset + sizeof(UInt) <= debuglink_sz); + /* Look for a build-id */ + buildid = find_buildid(oimage, n_oimage); + + /* Look for a debug image */ + if (buildid != NULL || debuglink_img != NULL) { + /* Do have a debuglink section? */ + if (debuglink_img != NULL) { + UInt crc_offset = VG_ROUNDUP(VG_(strlen)(debuglink_img)+1, 4); + UInt crc; - /* Extract the CRC from the debuglink section */ - crc = *(UInt *)(debuglink_img + crc_offset); + vg_assert(crc_offset + sizeof(UInt) <= debuglink_sz); - /* See if we can find a matching debug file */ - dimage = find_debug_file( di, di->filename, debuglink_img, - crc, &n_dimage ); + /* Extract the CRC from the debuglink section */ + crc = *(UInt *)(debuglink_img + crc_offset); + + /* See if we can find a matching debug file */ + dimage = find_debug_file( di, di->filename, buildid, + debuglink_img, crc, &n_dimage ); + } else { + /* See if we can find a matching debug file */ + dimage = find_debug_file( di, di->filename, buildid, NULL, 0, &n_dimage ); + } + + ML_(dinfo_free)(buildid); if (dimage != 0 && n_dimage >= sizeof(ElfXX_Ehdr) @@ -1963,6 +2157,8 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) FIND(need_dwarf2, ".debug_ranges", debug_ranges_sz, debug_ranges_img) FIND(need_dwarf2, ".debug_loc", debug_loc_sz, debug_loc_img) + FIND(need_dwarf2, ".debug_frame", debug_frame_sz, + debug_frame_img) FIND(need_dwarf1, ".debug", dwarf1d_sz, dwarf1d_img) FIND(need_dwarf1, ".line", dwarf1l_sz, dwarf1l_img) @@ -2000,10 +2196,14 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) False, opd_img); } - /* Read .eh_frame (call-frame-info) if any */ + /* Read .eh_frame and .debug_frame (call-frame-info) if any */ if (ehframe_img) { vg_assert(ehframe_sz == di->ehframe_size); - ML_(read_callframe_info_dwarf3)( di, ehframe_img ); + ML_(read_callframe_info_dwarf3)( di, ehframe_img, ehframe_sz, True ); + } + if (debug_frame_sz) { + ML_(read_callframe_info_dwarf3)( di, debug_frame_img, + debug_frame_sz, False ); } /* Read the stabs and/or dwarf2 debug information, if any. It diff --git a/coregrind/m_debuginfo/readmacho.c b/coregrind/m_debuginfo/readmacho.c index 9ecf64c..68ba359 100644 --- a/coregrind/m_debuginfo/readmacho.c +++ b/coregrind/m_debuginfo/readmacho.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Apple Inc. + Copyright (C) 2005-2010 Apple Inc. Greg Parker gparker@apple.com This program is free software; you can redistribute it and/or @@ -369,6 +369,7 @@ void read_symtab( /*OUT*/XArray* /* DiSym */ syms, di->text_avma+di->text_size - sym_addr; risym.name = ML_(addStr)(di, name, -1); risym.isText = True; + risym.isIFunc = False; // Lots of user function names get prepended with an underscore. Eg. the // function 'f' becomes the symbol '_f'. And the "below main" // function is called "start". So we skip the leading underscore, and @@ -947,10 +948,12 @@ Bool ML_(read_macho_debug_info)( struct _DebugInfo* di ) HChar* cmd = ML_(dinfo_zalloc)( "di.readmacho.tmp1", VG_(strlen)(dsymutil) + VG_(strlen)(di->filename) - + 30 /* misc */ ); + + 32 /* misc */ ); VG_(strcpy)(cmd, dsymutil); if (0) VG_(strcat)(cmd, "--verbose "); + VG_(strcat)(cmd, "\""); VG_(strcat)(cmd, di->filename); + VG_(strcat)(cmd, "\""); VG_(message)(Vg_DebugMsg, "run: %s\n", cmd); r = VG_(system)( cmd ); if (r) diff --git a/coregrind/m_debuginfo/readpdb.c b/coregrind/m_debuginfo/readpdb.c index 42badfe..c5a7a9a 100644 --- a/coregrind/m_debuginfo/readpdb.c +++ b/coregrind/m_debuginfo/readpdb.c @@ -42,7 +42,9 @@ #include "pub_core_vki.h" // VKI_PAGE_SIZE #include "pub_core_libcbase.h" #include "pub_core_libcassert.h" +#include "pub_core_libcfile.h" // VG_(open), read, lseek, close #include "pub_core_libcprint.h" +#include "pub_core_libcproc.h" // VG_(getpid), system #include "pub_core_options.h" // VG_(clo_verbosity) #include "pub_core_xarray.h" // keeps priv_storage.h happy #include "pub_core_redir.h" @@ -70,23 +72,36 @@ To complicate matters further, Wine supplies us, via the VG_USERREQ__LOAD_PDB_DEBUGINFO client request that initiates PDB - reading, a value 'reloc' which, if you read 'virtual.c' in the Wine - sources, looks a lot like a text bias value. Yet the code below - ignores it. + reading, a value 'unknown_purpose__reloc' which, if you read + 'virtual.c' in the Wine sources, looks a lot like a text bias + value. Yet the code below ignores it. To make future experimentation with biasing easier, here are four macros which give the bias to use in each of the four cases. Be warned, they can and do refer to local vars in the relevant functions. */ -/* This is the biasing arrangement in John's original patch. I don't - see that is makes any sense for the FPO bias to be hardwired to - zero, but perhaps that's OK when the reloc value is also zero. - (iow, the FPO bias should actually be 'reloc' ?) */ +/* The BIAS_FOR_{SYMBOLS,LINETAB,LINETAB2} are as in JohnR's original + patch. BIAS_FOR_FPO was originally hardwired to zero, but that + doesn't make much sense. Here, we use text_bias as empirically + producing the most ranges that fall inside the text segments for a + multi-dll program. Of course, it could still be nonsense :-) */ #define BIAS_FOR_SYMBOLS (di->rx_map_avma) #define BIAS_FOR_LINETAB (di->rx_map_avma) #define BIAS_FOR_LINETAB2 (di->text_bias) -#define BIAS_FOR_FPO 0 /* no, really */ +#define BIAS_FOR_FPO (di->text_bias) +/* Using di->text_bias for the FPOs causes 981 in range and 1 out of + range. Using rx_map_avma gives 953 in range and 29 out of range, + so di->text_bias looks like a better bet.: + $ grep FPO spew-B-text_bias | grep keep | wc + 981 4905 57429 + $ grep FPO spew-B-text_bias | grep SKIP | wc + 1 5 53 + $ grep FPO spew-B-rx_map_avma | grep keep | wc + 953 4765 55945 + $ grep FPO spew-B-rx_map_avma | grep SKIP | wc + 29 145 1537 +*/ /* This module leaks space; enable m_main's calling of VG_(di_discard_ALL_debuginfo)() at shutdown and run with @@ -982,6 +997,11 @@ static void* pdb_ds_read( struct pdb_reader* pdb, UInt i; if (!size) return NULL; + if (size > 512 * 1024 * 1024) { + VG_(umsg)("Warning: pdb_ds_read: implausible size " + "(%u); skipping -- possible invalid .pdb file?\n", size); + return NULL; + } blocksize = pdb->u.ds.header->block_size; nBlocks = (size + blocksize - 1) / blocksize; @@ -1201,8 +1221,6 @@ static void pdb_convert_symbols_header( PDB_SYMBOLS *symbols, /*--- ---*/ /*------------------------------------------------------------*/ -static Bool debug = False; // JRS: fixme - static ULong DEBUG_SnarfCodeView( DebugInfo* di, IMAGE_SECTION_HEADER* sectp, @@ -1216,12 +1234,13 @@ static ULong DEBUG_SnarfCodeView( UChar* nmstr; Char symname[4096 /*WIN32_PATH_MAX*/]; + Bool debug = di->trace_symtab; Addr bias = BIAS_FOR_SYMBOLS; ULong n_syms_read = 0; if (debug) VG_(message)(Vg_UserMsg, - "SnarfCodeView addr=%p offset=%d length=%d\n", + "BEGIN SnarfCodeView addr=%p offset=%d length=%d\n", root, offset, size ); VG_(memset)(&vsym, 0, sizeof(vsym)); /* avoid holes */ @@ -1262,7 +1281,7 @@ static ULong DEBUG_SnarfCodeView( symname[sym->data_v1.p_name.namelen] = '\0'; if (debug) - VG_(message)(Vg_UserMsg, "Data %s\n", symname ); + VG_(message)(Vg_UserMsg, " Data %s\n", symname ); if (0 /*VG_(needs).data_syms*/) { nmstr = ML_(addStr)(di, symname, sym->data_v1.p_name.namelen); @@ -1273,6 +1292,7 @@ static ULong DEBUG_SnarfCodeView( vsym.size = sym->data_v1.p_name.namelen; // FIXME: .namelen is sizeof(.data) including .name[] vsym.isText = (sym->generic.id == S_PUB_V1); + vsym.isIFunc = False; ML_(addSym)( di, &vsym ); n_syms_read++; } @@ -1286,7 +1306,7 @@ static ULong DEBUG_SnarfCodeView( if (debug) VG_(message)(Vg_UserMsg, - "S_GDATA_V2/S_LDATA_V2/S_PUB_V2 %s\n", symname ); + " S_GDATA_V2/S_LDATA_V2/S_PUB_V2 %s\n", symname ); if (sym->generic.id==S_PUB_V2 /*VG_(needs).data_syms*/) { nmstr = ML_(addStr)(di, symname, k); @@ -1299,6 +1319,7 @@ static ULong DEBUG_SnarfCodeView( // not size of function! vsym.isText = !!(IMAGE_SCN_CNT_CODE & sectp[sym->data_v2.segment-1].Characteristics); + vsym.isIFunc = False; ML_(addSym)( di, &vsym ); n_syms_read++; } @@ -1316,7 +1337,7 @@ static ULong DEBUG_SnarfCodeView( if (debug) VG_(message)(Vg_UserMsg, - "S_PUB_FUNC1_V3/S_PUB_FUNC2_V3/S_PUB_V3 %s\n", + " S_PUB_FUNC1_V3/S_PUB_FUNC2_V3/S_PUB_V3 %s\n", symname ); if (1 /*sym->generic.id==S_PUB_FUNC1_V3 @@ -1331,6 +1352,7 @@ static ULong DEBUG_SnarfCodeView( // .text of the function vsym.isText = !!(IMAGE_SCN_CNT_CODE & sectp[sym->data_v2.segment-1].Characteristics); + vsym.isIFunc = False; ML_(addSym)( di, &vsym ); n_syms_read++; } @@ -1362,9 +1384,10 @@ static ULong DEBUG_SnarfCodeView( vsym.name = nmstr; vsym.size = sym->proc_v1.proc_len; vsym.isText = True; + vsym.isIFunc = False; if (debug) VG_(message)(Vg_UserMsg, - "Adding function %s addr=%#lx length=%d\n", + " Adding function %s addr=%#lx length=%d\n", symname, vsym.addr, vsym.size ); ML_(addSym)( di, &vsym ); n_syms_read++; @@ -1382,9 +1405,10 @@ static ULong DEBUG_SnarfCodeView( vsym.name = nmstr; vsym.size = sym->proc_v2.proc_len; vsym.isText = True; + vsym.isIFunc = False; if (debug) VG_(message)(Vg_UserMsg, - "Adding function %s addr=%#lx length=%d\n", + " Adding function %s addr=%#lx length=%d\n", symname, vsym.addr, vsym.size ); ML_(addSym)( di, &vsym ); n_syms_read++; @@ -1393,7 +1417,7 @@ static ULong DEBUG_SnarfCodeView( case S_GPROC_V3: { if (debug) VG_(message)(Vg_UserMsg, - "S_LPROC_V3/S_GPROC_V3 %s\n", sym->proc_v3.name ); + " S_LPROC_V3/S_GPROC_V3 %s\n", sym->proc_v3.name ); if (1) { nmstr = ML_(addStr)(di, sym->proc_v3.name, @@ -1404,6 +1428,7 @@ static ULong DEBUG_SnarfCodeView( vsym.name = nmstr; vsym.size = sym->proc_v3.proc_len; vsym.isText = 1; + vsym.isIFunc = False; ML_(addSym)( di, &vsym ); n_syms_read++; } @@ -1477,6 +1502,10 @@ static ULong DEBUG_SnarfCodeView( } /* for ( i = offset; i < size; i += length ) */ + if (debug) + VG_(message)(Vg_UserMsg, + "END SnarfCodeView addr=%p offset=%d length=%d\n", + root, offset, size ); return n_syms_read; } @@ -1523,9 +1552,15 @@ static ULong DEBUG_SnarfLinetab( struct startend * start; Int this_seg; + Bool debug = di->trace_symtab; Addr bias = BIAS_FOR_LINETAB; ULong n_lines_read = 0; + if (debug) + VG_(message)(Vg_UserMsg, + "BEGIN SnarfLineTab linetab=%p size=%d\n", + linetab, size ); + /* * Now get the important bits. */ @@ -1594,7 +1629,7 @@ static ULong DEBUG_SnarfLinetab( if (debug) VG_(message)(Vg_UserMsg, - "Adding %d lines for file %s segment %d addr=%#x end=%#x\n", + " Adding %d lines for file %s segment %d addr=%#x end=%#x\n", linecount, filename, segno, start[k].start, start[k].end ); for ( j = 0; j < linecount; j++ ) { @@ -1606,7 +1641,7 @@ static ULong DEBUG_SnarfLinetab( : start[k].end); if (debug) VG_(message)(Vg_UserMsg, - "Adding line %d addr=%#lx end=%#lx\n", + " Adding line %d addr=%#lx end=%#lx\n", ((unsigned short *)(pnt2.ui + linecount))[j], startaddr, endaddr ); ML_(addLineInfo)( @@ -1618,6 +1653,11 @@ static ULong DEBUG_SnarfLinetab( } } + if (debug) + VG_(message)(Vg_UserMsg, + "END SnarfLineTab linetab=%p size=%d\n", + linetab, size ); + return n_lines_read; } @@ -1673,8 +1713,8 @@ static ULong codeview_dump_linetab2( unsigned i; struct codeview_linetab2_block* lbh; struct codeview_linetab2_file* fd; - //const Bool debug = False; + Bool debug = di->trace_symtab; Addr bias = BIAS_FOR_LINETAB2; ULong n_line2s_read = 0; @@ -1771,11 +1811,26 @@ static ULong codeview_dump_linetab2( /*--- ---*/ /*------------------------------------------------------------*/ +static Int cmp_FPO_DATA_for_canonicalisation ( void* f1V, void* f2V ) +{ + /* Cause FPO data to be sorted first in ascending order of range + starts, and for entries with the same range start, with the + shorter range (length) first. */ + FPO_DATA* f1 = (FPO_DATA*)f1V; + FPO_DATA* f2 = (FPO_DATA*)f2V; + if (f1->ulOffStart < f2->ulOffStart) return -1; + if (f1->ulOffStart > f2->ulOffStart) return 1; + if (f1->cbProcSize < f2->cbProcSize) return -1; + if (f1->cbProcSize > f2->cbProcSize) return 1; + return 0; /* identical in both start and length */ +} + + /* JRS fixme: compare with version in current Wine sources */ static void pdb_dump( struct pdb_reader* pdb, DebugInfo* di, Addr pe_avma, - Int reloc, + Int unknown_purpose__reloc, IMAGE_SECTION_HEADER* sectp_avma ) { Int header_size; @@ -1786,6 +1841,7 @@ static void pdb_dump( struct pdb_reader* pdb, char *modimage; char *file; + Bool debug = di->trace_symtab; Addr bias_for_fpo = BIAS_FOR_FPO; ULong n_fpos_read = 0, n_syms_read = 0, @@ -1813,7 +1869,7 @@ static void pdb_dump( struct pdb_reader* pdb, } } - if (VG_(clo_verbosity) > 0) { + if (VG_(clo_verbosity) > 1) { VG_(message)(Vg_DebugMsg, "PDB_READER:\n"); VG_(message)(Vg_DebugMsg, @@ -1830,7 +1886,7 @@ static void pdb_dump( struct pdb_reader* pdb, (PtrdiffT)BIAS_FOR_FPO, VG_STRINGIFY(BIAS_FOR_FPO)); VG_(message)(Vg_DebugMsg, " RELOC = %#08lx\n", - (PtrdiffT)reloc); + (PtrdiffT)unknown_purpose__reloc); } /* Since we just use the FPO data without reformatting, at least @@ -1841,76 +1897,162 @@ static void pdb_dump( struct pdb_reader* pdb, meaningless?) */ unsigned sz = 0; di->fpo = pdb->read_file( pdb, 5, &sz ); + + // FIXME: seems like the size can be a non-integral number + // of FPO_DATAs. Force-align it (moronically). Perhaps this + // signifies that we're not looking at a valid FPO table .. + // who knows. Needs investigation. + while (sz > 0 && (sz % sizeof(FPO_DATA)) != 0) + sz--; + di->fpo_size = sz; + if (0) VG_(printf)("FPO: got fpo_size %lu\n", (UWord)sz); + vg_assert(0 == (di->fpo_size % sizeof(FPO_DATA))); } else { vg_assert(di->fpo == NULL); vg_assert(di->fpo_size == 0); } - if (di->fpo) { - Word i; - Addr min_svma = ~(Addr)0; - Addr max_svma = (Addr)0; + // BEGIN clean up FPO data + if (di->fpo && di->fpo_size > 0) { + Word i, j; + Bool anyChanges; + Int itersAvail = 10; + vg_assert(sizeof(di->fpo[0]) == 16); di->fpo_size /= sizeof(di->fpo[0]); - /* Sanity-check the table, and find the min and max avmas. */ + // BEGIN FPO-data tidying-up loop + do { + + vg_assert(itersAvail >= 0); /* safety check -- don't loop forever */ + itersAvail--; + + anyChanges = False; + + /* First get them in ascending order of start point */ + VG_(ssort)( di->fpo, (SizeT)di->fpo_size, (SizeT)sizeof(FPO_DATA), + cmp_FPO_DATA_for_canonicalisation ); + /* Get rid of any zero length entries */ + j = 0; + for (i = 0; i < di->fpo_size; i++) { + if (di->fpo[i].cbProcSize == 0) { + anyChanges = True; + continue; + } + di->fpo[j++] = di->fpo[i]; + } + vg_assert(j >= 0 && j <= di->fpo_size); + di->fpo_size = j; + + /* Get rid of any dups */ + if (di->fpo_size > 1) { + j = 1; + for (i = 1; i < di->fpo_size; i++) { + Bool dup + = di->fpo[j-1].ulOffStart == di->fpo[i].ulOffStart + && di->fpo[j-1].cbProcSize == di->fpo[i].cbProcSize; + if (dup) { + anyChanges = True; + continue; + } + di->fpo[j++] = di->fpo[i]; + } + vg_assert(j >= 0 && j <= di->fpo_size); + di->fpo_size = j; + } + + /* Truncate any overlapping ranges */ + for (i = 1; i < di->fpo_size; i++) { + vg_assert(di->fpo[i-1].ulOffStart <= di->fpo[i].ulOffStart); + if (di->fpo[i-1].ulOffStart + di->fpo[i-1].cbProcSize + > di->fpo[i].ulOffStart) { + anyChanges = True; + di->fpo[i-1].cbProcSize + = di->fpo[i].ulOffStart - di->fpo[i-1].ulOffStart; + } + } + + } while (anyChanges); + // END FPO-data tidying-up loop + + /* Should now be in ascending order, non overlapping, no zero ranges. + Check this, get the min and max avmas, and bias the entries. */ for (i = 0; i < di->fpo_size; i++) { - /* If any of the following assertions fail, we'll need to add - an extra pass to tidy up the FPO info -- make them be in - order and non-overlapping, since in-orderness and - non-overlappingness are required for safe use of - ML_(search_one_fpotab). */ vg_assert(di->fpo[i].cbProcSize > 0); - if (i > 0) { - Bool ok; - Bool dup - = di->fpo[i-1].ulOffStart == di->fpo[i].ulOffStart - && di->fpo[i-1].cbProcSize == di->fpo[i].cbProcSize; - /* tolerate exact duplicates -- I think they are harmless - w.r.t. termination properties of the binary search in - ML_(search_one_fpotab). */ - if (dup) - continue; - ok = di->fpo[i-1].ulOffStart + di->fpo[i-1].cbProcSize - <= di->fpo[i].ulOffStart; - if (1 && !ok) - VG_(printf)("%#x +%d then %#x +%d\n", - di->fpo[i-1].ulOffStart, di->fpo[i-1].cbProcSize, - di->fpo[i-0].ulOffStart, di->fpo[i-0].cbProcSize ); - vg_assert(ok); + if (i > 0) { + vg_assert(di->fpo[i-1].ulOffStart < di->fpo[i].ulOffStart); + vg_assert(di->fpo[i-1].ulOffStart + di->fpo[i-1].cbProcSize + <= di->fpo[i].ulOffStart); } - /* Update min/max limits as we go along. */ - if (di->fpo[i].ulOffStart < min_svma) - min_svma = di->fpo[i].ulOffStart; - if (di->fpo[i].ulOffStart + di->fpo[i].cbProcSize - 1 > max_svma) - max_svma = di->fpo[i].ulOffStart + di->fpo[i].cbProcSize - 1; } + /* Now bias the table. This can't be done in the same pass as the sanity check, hence a second loop. */ for (i = 0; i < di->fpo_size; i++) { di->fpo[i].ulOffStart += bias_for_fpo; + // make sure the biasing didn't royally screw up, by wrapping + // the range around the end of the address space + vg_assert(0xFFFFFFFF - di->fpo[i].ulOffStart /* "remaining space" */ + >= di->fpo[i].cbProcSize); } - /* And record min/max */ - vg_assert(min_svma <= max_svma); /* should always hold */ - - di->fpo_minavma = min_svma + bias_for_fpo; - di->fpo_maxavma = max_svma + bias_for_fpo; + /* Dump any entries which point outside the text segment and + compute the min/max avma "hint" addresses. */ + Addr min_avma = ~(Addr)0; + Addr max_avma = (Addr)0; + vg_assert(di->text_present); + j = 0; + for (i = 0; i < di->fpo_size; i++) { + if ((Addr)(di->fpo[i].ulOffStart) >= di->text_avma + && (Addr)(di->fpo[i].ulOffStart + di->fpo[i].cbProcSize) + <= di->text_avma + di->text_size) { + /* Update min/max limits as we go along. */ + if (di->fpo[i].ulOffStart < min_avma) + min_avma = di->fpo[i].ulOffStart; + if (di->fpo[i].ulOffStart + di->fpo[i].cbProcSize - 1 > max_avma) + max_avma = di->fpo[i].ulOffStart + di->fpo[i].cbProcSize - 1; + /* Keep */ + di->fpo[j++] = di->fpo[i]; + if (0) + VG_(printf)("FPO: keep text=[0x%lx,0x%lx) 0x%lx 0x%lx\n", + di->text_avma, di->text_avma + di->text_size, + (Addr)di->fpo[i].ulOffStart, + (Addr)di->fpo[i].ulOffStart + + (Addr)di->fpo[i].cbProcSize - 1); + } else { + if (0) + VG_(printf)("FPO: SKIP text=[0x%lx,0x%lx) 0x%lx 0x%lx\n", + di->text_avma, di->text_avma + di->text_size, + (Addr)di->fpo[i].ulOffStart, + (Addr)di->fpo[i].ulOffStart + + (Addr)di->fpo[i].cbProcSize - 1); + /* out of range; ignore */ + } + } + vg_assert(j >= 0 && j <= di->fpo_size); + di->fpo_size = j; + /* And record min/max */ /* biasing shouldn't cause wraparound (?!) */ - vg_assert(di->fpo_minavma <= di->fpo_maxavma); + if (di->fpo_size > 0) { + vg_assert(min_avma <= max_avma); /* should always hold */ + di->fpo_minavma = min_avma; + di->fpo_maxavma = max_avma; + } else { + di->fpo_minavma = 0; + di->fpo_maxavma = 0; + } if (0) { - VG_(printf)("XXXXXXXXX min/max svma %#lx %#lx\n", - min_svma, max_svma); - VG_(printf)("XXXXXXXXX min/max avma %#lx %#lx\n", + VG_(printf)("FPO: min/max avma %#lx %#lx\n", di->fpo_minavma, di->fpo_maxavma); } n_fpos_read += (ULong)di->fpo_size; } + // END clean up FPO data pdb_convert_types_header( &types, types_image ); switch ( types.version ) { @@ -1946,6 +2088,8 @@ static void pdb_dump( struct pdb_reader* pdb, */ modimage = pdb->read_file( pdb, symbols.gsym_file, &len_modimage ); if (modimage) { + if (debug) + VG_(umsg)("\n"); if (VG_(clo_verbosity) > 1) VG_(message)(Vg_UserMsg, "Reading global symbols\n" ); DEBUG_SnarfCodeView( di, sectp_avma, modimage, 0, len_modimage ); @@ -1985,6 +2129,8 @@ static void pdb_dump( struct pdb_reader* pdb, total_size = pdb_get_file_size(pdb, file_nr); if (symbol_size) { + if (debug) + VG_(umsg)("\n"); if (VG_(clo_verbosity) > 1) VG_(message)(Vg_UserMsg, "Reading symbols for %s\n", file_name ); @@ -1995,6 +2141,8 @@ static void pdb_dump( struct pdb_reader* pdb, } if (lineno_size) { + if (debug) + VG_(umsg)("\n"); if (VG_(clo_verbosity) > 1) VG_(message)(Vg_UserMsg, "Reading lines for %s\n", file_name ); n_lines_read @@ -2033,7 +2181,7 @@ static void pdb_dump( struct pdb_reader* pdb, if ( types_image ) ML_(dinfo_free)( types_image ); if ( pdb->u.jg.toc ) ML_(dinfo_free)( pdb->u.jg.toc ); - if (VG_(clo_verbosity) > 0) { + if (VG_(clo_verbosity) > 1) { VG_(message)(Vg_DebugMsg, " # symbols read = %llu\n", n_syms_read ); VG_(message)(Vg_DebugMsg, @@ -2052,6 +2200,8 @@ static void pdb_dump( struct pdb_reader* pdb, /*--- ---*/ /*------------------------------------------------------------*/ +/* Read line, symbol and unwind information from a PDB file. +*/ Bool ML_(read_pdb_debug_info)( DebugInfo* di, Addr obj_avma, @@ -2281,6 +2431,122 @@ Bool ML_(read_pdb_debug_info)( return True; } +/* Examine a PE file to see if it states the path of an associated PDB + file; if so return that. Caller must deallocate with + ML_(dinfo_free). +*/ + +HChar* ML_(find_name_of_pdb_file)( HChar* pename ) +{ + /* This is a giant kludge, of the kind "you did WTF?!?", but it + works. */ + Bool do_cleanup = False; + HChar tmpname[100], tmpnameroot[50]; + Int fd, r; + HChar* res = NULL; + + if (!pename) + goto out; + + fd = -1; + VG_(memset)(tmpnameroot, 0, sizeof(tmpnameroot)); + VG_(sprintf)(tmpnameroot, "petmp%d", VG_(getpid)()); + VG_(memset)(tmpname, 0, sizeof(tmpname)); + fd = VG_(mkstemp)( tmpnameroot, tmpname ); + if (fd == -1) { + VG_(message)(Vg_UserMsg, + "Find PDB file: Can't create /tmp file %s\n", tmpname); + goto out; + } + do_cleanup = True; + + /* Make up the command to run, essentially: + sh -c "strings (pename) | egrep '\.pdb|\.PDB' > (tmpname)" + */ + HChar* sh = "/bin/sh"; + HChar* strings = "/usr/bin/strings"; + HChar* egrep = "/usr/bin/egrep"; + + /* (sh) -c "(strings) (pename) | (egrep) 'pdb' > (tmpname) */ + Int cmdlen = VG_(strlen)(strings) + VG_(strlen)(pename) + + VG_(strlen)(egrep) + VG_(strlen)(tmpname) + + 100/*misc*/; + HChar* cmd = ML_(dinfo_zalloc)("di.readpe.fnopf.cmd", cmdlen); + vg_assert(cmd); + VG_(sprintf)(cmd, "%s -c \"%s %s | %s '\\.pdb|\\.PDB' >> %s\"", + sh, strings, pename, egrep, tmpname); + vg_assert(cmd[cmdlen-1] == 0); + if (0) VG_(printf)("QQQQQQQQ: %s\n", cmd); + + r = VG_(system)( cmd ); + if (r) { + VG_(message)(Vg_DebugMsg, + "Find PDB file: Command failed:\n %s\n", cmd); + goto out; + } + + /* Find out how big the file is, and get it aboard. */ + struct vg_stat stat_buf; + VG_(memset)(&stat_buf, 0, sizeof(stat_buf)); + + SysRes sr = VG_(stat)(tmpname, &stat_buf); + if (sr_isError(sr)) { + VG_(umsg)("Find PDB file: can't stat %s\n", tmpname); + goto out; + } + + Int szB = (Int)stat_buf.size; + if (szB == 0) { + VG_(umsg)("Find PDB file: %s is empty\n", tmpname); + goto out; + } + /* 6 == strlen("X.pdb\n") */ + if (szB < 6 || szB > 1024/*let's say*/) { + VG_(umsg)("Find PDB file: %s has implausible size %d\n", + tmpname, szB); + goto out; + } + + HChar* pdbname = ML_(dinfo_zalloc)("di.readpe.fnopf.pdbname", szB + 1); + vg_assert(pdbname); + pdbname[szB] = 0; + + Int nread = VG_(read)(fd, pdbname, szB); + if (nread != szB) { + VG_(umsg)("Find PDB file: read of %s failed\n", tmpname); + goto out; + } + vg_assert(pdbname[szB] == 0); + + /* Check we've got something remotely sane -- must have one dot and + one \n in it, and the \n must be at the end */ + Bool saw_dot = False; + Int saw_n_crs = 0; + Int i; + for (i = 0; pdbname[i]; i++) { + if (pdbname[i] == '.') saw_dot = True; + if (pdbname[i] == '\n') saw_n_crs++; + } + if (!saw_dot || saw_n_crs != 1 || pdbname[szB-1] != '\n') { + VG_(umsg)("Find PDB file: can't make sense of: %s\n", pdbname); + goto out; + } + /* Change the \n to a terminating zero, so we have a "normal" string */ + pdbname[szB-1] = 0; + + if (0) VG_(printf)("QQQQQQQQ: got %s\n", pdbname); + + res = pdbname; + goto out; + + out: + if (do_cleanup) { + VG_(close)(fd); + VG_(unlink)( tmpname ); + } + return res; +} + #endif // defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_debuginfo/readstabs.c b/coregrind/m_debuginfo/readstabs.c index c811cf2..c5d7557 100644 --- a/coregrind/m_debuginfo/readstabs.c +++ b/coregrind/m_debuginfo/readstabs.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_debuginfo/readxcoff.c b/coregrind/m_debuginfo/readxcoff.c index 466e423..d0e67f4 100644 --- a/coregrind/m_debuginfo/readxcoff.c +++ b/coregrind/m_debuginfo/readxcoff.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -1521,10 +1521,11 @@ HChar* read_symbol_table ( /* Actually add the symbol (finallyatlast) */ if (sane) { UInt nlen; - dis.addr = addr; - dis.size = size; - dis.tocptr = s->r2known ? s->r2value : 0; - dis.isText = True; + dis.addr = addr; + dis.size = size; + dis.tocptr = s->r2known ? s->r2value : 0; + dis.isText = True; + dis.isIFunc = False; vg_assert(!is_empty_Name(s->name)); nlen = s->name.len; vg_assert(nlen > 0); diff --git a/coregrind/m_debuginfo/storage.c b/coregrind/m_debuginfo/storage.c index 1f6734f..268dfb8 100644 --- a/coregrind/m_debuginfo/storage.c +++ b/coregrind/m_debuginfo/storage.c @@ -9,7 +9,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -126,11 +126,23 @@ void ML_(ppDiCfSI) ( XArray* /* of CfiExpr */ exprs, DiCfSI* si ) VG_(printf)("[%#lx .. %#lx]: ", si->base, si->base + (UWord)si->len - 1); switch (si->cfa_how) { - case CFIC_SPREL: + case CFIC_IA_SPREL: VG_(printf)("let cfa=oldSP+%d", si->cfa_off); break; - case CFIC_FPREL: - VG_(printf)("let cfa=oldFP+%d", si->cfa_off); + case CFIC_IA_BPREL: + VG_(printf)("let cfa=oldBP+%d", si->cfa_off); + break; + case CFIC_ARM_R13REL: + VG_(printf)("let cfa=oldR13+%d", si->cfa_off); + break; + case CFIC_ARM_R12REL: + VG_(printf)("let cfa=oldR12+%d", si->cfa_off); + break; + case CFIC_ARM_R11REL: + VG_(printf)("let cfa=oldR11+%d", si->cfa_off); + break; + case CFIC_ARM_R7REL: + VG_(printf)("let cfa=oldR7+%d", si->cfa_off); break; case CFIC_EXPR: VG_(printf)("let cfa={"); @@ -143,10 +155,26 @@ void ML_(ppDiCfSI) ( XArray* /* of CfiExpr */ exprs, DiCfSI* si ) VG_(printf)(" in RA="); SHOW_HOW(si->ra_how, si->ra_off); +# if defined(VGA_x86) || defined(VGA_amd64) VG_(printf)(" SP="); SHOW_HOW(si->sp_how, si->sp_off); - VG_(printf)(" FP="); - SHOW_HOW(si->fp_how, si->fp_off); + VG_(printf)(" BP="); + SHOW_HOW(si->bp_how, si->bp_off); +# elif defined(VGA_arm) + VG_(printf)(" R14="); + SHOW_HOW(si->r14_how, si->r14_off); + VG_(printf)(" R13="); + SHOW_HOW(si->r13_how, si->r13_off); + VG_(printf)(" R12="); + SHOW_HOW(si->r12_how, si->r12_off); + VG_(printf)(" R11="); + SHOW_HOW(si->r11_how, si->r11_off); + VG_(printf)(" R7="); + SHOW_HOW(si->r7_how, si->r7_off); +# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# else +# error "Unknown arch" +# endif VG_(printf)("\n"); # undef SHOW_HOW } @@ -578,9 +606,13 @@ static void ppCfiOp ( CfiOp op ) static void ppCfiReg ( CfiReg reg ) { switch (reg) { - case Creg_SP: VG_(printf)("SP"); break; - case Creg_FP: VG_(printf)("FP"); break; - case Creg_IP: VG_(printf)("IP"); break; + case Creg_IA_SP: VG_(printf)("xSP"); break; + case Creg_IA_BP: VG_(printf)("xBP"); break; + case Creg_IA_IP: VG_(printf)("xIP"); break; + case Creg_ARM_R13: VG_(printf)("R13"); break; + case Creg_ARM_R12: VG_(printf)("R12"); break; + case Creg_ARM_R15: VG_(printf)("R15"); break; + case Creg_ARM_R14: VG_(printf)("R14"); break; default: vg_assert(0); } } @@ -1218,7 +1250,7 @@ static void canonicaliseSymtab ( struct _DebugInfo* di ) Word i, j, n_merged, n_truncated; Addr s1, s2, e1, e2, p1, p2; UChar *n1, *n2; - Bool t1, t2; + Bool t1, t2, f1, f2; # define SWAP(ty,aa,bb) \ do { ty tt = (aa); (aa) = (bb); (bb) = tt; } while (0) @@ -1282,11 +1314,13 @@ static void canonicaliseSymtab ( struct _DebugInfo* di ) p1 = di->symtab[i].tocptr; n1 = di->symtab[i].name; t1 = di->symtab[i].isText; + f1 = di->symtab[i].isIFunc; s2 = di->symtab[i+1].addr; e2 = s2 + di->symtab[i+1].size - 1; p2 = di->symtab[i+1].tocptr; n2 = di->symtab[i+1].name; t2 = di->symtab[i+1].isText; + f2 = di->symtab[i+1].isIFunc; if (s1 < s2) { e1 = s2-1; } else { @@ -1302,16 +1336,18 @@ static void canonicaliseSymtab ( struct _DebugInfo* di ) up back at cleanup_more, which will take care of it. */ } } - di->symtab[i].addr = s1; - di->symtab[i].size = e1 - s1 + 1; - di->symtab[i].tocptr = p1; - di->symtab[i].name = n1; - di->symtab[i].isText = t1; - di->symtab[i+1].addr = s2; - di->symtab[i+1].size = e2 - s2 + 1; - di->symtab[i+1].tocptr = p2; - di->symtab[i+1].name = n2; - di->symtab[i+1].isText = t2; + di->symtab[i].addr = s1; + di->symtab[i].size = e1 - s1 + 1; + di->symtab[i].tocptr = p1; + di->symtab[i].name = n1; + di->symtab[i].isText = t1; + di->symtab[i].isIFunc = f1; + di->symtab[i+1].addr = s2; + di->symtab[i+1].size = e2 - s2 + 1; + di->symtab[i+1].tocptr = p2; + di->symtab[i+1].name = n2; + di->symtab[i+1].isText = t2; + di->symtab[i+1].isIFunc = f2; vg_assert(s1 <= s2); vg_assert(di->symtab[i].size > 0); vg_assert(di->symtab[i+1].size > 0); @@ -1439,7 +1475,7 @@ static Int compare_DiCfSI ( void* va, void* vb ) return 0; } -static void canonicaliseCFI ( struct _DebugInfo* di ) +void ML_(canonicaliseCFI) ( struct _DebugInfo* di ) { Word i, j; const Addr minAvma = 0; @@ -1532,7 +1568,7 @@ void ML_(canonicaliseTables) ( struct _DebugInfo* di ) { canonicaliseSymtab ( di ); canonicaliseLoctab ( di ); - canonicaliseCFI ( di ); + ML_(canonicaliseCFI) ( di ); canonicaliseVarInfo ( di ); } diff --git a/coregrind/m_debuginfo/tytypes.c b/coregrind/m_debuginfo/tytypes.c index 4e3c9ee..c16813b 100644 --- a/coregrind/m_debuginfo/tytypes.c +++ b/coregrind/m_debuginfo/tytypes.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks LLP + Copyright (C) 2008-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -98,10 +98,15 @@ void ML_(pp_TyEnt)( TyEnt* te ) te->Te.Atom.value, te->Te.Atom.name); break; case Te_Field: - VG_(printf)("Te_Field(ty=0x%05lx,nLoc=%lu,loc=%p,\"%s\")", - te->Te.Field.typeR, te->Te.Field.nLoc, - te->Te.Field.loc, - te->Te.Field.name ? te->Te.Field.name : (UChar*)""); + if (te->Te.Field.nLoc == -1) + VG_(printf)("Te_Field(ty=0x%05lx,pos.offset=%ld,\"%s\")", + te->Te.Field.typeR, te->Te.Field.pos.offset, + te->Te.Field.name ? te->Te.Field.name : (UChar*)""); + else + VG_(printf)("Te_Field(ty=0x%05lx,nLoc=%lu,pos.loc=%p,\"%s\")", + te->Te.Field.typeR, te->Te.Field.nLoc, + te->Te.Field.pos.loc, + te->Te.Field.name ? te->Te.Field.name : (UChar*)""); break; case Te_Bound: VG_(printf)("Te_Bound["); @@ -476,8 +481,11 @@ Word ML_(TyEnt__cmp_by_all_except_cuOff) ( TyEnt* te1, TyEnt* te2 ) if (r != 0) return r; r = UWord__cmp(te1->Te.Field.nLoc, te2->Te.Field.nLoc); if (r != 0) return r; - r = Bytevector__cmp(te1->Te.Field.loc, te2->Te.Field.loc, - te1->Te.Field.nLoc); + if (te1->Te.Field.nLoc == -1) + r = Long__cmp(te1->Te.Field.pos.offset, te2->Te.Field.pos.offset); + else + r = Bytevector__cmp(te1->Te.Field.pos.loc, te2->Te.Field.pos.loc, + te1->Te.Field.nLoc); return r; case Te_Bound: r = Bool__cmp(te1->Te.Bound.knownL, te2->Te.Bound.knownL); @@ -568,7 +576,8 @@ void ML_(TyEnt__make_EMPTY) ( TyEnt* te ) break; case Te_Field: if (te->Te.Field.name) ML_(dinfo_free)(te->Te.Field.name); - if (te->Te.Field.loc) ML_(dinfo_free)(te->Te.Field.loc); + if (te->Te.Field.nLoc > 0 && te->Te.Field.pos.loc) + ML_(dinfo_free)(te->Te.Field.pos.loc); break; case Te_Bound: break; @@ -683,6 +692,8 @@ MaybeULong ML_(sizeOfType)( XArray* /* of TyEnt */ tyents, - bo->Te.Bound.boundL + 1) )); } return eszB; + case Te_TyVoid: + return mk_MaybeULong_Nothing(); /*UNKNOWN*/ default: VG_(printf)("ML_(sizeOfType): unhandled: "); ML_(pp_TyEnt)(ent); @@ -747,26 +758,32 @@ XArray* /*UChar*/ ML_(describe_type)( /*OUT*/PtrdiffT* residual_offset, field = ML_(TyEnts__index_by_cuOff)(tyents, NULL, fieldR); vg_assert(field); vg_assert(field->tag == Te_Field); - vg_assert(field->Te.Field.loc); - vg_assert(field->Te.Field.nLoc > 0); - /* Re data_bias in this call, we should really send in - a legitimate value. But the expression is expected - to be a constant expression, evaluation of which - will not need to use DW_OP_addr and hence we can - avoid the trouble of plumbing the data bias through - to this point (if, indeed, it has any meaning; from - which DebugInfo would we take the data bias? */ - res = ML_(evaluate_Dwarf3_Expr)( - field->Te.Field.loc, field->Te.Field.nLoc, - NULL/*fbGX*/, NULL/*RegSummary*/, - 0/*data_bias*/, - True/*push_initial_zero*/); - if (0) { - VG_(printf)("QQQ "); - ML_(pp_GXResult)(res); - VG_(printf)("\n"); + vg_assert(field->Te.Field.nLoc < 0 + || (field->Te.Field.nLoc > 0 + && field->Te.Field.pos.loc)); + if (field->Te.Field.nLoc == -1) { + res.kind = GXR_Addr; + res.word = field->Te.Field.pos.offset; + } else { + /* Re data_bias in this call, we should really send in + a legitimate value. But the expression is expected + to be a constant expression, evaluation of which + will not need to use DW_OP_addr and hence we can + avoid the trouble of plumbing the data bias through + to this point (if, indeed, it has any meaning; from + which DebugInfo would we take the data bias? */ + res = ML_(evaluate_Dwarf3_Expr)( + field->Te.Field.pos.loc, field->Te.Field.nLoc, + NULL/*fbGX*/, NULL/*RegSummary*/, + 0/*data_bias*/, + True/*push_initial_zero*/); + if (0) { + VG_(printf)("QQQ "); + ML_(pp_GXResult)(res); + VG_(printf)("\n"); + } } - if (res.kind != GXR_Value) + if (res.kind != GXR_Addr) continue; mul = ML_(sizeOfType)( tyents, field->Te.Field.typeR ); if (mul.b != True) diff --git a/coregrind/m_debuglog.c b/coregrind/m_debuglog.c index 5a56ebc..ce06d00 100644 --- a/coregrind/m_debuglog.c +++ b/coregrind/m_debuglog.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -232,6 +232,42 @@ static UInt local_sys_getpid ( void ) return (UInt)__res; } +#elif defined(VGP_arm_linux) + +static UInt local_sys_write_stderr ( HChar* buf, Int n ) +{ + volatile Int block[2]; + block[0] = (Int)buf; + block[1] = n; + __asm__ volatile ( + "mov r0, #2\n\t" /* stderr */ + "ldr r1, [%0]\n\t" /* buf */ + "ldr r2, [%0, #4]\n\t" /* n */ + "mov r7, #"VG_STRINGIFY(__NR_write)"\n\t" + "svc 0x0\n" /* write() */ + "str r0, [%0]\n\t" + : + : "r" (block) + : "r0","r1","r2","r7" + ); + if (block[0] < 0) + block[0] = -1; + return (UInt)block[0]; +} + +static UInt local_sys_getpid ( void ) +{ + UInt __res; + __asm__ volatile ( + "mov r7, #"VG_STRINGIFY(__NR_getpid)"\n" + "svc 0x0\n" /* getpid() */ + "mov %0, r0\n" + : "=r" (__res) + : + : "r0", "r7" ); + return __res; +} + #elif defined(VGP_ppc32_aix5) static UInt local_sys_write_stderr ( HChar* buf, Int n ) @@ -1024,7 +1060,6 @@ static void add_to_buf ( HChar c, void* p ) /* Send a logging message. Nothing is output unless 'level' is <= the current loglevel. */ /* EXPORTED */ -__attribute__((format(__printf__, 3, 4))) void VG_(debugLog) ( Int level, const HChar* modulename, const HChar* format, ... ) { diff --git a/coregrind/m_demangle/demangle.c b/coregrind/m_demangle/demangle.c index 262fcfc..f98a1f2 100644 --- a/coregrind/m_demangle/demangle.c +++ b/coregrind/m_demangle/demangle.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_demangle/vg_libciface.h b/coregrind/m_demangle/vg_libciface.h index a8e9510..285b0a3 100644 --- a/coregrind/m_demangle/vg_libciface.h +++ b/coregrind/m_demangle/vg_libciface.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_dispatch/dispatch-amd64-linux.S b/coregrind/m_dispatch/dispatch-amd64-linux.S index 6f52dbf..b125a57 100644 --- a/coregrind/m_dispatch/dispatch-amd64-linux.S +++ b/coregrind/m_dispatch/dispatch-amd64-linux.S @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_dispatch/dispatch-arm-linux.S b/coregrind/m_dispatch/dispatch-arm-linux.S new file mode 100644 index 0000000..8c92814 --- /dev/null +++ b/coregrind/m_dispatch/dispatch-arm-linux.S @@ -0,0 +1,274 @@ +/*--------------------------------------------------------------------*/ +/*--- The core dispatch loop, for jumping to a code address. ---*/ +/*--- dispatch-arm-linux.S ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2008-2010 Evan Geller + gaze@bea.ms + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#if defined(VGP_arm_linux) + .fpu vfp + +#include "pub_core_basics_asm.h" +#include "pub_core_dispatch_asm.h" +#include "pub_core_transtab_asm.h" +#include "libvex_guest_offsets.h" /* for OFFSET_arm_R* */ + + +/*------------------------------------------------------------*/ +/*--- ---*/ +/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/ +/*--- run all translations except no-redir ones. ---*/ +/*--- ---*/ +/*------------------------------------------------------------*/ + +/*----------------------------------------------------*/ +/*--- Preamble (set everything up) ---*/ +/*----------------------------------------------------*/ + +/* signature: +UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling ); +*/ +.text +.globl VG_(run_innerloop) +VG_(run_innerloop): + push {r0, r1, r4, r5, r6, r7, r8, r9, fp, lr} + + /* set FPSCR to vex-required default value */ + mov r4, #0 + fmxr fpscr, r4 + + /* r0 (hence also [sp,#0]) holds guest_state */ + /* r1 holds do_profiling */ + mov r8, r0 + ldr r0, [r8, #OFFSET_arm_R15T] + + /* fall into main loop (the right one) */ + cmp r1, #0 /* do_profiling */ + beq VG_(run_innerloop__dispatch_unprofiled) + b VG_(run_innerloop__dispatch_profiled) + + +/*----------------------------------------------------*/ +/*--- NO-PROFILING (standard) dispatcher ---*/ +/*----------------------------------------------------*/ + +.global VG_(run_innerloop__dispatch_unprofiled) +VG_(run_innerloop__dispatch_unprofiled): + + /* AT ENTRY: r0 is next guest addr, r8 is possibly + modified guest state ptr */ + + /* Has the guest state pointer been messed with? If yes, exit. */ + ldr r1, [sp, #0] + cmp r8, r1 + bne gsp_changed + + /* save the jump address in the guest state */ + str r0, [r8, #OFFSET_arm_R15T] + + /* Are we out of timeslice? If yes, defer to scheduler. */ + ldr r1, =VG_(dispatch_ctr) + ldr r2, [r1] + subs r2, r2, #1 + str r2, [r1] + beq counter_is_zero + + /* try a fast lookup in the translation cache */ + // r0 = next guest, r1,r2,r3 scratch + ldr r1, =VG_TT_FAST_MASK // r1 = VG_TT_FAST_MASK + and r2, r1, r0, LSR #2 // r2 = entry # + ldr r1, =VG_(tt_fast) // r1 = &tt_fast[0] + add r1, r1, r2, LSL #3 // r1 = &tt_fast[entry#] + ldr r3, [r1, #0] /* .guest */ + ldr r1, [r1, #4] /* .host */ + cmp r0, r3 + bne fast_lookup_failed + // r1: live, next-host r8: live, gsp + // r2: entry # (but not live) + // r0, r3: dead + + /* Found a match. Jump to .host. */ + blx r1 + b VG_(run_innerloop__dispatch_unprofiled) +.ltorg + /*NOTREACHED*/ + +/*----------------------------------------------------*/ +/*--- PROFILING dispatcher (can be much slower) ---*/ +/*----------------------------------------------------*/ + +.global VG_(run_innerloop__dispatch_profiled) +VG_(run_innerloop__dispatch_profiled): + + /* AT ENTRY: r0 is next guest addr, r8 is possibly + modified guest state ptr */ + + /* Has the guest state pointer been messed with? If yes, exit. */ + ldr r1, [sp, #0] + cmp r8, r1 + bne gsp_changed + + /* save the jump address in the guest state */ + str r0, [r8, #OFFSET_arm_R15T] + + /* Are we out of timeslice? If yes, defer to scheduler. */ + ldr r1, =VG_(dispatch_ctr) + ldr r2, [r1] + subs r2, r2, #1 + str r2, [r1] + beq counter_is_zero + + /* try a fast lookup in the translation cache */ + // r0 = next guest, r1,r2,r3 scratch + ldr r1, =VG_TT_FAST_MASK // r1 = VG_TT_FAST_MASK + and r2, r1, r0, LSR #2 // r2 = entry # + ldr r1, =VG_(tt_fast) // r1 = &tt_fast[0] + add r1, r1, r2, LSL #3 // r1 = &tt_fast[entry#] + ldr r3, [r1, #0] /* .guest */ + ldr r1, [r1, #4] /* .host */ + cmp r0, r3 + bne fast_lookup_failed + // r1: live, next-host r8: live, gsp + // r2: entry # (but not live) + // r0, r3: dead + + /* increment bb profile counter */ + ldr r0, =VG_(tt_fastN) // r0 = &tt_fastN[0] + ldr r0, [r0, r2, LSL #2] // r0 = tt_fast[entry #] + ldr r3, [r0] // *r0 ++ + add r3, r3, #1 + str r3, [r0] + + /* Found a match. Jump to .host. */ + blx r1 + b VG_(run_innerloop__dispatch_profiled) + /*NOTREACHED*/ + +/*----------------------------------------------------*/ +/*--- exit points ---*/ +/*----------------------------------------------------*/ + +gsp_changed: + // r0 = next guest addr (R15T), r8 = modified gsp + /* Someone messed with the gsp. Have to + defer to scheduler to resolve this. dispatch ctr + is not yet decremented, so no need to increment. */ + /* R15T is NOT up to date here. First, need to write + r0 back to R15T, but without trashing r8 since + that holds the value we want to return to the scheduler. + Hence use r1 transiently for the guest state pointer. */ + ldr r1, [sp, #0] + str r0, [r1, #OFFSET_arm_R15T] + mov r0, r8 // "return modified gsp" + b run_innerloop_exit + /*NOTREACHED*/ + +counter_is_zero: + /* R15T is up to date here */ + /* Back out increment of the dispatch ctr */ + ldr r1, =VG_(dispatch_ctr) + ldr r2, [r1] + add r2, r2, #1 + str r2, [r1] + mov r0, #VG_TRC_INNER_COUNTERZERO + b run_innerloop_exit + /*NOTREACHED*/ + +fast_lookup_failed: + /* R15T is up to date here */ + /* Back out increment of the dispatch ctr */ + ldr r1, =VG_(dispatch_ctr) + ldr r2, [r1] + add r2, r2, #1 + str r2, [r1] + mov r0, #VG_TRC_INNER_FASTMISS + b run_innerloop_exit + /*NOTREACHED*/ + +/* All exits from the dispatcher go through here. %r0 holds + the return value. +*/ +run_innerloop_exit: + /* We're leaving. Check that nobody messed with + FPSCR in ways we don't expect. */ + fmrx r4, fpscr + bic r4, #0xF8000000 /* mask out NZCV and QC */ + bic r4, #0x0000009F /* mask out IDC,IXC,UFC,OFC,DZC,IOC */ + cmp r4, #0 + bne invariant_violation + b run_innerloop_exit_REALLY + +invariant_violation: + mov r0, #VG_TRC_INVARIANT_FAILED + b run_innerloop_exit_REALLY + +run_innerloop_exit_REALLY: + add sp, sp, #8 + pop {r4, r5, r6, r7, r8, r9, fp, pc} + +.size VG_(run_innerloop), .-VG_(run_innerloop) + + +/*------------------------------------------------------------*/ +/*--- ---*/ +/*--- A special dispatcher, for running no-redir ---*/ +/*--- translations. Just runs the given translation once. ---*/ +/*--- ---*/ +/*------------------------------------------------------------*/ + +/* signature: +void VG_(run_a_noredir_translation) ( UWord* argblock ); +*/ + +/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args + and 2 to carry results: + 0: input: ptr to translation + 1: input: ptr to guest state + 2: output: next guest PC + 3: output: guest state pointer afterwards (== thread return code) +*/ +.global VG_(run_a_noredir_translation) +VG_(run_a_noredir_translation): + push {r0,r1 /* EABI compliance */, r4-r12, lr} + ldr r8, [r0, #4] + mov lr, pc + ldr pc, [r0, #0] + + pop {r1} + str r0, [r1, #8] + str r8, [r1, #12] + pop {r1/*EABI compliance*/,r4-r12, pc} + +.size VG_(run_a_noredir_translation), .-VG_(run_a_noredir_translation) + +/* Let the linker know we don't need an executable stack */ +.section .note.GNU-stack,"",%progbits + +#endif // defined(VGP_arm_linux) + +/*--------------------------------------------------------------------*/ +/*--- end dispatch-arm-linux.S ---*/ +/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_dispatch/dispatch-ppc32-aix5.S b/coregrind/m_dispatch/dispatch-ppc32-aix5.S index b98ef0d..fbe6690 100644 --- a/coregrind/m_dispatch/dispatch-ppc32-aix5.S +++ b/coregrind/m_dispatch/dispatch-ppc32-aix5.S @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_dispatch/dispatch-ppc32-linux.S b/coregrind/m_dispatch/dispatch-ppc32-linux.S index 2eb13ef..c8ba4e8 100644 --- a/coregrind/m_dispatch/dispatch-ppc32-linux.S +++ b/coregrind/m_dispatch/dispatch-ppc32-linux.S @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Cerion Armour-Brown + Copyright (C) 2005-2010 Cerion Armour-Brown This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -30,6 +30,7 @@ #if defined(VGP_ppc32_linux) +#include "config.h" #include "pub_core_basics_asm.h" #include "pub_core_dispatch_asm.h" #include "pub_core_transtab_asm.h" @@ -131,6 +132,7 @@ LafterFP1: cmplwi 5,0 beq LafterVMX1 +#ifdef HAS_ALTIVEC /* VRSAVE save word : 32 bytes */ mfspr 5,256 /* vrsave reg is spr number 256 */ stw 5,244(1) @@ -162,6 +164,8 @@ LafterFP1: stvx 21,5,1 li 5,48 stvx 20,5,1 +#endif + LafterVMX1: /* Save cr */ @@ -218,8 +222,11 @@ LafterFP2: cmplwi 5,0 beq LafterVMX2 +#ifdef HAS_ALTIVEC vspltisw 3,0x0 /* generate zero */ mtvscr 3 +#endif + LafterVMX2: /* make a stack frame for the code we are calling */ @@ -415,6 +422,7 @@ LafterFP8: cmplwi 11,0 beq LafterVMX8 +#ifdef HAS_ALTIVEC /* Check VSCR[NJ] == 1 */ /* first generate 4x 0x00010000 */ vspltisw 4,0x1 /* 4x 0x00000001 */ @@ -426,6 +434,7 @@ LafterFP8: vspltw 7,7,0x3 /* flags-word to all lanes */ vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */ bt 24,invariant_violation /* branch if all_equal */ +#endif LafterVMX8: /* otherwise we're OK */ @@ -502,6 +511,7 @@ LafterFP9: cmplwi 11,0 beq LafterVMX9 +#ifdef HAS_ALTIVEC /* VRSAVE */ lwz 4,244(1) mfspr 4,256 /* VRSAVE reg is spr number 256 */ @@ -531,6 +541,7 @@ LafterFP9: lvx 21,4,1 li 4,48 lvx 20,4,1 +#endif LafterVMX9: /* reset lr & sp */ diff --git a/coregrind/m_dispatch/dispatch-ppc64-aix5.S b/coregrind/m_dispatch/dispatch-ppc64-aix5.S index c829e1e..7938a16 100644 --- a/coregrind/m_dispatch/dispatch-ppc64-aix5.S +++ b/coregrind/m_dispatch/dispatch-ppc64-aix5.S @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_dispatch/dispatch-ppc64-linux.S b/coregrind/m_dispatch/dispatch-ppc64-linux.S index 801a1dd..c75359b 100644 --- a/coregrind/m_dispatch/dispatch-ppc64-linux.S +++ b/coregrind/m_dispatch/dispatch-ppc64-linux.S @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Cerion Armour-Brown + Copyright (C) 2005-2010 Cerion Armour-Brown This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/coregrind/m_dispatch/dispatch-x86-linux.S b/coregrind/m_dispatch/dispatch-x86-linux.S index 506fc0f..774aa8a 100644 --- a/coregrind/m_dispatch/dispatch-x86-linux.S +++ b/coregrind/m_dispatch/dispatch-x86-linux.S @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_errormgr.c b/coregrind/m_errormgr.c index 19353c6..573f427 100644 --- a/coregrind/m_errormgr.c +++ b/coregrind/m_errormgr.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_execontext.c b/coregrind/m_execontext.c index 7f00e4b..fcb45d7 100644 --- a/coregrind/m_execontext.c +++ b/coregrind/m_execontext.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_hashtable.c b/coregrind/m_hashtable.c index 2faba9c..80275f0 100644 --- a/coregrind/m_hashtable.c +++ b/coregrind/m_hashtable.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_initimg/initimg-aix5.c b/coregrind/m_initimg/initimg-aix5.c index f4cc2f6..b1c4dc8 100644 --- a/coregrind/m_initimg/initimg-aix5.c +++ b/coregrind/m_initimg/initimg-aix5.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c index a24799c..ad7dedd 100644 --- a/coregrind/m_initimg/initimg-linux.c +++ b/coregrind/m_initimg/initimg-linux.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -132,6 +132,7 @@ static HChar** setup_client_env ( HChar** origenv, const HChar* toolname) Int v_launcher_len = VG_(strlen)( v_launcher ); Bool ld_preload_done = False; Int vglib_len = VG_(strlen)(VG_(libdir)); + Bool debug = False; HChar** cpp; HChar** ret; @@ -172,9 +173,12 @@ static HChar** setup_client_env ( HChar** origenv, const HChar* toolname) VG_(debugLog)(2, "initimg", " \"%s\"\n", preload_string); /* Count the original size of the env */ + if (debug) VG_(printf)("\n\n"); envc = 0; - for (cpp = origenv; cpp && *cpp; cpp++) + for (cpp = origenv; cpp && *cpp; cpp++) { envc++; + if (debug) VG_(printf)("XXXXXXXXX: BEFORE %s\n", *cpp); + } /* Allocate a new space */ ret = VG_(malloc) ("initimg-linux.sce.3", @@ -182,8 +186,10 @@ static HChar** setup_client_env ( HChar** origenv, const HChar* toolname) vg_assert(ret); /* copy it over */ - for (cpp = ret; *origenv; ) + for (cpp = ret; *origenv; ) { + if (debug) VG_(printf)("XXXXXXXXX: COPY %s\n", *origenv); *cpp++ = *origenv++; + } *cpp = NULL; vg_assert(envc == (cpp - ret)); @@ -202,6 +208,7 @@ static HChar** setup_client_env ( HChar** origenv, const HChar* toolname) ld_preload_done = True; } + if (debug) VG_(printf)("XXXXXXXXX: MASH %s\n", *cpp); } /* Add the missing bits */ @@ -213,6 +220,7 @@ static HChar** setup_client_env ( HChar** origenv, const HChar* toolname) VG_(snprintf)(cp, len, "%s%s", ld_preload, preload_string); ret[envc++] = cp; + if (debug) VG_(printf)("XXXXXXXXX: ADD %s\n", cp); } /* ret[0 .. envc-1] is live now. */ @@ -230,6 +238,10 @@ static HChar** setup_client_env ( HChar** origenv, const HChar* toolname) VG_(free)(preload_string); ret[envc] = NULL; + for (i = 0; i < envc; i++) { + if (debug) VG_(printf)("XXXXXXXXX: FINAL %s\n", ret[i]); + } + return ret; } @@ -250,10 +262,18 @@ static HChar** setup_client_env ( HChar** origenv, const HChar* toolname) #define AT_UCACHEBSIZE 21 #endif /* AT_UCACHEBSIZE */ +#ifndef AT_BASE_PLATFORM +#define AT_BASE_PLATFORM 24 +#endif /* AT_BASE_PLATFORM */ + #ifndef AT_RANDOM #define AT_RANDOM 25 #endif /* AT_RANDOM */ +#ifndef AT_EXECFN +#define AT_EXECFN 31 +#endif /* AT_EXECFN */ + #ifndef AT_SYSINFO #define AT_SYSINFO 32 #endif /* AT_SYSINFO */ @@ -430,10 +450,13 @@ Addr setup_client_stack( void* init_sp, /* now, how big is the auxv? */ auxsize = sizeof(*auxv); /* there's always at least one entry: AT_NULL */ for (cauxv = orig_auxv; cauxv->a_type != AT_NULL; cauxv++) { - if (cauxv->a_type == AT_PLATFORM) + if (cauxv->a_type == AT_PLATFORM || + cauxv->a_type == AT_BASE_PLATFORM) stringsize += VG_(strlen)(cauxv->u.a_ptr) + 1; else if (cauxv->a_type == AT_RANDOM) stringsize += 16; + else if (cauxv->a_type == AT_EXECFN) + stringsize += VG_(strlen)(VG_(args_the_exename)) + 1; auxsize += sizeof(*cauxv); } @@ -597,6 +620,7 @@ Addr setup_client_stack( void* init_sp, # endif for (; orig_auxv->a_type != AT_NULL; auxv++, orig_auxv++) { + const NSegment *ehdrseg; /* copy the entry... */ *auxv = *orig_auxv; @@ -638,6 +662,7 @@ Addr setup_client_stack( void* init_sp, break; case AT_PLATFORM: + case AT_BASE_PLATFORM: /* points to a platform description string */ auxv->u.a_ptr = copy_str(&strtab, orig_auxv->u.a_ptr); break; @@ -647,6 +672,14 @@ Addr setup_client_stack( void* init_sp, break; case AT_HWCAP: +# if defined(VGP_arm_linux) + { Bool has_neon = (auxv->u.a_val & VKI_HWCAP_NEON) > 0; + VG_(debugLog)(2, "initimg", + "ARM has-neon from-auxv: %s\n", + has_neon ? "YES" : "NO"); + VG_(machine_arm_set_has_NEON)( has_neon ); + } +# endif break; case AT_DCACHEBSIZE: @@ -687,12 +720,19 @@ Addr setup_client_stack( void* init_sp, break; case AT_SYSINFO: + /* Trash this, because we don't reproduce it */ + auxv->a_type = AT_IGNORE; + break; + # if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64_linux) case AT_SYSINFO_EHDR: -# endif /* Trash this, because we don't reproduce it */ + ehdrseg = VG_(am_find_nsegment)((Addr)auxv->u.a_ptr); + vg_assert(ehdrseg); + VG_(am_munmap_valgrind)(ehdrseg->start, ehdrseg->end - ehdrseg->start); auxv->a_type = AT_IGNORE; break; +# endif case AT_RANDOM: /* points to 16 random bytes - we need to ensure this is @@ -703,6 +743,11 @@ Addr setup_client_stack( void* init_sp, strtab += 16; break; + case AT_EXECFN: + /* points to the executable filename */ + auxv->u.a_ptr = copy_str(&strtab, VG_(args_the_exename)); + break; + default: /* stomp out anything we don't know about */ VG_(debugLog)(2, "initimg", @@ -979,6 +1024,22 @@ void VG_(ii_finalise_image)( IIFinaliseImageInfo iifii ) arch->vex.guest_GPR2 = iifii.initial_client_TOC; arch->vex.guest_CIA = iifii.initial_client_IP; +# elif defined(VGP_arm_linux) + /* Zero out the initial state, and set up the simulated FPU in a + sane way. */ + LibVEX_GuestARM_initialise(&arch->vex); + + /* Zero out the shadow areas. */ + VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestARMState)); + VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestARMState)); + + arch->vex.guest_R13 = iifii.initial_client_SP; + arch->vex.guest_R15T = iifii.initial_client_IP; + + /* This is just EABI stuff. */ + // FIXME jrs: what's this for? + arch->vex.guest_R1 = iifii.initial_client_SP; + # else # error Unknown platform # endif diff --git a/coregrind/m_initimg/initimg-pathscan.c b/coregrind/m_initimg/initimg-pathscan.c index acde9c9..df47316 100644 --- a/coregrind/m_initimg/initimg-pathscan.c +++ b/coregrind/m_initimg/initimg-pathscan.c @@ -130,7 +130,7 @@ static Bool match_executable(const char *entry) } // Returns NULL if it wasn't found. -HChar* ML_(find_executable) ( HChar* exec ) +HChar* ML_(find_executable) ( const HChar* exec ) { vg_assert(NULL != exec); if (VG_(strchr)(exec, '/')) { diff --git a/coregrind/m_initimg/priv_initimg_pathscan.h b/coregrind/m_initimg/priv_initimg_pathscan.h index 8245ce1..f3169b1 100644 --- a/coregrind/m_initimg/priv_initimg_pathscan.h +++ b/coregrind/m_initimg/priv_initimg_pathscan.h @@ -32,6 +32,6 @@ #ifndef __PRIV_INITIMG_PATHSCAN_H #define __PRIV_INITIMG_PATHSCAN_ -extern HChar* ML_(find_executable) ( HChar* exec ); +extern HChar* ML_(find_executable) ( const HChar* exec ); #endif diff --git a/coregrind/m_libcassert.c b/coregrind/m_libcassert.c index e5842b3..69a7caf 100644 --- a/coregrind/m_libcassert.c +++ b/coregrind/m_libcassert.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -45,51 +45,96 @@ Assertery. ------------------------------------------------------------------ */ -#if defined(VGP_x86_linux) || defined(VGP_x86_darwin) || defined(VGP_x86_freebsd) -# define GET_REAL_PC_SP_AND_FP(pc, sp, fp) \ - asm("call 0f;" \ - "0: popl %0;" \ - "movl %%esp, %1;" \ - "movl %%ebp, %2;" \ - : "=r" (pc),\ - "=r" (sp),\ - "=r" (fp)); -#elif defined(VGP_amd64_linux) || defined(VGP_amd64_darwin) || defined(VGP_amd64_freebsd) -# define GET_REAL_PC_SP_AND_FP(pc, sp, fp) \ - asm("leaq 0(%%rip), %0;" \ - "movq %%rsp, %1;" \ - "movq %%rbp, %2;" \ - : "=r" (pc),\ - "=r" (sp),\ - "=r" (fp)); +#if defined(VGP_x86_linux) || defined(VGP_x86_darwin) || defined(VGP_x86_freebsd) +# define GET_STARTREGS(srP) \ + { UInt eip, esp, ebp; \ + __asm__ __volatile__( \ + "call 0f;" \ + "0: popl %0;" \ + "movl %%esp, %1;" \ + "movl %%ebp, %2;" \ + : "=r" (eip), "=r" (esp), "=r" (ebp) \ + : /* reads none */ \ + : "memory" \ + ); \ + (srP)->r_pc = (ULong)eip; \ + (srP)->r_sp = (ULong)esp; \ + (srP)->misc.X86.r_ebp = ebp; \ + } +#elif defined(VGP_amd64_linux) || defined(VGP_amd64_darwin) || defined(VGP_amd64_freebsd) +# define GET_STARTREGS(srP) \ + { ULong rip, rsp, rbp; \ + __asm__ __volatile__( \ + "leaq 0(%%rip), %0;" \ + "movq %%rsp, %1;" \ + "movq %%rbp, %2;" \ + : "=r" (rip), "=r" (rsp), "=r" (rbp) \ + : /* reads none */ \ + : "memory" \ + ); \ + (srP)->r_pc = rip; \ + (srP)->r_sp = rsp; \ + (srP)->misc.AMD64.r_rbp = rbp; \ + } #elif defined(VGP_ppc32_linux) || defined(VGP_ppc32_aix5) -# define GET_REAL_PC_SP_AND_FP(pc, sp, fp) \ - asm("mflr 0;" /* r0 = lr */ \ - "bl m_libcassert_get_ip;" /* lr = pc */ \ - "m_libcassert_get_ip:\n" \ - "mflr %0;" \ - "mtlr 0;" /* restore lr */ \ - "mr %1,1;" \ - "mr %2,1;" \ - : "=r" (pc), \ - "=r" (sp), \ - "=r" (fp) \ - : /* reads none */ \ - : "r0" /* trashed */ ); +# define GET_STARTREGS(srP) \ + { UInt cia, r1, lr; \ + __asm__ __volatile__( \ + "mflr 0;" /* r0 = lr */ \ + "bl m_libcassert_get_ip;" /* lr = pc */ \ + "m_libcassert_get_ip:\n" \ + "mflr %0;" /* %0 = pc */ \ + "mtlr 0;" /* restore lr */ \ + "mr %1,1;" /* %1 = r1 */ \ + "mr %2,0;" /* %2 = lr */ \ + : "=r" (cia), "=r" (r1), "=r" (lr) \ + : /* reads none */ \ + : "r0" /* trashed */ \ + ); \ + (srP)->r_pc = (ULong)cia; \ + (srP)->r_sp = (ULong)r1; \ + (srP)->misc.PPC32.r_lr = lr; \ + } #elif defined(VGP_ppc64_linux) || defined(VGP_ppc64_aix5) -# define GET_REAL_PC_SP_AND_FP(pc, sp, fp) \ - asm("mflr 0;" /* r0 = lr */ \ - "bl .m_libcassert_get_ip;" /* lr = pc */ \ - ".m_libcassert_get_ip:\n" \ - "mflr %0;" \ - "mtlr 0;" /* restore lr */ \ - "mr %1,1;" \ - "mr %2,1;" \ - : "=r" (pc), \ - "=r" (sp), \ - "=r" (fp) \ - : /* reads none */ \ - : "r0" /* trashed */ ); +# define GET_STARTREGS(srP) \ + { ULong cia, r1, lr; \ + __asm__ __volatile__( \ + "mflr 0;" /* r0 = lr */ \ + "bl .m_libcassert_get_ip;" /* lr = pc */ \ + ".m_libcassert_get_ip:\n" \ + "mflr %0;" /* %0 = pc */ \ + "mtlr 0;" /* restore lr */ \ + "mr %1,1;" /* %1 = r1 */ \ + "mr %2,0;" /* %2 = lr */ \ + : "=r" (cia), "=r" (r1), "=r" (lr) \ + : /* reads none */ \ + : "r0" /* trashed */ \ + ); \ + (srP)->r_pc = cia; \ + (srP)->r_sp = r1; \ + (srP)->misc.PPC64.r_lr = lr; \ + } +#elif defined(VGP_arm_linux) +# define GET_STARTREGS(srP) \ + { UInt block[6]; \ + __asm__ __volatile__( \ + "str r15, [%0, #+0];" \ + "str r14, [%0, #+4];" \ + "str r13, [%0, #+8];" \ + "str r12, [%0, #+12];" \ + "str r11, [%0, #+16];" \ + "str r7, [%0, #+20];" \ + : /* out */ \ + : /* in */ "r"(&block[0]) \ + : /* trash */ "memory" \ + ); \ + (srP)->r_pc = block[0] - 8; \ + (srP)->r_sp = block[1]; \ + (srP)->misc.ARM.r14 = block[2]; \ + (srP)->misc.ARM.r12 = block[3]; \ + (srP)->misc.ARM.r11 = block[4]; \ + (srP)->misc.ARM.r7 = block[5]; \ + } #else # error Unknown platform #endif @@ -129,8 +174,8 @@ void VG_(show_sched_status) ( void ) } __attribute__ ((noreturn)) -static void report_and_quit ( const Char* report, - Addr ip, Addr sp, Addr fp, Addr lr ) +static void report_and_quit ( const Char* report, + UnwindStartRegs* startRegsIN ) { Addr stacktop; Addr ips[BACKTRACE_DEPTH]; @@ -141,8 +186,13 @@ static void report_and_quit ( const Char* report, // If necessary, fake up an ExeContext which is of our actual real CPU // state. Could cause problems if we got the panic/exception within the // execontext/stack dump/symtab code. But it's better than nothing. - if (0 == ip && 0 == sp && 0 == fp) { - GET_REAL_PC_SP_AND_FP(ip, sp, fp); + UnwindStartRegs startRegs; + VG_(memset)(&startRegs, 0, sizeof(startRegs)); + + if (startRegsIN == NULL) { + GET_STARTREGS(&startRegs); + } else { + startRegs = *startRegsIN; } stacktop = tst->os_state.valgrind_stack_init_SP; @@ -153,7 +203,7 @@ static void report_and_quit ( const Char* report, ips, BACKTRACE_DEPTH, NULL/*array to dump SP values in*/, NULL/*array to dump FP values in*/, - ip, sp, fp, lr, sp, stacktop + &startRegs, stacktop ); VG_(clo_xml) = False; VG_(pp_StackTrace) (ips, n_ips); @@ -214,32 +264,32 @@ void VG_(assert_fail) ( Bool isCore, const Char* expr, const Char* file, if (!VG_STREQ(buf, "")) VG_(printf)("%s: %s\n", component, buf ); - report_and_quit(bugs_to, 0,0,0,0); + report_and_quit(bugs_to, NULL); } __attribute__ ((noreturn)) static void panic ( Char* name, Char* report, Char* str, - Addr ip, Addr sp, Addr fp, Addr lr ) + UnwindStartRegs* startRegs ) { if (VG_(clo_xml)) VG_(printf_xml)("\n"); VG_(printf)("\n%s: the 'impossible' happened:\n %s\n", name, str); - report_and_quit(report, ip, sp, fp, lr); + report_and_quit(report, startRegs); } -void VG_(core_panic_at) ( Char* str, Addr ip, Addr sp, Addr fp, Addr lr ) +void VG_(core_panic_at) ( Char* str, UnwindStartRegs* startRegs ) { - panic("valgrind", VG_BUGS_TO, str, ip, sp, fp, lr); + panic("valgrind", VG_BUGS_TO, str, startRegs); } void VG_(core_panic) ( Char* str ) { - VG_(core_panic_at)(str, 0,0,0,0); + VG_(core_panic_at)(str, NULL); } void VG_(tool_panic) ( Char* str ) { - panic(VG_(details).name, VG_(details).bug_reports_to, str, 0,0,0,0); + panic(VG_(details).name, VG_(details).bug_reports_to, str, NULL); } /* Print some helpful-ish text about unimplemented things, and give up. */ diff --git a/coregrind/m_libcbase.c b/coregrind/m_libcbase.c index 3614b92..98ff96b 100644 --- a/coregrind/m_libcbase.c +++ b/coregrind/m_libcbase.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -437,8 +437,8 @@ void* VG_(memmove)(void *dest, const void *src, SizeT sz) } } else if (dest > src) { - for (i = sz - 1; i >= 0; i--) { - ((UChar*)dest)[i] = ((UChar*)src)[i]; + for (i = 0; i < sz; i++) { + ((UChar*)dest)[sz-i-1] = ((UChar*)src)[sz-i-1]; } } return dest; diff --git a/coregrind/m_libcfile.c b/coregrind/m_libcfile.c index ac13599..ca77b61 100644 --- a/coregrind/m_libcfile.c +++ b/coregrind/m_libcfile.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -861,7 +861,7 @@ Int VG_(socket) ( Int domain, Int type, Int protocol ) res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_SOCKET, (UWord)&args); return sr_isError(res) ? -1 : sr_Res(res); -# elif defined(VGP_amd64_linux) || defined(VGO_freebsd) +# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) || defined(VGO_freebsd) SysRes res; res = VG_(do_syscall3)(__NR_socket, domain, type, protocol ); return sr_isError(res) ? -1 : sr_Res(res); @@ -902,7 +902,7 @@ Int my_connect ( Int sockfd, struct vki_sockaddr_in* serv_addr, Int addrlen ) res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_CONNECT, (UWord)&args); return sr_isError(res) ? -1 : sr_Res(res); -# elif defined(VGP_amd64_linux) || defined(VGO_freebsd) +# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) || defined(VGO_freebsd) SysRes res; res = VG_(do_syscall3)(__NR_connect, sockfd, (UWord)serv_addr, addrlen); return sr_isError(res) ? -1 : sr_Res(res); @@ -943,7 +943,7 @@ Int VG_(write_socket)( Int sd, void *msg, Int count ) res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_SEND, (UWord)&args); return sr_isError(res) ? -1 : sr_Res(res); -# elif defined(VGP_amd64_linux) || defined(VGO_freebsd) +# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) || defined(VGO_freebsd) SysRes res; res = VG_(do_syscall6)(__NR_sendto, sd, (UWord)msg, count, VKI_MSG_NOSIGNAL, 0,0); @@ -974,7 +974,7 @@ Int VG_(getsockname) ( Int sd, struct vki_sockaddr *name, Int *namelen) res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_GETSOCKNAME, (UWord)&args); return sr_isError(res) ? -1 : sr_Res(res); -# elif defined(VGP_amd64_linux) || defined(VGO_freebsd) +# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) || defined(VGO_freebsd) SysRes res; res = VG_(do_syscall3)( __NR_getsockname, (UWord)sd, (UWord)name, (UWord)namelen ); @@ -1006,7 +1006,7 @@ Int VG_(getpeername) ( Int sd, struct vki_sockaddr *name, Int *namelen) res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_GETPEERNAME, (UWord)&args); return sr_isError(res) ? -1 : sr_Res(res); -# elif defined(VGP_amd64_linux) || defined(VGO_freebsd) +# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) || defined(VGO_freebsd) SysRes res; res = VG_(do_syscall3)( __NR_getpeername, (UWord)sd, (UWord)name, (UWord)namelen ); @@ -1041,7 +1041,7 @@ Int VG_(getsockopt) ( Int sd, Int level, Int optname, void *optval, res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_GETSOCKOPT, (UWord)&args); return sr_isError(res) ? -1 : sr_Res(res); -# elif defined(VGP_amd64_linux) || defined(VGO_freebsd) +# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) || defined(VGO_freebsd) SysRes res; res = VG_(do_syscall5)( __NR_getsockopt, (UWord)sd, (UWord)level, (UWord)optname, diff --git a/coregrind/m_libcprint.c b/coregrind/m_libcprint.c index 1782417..389fd4c 100644 --- a/coregrind/m_libcprint.c +++ b/coregrind/m_libcprint.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -374,15 +374,13 @@ typedef leftmost column? */ /* Current message kind - changes from call to call */ VgMsgKind kind; - /* PID; acquired just once and stays constant */ - Int my_pid; /* destination */ OutputSink* sink; } vmessage_buf_t; static vmessage_buf_t vmessage_buf - = { "", 0, True, Vg_UserMsg, -1, &VG_(log_output_sink) }; + = { "", 0, True, Vg_UserMsg, &VG_(log_output_sink) }; // Adds a single char to the buffer. We aim to have at least 128 @@ -402,14 +400,6 @@ static void add_to__vmessage_buf ( HChar c, void *p ) HChar ch; Int i, depth; - switch (b->kind) { - case Vg_UserMsg: ch = '='; break; - case Vg_DebugMsg: ch = '-'; break; - case Vg_DebugExtraMsg: ch = '+'; break; - case Vg_ClientMsg: ch = '*'; break; - default: ch = '?'; break; - } - // Print one '>' in front of the messages for each level of // self-hosting being performed. depth = RUNNING_ON_VALGRIND; @@ -419,25 +409,46 @@ static void add_to__vmessage_buf ( HChar c, void *p ) b->buf[b->buf_used++] = '>'; } - b->buf[b->buf_used++] = ch; - b->buf[b->buf_used++] = ch; - - if (VG_(clo_time_stamp)) { - VG_(memset)(tmp, 0, sizeof(tmp)); - VG_(elapsed_wallclock_time)(tmp); + if (Vg_FailMsg == b->kind) { + // "valgrind: " prefix. + b->buf[b->buf_used++] = 'v'; + b->buf[b->buf_used++] = 'a'; + b->buf[b->buf_used++] = 'l'; + b->buf[b->buf_used++] = 'g'; + b->buf[b->buf_used++] = 'r'; + b->buf[b->buf_used++] = 'i'; + b->buf[b->buf_used++] = 'n'; + b->buf[b->buf_used++] = 'd'; + b->buf[b->buf_used++] = ':'; + b->buf[b->buf_used++] = ' '; + } else { + switch (b->kind) { + case Vg_UserMsg: ch = '='; break; + case Vg_DebugMsg: ch = '-'; break; + case Vg_ClientMsg: ch = '*'; break; + default: ch = '?'; break; + } + + b->buf[b->buf_used++] = ch; + b->buf[b->buf_used++] = ch; + + if (VG_(clo_time_stamp)) { + VG_(memset)(tmp, 0, sizeof(tmp)); + VG_(elapsed_wallclock_time)(tmp); + tmp[sizeof(tmp)-1] = 0; + for (i = 0; tmp[i]; i++) + b->buf[b->buf_used++] = tmp[i]; + } + + VG_(sprintf)(tmp, "%d", VG_(getpid)()); tmp[sizeof(tmp)-1] = 0; for (i = 0; tmp[i]; i++) b->buf[b->buf_used++] = tmp[i]; - } - VG_(sprintf)(tmp, "%d", b->my_pid); - tmp[sizeof(tmp)-1] = 0; - for (i = 0; tmp[i]; i++) - b->buf[b->buf_used++] = tmp[i]; - - b->buf[b->buf_used++] = ch; - b->buf[b->buf_used++] = ch; - b->buf[b->buf_used++] = ' '; + b->buf[b->buf_used++] = ch; + b->buf[b->buf_used++] = ch; + b->buf[b->buf_used++] = ' '; + } /* We can't possibly have stuffed 96 chars in merely as a result of making the preamble (can we?) */ @@ -468,13 +479,6 @@ UInt VG_(vmessage) ( VgMsgKind kind, const HChar* format, va_list vargs ) of preamble is emitted at each \n. */ b->kind = kind; - /* Cache the results of getpid just once, so we don't have to call - getpid once for each line of text output. */ - if (UNLIKELY(b->my_pid == -1)) { - b->my_pid = VG_(getpid)(); - vg_assert(b->my_pid >= 0); - } - ret = VG_(debugLog_vprintf) ( add_to__vmessage_buf, b, format, vargs ); @@ -512,33 +516,52 @@ UInt VG_(message) ( VgMsgKind kind, const HChar* format, ... ) return count; } +static void revert_to_stderr ( void ) +{ + VG_(log_output_sink).fd = 2; /* stderr */ + VG_(log_output_sink).is_socket = False; +} + /* VG_(message) variants with hardwired first argument. */ -UInt VG_(umsg) ( const HChar* format, ... ) + +UInt VG_(fmsg) ( const HChar* format, ... ) { UInt count; va_list vargs; va_start(vargs,format); - count = VG_(vmessage) ( Vg_UserMsg, format, vargs ); + count = VG_(vmessage) ( Vg_FailMsg, format, vargs ); va_end(vargs); return count; } -UInt VG_(dmsg) ( const HChar* format, ... ) +void VG_(fmsg_bad_option) ( HChar* opt, const HChar* format, ... ) +{ + va_list vargs; + va_start(vargs,format); + revert_to_stderr(); + VG_(message) (Vg_FailMsg, "Bad option: %s\n", opt); + VG_(vmessage)(Vg_FailMsg, format, vargs ); + VG_(message) (Vg_FailMsg, "Use --help for more information or consult the user manual.\n"); + VG_(exit)(1); + va_end(vargs); +} + +UInt VG_(umsg) ( const HChar* format, ... ) { UInt count; va_list vargs; va_start(vargs,format); - count = VG_(vmessage) ( Vg_DebugMsg, format, vargs ); + count = VG_(vmessage) ( Vg_UserMsg, format, vargs ); va_end(vargs); return count; } -UInt VG_(emsg) ( const HChar* format, ... ) +UInt VG_(dmsg) ( const HChar* format, ... ) { UInt count; va_list vargs; va_start(vargs,format); - count = VG_(vmessage) ( Vg_DebugExtraMsg, format, vargs ); + count = VG_(vmessage) ( Vg_DebugMsg, format, vargs ); va_end(vargs); return count; } @@ -552,6 +575,24 @@ void VG_(message_flush) ( void ) b->buf_used = 0; } +__attribute__((noreturn)) +void VG_(err_missing_prog) ( void ) +{ + revert_to_stderr(); + VG_(fmsg)("no program specified\n"); + VG_(fmsg)("Use --help for more information.\n"); + VG_(exit)(1); +} + +__attribute__((noreturn)) +void VG_(err_config_error) ( Char* msg ) +{ + revert_to_stderr(); + VG_(fmsg)("Startup or configuration error:\n %s\n", msg); + VG_(fmsg)("Unable to start up properly. Giving up.\n"); + VG_(exit)(1); +} + /*--------------------------------------------------------------------*/ /*--- end ---*/ diff --git a/coregrind/m_libcproc.c b/coregrind/m_libcproc.c index 9b3f5e3..0ee8a58 100644 --- a/coregrind/m_libcproc.c +++ b/coregrind/m_libcproc.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -64,6 +64,15 @@ Char** VG_(client_envp) = NULL; /* Path to library directory */ const Char *VG_(libdir) = VG_LIBDIR; +const Char *VG_(LD_PRELOAD_var_name) = +#if defined(VGO_linux) || defined(VGO_aix5) + "LD_PRELOAD"; +#elif defined(VGO_darwin) + "DYLD_INSERT_LIBRARIES"; +#else +# error Unknown OS +#endif + /* We do getenv without libc's help by snooping around in VG_(client_envp) as determined at startup time. */ Char *VG_(getenv)(Char *varname) @@ -182,9 +191,13 @@ static void mash_colon_env(Char *varp, const Char *remove_pattern) entry_start = output+1; /* entry starts after ':' */ } - *output++ = *varp++; + if (*varp) + *output++ = *varp++; } + /* make sure last entry is nul terminated */ + *output = '\0'; + /* match against the last entry */ if (VG_(string_match)(remove_pattern, entry_start)) { output = entry_start; @@ -539,6 +552,7 @@ Int VG_(getgroups)( Int size, UInt* list ) return sr_Res(sres); # elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) || defined(VGO_freebsd) \ + || defined(VGP_arm_linux) \ || defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5) \ || defined(VGO_darwin) SysRes sres; diff --git a/coregrind/m_libcsignal.c b/coregrind/m_libcsignal.c index 80e576e..f9ca598 100644 --- a/coregrind/m_libcsignal.c +++ b/coregrind/m_libcsignal.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index f93ce54..f8448d8 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -45,41 +45,62 @@ #define STACK_PTR(regs) ((regs).vex.VG_STACK_PTR) #define FRAME_PTR(regs) ((regs).vex.VG_FRAME_PTR) -Addr VG_(get_SP) ( ThreadId tid ) -{ +Addr VG_(get_IP) ( ThreadId tid ) { + return INSTR_PTR( VG_(threads)[tid].arch ); +} +Addr VG_(get_SP) ( ThreadId tid ) { return STACK_PTR( VG_(threads)[tid].arch ); } - -Addr VG_(get_IP) ( ThreadId tid ) -{ - return INSTR_PTR( VG_(threads)[tid].arch ); +Addr VG_(get_FP) ( ThreadId tid ) { + return FRAME_PTR( VG_(threads)[tid].arch ); } -Addr VG_(get_FP) ( ThreadId tid ) -{ - return FRAME_PTR( VG_(threads)[tid].arch ); +void VG_(set_IP) ( ThreadId tid, Addr ip ) { + INSTR_PTR( VG_(threads)[tid].arch ) = ip; +} +void VG_(set_SP) ( ThreadId tid, Addr sp ) { + STACK_PTR( VG_(threads)[tid].arch ) = sp; } -Addr VG_(get_LR) ( ThreadId tid ) +void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs, + ThreadId tid ) { -# if defined(VGA_ppc32) || defined(VGA_ppc64) - return VG_(threads)[tid].arch.vex.guest_LR; -# elif defined(VGA_x86) || defined(VGA_amd64) - return 0; +# if defined(VGA_x86) + regs->r_pc = (ULong)VG_(threads)[tid].arch.vex.guest_EIP; + regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_ESP; + regs->misc.X86.r_ebp + = VG_(threads)[tid].arch.vex.guest_EBP; +# elif defined(VGA_amd64) + regs->r_pc = VG_(threads)[tid].arch.vex.guest_RIP; + regs->r_sp = VG_(threads)[tid].arch.vex.guest_RSP; + regs->misc.AMD64.r_rbp + = VG_(threads)[tid].arch.vex.guest_RBP; +# elif defined(VGA_ppc32) + regs->r_pc = (ULong)VG_(threads)[tid].arch.vex.guest_CIA; + regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_GPR1; + regs->misc.PPC32.r_lr + = VG_(threads)[tid].arch.vex.guest_LR; +# elif defined(VGA_ppc64) + regs->r_pc = VG_(threads)[tid].arch.vex.guest_CIA; + regs->r_sp = VG_(threads)[tid].arch.vex.guest_GPR1; + regs->misc.PPC64.r_lr + = VG_(threads)[tid].arch.vex.guest_LR; +# elif defined(VGA_arm) + regs->r_pc = (ULong)VG_(threads)[tid].arch.vex.guest_R15T; + regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_R13; + regs->misc.ARM.r14 + = VG_(threads)[tid].arch.vex.guest_R14; + regs->misc.ARM.r12 + = VG_(threads)[tid].arch.vex.guest_R12; + regs->misc.ARM.r11 + = VG_(threads)[tid].arch.vex.guest_R11; + regs->misc.ARM.r7 + = VG_(threads)[tid].arch.vex.guest_R7; # else # error "Unknown arch" # endif } -void VG_(set_SP) ( ThreadId tid, Addr sp ) -{ - STACK_PTR( VG_(threads)[tid].arch ) = sp; -} - -void VG_(set_IP) ( ThreadId tid, Addr ip ) -{ - INSTR_PTR( VG_(threads)[tid].arch ) = ip; -} void VG_(set_syscall_return_shadows) ( ThreadId tid, /* shadow vals for the result */ @@ -96,6 +117,9 @@ void VG_(set_syscall_return_shadows) ( ThreadId tid, # elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) VG_(threads)[tid].arch.vex_shadow1.guest_GPR3 = s1res; VG_(threads)[tid].arch.vex_shadow2.guest_GPR3 = s2res; +# elif defined(VGP_arm_linux) + VG_(threads)[tid].arch.vex_shadow1.guest_R0 = s1res; + VG_(threads)[tid].arch.vex_shadow2.guest_R0 = s2res; # elif defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5) VG_(threads)[tid].arch.vex_shadow1.guest_GPR3 = s1res; VG_(threads)[tid].arch.vex_shadow2.guest_GPR3 = s2res; @@ -194,7 +218,6 @@ static void apply_to_GPs_of_tid(VexGuestArchState* vex, void (*f)(Addr)) (*f)(vex->guest_R14); (*f)(vex->guest_R15); #elif defined(VGA_ppc32) || defined(VGA_ppc64) - /* XXX ask tool about validity? */ (*f)(vex->guest_GPR0); (*f)(vex->guest_GPR1); (*f)(vex->guest_GPR2); @@ -229,7 +252,21 @@ static void apply_to_GPs_of_tid(VexGuestArchState* vex, void (*f)(Addr)) (*f)(vex->guest_GPR31); (*f)(vex->guest_CTR); (*f)(vex->guest_LR); - +#elif defined(VGA_arm) + (*f)(vex->guest_R0); + (*f)(vex->guest_R1); + (*f)(vex->guest_R2); + (*f)(vex->guest_R3); + (*f)(vex->guest_R4); + (*f)(vex->guest_R5); + (*f)(vex->guest_R6); + (*f)(vex->guest_R8); + (*f)(vex->guest_R9); + (*f)(vex->guest_R10); + (*f)(vex->guest_R11); + (*f)(vex->guest_R12); + (*f)(vex->guest_R13); + (*f)(vex->guest_R14); #else # error Unknown arch #endif @@ -285,6 +322,20 @@ SizeT VG_(thread_get_stack_size)(ThreadId tid) return VG_(threads)[tid].client_stack_szB; } +Addr VG_(thread_get_altstack_min)(ThreadId tid) +{ + vg_assert(0 <= tid && tid < VG_N_THREADS && tid != VG_INVALID_THREADID); + vg_assert(VG_(threads)[tid].status != VgTs_Empty); + return (Addr)VG_(threads)[tid].altstack.ss_sp; +} + +SizeT VG_(thread_get_altstack_size)(ThreadId tid) +{ + vg_assert(0 <= tid && tid < VG_N_THREADS && tid != VG_INVALID_THREADID); + vg_assert(VG_(threads)[tid].status != VgTs_Empty); + return VG_(threads)[tid].altstack.ss_size; +} + //------------------------------------------------------------- /* Details about the capabilities of the underlying (host) CPU. These details are acquired by (1) enquiring with the CPU at startup, or @@ -322,7 +373,7 @@ SizeT VG_(thread_get_stack_size)(ThreadId tid) */ /* --------- State --------- */ -static Bool hwcaps_done = False; +static Bool hwcaps_done = False; /* --- all archs --- */ static VexArch va; @@ -338,18 +389,89 @@ UInt VG_(machine_ppc32_has_VMX) = 0; #if defined(VGA_ppc64) ULong VG_(machine_ppc64_has_VMX) = 0; #endif +#if defined(VGA_arm) +Int VG_(machine_arm_archlevel) = 4; +#endif -/* Determine what insn set and insn set variant the host has, and - record it. To be called once at system startup. Returns False if - this a CPU incapable of running Valgrind. */ - -#if defined(VGA_ppc32) || defined(VGA_ppc64) +/* For hwcaps detection on ppc32/64 and arm we'll need to do SIGILL + testing, so we need a jmp_buf. */ +#if defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm) #include // For jmp_buf static jmp_buf env_unsup_insn; static void handler_unsup_insn ( Int x ) { __builtin_longjmp(env_unsup_insn,1); } #endif + +/* Helper function for VG_(machine_get_hwcaps), assumes the SIGILL/etc + * handlers are installed. Determines the the sizes affected by dcbz + * and dcbzl instructions and updates the given VexArchInfo structure + * accordingly. + * + * Not very defensive: assumes that as long as the dcbz/dcbzl + * instructions don't raise a SIGILL, that they will zero an aligned, + * contiguous block of memory of a sensible size. */ +#if defined(VGA_ppc32) || defined(VGA_ppc64) +static void find_ppc_dcbz_sz(VexArchInfo *arch_info) +{ + Int dcbz_szB = 0; + Int dcbzl_szB; +# define MAX_DCBZL_SZB (128) /* largest known effect of dcbzl */ + char test_block[4*MAX_DCBZL_SZB]; + char *aligned = test_block; + Int i; + + /* round up to next max block size, assumes MAX_DCBZL_SZB is pof2 */ + aligned = (char *)(((HWord)aligned + MAX_DCBZL_SZB) & ~(MAX_DCBZL_SZB - 1)); + vg_assert((aligned + MAX_DCBZL_SZB) <= &test_block[sizeof(test_block)]); + + /* dcbz often clears 32B, although sometimes whatever the native cache + * block size is */ + VG_(memset)(test_block, 0xff, sizeof(test_block)); + __asm__ __volatile__("dcbz 0,%0" + : /*out*/ + : "r" (aligned) /*in*/ + : "memory" /*clobber*/); + for (dcbz_szB = 0, i = 0; i < sizeof(test_block); ++i) { + if (!test_block[i]) + ++dcbz_szB; + } + vg_assert(dcbz_szB == 32 || dcbz_szB == 64 || dcbz_szB == 128); + + /* dcbzl clears 128B on G5/PPC970, and usually 32B on other platforms */ + if (__builtin_setjmp(env_unsup_insn)) { + dcbzl_szB = 0; /* indicates unsupported */ + } + else { + VG_(memset)(test_block, 0xff, sizeof(test_block)); + /* some older assemblers won't understand the dcbzl instruction + * variant, so we directly emit the instruction ourselves */ + __asm__ __volatile__("mr 9, %0 ; .long 0x7C204FEC" /*dcbzl 0,9*/ + : /*out*/ + : "r" (aligned) /*in*/ + : "memory", "r9" /*clobber*/); + for (dcbzl_szB = 0, i = 0; i < sizeof(test_block); ++i) { + if (!test_block[i]) + ++dcbzl_szB; + } + vg_assert(dcbzl_szB == 32 || dcbzl_szB == 64 || dcbzl_szB == 128); + } + + arch_info->ppc_dcbz_szB = dcbz_szB; + arch_info->ppc_dcbzl_szB = dcbzl_szB; + + VG_(debugLog)(1, "machine", "dcbz_szB=%d dcbzl_szB=%d\n", + dcbz_szB, dcbzl_szB); +# undef MAX_DCBZL_SZB +} +#endif /* defined(VGA_ppc32) || defined(VGA_ppc64) */ + + + +/* Determine what insn set and insn set variant the host has, and + record it. To be called once at system startup. Returns False if + this a CPU incapable of running Valgrind. */ + Bool VG_(machine_get_hwcaps)( void ) { vg_assert(hwcaps_done == False); @@ -360,8 +482,10 @@ Bool VG_(machine_get_hwcaps)( void ) LibVEX_default_VexArchInfo(&vai); #if defined(VGA_x86) - { Bool have_sse1, have_sse2, have_cx8; - UInt eax, ebx, ecx, edx; + { Bool have_sse1, have_sse2, have_cx8, have_lzcnt; + UInt eax, ebx, ecx, edx, max_basic, max_extended; + UChar vstr[13]; + vstr[0] = 0; if (!VG_(has_cpuid)()) /* we can't do cpuid at all. Give up. */ @@ -372,6 +496,17 @@ Bool VG_(machine_get_hwcaps)( void ) /* we can't ask for cpuid(x) for x > 0. Give up. */ return False; + /* Get processor ID string, and max basic/extended index + values. */ + max_basic = eax; + VG_(memcpy)(&vstr[0], &ebx, 4); + VG_(memcpy)(&vstr[4], &edx, 4); + VG_(memcpy)(&vstr[8], &ecx, 4); + vstr[12] = 0; + + VG_(cpuid)(0x80000000, &eax, &ebx, &ecx, &edx); + max_extended = eax; + /* get capabilities bits into edx */ VG_(cpuid)(1, &eax, &ebx, &ecx, &edx); @@ -397,12 +532,21 @@ Bool VG_(machine_get_hwcaps)( void ) have_sse2 = 0; VG_(message)(Vg_UserMsg, "Warning: cpu has SSE, but the OS has not enabled it. Disabling in valgrind!"); } - } #endif + /* Figure out if this is an AMD that can do LZCNT. */ + have_lzcnt = False; + if (0 == VG_(strcmp)(vstr, "AuthenticAMD") + && max_extended >= 0x80000001) { + VG_(cpuid)(0x80000001, &eax, &ebx, &ecx, &edx); + have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */ + } + if (have_sse2 && have_sse1) { va = VexArchX86; vai.hwcaps = VEX_HWCAPS_X86_SSE1; vai.hwcaps |= VEX_HWCAPS_X86_SSE2; + if (have_lzcnt) + vai.hwcaps |= VEX_HWCAPS_X86_LZCNT; VG_(machine_x86_have_mxcsr) = 1; return True; } @@ -422,7 +566,10 @@ Bool VG_(machine_get_hwcaps)( void ) #elif defined(VGA_amd64) { Bool have_sse1, have_sse2, have_sse3, have_cx8, have_cx16; - UInt eax, ebx, ecx, edx; + Bool have_lzcnt; + UInt eax, ebx, ecx, edx, max_basic, max_extended; + UChar vstr[13]; + vstr[0] = 0; if (!VG_(has_cpuid)()) /* we can't do cpuid at all. Give up. */ @@ -433,12 +580,26 @@ Bool VG_(machine_get_hwcaps)( void ) /* we can't ask for cpuid(x) for x > 0. Give up. */ return False; + /* Get processor ID string, and max basic/extended index + values. */ + max_basic = eax; + VG_(memcpy)(&vstr[0], &ebx, 4); + VG_(memcpy)(&vstr[4], &edx, 4); + VG_(memcpy)(&vstr[8], &ecx, 4); + vstr[12] = 0; + + VG_(cpuid)(0x80000000, &eax, &ebx, &ecx, &edx); + max_extended = eax; + /* get capabilities bits into edx */ VG_(cpuid)(1, &eax, &ebx, &ecx, &edx); have_sse1 = (edx & (1<<25)) != 0; /* True => have sse insns */ have_sse2 = (edx & (1<<26)) != 0; /* True => have sse2 insns */ have_sse3 = (ecx & (1<<0)) != 0; /* True => have sse3 insns */ + // ssse3 is ecx:9 + // sse41 is ecx:19 + // sse42 is ecx:20 /* cmpxchg8b is a minimum requirement now; if we don't have it we must simply give up. But all CPUs since Pentium-I have it, so @@ -450,9 +611,18 @@ Bool VG_(machine_get_hwcaps)( void ) /* on amd64 we tolerate older cpus, which don't have cmpxchg16b */ have_cx16 = (ecx & (1<<13)) != 0; /* True => have cmpxchg16b */ + /* Figure out if this is an AMD that can do LZCNT. */ + have_lzcnt = False; + if (0 == VG_(strcmp)(vstr, "AuthenticAMD") + && max_extended >= 0x80000001) { + VG_(cpuid)(0x80000001, &eax, &ebx, &ecx, &edx); + have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */ + } + va = VexArchAMD64; vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0) - | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0); + | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0) + | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0); return True; } @@ -547,6 +717,10 @@ Bool VG_(machine_get_hwcaps)( void ) __asm__ __volatile__(".long 0xFC000034"); /* frsqrte 0,0 */ } + /* determine dcbz/dcbzl sizes while we still have the signal + * handlers registered */ + find_ppc_dcbz_sz(&vai); + r = VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL); vg_assert(r == 0); r = VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL); @@ -657,6 +831,10 @@ Bool VG_(machine_get_hwcaps)( void ) __asm__ __volatile__(".long 0xFC000034"); /*frsqrte 0,0*/ } + /* determine dcbz/dcbzl sizes while we still have the signal + * handlers registered */ + find_ppc_dcbz_sz(&vai); + VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL); VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL); VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); @@ -680,6 +858,115 @@ Bool VG_(machine_get_hwcaps)( void ) return True; } +#elif defined(VGA_arm) + { + /* Same instruction set detection algorithm as for ppc32. */ + vki_sigset_t saved_set, tmp_set; + vki_sigaction_fromK_t saved_sigill_act, saved_sigfpe_act; + vki_sigaction_toK_t tmp_sigill_act, tmp_sigfpe_act; + + volatile Bool have_VFP, have_VFP2, have_VFP3, have_NEON; + volatile Int archlevel; + Int r; + + /* This is a kludge. Really we ought to back-convert saved_act + into a toK_t using VG_(convert_sigaction_fromK_to_toK), but + since that's a no-op on all ppc64 platforms so far supported, + it's not worth the typing effort. At least include most basic + sanity check: */ + vg_assert(sizeof(vki_sigaction_fromK_t) == sizeof(vki_sigaction_toK_t)); + + VG_(sigemptyset)(&tmp_set); + VG_(sigaddset)(&tmp_set, VKI_SIGILL); + VG_(sigaddset)(&tmp_set, VKI_SIGFPE); + + r = VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set); + vg_assert(r == 0); + + r = VG_(sigaction)(VKI_SIGILL, NULL, &saved_sigill_act); + vg_assert(r == 0); + tmp_sigill_act = saved_sigill_act; + + VG_(sigaction)(VKI_SIGFPE, NULL, &saved_sigfpe_act); + tmp_sigfpe_act = saved_sigfpe_act; + + /* NODEFER: signal handler does not return (from the kernel's point of + view), hence if it is to successfully catch a signal more than once, + we need the NODEFER flag. */ + tmp_sigill_act.sa_flags &= ~VKI_SA_RESETHAND; + tmp_sigill_act.sa_flags &= ~VKI_SA_SIGINFO; + tmp_sigill_act.sa_flags |= VKI_SA_NODEFER; + tmp_sigill_act.ksa_handler = handler_unsup_insn; + VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL); + + tmp_sigfpe_act.sa_flags &= ~VKI_SA_RESETHAND; + tmp_sigfpe_act.sa_flags &= ~VKI_SA_SIGINFO; + tmp_sigfpe_act.sa_flags |= VKI_SA_NODEFER; + tmp_sigfpe_act.ksa_handler = handler_unsup_insn; + VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL); + + /* VFP insns */ + have_VFP = True; + if (__builtin_setjmp(env_unsup_insn)) { + have_VFP = False; + } else { + __asm__ __volatile__(".word 0xEEB02B42"); /* VMOV.F64 d2, d2 */ + } + /* There are several generation of VFP extension but they differs very + little so for now we will not distinguish them. */ + have_VFP2 = have_VFP; + have_VFP3 = have_VFP; + + /* NEON insns */ + have_NEON = True; + if (__builtin_setjmp(env_unsup_insn)) { + have_NEON = False; + } else { + __asm__ __volatile__(".word 0xF2244154"); /* VMOV q2, q2 */ + } + + /* ARM architecture level */ + archlevel = 5; /* v5 will be base level */ + if (archlevel < 7) { + archlevel = 7; + if (__builtin_setjmp(env_unsup_insn)) { + archlevel = 5; + } else { + __asm__ __volatile__(".word 0xF45FF000"); /* PLI [PC,#-0] */ + } + } + if (archlevel < 6) { + archlevel = 6; + if (__builtin_setjmp(env_unsup_insn)) { + archlevel = 5; + } else { + __asm__ __volatile__(".word 0xE6822012"); /* PKHBT r2, r2, r2 */ + } + } + + VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act); + VG_(convert_sigaction_fromK_to_toK)(&saved_sigfpe_act, &tmp_sigfpe_act); + VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL); + VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL); + VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); + + VG_(debugLog)(1, "machine", "ARMv%d VFP %d VFP2 %d VFP3 %d NEON %d\n", + archlevel, (Int)have_VFP, (Int)have_VFP2, (Int)have_VFP3, + (Int)have_NEON); + + VG_(machine_arm_archlevel) = archlevel; + + va = VexArchARM; + + vai.hwcaps = VEX_ARM_ARCHLEVEL(archlevel); + if (have_VFP3) vai.hwcaps |= VEX_HWCAPS_ARM_VFP3; + if (have_VFP2) vai.hwcaps |= VEX_HWCAPS_ARM_VFP2; + if (have_VFP) vai.hwcaps |= VEX_HWCAPS_ARM_VFP; + if (have_NEON) vai.hwcaps |= VEX_HWCAPS_ARM_NEON; + + return True; + } + #else # error "Unknown arch" #endif @@ -721,6 +1008,22 @@ void VG_(machine_ppc64_set_clszB)( Int szB ) #endif +/* Notify host's ability to handle NEON instructions. */ +#if defined(VGA_arm) +void VG_(machine_arm_set_has_NEON)( Bool has_neon ) +{ + vg_assert(hwcaps_done); + /* There's nothing else we can sanity check. */ + + if (has_neon) { + vai.hwcaps |= VEX_HWCAPS_ARM_NEON; + } else { + vai.hwcaps &= ~VEX_HWCAPS_ARM_NEON; + } +} +#endif + + /* Fetch host cpu info, once established. */ void VG_(machine_get_VexArchInfo)( /*OUT*/VexArch* pVa, /*OUT*/VexArchInfo* pVai ) @@ -735,9 +1038,10 @@ void VG_(machine_get_VexArchInfo)( /*OUT*/VexArch* pVa, // produce a pointer to the actual entry point for the function. void* VG_(fnptr_to_fnentry)( void* f ) { -#if defined(VGP_x86_linux) || defined(VGP_amd64_linux) || \ - defined(VGP_ppc32_linux) || defined(VGO_darwin) || \ - defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) +#if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \ + || defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) \ + || defined(VGP_arm_linux) \ + || defined(VGP_ppc32_linux) || defined(VGO_darwin) return f; #elif defined(VGP_ppc64_linux) || defined(VGP_ppc32_aix5) \ || defined(VGP_ppc64_aix5) diff --git a/coregrind/m_main.c b/coregrind/m_main.c index e862ffd..381c8df 100644 --- a/coregrind/m_main.c +++ b/coregrind/m_main.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -55,6 +55,7 @@ #include "pub_core_debuginfo.h" #include "pub_core_redir.h" #include "pub_core_scheduler.h" +#include "pub_core_seqmatch.h" // For VG_(string_match) #include "pub_core_signals.h" #include "pub_core_stacks.h" // For VG_(register_stack) #include "pub_core_syswrap.h" @@ -121,6 +122,8 @@ static void usage_NORETURN ( Bool debug_help ) " -q --quiet run silently; only print error msgs\n" " -v --verbose be more verbose -- show misc extra info\n" " --trace-children=no|yes Valgrind-ise child processes (follow execve)? [no]\n" +" --trace-children-skip=patt1,patt2,... specifies a list of executables\n" +" that --trace-children=yes should not trace into\n" " --child-silent-after-fork=no|yes omit child output between fork & exec? [no]\n" " --track-fds=no|yes track open file descriptors? [no]\n" " --time-stamp=no|yes add timestamps to log messages? [no]\n" @@ -154,25 +157,34 @@ static void usage_NORETURN ( Bool debug_help ) " --alignment= set minimum alignment of heap allocations [%ld]\n" "\n" " uncommon user options for all Valgrind tools:\n" +" --fullpath-after= (with nothing after the '=')\n" +" show full source paths in call stacks\n" +" --fullpath-after=string like --fullpath-after=, but only show the\n" +" part of the path after 'string'. Allows removal\n" +" of path prefixes. Use this flag multiple times\n" +" to specify a set of prefixes to remove.\n" " --smc-check=none|stack|all checks for self-modifying code: none,\n" " only for code found in stacks, or all [stack]\n" " --read-var-info=yes|no read debug info on stack and global variables\n" " and use it to print better error messages in\n" " tools that make use of it (Memcheck, Helgrind,\n" -" DRD)\n" +" DRD) [no]\n" " --run-libc-freeres=no|yes free up glibc memory at exit on Linux? [yes]\n" " --sim-hints=hint1,hint2,... known hints:\n" " lax-ioctls, enable-outer [none]\n" " --kernel-variant=variant1,variant2,... known variants: bproc [none]\n" " handle non-standard kernel variants\n" " --show-emwarns=no|yes show warnings about emulation limits? [no]\n" +" --require-text-symbol=:sonamepattern:symbolpattern abort run if the\n" +" stated shared object doesn't have the stated\n" +" text symbol. Patterns can contain ? and *.\n" "\n"; Char* usage2 = "\n" " debugging options for all Valgrind tools:\n" -" --stats=no|yes show tool and core statistics [no]\n" " -d show verbose debugging output\n" +" --stats=no|yes show tool and core statistics [no]\n" " --sanity-level= level of sanity checking to do [1]\n" " --trace-flags= show generated code? (X = 0|1) [00000000]\n" " --profile-flags= ditto, but for profiling (X = 0|1) [00000000]\n" @@ -199,6 +211,7 @@ static void usage_NORETURN ( Bool debug_help ) " --vex-iropt-unroll-thresh=<0..400> [120]\n" " --vex-guest-max-insns=<1..100> [50]\n" " --vex-guest-chase-thresh=<0..99> [10]\n" +" --vex-guest-chase-cond=no|yes [no]\n" " --trace-flags and --profile-flags values (omit the middle space):\n" " 1000 0000 show conversion into IR\n" " 0100 0000 show after initial opt\n" @@ -223,8 +236,8 @@ static void usage_NORETURN ( Bool debug_help ) " Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc\n" "\n" " %s is %s\n" -" Valgrind is Copyright (C) 2000-2009, and GNU GPL'd, by Julian Seward et al.\n" -" LibVEX is Copyright (C) 2004-2009, and GNU GPL'd, by OpenWorks LLP.\n" +" Valgrind is Copyright (C) 2000-2010, and GNU GPL'd, by Julian Seward et al.\n" +" LibVEX is Copyright (C) 2004-2010, and GNU GPL'd, by OpenWorks LLP et al.\n" "\n" " Bug reports, feedback, admiration, abuse, etc, to: %s.\n" "\n"; @@ -296,10 +309,10 @@ static void early_process_cmd_line_options ( /*OUT*/Int* need_help, VG_(printf)("valgrind-" VERSION "\n"); VG_(exit)(0); } - else if VG_XACT_CLO(str, "--help", *need_help, 1) {} - else if VG_XACT_CLO(str, "-h", *need_help, 1) {} + else if VG_XACT_CLO(str, "--help", *need_help, *need_help+1) {} + else if VG_XACT_CLO(str, "-h", *need_help, *need_help+1) {} - else if VG_XACT_CLO(str, "--help-debug", *need_help, 2) {} + else if VG_XACT_CLO(str, "--help-debug", *need_help, *need_help+2) {} // The tool has already been determined, but we need to know the name // here. @@ -490,6 +503,8 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, else if VG_BOOL_CLO(arg, "--dsymutil", VG_(clo_dsymutil)) {} + else if VG_STR_CLO (arg, "--trace-children-skip", VG_(clo_trace_children_skip)) {} + else if VG_BINT_CLO(arg, "--vex-iropt-verbosity", VG_(clo_vex_control).iropt_verbosity, 0, 10) {} else if VG_BINT_CLO(arg, "--vex-iropt-level", @@ -502,6 +517,8 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, VG_(clo_vex_control).guest_max_insns, 1, 100) {} else if VG_BINT_CLO(arg, "--vex-guest-chase-thresh", VG_(clo_vex_control).guest_chase_thresh, 0, 99) {} + else if VG_BOOL_CLO(arg, "--vex-guest-chase-cond", + VG_(clo_vex_control).guest_chase_cond) {} else if VG_INT_CLO(arg, "--log-fd", tmp_log_fd) { log_to = VgLogTo_Fd; @@ -531,31 +548,68 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, else if VG_STR_CLO(arg, "--suppressions", tmp_str) { if (VG_(clo_n_suppressions) >= VG_CLO_MAX_SFILES) { - VG_(message)(Vg_UserMsg, "Too many suppression files specified.\n"); - VG_(message)(Vg_UserMsg, - "Increase VG_CLO_MAX_SFILES and recompile.\n"); - VG_(err_bad_option)(arg); + VG_(fmsg_bad_option)(arg, + "Too many suppression files specified.\n" + "Increase VG_CLO_MAX_SFILES and recompile.\n"); } VG_(clo_suppressions)[VG_(clo_n_suppressions)] = tmp_str; VG_(clo_n_suppressions)++; } + else if VG_STR_CLO (arg, "--fullpath-after", tmp_str) { + if (VG_(clo_n_fullpath_after) >= VG_CLO_MAX_FULLPATH_AFTER) { + VG_(fmsg_bad_option)(arg, + "Too many --fullpath-after= specifications.\n" + "Increase VG_CLO_MAX_FULLPATH_AFTER and recompile.\n"); + } + VG_(clo_fullpath_after)[VG_(clo_n_fullpath_after)] = tmp_str; + VG_(clo_n_fullpath_after)++; + } + + else if VG_STR_CLO(arg, "--require-text-symbol", tmp_str) { + if (VG_(clo_n_req_tsyms) >= VG_CLO_MAX_REQ_TSYMS) { + VG_(fmsg_bad_option)(arg, + "Too many --require-text-symbol= specifications.\n" + "Increase VG_CLO_MAX_REQ_TSYMS and recompile.\n"); + } + /* String needs to be of the form C?*C?*, where C is any + character, but is the same both times. Having it in this + form facilitates finding the boundary between the sopatt + and the fnpatt just by looking for the second occurrence + of C, without hardwiring any assumption about what C + is. */ + Char patt[7]; + Bool ok = True; + ok = tmp_str && VG_(strlen)(tmp_str) > 0; + if (ok) { + patt[0] = patt[3] = tmp_str[0]; + patt[1] = patt[4] = '?'; + patt[2] = patt[5] = '*'; + patt[6] = 0; + ok = VG_(string_match)(patt, tmp_str); + } + if (!ok) { + VG_(fmsg_bad_option)(arg, + "Invalid --require-text-symbol= specification.\n"); + } + VG_(clo_req_tsyms)[VG_(clo_n_req_tsyms)] = tmp_str; + VG_(clo_n_req_tsyms)++; + } + /* "stuvwxyz" --> stuvwxyz (binary) */ else if VG_STR_CLO(arg, "--trace-flags", tmp_str) { Int j; if (8 != VG_(strlen)(tmp_str)) { - VG_(message)(Vg_UserMsg, - "--trace-flags argument must have 8 digits\n"); - VG_(err_bad_option)(arg); + VG_(fmsg_bad_option)(arg, + "--trace-flags argument must have 8 digits\n"); } for (j = 0; j < 8; j++) { if ('0' == tmp_str[j]) { /* do nothing */ } else if ('1' == tmp_str[j]) VG_(clo_trace_flags) |= (1 << (7-j)); else { - VG_(message)(Vg_UserMsg, "--trace-flags argument can only " - "contain 0s and 1s\n"); - VG_(err_bad_option)(arg); + VG_(fmsg_bad_option)(arg, + "--trace-flags argument can only contain 0s and 1s\n"); } } } @@ -565,17 +619,15 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, Int j; if (8 != VG_(strlen)(tmp_str)) { - VG_(message)(Vg_UserMsg, - "--profile-flags argument must have 8 digits\n"); - VG_(err_bad_option)(arg); + VG_(fmsg_bad_option)(arg, + "--profile-flags argument must have 8 digits\n"); } for (j = 0; j < 8; j++) { if ('0' == tmp_str[j]) { /* do nothing */ } else if ('1' == tmp_str[j]) VG_(clo_profile_flags) |= (1 << (7-j)); else { - VG_(message)(Vg_UserMsg, "--profile-flags argument can only " - "contain 0s and 1s\n"); - VG_(err_bad_option)(arg); + VG_(fmsg_bad_option)(arg, + "--profile-flags argument can only contain 0s and 1s\n"); } } } @@ -591,7 +643,7 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, else if ( ! VG_(needs).command_line_options || ! VG_TDICT_CALL(tool_process_cmd_line_option, arg) ) { - VG_(err_bad_option)(arg); + VG_(fmsg_bad_option)(arg, ""); } } @@ -614,20 +666,17 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, if (VG_(clo_gen_suppressions) > 0 && !VG_(needs).core_errors && !VG_(needs).tool_errors) { - VG_(message)(Vg_UserMsg, - "Can't use --gen-suppressions= with this tool,\n"); - VG_(message)(Vg_UserMsg, - "as it doesn't generate errors.\n"); - VG_(err_bad_option)("--gen-suppressions="); + VG_(fmsg_bad_option)("--gen-suppressions=yes", + "Can't use --gen-suppressions= with %s\n" + "because it doesn't generate errors.\n", VG_(details).name); } /* If XML output is requested, check that the tool actually supports it. */ if (VG_(clo_xml) && !VG_(needs).xml_output) { VG_(clo_xml) = False; - VG_(message)(Vg_UserMsg, + VG_(fmsg_bad_option)("--xml=yes", "%s does not support XML output.\n", VG_(details).name); - VG_(err_bad_option)("--xml=yes"); /*NOTREACHED*/ } @@ -648,33 +697,28 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, (--gen-suppressions=all is still OK since we don't need any user interaction in this case.) */ if (VG_(clo_gen_suppressions) == 1) { - VG_(umsg)( - "When --xml=yes is specified, only --gen-suppressions=no\n" - "or --gen-suppressions=all are allowed, but not " + VG_(fmsg_bad_option)( + "--xml=yes together with --gen-suppressions=yes", + "When --xml=yes is specified, --gen-suppressions=no\n" + "or --gen-suppressions=all is allowed, but not " "--gen-suppressions=yes.\n"); - /* FIXME: this is really a misuse of VG_(err_bad_option). */ - VG_(err_bad_option)( - "--xml=yes together with --gen-suppressions=yes"); } /* We can't allow DB attaching (or we maybe could, but results could be chaotic ..) since it requires user input. Hence disallow. */ if (VG_(clo_db_attach)) { - VG_(umsg)("--db-attach=yes is not allowed in XML mode,\n" - "as it would require user input.\n"); - /* FIXME: this is really a misuse of VG_(err_bad_option). */ - VG_(err_bad_option)( - "--xml=yes together with --db-attach=yes"); + VG_(fmsg_bad_option)( + "--xml=yes together with --db-attach=yes", + "--db-attach=yes is not allowed with --xml=yes\n" + "because it would require user input.\n"); } /* Disallow dump_error in XML mode; sounds like a recipe for chaos. No big deal; dump_error is a flag for debugging V itself. */ if (VG_(clo_dump_error) > 0) { - /* FIXME: this is really a misuse of VG_(err_bad_option). */ - VG_(err_bad_option)( - "--xml=yes together with --dump-error="); + VG_(fmsg_bad_option)("--xml=yes together with --dump-error", ""); } /* Disable error limits (this might be a bad idea!) */ @@ -732,11 +776,9 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, tmp_log_fd = sr_Res(sres); VG_(clo_log_fname_expanded) = logfilename; } else { - VG_(message)(Vg_UserMsg, - "Can't create log file '%s' (%s); giving up!\n", - logfilename, VG_(strerror)(sr_Err(sres))); - VG_(err_bad_option)( - "--log-file= (didn't work out for some reason.)"); + VG_(fmsg)("can't create log file '%s': %s\n", + logfilename, VG_(strerror)(sr_Err(sres))); + VG_(exit)(1); /*NOTREACHED*/ } break; @@ -747,23 +789,16 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, vg_assert(VG_(strlen)(log_fsname_unexpanded) <= 900); /* paranoia */ tmp_log_fd = VG_(connect_via_socket)( log_fsname_unexpanded ); if (tmp_log_fd == -1) { - VG_(message)(Vg_UserMsg, - "Invalid --log-socket=ipaddr or " - "--log-socket=ipaddr:port spec\n"); - VG_(message)(Vg_UserMsg, - "of '%s'; giving up!\n", log_fsname_unexpanded ); - VG_(err_bad_option)( - "--log-socket="); + VG_(fmsg)("Invalid --log-socket spec of '%s'\n", + log_fsname_unexpanded); + VG_(exit)(1); /*NOTREACHED*/ } if (tmp_log_fd == -2) { - VG_(message)(Vg_UserMsg, - "valgrind: failed to connect to logging server '%s'.\n", - log_fsname_unexpanded ); - VG_(message)(Vg_UserMsg, - "Log messages will sent to stderr instead.\n" ); - VG_(message)(Vg_UserMsg, - "\n" ); + VG_(umsg)("failed to connect to logging server '%s'.\n" + "Log messages will sent to stderr instead.\n", + log_fsname_unexpanded ); + /* We don't change anything here. */ vg_assert(VG_(log_output_sink).fd == 2); tmp_log_fd = 2; @@ -803,11 +838,9 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, *xml_fname_unexpanded = VG_(strdup)( "main.mpclo.2", xml_fsname_unexpanded ); } else { - VG_(message)(Vg_UserMsg, - "Can't create XML file '%s' (%s); giving up!\n", - xmlfilename, VG_(strerror)(sr_Err(sres))); - VG_(err_bad_option)( - "--xml-file= (didn't work out for some reason.)"); + VG_(fmsg)("can't create XML file '%s': %s\n", + xmlfilename, VG_(strerror)(sr_Err(sres))); + VG_(exit)(1); /*NOTREACHED*/ } break; @@ -818,23 +851,15 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, vg_assert(VG_(strlen)(xml_fsname_unexpanded) <= 900); /* paranoia */ tmp_xml_fd = VG_(connect_via_socket)( xml_fsname_unexpanded ); if (tmp_xml_fd == -1) { - VG_(message)(Vg_UserMsg, - "Invalid --xml-socket=ipaddr or " - "--xml-socket=ipaddr:port spec\n"); - VG_(message)(Vg_UserMsg, - "of '%s'; giving up!\n", xml_fsname_unexpanded ); - VG_(err_bad_option)( - "--xml-socket="); + VG_(fmsg)("Invalid --xml-socket spec of '%s'\n", + xml_fsname_unexpanded ); + VG_(exit)(1); /*NOTREACHED*/ } if (tmp_xml_fd == -2) { - VG_(message)(Vg_UserMsg, - "valgrind: failed to connect to XML logging server '%s'.\n", - xml_fsname_unexpanded ); - VG_(message)(Vg_UserMsg, - "XML output will sent to stderr instead.\n" ); - VG_(message)(Vg_UserMsg, - "\n" ); + VG_(umsg)("failed to connect to XML logging server '%s'.\n" + "XML output will sent to stderr instead.\n", + xml_fsname_unexpanded); /* We don't change anything here. */ vg_assert(VG_(xml_output_sink).fd == 2); tmp_xml_fd = 2; @@ -852,13 +877,12 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd, but that is likely to confuse the hell out of users, which is distinctly Ungood. */ if (VG_(clo_xml) && tmp_xml_fd == -1) { - VG_(umsg)( + VG_(fmsg_bad_option)( + "--xml=yes, but no XML destination specified", "--xml=yes has been specified, but there is no XML output\n" "destination. You must specify an XML output destination\n" - "using --xml-fd=, --xml-file= or --xml=socket=.\n" ); - /* FIXME: this is really a misuse of VG_(err_bad_option). */ - VG_(err_bad_option)( - "--xml=yes, but no XML destination specified"); + "using --xml-fd, --xml-file or --xml-socket.\n" + ); } // Finalise the output fds: the log fd .. @@ -971,7 +995,7 @@ static void print_file_vars(Char* format) /*====================================================================*/ // Print the command, escaping any chars that require it. -static void umsg_or_xml_arg(Char* arg, +static void umsg_or_xml_arg(const Char* arg, UInt (*umsg_or_xml)( const HChar*, ... ) ) { SizeT len = VG_(strlen)(arg); @@ -1019,7 +1043,7 @@ static void print_preamble ( Bool logging_to_fd, VG_(printf_xml)("\n"); /* Tool details */ - umsg_or_xml( "%s%s%s%s, %s%s\n", + umsg_or_xml( VG_(clo_xml) ? "%s%t%t%t, %t%s\n" : "%s%s%s%s, %s%s\n", xpre, VG_(details).name, NULL == VG_(details).version ? "" : "-", @@ -1035,7 +1059,8 @@ static void print_preamble ( Bool logging_to_fd, ); } - umsg_or_xml("%s%s%s\n", xpre, VG_(details).copyright_author, xpost); + umsg_or_xml( VG_(clo_xml) ? "%s%t%s\n" : "%s%s%s\n", + xpre, VG_(details).copyright_author, xpost ); /* Core details */ umsg_or_xml( @@ -1088,8 +1113,8 @@ static void print_preamble ( Bool logging_to_fd, VG_(printf_xml_no_f_c)(" %t\n", VG_(name_of_launcher)); else - VG_(printf_xml_no_f_c)(Vg_UserMsg, " %t\n", - "(launcher name unknown)"); + VG_(printf_xml_no_f_c)(" %t\n", + "(launcher name unknown)"); for (i = 0; i < VG_(sizeXA)( VG_(args_for_valgrind) ); i++) { VG_(printf_xml_no_f_c)( " %t\n", @@ -1482,52 +1507,10 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) } # endif - //-------------------------------------------------------------- - // Darwin only: munmap address-space-filling segments - // (oversized pagezero or stack) - // p: none - //-------------------------------------------------------------- - // DDD: comments from Greg Parker why these address-space-filling segments - // are necessary: - // - // The memory maps are there to make sure that Valgrind's copies of libc - // and dyld load in a non-default location, so that the inferior's own - // libc and dyld do load in the default locations. (The kernel performs - // the work of loading several things as described by the executable's - // load commands, including the executable itself, dyld, the main - // thread's stack, and the page-zero segment.) There might be a way to - // fine-tune it so the maps are smaller but still do the job. - // - // The post-launch mmap behavior can be cleaned up - looks like we don't - // unmap as much as we should - which would improve post-launch - // performance. - // - // Hmm, there might be an extra-clever way to give Valgrind a custom - // MH_DYLINKER that performs the "bootloader" work of loading dyld in an - // acceptable place and then unloading itself. Then no mmaps would be - // needed. I'll have to think about that one. - // - // [I can't work out where the address-space-filling segments are - // created in the first place. --njn] - // -#if defined(VGO_darwin) -# if VG_WORDSIZE == 4 - VG_(do_syscall2)(__NR_munmap, 0x00000000, 0xf0000000); -# else - // open up client space - VG_(do_syscall2)(__NR_munmap, 0x100000000, 0x700000000000-0x100000000); - // open up client stack and dyld - VG_(do_syscall2)(__NR_munmap, 0x7fff5c000000, 0x4000000); -# endif -#endif - //-------------------------------------------------------------- // Ensure we're on a plausible stack. // p: logging //-------------------------------------------------------------- -#if defined(VGO_darwin) - // Darwin doesn't use the interim stack. -#else VG_(debugLog)(1, "main", "Checking current stack is plausible\n"); { HChar* limLo = (HChar*)(&VG_(interim_stack).bytes[0]); HChar* limHi = limLo + sizeof(VG_(interim_stack)); @@ -1555,12 +1538,11 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) VG_(debugLog)(0, "main", " Cannot continue. Sorry.\n"); VG_(exit)(1); } -#endif //-------------------------------------------------------------- // Start up the address space manager, and determine the // approximate location of the client's stack - // p: logging, plausible-stack, darwin-munmap + // p: logging, plausible-stack //-------------------------------------------------------------- VG_(debugLog)(1, "main", "Starting the address space manager\n"); vg_assert(VKI_PAGE_SIZE == 4096 || VKI_PAGE_SIZE == 65536); @@ -1807,7 +1789,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) // when it tries to open /proc//cmdline for itself. // p: setup file descriptors //-------------------------------------------------------------- -#if !HAVE_PROC +#if !defined(VGO_linux) // client shouldn't be using /proc! VG_(cl_cmdline_fd) = -1; #else @@ -1815,7 +1797,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) HChar buf[50], buf2[50+64]; HChar nul[1]; Int fd, r; - HChar* exename; + const HChar* exename; VG_(debugLog)(1, "main", "Create fake /proc//cmdline\n"); @@ -1866,7 +1848,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) //-------------------------------------------------------------- VG_(debugLog)(1, "main", "Print help and quit, if requested\n"); if (need_help) { - usage_NORETURN(/*--help-debug?*/2 == need_help); + usage_NORETURN(/*--help-debug?*/need_help >= 2); } //-------------------------------------------------------------- @@ -1952,6 +1934,8 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) iters = 10; # elif defined(VGP_ppc32_linux) iters = 5; +# elif defined(VGP_arm_linux) + iters = 1; # elif defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5) iters = 4; # elif defined(VGO_darwin) @@ -2192,7 +2176,9 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) VG_(deleteXA)( addr2dihandle ); /* Also do the initial stack permissions. */ - { NSegment const* seg + { + SSizeT inaccessible_len; + NSegment const* seg = VG_(am_find_nsegment)( the_iifii.initial_client_SP ); vg_assert(seg); vg_assert(seg->kind == SkAnonC); @@ -2208,12 +2194,13 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) is required (VG_STACK_REDZONE_SZB). setup_client_stack() will have allocated an extra page if a red zone is required, to be on the safe side. */ - vg_assert(the_iifii.initial_client_SP - VG_STACK_REDZONE_SZB - >= seg->start); - VG_TRACK( die_mem_stack, - seg->start, - the_iifii.initial_client_SP - VG_STACK_REDZONE_SZB - - seg->start ); + inaccessible_len = the_iifii.initial_client_SP - VG_STACK_REDZONE_SZB + - seg->start; + vg_assert(inaccessible_len >= 0); + if (inaccessible_len > 0) + VG_TRACK( die_mem_stack, + seg->start, + inaccessible_len ); VG_(debugLog)(2, "main", "mark stack inaccessible %010lx-%010lx\n", seg->start, the_iifii.initial_client_SP-1 - VG_STACK_REDZONE_SZB); @@ -2627,6 +2614,36 @@ void* memset(void *s, int c, SizeT n) { return VG_(memset)(s,c,n); } +/* BVA: abort() for those platforms that need it (PPC and ARM). */ +void abort(void); +void abort(void){ + VG_(printf)("Something called raise().\n"); + vg_assert(0); +} + +/* EAZG: ARM's EABI will call floating point exception handlers in + libgcc which boil down to an abort or raise, that's usually defined + in libc. Instead, define them here. */ +#if defined(VGP_arm_linux) +void raise(void); +void raise(void){ + VG_(printf)("Something called raise().\n"); + vg_assert(0); +} + +void __aeabi_unwind_cpp_pr0(void); +void __aeabi_unwind_cpp_pr0(void){ + VG_(printf)("Something called __aeabi_unwind_cpp_pr0()\n"); + vg_assert(0); +} + +void __aeabi_unwind_cpp_pr1(void); +void __aeabi_unwind_cpp_pr1(void){ + VG_(printf)("Something called __aeabi_unwind_cpp_pr1()\n"); + vg_assert(0); +} +#endif + /* ---------------- Requirement 2 ---------------- */ /* Glibc's sysdeps/i386/elf/start.S has the following gem of a @@ -2760,6 +2777,26 @@ asm("\n" "\tnop\n" "\ttrap\n" ); +#elif defined(VGP_arm_linux) +asm("\n" + "\t.align 2\n" + "\t.global _start\n" + "_start:\n" + "\tldr r0, [pc, #36]\n" + "\tldr r1, [pc, #36]\n" + "\tadd r0, r1, r0\n" + "\tldr r1, [pc, #32]\n" + "\tadd r0, r1, r0\n" + "\tmvn r1, #15\n" + "\tand r0, r0, r1\n" + "\tmov r1, sp\n" + "\tmov sp, r0\n" + "\tmov r0, r1\n" + "\tb _start_in_C_linux\n" + "\t.word vgPlain_interim_stack\n" + "\t.word "VG_STRINGIFY(VG_STACK_GUARD_SZB)"\n" + "\t.word "VG_STRINGIFY(VG_STACK_ACTIVE_SZB)"\n" +); #elif defined(VGP_x86_freebsd) asm("\n" ".text\n" @@ -2991,6 +3028,68 @@ void max_pw_passlen ( void ) { vg_assert(0); } #elif defined(VGO_darwin) +/* + Memory layout established by kernel: + + 0(%esp) argc + 4(%esp) argv[0] + ... + argv[argc-1] + NULL + envp[0] + ... + envp[n] + NULL + executable name (presumably, a pointer to it) + NULL + + Ditto in the 64-bit case, except all offsets from SP are obviously + twice as large. +*/ + +/* The kernel hands control to _start, which extracts the initial + stack pointer and calls onwards to _start_in_C_darwin. This also + switches to the new stack. */ +#if defined(VGP_x86_darwin) +asm("\n" + ".text\n" + ".align 2,0x90\n" + "\t.globl __start\n" + "__start:\n" + /* set up the new stack in %eax */ + "\tmovl $_vgPlain_interim_stack, %eax\n" + "\taddl $"VG_STRINGIFY(VG_STACK_GUARD_SZB)", %eax\n" + "\taddl $"VG_STRINGIFY(VG_STACK_ACTIVE_SZB)", %eax\n" + "\tsubl $16, %eax\n" + "\tandl $~15, %eax\n" + /* install it, and collect the original one */ + "\txchgl %eax, %esp\n" + /* call _start_in_C_darwin, passing it the startup %esp */ + "\tpushl %eax\n" + "\tcall __start_in_C_darwin\n" + "\tint $3\n" + "\tint $3\n" +); +#elif defined(VGP_amd64_darwin) +asm("\n" + ".text\n" + "\t.globl __start\n" + ".align 3,0x90\n" + "__start:\n" + /* set up the new stack in %rdi */ + "\tmovabsq $_vgPlain_interim_stack, %rdi\n" + "\taddq $"VG_STRINGIFY(VG_STACK_GUARD_SZB)", %rdi\n" + "\taddq $"VG_STRINGIFY(VG_STACK_ACTIVE_SZB)", %rdi\n" + "\tandq $~15, %rdi\n" + /* install it, and collect the original one */ + "\txchgq %rdi, %rsp\n" + /* call _start_in_C_darwin, passing it the startup %rsp */ + "\tcall __start_in_C_darwin\n" + "\tint $3\n" + "\tint $3\n" +); +#endif + void* __memcpy_chk(void *dest, const void *src, SizeT n, SizeT n2); void* __memcpy_chk(void *dest, const void *src, SizeT n, SizeT n2) { // skip check @@ -3015,15 +3114,13 @@ void* memset(void *s, int c, SizeT n) { return VG_(memset)(s,c,n); } -/* _start in m_start--darwin.S calls _start_in_C_darwin(). */ - /* Avoid compiler warnings: this fn _is_ used, but labelling it 'static' causes gcc to complain it isn't. */ void _start_in_C_darwin ( UWord* pArgc ); void _start_in_C_darwin ( UWord* pArgc ) { Int r; - Int argc = *(Int *)pArgc; // not pArgc[0] on LP64 + Int argc = *(Int *)pArgc; // not pArgc[0] on LP64 HChar** argv = (HChar**)&pArgc[1]; HChar** envp = (HChar**)&pArgc[1+argc+1]; @@ -3044,6 +3141,330 @@ void _start_in_C_darwin ( UWord* pArgc ) #endif +/*====================================================================*/ +/*=== {u,}{div,mod}di3 replacements ===*/ +/*====================================================================*/ + +/* For static linking on x86-darwin, we need to supply our own 64-bit + integer division code, else the link dies thusly: + + ld_classic: Undefined symbols: + ___udivdi3 + ___umoddi3 +*/ +#if defined(VGP_x86_darwin) + +/* Routines for doing signed/unsigned 64 x 64 ==> 64 div and mod + (udivdi3, umoddi3, divdi3, moddi3) using only 32 x 32 ==> 32 + division. Cobbled together from + + http://www.hackersdelight.org/HDcode/divlu.c + http://www.hackersdelight.org/HDcode/divls.c + http://www.hackersdelight.org/HDcode/newCode/divDouble.c + + The code from those three files is covered by the following license, + as it appears at: + + http://www.hackersdelight.org/permissions.htm + + You are free to use, copy, and distribute any of the code on + this web site, whether modified by you or not. You need not give + attribution. This includes the algorithms (some of which appear + in Hacker's Delight), the Hacker's Assistant, and any code + submitted by readers. Submitters implicitly agree to this. +*/ + +/* Long division, unsigned (64/32 ==> 32). + This procedure performs unsigned "long division" i.e., division of a +64-bit unsigned dividend by a 32-bit unsigned divisor, producing a +32-bit quotient. In the overflow cases (divide by 0, or quotient +exceeds 32 bits), it returns a remainder of 0xFFFFFFFF (an impossible +value). + The dividend is u1 and u0, with u1 being the most significant word. +The divisor is parameter v. The value returned is the quotient. + Max line length is 57, to fit in hacker.book. */ + +static Int nlz32(UInt x) +{ + Int n; + if (x == 0) return(32); + n = 0; + if (x <= 0x0000FFFF) {n = n +16; x = x <<16;} + if (x <= 0x00FFFFFF) {n = n + 8; x = x << 8;} + if (x <= 0x0FFFFFFF) {n = n + 4; x = x << 4;} + if (x <= 0x3FFFFFFF) {n = n + 2; x = x << 2;} + if (x <= 0x7FFFFFFF) {n = n + 1;} + return n; +} + +/* 64 x 32 ==> 32 unsigned division, using only 32 x 32 ==> 32 + division as a primitive. */ +static UInt divlu2(UInt u1, UInt u0, UInt v, UInt *r) +{ + const UInt b = 65536; // Number base (16 bits). + UInt un1, un0, // Norm. dividend LSD's. + vn1, vn0, // Norm. divisor digits. + q1, q0, // Quotient digits. + un32, un21, un10, // Dividend digit pairs. + rhat; // A remainder. + Int s; // Shift amount for norm. + + if (u1 >= v) { // If overflow, set rem. + if (r != NULL) // to an impossible value, + *r = 0xFFFFFFFF; // and return the largest + return 0xFFFFFFFF;} // possible quotient. + + s = nlz32(v); // 0 <= s <= 31. + v = v << s; // Normalize divisor. + vn1 = v >> 16; // Break divisor up into + vn0 = v & 0xFFFF; // two 16-bit digits. + + un32 = (u1 << s) | ((u0 >> (32 - s)) & (-s >> 31)); + un10 = u0 << s; // Shift dividend left. + + un1 = un10 >> 16; // Break right half of + un0 = un10 & 0xFFFF; // dividend into two digits. + + q1 = un32/vn1; // Compute the first + rhat = un32 - q1*vn1; // quotient digit, q1. + again1: + if (q1 >= b || q1*vn0 > b*rhat + un1) { + q1 = q1 - 1; + rhat = rhat + vn1; + if (rhat < b) goto again1;} + + un21 = un32*b + un1 - q1*v; // Multiply and subtract. + + q0 = un21/vn1; // Compute the second + rhat = un21 - q0*vn1; // quotient digit, q0. + again2: + if (q0 >= b || q0*vn0 > b*rhat + un0) { + q0 = q0 - 1; + rhat = rhat + vn1; + if (rhat < b) goto again2;} + + if (r != NULL) // If remainder is wanted, + *r = (un21*b + un0 - q0*v) >> s; // return it. + return q1*b + q0; +} + + +/* 64 x 32 ==> 32 signed division, using only 32 x 32 ==> 32 division + as a primitive. */ +static Int divls(Int u1, UInt u0, Int v, Int *r) +{ + Int q, uneg, vneg, diff, borrow; + + uneg = u1 >> 31; // -1 if u < 0. + if (uneg) { // Compute the absolute + u0 = -u0; // value of the dividend u. + borrow = (u0 != 0); + u1 = -u1 - borrow;} + + vneg = v >> 31; // -1 if v < 0. + v = (v ^ vneg) - vneg; // Absolute value of v. + + if ((UInt)u1 >= (UInt)v) goto overflow; + + q = divlu2(u1, u0, v, (UInt *)r); + + diff = uneg ^ vneg; // Negate q if signs of + q = (q ^ diff) - diff; // u and v differed. + if (uneg && r != NULL) + *r = -*r; + + if ((diff ^ q) < 0 && q != 0) { // If overflow, + overflow: // set remainder + if (r != NULL) // to an impossible value, + *r = 0x80000000; // and return the largest + q = 0x80000000;} // possible neg. quotient. + return q; +} + + + +/* This file contains a program for doing 64/64 ==> 64 division, on a +machine that does not have that instruction but that does have +instructions for "long division" (64/32 ==> 32). Code for unsigned +division is given first, followed by a simple program for doing the +signed version by using the unsigned version. + These programs are useful in implementing "long long" (64-bit) +arithmetic on a machine that has the long division instruction. It will +work on 64- and 32-bit machines, provided the compiler implements long +long's (64-bit integers). It is desirable that the machine have the +Count Leading Zeros instruction. + In the GNU world, these programs are known as __divdi3 and __udivdi3, +and similar names are used here. + This material is not in HD, but may be in a future edition. +Max line length is 57, to fit in hacker.book. */ + + +static Int nlz64(ULong x) +{ + Int n; + if (x == 0) return(64); + n = 0; + if (x <= 0x00000000FFFFFFFFULL) {n = n + 32; x = x << 32;} + if (x <= 0x0000FFFFFFFFFFFFULL) {n = n + 16; x = x << 16;} + if (x <= 0x00FFFFFFFFFFFFFFULL) {n = n + 8; x = x << 8;} + if (x <= 0x0FFFFFFFFFFFFFFFULL) {n = n + 4; x = x << 4;} + if (x <= 0x3FFFFFFFFFFFFFFFULL) {n = n + 2; x = x << 2;} + if (x <= 0x7FFFFFFFFFFFFFFFULL) {n = n + 1;} + return n; +} + +// ---------------------------- udivdi3 -------------------------------- + + /* The variables u0, u1, etc. take on only 32-bit values, but they + are declared long long to avoid some compiler warning messages and to + avoid some unnecessary EXTRs that the compiler would put in, to + convert long longs to ints. + + First the procedure takes care of the case in which the divisor is a + 32-bit quantity. There are two subcases: (1) If the left half of the + dividend is less than the divisor, one execution of DIVU is all that + is required (overflow is not possible). (2) Otherwise it does two + divisions, using the grade school method, with variables used as + suggested below. + + q1 q0 + ________ + v) u1 u0 + q1*v + ____ + k u0 */ + +/* These macros must be used with arguments of the appropriate type +(unsigned long long for DIVU and long long for DIVS. They are +simulations of the presumed machines ops. I.e., they look at only the +low-order 32 bits of the divisor, they return garbage if the division +overflows, and they return garbage in the high-order half of the +quotient doubleword. + In practice, these would be replaced with uses of the machine's DIVU +and DIVS instructions (e.g., by using the GNU "asm" facility). */ + +static UInt DIVU ( ULong u, UInt v ) +{ + UInt uHi = (UInt)(u >> 32); + UInt uLo = (UInt)u; + return divlu2(uHi, uLo, v, NULL); +} + +static Int DIVS ( Long u, Int v ) +{ + Int uHi = (Int)(u >> 32); + UInt uLo = (UInt)u; + return divls(uHi, uLo, v, NULL); +} + +/* 64 x 64 ==> 64 unsigned division, using only 32 x 32 ==> 32 + division as a primitive. */ +static ULong udivdi3(ULong u, ULong v) +{ + ULong u0, u1, v1, q0, q1, k, n; + + if (v >> 32 == 0) { // If v < 2**32: + if (u >> 32 < v) // If u/v cannot overflow, + return DIVU(u, v) // just do one division. + & 0xFFFFFFFF; + else { // If u/v would overflow: + u1 = u >> 32; // Break u up into two + u0 = u & 0xFFFFFFFF; // halves. + q1 = DIVU(u1, v) // First quotient digit. + & 0xFFFFFFFF; + k = u1 - q1*v; // First remainder, < v. + q0 = DIVU((k << 32) + u0, v) // 2nd quot. digit. + & 0xFFFFFFFF; + return (q1 << 32) + q0; + } + } + // Here v >= 2**32. + n = nlz64(v); // 0 <= n <= 31. + v1 = (v << n) >> 32; // Normalize the divisor + // so its MSB is 1. + u1 = u >> 1; // To ensure no overflow. + q1 = DIVU(u1, v1) // Get quotient from + & 0xFFFFFFFF; // divide unsigned insn. + q0 = (q1 << n) >> 31; // Undo normalization and + // division of u by 2. + if (q0 != 0) // Make q0 correct or + q0 = q0 - 1; // too small by 1. + if ((u - q0*v) >= v) + q0 = q0 + 1; // Now q0 is correct. + return q0; +} + + +// ----------------------------- divdi3 -------------------------------- + +/* This routine presumes that smallish cases (those which can be done in +one execution of DIVS) are common. If this is not the case, the test for +this case should be deleted. + Note that the test for when DIVS can be used is not entirely +accurate. For example, DIVS is not used if v = 0xFFFFFFFF8000000, +whereas if could be (if u is sufficiently small in magnitude). */ + +// ------------------------------ cut ---------------------------------- + +static ULong my_llabs ( Long x ) +{ + ULong t = x >> 63; + return (x ^ t) - t; +} + +/* 64 x 64 ==> 64 signed division, using only 32 x 32 ==> 32 division + as a primitive. */ +static Long divdi3(Long u, Long v) +{ + ULong au, av; + Long q, t; + au = my_llabs(u); + av = my_llabs(v); + if (av >> 31 == 0) { // If |v| < 2**31 and + // if (v << 32 >> 32 == v) { // If v is in range and + if (au < av << 31) { // |u|/|v| cannot + q = DIVS(u, v); // overflow, use DIVS. + return (q << 32) >> 32; + } + } + q = udivdi3(au,av); // Invoke udivdi3. + t = (u ^ v) >> 63; // If u, v have different + return (q ^ t) - t; // signs, negate q. +} + +// ---------------------------- end cut -------------------------------- + +ULong __udivdi3 (ULong u, ULong v); +ULong __udivdi3 (ULong u, ULong v) +{ + return udivdi3(u,v); +} + +Long __divdi3 (Long u, Long v); +Long __divdi3 (Long u, Long v) +{ + return divdi3(u,v); +} + +ULong __umoddi3 (ULong u, ULong v); +ULong __umoddi3 (ULong u, ULong v) +{ + ULong q = __udivdi3(u, v); + ULong r = u - q * v; + return r; +} + +Long __moddi3 (Long u, Long v); +Long __moddi3 (Long u, Long v) +{ + Long q = __divdi3(u, v); + Long r = u - q * v; + return r; +} + +#endif + + /*--------------------------------------------------------------------*/ /*--- end ---*/ /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_mallocfree.c b/coregrind/m_mallocfree.c index bad1f7f..dabc39a 100644 --- a/coregrind/m_mallocfree.c +++ b/coregrind/m_mallocfree.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_options.c b/coregrind/m_options.c index 3582818..a347c7d 100644 --- a/coregrind/m_options.c +++ b/coregrind/m_options.c @@ -1,14 +1,13 @@ /*--------------------------------------------------------------------*/ -/*--- Command line options. ---*/ -/*--- m_options.c ---*/ +/*--- Command line options. m_options.c ---*/ /*--------------------------------------------------------------------*/ /* This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -38,6 +37,7 @@ #include "pub_core_libcprint.h" #include "pub_core_libcproc.h" #include "pub_core_mallocfree.h" +#include "pub_core_seqmatch.h" // VG_(string_match) // See pub_{core,tool}_options.h for explanations of all these. @@ -56,6 +56,7 @@ Bool VG_(clo_xml) = False; HChar* VG_(clo_xml_user_comment) = NULL; Bool VG_(clo_demangle) = True; Bool VG_(clo_trace_children) = False; +HChar* VG_(clo_trace_children_skip) = NULL; Bool VG_(clo_child_silent_after_fork) = False; Char* VG_(clo_log_fname_expanded) = NULL; Char* VG_(clo_xml_fname_expanded) = NULL; @@ -63,6 +64,8 @@ Bool VG_(clo_time_stamp) = False; Int VG_(clo_input_fd) = 0; /* stdin */ Int VG_(clo_n_suppressions) = 0; Char* VG_(clo_suppressions)[VG_CLO_MAX_SFILES]; +Int VG_(clo_n_fullpath_after) = 0; +Char* VG_(clo_fullpath_after)[VG_CLO_MAX_FULLPATH_AFTER]; UChar VG_(clo_trace_flags) = 0; // 00000000b UChar VG_(clo_profile_flags) = 0; // 00000000b Int VG_(clo_trace_notbelow) = 999999999; @@ -82,6 +85,9 @@ Int VG_(clo_backtrace_size) = 12; Char* VG_(clo_sim_hints) = NULL; Bool VG_(clo_sym_offsets) = False; Bool VG_(clo_read_var_info) = False; +Int VG_(clo_n_req_tsyms) = 0; +HChar* VG_(clo_req_tsyms)[VG_CLO_MAX_REQ_TSYMS]; +HChar* VG_(clo_require_text_symbol) = NULL; Bool VG_(clo_run_libc_freeres) = True; Bool VG_(clo_track_fds) = False; Bool VG_(clo_show_below_main)= False; @@ -95,42 +101,9 @@ Bool VG_(clo_dsymutil) = False; /*====================================================================*/ -/*=== Command line errors ===*/ +/*=== File expansion ===*/ /*====================================================================*/ -static void revert_to_stderr ( void ) -{ - VG_(log_output_sink).fd = 2; /* stderr */ - VG_(log_output_sink).is_socket = False; -} - -__attribute__((noreturn)) -void VG_(err_bad_option) ( Char* opt ) -{ - revert_to_stderr(); - VG_(printf)("valgrind: Bad option '%s'; aborting.\n", opt); - VG_(printf)("valgrind: Use --help for more information.\n"); - VG_(exit)(1); -} - -__attribute__((noreturn)) -void VG_(err_missing_prog) ( void ) -{ - revert_to_stderr(); - VG_(printf)("valgrind: no program specified\n"); - VG_(printf)("valgrind: Use --help for more information.\n"); - VG_(exit)(1); -} - -__attribute__((noreturn)) -void VG_(err_config_error) ( Char* msg ) -{ - revert_to_stderr(); - VG_(printf)("valgrind: Startup or configuration error:\n %s\n", msg); - VG_(printf)("valgrind: Unable to start up properly. Giving up.\n"); - VG_(exit)(1); -} - // Copies the string, prepending it with the startup working directory, and // expanding %p and %q entries. Returns a new, malloc'd string. Char* VG_(expand_file_name)(Char* option_name, Char* format) @@ -144,7 +117,7 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format) if (VG_STREQ(format, "")) { // Empty name, bad. - VG_(umsg)("%s: filename is empty", option_name); + VG_(fmsg)("%s: filename is empty", option_name); goto bad; } @@ -153,11 +126,13 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format) // that we don't allow a legitimate filename beginning with '~' but that // seems very unlikely. if (format[0] == '~') { - VG_(umsg)("%s: filename begins with '~'\n", option_name); - VG_(umsg)("You probably expected the shell to expand the '~', but it\n"); - VG_(umsg)("didn't. The rules for '~'-expansion " - "vary from shell to shell.\n"); - VG_(umsg)("You might have more luck using $HOME instead.\n"); + VG_(fmsg)( + "%s: filename begins with '~'\n" + "You probably expected the shell to expand the '~', but it\n" + "didn't. The rules for '~'-expansion vary from shell to shell.\n" + "You might have more luck using $HOME instead.\n", + option_name + ); goto bad; } @@ -211,8 +186,7 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format) qualname = &format[i]; while (True) { if (0 == format[i]) { - VG_(message)(Vg_UserMsg, "%s: malformed %%q specifier\n", - option_name); + VG_(fmsg)("%s: malformed %%q specifier\n", option_name); goto bad; } else if ('}' == format[i]) { // Temporarily replace the '}' with NUL to extract var @@ -220,9 +194,8 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format) format[i] = 0; qual = VG_(getenv)(qualname); if (NULL == qual) { - VG_(message)(Vg_UserMsg, - "%s: environment variable %s is not set\n", - option_name, qualname); + VG_(fmsg)("%s: environment variable %s is not set\n", + option_name, qualname); format[i] = '}'; // Put the '}' back. goto bad; } @@ -235,15 +208,14 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format) ENSURE_THIS_MUCH_SPACE(VG_(strlen)(qual)); j += VG_(sprintf)(&out[j], "%s", qual); } else { - VG_(message)(Vg_UserMsg, - "%s: expected '{' after '%%q'\n", option_name); + VG_(fmsg)("%s: expected '{' after '%%q'\n", option_name); goto bad; } } else { // Something else, abort. - VG_(message)(Vg_UserMsg, - "%s: expected 'p' or 'q' or '%%' after '%%'\n", option_name); + VG_(fmsg)("%s: expected 'p' or 'q' or '%%' after '%%'\n", + option_name); goto bad; } } @@ -260,12 +232,75 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format) VG_(strcpy)(opt, option_name); VG_(strcat)(opt, "="); VG_(strcat)(opt, format); - VG_(err_bad_option)(opt); + VG_(fmsg_bad_option)(opt, ""); } } +/*====================================================================*/ +/*=== --trace-children= support ===*/ +/*====================================================================*/ + +static HChar const* consume_commas ( HChar const* c ) { + while (*c && *c == ',') { + ++c; + } + return c; +} + +static HChar const* consume_field ( HChar const* c ) { + while (*c && *c != ',') { + ++c; + } + return c; +} + +/* Should we trace into this child executable (across execve etc) ? + This involves considering --trace-children=, --trace-children-skip= + and the name of the executable. */ +Bool VG_(should_we_trace_this_child) ( HChar* child_exe_name ) +{ + // child_exe_name is pulled out of the guest's space. We + // should be at least marginally cautious with it, lest it + // explode or burst into flames unexpectedly. + if (child_exe_name == NULL || VG_(strlen)(child_exe_name) == 0) + return VG_(clo_trace_children); // we know narfink + + // the main logic + // If --trace-children=no, the answer is simply NO. + if (! VG_(clo_trace_children)) + return False; + + // otherwise, return True, unless the exe name matches any of the + // patterns specified by --trace-children-skip=. + if (VG_(clo_trace_children_skip)) { + HChar const* last = VG_(clo_trace_children_skip); + HChar const* name = (HChar const*)child_exe_name; + while (*last) { + Bool matches; + HChar* patt; + HChar const* first = consume_commas(last); + last = consume_field(first); + if (first == last) + break; + vg_assert(last > first); + /* copy the candidate string into a temporary malloc'd block + so we can use VG_(string_match) on it. */ + patt = VG_(calloc)("m_options.swttc.1", last - first + 1, 1); + VG_(memcpy)(patt, first, last - first); + vg_assert(patt[last-first] == 0); + matches = VG_(string_match)(patt, name); + VG_(free)(patt); + if (matches) + return False; + } + } + + // --trace-children=yes, and this particular executable isn't + // excluded + return True; +} /*--------------------------------------------------------------------*/ -/*--- end m_options.c ---*/ +/*--- end ---*/ /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_oset.c b/coregrind/m_oset.c index 4753418..003a3cf 100644 --- a/coregrind/m_oset.c +++ b/coregrind/m_oset.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c index 5381f99..a22f2d2 100644 --- a/coregrind/m_redir.c +++ b/coregrind/m_redir.c @@ -7,9 +7,9 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org - Copyright (C) 2003-2009 Jeremy Fitzhardinge + Copyright (C) 2003-2010 Jeremy Fitzhardinge jeremy@goop.org This program is free software; you can redistribute it and/or @@ -50,6 +50,8 @@ #include "pub_core_clientstate.h" // VG_(client___libc_freeres_wrapper) #include "pub_core_demangle.h" // VG_(maybe_Z_demangle) +#include "config.h" /* GLIBC_2_* */ + /* This module is a critical part of the redirection/intercept system. It keeps track of the current intercept state, cleans up the @@ -65,13 +67,14 @@ platform-specific. The module is notified of redirection state changes by m_debuginfo. - That calls VG_(redir_notify_new_SegInfo) when a new SegInfo (shared - object symbol table, basically) appears. Appearance of new symbols - can cause new (active) redirections to appear for two reasons: the - symbols in the new table may match existing redirection - specifications (see comments below), and because the symbols in the - new table may themselves supply new redirect specifications which - match existing symbols (or ones in the new table). + That calls VG_(redir_notify_new_DebugInfo) when a new DebugInfo + (shared object symbol table, basically) appears. Appearance of new + symbols can cause new (active) redirections to appear for two + reasons: the symbols in the new table may match existing + redirection specifications (see comments below), and because the + symbols in the new table may themselves supply new redirect + specifications which match existing symbols (or ones in the new + table). Redirect specifications are really symbols with "funny" prefixes (_vgrZU_ and _vgrZZ_). These names tell m_redir that the @@ -84,8 +87,8 @@ by VG_(maybe_Z_demangle). When a shared object is unloaded, this module learns of it via a - call to VG_(redir_notify_delete_SegInfo). It then removes from its - tables all active redirections in any way associated with that + call to VG_(redir_notify_delete_DebugInfo). It then removes from + its tables all active redirections in any way associated with that object, and tidies up the translation caches accordingly. That takes care of tracking the redirection state. When a @@ -166,23 +169,23 @@ =========================================================== Incremental implementation: - When a new SegInfo appears: + When a new DebugInfo appears: - it may be the source of new specs - it may be the source of new matches for existing specs Therefore: - - (new Specs x existing SegInfos): scan all symbols in the new - SegInfo to find new specs. Each of these needs to be compared - against all symbols in all the existing SegInfos to generate + - (new Specs x existing DebugInfos): scan all symbols in the new + DebugInfo to find new specs. Each of these needs to be compared + against all symbols in all the existing DebugInfos to generate new actives. - - (existing Specs x new SegInfo): scan all symbols in the SegInfo, - trying to match them to any existing specs, also generating - new actives. + - (existing Specs x new DebugInfo): scan all symbols in the + DebugInfo, trying to match them to any existing specs, also + generating new actives. - - (new Specs x new SegInfo): scan all symbols in the new SegInfo, - trying to match them against the new specs, to generate new - actives. + - (new Specs x new DebugInfo): scan all symbols in the new + DebugInfo, trying to match them against the new specs, to + generate new actives. - Finally, add new new specs to the current set of specs. @@ -193,7 +196,7 @@ else add (s,d) to Actives and discard (s,1) and (d,1) (maybe overly conservative) - When a SegInfo disappears: + When a DebugInfo disappears: - delete all specs acquired from the seginfo - delete all actives derived from the just-deleted specs - if each active (s,d) deleted, discard (s,1) and (d,1) @@ -232,8 +235,8 @@ typedef } Spec; -/* Top-level data structure. It contains a pointer to a SegInfo and - also a list of the specs harvested from that SegInfo. Note that +/* Top-level data structure. It contains a pointer to a DebugInfo and + also a list of the specs harvested from that DebugInfo. Note that seginfo is allowed to be NULL, meaning that the specs are pre-loaded ones at startup and are not associated with any particular seginfo. */ @@ -247,7 +250,7 @@ typedef TopSpec; /* This is the top level list of redirections. m_debuginfo maintains - a list of SegInfos, and the idea here is to maintain a list with + a list of DebugInfos, and the idea here is to maintain a list with the same number of elements (in fact, with one more element, so as to record abovementioned preloaded specifications.) */ static TopSpec* topSpecs = NULL; @@ -268,12 +271,15 @@ typedef TopSpec* parent_spec; /* the TopSpec which supplied the Spec */ TopSpec* parent_sym; /* the TopSpec which supplied the symbol */ Bool isWrap; /* wrap or replacement? */ + Bool isIFunc; /* indirect function? */ } Active; /* The active set is a fast lookup table */ static OSet* activeSet = NULL; +/* Wrapper routine for indirect functions */ +static Addr iFuncWrapper; /*------------------------------------------------------------*/ /*--- FWDses ---*/ @@ -293,6 +299,7 @@ static void show_active ( HChar* left, Active* act ); static void handle_maybe_load_notifier( const UChar* soname, HChar* symbol, Addr addr ); +static void handle_require_text_symbols ( DebugInfo* ); /*------------------------------------------------------------*/ /*--- NOTIFICATIONS ---*/ @@ -350,8 +357,8 @@ void VG_(redir_notify_new_DebugInfo)( DebugInfo* newsi ) nsyms = VG_(DebugInfo_syms_howmany)( newsi ); for (i = 0; i < nsyms; i++) { - VG_(DebugInfo_syms_getidx)( newsi, i, &sym_addr, &sym_toc, - NULL, &sym_name, &isText ); + VG_(DebugInfo_syms_getidx)( newsi, i, &sym_addr, &sym_toc, + NULL, &sym_name, &isText, NULL ); ok = VG_(maybe_Z_demangle)( sym_name, demangled_sopatt, N_DEMANGLED, demangled_fnpatt, N_DEMANGLED, &isWrap ); /* ignore data symbols */ @@ -388,8 +395,8 @@ void VG_(redir_notify_new_DebugInfo)( DebugInfo* newsi ) if (check_ppcTOCs) { for (i = 0; i < nsyms; i++) { - VG_(DebugInfo_syms_getidx)( newsi, i, &sym_addr, &sym_toc, - NULL, &sym_name, &isText ); + VG_(DebugInfo_syms_getidx)( newsi, i, &sym_addr, &sym_toc, + NULL, &sym_name, &isText, NULL ); ok = isText && VG_(maybe_Z_demangle)( sym_name, demangled_sopatt, N_DEMANGLED, @@ -417,7 +424,7 @@ void VG_(redir_notify_new_DebugInfo)( DebugInfo* newsi ) } } - /* Ok. Now specList holds the list of specs from the DebugInfo. + /* Ok. Now specList holds the list of specs from the DebugInfo. Build a new TopSpec, but don't add it to topSpecs yet. */ newts = dinfo_zalloc("redir.rnnD.4", sizeof(TopSpec)); vg_assert(newts); @@ -466,10 +473,39 @@ void VG_(redir_notify_new_DebugInfo)( DebugInfo* newsi ) if (VG_(clo_trace_redir)) show_redir_state("after VG_(redir_notify_new_DebugInfo)"); + + /* Really finally (quite unrelated to all the above) check the + names in the module against any --require-text-symbol= + specifications we might have. */ + handle_require_text_symbols(newsi); } #undef N_DEMANGLED +/* Add a new target for an indirect function. Adds a new redirection + for the indirection function with address old_from that redirects + the ordinary function with address new_from to the target address + of the original redirection. */ + +void VG_(redir_add_ifunc_target)( Addr old_from, Addr new_from ) +{ + Active *old, new; + + old = VG_(OSetGen_Lookup)(activeSet, &old_from); + vg_assert(old); + vg_assert(old->isIFunc); + + new = *old; + new.from_addr = new_from; + new.isIFunc = False; + maybe_add_active (new); + + if (VG_(clo_trace_redir)) { + VG_(message)( Vg_DebugMsg, + "Adding redirect for indirect function 0x%llx from 0x%llx -> 0x%llx\n", + (ULong)old_from, (ULong)new_from, (ULong)new.to_addr ); + } +} /* Do one element of the basic cross product: add to the active set, all matches resulting from comparing all the given specs against @@ -487,7 +523,7 @@ void generate_and_add_actives ( ) { Spec* sp; - Bool anyMark, isText; + Bool anyMark, isText, isIFunc; Active act; Int nsyms, i; Addr sym_addr; @@ -513,7 +549,7 @@ void generate_and_add_actives ( nsyms = VG_(DebugInfo_syms_howmany)( di ); for (i = 0; i < nsyms; i++) { VG_(DebugInfo_syms_getidx)( di, i, &sym_addr, NULL, NULL, - &sym_name, &isText ); + &sym_name, &isText, &isIFunc ); /* ignore data symbols */ if (!isText) @@ -539,6 +575,7 @@ void generate_and_add_actives ( act.parent_spec = parent_spec; act.parent_sym = parent_sym; act.isWrap = sp->isWrap; + act.isIFunc = isIFunc; sp->done = True; maybe_add_active( act ); } @@ -780,7 +817,11 @@ Addr VG_(redir_do_lookup) ( Addr orig, Bool* isWrap ) vg_assert(r->to_addr != 0); if (isWrap) - *isWrap = r->isWrap; + *isWrap = r->isWrap || r->isIFunc; + if (r->isIFunc) { + vg_assert(iFuncWrapper); + return iFuncWrapper; + } return r->to_addr; } @@ -800,6 +841,7 @@ static void add_hardwired_active ( Addr from, Addr to ) act.parent_spec = NULL; act.parent_sym = NULL; act.isWrap = False; + act.isIFunc = False; maybe_add_active( act ); } @@ -960,6 +1002,28 @@ void VG_(redir_initialise) ( void ) ); } +# elif defined(VGP_arm_linux) + /* If we're using memcheck, use these intercepts right from + the start, otherwise ld.so makes a lot of noise. */ + if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { + add_hardwired_spec( + "ld-linux.so.3", "strlen", + (Addr)&VG_(arm_linux_REDIR_FOR_strlen), + complain_about_stripped_glibc_ldso + ); + //add_hardwired_spec( + // "ld-linux.so.3", "index", + // (Addr)&VG_(arm_linux_REDIR_FOR_index), + // NULL + //); + add_hardwired_spec( + "ld-linux.so.3", "memcpy", + (Addr)&VG_(arm_linux_REDIR_FOR_memcpy), + complain_about_stripped_glibc_ldso + ); + } + /* nothing so far */ + # elif defined(VGP_ppc32_aix5) /* nothing so far */ # elif defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) @@ -968,25 +1032,39 @@ void VG_(redir_initialise) ( void ) # elif defined(VGP_ppc64_aix5) /* nothing so far */ -# elif defined(VGO_darwin) +# elif defined(VGP_x86_darwin) /* If we're using memcheck, use these intercepts right from the start, otherwise dyld makes a lot of noise. */ if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { add_hardwired_spec("dyld", "strcmp", - (Addr)&VG_(darwin_REDIR_FOR_strcmp), NULL); + (Addr)&VG_(x86_darwin_REDIR_FOR_strcmp), NULL); add_hardwired_spec("dyld", "strlen", - (Addr)&VG_(darwin_REDIR_FOR_strlen), NULL); + (Addr)&VG_(x86_darwin_REDIR_FOR_strlen), NULL); add_hardwired_spec("dyld", "strcat", - (Addr)&VG_(darwin_REDIR_FOR_strcat), NULL); + (Addr)&VG_(x86_darwin_REDIR_FOR_strcat), NULL); add_hardwired_spec("dyld", "strcpy", - (Addr)&VG_(darwin_REDIR_FOR_strcpy), NULL); + (Addr)&VG_(x86_darwin_REDIR_FOR_strcpy), NULL); add_hardwired_spec("dyld", "strlcat", - (Addr)&VG_(darwin_REDIR_FOR_strlcat), NULL); -# if defined(VGP_amd64_darwin) + (Addr)&VG_(x86_darwin_REDIR_FOR_strlcat), NULL); + } + +# elif defined(VGP_amd64_darwin) + /* If we're using memcheck, use these intercepts right from + the start, otherwise dyld makes a lot of noise. */ + if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { + add_hardwired_spec("dyld", "strcmp", + (Addr)&VG_(amd64_darwin_REDIR_FOR_strcmp), NULL); + add_hardwired_spec("dyld", "strlen", + (Addr)&VG_(amd64_darwin_REDIR_FOR_strlen), NULL); + add_hardwired_spec("dyld", "strcat", + (Addr)&VG_(amd64_darwin_REDIR_FOR_strcat), NULL); + add_hardwired_spec("dyld", "strcpy", + (Addr)&VG_(amd64_darwin_REDIR_FOR_strcpy), NULL); + add_hardwired_spec("dyld", "strlcat", + (Addr)&VG_(amd64_darwin_REDIR_FOR_strlcat), NULL); // DDD: #warning fixme rdar://6166275 add_hardwired_spec("dyld", "arc4random", - (Addr)&VG_(darwin_REDIR_FOR_arc4random), NULL); -# endif + (Addr)&VG_(amd64_darwin_REDIR_FOR_arc4random), NULL); } # else @@ -1068,6 +1146,7 @@ static Bool is_aix5_glink_idiom ( Addr sym_addr ) return False; } + /*------------------------------------------------------------*/ /*--- NOTIFY-ON-LOAD FUNCTIONS ---*/ /*------------------------------------------------------------*/ @@ -1098,11 +1177,121 @@ void handle_maybe_load_notifier( const UChar* soname, if (VG_(strcmp)(symbol, VG_STRINGIFY(VG_NOTIFY_ON_LOAD(freeres))) == 0) VG_(client___libc_freeres_wrapper) = addr; + else if (VG_(strcmp)(symbol, VG_STRINGIFY(VG_NOTIFY_ON_LOAD(ifunc_wrapper))) == 0) + iFuncWrapper = addr; else vg_assert2(0, "unrecognised load notification function: %s", symbol); } +/*------------------------------------------------------------*/ +/*--- REQUIRE-TEXT-SYMBOL HANDLING ---*/ +/*------------------------------------------------------------*/ + +/* In short: check that the currently-being-loaded object has text + symbols that satisfy any --require-text-symbol= specifications that + apply to it, and abort the run with an error message if not. +*/ +static void handle_require_text_symbols ( DebugInfo* di ) +{ + /* First thing to do is figure out which, if any, + --require-text-symbol specification strings apply to this + object. Most likely none do, since it is not expected to + frequently be used. Work through the list of specs and + accumulate in fnpatts[] the fn patterns that pertain to this + object. */ + HChar* fnpatts[VG_CLO_MAX_REQ_TSYMS]; + Int fnpatts_used = 0; + Int i, j; + const HChar* di_soname = VG_(DebugInfo_get_soname)(di); + vg_assert(di_soname); // must be present + + VG_(memset)(&fnpatts, 0, sizeof(fnpatts)); + + vg_assert(VG_(clo_n_req_tsyms) >= 0); + vg_assert(VG_(clo_n_req_tsyms) <= VG_CLO_MAX_REQ_TSYMS); + for (i = 0; i < VG_(clo_n_req_tsyms); i++) { + HChar* spec = VG_(clo_req_tsyms)[i]; + vg_assert(spec && VG_(strlen)(spec) >= 4); + // clone the spec, so we can stick a zero at the end of the sopatt + spec = VG_(strdup)("m_redir.hrts.1", spec); + HChar sep = spec[0]; + HChar* sopatt = &spec[1]; + HChar* fnpatt = VG_(strchr)(sopatt, sep); + // the initial check at clo processing in time in m_main + // should ensure this. + vg_assert(fnpatt && *fnpatt == sep); + *fnpatt = 0; + fnpatt++; + if (VG_(string_match)(sopatt, di_soname)) + fnpatts[fnpatts_used++] + = VG_(strdup)("m_redir.hrts.2", fnpatt); + VG_(free)(spec); + } + + if (fnpatts_used == 0) + return; /* no applicable spec strings */ + + /* So finally, fnpatts[0 .. fnpatts_used - 1] contains the set of + (patterns for) text symbol names that must be found in this + object, in order to continue. That is, we must find at least + one text symbol name that matches each pattern, else we must + abort the run. */ + + if (0) VG_(printf)("for %s\n", di_soname); + for (i = 0; i < fnpatts_used; i++) + if (0) VG_(printf)(" fnpatt: %s\n", fnpatts[i]); + + /* For each spec, look through the syms to find one that matches. + This isn't terribly efficient but it happens rarely, so no big + deal. */ + for (i = 0; i < fnpatts_used; i++) { + Bool found = False; + HChar* fnpatt = fnpatts[i]; + Int nsyms = VG_(DebugInfo_syms_howmany)(di); + for (j = 0; j < nsyms; j++) { + Bool isText = False; + HChar* sym_name = NULL; + VG_(DebugInfo_syms_getidx)( di, j, NULL, NULL, + NULL, &sym_name, &isText, NULL ); + /* ignore data symbols */ + if (0) VG_(printf)("QQQ %s\n", sym_name); + vg_assert(sym_name); + if (!isText) + continue; + if (VG_(string_match)(fnpatt, sym_name)) { + found = True; + break; + } + } + + if (!found) { + HChar* v = "valgrind: "; + VG_(printf)("\n"); + VG_(printf)( + "%sFatal error at when loading library with soname\n", v); + VG_(printf)( + "%s %s\n", v, di_soname); + VG_(printf)( + "%sCannot find any text symbol with a name " + "that matches the pattern\n", v); + VG_(printf)("%s %s\n", v, fnpatt); + VG_(printf)("%sas required by a --require-text-symbol= " + "specification.\n", v); + VG_(printf)("\n"); + VG_(printf)( + "%sCannot continue -- exiting now.\n", v); + VG_(printf)("\n"); + VG_(exit)(1); + } + } + + /* All required specs were found. Just free memory and return. */ + for (i = 0; i < fnpatts_used; i++) + VG_(free)(fnpatts[i]); +} + + /*------------------------------------------------------------*/ /*--- SANITY/DEBUG ---*/ /*------------------------------------------------------------*/ diff --git a/coregrind/m_replacemalloc/replacemalloc_core.c b/coregrind/m_replacemalloc/replacemalloc_core.c index a7f620d..c861fde 100644 --- a/coregrind/m_replacemalloc/replacemalloc_core.c +++ b/coregrind/m_replacemalloc/replacemalloc_core.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -58,12 +58,9 @@ Bool VG_(replacement_malloc_process_cmd_line_option)(Char* arg) VG_(clo_alignment) > 4096 || VG_(log2)( VG_(clo_alignment) ) == -1 /* not a power of 2 */) { - VG_(message)(Vg_UserMsg, - "Invalid --alignment= setting. " - "Should be a power of 2, >= %d, <= 4096.\n", - VG_MIN_MALLOC_SZB - ); - VG_(err_bad_option)("--alignment"); + VG_(fmsg_bad_option)(arg, + "Alignment must be a power of 2 in the range %d..4096.\n", + VG_MIN_MALLOC_SZB); } } diff --git a/coregrind/m_replacemalloc/vg_replace_malloc.c b/coregrind/m_replacemalloc/vg_replace_malloc.c index 89a38db..95756d2 100644 --- a/coregrind/m_replacemalloc/vg_replace_malloc.c +++ b/coregrind/m_replacemalloc/vg_replace_malloc.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -42,6 +42,23 @@ It is called vg_replace_malloc.c because this filename appears in stack traces, so we want the name to be (hopefully!) meaningful to users. + + IMPORTANT: this file must not contain any floating point code, nor + any integer division. This is because on ARM these can cause calls + to helper functions, which will be unresolved within this .so. + Although it is usually the case that the client's ld.so instance + can bind them at runtime to the relevant functions in the client + executable, there is no guarantee of this; and so the client may + die via a runtime link failure. Hence the only safe approach is to + avoid such function calls in the first place. See "#define CALLOC" + below for a specific example. + + A useful command is + for f in `find . -name "*preload*.so*"` ; \ + do nm -A $f | grep " U " ; \ + done + + to see all the undefined symbols in all the preload shared objects. ------------------------------------------------------------------ */ #include "pub_core_basics.h" @@ -94,6 +111,30 @@ void *memcpy(void *destV, const void *srcV, unsigned long n) #endif +/* Compute the high word of the double-length unsigned product of U + and V. This is for calloc argument overflow checking; see comments + below. Algorithm as described in Hacker's Delight, chapter 8. */ +static UWord umulHW ( UWord u, UWord v ) +{ + UWord u0, v0, w0, rHi; + UWord u1, v1, w1,w2,t; + UWord halfMask = sizeof(UWord)==4 ? (UWord)0xFFFF + : (UWord)0xFFFFFFFFULL; + UWord halfShift = sizeof(UWord)==4 ? 16 : 32; + u0 = u & halfMask; + u1 = u >> halfShift; + v0 = v & halfMask; + v1 = v >> halfShift; + w0 = u0 * v0; + t = u1 * v0 + (w0 >> halfShift); + w1 = t & halfMask; + w2 = t >> halfShift; + w1 = u0 * v1 + w1; + rHi = u1 * v1 + w2 + (w1 >> halfShift); + return rHi; +} + + /*------------------------------------------------------------*/ /*--- Replacing malloc() et al ---*/ /*------------------------------------------------------------*/ @@ -178,7 +219,7 @@ static void init(void); v = (void*)VALGRIND_NON_SIMD_CALL1( info.tl_##vg_replacement, n ); \ MALLOC_TRACE(" = %p\n", v ); \ if (NULL == v) { \ - VALGRIND_PRINTF_BACKTRACE( \ + VALGRIND_PRINTF( \ "new/new[] failed and should throw an exception, but Valgrind\n"); \ VALGRIND_PRINTF_BACKTRACE( \ " cannot throw exceptions and so is aborting instead. Sorry.\n"); \ @@ -408,8 +449,16 @@ FREE(VG_Z_LIBC_SONAME, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete ); if (!init_done) init(); \ MALLOC_TRACE("calloc(%llu,%llu)", (ULong)nmemb, (ULong)size ); \ \ - /* Protect against overflow. See bug 24078. */ \ - if (size && nmemb > (SizeT)-1 / size) return NULL; \ + /* Protect against overflow. See bug 24078. (that bug number is + invalid. Which one really?) */ \ + /* But don't use division, since that produces an external symbol + reference on ARM, in the form of a call to __aeabi_uidiv. It's + normally OK, because ld.so manages to resolve it to something in the + executable, or one of its shared objects. But that isn't guaranteed + to be the case, and it has been observed to fail in rare cases, eg: + echo x | valgrind /bin/sed -n "s/.*-\>\ //p" + So instead compute the high word of the product and check it is zero. */ \ + if (umulHW(size, nmemb) != 0) return NULL; \ v = (void*)VALGRIND_NON_SIMD_CALL2( info.tl_calloc, nmemb, size ); \ MALLOC_TRACE(" = %p\n", v ); \ return v; \ @@ -698,7 +747,7 @@ static void panic(const char *str) { VALGRIND_PRINTF_BACKTRACE("Program aborting because of call to %s\n", str); _exit(99); - *(int *)0 = 'x'; + *(volatile int *)0 = 'x'; } #define PANIC(soname, fnname) \ diff --git a/coregrind/m_scheduler/priv_sema.h b/coregrind/m_scheduler/priv_sema.h index 6693e88..1d3b920 100644 --- a/coregrind/m_scheduler/priv_sema.h +++ b/coregrind/m_scheduler/priv_sema.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c index 0687ba8..263b7d1 100644 --- a/coregrind/m_scheduler/scheduler.c +++ b/coregrind/m_scheduler/scheduler.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -89,6 +89,7 @@ #include "pub_core_debuginfo.h" // VG_(di_notify_pdb_debuginfo) #include "priv_sema.h" #include "pub_core_scheduler.h" // self +#include "pub_core_redir.h" /* --------------------------------------------------------------------- @@ -646,6 +647,16 @@ static void do_pre_run_checks ( ThreadState* tst ) vg_assert(sz_spill == LibVEX_N_SPILL_BYTES); vg_assert(a_vex + 3 * sz_vex == a_spill); +# if defined(VGA_amd64) + /* x86/amd64 XMM regs must form an array, ie, have no + holes in between. */ + vg_assert( + (offsetof(VexGuestAMD64State,guest_XMM16) + - offsetof(VexGuestAMD64State,guest_XMM0)) + == (17/*#regs*/-1) * 16/*bytes per reg*/ + ); +# endif + # if defined(VGA_ppc32) || defined(VGA_ppc64) /* ppc guest_state vector regs must be 16 byte aligned for loads/stores. This is important! */ @@ -656,7 +667,19 @@ static void do_pre_run_checks ( ThreadState* tst ) vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VR1)); vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_VR1)); vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_VR1)); -# endif +# endif + +# if defined(VGA_arm) + /* arm guest_state VFP regs must be 8 byte aligned for + loads/stores. */ + vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex.guest_D0)); + vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow1.guest_D0)); + vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow2.guest_D0)); + /* be extra paranoid .. */ + vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex.guest_D1)); + vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow1.guest_D1)); + vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow2.guest_D1)); +# endif } @@ -842,7 +865,7 @@ static void handle_tt_miss ( ThreadId tid ) /* Trivial event. Miss in the fast-cache. Do a full lookup for it. */ found = VG_(search_transtab)( NULL, ip, True/*upd_fast_cache*/ ); - if (!found) { + if (UNLIKELY(!found)) { /* Not found; we need to request a translation. */ if (VG_(translate)( tid, ip, /*debug*/False, 0/*not verbose*/, bbs_done, True/*allow redirection*/ )) { @@ -1197,6 +1220,12 @@ VgSchedReturnCode VG_(scheduler) ( ThreadId tid ) be in on entry to Vex-generated code, and they should be unchanged on exit from it. Failure of this assertion usually means a bug in Vex's code generation. */ + //{ UInt xx; + // __asm__ __volatile__ ( + // "\t.word 0xEEF12A10\n" // fmrx r2,fpscr + // "\tmov %0, r2" : "=r"(xx) : : "r2" ); + // VG_(printf)("QQQQ new fpscr = %08x\n", xx); + //} vg_assert2(0, "VG_(scheduler), phase 3: " "run_innerloop detected host " "state invariant failure", trc); @@ -1281,6 +1310,9 @@ void VG_(nuke_all_threads_except) ( ThreadId me, VgSchedReturnCode src ) #elif defined(VGA_ppc32) || defined(VGA_ppc64) # define VG_CLREQ_ARGS guest_GPR4 # define VG_CLREQ_RET guest_GPR3 +#elif defined(VGA_arm) +# define VG_CLREQ_ARGS guest_R4 +# define VG_CLREQ_RET guest_R3 #else # error Unknown arch #endif @@ -1389,25 +1421,71 @@ void do_client_request ( ThreadId tid ) break; case VG_USERREQ__PRINTF: { + /* JRS 2010-Jan-28: this is DEPRECATED; use the + _VALIST_BY_REF version instead */ + if (sizeof(va_list) != sizeof(UWord)) + goto va_list_casting_error_NORETURN; + union { + va_list vargs; + unsigned long uw; + } u; + u.uw = (unsigned long)arg[2]; Int count = - VG_(vmessage)( Vg_ClientMsg, (char *)arg[1], (void*)arg[2] ); - VG_(message_flush)(); - SET_CLREQ_RETVAL( tid, count ); - break; } + VG_(vmessage)( Vg_ClientMsg, (char *)arg[1], u.vargs ); + VG_(message_flush)(); + SET_CLREQ_RETVAL( tid, count ); + break; + } + + case VG_USERREQ__PRINTF_BACKTRACE: { + /* JRS 2010-Jan-28: this is DEPRECATED; use the + _VALIST_BY_REF version instead */ + if (sizeof(va_list) != sizeof(UWord)) + goto va_list_casting_error_NORETURN; + union { + va_list vargs; + unsigned long uw; + } u; + u.uw = (unsigned long)arg[2]; + Int count = + VG_(vmessage)( Vg_ClientMsg, (char *)arg[1], u.vargs ); + VG_(message_flush)(); + VG_(get_and_pp_StackTrace)( tid, VG_(clo_backtrace_size) ); + SET_CLREQ_RETVAL( tid, count ); + break; + } - case VG_USERREQ__INTERNAL_PRINTF: { + case VG_USERREQ__PRINTF_VALIST_BY_REF: { + va_list* vargsp = (va_list*)arg[2]; Int count = - VG_(vmessage)( Vg_DebugMsg, (char *)arg[1], (void*)arg[2] ); - VG_(message_flush)(); - SET_CLREQ_RETVAL( tid, count ); - break; } + VG_(vmessage)( Vg_ClientMsg, (char *)arg[1], *vargsp ); + VG_(message_flush)(); + SET_CLREQ_RETVAL( tid, count ); + break; + } - case VG_USERREQ__PRINTF_BACKTRACE: { + case VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF: { + va_list* vargsp = (va_list*)arg[2]; Int count = - VG_(vmessage)( Vg_ClientMsg, (char *)arg[1], (void*)arg[2] ); - VG_(message_flush)(); - VG_(get_and_pp_StackTrace)( tid, VG_(clo_backtrace_size) ); - SET_CLREQ_RETVAL( tid, count ); + VG_(vmessage)( Vg_ClientMsg, (char *)arg[1], *vargsp ); + VG_(message_flush)(); + VG_(get_and_pp_StackTrace)( tid, VG_(clo_backtrace_size) ); + SET_CLREQ_RETVAL( tid, count ); + break; + } + + case VG_USERREQ__INTERNAL_PRINTF_VALIST_BY_REF: { + va_list* vargsp = (va_list*)arg[2]; + Int count = + VG_(vmessage)( Vg_DebugMsg, (char *)arg[1], *vargsp ); + VG_(message_flush)(); + SET_CLREQ_RETVAL( tid, count ); + break; + } + + case VG_USERREQ__ADD_IFUNC_TARGET: { + VG_(redir_add_ifunc_target)( arg[1], arg[2] ); + SET_CLREQ_RETVAL( tid, 0); break; } case VG_USERREQ__STACK_REGISTER: { @@ -1471,6 +1549,35 @@ void do_client_request ( ThreadId tid ) SET_CLREQ_RETVAL( tid, 0 ); /* return value is meaningless */ break; + case VG_USERREQ__MAP_IP_TO_SRCLOC: { + Addr ip = arg[1]; + UChar* buf64 = (UChar*)arg[2]; + + VG_(memset)(buf64, 0, 64); + UInt linenum = 0; + Bool ok = VG_(get_filename_linenum)( + ip, &buf64[0], 50, NULL, 0, NULL, &linenum + ); + if (ok) { + /* Find the terminating zero in the first 50 bytes. */ + UInt i; + for (i = 0; i < 50; i++) { + if (buf64[i] == 0) + break; + } + /* We must find a zero somewhere in 0 .. 49. Else + VG_(get_filename_linenum) is not properly zero + terminating. */ + vg_assert(i < 50); + VG_(sprintf)(&buf64[i], ":%u", linenum); + } else { + buf64[0] = 0; + } + + SET_CLREQ_RETVAL( tid, 0 ); /* return value is meaningless */ + break; + } + case VG_USERREQ__MALLOCLIKE_BLOCK: case VG_USERREQ__FREELIKE_BLOCK: // Ignore them if the addr is NULL; otherwise pass onto the tool. @@ -1513,6 +1620,32 @@ void do_client_request ( ThreadId tid ) } break; } + return; + + /*NOTREACHED*/ + va_list_casting_error_NORETURN: + VG_(umsg)( + "Valgrind: fatal error - cannot continue: use of the deprecated\n" + "client requests VG_USERREQ__PRINTF or VG_USERREQ__PRINTF_BACKTRACE\n" + "on a platform where they cannot be supported. Please use the\n" + "equivalent _VALIST_BY_REF versions instead.\n" + "\n" + "This is a binary-incompatible change in Valgrind's client request\n" + "mechanism. It is unfortunate, but difficult to avoid. End-users\n" + "are expected to almost never see this message. The only case in\n" + "which you might see this message is if your code uses the macros\n" + "VALGRIND_PRINTF or VALGRIND_PRINTF_BACKTRACE. If so, you will need\n" + "to recompile such code, using the header files from this version of\n" + "Valgrind, and not any previous version.\n" + "\n" + "If you see this mesage in any other circumstances, it is probably\n" + "a bug in Valgrind. In this case, please file a bug report at\n" + "\n" + " http://www.valgrind.org/support/bug_reports.html\n" + "\n" + "Will now abort.\n" + ); + vg_assert(0); } @@ -1623,9 +1756,11 @@ void VG_(sanity_check_general) ( Bool force_expensive ) stack = (VgStack*) VG_(get_ThreadState)(tid)->os_state.valgrind_stack_base; + SizeT limit + = 4096; // Let's say. Checking more causes lots of L2 misses. remains - = VG_(am_get_VgStack_unused_szB)(stack); - if (remains < VKI_PAGE_SIZE) + = VG_(am_get_VgStack_unused_szB)(stack, limit); + if (remains < limit) VG_(message)(Vg_DebugMsg, "WARNING: Thread %d is within %ld bytes " "of running out of stack!\n", diff --git a/coregrind/m_scheduler/sema.c b/coregrind/m_scheduler/sema.c index ed84505..25af75f 100644 --- a/coregrind/m_scheduler/sema.c +++ b/coregrind/m_scheduler/sema.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_seqmatch.c b/coregrind/m_seqmatch.c index 27270ab..c61273f 100644 --- a/coregrind/m_seqmatch.c +++ b/coregrind/m_seqmatch.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_sigframe/sigframe-amd64-darwin.c b/coregrind/m_sigframe/sigframe-amd64-darwin.c index 4898255..273dea5 100644 --- a/coregrind/m_sigframe/sigframe-amd64-darwin.c +++ b/coregrind/m_sigframe/sigframe-amd64-darwin.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks Ltd + Copyright (C) 2006-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -47,6 +47,64 @@ #include "pub_core_sigframe.h" /* self */ +/* Cheap-ass hack copied from ppc32-aix5 code, just to get started. + Produce a frame with layout entirely of our own choosing. */ + +/* This module creates and removes signal frames for signal deliveries + on amd64-darwin. Kludgey; the machine state ought to be saved in a + ucontext and retrieved from it later, so the handler can modify it + and return. However .. for now .. just stick the vex guest state + in the frame and snarf it again later. + + Also, don't bother with creating siginfo and ucontext in the + handler, although do point them somewhere non-faulting. + + Frame should have a 16-aligned size, just in case that turns out to + be important for Darwin. (be conservative) +*/ +struct hacky_sigframe { + /* first word looks like a call to a 3-arg amd64-ELF function */ + ULong returnAddr; + UChar lower_guardzone[512]; // put nothing here + VexGuestAMD64State gst; + VexGuestAMD64State gshadow1; + VexGuestAMD64State gshadow2; + vki_siginfo_t fake_siginfo; + struct vki_ucontext fake_ucontext; + UInt magicPI; + UInt sigNo_private; + vki_sigset_t mask; // saved sigmask; restore when hdlr returns + UInt __pad[2]; + UChar upper_guardzone[512]; // put nothing here + // and don't zero it, since that might overwrite the client's + // stack redzone, at least on archs which have one +}; + + +/* Extend the stack segment downwards if needed so as to ensure the + new signal frames are mapped to something. Return a Bool + indicating whether or not the operation was successful. +*/ +static Bool extend ( ThreadState *tst, Addr addr, SizeT size ) +{ + ThreadId tid = tst->tid; + /* For tracking memory events, indicate the entire frame has been + allocated. Except, don't mess with the area which + overlaps the previous frame's redzone. */ + /* XXX is the following call really right? compared with the + amd64-linux version, this doesn't appear to handle the redzone + in the same way. */ + VG_TRACK( new_mem_stack_signal, + addr - VG_STACK_REDZONE_SZB, size, tid ); + return True; +} + + +/* Create a signal frame for thread 'tid'. Make a 3-arg frame + regardless of whether the client originally requested a 1-arg + version (no SA_SIGINFO) or a 3-arg one (SA_SIGINFO) since in the + former case, the amd64 calling conventions will simply cause the + extra 2 args to be ignored (inside the handler). (We hope!) */ void VG_(sigframe_create) ( ThreadId tid, Addr sp_top_of_frame, const vki_siginfo_t *siginfo, @@ -56,13 +114,121 @@ void VG_(sigframe_create) ( ThreadId tid, const vki_sigset_t *mask, void *restorer ) { - I_die_here; + ThreadState* tst; + Addr rsp; + struct hacky_sigframe* frame; + Int sigNo = siginfo->si_signo; + + vg_assert(VG_IS_16_ALIGNED(sizeof(struct hacky_sigframe))); + + sp_top_of_frame &= ~0xfUL; + rsp = sp_top_of_frame - sizeof(struct hacky_sigframe); + + tst = VG_(get_ThreadState)(tid); + if (!extend(tst, rsp, sp_top_of_frame - rsp)) + return; + + vg_assert(VG_IS_16_ALIGNED(rsp)); + + frame = (struct hacky_sigframe *) rsp; + + /* clear it (very conservatively) (why so conservatively??) */ + VG_(memset)(&frame->lower_guardzone, 0, 512); + VG_(memset)(&frame->gst, 0, sizeof(VexGuestAMD64State)); + VG_(memset)(&frame->gshadow1, 0, sizeof(VexGuestAMD64State)); + VG_(memset)(&frame->gshadow2, 0, sizeof(VexGuestAMD64State)); + VG_(memset)(&frame->fake_siginfo, 0, sizeof(frame->fake_siginfo)); + VG_(memset)(&frame->fake_ucontext, 0, sizeof(frame->fake_ucontext)); + + /* save stuff in frame */ + frame->gst = tst->arch.vex; + frame->gshadow1 = tst->arch.vex_shadow1; + frame->gshadow2 = tst->arch.vex_shadow2; + frame->sigNo_private = sigNo; + frame->mask = tst->sig_mask; + frame->magicPI = 0x31415927; + + /* Minimally fill in the siginfo and ucontext. Note, utter + lameness prevails. Be underwhelmed, be very underwhelmed. */ + frame->fake_siginfo.si_signo = sigNo; + frame->fake_siginfo.si_code = siginfo->si_code; + + /* Set up stack pointer */ + vg_assert(rsp == (Addr)&frame->returnAddr); + VG_(set_SP)(tid, rsp); + VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, sizeof(ULong)); + + /* Set up program counter */ + VG_(set_IP)(tid, (ULong)handler); + VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_INSTR_PTR, sizeof(ULong)); + + /* Set up RA and args for the frame */ + VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal handler frame", + (Addr)frame, 1*sizeof(ULong) ); + frame->returnAddr = (ULong)&VG_(amd64_darwin_SUBST_FOR_sigreturn); + + /* XXX should tell the tool that these regs got written */ + tst->arch.vex.guest_RDI = (ULong) sigNo; + tst->arch.vex.guest_RSI = (Addr) &frame->fake_siginfo;/* oh well */ + tst->arch.vex.guest_RDX = (Addr) &frame->fake_ucontext; /* oh well */ + + VG_TRACK( post_mem_write, Vg_CoreSignal, tid, + (Addr)frame, 1*sizeof(ULong) ); + VG_TRACK( post_mem_write, Vg_CoreSignal, tid, + (Addr)&frame->fake_siginfo, sizeof(frame->fake_siginfo)); + VG_TRACK( post_mem_write, Vg_CoreSignal, tid, + (Addr)&frame->fake_ucontext, sizeof(frame->fake_ucontext)); + + if (VG_(clo_trace_signals)) + VG_(message)(Vg_DebugMsg, + "sigframe_create (thread %d): next EIP=%#lx, next ESP=%#lx", + tid, (Addr)handler, (Addr)frame ); } +/* Remove a signal frame from thread 'tid's stack, and restore the CPU + state from it. Note, isRT is irrelevant here. */ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) { - I_die_here; + ThreadState *tst; + Addr rsp; + Int sigNo; + struct hacky_sigframe* frame; + + vg_assert(VG_(is_valid_tid)(tid)); + tst = VG_(get_ThreadState)(tid); + + /* Check that the stack frame looks valid */ + rsp = VG_(get_SP)(tid); + + /* why -8 ? because the signal handler's return will have popped + the return address of the stack; and the return address is the + lowest-addressed element of hacky_sigframe. */ + frame = (struct hacky_sigframe*)(rsp - 8); + vg_assert(frame->magicPI == 0x31415927); + vg_assert(VG_IS_16_ALIGNED(frame)); + + /* restore the entire guest state, and shadows, from the + frame. Note, as per comments above, this is a kludge - should + restore it from saved ucontext. Oh well. */ + tst->arch.vex = frame->gst; + tst->arch.vex_shadow1 = frame->gshadow1; + tst->arch.vex_shadow2 = frame->gshadow2; + tst->sig_mask = frame->mask; + tst->tmp_sig_mask = frame->mask; + sigNo = frame->sigNo_private; + + if (VG_(clo_trace_signals)) + VG_(message)(Vg_DebugMsg, + "sigframe_destroy (thread %d): valid magic; next RIP=%#llx", + tid, tst->arch.vex.guest_RIP); + + VG_TRACK( die_mem_stack_signal, + (Addr)frame - VG_STACK_REDZONE_SZB, + sizeof(struct hacky_sigframe) ); + + /* tell the tools */ + VG_TRACK( post_deliver_signal, tid, sigNo ); } #endif // defined(VGP_amd64_darwin) diff --git a/coregrind/m_sigframe/sigframe-amd64-linux.c b/coregrind/m_sigframe/sigframe-amd64-linux.c index 30f78dc..b234e3a 100644 --- a/coregrind/m_sigframe/sigframe-amd64-linux.c +++ b/coregrind/m_sigframe/sigframe-amd64-linux.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_sigframe/sigframe-arm-linux.c b/coregrind/m_sigframe/sigframe-arm-linux.c new file mode 100644 index 0000000..01c1c05 --- /dev/null +++ b/coregrind/m_sigframe/sigframe-arm-linux.c @@ -0,0 +1,338 @@ + +/*--------------------------------------------------------------------*/ +/*--- Create/destroy signal delivery frames. ---*/ +/*--- sigframe-arm-linux.c ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2000-2010 Nicholas Nethercote + njn@valgrind.org + Copyright (C) 2004-2010 Paul Mackerras + paulus@samba.org + Copyright (C) 2008-2010 Evan Geller + gaze@bea.ms + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#if defined(VGP_arm_linux) + +#include "pub_core_basics.h" +#include "pub_core_vki.h" +#include "pub_core_vkiscnums.h" +#include "pub_core_threadstate.h" +#include "pub_core_aspacemgr.h" +#include "pub_core_libcbase.h" +#include "pub_core_libcassert.h" +#include "pub_core_libcprint.h" +#include "pub_core_machine.h" +#include "pub_core_options.h" +#include "pub_core_sigframe.h" +#include "pub_core_signals.h" +#include "pub_core_tooliface.h" +#include "pub_core_trampoline.h" +#include "pub_core_transtab.h" // VG_(discard_translations) + + +struct vg_sig_private { + UInt magicPI; + UInt sigNo_private; + VexGuestARMState vex_shadow1; + VexGuestARMState vex_shadow2; +}; + +struct sigframe { + struct vki_ucontext uc; + unsigned long retcode[2]; + struct vg_sig_private vp; +}; + +struct rt_sigframe { + vki_siginfo_t info; + struct sigframe sig; +}; + +static Bool extend ( ThreadState *tst, Addr addr, SizeT size ) +{ + ThreadId tid = tst->tid; + NSegment const* stackseg = NULL; + + if (VG_(extend_stack)(addr, tst->client_stack_szB)) { + stackseg = VG_(am_find_nsegment)(addr); + if (0 && stackseg) + VG_(printf)("frame=%#lx seg=%#lx-%#lx\n", + addr, stackseg->start, stackseg->end); + } + + if (stackseg == NULL || !stackseg->hasR || !stackseg->hasW) { + VG_(message)( + Vg_UserMsg, + "Can't extend stack to %#lx during signal delivery for thread %d:", + addr, tid); + if (stackseg == NULL) + VG_(message)(Vg_UserMsg, " no stack segment"); + else + VG_(message)(Vg_UserMsg, " too small or bad protection modes"); + + /* set SIGSEGV to default handler */ + VG_(set_default_handler)(VKI_SIGSEGV); + VG_(synth_fault_mapping)(tid, addr); + + /* The whole process should be about to die, since the default + action of SIGSEGV to kill the whole process. */ + return False; + } + + /* For tracking memory events, indicate the entire frame has been + allocated. */ + VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB, + size + VG_STACK_REDZONE_SZB, tid ); + + return True; +} + +static void synth_ucontext( ThreadId tid, const vki_siginfo_t *si, + UWord trapno, UWord err, const vki_sigset_t *set, + struct vki_ucontext *uc){ + + ThreadState *tst = VG_(get_ThreadState)(tid); + struct vki_sigcontext *sc = &uc->uc_mcontext; + + VG_(memset)(uc, 0, sizeof(*uc)); + + uc->uc_flags = 0; + uc->uc_link = 0; + uc->uc_sigmask = *set; + uc->uc_stack = tst->altstack; + +# define SC2(reg,REG) sc->arm_##reg = tst->arch.vex.guest_##REG + SC2(r0,R0); + SC2(r1,R1); + SC2(r2,R2); + SC2(r3,R3); + SC2(r4,R4); + SC2(r5,R5); + SC2(r6,R6); + SC2(r7,R7); + SC2(r8,R8); + SC2(r9,R9); + SC2(r10,R10); + SC2(fp,R11); + SC2(ip,R12); + SC2(sp,R13); + SC2(lr,R14); + SC2(pc,R15T); +# undef SC2 + + sc->trap_no = trapno; + sc->error_code = err; + sc->fault_address = (UInt)si->_sifields._sigfault._addr; +} + + +static void build_sigframe(ThreadState *tst, + struct sigframe *frame, + const vki_siginfo_t *siginfo, + const struct vki_ucontext *siguc, + void *handler, UInt flags, + const vki_sigset_t *mask, + void *restorer){ + + UWord trapno; + UWord err; + Int sigNo = siginfo->si_signo; + struct vg_sig_private *priv = &frame->vp; + + VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, "signal handler frame", + (Addr)frame, offsetof(struct sigframe, vp)); + + if(siguc) { + trapno = siguc->uc_mcontext.trap_no; + err = siguc->uc_mcontext.error_code; + } else { + trapno = 0; + err = 0; + } + + synth_ucontext(tst->tid, siginfo, trapno, err, mask, &frame->uc); + + VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, + (Addr)frame, offsetof(struct sigframe, vp)); + + priv->magicPI = 0x31415927; + priv->sigNo_private = sigNo; + priv->vex_shadow1 = tst->arch.vex_shadow1; + priv->vex_shadow2 = tst->arch.vex_shadow2; + +} + + + +/* EXPORTED */ +void VG_(sigframe_create)( ThreadId tid, + Addr sp_top_of_frame, + const vki_siginfo_t *siginfo, + const struct vki_ucontext *siguc, + void *handler, + UInt flags, + const vki_sigset_t *mask, + void *restorer ) +{ +// struct vg_sig_private *priv; + Addr sp = sp_top_of_frame; + ThreadState *tst; + Int sigNo = siginfo->si_signo; +// Addr faultaddr; + UInt size; + + tst = VG_(get_ThreadState)(tid); + + size = flags & VKI_SA_SIGINFO ? sizeof(struct rt_sigframe) : + sizeof(struct sigframe); + + sp -= size; + sp = VG_ROUNDDN(sp, 16); + + if(!extend(tst, sp, size)) + I_die_here; // XXX Incorrect behavior + + + if (flags & VKI_SA_SIGINFO){ + struct rt_sigframe *rsf = (struct rt_sigframe *)sp; + + /* Track our writes to siginfo */ + VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, /* VVVVV */ + "signal handler siginfo", (Addr)rsf, + offsetof(struct rt_sigframe, sig)); + + VG_(memcpy)(&rsf->info, siginfo, sizeof(vki_siginfo_t)); + + if(sigNo == VKI_SIGILL && siginfo->si_code > 0) { + rsf->info._sifields._sigfault._addr = (Addr *) (tst)->arch.vex.guest_R12; /* IP */ + } + VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, /* ^^^^^ */ + (Addr)rsf, offsetof(struct rt_sigframe, sig)); + + build_sigframe(tst, &rsf->sig, siginfo, siguc, + handler, flags, mask, restorer); + tst->arch.vex.guest_R1 = (Addr)&rsf->info; + tst->arch.vex.guest_R2 = (Addr)&rsf->sig.uc; + } + else { + build_sigframe(tst, (struct sigframe *)sp, siginfo, siguc, + handler, flags, mask, restorer); + } + + VG_(set_SP)(tid, sp); + VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, + sizeof(Addr)); + tst->arch.vex.guest_R0 = sigNo; + + if (flags & VKI_SA_RESTORER) + tst->arch.vex.guest_R14 = (Addr) restorer; + + tst->arch.vex.guest_R15T = (Addr) handler; /* R15 == PC */ +} + + +/*------------------------------------------------------------*/ +/*--- Destroying signal frames ---*/ +/*------------------------------------------------------------*/ + +/* EXPORTED */ +void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) +{ + ThreadState *tst; + struct vg_sig_private *priv; + Addr sp; + UInt frame_size; + struct vki_sigcontext *mc; + Int sigNo; + Bool has_siginfo = isRT; + + vg_assert(VG_(is_valid_tid)(tid)); + tst = VG_(get_ThreadState)(tid); + sp = tst->arch.vex.guest_R13; + + if (has_siginfo) { + struct rt_sigframe *frame = (struct rt_sigframe *)sp; + frame_size = sizeof(*frame); + mc = &frame->sig.uc.uc_mcontext; + priv = &frame->sig.vp; + vg_assert(priv->magicPI == 0x31415927); + tst->sig_mask = frame->sig.uc.uc_sigmask; + } else { + struct sigframe *frame = (struct sigframe *)sp; + frame_size = sizeof(*frame); + mc = &frame->uc.uc_mcontext; + priv = &frame->vp; + vg_assert(priv->magicPI == 0x31415927); + tst->sig_mask = frame->uc.uc_sigmask; + /*tst->sig_mask.sig[0] = frame->uc.uc_mcontext.oldmask; + tst->sig_mask.sig[1] = frame->uc.uc_mcontext._unused[3]; + VG_(printf)("Setting signmask to %08x%08x\n",tst->sig_mask[0],tst->sig_mask[1]); +*/ + } + tst->tmp_sig_mask = tst->sig_mask; + + sigNo = priv->sigNo_private; + + //XXX: restore regs +# define REST(reg,REG) tst->arch.vex.guest_##REG = mc->arm_##reg; + REST(r0,R0); + REST(r1,R1); + REST(r2,R2); + REST(r3,R3); + REST(r4,R4); + REST(r5,R5); + REST(r6,R6); + REST(r7,R7); + REST(r8,R8); + REST(r9,R9); + REST(r10,R10); + REST(fp,R11); + REST(ip,R12); + REST(sp,R13); + REST(lr,R14); + REST(pc,R15T); +# undef REST + + tst->arch.vex_shadow1 = priv->vex_shadow1; + tst->arch.vex_shadow2 = priv->vex_shadow2; + + VG_TRACK( die_mem_stack_signal, sp - VG_STACK_REDZONE_SZB, + frame_size + VG_STACK_REDZONE_SZB ); + + if (VG_(clo_trace_signals)) + VG_(message)(Vg_DebugMsg, + "vg_pop_signal_frame (thread %d): " + "isRT=%d valid magic; PC=%#x", + tid, has_siginfo, tst->arch.vex.guest_R15T); + + /* tell the tools */ + VG_TRACK( post_deliver_signal, tid, sigNo ); +} + +#endif // defined(VGP_arm_linux) + +/*--------------------------------------------------------------------*/ +/*--- end sigframe-arm-linux.c ---*/ +/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_sigframe/sigframe-ppc32-aix5.c b/coregrind/m_sigframe/sigframe-ppc32-aix5.c index d6b6e28..999fe20 100644 --- a/coregrind/m_sigframe/sigframe-ppc32-aix5.c +++ b/coregrind/m_sigframe/sigframe-ppc32-aix5.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_sigframe/sigframe-ppc32-linux.c b/coregrind/m_sigframe/sigframe-ppc32-linux.c index 7144230..9710b37 100644 --- a/coregrind/m_sigframe/sigframe-ppc32-linux.c +++ b/coregrind/m_sigframe/sigframe-ppc32-linux.c @@ -8,9 +8,9 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2004-2009 Paul Mackerras + Copyright (C) 2004-2010 Paul Mackerras paulus@samba.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_sigframe/sigframe-ppc64-aix5.c b/coregrind/m_sigframe/sigframe-ppc64-aix5.c index 1f94a93..474b933 100644 --- a/coregrind/m_sigframe/sigframe-ppc64-aix5.c +++ b/coregrind/m_sigframe/sigframe-ppc64-aix5.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_sigframe/sigframe-ppc64-linux.c b/coregrind/m_sigframe/sigframe-ppc64-linux.c index f3cd180..0328378 100644 --- a/coregrind/m_sigframe/sigframe-ppc64-linux.c +++ b/coregrind/m_sigframe/sigframe-ppc64-linux.c @@ -8,9 +8,9 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2004-2009 Paul Mackerras + Copyright (C) 2004-2010 Paul Mackerras paulus@samba.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_sigframe/sigframe-x86-darwin.c b/coregrind/m_sigframe/sigframe-x86-darwin.c index 3b5a018..383a8d3 100644 --- a/coregrind/m_sigframe/sigframe-x86-darwin.c +++ b/coregrind/m_sigframe/sigframe-x86-darwin.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks Ltd + Copyright (C) 2006-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -79,6 +79,8 @@ struct hacky_sigframe { vki_sigset_t mask; // saved sigmask; restore when hdlr returns UInt __pad[1]; UChar upper_guardzone[512]; // put nothing here + // and don't zero it, since that might overwrite the client's + // stack redzone, at least on archs which have one }; @@ -96,7 +98,7 @@ static Bool extend ( ThreadState *tst, Addr addr, SizeT size ) amd64-linux version, this doesn't appear to handle the redzone in the same way. */ VG_TRACK( new_mem_stack_signal, - addr, size - VG_STACK_REDZONE_SZB, tid ); + addr - VG_STACK_REDZONE_SZB, size, tid ); return True; } @@ -222,8 +224,8 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) tid, tst->arch.vex.guest_EIP); VG_TRACK( die_mem_stack_signal, - (Addr)frame, - sizeof(struct hacky_sigframe) - VG_STACK_REDZONE_SZB ); + (Addr)frame - VG_STACK_REDZONE_SZB, + sizeof(struct hacky_sigframe) ); /* tell the tools */ VG_TRACK( post_deliver_signal, tid, sigNo ); diff --git a/coregrind/m_sigframe/sigframe-x86-linux.c b/coregrind/m_sigframe/sigframe-x86-linux.c index cfaaafb..6b61055 100644 --- a/coregrind/m_sigframe/sigframe-x86-linux.c +++ b/coregrind/m_sigframe/sigframe-x86-linux.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c index 59522f3..b006225 100644 --- a/coregrind/m_signals.c +++ b/coregrind/m_signals.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -54,17 +54,13 @@ a signal with kill, its expected to be synchronous: ie, the signal will have been delivered by the time the syscall finishes. - 4. Asyncronous, general signals. All other signals, sent by + 4. Asynchronous, general signals. All other signals, sent by another process with kill. These are generally blocked, except for two special cases: we poll for them each time we're about to run a thread for a time quanta, and while running blocking syscalls. - In addition, we define two signals for internal use: SIGVGCHLD and - SIGVGKILL. SIGVGCHLD is used to indicate thread death to any - reaping thread (the master thread). It is always blocked and never - delivered as a signal; it is always polled with sigtimedwait. - + In addition, we reserve one signal for internal use: SIGVGKILL. SIGVGKILL is used to terminate threads. When one thread wants another to exit, it will set its exitreason and send it SIGVGKILL if it appears to be blocked in a syscall. @@ -263,23 +259,30 @@ typedef struct SigQueue { meaningless, so the caller of VG_UCONTEXT_SYSCALL_SYSRES has to be very careful to pay attention to the results only when it is sure that the said constraint on the program counter is indeed valid. */ + #if defined(VGP_x86_linux) # define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.eip) # define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.esp) -# define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_mcontext.ebp) # define VG_UCONTEXT_SYSCALL_SYSRES(uc) \ /* Convert the value in uc_mcontext.eax into a SysRes. */ \ VG_(mk_SysRes_x86_linux)( (uc)->uc_mcontext.eax ) -# define VG_UCONTEXT_LINK_REG(uc) 0 /* Dude, where's my LR? */ +# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ + { (srP)->r_pc = (ULong)((uc)->uc_mcontext.eip); \ + (srP)->r_sp = (ULong)((uc)->uc_mcontext.esp); \ + (srP)->misc.X86.r_ebp = (uc)->uc_mcontext.ebp; \ + } #elif defined(VGP_amd64_linux) # define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.rip) # define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.rsp) -# define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_mcontext.rbp) # define VG_UCONTEXT_SYSCALL_SYSRES(uc) \ /* Convert the value in uc_mcontext.rax into a SysRes. */ \ VG_(mk_SysRes_amd64_linux)( (uc)->uc_mcontext.rax ) -# define VG_UCONTEXT_LINK_REG(uc) 0 /* No LR on amd64 either */ +# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ + { (srP)->r_pc = (uc)->uc_mcontext.rip; \ + (srP)->r_sp = (uc)->uc_mcontext.rsp; \ + (srP)->misc.AMD64.r_rbp = (uc)->uc_mcontext.rbp; \ + } #elif defined(VGP_ppc32_linux) /* Comments from Paul Mackerras 25 Nov 05: @@ -326,21 +329,23 @@ typedef struct SigQueue { uc->uc_regs->mc_gregs[PT_MSR], otherwise it clears it. That bit will always be clear under 2.4.20. So you can use that bit to tell whether uc->uc_regs->mc_vregs is valid. */ -# define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_regs->mc_gregs[VKI_PT_NIP]) -# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_regs->mc_gregs[VKI_PT_R1]) -# define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_regs->mc_gregs[VKI_PT_R1]) +# define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_regs->mc_gregs[VKI_PT_NIP]) +# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_regs->mc_gregs[VKI_PT_R1]) # define VG_UCONTEXT_SYSCALL_SYSRES(uc) \ /* Convert the values in uc_mcontext r3,cr into a SysRes. */ \ VG_(mk_SysRes_ppc32_linux)( \ (uc)->uc_regs->mc_gregs[VKI_PT_R3], \ (((uc)->uc_regs->mc_gregs[VKI_PT_CCR] >> 28) & 1) \ ) -# define VG_UCONTEXT_LINK_REG(uc) ((uc)->uc_regs->mc_gregs[VKI_PT_LNK]) +# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ + { (srP)->r_pc = (ULong)((uc)->uc_regs->mc_gregs[VKI_PT_NIP]); \ + (srP)->r_sp = (ULong)((uc)->uc_regs->mc_gregs[VKI_PT_R1]); \ + (srP)->misc.PPC32.r_lr = (uc)->uc_regs->mc_gregs[VKI_PT_LNK]; \ + } #elif defined(VGP_ppc64_linux) -# define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_NIP]) -# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_R1]) -# define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_R1]) +# define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_NIP]) +# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_R1]) /* Dubious hack: if there is an error, only consider the lowest 8 bits of r3. memcheck/tests/post-syscall shows a case where an interrupted syscall should have produced a ucontext with 0x4 @@ -355,7 +360,26 @@ typedef struct SigQueue { if (err) r3 &= 0xFF; return VG_(mk_SysRes_ppc64_linux)( r3, err ); } -# define VG_UCONTEXT_LINK_REG(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_LNK]) +# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ + { (srP)->r_pc = (uc)->uc_mcontext.gp_regs[VKI_PT_NIP]; \ + (srP)->r_sp = (uc)->uc_mcontext.gp_regs[VKI_PT_R1]; \ + (srP)->misc.PPC64.r_lr = (uc)->uc_mcontext.gp_regs[VKI_PT_LNK]; \ + } + +#elif defined(VGP_arm_linux) +# define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.arm_pc) +# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.arm_sp) +# define VG_UCONTEXT_SYSCALL_SYSRES(uc) \ + /* Convert the value in uc_mcontext.rax into a SysRes. */ \ + VG_(mk_SysRes_arm_linux)( (uc)->uc_mcontext.arm_r0 ) +# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ + { (srP)->r_pc = (uc)->uc_mcontext.arm_pc; \ + (srP)->r_sp = (uc)->uc_mcontext.arm_sp; \ + (srP)->misc.ARM.r14 = (uc)->uc_mcontext.arm_lr; \ + (srP)->misc.ARM.r12 = (uc)->uc_mcontext.arm_ip; \ + (srP)->misc.ARM.r11 = (uc)->uc_mcontext.arm_fp; \ + (srP)->misc.ARM.r7 = (uc)->uc_mcontext.arm_r7; \ + } #elif defined(VGP_ppc32_aix5) @@ -470,14 +494,15 @@ typedef struct SigQueue { return VG_(mk_SysRes_x86_darwin)( scclass, err ? True : False, wHI, wLO ); } - static inline Addr VG_UCONTEXT_LINK_REG( void* ucV ) { - return 0; /* No, really. We have no LRs today. */ - } - static inline Addr VG_UCONTEXT_FRAME_PTR( void* ucV ) { - ucontext_t* uc = (ucontext_t*)ucV; + static inline + void VG_UCONTEXT_TO_UnwindStartRegs( UnwindStartRegs* srP, + void* ucV ) { + ucontext_t* uc = (ucontext_t*)(ucV); struct __darwin_mcontext32* mc = uc->uc_mcontext; struct __darwin_i386_thread_state* ss = &mc->__ss; - return ss->__ebp; + srP->r_pc = (ULong)(ss->__eip); + srP->r_sp = (ULong)(ss->__esp); + srP->misc.X86.r_ebp = (UInt)(ss->__ebp); } #elif defined(VGP_amd64_darwin) @@ -492,10 +517,9 @@ typedef struct SigQueue { UWord scclass ) { I_die_here; } - static inline Addr VG_UCONTEXT_LINK_REG( void* ucV ) { - return 0; /* No, really. We have no LRs today. */ - } - static inline Addr VG_UCONTEXT_FRAME_PTR( void* ucV ) { + static inline + void VG_UCONTEXT_TO_UnwindStartRegs( UnwindStartRegs* srP, + void* ucV ) { I_die_here; } @@ -789,6 +813,7 @@ extern void my_sigreturn(void); " movl $" #name ", %eax\n" \ " int $0x80\n" \ ".previous\n" + #elif defined(VGP_amd64_linux) # define _MY_SIGRETURN(name) \ ".text\n" \ @@ -796,6 +821,7 @@ extern void my_sigreturn(void); " movq $" #name ", %rax\n" \ " syscall\n" \ ".previous\n" + #elif defined(VGP_ppc32_linux) # define _MY_SIGRETURN(name) \ ".text\n" \ @@ -803,6 +829,7 @@ extern void my_sigreturn(void); " li 0, " #name "\n" \ " sc\n" \ ".previous\n" + #elif defined(VGP_ppc64_linux) # define _MY_SIGRETURN(name) \ ".align 2\n" \ @@ -817,6 +844,15 @@ extern void my_sigreturn(void); ".my_sigreturn:\n" \ " li 0, " #name "\n" \ " sc\n" + +#elif defined(VGP_arm_linux) +# define _MY_SIGRETURN(name) \ + ".text\n" \ + "my_sigreturn:\n\t" \ + " mov r7, #" #name "\n\t" \ + " svc 0x00000000\n" \ + ".previous\n" + #elif defined(VGP_ppc32_aix5) # define _MY_SIGRETURN(name) \ ".globl my_sigreturn\n" \ @@ -827,18 +863,21 @@ extern void my_sigreturn(void); ".globl my_sigreturn\n" \ "my_sigreturn:\n" \ ".long 0\n" + #elif defined(VGP_x86_darwin) # define _MY_SIGRETURN(name) \ ".text\n" \ "my_sigreturn:\n" \ "movl $" VG_STRINGIFY(__NR_DARWIN_FAKE_SIGRETURN) ",%eax\n" \ "int $0x80" + #elif defined(VGP_amd64_darwin) // DDD: todo # define _MY_SIGRETURN(name) \ ".text\n" \ "my_sigreturn:\n" \ "ud2\n" + #else # error Unknown platform #endif @@ -964,7 +1003,7 @@ SysRes VG_(do_sys_sigaltstack) ( ThreadId tid, vki_stack_t* ss, vki_stack_t* oss m_SP = VG_(get_SP)(tid); if (VG_(clo_trace_signals)) - VG_(emsg)("sys_sigaltstack: tid %d, " + VG_(dmsg)("sys_sigaltstack: tid %d, " "ss %p{%p,sz=%llu,flags=0x%llx}, oss %p (current SP %p)\n", tid, (void*)ss, ss ? ss->ss_sp : 0, @@ -1009,7 +1048,7 @@ SysRes VG_(do_sys_sigaction) ( Int signo, vki_sigaction_fromK_t* old_act ) { if (VG_(clo_trace_signals)) - VG_(emsg)("sys_sigaction: sigNo %d, " + VG_(dmsg)("sys_sigaction: sigNo %d, " "new %#lx, old %#lx, new flags 0x%llx\n", signo, (UWord)new_act, (UWord)old_act, (ULong)(new_act ? new_act->sa_flags : 0)); @@ -1160,7 +1199,7 @@ void do_setmask ( ThreadId tid, vki_sigset_t* oldset ) { if (VG_(clo_trace_signals)) - VG_(emsg)("do_setmask: tid = %d how = %d (%s), newset = %p (%s)\n", + VG_(dmsg)("do_setmask: tid = %d how = %d (%s), newset = %p (%s)\n", tid, how, how==VKI_SIG_BLOCK ? "SIG_BLOCK" : ( how==VKI_SIG_UNBLOCK ? "SIG_UNBLOCK" : ( @@ -1172,7 +1211,7 @@ void do_setmask ( ThreadId tid, if (oldset) { *oldset = VG_(threads)[tid].sig_mask; if (VG_(clo_trace_signals)) - VG_(emsg)("\toldset=%p %s\n", oldset, format_sigset(oldset)); + VG_(dmsg)("\toldset=%p %s\n", oldset, format_sigset(oldset)); } if (newset) { do_sigprocmask_bitops (how, &VG_(threads)[tid].sig_mask, newset ); @@ -2328,11 +2367,11 @@ void sync_signalhandler_from_kernel ( ThreadId tid, // tid = VG_(master_tid); vg_assert(tid != 0); - VG_(core_panic_at)("Killed by fatal signal", - VG_UCONTEXT_INSTR_PTR(uc), - VG_UCONTEXT_STACK_PTR(uc), - VG_UCONTEXT_FRAME_PTR(uc), - VG_UCONTEXT_LINK_REG(uc)); + UnwindStartRegs startRegs; + VG_(memset)(&startRegs, 0, sizeof(startRegs)); + + VG_UCONTEXT_TO_UnwindStartRegs(&startRegs, uc); + VG_(core_panic_at)("Killed by fatal signal", &startRegs); } } @@ -2549,7 +2588,7 @@ void VG_(sigstartup_actions) ( void ) /* Get the old host action */ ret = VG_(sigaction)(i, NULL, &sa); -# if defined(VGP_x86_darwin) +# if defined(VGP_x86_darwin) || defined(VGP_amd64_darwin) /* apparently we may not even ask about the disposition of these signals, let alone change them */ if (ret != 0 && (i == VKI_SIGKILL || i == VKI_SIGSTOP)) diff --git a/coregrind/m_sparsewa.c b/coregrind/m_sparsewa.c index e8f4965..db395ae 100644 --- a/coregrind/m_sparsewa.c +++ b/coregrind/m_sparsewa.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_stacks.c b/coregrind/m_stacks.c index c9e9abf..f445749 100644 --- a/coregrind/m_stacks.c +++ b/coregrind/m_stacks.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_stacktrace.c b/coregrind/m_stacktrace.c index 3f02286..645b459 100644 --- a/coregrind/m_stacktrace.c +++ b/coregrind/m_stacktrace.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -44,8 +44,11 @@ #include "pub_core_clientstate.h" // VG_(client__dl_sysinfo_int80) #include "pub_core_trampoline.h" + /*------------------------------------------------------------*/ -/*--- Exported functions. ---*/ +/*--- ---*/ +/*--- BEGIN platform-dependent unwinder worker functions ---*/ +/*--- ---*/ /*------------------------------------------------------------*/ /* Take a snapshot of the client's stack, putting up to 'max_n_ips' @@ -57,23 +60,17 @@ first parameter, else send zero. This helps generate better stack traces on ppc64-linux and has no effect on other platforms. */ + +/* ------------------------ x86 ------------------------- */ + +#if defined(VGP_x86_linux) || defined(VGP_x86_darwin) || defined(VGP_x86_freebsd) + UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, /*OUT*/Addr* ips, UInt max_n_ips, /*OUT*/Addr* sps, /*OUT*/Addr* fps, - Addr ip, Addr sp, Addr fp, Addr lr, - Addr fp_min, Addr fp_max_orig ) + UnwindStartRegs* startRegs, + Addr fp_max_orig ) { -# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_ppc32_aix5) \ - || defined(VGP_ppc64_aix5) - Bool lr_is_first_RA = False; -# endif -# if defined(VGP_ppc64_linux) || defined(VGP_ppc64_aix5) \ - || defined(VGP_ppc32_aix5) - Word redir_stack_size = 0; - Word redirs_used = 0; -# endif - Bool debug = False; Int i; Addr fp_max; @@ -82,6 +79,12 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, vg_assert(sizeof(Addr) == sizeof(UWord)); vg_assert(sizeof(Addr) == sizeof(void*)); + D3UnwindRegs uregs; + uregs.xip = (Addr)startRegs->r_pc; + uregs.xsp = (Addr)startRegs->r_sp; + uregs.xbp = startRegs->misc.X86.r_ebp; + Addr fp_min = uregs.xsp; + /* Snaffle IPs from the client's stack into ips[0 .. max_n_ips-1], stopping when the trail goes cold, which we guess to be when FP is not a reasonable stack location. */ @@ -96,38 +99,30 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, if (debug) VG_(printf)("max_n_ips=%d fp_min=0x%lx fp_max_orig=0x%lx, " "fp_max=0x%lx ip=0x%lx fp=0x%lx\n", - max_n_ips, fp_min, fp_max_orig, fp_max, ip, fp); + max_n_ips, fp_min, fp_max_orig, fp_max, + uregs.xip, uregs.xbp); /* Assertion broken before main() is reached in pthreaded programs; the * offending stack traces only have one item. --njn, 2002-aug-16 */ /* vg_assert(fp_min <= fp_max);*/ // On Darwin, this kicks in for pthread-related stack traces, so they're // only 1 entry long which is wrong. -#if !defined(VGO_darwin) +# if !defined(VGO_darwin) if (fp_min + 512 >= fp_max) { /* If the stack limits look bogus, don't poke around ... but don't bomb out either. */ - if (sps) sps[0] = sp; - if (fps) fps[0] = fp; - ips[0] = ip; + if (sps) sps[0] = uregs.xsp; + if (fps) fps[0] = uregs.xbp; + ips[0] = uregs.xip; return 1; } -#endif - - /* Otherwise unwind the stack in a platform-specific way. Trying - to merge the x86, amd64, ppc32 and ppc64 logic into a single - piece of code is just too confusing and difficult to - performance-tune. */ - -# if defined(VGP_x86_linux) || defined(VGP_x86_darwin) || defined(VGP_x86_freebsd) - - /*--------------------- x86 ---------------------*/ +# endif /* fp is %ebp. sp is %esp. ip is %eip. */ - if (sps) sps[0] = sp; - if (fps) fps[0] = fp; - ips[0] = ip; + if (sps) sps[0] = uregs.xsp; + if (fps) fps[0] = uregs.xbp; + ips[0] = uregs.xip; i = 1; /* Loop unwinding the stack. Note that the IP value we get on @@ -160,52 +155,55 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, fails, and is expensive. */ /* Deal with frames resulting from functions which begin "pushl% ebp ; movl %esp, %ebp" which is the ABI-mandated preamble. */ - if (fp_min <= fp && - fp <= fp_max - 1 * sizeof(UWord)/*see comment below*/) + if (fp_min <= uregs.xbp && + uregs.xbp <= fp_max - 1 * sizeof(UWord)/*see comment below*/) { /* fp looks sane, so use it. */ - ip = (((UWord*)fp)[1]); + uregs.xip = (((UWord*)uregs.xbp)[1]); // We stop if we hit a zero (the traditional end-of-stack // marker) or a one -- these correspond to recorded IPs of 0 or -1. // The latter because r8818 (in this file) changes the meaning of // entries [1] and above in a stack trace, by subtracting 1 from // them. Hence stacks that used to end with a zero value now end in // -1 and so we must detect that too. - if (0 == ip || 1 == ip) break; - sp = fp + sizeof(Addr) /*saved %ebp*/ - + sizeof(Addr) /*ra*/; - fp = (((UWord*)fp)[0]); - if (sps) sps[i] = sp; - if (fps) fps[i] = fp; - ips[i++] = ip - 1; /* -1: refer to calling insn, not the RA */ + if (0 == uregs.xip || 1 == uregs.xip) break; + uregs.xsp = uregs.xbp + sizeof(Addr) /*saved %ebp*/ + + sizeof(Addr) /*ra*/; + uregs.xbp = (((UWord*)uregs.xbp)[0]); + if (sps) sps[i] = uregs.xsp; + if (fps) fps[i] = uregs.xbp; + ips[i++] = uregs.xip - 1; /* -1: refer to calling insn, not the RA */ if (debug) VG_(printf)(" ipsF[%d]=0x%08lx\n", i-1, ips[i-1]); - ip = ip - 1; /* as per comment at the head of this loop */ + uregs.xip = uregs.xip - 1; + /* as per comment at the head of this loop */ continue; } /* That didn't work out, so see if there is any CF info to hand which can be used. */ - if ( VG_(use_CF_info)( &ip, &sp, &fp, fp_min, fp_max ) ) { - if (0 == ip || 1 == ip) break; - if (sps) sps[i] = sp; - if (fps) fps[i] = fp; - ips[i++] = ip - 1; /* -1: refer to calling insn, not the RA */ + if ( VG_(use_CF_info)( &uregs, fp_min, fp_max ) ) { + if (0 == uregs.xip || 1 == uregs.xip) break; + if (sps) sps[i] = uregs.xsp; + if (fps) fps[i] = uregs.xbp; + ips[i++] = uregs.xip - 1; /* -1: refer to calling insn, not the RA */ if (debug) VG_(printf)(" ipsC[%d]=0x%08lx\n", i-1, ips[i-1]); - ip = ip - 1; /* as per comment at the head of this loop */ + uregs.xip = uregs.xip - 1; + /* as per comment at the head of this loop */ continue; } /* And, similarly, try for MSVC FPO unwind info. */ - if ( VG_(use_FPO_info)( &ip, &sp, &fp, fp_min, fp_max ) ) { - if (0 == ip || 1 == ip) break; - if (sps) sps[i] = sp; - if (fps) fps[i] = fp; - ips[i++] = ip; + if ( VG_(use_FPO_info)( &uregs.xip, &uregs.xsp, &uregs.xbp, + fp_min, fp_max ) ) { + if (0 == uregs.xip || 1 == uregs.xip) break; + if (sps) sps[i] = uregs.xsp; + if (fps) fps[i] = uregs.xbp; + ips[i++] = uregs.xip; if (debug) VG_(printf)(" ipsC[%d]=0x%08lx\n", i-1, ips[i-1]); - ip = ip - 1; + uregs.xip = uregs.xip - 1; continue; } @@ -213,15 +211,74 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, break; } -# elif defined(VGP_amd64_linux) || defined(VGP_amd64_darwin) || defined(VGP_amd64_freebsd) + n_found = i; + return n_found; +} + +#endif + +/* ----------------------- amd64 ------------------------ */ - /*--------------------- amd64 ---------------------*/ +#if defined(VGP_amd64_linux) || defined(VGP_amd64_darwin) || defined(VGP_amd64_freebsd) + +UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, + /*OUT*/Addr* ips, UInt max_n_ips, + /*OUT*/Addr* sps, /*OUT*/Addr* fps, + UnwindStartRegs* startRegs, + Addr fp_max_orig ) +{ + Bool debug = False; + Int i; + Addr fp_max; + UInt n_found = 0; + + vg_assert(sizeof(Addr) == sizeof(UWord)); + vg_assert(sizeof(Addr) == sizeof(void*)); + + D3UnwindRegs uregs; + uregs.xip = startRegs->r_pc; + uregs.xsp = startRegs->r_sp; + uregs.xbp = startRegs->misc.AMD64.r_rbp; + Addr fp_min = uregs.xsp; + + /* Snaffle IPs from the client's stack into ips[0 .. max_n_ips-1], + stopping when the trail goes cold, which we guess to be + when FP is not a reasonable stack location. */ + + // JRS 2002-sep-17: hack, to round up fp_max to the end of the + // current page, at least. Dunno if it helps. + // NJN 2002-sep-17: seems to -- stack traces look like 1.0.X again + fp_max = VG_PGROUNDUP(fp_max_orig); + if (fp_max >= sizeof(Addr)) + fp_max -= sizeof(Addr); + + if (debug) + VG_(printf)("max_n_ips=%d fp_min=0x%lx fp_max_orig=0x%lx, " + "fp_max=0x%lx ip=0x%lx fp=0x%lx\n", + max_n_ips, fp_min, fp_max_orig, fp_max, + uregs.xip, uregs.xbp); + + /* Assertion broken before main() is reached in pthreaded programs; the + * offending stack traces only have one item. --njn, 2002-aug-16 */ + /* vg_assert(fp_min <= fp_max);*/ + // On Darwin, this kicks in for pthread-related stack traces, so they're + // only 1 entry long which is wrong. +# if !defined(VGO_darwin) + if (fp_min + 256 >= fp_max) { + /* If the stack limits look bogus, don't poke around ... but + don't bomb out either. */ + if (sps) sps[0] = uregs.xsp; + if (fps) fps[0] = uregs.xbp; + ips[0] = uregs.xip; + return 1; + } +# endif /* fp is %rbp. sp is %rsp. ip is %rip. */ - ips[0] = ip; - if (sps) sps[0] = sp; - if (fps) fps[0] = fp; + ips[0] = uregs.xip; + if (sps) sps[0] = uregs.xsp; + if (fps) fps[0] = uregs.xbp; i = 1; /* Loop unwinding the stack. Note that the IP value we get on @@ -248,14 +305,14 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, /* First off, see if there is any CFI info to hand which can be used. */ - if ( VG_(use_CF_info)( &ip, &sp, &fp, fp_min, fp_max ) ) { - if (0 == ip || 1 == ip) break; - if (sps) sps[i] = sp; - if (fps) fps[i] = fp; - ips[i++] = ip - 1; /* -1: refer to calling insn, not the RA */ + if ( VG_(use_CF_info)( &uregs, fp_min, fp_max ) ) { + if (0 == uregs.xip || 1 == uregs.xip) break; + if (sps) sps[i] = uregs.xsp; + if (fps) fps[i] = uregs.xbp; + ips[i++] = uregs.xip - 1; /* -1: refer to calling insn, not the RA */ if (debug) VG_(printf)(" ipsC[%d]=%#08lx\n", i-1, ips[i-1]); - ip = ip - 1; /* as per comment at the head of this loop */ + uregs.xip = uregs.xip - 1; /* as per comment at the head of this loop */ continue; } @@ -271,19 +328,19 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, fact that we are prodding at & ((UWord*)fp)[1] and so need to adjust the limit check accordingly. Omitting this has been observed to cause segfaults on rare occasions. */ - if (fp_min <= fp && fp <= fp_max - 1 * sizeof(UWord)) { + if (fp_min <= uregs.xbp && uregs.xbp <= fp_max - 1 * sizeof(UWord)) { /* fp looks sane, so use it. */ - ip = (((UWord*)fp)[1]); - if (0 == ip || 1 == ip) break; - sp = fp + sizeof(Addr) /*saved %rbp*/ - + sizeof(Addr) /*ra*/; - fp = (((UWord*)fp)[0]); - if (sps) sps[i] = sp; - if (fps) fps[i] = fp; - ips[i++] = ip - 1; /* -1: refer to calling insn, not the RA */ + uregs.xip = (((UWord*)uregs.xbp)[1]); + if (0 == uregs.xip || 1 == uregs.xip) break; + uregs.xsp = uregs.xbp + sizeof(Addr) /*saved %rbp*/ + + sizeof(Addr) /*ra*/; + uregs.xbp = (((UWord*)uregs.xbp)[0]); + if (sps) sps[i] = uregs.xsp; + if (fps) fps[i] = uregs.xbp; + ips[i++] = uregs.xip - 1; /* -1: refer to calling insn, not the RA */ if (debug) VG_(printf)(" ipsF[%d]=%#08lx\n", i-1, ips[i-1]); - ip = ip - 1; /* as per comment at the head of this loop */ + uregs.xip = uregs.xip - 1; /* as per comment at the head of this loop */ continue; } @@ -299,19 +356,20 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, address; instead scan a likely section of stack (eg sp .. sp+256) and use suitable values found there. */ - if (fp_min <= sp && sp < fp_max) { - ip = ((UWord*)sp)[0]; - if (0 == ip || 1 == ip) break; - if (sps) sps[i] = sp; - if (fps) fps[i] = fp; - ips[i++] = ip == 0 + if (fp_min <= uregs.xsp && uregs.xsp < fp_max) { + uregs.xip = ((UWord*)uregs.xsp)[0]; + if (0 == uregs.xip || 1 == uregs.xip) break; + if (sps) sps[i] = uregs.xsp; + if (fps) fps[i] = uregs.xbp; + ips[i++] = uregs.xip == 0 ? 0 /* sp[0] == 0 ==> stuck at the bottom of a thread stack */ - : ip - 1; /* -1: refer to calling insn, not the RA */ + : uregs.xip - 1; + /* -1: refer to calling insn, not the RA */ if (debug) VG_(printf)(" ipsH[%d]=%#08lx\n", i-1, ips[i-1]); - ip = ip - 1; /* as per comment at the head of this loop */ - sp += 8; + uregs.xip = uregs.xip - 1; /* as per comment at the head of this loop */ + uregs.xsp += 8; continue; } @@ -319,10 +377,74 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, break; } -# elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5) + n_found = i; + return n_found; +} + +#endif + +/* -----------------------ppc32/64 ---------------------- */ + +#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ + || defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5) + +UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, + /*OUT*/Addr* ips, UInt max_n_ips, + /*OUT*/Addr* sps, /*OUT*/Addr* fps, + UnwindStartRegs* startRegs, + Addr fp_max_orig ) +{ + Bool lr_is_first_RA = False; +# if defined(VG_PLAT_USES_PPCTOC) + Word redir_stack_size = 0; + Word redirs_used = 0; +# endif + + Bool debug = False; + Int i; + Addr fp_max; + UInt n_found = 0; + + vg_assert(sizeof(Addr) == sizeof(UWord)); + vg_assert(sizeof(Addr) == sizeof(void*)); + + Addr ip = (Addr)startRegs->r_pc; + Addr sp = (Addr)startRegs->r_sp; + Addr fp = sp; +# if defined(VGP_ppc32_linux) || defined(VGP_ppc32_aix5) + Addr lr = startRegs->misc.PPC32.r_lr; +# elif defined(VGP_ppc64_linux) || defined(VGP_ppc64_aix5) + Addr lr = startRegs->misc.PPC64.r_lr; +# endif + Addr fp_min = sp; + + /* Snaffle IPs from the client's stack into ips[0 .. max_n_ips-1], + stopping when the trail goes cold, which we guess to be + when FP is not a reasonable stack location. */ + + // JRS 2002-sep-17: hack, to round up fp_max to the end of the + // current page, at least. Dunno if it helps. + // NJN 2002-sep-17: seems to -- stack traces look like 1.0.X again + fp_max = VG_PGROUNDUP(fp_max_orig); + if (fp_max >= sizeof(Addr)) + fp_max -= sizeof(Addr); - /*--------------------- ppc32/64 ---------------------*/ + if (debug) + VG_(printf)("max_n_ips=%d fp_min=0x%lx fp_max_orig=0x%lx, " + "fp_max=0x%lx ip=0x%lx fp=0x%lx\n", + max_n_ips, fp_min, fp_max_orig, fp_max, ip, fp); + + /* Assertion broken before main() is reached in pthreaded programs; the + * offending stack traces only have one item. --njn, 2002-aug-16 */ + /* vg_assert(fp_min <= fp_max);*/ + if (fp_min + 512 >= fp_max) { + /* If the stack limits look bogus, don't poke around ... but + don't bomb out either. */ + if (sps) sps[0] = sp; + if (fps) fps[0] = fp; + ips[0] = ip; + return 1; + } /* fp is %r1. ip is %cia. Note, ppc uses r1 as both the stack and frame pointers. */ @@ -386,8 +508,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, /* On ppc64-linux (ppc64-elf, really), and on AIX, the lr save slot is 2 words back from sp, whereas on ppc32-elf(?) it's only one word back. */ -# if defined(VGP_ppc64_linux) \ - || defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5) +# if defined(VG_PLAT_USES_PPCTOC) const Int lr_offset = 2; # else const Int lr_offset = 1; @@ -430,9 +551,9 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, # endif if (0 == ip || 1 == ip) break; - fp = (((UWord*)fp)[0]); if (sps) sps[i] = fp; /* NB. not sp */ if (fps) fps[i] = fp; + fp = (((UWord*)fp)[0]); ips[i++] = ip - 1; /* -1: refer to calling insn, not the RA */ if (debug) VG_(printf)(" ipsF[%d]=%#08lx\n", i-1, ips[i-1]); @@ -447,25 +568,129 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, } } -# else -# error "Unknown platform" -# endif + n_found = i; + return n_found; +} + +#endif + +/* ------------------------ arm ------------------------- */ + +#if defined(VGP_arm_linux) + +UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, + /*OUT*/Addr* ips, UInt max_n_ips, + /*OUT*/Addr* sps, /*OUT*/Addr* fps, + UnwindStartRegs* startRegs, + Addr fp_max_orig ) +{ + Bool debug = False; + Int i; + Addr fp_max; + UInt n_found = 0; + + vg_assert(sizeof(Addr) == sizeof(UWord)); + vg_assert(sizeof(Addr) == sizeof(void*)); + + D3UnwindRegs uregs; + uregs.r15 = startRegs->r_pc & 0xFFFFFFFE; + uregs.r14 = startRegs->misc.ARM.r14; + uregs.r13 = startRegs->r_sp; + uregs.r12 = startRegs->misc.ARM.r12; + uregs.r11 = startRegs->misc.ARM.r11; + uregs.r7 = startRegs->misc.ARM.r7; + Addr fp_min = uregs.r13; + + /* Snaffle IPs from the client's stack into ips[0 .. max_n_ips-1], + stopping when the trail goes cold, which we guess to be + when FP is not a reasonable stack location. */ + + // JRS 2002-sep-17: hack, to round up fp_max to the end of the + // current page, at least. Dunno if it helps. + // NJN 2002-sep-17: seems to -- stack traces look like 1.0.X again + fp_max = VG_PGROUNDUP(fp_max_orig); + if (fp_max >= sizeof(Addr)) + fp_max -= sizeof(Addr); + + if (debug) + VG_(printf)("\nmax_n_ips=%d fp_min=0x%lx fp_max_orig=0x%lx, " + "fp_max=0x%lx r15=0x%lx r13=0x%lx\n", + max_n_ips, fp_min, fp_max_orig, fp_max, + uregs.r15, uregs.r13); + + /* Assertion broken before main() is reached in pthreaded programs; the + * offending stack traces only have one item. --njn, 2002-aug-16 */ + /* vg_assert(fp_min <= fp_max);*/ + // On Darwin, this kicks in for pthread-related stack traces, so they're + // only 1 entry long which is wrong. + if (fp_min + 512 >= fp_max) { + /* If the stack limits look bogus, don't poke around ... but + don't bomb out either. */ + if (sps) sps[0] = uregs.r13; + if (fps) fps[0] = 0; + ips[0] = uregs.r15; + return 1; + } + + /* */ + + if (sps) sps[0] = uregs.r13; + if (fps) fps[0] = 0; + ips[0] = uregs.r15; + i = 1; + + /* Loop unwinding the stack. */ + + while (True) { + if (debug) { + VG_(printf)("i: %d, r15: 0x%lx, r13: 0x%lx\n", + i, uregs.r15, uregs.r13); + } + + if (i >= max_n_ips) + break; + + if (VG_(use_CF_info)( &uregs, fp_min, fp_max )) { + if (sps) sps[i] = uregs.r13; + if (fps) fps[i] = 0; + ips[i++] = (uregs.r15 & 0xFFFFFFFE) - 1; + if (debug) + VG_(printf)("USING CFI: r15: 0x%lx, r13: 0x%lx\n", + uregs.r15, uregs.r13); + uregs.r15 = (uregs.r15 & 0xFFFFFFFE) - 1; + continue; + } + /* No luck. We have to give up. */ + break; + } n_found = i; return n_found; } +#endif + +/*------------------------------------------------------------*/ +/*--- ---*/ +/*--- END platform-dependent unwinder worker functions ---*/ +/*--- ---*/ +/*------------------------------------------------------------*/ + +/*------------------------------------------------------------*/ +/*--- Exported functions. ---*/ +/*------------------------------------------------------------*/ + UInt VG_(get_StackTrace) ( ThreadId tid, /*OUT*/StackTrace ips, UInt max_n_ips, /*OUT*/StackTrace sps, /*OUT*/StackTrace fps, Word first_ip_delta ) { - /* thread in thread table */ - Addr ip = VG_(get_IP)(tid); - Addr fp = VG_(get_FP)(tid); - Addr sp = VG_(get_SP)(tid); - Addr lr = VG_(get_LR)(tid); + /* Get the register values with which to start the unwind. */ + UnwindStartRegs startRegs; + VG_(memset)( &startRegs, 0, sizeof(startRegs) ); + VG_(get_UnwindStartRegs)( &startRegs, tid ); + Addr stack_highest_word = VG_(threads)[tid].client_stack_highest_word; Addr stack_lowest_word = 0; @@ -488,29 +713,31 @@ UInt VG_(get_StackTrace) ( ThreadId tid, bothered. */ if (VG_(client__dl_sysinfo_int80) != 0 /* we know its address */ - && ip >= VG_(client__dl_sysinfo_int80) - && ip < VG_(client__dl_sysinfo_int80)+3 - && VG_(am_is_valid_for_client)(sp, sizeof(Addr), VKI_PROT_READ)) { - ip = *(Addr *)sp; - sp += sizeof(Addr); + && startRegs.r_pc >= VG_(client__dl_sysinfo_int80) + && startRegs.r_pc < VG_(client__dl_sysinfo_int80)+3 + && VG_(am_is_valid_for_client)(startRegs.r_pc, sizeof(Addr), + VKI_PROT_READ)) { + startRegs.r_pc = (ULong) *(Addr*)(UWord)startRegs.r_sp; + startRegs.r_sp += (ULong) sizeof(Addr); } # endif /* See if we can get a better idea of the stack limits */ - VG_(stack_limits)(sp, &stack_lowest_word, &stack_highest_word); + VG_(stack_limits)( (Addr)startRegs.r_sp, + &stack_lowest_word, &stack_highest_word ); /* Take into account the first_ip_delta. */ - vg_assert( sizeof(Addr) == sizeof(Word) ); - ip += first_ip_delta; + startRegs.r_pc += (Long)(Word)first_ip_delta; if (0) - VG_(printf)("tid %d: stack_highest=0x%08lx ip=0x%08lx " - "sp=0x%08lx fp=0x%08lx\n", - tid, stack_highest_word, ip, sp, fp); + VG_(printf)("tid %d: stack_highest=0x%08lx ip=0x%010llx " + "sp=0x%010llx\n", + tid, stack_highest_word, + startRegs.r_pc, startRegs.r_sp); return VG_(get_StackTrace_wrk)(tid, ips, max_n_ips, sps, fps, - ip, sp, fp, lr, sp, + &startRegs, stack_highest_word); } diff --git a/coregrind/m_start-amd64-darwin.S b/coregrind/m_start-amd64-darwin.S deleted file mode 100644 index edd9613..0000000 --- a/coregrind/m_start-amd64-darwin.S +++ /dev/null @@ -1,88 +0,0 @@ - -/*--------------------------------------------------------------------*/ -/*--- Darwin amd64 bootstrap. m_start-amd64-darwin.S ---*/ -/*--------------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright (C) 2007 Apple Inc. - Greg Parker gparker@apple.com - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - -#if defined(VGP_amd64_darwin) - -#include "pub_core_basics_asm.h" - - .text - .align 3,0x90 -Ldyld_stub_binding_helper: - pushq %r11 - leaq ___dso_handle(%rip), %r11 - pushq %r11 - jmpq *Ldyld_lazy_symbol_binding_entry_point(%rip) - - .dyld - .align 3 -Ldyld_lazy_symbol_binding_entry_point: - .quad 0 - .quad 0 - .quad 0 - .quad 0 - .quad 0 - .quad Ldyld_stub_binding_helper - .quad 0 - - - // Memory layout established by kernel: - // - // 0 - // executable_name - // 0 - // envp[n] - // ... - // envp[0] - // 0 - // argv[argc-1] - // ... - // sp+8-> argv[0] - // sp -> argc - - .text - .align 3,0x90 - .globl __start -__start: - movq %rsp, %rdi // save &argc - andq $-16, %rsp // align stack - pushq $0 // push NULL "return address" for backtraces - pushq $0 // push fake saved ebp and align stack - movq %rsp, %rbp // save frame pointer - call __start_in_C_darwin // __start_in_C_darwin(&argc) - - // should not reach here - int $3 - int $3 - -#endif // defined(VGP_amd64_darwin) - -/*--------------------------------------------------------------------*/ -/*--- end ---*/ -/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_start-x86-darwin.S b/coregrind/m_start-x86-darwin.S deleted file mode 100644 index 10e7e13..0000000 --- a/coregrind/m_start-x86-darwin.S +++ /dev/null @@ -1,88 +0,0 @@ - -/*--------------------------------------------------------------------*/ -/*--- Darwin x86 bootstrap. m_start-x86-darwin.S ---*/ -/*--------------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright (C) 2007 Apple Inc. - Greg Parker gparker@apple.com - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - -#if defined(VGP_x86_darwin) - -#include "pub_core_basics_asm.h" - - .text - .align 2,0x90 -Ldyld_stub_binding_helper: - pushl $__mh_execute_header - jmpl *Ldyld_lazy_symbol_binding_entry_point - - .dyld - .align 2 -Ldyld_lazy_symbol_binding_entry_point: - .long 0 - .long 0 - .long 0 - .long 0 - .long 0 - .long Ldyld_stub_binding_helper - .long 0 - - - // Memory layout established by kernel: - // - // 0 - // executable_name - // 0 - // envp[n] - // ... - // envp[0] - // 0 - // argv[argc-1] - // ... - // sp+4-> argv[0] - // sp -> argc - - .text - .align 2,0x90 - .globl __start -__start: - movl %esp, %eax // save &argc - andl $-16, %esp // align stack - pushl $0 // push NULL "return address" for backtraces - pushl $0 // push fake saved ebp - movl %esp, %ebp // save frame pointer - pushl $0 // align stack - pushl %eax // start_in_C_darwin(&argc) - call __start_in_C_darwin - - // should not reach here - int $3 - int $3 - -#endif // defined(VGP_x86_darwin) - -/*--------------------------------------------------------------------*/ -/*--- end ---*/ -/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_syscall.c b/coregrind/m_syscall.c index a047419..3b7a60e 100644 --- a/coregrind/m_syscall.c +++ b/coregrind/m_syscall.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -100,6 +100,17 @@ SysRes VG_(mk_SysRes_ppc64_linux) ( ULong val, ULong cr0so ) { return res; } +SysRes VG_(mk_SysRes_arm_linux) ( Int val ) { + SysRes res; + res._isError = val >= -4095 && val <= -1; + if (res._isError) { + res._val = (UInt)(-val); + } else { + res._val = (UInt)val; + } + return res; +} + /* Generic constructors. */ SysRes VG_(mk_SysRes_Error) ( UWord err ) { SysRes r; @@ -460,6 +471,31 @@ asm( " ret\n" ".previous\n" ); +#elif defined(VGP_arm_linux) +/* I think the conventions are: + args in r0 r1 r2 r3 r4 r5 + sysno in r7 + return value in r0, w/ same conventions as x86-linux, viz r0 in + -4096 .. -1 is an error value. All other values are success + values. +*/ +extern UWord do_syscall_WRK ( + UWord a1, UWord a2, UWord a3, + UWord a4, UWord a5, UWord a6, + UWord syscall_no + ); +asm( +".text\n" +"do_syscall_WRK:\n" +" push {r4, r5, r7}\n" +" ldr r4, [sp, #12]\n" +" ldr r5, [sp, #16]\n" +" ldr r7, [sp, #20]\n" +" svc 0x0\n" +" pop {r4, r5, r7}\n" +" bx lr\n" +".previous\n" +); #elif defined(VGP_amd64_freebsd) extern UWord do_syscall_WRK ( @@ -846,6 +882,10 @@ SysRes VG_(do_syscall) ( UWord sysno, UWord a1, UWord a2, UWord a3, do_syscall_WRK( &argblock[0] ); return VG_(mk_SysRes_ppc64_linux)( argblock[0], argblock[1] ); +# elif defined(VGP_arm_linux) + UWord val = do_syscall_WRK(a1,a2,a3,a4,a5,a6,sysno); + return VG_(mk_SysRes_arm_linux)( val ); + # elif defined(VGP_ppc32_aix5) UWord res; UWord err; diff --git a/coregrind/m_syswrap/priv_syswrap-aix5.h b/coregrind/m_syswrap/priv_syswrap-aix5.h index 4e56095..037b8fa 100644 --- a/coregrind/m_syswrap/priv_syswrap-aix5.h +++ b/coregrind/m_syswrap/priv_syswrap-aix5.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/priv_syswrap-darwin.h b/coregrind/m_syswrap/priv_syswrap-darwin.h index 776f5e0..ec99d8b 100644 --- a/coregrind/m_syswrap/priv_syswrap-darwin.h +++ b/coregrind/m_syswrap/priv_syswrap-darwin.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Apple Inc. + Copyright (C) 2005-2010 Apple Inc. Greg Parker gparker@apple.com This program is free software; you can redistribute it and/or @@ -295,8 +295,8 @@ DECL_TEMPLATE(darwin, getxattr); // 234 DECL_TEMPLATE(darwin, fgetxattr); // 235 DECL_TEMPLATE(darwin, setxattr); // 236 DECL_TEMPLATE(darwin, fsetxattr); // 237 -// NYI removexattr 238 -// NYI fremovexattr 239 +DECL_TEMPLATE(darwin, removexattr); // 238 +DECL_TEMPLATE(darwin, fremovexattr); // 239 DECL_TEMPLATE(darwin, listxattr); // 240 DECL_TEMPLATE(darwin, flistxattr); // 241 DECL_TEMPLATE(darwin, fsctl); // 242 @@ -334,7 +334,7 @@ DECL_TEMPLATE(darwin, sem_post); // 273 // NYI sem_getvalue 274 DECL_TEMPLATE(darwin, sem_init); // 275 DECL_TEMPLATE(darwin, sem_destroy); // 276 -// NYI open_extended 277 +DECL_TEMPLATE(darwin, open_extended) // 277 // NYI umask_extended 278 DECL_TEMPLATE(darwin, stat_extended); // 279 DECL_TEMPLATE(darwin, lstat_extended); // 280 @@ -393,7 +393,9 @@ DECL_TEMPLATE(darwin, __pthread_markcancel); // 332 DECL_TEMPLATE(darwin, __pthread_canceled); // 333 DECL_TEMPLATE(darwin, __semwait_signal); // 334 // old utrace -// NYI proc_info 336 +#if DARWIN_VERS >= DARWIN_10_6 +DECL_TEMPLATE(darwin, proc_info); // 336 +#endif DECL_TEMPLATE(darwin, sendfile); // 337 DECL_TEMPLATE(darwin, stat64); // 338 DECL_TEMPLATE(darwin, fstat64); // 339 @@ -429,7 +431,7 @@ DECL_TEMPLATE(darwin, workq_ops); // 368 // 369 // 370 // 371 -// 372 +DECL_TEMPLATE(darwin, __thread_selfid); // 372 // 373 // 374 // 375 @@ -484,6 +486,9 @@ DECL_TEMPLATE(darwin, __mac_syscall); // 381 // NYI __mac_mount 424 // NYI __mac_get_mount 425 // NYI __mac_getfsstat 426 +DECL_TEMPLATE(darwin, fsgetpath); // 427 +DECL_TEMPLATE(darwin, audit_session_self); // 428 +// NYI audit_session_join 429 // Mach message helpers DECL_TEMPLATE(darwin, host_info); @@ -498,9 +503,11 @@ DECL_TEMPLATE(darwin, mach_port_deallocate); DECL_TEMPLATE(darwin, mach_port_get_refs); DECL_TEMPLATE(darwin, mach_port_mod_refs); DECL_TEMPLATE(darwin, mach_port_get_set_status); +DECL_TEMPLATE(darwin, mach_port_move_member); DECL_TEMPLATE(darwin, mach_port_destroy); DECL_TEMPLATE(darwin, mach_port_request_notification); DECL_TEMPLATE(darwin, mach_port_insert_right); +DECL_TEMPLATE(darwin, mach_port_extract_right); DECL_TEMPLATE(darwin, mach_port_get_attributes); DECL_TEMPLATE(darwin, mach_port_set_attributes); DECL_TEMPLATE(darwin, mach_port_insert_member); @@ -537,6 +544,7 @@ DECL_TEMPLATE(darwin, thread_create_running); DECL_TEMPLATE(darwin, thread_suspend); DECL_TEMPLATE(darwin, thread_get_state); DECL_TEMPLATE(darwin, thread_policy); +DECL_TEMPLATE(darwin, thread_policy_set); DECL_TEMPLATE(darwin, thread_info); DECL_TEMPLATE(darwin, bootstrap_register); DECL_TEMPLATE(darwin, bootstrap_look_up); diff --git a/coregrind/m_syswrap/priv_syswrap-generic.h b/coregrind/m_syswrap/priv_syswrap-generic.h index 0d94a63..8174718 100644 --- a/coregrind/m_syswrap/priv_syswrap-generic.h +++ b/coregrind/m_syswrap/priv_syswrap-generic.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -268,23 +268,23 @@ extern void ML_(generic_POST_sys_shmctl) ( TId, UW, UW, UW, UW ); extern SysRes ML_(generic_PRE_sys_mmap) ( TId, UW, UW, UW, UW, UW, Off64T ); -#define PRE_timeval_READ(zzname, zzarg) \ - do { \ - struct vki_timeval *zztv = (struct vki_timeval *)zzarg; \ - PRE_FIELD_READ(zzname, zztv->tv_sec); \ - PRE_FIELD_READ(zzname, zztv->tv_usec); \ +#define PRE_timeval_READ(zzname, zzarg) \ + do { \ + struct vki_timeval *zztv = (struct vki_timeval *)(zzarg); \ + PRE_FIELD_READ(zzname, zztv->tv_sec); \ + PRE_FIELD_READ(zzname, zztv->tv_usec); \ } while (0) -#define PRE_timeval_WRITE(zzname, zzarg) \ - do { \ - struct vki_timeval *zztv = (struct vki_timeval *)zzarg; \ - PRE_FIELD_WRITE(zzname, zztv->tv_sec); \ - PRE_FIELD_WRITE(zzname, zztv->tv_usec); \ +#define PRE_timeval_WRITE(zzname, zzarg) \ + do { \ + struct vki_timeval *zztv = (struct vki_timeval *)(zzarg); \ + PRE_FIELD_WRITE(zzname, zztv->tv_sec); \ + PRE_FIELD_WRITE(zzname, zztv->tv_usec); \ } while (0) -#define POST_timeval_WRITE(zzarg) \ - do { \ - struct vki_timeval *zztv = (struct vki_timeval *)zzarg; \ - POST_FIELD_WRITE(zztv->tv_sec); \ - POST_FIELD_WRITE(zztv->tv_usec); \ +#define POST_timeval_WRITE(zzarg) \ + do { \ + struct vki_timeval *zztv = (struct vki_timeval *)(zzarg); \ + POST_FIELD_WRITE(zztv->tv_sec); \ + POST_FIELD_WRITE(zztv->tv_usec); \ } while (0) diff --git a/coregrind/m_syswrap/priv_syswrap-linux-variants.h b/coregrind/m_syswrap/priv_syswrap-linux-variants.h index 3c16000..413c130 100644 --- a/coregrind/m_syswrap/priv_syswrap-linux-variants.h +++ b/coregrind/m_syswrap/priv_syswrap-linux-variants.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/priv_syswrap-linux.h b/coregrind/m_syswrap/priv_syswrap-linux.h index fed3ba6..e2a21d6 100644 --- a/coregrind/m_syswrap/priv_syswrap-linux.h +++ b/coregrind/m_syswrap/priv_syswrap-linux.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -47,6 +47,13 @@ extern SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, DECL_TEMPLATE(linux, sys_mount); DECL_TEMPLATE(linux, sys_oldumount); DECL_TEMPLATE(linux, sys_umount); +DECL_TEMPLATE(linux, sys_perf_counter_open); +DECL_TEMPLATE(linux, sys_preadv); +DECL_TEMPLATE(linux, sys_pwritev); +DECL_TEMPLATE(linux, sys_dup3); +DECL_TEMPLATE(linux, sys_getcpu); +DECL_TEMPLATE(linux, sys_splice); +DECL_TEMPLATE(linux, sys_readahead); // POSIX, but various sub-cases differ between Linux and Darwin. DECL_TEMPLATE(linux, sys_fcntl); @@ -116,6 +123,7 @@ DECL_TEMPLATE(linux, sys_set_mempolicy); DECL_TEMPLATE(linux, sys_get_mempolicy); DECL_TEMPLATE(linux, sys_inotify_init); +DECL_TEMPLATE(linux, sys_inotify_init1); DECL_TEMPLATE(linux, sys_inotify_add_watch); DECL_TEMPLATE(linux, sys_inotify_rm_watch); @@ -209,7 +217,7 @@ DECL_TEMPLATE(linux, sys_sched_getscheduler); DECL_TEMPLATE(linux, sys_sched_yield); DECL_TEMPLATE(linux, sys_sched_get_priority_max); DECL_TEMPLATE(linux, sys_sched_get_priority_min); -//DECL_TEMPLATE(linux, sys_sched_rr_get_interval); // not yet encountered +DECL_TEMPLATE(linux, sys_sched_rr_get_interval); DECL_TEMPLATE(linux, sys_sched_setaffinity); DECL_TEMPLATE(linux, sys_sched_getaffinity); @@ -237,10 +245,12 @@ DECL_TEMPLATE(linux, sys_rt_sigprocmask); DECL_TEMPLATE(linux, sys_rt_sigpending); DECL_TEMPLATE(linux, sys_rt_sigtimedwait); DECL_TEMPLATE(linux, sys_rt_sigqueueinfo); +DECL_TEMPLATE(linux, sys_rt_tgsigqueueinfo); DECL_TEMPLATE(linux, sys_rt_sigsuspend); // Linux-specific? DECL_TEMPLATE(linux, sys_sync_file_range); +DECL_TEMPLATE(linux, sys_sync_file_range2); DECL_TEMPLATE(linux, sys_stime); /* maybe generic? I'm not sure */ // Linux specific (kernel modules) diff --git a/coregrind/m_syswrap/priv_syswrap-main.h b/coregrind/m_syswrap/priv_syswrap-main.h index e4b87b3..62784de 100644 --- a/coregrind/m_syswrap/priv_syswrap-main.h +++ b/coregrind/m_syswrap/priv_syswrap-main.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/priv_types_n_macros.h b/coregrind/m_syswrap/priv_types_n_macros.h index fe0a8c4..3ae953a 100644 --- a/coregrind/m_syswrap/priv_types_n_macros.h +++ b/coregrind/m_syswrap/priv_types_n_macros.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -84,12 +84,13 @@ typedef // Note that, depending on the platform, arguments may be found in // registers or on the stack. (See the comment at the top of // syswrap-main.c for per-platform details.) For register arguments - // (which have o_arg field names) the o_arg value is the offset from + // (which have o_arg field names) the o_arg value is the offset into // the vex register state. For stack arguments (which have s_arg // field names), the s_arg value is the offset from the stack pointer. Int o_sysno; # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \ - || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) + || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ + || defined(VGP_arm_linux) Int o_arg1; Int o_arg2; Int o_arg3; @@ -189,20 +190,19 @@ typedef */ -#if defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) -/* On Linux, finding the wrapper is easy: just look up in fixed, - platform-specific tables. These are defined in the relevant - platform-specific files -- syswrap-arch-os.c */ - -extern const SyscallTableEntry ML_(syscall_table)[]; - -extern const UInt ML_(syscall_table_size); +/* A function to find the syscall table entry for a given sysno. If + none is found, return NULL. This used to be done with a single + fixed sized table exposed to the caller, but that's too inflexible; + hence now use a function which can do arbitrary messing around to + find the required entry. */ +#if defined(VGO_linux) +extern +SyscallTableEntry* ML_(get_linux_syscall_entry)( UInt sysno ); #elif defined(VGP_ppc32_aix5) -/* On AIX5 this is more complex than the simple fixed table lookup on - Linux, since the syscalls don't have fixed numbers. So it's - simplest to use a function, which does all the required messing - around. */ +/* Same scheme on AIX5. This is more complex than the simple fixed + table lookup typical for Linux, since the syscalls don't have fixed + numbers. */ extern SyscallTableEntry* ML_(get_ppc32_aix5_syscall_entry) ( UInt sysno ); @@ -210,6 +210,14 @@ SyscallTableEntry* ML_(get_ppc32_aix5_syscall_entry) ( UInt sysno ); extern SyscallTableEntry* ML_(get_ppc64_aix5_syscall_entry) ( UInt sysno ); +#elif defined(VGO_darwin) || defined(VGO_freebsd) +/* XXX: Darwin still uses the old scheme of exposing the table + array(s) and size(s) directly to syswrap-main.c. This should be + fixed. */ + +extern const SyscallTableEntry ML_(syscall_table)[]; +extern const UInt ML_(syscall_table_size); + #else # error Unknown OS #endif diff --git a/coregrind/m_syswrap/syscall-amd64-linux.S b/coregrind/m_syswrap/syscall-amd64-linux.S index 3e7c697..4c9b64e 100644 --- a/coregrind/m_syswrap/syscall-amd64-linux.S +++ b/coregrind/m_syswrap/syscall-amd64-linux.S @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/syscall-arm-linux.S b/coregrind/m_syswrap/syscall-arm-linux.S new file mode 100644 index 0000000..327d442 --- /dev/null +++ b/coregrind/m_syswrap/syscall-arm-linux.S @@ -0,0 +1,153 @@ + +/*--------------------------------------------------------------------*/ +/*--- Support for doing system calls. syscall-arm-linux.S ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2008-2010 Evan Geller (gaze@bea.ms) + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#if defined(VGP_arm_linux) + +#include "pub_core_basics_asm.h" +#include "pub_core_vkiscnums_asm.h" +#include "libvex_guest_offsets.h" + + +/*----------------------------------------------------------------*/ +/* + Perform a syscall for the client. This will run a syscall + with the client's specific per-thread signal mask. + + The structure of this function is such that, if the syscall is + interrupted by a signal, we can determine exactly what + execution state we were in with respect to the execution of + the syscall by examining the value of IP in the signal + handler. This means that we can always do the appropriate + thing to precisely emulate the kernel's signal/syscall + interactions. + + The syscall number is taken from the argument, even though it + should also be in regs->m_R7. The syscall result is written + back to regs->m_R0 on completion. + + Returns 0 if the syscall was successfully called (even if the + syscall itself failed), or a nonzero error code in the lowest + 8 bits if one of the sigprocmasks failed (there's no way to + determine which one failed). And there's no obvious way to + recover from that either, but nevertheless we want to know. + + VG_(fixup_guest_state_after_syscall_interrupted) does the + thread state fixup in the case where we were interrupted by a + signal. + + Prototype: + + UWord ML_(do_syscall_for_client_WRK)( + Int syscallno, // r0 + void* guest_state, // r1 + const vki_sigset_t *sysmask, // r2 + const vki_sigset_t *postmask, // r3 + Int nsigwords) // [sp, #0] +*/ +/* from vki_arch.h */ +#define VKI_SIG_SETMASK 2 + +.globl ML_(do_syscall_for_client_WRK) +ML_(do_syscall_for_client_WRK): + + /* Stash callee-saves and our args on the stack */ + push {r0, r1, r3, r4, r5, r7, fp, lr} + +1: + + mov r7, #__NR_rt_sigprocmask + mov r0, #VKI_SIG_SETMASK + mov r1, r2 /* sysmask */ + mov r2, r3 /* postmask */ + ldr r3, [sp, #32] /* nsigwords */ + svc 0x00000000 + + + ldr r5, [sp, #4] /* guest_state */ + + ldr r7, [sp, #0] /* syscall# */ + ldr r0, [r5, #OFFSET_arm_R0] + ldr r1, [r5, #OFFSET_arm_R1] + ldr r2, [r5, #OFFSET_arm_R2] + ldr r3, [r5, #OFFSET_arm_R3] + ldr r4, [r5, #OFFSET_arm_R4] + ldr r5, [r5, #OFFSET_arm_R5] + +2: svc 0x00000000 +3: + ldr r5, [sp, #4] /* guest_state */ + str r0, [r5, #OFFSET_arm_R0] + +4: + mov r7, #__NR_rt_sigprocmask + mov r0, #VKI_SIG_SETMASK + ldr r1, [sp, #8] /* postmask */ + mov r2, #0 + ldr r3, [sp, #32] /* nsigwords */ + svc 0x00000000 + + cmp r0, #0 + blt 7f + add sp, sp, #4 /* r0 contains return value */ + +5: /* Success */ + mov r0, #0 + pop {r1, r3, r4, r5, r7, fp, pc} + +7: /* Failure: return 0x8000 | error code */ + orr r0, r0, #0x8000 + pop {r1, r3, r4, r5, r7, fp, pc} + + +.section .rodata +/* export the ranges so that + VG_(fixup_guest_state_after_syscall_interrupted) can do the + right thing */ + +.globl ML_(blksys_setup) +.globl ML_(blksys_restart) +.globl ML_(blksys_complete) +.globl ML_(blksys_committed) +.globl ML_(blksys_finished) +ML_(blksys_setup): .long 1b +ML_(blksys_restart): .long 2b +ML_(blksys_complete): .long 3b +ML_(blksys_committed): .long 4b +ML_(blksys_finished): .long 5b + +/* Let the linker know we don't need an executable stack */ +.section .note.GNU-stack,"",%progbits + +.previous + +#endif // defined(VGP_arm_linux) + +/*--------------------------------------------------------------------*/ +/*--- end ---*/ +/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_syswrap/syscall-ppc32-aix5.S b/coregrind/m_syswrap/syscall-ppc32-aix5.S index 7d8d16c..65f7dc3 100644 --- a/coregrind/m_syswrap/syscall-ppc32-aix5.S +++ b/coregrind/m_syswrap/syscall-ppc32-aix5.S @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk Derived from Paul Mackerras' implementation of same for ppc32-linux diff --git a/coregrind/m_syswrap/syscall-ppc32-linux.S b/coregrind/m_syswrap/syscall-ppc32-linux.S index 4a89135..b23eeb0 100644 --- a/coregrind/m_syswrap/syscall-ppc32-linux.S +++ b/coregrind/m_syswrap/syscall-ppc32-linux.S @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Paul Mackerras (paulus@samba.org) + Copyright (C) 2005-2010 Paul Mackerras (paulus@samba.org) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/coregrind/m_syswrap/syscall-ppc64-aix5.S b/coregrind/m_syswrap/syscall-ppc64-aix5.S index ee4ad51..0e6cdc5 100644 --- a/coregrind/m_syswrap/syscall-ppc64-aix5.S +++ b/coregrind/m_syswrap/syscall-ppc64-aix5.S @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk Derived from Paul Mackerras' implementation of same for ppc32-linux diff --git a/coregrind/m_syswrap/syscall-ppc64-linux.S b/coregrind/m_syswrap/syscall-ppc64-linux.S index 4c0fb10..aea8e85 100644 --- a/coregrind/m_syswrap/syscall-ppc64-linux.S +++ b/coregrind/m_syswrap/syscall-ppc64-linux.S @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Paul Mackerras + Copyright (C) 2005-2010 Paul Mackerras This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/coregrind/m_syswrap/syscall-x86-linux.S b/coregrind/m_syswrap/syscall-x86-linux.S index f460199..2361de0 100644 --- a/coregrind/m_syswrap/syscall-x86-linux.S +++ b/coregrind/m_syswrap/syscall-x86-linux.S @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/syswrap-aix5.c b/coregrind/m_syswrap/syswrap-aix5.c index 6108cce..8c45606 100644 --- a/coregrind/m_syswrap/syswrap-aix5.c +++ b/coregrind/m_syswrap/syswrap-aix5.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -798,7 +798,8 @@ static void pre_argv_envp(Addr a, ThreadId tid, Char* s1, Char* s2) a += sizeof(char*); } } -static SysRes simple_pre_exec_check(const HChar* exe_name) +static SysRes simple_pre_exec_check ( const HChar* exe_name, + Bool trace_this_child ) { Int fd, ret; SysRes res; @@ -815,7 +816,7 @@ static SysRes simple_pre_exec_check(const HChar* exe_name) // Check we have execute permissions. We allow setuid executables // to be run only in the case when we are not simulating them, that // is, they to be run natively. - setuid_allowed = VG_(clo_trace_children) ? False : True; + setuid_allowed = trace_this_child ? False : True; ret = VG_(check_executable)(NULL/*&is_setuid*/, (HChar*)exe_name, setuid_allowed); if (0 != ret) { @@ -833,6 +834,7 @@ PRE(sys_execve) ThreadState* tst; Int i, j, tot_args; SysRes res; + Bool trace_this_child; PRINT("sys_execve ( %#lx(%s), %#lx, %#lx )", ARG1, (Char*)ARG1, ARG2, ARG3); PRE_REG_READ3(vki_off_t, "execve", @@ -862,10 +864,16 @@ PRE(sys_execve) // SET_STATUS_Failure( VKI_EFAULT ); // return; //} + if (ARG1 == 0 /* obviously bogus */) { + SET_STATUS_Failure( VKI_EFAULT ); + } + + // Decide whether or not we want to follow along + trace_this_child = VG_(should_we_trace_this_child)( (HChar*)ARG1 ); // Do the important checks: it is a file, is executable, permissions are // ok, etc. - res = simple_pre_exec_check((const HChar*)ARG1); + res = simple_pre_exec_check( (const HChar*)ARG1, trace_this_child ); if (res.isError) { SET_STATUS_Failure( res.err ); return; @@ -874,7 +882,7 @@ PRE(sys_execve) /* If we're tracing the child, and the launcher name looks bogus (possibly because launcher.c couldn't figure it out, see comments therein) then we have no option but to fail. */ - if (VG_(clo_trace_children) + if (trace_this_child && (VG_(name_of_launcher) == NULL || VG_(name_of_launcher)[0] != '/')) { SET_STATUS_Failure( VKI_ECHILD ); /* "No child processes" */ @@ -892,7 +900,7 @@ PRE(sys_execve) // Set up the child's exe path. // - if (VG_(clo_trace_children)) { + if (trace_this_child) { // We want to exec the launcher. Get its pre-remembered path. path = VG_(name_of_launcher); @@ -930,7 +938,7 @@ PRE(sys_execve) VG_(env_remove_valgrind_env_stuff)( envp ); } - if (VG_(clo_trace_children)) { + if (trace_this_child) { // Set VALGRIND_LIB in ARG3 (the environment) VG_(env_setenv)( &envp, VALGRIND_LIB, VG_(libdir)); } @@ -943,7 +951,7 @@ PRE(sys_execve) // except that the first VG_(args_for_valgrind_noexecpass) args // are omitted. // - if (!VG_(clo_trace_children)) { + if (!trace_this_child) { argv = (Char**)ARG2; } else { vg_assert( VG_(args_for_valgrind_noexecpass) >= 0 ); diff --git a/coregrind/m_syswrap/syswrap-amd64-darwin.c b/coregrind/m_syswrap/syswrap-amd64-darwin.c index 0347db4..1057bb1 100644 --- a/coregrind/m_syswrap/syswrap-amd64-darwin.c +++ b/coregrind/m_syswrap/syswrap-amd64-darwin.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Apple Inc. + Copyright (C) 2005-2010 Apple Inc. Greg Parker gparker@apple.com This program is free software; you can redistribute it and/or @@ -288,6 +288,7 @@ asm( void pthread_hijack(Addr self, Addr kport, Addr func, Addr func_arg, Addr stacksize, Addr flags, Addr sp) { + vki_sigset_t blockall; ThreadState *tst = (ThreadState *)func_arg; VexGuestAMD64State *vex = &tst->arch.vex; @@ -297,6 +298,11 @@ void pthread_hijack(Addr self, Addr kport, Addr func, Addr func_arg, // The parent thread holds V's lock on our behalf. semaphore_wait(tst->os_state.child_go); + /* Start the thread with all signals blocked. VG_(scheduler) will + set the mask correctly when we finally get there. */ + VG_(sigfillset)(&blockall); + VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, NULL); + // Set thread's registers // Do this FIRST because some code below tries to collect a backtrace, // which requires valid register data. @@ -331,12 +337,17 @@ void pthread_hijack(Addr self, Addr kport, Addr func, Addr func_arg, VKI_PROT_READ|VKI_PROT_WRITE, VKI_MAP_PRIVATE, -1, 0); // guard page ML_(notify_core_and_tool_of_mmap)( - stack-VKI_PAGE_SIZE, VKI_PAGE_SIZE, 0, VKI_MAP_PRIVATE, -1, 0); + stack-VKI_PAGE_SIZE, VKI_PAGE_SIZE, + 0, VKI_MAP_PRIVATE, -1, 0); } else { // client allocated stack find_stack_segment(tst->tid, sp); } - VG_(am_do_sync_check)("after", "pthread_hijack", 0); + ML_(sync_mappings)("after", "pthread_hijack", 0); + + // DDD: should this be here rather than in POST(sys_bsdthread_create)? + // But we don't have ptid here... + //VG_TRACK ( pre_thread_ll_create, ptid, tst->tid ); // Tell parent thread's POST(sys_bsdthread_create) that we're done // initializing registers and mapping memory. @@ -363,8 +374,7 @@ asm( ); -/* - wqthread note: The kernel may create or destroy pthreads in the +/* wqthread note: The kernel may create or destroy pthreads in the wqthread pool at any time with no userspace interaction, and wqthread_start may be entered at any time with no userspace interaction. @@ -378,6 +388,22 @@ void wqthread_hijack(Addr self, Addr kport, Addr stackaddr, Addr workitem, VexGuestAMD64State *vex; Addr stack; SizeT stacksize; + vki_sigset_t blockall; + + /* When we enter here we hold no lock (!), so we better acquire it + pronto. Why do we hold no lock? Because (presumably) the only + way to get here is as a result of a SfMayBlock syscall + "workq_ops(WQOPS_THREAD_RETURN)", which will have dropped the + lock. At least that's clear for the 'reuse' case. The + non-reuse case? Dunno, perhaps it's a new thread the kernel + pulled out of a hat. In any case we still need to take a + lock. */ + VG_(acquire_BigLock_LL)("wqthread_hijack"); + + /* Start the thread with all signals blocked. VG_(scheduler) will + set the mask correctly when we finally get there. */ + VG_(sigfillset)(&blockall); + VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, NULL); if (reuse) { // This thread already exists; we're merely re-entering @@ -418,10 +444,18 @@ void wqthread_hijack(Addr self, Addr kport, Addr stackaddr, Addr workitem, if (reuse) { // Continue V's thread back in the scheduler. // The client thread is of course in another location entirely. + + /* Drop the lock before going into + ML_(wqthread_continue_NORETURN). The latter will immediately + attempt to reacquire it in non-LL mode, which is a bit + wasteful but I don't think is harmful. A better solution + would be to not drop the lock but instead "upgrade" it from a + LL lock to a full lock, but that's too much like hard work + right now. */ + VG_(release_BigLock_LL)("wqthread_hijack(1)"); ML_(wqthread_continue_NORETURN)(tst->tid); } else { - // Record thread's stack and Mach port and pthread struct tst->os_state.pthread = self; tst->os_state.lwpid = kport; @@ -445,11 +479,22 @@ void wqthread_hijack(Addr self, Addr kport, Addr stackaddr, Addr workitem, // guard page // GrP fixme ban_mem_stack! ML_(notify_core_and_tool_of_mmap)( - stack-VKI_PAGE_SIZE, VKI_PAGE_SIZE, 0, VKI_MAP_PRIVATE, -1, 0); + stack-VKI_PAGE_SIZE, VKI_PAGE_SIZE, + 0, VKI_MAP_PRIVATE, -1, 0); - VG_(am_do_sync_check)("after", "wqthread_hijack", 0); + ML_(sync_mappings)("after", "wqthread_hijack", 0); // Go! + /* Same comments as the 'release' in the then-clause. + start_thread_NORETURN calls run_thread_NORETURN calls + thread_wrapper which acquires the lock before continuing. + Let's hope nothing non-thread-local happens until that point. + + DDD: I think this is plain wrong .. if we get to + thread_wrapper not holding the lock, and someone has recycled + this thread slot in the meantime, we're hosed. Is that + possible, though? */ + VG_(release_BigLock_LL)("wqthread_hijack(2)"); call_on_new_stack_0_1(tst->os_state.valgrind_stack_init_SP, 0, start_thread_NORETURN, (Word)tst); } diff --git a/coregrind/m_syswrap/syswrap-amd64-linux.c b/coregrind/m_syswrap/syswrap-amd64-linux.c index 605d844..ecb3d00 100644 --- a/coregrind/m_syswrap/syswrap-amd64-linux.c +++ b/coregrind/m_syswrap/syswrap-amd64-linux.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -251,6 +251,17 @@ static SysRes do_clone ( ThreadId ptid, ctst->sig_mask = ptst->sig_mask; ctst->tmp_sig_mask = ptst->sig_mask; + /* Start the child with its threadgroup being the same as the + parent's. This is so that any exit_group calls that happen + after the child is created but before it sets its + os_state.threadgroup field for real (in thread_wrapper in + syswrap-linux.c), really kill the new thread. a.k.a this avoids + a race condition in which the thread is unkillable (via + exit_group) because its threadgroup is not set. The race window + is probably only a few hundred or a few thousand cycles long. + See #226116. */ + ctst->os_state.threadgroup = ptst->os_state.threadgroup; + /* We don't really know where the client stack is, because its allocated by the client. The best we can do is look at the memory mappings and try to derive some useful information. We @@ -349,6 +360,7 @@ DECL_TEMPLATE(amd64_linux, sys_setsockopt); DECL_TEMPLATE(amd64_linux, sys_getsockopt); DECL_TEMPLATE(amd64_linux, sys_connect); DECL_TEMPLATE(amd64_linux, sys_accept); +DECL_TEMPLATE(amd64_linux, sys_accept4); DECL_TEMPLATE(amd64_linux, sys_sendto); DECL_TEMPLATE(amd64_linux, sys_recvfrom); DECL_TEMPLATE(amd64_linux, sys_sendmsg); @@ -684,6 +696,23 @@ POST(sys_accept) SET_STATUS_from_SysRes(r); } +PRE(sys_accept4) +{ + *flags |= SfMayBlock; + PRINT("sys_accept4 ( %ld, %#lx, %ld, %ld )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "accept4", + int, s, struct sockaddr *, addr, int, *addrlen, int, flags); + ML_(generic_PRE_sys_accept)(tid, ARG1,ARG2,ARG3); +} +POST(sys_accept4) +{ + SysRes r; + vg_assert(SUCCESS); + r = ML_(generic_POST_sys_accept)(tid, VG_(mk_SysRes_Success)(RES), + ARG1,ARG2,ARG3); + SET_STATUS_from_SysRes(r); +} + PRE(sys_sendto) { *flags |= SfMayBlock; @@ -785,7 +814,7 @@ PRE(sys_socketpair) { PRINT("sys_socketpair ( %ld, %ld, %ld, %#lx )",ARG1,ARG2,ARG3,ARG4); PRE_REG_READ4(long, "socketpair", - int, d, int, type, int, protocol, int [2], sv); + int, d, int, type, int, protocol, int*, sv); ML_(generic_PRE_sys_socketpair)(tid, ARG1,ARG2,ARG3,ARG4); } POST(sys_socketpair) @@ -848,11 +877,11 @@ PRE(sys_semctl) int, semid, int, semnum, int, cmd); break; } - ML_(generic_PRE_sys_semctl)(tid, ARG1,ARG2,ARG3,ARG4); + ML_(generic_PRE_sys_semctl)(tid, ARG1,ARG2,ARG3|VKI_IPC_64,ARG4); } POST(sys_semctl) { - ML_(generic_POST_sys_semctl)(tid, RES,ARG1,ARG2,ARG3,ARG4); + ML_(generic_POST_sys_semctl)(tid, RES,ARG1,ARG2,ARG3|VKI_IPC_64,ARG4); } PRE(sys_msgget) @@ -938,11 +967,11 @@ PRE(sys_shmctl) PRINT("sys_shmctl ( %ld, %ld, %#lx )",ARG1,ARG2,ARG3); PRE_REG_READ3(long, "shmctl", int, shmid, int, cmd, struct shmid_ds *, buf); - ML_(generic_PRE_sys_shmctl)(tid, ARG1,ARG2,ARG3); + ML_(generic_PRE_sys_shmctl)(tid, ARG1,ARG2|VKI_IPC_64,ARG3); } POST(sys_shmctl) { - ML_(generic_POST_sys_shmctl)(tid, RES,ARG1,ARG2,ARG3); + ML_(generic_POST_sys_shmctl)(tid, RES,ARG1,ARG2|VKI_IPC_64,ARG3); } PRE(sys_fadvise64) @@ -1022,7 +1051,7 @@ POST(sys_syscall184) // When implementing these wrappers, you need to work out if the wrapper is // generic, Linux-only (but arch-independent), or AMD64/Linux only. -const SyscallTableEntry ML_(syscall_table)[] = { +static SyscallTableEntry syscall_table[] = { GENXY(__NR_read, sys_read), // 0 GENX_(__NR_write, sys_write), // 1 GENXY(__NR_open, sys_open), // 2 @@ -1200,20 +1229,20 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_sched_getscheduler, sys_sched_getscheduler), // 145 LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max), // 146 LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min), // 147 - //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 148 + LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 148 GENX_(__NR_mlock, sys_mlock), // 149 GENX_(__NR_munlock, sys_munlock), // 150 GENX_(__NR_mlockall, sys_mlockall), // 151 LINX_(__NR_munlockall, sys_munlockall), // 152 - // (__NR_vhangup, sys_vhangup), // 153 + LINX_(__NR_vhangup, sys_vhangup), // 153 // (__NR_modify_ldt, sys_modify_ldt), // 154 // (__NR_pivot_root, sys_pivot_root), // 155 LINXY(__NR__sysctl, sys_sysctl), // 156 LINXY(__NR_prctl, sys_prctl), // 157 PLAX_(__NR_arch_prctl, sys_arch_prctl), // 158 - // (__NR_adjtimex, sys_adjtimex), // 159 + LINXY(__NR_adjtimex, sys_adjtimex), // 159 GENX_(__NR_setrlimit, sys_setrlimit), // 160 GENX_(__NR_chroot, sys_chroot), // 161 @@ -1247,7 +1276,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { // (__NR_security, sys_ni_syscall), // 185 LINX_(__NR_gettid, sys_gettid), // 186 - // (__NR_readahead, sys_readahead), // 187 + LINX_(__NR_readahead, sys_readahead), // 187 LINX_(__NR_setxattr, sys_setxattr), // 188 LINX_(__NR_lsetxattr, sys_lsetxattr), // 189 @@ -1314,7 +1343,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINXY(__NR_mq_open, sys_mq_open), // 240 LINX_(__NR_mq_unlink, sys_mq_unlink), // 241 LINX_(__NR_mq_timedsend, sys_mq_timedsend), // 242 - LINX_(__NR_mq_timedreceive, sys_mq_timedreceive),// 243 + LINXY(__NR_mq_timedreceive, sys_mq_timedreceive),// 243 LINX_(__NR_mq_notify, sys_mq_notify), // 244 LINXY(__NR_mq_getsetattr, sys_mq_getsetattr), // 245 @@ -1353,7 +1382,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_set_robust_list, sys_set_robust_list), // 273 LINXY(__NR_get_robust_list, sys_get_robust_list), // 274 -// LINX_(__NR_splice, sys_ni_syscall), // 275 + LINX_(__NR_splice, sys_splice), // 275 // LINX_(__NR_tee, sys_ni_syscall), // 276 LINX_(__NR_sync_file_range, sys_sync_file_range), // 277 // LINX_(__NR_vmsplice, sys_ni_syscall), // 278 @@ -1368,18 +1397,38 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_fallocate, sys_fallocate), // 285 LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 286 LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 287 - // (__NR_paccept, sys_ni_syscall) // 288 + PLAXY(__NR_accept4, sys_accept4), // 288 LINXY(__NR_signalfd4, sys_signalfd4), // 289 LINX_(__NR_eventfd2, sys_eventfd2), // 290 LINXY(__NR_epoll_create1, sys_epoll_create1), // 291 - // (__NR_dup3, sys_ni_syscall) // 292 - LINXY(__NR_pipe2, sys_pipe2) // 293 - // (__NR_inotify_init1, sys_ni_syscall) // 294 + LINXY(__NR_dup3, sys_dup3), // 292 + LINXY(__NR_pipe2, sys_pipe2), // 293 + LINXY(__NR_inotify_init1, sys_inotify_init1), // 294 + + LINXY(__NR_preadv, sys_preadv), // 295 + LINX_(__NR_pwritev, sys_pwritev), // 296 + LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 297 + LINXY(__NR_perf_counter_open, sys_perf_counter_open) // 298 }; -const UInt ML_(syscall_table_size) = - sizeof(ML_(syscall_table)) / sizeof(ML_(syscall_table)[0]); +SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno ) +{ + const UInt syscall_table_size + = sizeof(syscall_table) / sizeof(syscall_table[0]); + + /* Is it in the contiguous initial section of the table? */ + if (sysno < syscall_table_size) { + SyscallTableEntry* sys = &syscall_table[sysno]; + if (sys->before == NULL) + return NULL; /* no entry */ + else + return sys; + } + + /* Can't find a wrapper */ + return NULL; +} #endif // defined(VGP_amd64_linux) diff --git a/coregrind/m_syswrap/syswrap-arm-linux.c b/coregrind/m_syswrap/syswrap-arm-linux.c new file mode 100644 index 0000000..fb12728 --- /dev/null +++ b/coregrind/m_syswrap/syswrap-arm-linux.c @@ -0,0 +1,1715 @@ + +/*--------------------------------------------------------------------*/ +/*--- Platform-specific syscalls stuff. syswrap-arm-linux.c -----*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2000-2010 Nicholas Nethercote + njn@valgrind.org + Copyright (C) 2008-2010 Evan Geller + gaze@bea.ms + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#if defined(VGP_arm_linux) + +#include "pub_core_basics.h" +#include "pub_core_vki.h" +#include "pub_core_vkiscnums.h" +#include "pub_core_threadstate.h" +#include "pub_core_aspacemgr.h" +#include "pub_core_debuglog.h" +#include "pub_core_libcbase.h" +#include "pub_core_libcassert.h" +#include "pub_core_libcprint.h" +#include "pub_core_libcproc.h" +#include "pub_core_libcsignal.h" +#include "pub_core_options.h" +#include "pub_core_scheduler.h" +#include "pub_core_sigframe.h" // For VG_(sigframe_destroy)() +#include "pub_core_signals.h" +#include "pub_core_syscall.h" +#include "pub_core_syswrap.h" +#include "pub_core_tooliface.h" +#include "pub_core_stacks.h" // VG_(register_stack) +#include "pub_core_transtab.h" // VG_(discard_translations) + +#include "priv_types_n_macros.h" +#include "priv_syswrap-generic.h" /* for decls of generic wrappers */ +#include "priv_syswrap-linux.h" /* for decls of linux-ish wrappers */ +#include "priv_syswrap-main.h" + + +/* --------------------------------------------------------------------- + clone() handling + ------------------------------------------------------------------ */ + +/* Call f(arg1), but first switch stacks, using 'stack' as the new + stack, and use 'retaddr' as f's return-to address. Also, clear all + the integer registers before entering f.*/ +__attribute__((noreturn)) +void ML_(call_on_new_stack_0_1) ( Addr stack, + Addr retaddr, + void (*f)(Word), + Word arg1 ); +// r0 = stack +// r1 = retaddr +// r2 = f +// r3 = arg1 +asm( +".text\n" +".globl vgModuleLocal_call_on_new_stack_0_1\n" +"vgModuleLocal_call_on_new_stack_0_1:\n" +" mov sp,r0\n\t" /* Stack pointer */ +" mov lr,r1\n\t" /* Return address */ +" mov r0,r3\n\t" /* First argument */ +" push {r2}\n\t" /* So we can ret to the new dest */ +" mov r1, #0\n\t" /* Clear our GPRs */ +" mov r2, #0\n\t" +" mov r3, #0\n\t" +" mov r4, #0\n\t" +" mov r5, #0\n\t" +" mov r6, #0\n\t" +" mov r7, #0\n\t" +" mov r8, #0\n\t" +" mov r9, #0\n\t" +" mov r10, #0\n\t" +" mov r11, #0\n\t" +" mov r12, #0\n\t" +" pop {pc}\n\t" /* Herrre we go! */ +".previous\n" +); + + +#define __NR_CLONE VG_STRINGIFY(__NR_clone) +#define __NR_EXIT VG_STRINGIFY(__NR_exit) + +extern +ULong do_syscall_clone_arm_linux ( Word (*fn)(void *), + void* stack, + Int flags, + void* arg, + Int* child_tid, + Int* parent_tid, + void* tls ); +asm( +".text\n" +"do_syscall_clone_arm_linux:\n" + +/*Setup child stack */ +" str r0, [r1, #-4]!\n" +" str r3, [r1, #-4]!\n" +" push {r4,r7}\n" +" mov r0, r2\n" /* arg1: flags */ +/* r1 (arg2) is already our child's stack */ +" ldr r2, [sp, #12]\n" // parent tid +" ldr r3, [sp, #16]\n" // tls +" ldr r4, [sp, #8]\n" // Child tid +" mov r7, #"__NR_CLONE"\n" +" svc 0x00000000\n" +" cmp r0, #0\n" +" beq 1f\n" + +/* Parent */ +" pop {r4,r7}\n" +" bx lr\n" + +"1:\n" /*child*/ +" mov lr, pc\n" +" pop {r0,pc}\n" +/* Retval from child is already in r0 */ +" mov r7, #"__NR_EXIT"\n" +" svc 0x00000000\n" +/* Urh.. why did exit return? */ +" .long 0\n" +" .previous\n" +); + +#undef __NR_CLONE +#undef __NR_EXIT + +// forward declarations +static void setup_child ( ThreadArchState*, ThreadArchState* ); +static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ); + +/* + When a client clones, we need to keep track of the new thread. This means: + 1. allocate a ThreadId+ThreadState+stack for the the thread + + 2. initialize the thread's new VCPU state + + 3. create the thread using the same args as the client requested, + but using the scheduler entrypoint for IP, and a separate stack + for SP. + */ +static SysRes do_clone ( ThreadId ptid, + UInt flags, Addr sp, + Int *parent_tidptr, + Int *child_tidptr, + Addr child_tls) +{ + const Bool debug = False; + + ThreadId ctid = VG_(alloc_ThreadState)(); + ThreadState* ptst = VG_(get_ThreadState)(ptid); + ThreadState* ctst = VG_(get_ThreadState)(ctid); + UInt r0; + UWord *stack; + NSegment const* seg; + SysRes res; + vki_sigset_t blockall, savedmask; + + VG_(sigfillset)(&blockall); + + vg_assert(VG_(is_running_thread)(ptid)); + vg_assert(VG_(is_valid_tid)(ctid)); + + stack = (UWord*)ML_(allocstack)(ctid); + + if(stack == NULL) { + res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); + goto out; + } + + setup_child( &ctst->arch, &ptst->arch ); + + ctst->arch.vex.guest_R0 = 0; + if(sp != 0) + ctst->arch.vex.guest_R13 = sp; + + ctst->os_state.parent = ptid; + + ctst->sig_mask = ptst->sig_mask; + ctst->tmp_sig_mask = ptst->sig_mask; + + /* Start the child with its threadgroup being the same as the + parent's. This is so that any exit_group calls that happen + after the child is created but before it sets its + os_state.threadgroup field for real (in thread_wrapper in + syswrap-linux.c), really kill the new thread. a.k.a this avoids + a race condition in which the thread is unkillable (via + exit_group) because its threadgroup is not set. The race window + is probably only a few hundred or a few thousand cycles long. + See #226116. */ + ctst->os_state.threadgroup = ptst->os_state.threadgroup; + + seg = VG_(am_find_nsegment)((Addr)sp); + if (seg && seg->kind != SkResvn) { + ctst->client_stack_highest_word = (Addr)VG_PGROUNDUP(sp); + ctst->client_stack_szB = ctst->client_stack_highest_word - seg->start; + + VG_(register_stack)(seg->start, ctst->client_stack_highest_word); + + if (debug) + VG_(printf)("tid %d: guessed client stack range %#lx-%#lx\n", + ctid, seg->start, VG_PGROUNDUP(sp)); + } else { + VG_(message)(Vg_UserMsg, "!? New thread %d starts with sp+%#lx) unmapped\n", ctid, sp); + ctst->client_stack_szB = 0; + } + + VG_TRACK ( pre_thread_ll_create, ptid, ctid ); + + if (flags & VKI_CLONE_SETTLS) { + res = sys_set_tls(ctid, child_tls); + if (sr_isError(res)) + goto out; + } + + flags &= ~VKI_CLONE_SETTLS; + + VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); + + r0 = do_syscall_clone_arm_linux( + ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid], + child_tidptr, parent_tidptr, NULL + ); + //VG_(printf)("AFTER SYSCALL, %x and %x CHILD: %d PARENT: %d\n",child_tidptr, parent_tidptr,*child_tidptr,*parent_tidptr); + + res = VG_(mk_SysRes_arm_linux)( r0 ); + + VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); + +out: + if (sr_isError(res)) { + VG_(cleanup_thread)(&ctst->arch); + ctst->status = VgTs_Empty; + VG_TRACK( pre_thread_ll_exit, ctid ); + } + + return res; +} + + + +/* --------------------------------------------------------------------- + More thread stuff + ------------------------------------------------------------------ */ + +// ARM doesn't have any architecture specific thread stuff that +// needs to be cleaned up +void VG_(cleanup_thread) ( ThreadArchState* arch ) +{ +} + +void setup_child ( /*OUT*/ ThreadArchState *child, + /*IN*/ ThreadArchState *parent ) +{ + child->vex = parent->vex; + child->vex_shadow1 = parent->vex_shadow1; + child->vex_shadow2 = parent->vex_shadow2; +} + +static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) +{ + VG_(threads)[tid].arch.vex.guest_TPIDRURO = tlsptr; + return VG_(mk_SysRes_Success)( 0 ); +} + +/* --------------------------------------------------------------------- + PRE/POST wrappers for arm/Linux-specific syscalls + ------------------------------------------------------------------ */ + +#define PRE(name) DEFN_PRE_TEMPLATE(arm_linux, name) +#define POST(name) DEFN_POST_TEMPLATE(arm_linux, name) + +/* Add prototypes for the wrappers declared here, so that gcc doesn't + harass us for not having prototypes. Really this is a kludge -- + the right thing to do is to make these wrappers 'static' since they + aren't visible outside this file, but that requires even more macro + magic. */ + +DECL_TEMPLATE(arm_linux, sys_socketcall); +DECL_TEMPLATE(arm_linux, sys_socket); +DECL_TEMPLATE(arm_linux, sys_setsockopt); +DECL_TEMPLATE(arm_linux, sys_getsockopt); +DECL_TEMPLATE(arm_linux, sys_connect); +DECL_TEMPLATE(arm_linux, sys_accept); +DECL_TEMPLATE(arm_linux, sys_sendto); +DECL_TEMPLATE(arm_linux, sys_recvfrom); +//XXX: Semaphore code ripped from AMD64. +DECL_TEMPLATE(arm_linux, sys_semget); +DECL_TEMPLATE(arm_linux, sys_semop); +DECL_TEMPLATE(arm_linux, sys_semctl); +DECL_TEMPLATE(arm_linux, sys_semtimedop); +//XXX: Shared memory code ripped from AMD64 +// +DECL_TEMPLATE(arm_linux, wrap_sys_shmat); +DECL_TEMPLATE(arm_linux, sys_shmget); +DECL_TEMPLATE(arm_linux, sys_shmdt); +DECL_TEMPLATE(arm_linux, sys_shmctl); +DECL_TEMPLATE(arm_linux, sys_sendmsg); +DECL_TEMPLATE(arm_linux, sys_recvmsg); +//msg* code from AMD64 +DECL_TEMPLATE(arm_linux, sys_msgget); +DECL_TEMPLATE(arm_linux, sys_msgrcv); +DECL_TEMPLATE(arm_linux, sys_msgsnd); +DECL_TEMPLATE(arm_linux, sys_msgctl); +DECL_TEMPLATE(arm_linux, sys_shutdown); +DECL_TEMPLATE(arm_linux, sys_bind); +DECL_TEMPLATE(arm_linux, sys_listen); +DECL_TEMPLATE(arm_linux, sys_getsockname); +DECL_TEMPLATE(arm_linux, sys_getpeername); +DECL_TEMPLATE(arm_linux, sys_socketpair); +DECL_TEMPLATE(arm_linux, sys_send); +DECL_TEMPLATE(arm_linux, sys_recv); +DECL_TEMPLATE(arm_linux, sys_mmap2); +DECL_TEMPLATE(arm_linux, sys_stat64); +DECL_TEMPLATE(arm_linux, sys_lstat64); +DECL_TEMPLATE(arm_linux, sys_fstatat64); +DECL_TEMPLATE(arm_linux, sys_fstat64); +DECL_TEMPLATE(arm_linux, sys_clone); +DECL_TEMPLATE(arm_linux, sys_sigreturn); +DECL_TEMPLATE(arm_linux, sys_rt_sigreturn); +DECL_TEMPLATE(arm_linux, sys_set_tls); +DECL_TEMPLATE(arm_linux, sys_cacheflush); + +PRE(sys_socketcall) +{ +# define ARG2_0 (((UWord*)ARG2)[0]) +# define ARG2_1 (((UWord*)ARG2)[1]) +# define ARG2_2 (((UWord*)ARG2)[2]) +# define ARG2_3 (((UWord*)ARG2)[3]) +# define ARG2_4 (((UWord*)ARG2)[4]) +# define ARG2_5 (((UWord*)ARG2)[5]) + + *flags |= SfMayBlock; + PRINT("sys_socketcall ( %ld, %#lx )",ARG1,ARG2); + PRE_REG_READ2(long, "socketcall", int, call, unsigned long *, args); + + switch (ARG1 /* request */) { + + case VKI_SYS_SOCKETPAIR: + /* int socketpair(int d, int type, int protocol, int sv[2]); */ + PRE_MEM_READ( "socketcall.socketpair(args)", ARG2, 4*sizeof(Addr) ); + ML_(generic_PRE_sys_socketpair)( tid, ARG2_0, ARG2_1, ARG2_2, ARG2_3 ); + break; + + case VKI_SYS_SOCKET: + /* int socket(int domain, int type, int protocol); */ + PRE_MEM_READ( "socketcall.socket(args)", ARG2, 3*sizeof(Addr) ); + break; + + case VKI_SYS_BIND: + /* int bind(int sockfd, struct sockaddr *my_addr, + int addrlen); */ + PRE_MEM_READ( "socketcall.bind(args)", ARG2, 3*sizeof(Addr) ); + ML_(generic_PRE_sys_bind)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_LISTEN: + /* int listen(int s, int backlog); */ + PRE_MEM_READ( "socketcall.listen(args)", ARG2, 2*sizeof(Addr) ); + break; + + case VKI_SYS_ACCEPT: { + /* int accept(int s, struct sockaddr *addr, int *addrlen); */ + PRE_MEM_READ( "socketcall.accept(args)", ARG2, 3*sizeof(Addr) ); + ML_(generic_PRE_sys_accept)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + } + + case VKI_SYS_SENDTO: + /* int sendto(int s, const void *msg, int len, + unsigned int flags, + const struct sockaddr *to, int tolen); */ + PRE_MEM_READ( "socketcall.sendto(args)", ARG2, 6*sizeof(Addr) ); + ML_(generic_PRE_sys_sendto)( tid, ARG2_0, ARG2_1, ARG2_2, + ARG2_3, ARG2_4, ARG2_5 ); + break; + + case VKI_SYS_SEND: + /* int send(int s, const void *msg, size_t len, int flags); */ + PRE_MEM_READ( "socketcall.send(args)", ARG2, 4*sizeof(Addr) ); + ML_(generic_PRE_sys_send)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_RECVFROM: + /* int recvfrom(int s, void *buf, int len, unsigned int flags, + struct sockaddr *from, int *fromlen); */ + PRE_MEM_READ( "socketcall.recvfrom(args)", ARG2, 6*sizeof(Addr) ); + ML_(generic_PRE_sys_recvfrom)( tid, ARG2_0, ARG2_1, ARG2_2, + ARG2_3, ARG2_4, ARG2_5 ); + break; + + case VKI_SYS_RECV: + /* int recv(int s, void *buf, int len, unsigned int flags); */ + /* man 2 recv says: + The recv call is normally used only on a connected socket + (see connect(2)) and is identical to recvfrom with a NULL + from parameter. + */ + PRE_MEM_READ( "socketcall.recv(args)", ARG2, 4*sizeof(Addr) ); + ML_(generic_PRE_sys_recv)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_CONNECT: + /* int connect(int sockfd, + struct sockaddr *serv_addr, int addrlen ); */ + PRE_MEM_READ( "socketcall.connect(args)", ARG2, 3*sizeof(Addr) ); + ML_(generic_PRE_sys_connect)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_SETSOCKOPT: + /* int setsockopt(int s, int level, int optname, + const void *optval, int optlen); */ + PRE_MEM_READ( "socketcall.setsockopt(args)", ARG2, 5*sizeof(Addr) ); + ML_(generic_PRE_sys_setsockopt)( tid, ARG2_0, ARG2_1, ARG2_2, + ARG2_3, ARG2_4 ); + break; + + case VKI_SYS_GETSOCKOPT: + /* int getsockopt(int s, int level, int optname, + void *optval, socklen_t *optlen); */ + PRE_MEM_READ( "socketcall.getsockopt(args)", ARG2, 5*sizeof(Addr) ); + ML_(linux_PRE_sys_getsockopt)( tid, ARG2_0, ARG2_1, ARG2_2, + ARG2_3, ARG2_4 ); + break; + + case VKI_SYS_GETSOCKNAME: + /* int getsockname(int s, struct sockaddr* name, int* namelen) */ + PRE_MEM_READ( "socketcall.getsockname(args)", ARG2, 3*sizeof(Addr) ); + ML_(generic_PRE_sys_getsockname)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_GETPEERNAME: + /* int getpeername(int s, struct sockaddr* name, int* namelen) */ + PRE_MEM_READ( "socketcall.getpeername(args)", ARG2, 3*sizeof(Addr) ); + ML_(generic_PRE_sys_getpeername)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_SHUTDOWN: + /* int shutdown(int s, int how); */ + PRE_MEM_READ( "socketcall.shutdown(args)", ARG2, 2*sizeof(Addr) ); + break; + + case VKI_SYS_SENDMSG: { + /* int sendmsg(int s, const struct msghdr *msg, int flags); */ + + /* this causes warnings, and I don't get why. glibc bug? + * (after all it's glibc providing the arguments array) + PRE_MEM_READ( "socketcall.sendmsg(args)", ARG2, 3*sizeof(Addr) ); + */ + ML_(generic_PRE_sys_sendmsg)( tid, ARG2_0, ARG2_1 ); + break; + } + + case VKI_SYS_RECVMSG: { + /* int recvmsg(int s, struct msghdr *msg, int flags); */ + + /* this causes warnings, and I don't get why. glibc bug? + * (after all it's glibc providing the arguments array) + PRE_MEM_READ("socketcall.recvmsg(args)", ARG2, 3*sizeof(Addr) ); + */ + ML_(generic_PRE_sys_recvmsg)( tid, ARG2_0, ARG2_1 ); + break; + } + + default: + VG_(message)(Vg_DebugMsg,"Warning: unhandled socketcall 0x%lx",ARG1); + SET_STATUS_Failure( VKI_EINVAL ); + break; + } +# undef ARG2_0 +# undef ARG2_1 +# undef ARG2_2 +# undef ARG2_3 +# undef ARG2_4 +# undef ARG2_5 +} + +POST(sys_socketcall) +{ +# define ARG2_0 (((UWord*)ARG2)[0]) +# define ARG2_1 (((UWord*)ARG2)[1]) +# define ARG2_2 (((UWord*)ARG2)[2]) +# define ARG2_3 (((UWord*)ARG2)[3]) +# define ARG2_4 (((UWord*)ARG2)[4]) +# define ARG2_5 (((UWord*)ARG2)[5]) + + SysRes r; + vg_assert(SUCCESS); + switch (ARG1 /* request */) { + + case VKI_SYS_SOCKETPAIR: + r = ML_(generic_POST_sys_socketpair)( + tid, VG_(mk_SysRes_Success)(RES), + ARG2_0, ARG2_1, ARG2_2, ARG2_3 + ); + SET_STATUS_from_SysRes(r); + break; + + case VKI_SYS_SOCKET: + r = ML_(generic_POST_sys_socket)( tid, VG_(mk_SysRes_Success)(RES) ); + SET_STATUS_from_SysRes(r); + break; + + case VKI_SYS_BIND: + /* int bind(int sockfd, struct sockaddr *my_addr, + int addrlen); */ + break; + + case VKI_SYS_LISTEN: + /* int listen(int s, int backlog); */ + break; + + case VKI_SYS_ACCEPT: + /* int accept(int s, struct sockaddr *addr, int *addrlen); */ + r = ML_(generic_POST_sys_accept)( tid, VG_(mk_SysRes_Success)(RES), + ARG2_0, ARG2_1, ARG2_2 ); + SET_STATUS_from_SysRes(r); + break; + + case VKI_SYS_SENDTO: + break; + + case VKI_SYS_SEND: + break; + + case VKI_SYS_RECVFROM: + ML_(generic_POST_sys_recvfrom)( tid, VG_(mk_SysRes_Success)(RES), + ARG2_0, ARG2_1, ARG2_2, + ARG2_3, ARG2_4, ARG2_5 ); + break; + + case VKI_SYS_RECV: + ML_(generic_POST_sys_recv)( tid, RES, ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_CONNECT: + break; + + case VKI_SYS_SETSOCKOPT: + break; + + case VKI_SYS_GETSOCKOPT: + ML_(linux_POST_sys_getsockopt)( tid, VG_(mk_SysRes_Success)(RES), + ARG2_0, ARG2_1, + ARG2_2, ARG2_3, ARG2_4 ); + break; + + case VKI_SYS_GETSOCKNAME: + ML_(generic_POST_sys_getsockname)( tid, VG_(mk_SysRes_Success)(RES), + ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_GETPEERNAME: + ML_(generic_POST_sys_getpeername)( tid, VG_(mk_SysRes_Success)(RES), + ARG2_0, ARG2_1, ARG2_2 ); + break; + + case VKI_SYS_SHUTDOWN: + break; + + case VKI_SYS_SENDMSG: + break; + + case VKI_SYS_RECVMSG: + ML_(generic_POST_sys_recvmsg)( tid, ARG2_0, ARG2_1 ); + break; + + default: + VG_(message)(Vg_DebugMsg,"FATAL: unhandled socketcall 0x%lx",ARG1); + VG_(core_panic)("... bye!\n"); + break; /*NOTREACHED*/ + } +# undef ARG2_0 +# undef ARG2_1 +# undef ARG2_2 +# undef ARG2_3 +# undef ARG2_4 +# undef ARG2_5 +} + +PRE(sys_socket) +{ + PRINT("sys_socket ( %ld, %ld, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "socket", int, domain, int, type, int, protocol); +} +POST(sys_socket) +{ + SysRes r; + vg_assert(SUCCESS); + r = ML_(generic_POST_sys_socket)(tid, VG_(mk_SysRes_Success)(RES)); + SET_STATUS_from_SysRes(r); +} + +PRE(sys_setsockopt) +{ + PRINT("sys_setsockopt ( %ld, %ld, %ld, %#lx, %ld )",ARG1,ARG2,ARG3,ARG4,ARG5); + PRE_REG_READ5(long, "setsockopt", + int, s, int, level, int, optname, + const void *, optval, int, optlen); + ML_(generic_PRE_sys_setsockopt)(tid, ARG1,ARG2,ARG3,ARG4,ARG5); +} + +PRE(sys_getsockopt) +{ + PRINT("sys_getsockopt ( %ld, %ld, %ld, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); + PRE_REG_READ5(long, "getsockopt", + int, s, int, level, int, optname, + void *, optval, int, *optlen); + ML_(linux_PRE_sys_getsockopt)(tid, ARG1,ARG2,ARG3,ARG4,ARG5); +} +POST(sys_getsockopt) +{ + vg_assert(SUCCESS); + ML_(linux_POST_sys_getsockopt)(tid, VG_(mk_SysRes_Success)(RES), + ARG1,ARG2,ARG3,ARG4,ARG5); +} + +PRE(sys_connect) +{ + *flags |= SfMayBlock; + PRINT("sys_connect ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "connect", + int, sockfd, struct sockaddr *, serv_addr, int, addrlen); + ML_(generic_PRE_sys_connect)(tid, ARG1,ARG2,ARG3); +} + +PRE(sys_accept) +{ + *flags |= SfMayBlock; + PRINT("sys_accept ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "accept", + int, s, struct sockaddr *, addr, int, *addrlen); + ML_(generic_PRE_sys_accept)(tid, ARG1,ARG2,ARG3); +} +POST(sys_accept) +{ + SysRes r; + vg_assert(SUCCESS); + r = ML_(generic_POST_sys_accept)(tid, VG_(mk_SysRes_Success)(RES), + ARG1,ARG2,ARG3); + SET_STATUS_from_SysRes(r); +} + +PRE(sys_sendto) +{ + *flags |= SfMayBlock; + PRINT("sys_sendto ( %ld, %#lx, %ld, %lu, %#lx, %ld )",ARG1,ARG2,ARG3,ARG4,ARG5,ARG6); + PRE_REG_READ6(long, "sendto", + int, s, const void *, msg, int, len, + unsigned int, flags, + const struct sockaddr *, to, int, tolen); + ML_(generic_PRE_sys_sendto)(tid, ARG1,ARG2,ARG3,ARG4,ARG5,ARG6); +} + +PRE(sys_recvfrom) +{ + *flags |= SfMayBlock; + PRINT("sys_recvfrom ( %ld, %#lx, %ld, %lu, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5,ARG6); + PRE_REG_READ6(long, "recvfrom", + int, s, void *, buf, int, len, unsigned int, flags, + struct sockaddr *, from, int *, fromlen); + ML_(generic_PRE_sys_recvfrom)(tid, ARG1,ARG2,ARG3,ARG4,ARG5,ARG6); +} +POST(sys_recvfrom) +{ + vg_assert(SUCCESS); + ML_(generic_POST_sys_recvfrom)(tid, VG_(mk_SysRes_Success)(RES), + ARG1,ARG2,ARG3,ARG4,ARG5,ARG6); +} + +PRE(sys_sendmsg) +{ + *flags |= SfMayBlock; + PRINT("sys_sendmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "sendmsg", + int, s, const struct msghdr *, msg, int, flags); + ML_(generic_PRE_sys_sendmsg)(tid, ARG1,ARG2); +} + +PRE(sys_recvmsg) +{ + *flags |= SfMayBlock; + PRINT("sys_recvmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "recvmsg", int, s, struct msghdr *, msg, int, flags); + ML_(generic_PRE_sys_recvmsg)(tid, ARG1,ARG2); +} +POST(sys_recvmsg) +{ + ML_(generic_POST_sys_recvmsg)(tid, ARG1,ARG2); +} + +//XXX: Semaphore code ripped from AMD64. +PRE(sys_semget) +{ + PRINT("sys_semget ( %ld, %ld, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "semget", vki_key_t, key, int, nsems, int, semflg); +} + +PRE(sys_semop) +{ + *flags |= SfMayBlock; + PRINT("sys_semop ( %ld, %#lx, %lu )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "semop", + int, semid, struct sembuf *, sops, unsigned, nsoops); + ML_(generic_PRE_sys_semop)(tid, ARG1,ARG2,ARG3); +} + +PRE(sys_semctl) +{ + switch (ARG3 & ~VKI_IPC_64) { + case VKI_IPC_INFO: + case VKI_SEM_INFO: + PRINT("sys_semctl ( %ld, %ld, %ld, %#lx )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "semctl", + int, semid, int, semnum, int, cmd, struct seminfo *, arg); + break; + case VKI_IPC_STAT: + case VKI_SEM_STAT: + case VKI_IPC_SET: + PRINT("sys_semctl ( %ld, %ld, %ld, %#lx )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "semctl", + int, semid, int, semnum, int, cmd, struct semid_ds *, arg); + break; + case VKI_GETALL: + case VKI_SETALL: + PRINT("sys_semctl ( %ld, %ld, %ld, %#lx )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "semctl", + int, semid, int, semnum, int, cmd, unsigned short *, arg); + break; + default: + PRINT("sys_semctl ( %ld, %ld, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "semctl", + int, semid, int, semnum, int, cmd); + break; + } + ML_(generic_PRE_sys_semctl)(tid, ARG1,ARG2,ARG3,ARG4); +} + +POST(sys_semctl) +{ + ML_(generic_POST_sys_semctl)(tid, RES,ARG1,ARG2,ARG3,ARG4); +} + +PRE(sys_semtimedop) +{ + *flags |= SfMayBlock; + PRINT("sys_semtimedop ( %ld, %#lx, %lu, %#lx )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "semtimedop", + int, semid, struct sembuf *, sops, unsigned, nsoops, + struct timespec *, timeout); + ML_(generic_PRE_sys_semtimedop)(tid, ARG1,ARG2,ARG3,ARG4); +} + +//amd64 +PRE(sys_msgget) +{ + PRINT("sys_msgget ( %ld, %ld )",ARG1,ARG2); + PRE_REG_READ2(long, "msgget", vki_key_t, key, int, msgflg); +} + +PRE(sys_msgsnd) +{ + PRINT("sys_msgsnd ( %ld, %#lx, %ld, %ld )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "msgsnd", + int, msqid, struct msgbuf *, msgp, vki_size_t, msgsz, int, msgflg); + ML_(linux_PRE_sys_msgsnd)(tid, ARG1,ARG2,ARG3,ARG4); + if ((ARG4 & VKI_IPC_NOWAIT) == 0) + *flags |= SfMayBlock; +} + +PRE(sys_msgrcv) +{ + PRINT("sys_msgrcv ( %ld, %#lx, %ld, %ld, %ld )",ARG1,ARG2,ARG3,ARG4,ARG5); + PRE_REG_READ5(long, "msgrcv", + int, msqid, struct msgbuf *, msgp, vki_size_t, msgsz, + long, msgytp, int, msgflg); + ML_(linux_PRE_sys_msgrcv)(tid, ARG1,ARG2,ARG3,ARG4,ARG5); + if ((ARG4 & VKI_IPC_NOWAIT) == 0) + *flags |= SfMayBlock; +} +POST(sys_msgrcv) +{ + ML_(linux_POST_sys_msgrcv)(tid, RES,ARG1,ARG2,ARG3,ARG4,ARG5); +} + + +PRE(sys_msgctl) +{ + PRINT("sys_msgctl ( %ld, %ld, %#lx )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "msgctl", + int, msqid, int, cmd, struct msqid_ds *, buf); + ML_(linux_PRE_sys_msgctl)(tid, ARG1,ARG2,ARG3); +} +POST(sys_msgctl) +{ + ML_(linux_POST_sys_msgctl)(tid, RES,ARG1,ARG2,ARG3); +} + +//shared memory code from AMD64 +PRE(sys_shmget) +{ + PRINT("sys_shmget ( %ld, %ld, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "shmget", vki_key_t, key, vki_size_t, size, int, shmflg); +} + +PRE(wrap_sys_shmat) +{ + UWord arg2tmp; + PRINT("wrap_sys_shmat ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "shmat", + int, shmid, const void *, shmaddr, int, shmflg); + /* Round the attach address down to an VKI_SHMLBA boundary if the + client requested rounding. See #222545. This is necessary only + on arm-linux because VKI_SHMLBA is 4 * VKI_PAGE size; on all + other linux targets it is the same as the page size. */ + if (ARG3 & VKI_SHM_RND) + ARG2 = VG_ROUNDDN(ARG2, VKI_SHMLBA); + arg2tmp = ML_(generic_PRE_sys_shmat)(tid, ARG1,ARG2,ARG3); + if (arg2tmp == 0) + SET_STATUS_Failure( VKI_EINVAL ); + else + ARG2 = arg2tmp; +} + +POST(wrap_sys_shmat) +{ + ML_(generic_POST_sys_shmat)(tid, RES,ARG1,ARG2,ARG3); +} + +PRE(sys_shmdt) +{ + PRINT("sys_shmdt ( %#lx )",ARG1); + PRE_REG_READ1(long, "shmdt", const void *, shmaddr); + if (!ML_(generic_PRE_sys_shmdt)(tid, ARG1)) + SET_STATUS_Failure( VKI_EINVAL ); +} + +POST(sys_shmdt) +{ + ML_(generic_POST_sys_shmdt)(tid, RES,ARG1); +} + +PRE(sys_shmctl) +{ + PRINT("sys_shmctl ( %ld, %ld, %#lx )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "shmctl", + int, shmid, int, cmd, struct shmid_ds *, buf); + ML_(generic_PRE_sys_shmctl)(tid, ARG1,ARG2,ARG3); +} + +POST(sys_shmctl) +{ + ML_(generic_POST_sys_shmctl)(tid, RES,ARG1,ARG2,ARG3); +} + +PRE(sys_shutdown) +{ + *flags |= SfMayBlock; + PRINT("sys_shutdown ( %ld, %ld )",ARG1,ARG2); + PRE_REG_READ2(int, "shutdown", int, s, int, how); +} + +PRE(sys_bind) +{ + PRINT("sys_bind ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "bind", + int, sockfd, struct sockaddr *, my_addr, int, addrlen); + ML_(generic_PRE_sys_bind)(tid, ARG1,ARG2,ARG3); +} + +PRE(sys_listen) +{ + PRINT("sys_listen ( %ld, %ld )",ARG1,ARG2); + PRE_REG_READ2(long, "listen", int, s, int, backlog); +} + +PRE(sys_getsockname) +{ + PRINT("sys_getsockname ( %ld, %#lx, %#lx )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "getsockname", + int, s, struct sockaddr *, name, int *, namelen); + ML_(generic_PRE_sys_getsockname)(tid, ARG1,ARG2,ARG3); +} +POST(sys_getsockname) +{ + vg_assert(SUCCESS); + ML_(generic_POST_sys_getsockname)(tid, VG_(mk_SysRes_Success)(RES), + ARG1,ARG2,ARG3); +} + +PRE(sys_getpeername) +{ + PRINT("sys_getpeername ( %ld, %#lx, %#lx )",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "getpeername", + int, s, struct sockaddr *, name, int *, namelen); + ML_(generic_PRE_sys_getpeername)(tid, ARG1,ARG2,ARG3); +} +POST(sys_getpeername) +{ + vg_assert(SUCCESS); + ML_(generic_POST_sys_getpeername)(tid, VG_(mk_SysRes_Success)(RES), + ARG1,ARG2,ARG3); +} + +PRE(sys_socketpair) +{ + PRINT("sys_socketpair ( %ld, %ld, %ld, %#lx )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "socketpair", + int, d, int, type, int, protocol, int*, sv); + ML_(generic_PRE_sys_socketpair)(tid, ARG1,ARG2,ARG3,ARG4); +} +POST(sys_socketpair) +{ + vg_assert(SUCCESS); + ML_(generic_POST_sys_socketpair)(tid, VG_(mk_SysRes_Success)(RES), + ARG1,ARG2,ARG3,ARG4); +} + +PRE(sys_send) +{ + *flags |= SfMayBlock; + PRINT("sys_send ( %ld, %#lx, %ld, %lu )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "send", + int, s, const void *, msg, int, len, + unsigned int, flags); + + ML_(generic_PRE_sys_send)( tid, ARG1, ARG2, ARG3 ); +} + +PRE(sys_recv) +{ + *flags |= SfMayBlock; + PRINT("sys_recv ( %ld, %#lx, %ld, %lu )",ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(long, "recv", + int, s, void *, buf, int, len, unsigned int, flags); + ML_(generic_PRE_sys_recv)( tid, ARG1, ARG2, ARG3 ); +} + +POST(sys_recv) +{ + ML_(generic_POST_sys_recv)( tid, RES, ARG1, ARG2, ARG3 ); +} + +PRE(sys_mmap2) +{ + SysRes r; + + // Exactly like old_mmap() except: + // - all 6 args are passed in regs, rather than in a memory-block. + // - the file offset is specified in pagesize units rather than bytes, + // so that it can be used for files bigger than 2^32 bytes. + // pagesize or 4K-size units in offset? For ppc32/64-linux, this is + // 4K-sized. Assert that the page size is 4K here for safety. + vg_assert(VKI_PAGE_SIZE == 4096); + PRINT("sys_mmap2 ( %#lx, %llu, %ld, %ld, %ld, %ld )", + ARG1, (ULong)ARG2, ARG3, ARG4, ARG5, ARG6 ); + PRE_REG_READ6(long, "mmap2", + unsigned long, start, unsigned long, length, + unsigned long, prot, unsigned long, flags, + unsigned long, fd, unsigned long, offset); + + r = ML_(generic_PRE_sys_mmap)( tid, ARG1, ARG2, ARG3, ARG4, ARG5, + 4096 * (Off64T)ARG6 ); + SET_STATUS_from_SysRes(r); +} + +// XXX: lstat64/fstat64/stat64 are generic, but not necessarily +// applicable to every architecture -- I think only to 32-bit archs. +// We're going to need something like linux/core_os32.h for such +// things, eventually, I think. --njn +PRE(sys_lstat64) +{ + PRINT("sys_lstat64 ( %#lx(%s), %#lx )",ARG1,(char*)ARG1,ARG2); + PRE_REG_READ2(long, "lstat64", char *, file_name, struct stat64 *, buf); + PRE_MEM_RASCIIZ( "lstat64(file_name)", ARG1 ); + PRE_MEM_WRITE( "lstat64(buf)", ARG2, sizeof(struct vki_stat64) ); +} + +POST(sys_lstat64) +{ + vg_assert(SUCCESS); + if (RES == 0) { + POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); + } +} + +PRE(sys_stat64) +{ + PRINT("sys_stat64 ( %#lx(%s), %#lx )",ARG1,(char*)ARG1,ARG2); + PRE_REG_READ2(long, "stat64", char *, file_name, struct stat64 *, buf); + PRE_MEM_RASCIIZ( "stat64(file_name)", ARG1 ); + PRE_MEM_WRITE( "stat64(buf)", ARG2, sizeof(struct vki_stat64) ); +} + +POST(sys_stat64) +{ + POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); +} + +PRE(sys_fstatat64) +{ + PRINT("sys_fstatat64 ( %ld, %#lx(%s), %#lx )",ARG1,ARG2,(char*)ARG2,ARG3); + PRE_REG_READ3(long, "fstatat64", + int, dfd, char *, file_name, struct stat64 *, buf); + PRE_MEM_RASCIIZ( "fstatat64(file_name)", ARG2 ); + PRE_MEM_WRITE( "fstatat64(buf)", ARG3, sizeof(struct vki_stat64) ); +} + +POST(sys_fstatat64) +{ + POST_MEM_WRITE( ARG3, sizeof(struct vki_stat64) ); +} + +PRE(sys_fstat64) +{ + PRINT("sys_fstat64 ( %ld, %#lx )",ARG1,ARG2); + PRE_REG_READ2(long, "fstat64", unsigned long, fd, struct stat64 *, buf); + PRE_MEM_WRITE( "fstat64(buf)", ARG2, sizeof(struct vki_stat64) ); +} + +POST(sys_fstat64) +{ + POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); +} + +PRE(sys_clone) +{ + UInt cloneflags; + + PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); + PRE_REG_READ5(int, "clone", + unsigned long, flags, + void *, child_stack, + int *, parent_tidptr, + void *, child_tls, + int *, child_tidptr); + + if (ARG1 & VKI_CLONE_PARENT_SETTID) { + PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); + if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), + VKI_PROT_WRITE)) { + SET_STATUS_Failure( VKI_EFAULT ); + return; + } + } + if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { + PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int)); + if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int), + VKI_PROT_WRITE)) { + SET_STATUS_Failure( VKI_EFAULT ); + return; + } + } + if (ARG1 & VKI_CLONE_SETTLS) { + PRE_MEM_READ("clone(tls_user_desc)", ARG4, sizeof(vki_modify_ldt_t)); + if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t), + VKI_PROT_READ)) { + SET_STATUS_Failure( VKI_EFAULT ); + return; + } + } + + cloneflags = ARG1; + + if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { + SET_STATUS_Failure( VKI_EINVAL ); + return; + } + + /* Only look at the flags we really care about */ + switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS + | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { + case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: + /* thread creation */ + SET_STATUS_from_SysRes( + do_clone(tid, + ARG1, /* flags */ + (Addr)ARG2, /* child ESP */ + (Int *)ARG3, /* parent_tidptr */ + (Int *)ARG5, /* child_tidptr */ + (Addr)ARG4)); /* set_tls */ + break; + + case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ + /* FALLTHROUGH - assume vfork == fork */ + cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); + + case 0: /* plain fork */ + SET_STATUS_from_SysRes( + ML_(do_fork_clone)(tid, + cloneflags, /* flags */ + (Int *)ARG3, /* parent_tidptr */ + (Int *)ARG5)); /* child_tidptr */ + break; + + default: + /* should we just ENOSYS? */ + VG_(message)(Vg_UserMsg, ""); + VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx", ARG1); + VG_(message)(Vg_UserMsg, ""); + VG_(message)(Vg_UserMsg, "The only supported clone() uses are:"); + VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)"); + VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork"); + VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver"); + VG_(unimplemented) + ("Valgrind does not support general clone()."); + } + + if (SUCCESS) { + if (ARG1 & VKI_CLONE_PARENT_SETTID) + POST_MEM_WRITE(ARG3, sizeof(Int)); + if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) + POST_MEM_WRITE(ARG5, sizeof(Int)); + + /* Thread creation was successful; let the child have the chance + to run */ + *flags |= SfYieldAfter; + } +} + +PRE(sys_sigreturn) +{ + /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for + an explanation of what follows. */ + + PRINT("sys_sigreturn ( )"); + + vg_assert(VG_(is_valid_tid)(tid)); + vg_assert(tid >= 1 && tid < VG_N_THREADS); + vg_assert(VG_(is_running_thread)(tid)); + + /* Restore register state from frame and remove it */ + VG_(sigframe_destroy)(tid, False); + + /* Tell the driver not to update the guest state with the "result", + and set a bogus result to keep it happy. */ + *flags |= SfNoWriteResult; + SET_STATUS_Success(0); + + /* Check to see if any signals arose as a result of this. */ + *flags |= SfPollAfter; +} + +PRE(sys_rt_sigreturn) +{ + /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for + an explanation of what follows. */ + + PRINT("rt_sigreturn ( )"); + + vg_assert(VG_(is_valid_tid)(tid)); + vg_assert(tid >= 1 && tid < VG_N_THREADS); + vg_assert(VG_(is_running_thread)(tid)); + + /* Restore register state from frame and remove it */ + VG_(sigframe_destroy)(tid, True); + + /* Tell the driver not to update the guest state with the "result", + and set a bogus result to keep it happy. */ + *flags |= SfNoWriteResult; + SET_STATUS_Success(0); + + /* Check to see if any signals arose as a result of this. */ + *flags |= SfPollAfter; +} + +/* Very much ARM specific */ + +PRE(sys_set_tls) +{ + PRE_REG_READ1(long, "set_tls", unsigned long, addr); + + SET_STATUS_from_SysRes( sys_set_tls( tid, ARG1 ) ); +} + +PRE(sys_cacheflush) +{ + PRINT("cacheflush (%lx, %#lx, %#lx)",ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "cacheflush", void*, addrlow,void*, addrhigh,int, flags); + VG_(discard_translations)( (Addr64)ARG1, + ((ULong)ARG2) - ((ULong)ARG1) + 1ULL/*paranoia*/, + "PRE(sys_cacheflush)" ); + SET_STATUS_Success(0); +} + + +#undef PRE +#undef POST + +/* --------------------------------------------------------------------- + The arm/Linux syscall table + ------------------------------------------------------------------ */ + +#if 0 +#define __NR_OABI_SYSCALL_BASE 0x900000 +#else +#define __NR_OABI_SYSCALL_BASE 0x0 +#endif + +#define PLAX_(sysno, name) WRAPPER_ENTRY_X_(arm_linux, sysno, name) +#define PLAXY(sysno, name) WRAPPER_ENTRY_XY(arm_linux, sysno, name) + +// This table maps from __NR_xxx syscall numbers (from +// linux/include/asm-arm/unistd.h) to the appropriate PRE/POST sys_foo() +// wrappers on arm (as per sys_call_table in linux/arch/arm/kernel/entry.S). +// +// For those syscalls not handled by Valgrind, the annotation indicate its +// arch/OS combination, eg. */* (generic), */Linux (Linux only), ?/? +// (unknown). + +static SyscallTableEntry syscall_main_table[] = { +//zz // (restart_syscall) // 0 + GENX_(__NR_exit, sys_exit), // 1 + GENX_(__NR_fork, sys_fork), // 2 + GENXY(__NR_read, sys_read), // 3 + GENX_(__NR_write, sys_write), // 4 + + GENXY(__NR_open, sys_open), // 5 + GENXY(__NR_close, sys_close), // 6 +// GENXY(__NR_waitpid, sys_waitpid), // 7 + GENXY(__NR_creat, sys_creat), // 8 + GENX_(__NR_link, sys_link), // 9 + + GENX_(__NR_unlink, sys_unlink), // 10 + GENX_(__NR_execve, sys_execve), // 11 + GENX_(__NR_chdir, sys_chdir), // 12 + GENXY(__NR_time, sys_time), // 13 + GENX_(__NR_mknod, sys_mknod), // 14 + + GENX_(__NR_chmod, sys_chmod), // 15 +//zz LINX_(__NR_lchown, sys_lchown16), // 16 +// GENX_(__NR_break, sys_ni_syscall), // 17 +//zz // (__NR_oldstat, sys_stat), // 18 (obsolete) + LINX_(__NR_lseek, sys_lseek), // 19 + + GENX_(__NR_getpid, sys_getpid), // 20 + LINX_(__NR_mount, sys_mount), // 21 + LINX_(__NR_umount, sys_oldumount), // 22 + LINX_(__NR_setuid, sys_setuid16), // 23 ## P + LINX_(__NR_getuid, sys_getuid16), // 24 ## P +//zz +//zz // (__NR_stime, sys_stime), // 25 * (SVr4,SVID,X/OPEN) +// PLAXY(__NR_ptrace, sys_ptrace), // 26 + GENX_(__NR_alarm, sys_alarm), // 27 +//zz // (__NR_oldfstat, sys_fstat), // 28 * L -- obsolete + GENX_(__NR_pause, sys_pause), // 29 + + LINX_(__NR_utime, sys_utime), // 30 +// GENX_(__NR_stty, sys_ni_syscall), // 31 +// GENX_(__NR_gtty, sys_ni_syscall), // 32 + GENX_(__NR_access, sys_access), // 33 + GENX_(__NR_nice, sys_nice), // 34 + +// GENX_(__NR_ftime, sys_ni_syscall), // 35 + GENX_(__NR_sync, sys_sync), // 36 + GENX_(__NR_kill, sys_kill), // 37 + GENX_(__NR_rename, sys_rename), // 38 + GENX_(__NR_mkdir, sys_mkdir), // 39 + + GENX_(__NR_rmdir, sys_rmdir), // 40 + GENXY(__NR_dup, sys_dup), // 41 + LINXY(__NR_pipe, sys_pipe), // 42 + GENXY(__NR_times, sys_times), // 43 +// GENX_(__NR_prof, sys_ni_syscall), // 44 +//zz + GENX_(__NR_brk, sys_brk), // 45 + LINX_(__NR_setgid, sys_setgid16), // 46 + LINX_(__NR_getgid, sys_getgid16), // 47 +//zz // (__NR_signal, sys_signal), // 48 */* (ANSI C) + LINX_(__NR_geteuid, sys_geteuid16), // 49 + + LINX_(__NR_getegid, sys_getegid16), // 50 + GENX_(__NR_acct, sys_acct), // 51 + LINX_(__NR_umount2, sys_umount), // 52 +// GENX_(__NR_lock, sys_ni_syscall), // 53 + LINXY(__NR_ioctl, sys_ioctl), // 54 + + LINXY(__NR_fcntl, sys_fcntl), // 55 +// GENX_(__NR_mpx, sys_ni_syscall), // 56 + GENX_(__NR_setpgid, sys_setpgid), // 57 +// GENX_(__NR_ulimit, sys_ni_syscall), // 58 +//zz // (__NR_oldolduname, sys_olduname), // 59 Linux -- obsolete +//zz + GENX_(__NR_umask, sys_umask), // 60 + GENX_(__NR_chroot, sys_chroot), // 61 +//zz // (__NR_ustat, sys_ustat) // 62 SVr4 -- deprecated + GENXY(__NR_dup2, sys_dup2), // 63 + GENX_(__NR_getppid, sys_getppid), // 64 + + GENX_(__NR_getpgrp, sys_getpgrp), // 65 + GENX_(__NR_setsid, sys_setsid), // 66 +// _____(__NR_sigaction, sys_sigaction), // 67 +//zz // (__NR_sgetmask, sys_sgetmask), // 68 */* (ANSI C) +//zz // (__NR_ssetmask, sys_ssetmask), // 69 */* (ANSI C) +//zz + LINX_(__NR_setreuid, sys_setreuid16), // 70 + LINX_(__NR_setregid, sys_setregid16), // 71 +// _____(__NR_sigsuspend, sys_sigsuspend), // 72 + LINXY(__NR_sigpending, sys_sigpending), // 73 +//zz // (__NR_sethostname, sys_sethostname), // 74 */* +//zz + GENX_(__NR_setrlimit, sys_setrlimit), // 75 + GENXY(__NR_getrlimit, sys_old_getrlimit), // 76 + GENXY(__NR_getrusage, sys_getrusage), // 77 + GENXY(__NR_gettimeofday, sys_gettimeofday), // 78 + GENX_(__NR_settimeofday, sys_settimeofday), // 79 + + LINXY(__NR_getgroups, sys_getgroups16), // 80 + LINX_(__NR_setgroups, sys_setgroups16), // 81 +// PLAX_(__NR_select, old_select), // 82 + GENX_(__NR_symlink, sys_symlink), // 83 +//zz // (__NR_oldlstat, sys_lstat), // 84 -- obsolete +//zz + GENX_(__NR_readlink, sys_readlink), // 85 +//zz // (__NR_uselib, sys_uselib), // 86 */Linux +//zz // (__NR_swapon, sys_swapon), // 87 */Linux +//zz // (__NR_reboot, sys_reboot), // 88 */Linux +//zz // (__NR_readdir, old_readdir), // 89 -- superseded +//zz +// _____(__NR_mmap, old_mmap), // 90 + GENXY(__NR_munmap, sys_munmap), // 91 + GENX_(__NR_truncate, sys_truncate), // 92 + GENX_(__NR_ftruncate, sys_ftruncate), // 93 + GENX_(__NR_fchmod, sys_fchmod), // 94 + + LINX_(__NR_fchown, sys_fchown16), // 95 + GENX_(__NR_getpriority, sys_getpriority), // 96 + GENX_(__NR_setpriority, sys_setpriority), // 97 +// GENX_(__NR_profil, sys_ni_syscall), // 98 + GENXY(__NR_statfs, sys_statfs), // 99 + + GENXY(__NR_fstatfs, sys_fstatfs), // 100 +// LINX_(__NR_ioperm, sys_ioperm), // 101 + PLAXY(__NR_socketcall, sys_socketcall), // 102 + LINXY(__NR_syslog, sys_syslog), // 103 + GENXY(__NR_setitimer, sys_setitimer), // 104 + + GENXY(__NR_getitimer, sys_getitimer), // 105 + GENXY(__NR_stat, sys_newstat), // 106 + GENXY(__NR_lstat, sys_newlstat), // 107 + GENXY(__NR_fstat, sys_newfstat), // 108 +//zz // (__NR_olduname, sys_uname), // 109 -- obsolete +//zz +// GENX_(__NR_iopl, sys_iopl), // 110 + LINX_(__NR_vhangup, sys_vhangup), // 111 +// GENX_(__NR_idle, sys_ni_syscall), // 112 +// PLAXY(__NR_vm86old, sys_vm86old), // 113 __NR_syscall... weird + GENXY(__NR_wait4, sys_wait4), // 114 +//zz +//zz // (__NR_swapoff, sys_swapoff), // 115 */Linux + LINXY(__NR_sysinfo, sys_sysinfo), // 116 +// _____(__NR_ipc, sys_ipc), // 117 + GENX_(__NR_fsync, sys_fsync), // 118 + PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux + + PLAX_(__NR_clone, sys_clone), // 120 +//zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) + GENXY(__NR_uname, sys_newuname), // 122 +// PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 +//zz LINXY(__NR_adjtimex, sys_adjtimex), // 124 +//zz + GENXY(__NR_mprotect, sys_mprotect), // 125 + // LINXY(__NR_sigprocmask, sys_sigprocmask), // 126 +//zz // Nb: create_module() was removed 2.4-->2.6 +// GENX_(__NR_create_module, sys_ni_syscall), // 127 + LINX_(__NR_init_module, sys_init_module), // 128 + LINX_(__NR_delete_module, sys_delete_module), // 129 +//zz +//zz // Nb: get_kernel_syms() was removed 2.4-->2.6 +// GENX_(__NR_get_kernel_syms, sys_ni_syscall), // 130 + LINX_(__NR_quotactl, sys_quotactl), // 131 + GENX_(__NR_getpgid, sys_getpgid), // 132 + GENX_(__NR_fchdir, sys_fchdir), // 133 +//zz // (__NR_bdflush, sys_bdflush), // 134 */Linux +//zz +//zz // (__NR_sysfs, sys_sysfs), // 135 SVr4 + LINX_(__NR_personality, sys_personality), // 136 +// GENX_(__NR_afs_syscall, sys_ni_syscall), // 137 + LINX_(__NR_setfsuid, sys_setfsuid16), // 138 + LINX_(__NR_setfsgid, sys_setfsgid16), // 139 + + LINXY(__NR__llseek, sys_llseek), // 140 + GENXY(__NR_getdents, sys_getdents), // 141 + GENX_(__NR__newselect, sys_select), // 142 + GENX_(__NR_flock, sys_flock), // 143 + GENX_(__NR_msync, sys_msync), // 144 + + GENXY(__NR_readv, sys_readv), // 145 + GENX_(__NR_writev, sys_writev), // 146 + GENX_(__NR_getsid, sys_getsid), // 147 + GENX_(__NR_fdatasync, sys_fdatasync), // 148 + LINXY(__NR__sysctl, sys_sysctl), // 149 + + GENX_(__NR_mlock, sys_mlock), // 150 + GENX_(__NR_munlock, sys_munlock), // 151 + GENX_(__NR_mlockall, sys_mlockall), // 152 + LINX_(__NR_munlockall, sys_munlockall), // 153 + LINXY(__NR_sched_setparam, sys_sched_setparam), // 154 + + LINXY(__NR_sched_getparam, sys_sched_getparam), // 155 + LINX_(__NR_sched_setscheduler, sys_sched_setscheduler), // 156 + LINX_(__NR_sched_getscheduler, sys_sched_getscheduler), // 157 + LINX_(__NR_sched_yield, sys_sched_yield), // 158 + LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max),// 159 + + LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min),// 160 +//zz //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 */* + GENXY(__NR_nanosleep, sys_nanosleep), // 162 + GENX_(__NR_mremap, sys_mremap), // 163 + LINX_(__NR_setresuid, sys_setresuid16), // 164 + + LINXY(__NR_getresuid, sys_getresuid16), // 165 +// PLAXY(__NR_vm86, sys_vm86), // 166 x86/Linux-only +// GENX_(__NR_query_module, sys_ni_syscall), // 167 + GENXY(__NR_poll, sys_poll), // 168 +//zz // (__NR_nfsservctl, sys_nfsservctl), // 169 */Linux +//zz + LINX_(__NR_setresgid, sys_setresgid16), // 170 + LINXY(__NR_getresgid, sys_getresgid16), // 171 + LINXY(__NR_prctl, sys_prctl), // 172 + PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 173 + LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 174 + + LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 175 + LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 176 + LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait),// 177 + LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo),// 178 + LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 179 + + GENXY(__NR_pread64, sys_pread64), // 180 + GENX_(__NR_pwrite64, sys_pwrite64), // 181 + LINX_(__NR_chown, sys_chown16), // 182 + GENXY(__NR_getcwd, sys_getcwd), // 183 + LINXY(__NR_capget, sys_capget), // 184 + + LINX_(__NR_capset, sys_capset), // 185 + GENXY(__NR_sigaltstack, sys_sigaltstack), // 186 + LINXY(__NR_sendfile, sys_sendfile), // 187 +// GENXY(__NR_getpmsg, sys_getpmsg), // 188 +// GENX_(__NR_putpmsg, sys_putpmsg), // 189 + + // Nb: we treat vfork as fork + GENX_(__NR_vfork, sys_fork), // 190 + GENXY(__NR_ugetrlimit, sys_getrlimit), // 191 + PLAX_(__NR_mmap2, sys_mmap2), // 192 + GENX_(__NR_truncate64, sys_truncate64), // 193 + GENX_(__NR_ftruncate64, sys_ftruncate64), // 194 + + PLAXY(__NR_stat64, sys_stat64), // 195 + PLAXY(__NR_lstat64, sys_lstat64), // 196 + PLAXY(__NR_fstat64, sys_fstat64), // 197 + GENX_(__NR_lchown32, sys_lchown), // 198 + GENX_(__NR_getuid32, sys_getuid), // 199 + + GENX_(__NR_getgid32, sys_getgid), // 200 + GENX_(__NR_geteuid32, sys_geteuid), // 201 + GENX_(__NR_getegid32, sys_getegid), // 202 + GENX_(__NR_setreuid32, sys_setreuid), // 203 + GENX_(__NR_setregid32, sys_setregid), // 204 + + GENXY(__NR_getgroups32, sys_getgroups), // 205 + GENX_(__NR_setgroups32, sys_setgroups), // 206 + GENX_(__NR_fchown32, sys_fchown), // 207 + LINX_(__NR_setresuid32, sys_setresuid), // 208 + LINXY(__NR_getresuid32, sys_getresuid), // 209 + + LINX_(__NR_setresgid32, sys_setresgid), // 210 + LINXY(__NR_getresgid32, sys_getresgid), // 211 + GENX_(__NR_chown32, sys_chown), // 212 + GENX_(__NR_setuid32, sys_setuid), // 213 + GENX_(__NR_setgid32, sys_setgid), // 214 + + LINX_(__NR_setfsuid32, sys_setfsuid), // 215 + LINX_(__NR_setfsgid32, sys_setfsgid), // 216 +//zz // (__NR_pivot_root, sys_pivot_root), // 217 */Linux + GENXY(__NR_mincore, sys_mincore), // 218 + GENX_(__NR_madvise, sys_madvise), // 219 + + GENXY(__NR_getdents64, sys_getdents64), // 220 + LINXY(__NR_fcntl64, sys_fcntl64), // 221 +// GENX_(222, sys_ni_syscall), // 222 +// PLAXY(223, sys_syscall223), // 223 // sys_bproc? + LINX_(__NR_gettid, sys_gettid), // 224 + + LINX_(__NR_readahead, sys_readahead), // 225 */Linux + LINX_(__NR_setxattr, sys_setxattr), // 226 + LINX_(__NR_lsetxattr, sys_lsetxattr), // 227 + LINX_(__NR_fsetxattr, sys_fsetxattr), // 228 + LINXY(__NR_getxattr, sys_getxattr), // 229 + + LINXY(__NR_lgetxattr, sys_lgetxattr), // 230 + LINXY(__NR_fgetxattr, sys_fgetxattr), // 231 + LINXY(__NR_listxattr, sys_listxattr), // 232 + LINXY(__NR_llistxattr, sys_llistxattr), // 233 + LINXY(__NR_flistxattr, sys_flistxattr), // 234 + + LINX_(__NR_removexattr, sys_removexattr), // 235 + LINX_(__NR_lremovexattr, sys_lremovexattr), // 236 + LINX_(__NR_fremovexattr, sys_fremovexattr), // 237 + LINXY(__NR_tkill, sys_tkill), // 238 */Linux + LINXY(__NR_sendfile64, sys_sendfile64), // 239 + + LINXY(__NR_futex, sys_futex), // 240 + LINX_(__NR_sched_setaffinity, sys_sched_setaffinity), // 241 + LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 242 +// PLAX_(__NR_set_thread_area, sys_set_thread_area), // 243 +// PLAX_(__NR_get_thread_area, sys_get_thread_area), // 244 + + LINXY(__NR_io_setup, sys_io_setup), // 245 + LINX_(__NR_io_destroy, sys_io_destroy), // 246 + LINXY(__NR_io_getevents, sys_io_getevents), // 247 + LINX_(__NR_io_submit, sys_io_submit), // 248 + LINXY(__NR_io_cancel, sys_io_cancel), // 249 + +// LINX_(__NR_fadvise64, sys_fadvise64), // 250 */(Linux?) + GENX_(251, sys_ni_syscall), // 251 + LINX_(__NR_exit_group, sys_exit_group), // 252 +// GENXY(__NR_lookup_dcookie, sys_lookup_dcookie), // 253 + LINXY(__NR_epoll_create, sys_epoll_create), // 254 + + LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 255 + LINXY(__NR_epoll_wait, sys_epoll_wait), // 256 +//zz // (__NR_remap_file_pages, sys_remap_file_pages), // 257 */Linux + LINX_(__NR_set_tid_address, sys_set_tid_address), // 258 + LINXY(__NR_timer_create, sys_timer_create), // 259 + + LINXY(__NR_timer_settime, sys_timer_settime), // (timer_create+1) + LINXY(__NR_timer_gettime, sys_timer_gettime), // (timer_create+2) + LINX_(__NR_timer_getoverrun, sys_timer_getoverrun),//(timer_create+3) + LINX_(__NR_timer_delete, sys_timer_delete), // (timer_create+4) + LINX_(__NR_clock_settime, sys_clock_settime), // (timer_create+5) + + LINXY(__NR_clock_gettime, sys_clock_gettime), // (timer_create+6) + LINXY(__NR_clock_getres, sys_clock_getres), // (timer_create+7) + LINXY(__NR_clock_nanosleep, sys_clock_nanosleep),// (timer_create+8) */* + GENXY(__NR_statfs64, sys_statfs64), // 268 + GENXY(__NR_fstatfs64, sys_fstatfs64), // 269 + + LINX_(__NR_tgkill, sys_tgkill), // 270 */Linux + GENX_(__NR_utimes, sys_utimes), // 271 +// LINX_(__NR_fadvise64_64, sys_fadvise64_64), // 272 */(Linux?) + GENX_(__NR_vserver, sys_ni_syscall), // 273 + LINX_(__NR_mbind, sys_mbind), // 274 ?/? + + LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 275 ?/? + LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 276 ?/? + LINXY(__NR_mq_open, sys_mq_open), // 277 + LINX_(__NR_mq_unlink, sys_mq_unlink), // (mq_open+1) + LINX_(__NR_mq_timedsend, sys_mq_timedsend), // (mq_open+2) + + LINXY(__NR_mq_timedreceive, sys_mq_timedreceive),// (mq_open+3) + LINX_(__NR_mq_notify, sys_mq_notify), // (mq_open+4) + LINXY(__NR_mq_getsetattr, sys_mq_getsetattr), // (mq_open+5) + LINXY(__NR_waitid, sys_waitid), // 280 + + PLAXY(__NR_socket, sys_socket), // 281 + PLAX_(__NR_bind, sys_bind), // 282 + PLAX_(__NR_connect, sys_connect), // 283 + PLAX_(__NR_listen, sys_listen), // 284 + PLAXY(__NR_accept, sys_accept), // 285 + PLAXY(__NR_getsockname, sys_getsockname), // 286 + PLAXY(__NR_getpeername, sys_getpeername), // 287 + PLAXY(__NR_socketpair, sys_socketpair), // 288 + PLAX_(__NR_send, sys_send), + PLAX_(__NR_sendto, sys_sendto), // 290 + PLAXY(__NR_recv, sys_recv), + PLAXY(__NR_recvfrom, sys_recvfrom), // 292 + PLAX_(__NR_shutdown, sys_shutdown), // 293 + PLAX_(__NR_setsockopt, sys_setsockopt), // 294 + PLAXY(__NR_getsockopt, sys_getsockopt), // 295 + PLAX_(__NR_sendmsg, sys_sendmsg), // 296 + PLAXY(__NR_recvmsg, sys_recvmsg), // 297 + PLAX_(__NR_semop, sys_semop), // 298 + PLAX_(__NR_semget, sys_semget), // 299 + PLAXY(__NR_semctl, sys_semctl), // 300 + PLAX_(__NR_msgget, sys_msgget), + PLAX_(__NR_msgsnd, sys_msgsnd), + PLAXY(__NR_msgrcv, sys_msgrcv), + PLAXY(__NR_msgctl, sys_msgctl), // 304 + PLAX_(__NR_semtimedop, sys_semtimedop), // 312 + + LINX_(__NR_add_key, sys_add_key), // 286 + LINX_(__NR_request_key, sys_request_key), // 287 + LINXY(__NR_keyctl, sys_keyctl), // not 288... +// LINX_(__NR_ioprio_set, sys_ioprio_set), // 289 + +// LINX_(__NR_ioprio_get, sys_ioprio_get), // 290 + LINX_(__NR_inotify_init, sys_inotify_init), // 291 + LINX_(__NR_inotify_add_watch, sys_inotify_add_watch), // 292 + LINX_(__NR_inotify_rm_watch, sys_inotify_rm_watch), // 293 +// LINX_(__NR_migrate_pages, sys_migrate_pages), // 294 + + LINXY(__NR_openat, sys_openat), // 295 + LINX_(__NR_mkdirat, sys_mkdirat), // 296 + LINX_(__NR_mknodat, sys_mknodat), // 297 + LINX_(__NR_fchownat, sys_fchownat), // 298 + LINX_(__NR_futimesat, sys_futimesat), // 326 on arm + + PLAXY(__NR_fstatat64, sys_fstatat64), // 300 + LINX_(__NR_unlinkat, sys_unlinkat), // 301 + LINX_(__NR_renameat, sys_renameat), // 302 + LINX_(__NR_linkat, sys_linkat), // 303 + LINX_(__NR_symlinkat, sys_symlinkat), // 304 + + LINX_(__NR_readlinkat, sys_readlinkat), // + LINX_(__NR_fchmodat, sys_fchmodat), // + LINX_(__NR_faccessat, sys_faccessat), // + PLAXY(__NR_shmat, wrap_sys_shmat), //305 + PLAXY(__NR_shmdt, sys_shmdt), //306 + PLAX_(__NR_shmget, sys_shmget), //307 + PLAXY(__NR_shmctl, sys_shmctl), // 308 +// LINX_(__NR_pselect6, sys_pselect6), // + +// LINX_(__NR_unshare, sys_unshare), // 310 + LINX_(__NR_set_robust_list, sys_set_robust_list), // 311 + LINXY(__NR_get_robust_list, sys_get_robust_list), // 312 +// LINX_(__NR_splice, sys_ni_syscall), // 313 +// LINX_(__NR_sync_file_range, sys_sync_file_range), // 314 + +// LINX_(__NR_tee, sys_ni_syscall), // 315 +// LINX_(__NR_vmsplice, sys_ni_syscall), // 316 +// LINX_(__NR_move_pages, sys_ni_syscall), // 317 +// LINX_(__NR_getcpu, sys_ni_syscall), // 318 +// LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 319 + + LINX_(__NR_utimensat, sys_utimensat), // 320 + LINXY(__NR_signalfd, sys_signalfd), // 321 + LINXY(__NR_timerfd_create, sys_timerfd_create), // 322 + LINX_(__NR_eventfd, sys_eventfd), // 323 +// LINX_(__NR_fallocate, sys_ni_syscall), // 324 + LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 325 + LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 326 + + /////////////// + + // JRS 2010-Jan-03: I believe that all the numbers listed + // in comments in the table prior to this point (eg "// 326", + // etc) are bogus since it looks to me like they are copied + // verbatim from syswrap-x86-linux.c and they certainly do not + // correspond to what's in include/vki/vki-scnums-arm-linux.h. + // From here onwards, please ensure the numbers are correct. + + LINX_(__NR_pselect6, sys_pselect6), // 335 + LINXY(__NR_ppoll, sys_ppoll), // 336 + + LINXY(__NR_signalfd4, sys_signalfd4), // 355 + LINX_(__NR_eventfd2, sys_eventfd2), // 356 + + LINXY(__NR_pipe2, sys_pipe2), // 359 + LINXY(__NR_inotify_init1, sys_inotify_init1) // 360 +}; + + +/* These are not in the main table because there indexes are not small + integers, but rather values close to one million. So their + inclusion would force the main table to be huge (about 8 MB). */ + +static SyscallTableEntry ste___ARM_set_tls + = { WRAPPER_PRE_NAME(arm_linux,sys_set_tls), NULL }; + +static SyscallTableEntry ste___ARM_cacheflush + = { WRAPPER_PRE_NAME(arm_linux,sys_cacheflush), NULL }; + +SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno ) +{ + const UInt syscall_main_table_size + = sizeof(syscall_main_table) / sizeof(syscall_main_table[0]); + + /* Is it in the contiguous initial section of the table? */ + if (sysno < syscall_main_table_size) { + SyscallTableEntry* sys = &syscall_main_table[sysno]; + if (sys->before == NULL) + return NULL; /* no entry */ + else + return sys; + } + + /* Check if it's one of the out-of-line entries. */ + switch (sysno) { + case __NR_ARM_set_tls: return &ste___ARM_set_tls; + case __NR_ARM_cacheflush: return &ste___ARM_cacheflush; + default: break; + } + + /* Can't find a wrapper */ + return NULL; +} + +#endif // defined(VGP_arm_linux) + +/*--------------------------------------------------------------------*/ +/*--- end syswrap-arm-linux.c ---*/ +/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_syswrap/syswrap-darwin.c b/coregrind/m_syswrap/syswrap-darwin.c index 86c974f..76ad867 100644 --- a/coregrind/m_syswrap/syswrap-darwin.c +++ b/coregrind/m_syswrap/syswrap-darwin.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Apple Inc. + Copyright (C) 2005-2010 Apple Inc. Greg Parker gparker@apple.com This program is free software; you can redistribute it and/or @@ -66,7 +66,6 @@ #include #include #include -#include /* struct kauth_filesec */ /* --- !!! --- EXTERNAL HEADERS end --- !!! --- */ #define msgh_request_port msgh_remote_port @@ -1240,7 +1239,9 @@ PRE(futimes) { PRINT("futimes ( %ld, %#lx )", ARG1,ARG2); PRE_REG_READ2(long, "futimes", int, fd, struct timeval *, tvp); - if (ARG2 != 0) { + if (!ML_(fd_allowed)(ARG1, "futimes", tid, False)) { + SET_STATUS_Failure( VKI_EBADF ); + } else if (ARG2 != 0) { PRE_timeval_READ( "futimes(tvp[0])", ARG2 ); PRE_timeval_READ( "futimes(tvp[1])", ARG2+sizeof(struct vki_timeval) ); } @@ -1635,10 +1636,12 @@ PRE(kdebug_trace) { PRINT("kdebug_trace(%ld, %ld, %ld, %ld, %ld, %ld)", ARG1, ARG2, ARG3, ARG4, ARG5, ARG6); + /* + Don't check anything - some clients pass fewer arguments. PRE_REG_READ6(long, "kdebug_trace", int,"code", int,"arg1", int,"arg2", int,"arg3", int,"arg4", int,"arg5"); - // GrP fixme anything else? + */ } @@ -1770,6 +1773,27 @@ PRE(fsetxattr) } +PRE(removexattr) +{ + PRINT( "removexattr ( %#lx(%s), %#lx(%s), %ld )", + ARG1, (HChar*)ARG1, ARG2, (HChar*)ARG2, ARG3 ); + PRE_REG_READ3(int, "removexattr", + const char*, "path", char*, "attrname", int, "options"); + PRE_MEM_RASCIIZ( "removexattr(path)", ARG1 ); + PRE_MEM_RASCIIZ( "removexattr(attrname)", ARG2 ); +} + + +PRE(fremovexattr) +{ + PRINT( "fremovexattr ( %ld, %#lx(%s), %ld )", + ARG1, ARG2, (HChar*)ARG2, ARG3 ); + PRE_REG_READ3(int, "fremovexattr", + int, "fd", char*, "attrname", int, "options"); + PRE_MEM_RASCIIZ( "removexattr(attrname)", ARG2 ); +} + + PRE(listxattr) { PRINT( "listxattr ( %#lx(%s), %#lx, %lu, %ld )", @@ -2008,7 +2032,7 @@ PRE(fchmod_extended) chmod_extended is broken in the same way. */ PRINT("fchmod_extended ( %ld, %ld, %ld, %ld, %#lx )", ARG1, ARG2, ARG3, ARG4, ARG5); - PRE_REG_READ5(long, "fchmod", + PRE_REG_READ5(long, "fchmod_extended", unsigned int, fildes, uid_t, uid, gid_t, gid, @@ -2017,8 +2041,10 @@ PRE(fchmod_extended) /* DDD: relative to the xnu sources (kauth_copyinfilesec), this is just way wrong. [The trouble is with the size, which depends on a non-trival kernel computation] */ - PRE_MEM_READ( "fchmod_extended(xsecurity)", ARG5, - sizeof(struct kauth_filesec) ); + if (ARG5) { + PRE_MEM_READ( "fchmod_extended(xsecurity)", ARG5, + sizeof(struct vki_kauth_filesec) ); + } } PRE(chmod_extended) @@ -2027,7 +2053,7 @@ PRE(chmod_extended) fchmod_extended is broken in the same way. */ PRINT("chmod_extended ( %#lx(%s), %ld, %ld, %ld, %#lx )", ARG1, ARG1 ? (HChar*)ARG1 : "(null)", ARG2, ARG3, ARG4, ARG5); - PRE_REG_READ5(long, "chmod", + PRE_REG_READ5(long, "chmod_extended", unsigned int, fildes, uid_t, uid, gid_t, gid, @@ -2037,10 +2063,34 @@ PRE(chmod_extended) /* DDD: relative to the xnu sources (kauth_copyinfilesec), this is just way wrong. [The trouble is with the size, which depends on a non-trival kernel computation] */ - PRE_MEM_READ( "chmod_extended(xsecurity)", ARG5, - sizeof(struct kauth_filesec) ); + if (ARG5) { + PRE_MEM_READ( "chmod_extended(xsecurity)", ARG5, + sizeof(struct vki_kauth_filesec) ); + } } +PRE(open_extended) +{ + /* DDD: Note: this is not really correct. Handling of + {,f}chmod_extended is broken in the same way. */ + PRINT("open_extended ( %#lx(%s), 0x%lx, %ld, %ld, %ld, %#lx )", + ARG1, ARG1 ? (HChar*)ARG1 : "(null)", + ARG2, ARG3, ARG4, ARG5, ARG6); + PRE_REG_READ6(long, "open_extended", + char*, path, + int, flags, + uid_t, uid, + gid_t, gid, + vki_mode_t, mode, + void* /*really,user_addr_t*/, xsecurity); + PRE_MEM_RASCIIZ("open_extended(path)", ARG1); + /* DDD: relative to the xnu sources (kauth_copyinfilesec), this + is just way wrong. [The trouble is with the size, which depends on a + non-trival kernel computation] */ + if (ARG6) + PRE_MEM_READ( "open_extended(xsecurity)", ARG6, + sizeof(struct vki_kauth_filesec) ); +} // This is a ridiculous syscall. Specifically, the 'entries' argument points // to a buffer that contains one or more 'accessx_descriptor' structs followed @@ -2241,6 +2291,9 @@ static void scan_attrlist(ThreadId tid, struct vki_attrlist *attrList, } attrspec; static const attrspec commonattr[] = { // This order is important. +#if DARWIN_VERS >= DARWIN_10_6 + { ATTR_CMN_RETURNED_ATTRS, sizeof(attribute_set_t) }, +#endif { ATTR_CMN_NAME, -1 }, { ATTR_CMN_DEVID, sizeof(dev_t) }, { ATTR_CMN_FSID, sizeof(fsid_t) }, @@ -2263,8 +2316,14 @@ static void scan_attrlist(ThreadId tid, struct vki_attrlist *attrList, { ATTR_CMN_NAMEDATTRLIST, -1 }, { ATTR_CMN_FLAGS, sizeof(uint32_t) }, { ATTR_CMN_USERACCESS, sizeof(uint32_t) }, + { ATTR_CMN_EXTENDED_SECURITY, -1 }, + { ATTR_CMN_UUID, sizeof(guid_t) }, + { ATTR_CMN_GRPUUID, sizeof(guid_t) }, { ATTR_CMN_FILEID, sizeof(uint64_t) }, { ATTR_CMN_PARENTID, sizeof(uint64_t) }, +#if DARWIN_VERS >= DARWIN_10_6 + { ATTR_CMN_FULLPATH, -1 }, +#endif { 0, 0 } }; static const attrspec volattr[] = { @@ -2288,6 +2347,9 @@ static void scan_attrlist(ThreadId tid, struct vki_attrlist *attrList, { ATTR_VOL_MOUNTEDDEVICE, -1 }, { ATTR_VOL_ENCODINGSUSED, sizeof(uint64_t) }, { ATTR_VOL_CAPABILITIES, sizeof(vol_capabilities_attr_t) }, +#if DARWIN_VERS >= DARWIN_10_6 + { ATTR_VOL_UUID, sizeof(uuid_t) }, +#endif { ATTR_VOL_ATTRIBUTES, sizeof(vol_attributes_attr_t) }, { 0, 0 } }; @@ -2336,6 +2398,16 @@ static void scan_attrlist(ThreadId tid, struct vki_attrlist *attrList, d = attrBuf; dend = d + attrBufSize; +#if DARWIN_VERS >= DARWIN_10_6 + // ATTR_CMN_RETURNED_ATTRS tells us what's really here, if set + if (a[0] & ATTR_CMN_RETURNED_ATTRS) { + // fixme range check this? + a[0] &= ~ATTR_CMN_RETURNED_ATTRS; + fn(tid, d, sizeof(attribute_set_t)); + VG_(memcpy)(a, d, sizeof(a)); + } +#endif + for (g = 0; g < 5; g++) { for (i = 0; attrdefs[g][i].attrBit; i++) { uint32_t bit = attrdefs[g][i].attrBit; @@ -2398,10 +2470,15 @@ PRE(getattrlist) POST(getattrlist) { if (ARG4 > sizeof(vki_uint32_t)) { - // attrBuf is uint32_t bytes written followed by attr data + // attrBuf is uint32_t size followed by attr data vki_uint32_t *sizep = (vki_uint32_t *)ARG3; POST_MEM_WRITE(ARG3, sizeof(vki_uint32_t)); - scan_attrlist(tid, (struct vki_attrlist *)ARG2, sizep+1, *sizep, &get1attr); + if (ARG5 & FSOPT_REPORT_FULLSIZE) { + // *sizep is bytes required for return value, including *sizep + } else { + // *sizep is actual bytes returned, including *sizep + } + scan_attrlist(tid, (struct vki_attrlist *)ARG2, sizep+1, MIN(*sizep, ARG4), &get1attr); } } @@ -2457,9 +2534,50 @@ POST(getdirentriesattr) POST_MEM_WRITE(ARG3, p - (char *)ARG3); - PRINT("got %d records, %d/%lu bytes\n", count, p-(char *)ARG3, ARG4); + PRINT("got %d records, %ld/%lu bytes\n", + count, (Addr)p-(Addr)ARG3, ARG4); +} + + +PRE(fsgetpath) +{ +#if VG_WORDSIZE == 4 + PRINT("fsgetpath(%#lx, %ld, %#lx {%u,%u}, %llu)", + ARG1, ARG2, ARG3, + ((unsigned int *)ARG3)[0], ((unsigned int *)ARG3)[1], + LOHI64(ARG4, ARG5)); + PRE_REG_READ5(ssize_t, "fsgetpath", + void*,"buf", size_t,"bufsize", + fsid_t *,"fsid", + vki_uint32_t, "objid_low32", vki_uint32_t, "objid_high32"); +#else + PRINT("fsgetpath(%#lx, %ld, %#lx {%u,%u}, %lu)", + ARG1, ARG2, ARG3, + ((unsigned int *)ARG3)[0], + ((unsigned int *)ARG3)[1], ARG4); + PRE_REG_READ4(ssize_t, "fsgetpath", + void*,"buf", size_t,"bufsize", + fsid_t *,"fsid", uint64_t,"objid"); +#endif + PRE_MEM_READ("fsgetpath(fsid)", ARG3, sizeof(fsid_t)); + PRE_MEM_WRITE("fsgetpath(buf)", ARG1, ARG2); +} + +POST(fsgetpath) +{ + POST_MEM_WRITE(ARG1, RES); +} + +PRE(audit_session_self) +{ + PRINT("audit_session_self()"); } +POST(audit_session_self) +{ + record_named_port(tid, RES, MACH_PORT_RIGHT_SEND, "audit-session-%p"); + PRINT("audit-session %#lx", RES); +} PRE(exchangedata) { @@ -2556,7 +2674,8 @@ static void pre_argv_envp(Addr a, ThreadId tid, Char* s1, Char* s2) a += sizeof(char*); } } -static SysRes simple_pre_exec_check(const HChar* exe_name) +static SysRes simple_pre_exec_check ( const HChar* exe_name, + Bool trace_this_child ) { Int fd, ret; SysRes res; @@ -2573,7 +2692,7 @@ static SysRes simple_pre_exec_check(const HChar* exe_name) // Check we have execute permissions. We allow setuid executables // to be run only in the case when we are not simulating them, that // is, they to be run natively. - setuid_allowed = VG_(clo_trace_children) ? False : True; + setuid_allowed = trace_this_child ? False : True; ret = VG_(check_executable)(NULL/*&is_setuid*/, (HChar*)exe_name, setuid_allowed); if (0 != ret) { @@ -2590,6 +2709,7 @@ PRE(posix_spawn) Char* launcher_basename = NULL; Int i, j, tot_args; SysRes res; + Bool trace_this_child; /* args: pid_t* pid char* path @@ -2622,15 +2742,19 @@ PRE(posix_spawn) syswrap-generic.c. */ /* Check that the name at least begins in client-accessible storage. */ - if (!VG_(am_is_valid_for_client)( ARG2, 1, VKI_PROT_READ )) { + if (ARG2 == 0 /* obviously bogus */ + || !VG_(am_is_valid_for_client)( ARG2, 1, VKI_PROT_READ )) { SET_STATUS_Failure( VKI_EFAULT ); return; } + // Decide whether or not we want to follow along + trace_this_child = VG_(should_we_trace_this_child)( (HChar*)ARG2 ); + // Do the important checks: it is a file, is executable, permissions are // ok, etc. We allow setuid executables to run only in the case when // we are not simulating them, that is, they to be run natively. - res = simple_pre_exec_check((const HChar*)ARG2); + res = simple_pre_exec_check( (const HChar*)ARG2, trace_this_child ); if (sr_isError(res)) { SET_STATUS_Failure( sr_Err(res) ); return; @@ -2639,7 +2763,7 @@ PRE(posix_spawn) /* If we're tracing the child, and the launcher name looks bogus (possibly because launcher.c couldn't figure it out, see comments therein) then we have no option but to fail. */ - if (VG_(clo_trace_children) + if (trace_this_child && (VG_(name_of_launcher) == NULL || VG_(name_of_launcher)[0] != '/')) { SET_STATUS_Failure( VKI_ECHILD ); /* "No child processes" */ @@ -2651,7 +2775,7 @@ PRE(posix_spawn) // Set up the child's exe path. // - if (VG_(clo_trace_children)) { + if (trace_this_child) { // We want to exec the launcher. Get its pre-remembered path. path = VG_(name_of_launcher); @@ -2685,7 +2809,7 @@ PRE(posix_spawn) VG_(env_remove_valgrind_env_stuff)( envp ); } - if (VG_(clo_trace_children)) { + if (trace_this_child) { // Set VALGRIND_LIB in ARG5 (the environment) VG_(env_setenv)( &envp, VALGRIND_LIB, VG_(libdir)); } @@ -2698,7 +2822,7 @@ PRE(posix_spawn) // except that the first VG_(args_for_valgrind_noexecpass) args // are omitted. // - if (!VG_(clo_trace_children)) { + if (!trace_this_child) { argv = (Char**)ARG4; } else { vg_assert( VG_(args_for_valgrind) ); @@ -3242,6 +3366,9 @@ PRE(auditon) case VKI_A_SETCLASS: case VKI_A_SETPMASK: case VKI_A_SETFSIZE: +#if DARWIN_VERS >= DARWIN_10_6 + case VKI_A_SENDTRIGGER: +#endif // kernel reads data..data+length PRE_MEM_READ("auditon(data)", ARG2, ARG3); break; @@ -3260,6 +3387,9 @@ PRE(auditon) case VKI_A_GETCLASS: case VKI_A_GETPINFO: case VKI_A_GETPINFO_ADDR: +#if DARWIN_VERS >= DARWIN_10_6 + case VKI_A_GETSINFO_ADDR: +#endif // kernel reads and writes data..data+length // GrP fixme be precise about what gets read and written PRE_MEM_READ("auditon(data)", ARG2, ARG3); @@ -3293,6 +3423,9 @@ POST(auditon) case VKI_A_SETCLASS: case VKI_A_SETPMASK: case VKI_A_SETFSIZE: +#if DARWIN_VERS >= DARWIN_10_6 + case VKI_A_SENDTRIGGER: +#endif // kernel reads data..data+length break; @@ -3310,6 +3443,9 @@ POST(auditon) case VKI_A_GETCLASS: case VKI_A_GETPINFO: case VKI_A_GETPINFO_ADDR: +#if DARWIN_VERS >= DARWIN_10_6 + case VKI_A_GETSINFO_ADDR: +#endif // kernel reads and writes data..data+length // GrP fixme be precise about what gets read and written POST_MEM_WRITE(ARG2, ARG3); @@ -3532,6 +3668,57 @@ PRE(sigsuspend) PRE_REG_READ1(int, "sigsuspend", int, sigmask); } + +/* Be careful about the 4th arg, since that is a uint64_t. Hence 64- + and 32-bit wrappers are different. + + ARG5 and ARG6 (buffer, buffersize) specify a buffer start and + length in the usual way. I have seen values NULL, 0 passed in some + cases. I left the calls to PRE_MEM_WRITE/READ unconditional on the + basis that they don't do anything if the length is zero, so it's OK + for the buffer pointer to be NULL in that case (meaning they don't + complain). + + int proc_info(int32_t callnum, int32_t pid, + uint32_t flavor, uint64_t arg, + user_addr_t buffer, int32_t buffersize) +*/ +#if DARWIN_VERS >= DARWIN_10_6 +PRE(proc_info) +{ +#if VG_WORDSIZE == 4 + PRINT("proc_info(%d, %d, %u, %llu, %#lx, %d)", + (Int)ARG1, (Int)ARG2, (UInt)ARG3, LOHI64(ARG4,ARG5), ARG6, (Int)ARG7); + PRE_REG_READ7(int, "proc_info", + int, callnum, int, pid, unsigned int, flavor, + vki_uint32_t, arg_low32, + vki_uint32_t, arg_high32, + void*, buffer, int, buffersize); + PRE_MEM_WRITE("proc_info(buffer)", ARG6, ARG7); +#else + PRINT("proc_info(%d, %d, %u, %llu, %#lx, %d)", + (Int)ARG1, (Int)ARG2, (UInt)ARG3, (ULong)ARG4, ARG5, (Int)ARG6); + PRE_REG_READ6(int, "proc_info", + int, callnum, int, pid, unsigned int, flavor, + unsigned long long int, arg, + void*, buffer, int, buffersize); + PRE_MEM_WRITE("proc_info(buffer)", ARG5, ARG6); +#endif +} + +POST(proc_info) +{ +#if VG_WORDSIZE == 4 + vg_assert(SUCCESS); + POST_MEM_WRITE(ARG6, ARG7); +#else + vg_assert(SUCCESS); + POST_MEM_WRITE(ARG5, ARG6); +#endif +} + +#endif /* DARWIN_VERS >= DARWIN_10_6 */ + /* --------------------------------------------------------------------- aio_* ------------------------------------------------------------------ */ @@ -3953,7 +4140,7 @@ POST(host_page_size) Reply *reply = (Reply *)ARG1; if (!reply->RetCode) { - PRINT("page size %u", reply->out_page_size); + PRINT("page size %llu", (ULong)reply->out_page_size); } else { PRINT("mig return %d", reply->RetCode); } @@ -4378,6 +4565,51 @@ POST(mach_port_get_set_status) } +PRE(mach_port_move_member) +{ +#pragma pack(4) + typedef struct { + mach_msg_header_t Head; + NDR_record_t NDR; + mach_port_name_t member; + mach_port_name_t after; + } Request; +#pragma pack() + + Request *req = (Request *)ARG1; + + PRINT("mach_port_move_member(%s, %s, %s)", + name_for_port(MACH_REMOTE), + name_for_port(req->member), + name_for_port(req->after)); + /* + MACH_ARG(mach_port_move_member.member) = req->member; + MACH_ARG(mach_port_move_member.after) = req->after; + */ + AFTER = POST_FN(mach_port_move_member); +} + +POST(mach_port_move_member) +{ +#pragma pack(4) + typedef struct { + mach_msg_header_t Head; + NDR_record_t NDR; + kern_return_t RetCode; + mach_msg_trailer_t trailer; + } Reply; +#pragma pack() + + Reply *reply = (Reply *)ARG1; + + if (!reply->RetCode) { + // fixme port set tracker? + } else { + PRINT("mig return %d", reply->RetCode); + } +} + + PRE(mach_port_destroy) { #pragma pack(4) @@ -4498,6 +4730,34 @@ POST(mach_port_insert_right) } +PRE(mach_port_extract_right) +{ +#pragma pack(4) + typedef struct { + mach_msg_header_t Head; + NDR_record_t NDR; + mach_port_name_t name; + mach_msg_type_name_t msgt_name; + } Request; +#pragma pack() + + Request *req = (Request *)ARG1; + + PRINT("mach_port_extract_right(%s, %s, %d)", + name_for_port(MACH_REMOTE), + name_for_port(req->name), req->msgt_name); + + AFTER = POST_FN(mach_port_extract_right); + + // fixme port tracker? +} + +POST(mach_port_extract_right) +{ + // fixme import_complex_message handles the returned result, right? +} + + PRE(mach_port_get_attributes) { #pragma pack(4) @@ -4869,9 +5129,9 @@ PRE(vm_allocate) Request *req = (Request *)ARG1; - PRINT("vm_allocate (%s, at %#x, size %d, flags %#x)", + PRINT("vm_allocate (%s, at %#llx, size %lld, flags %#x)", name_for_port(MACH_REMOTE), - req->address, req->size, req->flags); + (ULong)req->address, (ULong)req->size, req->flags); MACH_ARG(vm_allocate.size) = req->size; MACH_ARG(vm_allocate.flags) = req->flags; @@ -4895,7 +5155,7 @@ POST(vm_allocate) if (!reply->RetCode) { if (MACH_REMOTE == vg_task_port) { - PRINT("allocated at %#x", reply->address); + PRINT("allocated at %#llx", (ULong)reply->address); // requesting 0 bytes returns address 0 with no error if (MACH_ARG(vm_allocate.size)) { ML_(notify_core_and_tool_of_mmap)( @@ -4903,7 +5163,8 @@ POST(vm_allocate) VKI_PROT_READ|VKI_PROT_WRITE, VKI_MAP_ANON, -1, 0); } } else { - PRINT("allocated at %#x in remote task %s", reply->address, + PRINT("allocated at %#llx in remote task %s", + (ULong)reply->address, name_for_port(MACH_REMOTE)); } } else { @@ -4925,9 +5186,9 @@ PRE(vm_deallocate) Request *req = (Request *)ARG1; - PRINT("vm_deallocate(%s, at %#x, size %d)", + PRINT("vm_deallocate(%s, at %#llx, size %lld)", name_for_port(MACH_REMOTE), - req->address, req->size); + (ULong)req->address, (ULong)req->size); MACH_ARG(vm_deallocate.address) = req->address; MACH_ARG(vm_deallocate.size) = req->size; @@ -4983,8 +5244,9 @@ PRE(vm_protect) Request *req = (Request *)ARG1; - PRINT("vm_protect(%s, at %#x, size %d, set_max %d, prot %d)", - name_for_port(MACH_REMOTE), req->address, req->size, + PRINT("vm_protect(%s, at %#llx, size %lld, set_max %d, prot %d)", + name_for_port(MACH_REMOTE), + (ULong)req->address, (ULong)req->size, req->set_maximum, req->new_protection); MACH_ARG(vm_protect.address) = req->address; @@ -5042,9 +5304,9 @@ PRE(vm_inherit) Request *req = (Request *)ARG1; - PRINT("vm_inherit(%s, at %#x, size %d, value %d)", + PRINT("vm_inherit(%s, at %#llx, size %lld, value %d)", name_for_port(MACH_REMOTE), - req->address, req->size, + (ULong)req->address, (ULong)req->size, req->new_inheritance); AFTER = POST_FN(vm_inherit); @@ -5086,8 +5348,9 @@ PRE(vm_read) Request *req = (Request *)ARG1; - PRINT("vm_read(from %s at %#x size %u)", - name_for_port(MACH_REMOTE), req->address, req->size); + PRINT("vm_read(from %s at %#llx size %llu)", + name_for_port(MACH_REMOTE), + (ULong)req->address, (ULong)req->size); MACH_ARG(vm_read.addr) = req->address; MACH_ARG(vm_read.size) = req->size; @@ -5178,8 +5441,9 @@ PRE(vm_read_overwrite) Request *req = (Request *)ARG1; - PRINT("vm_read_overwrite(from %s at %#x size %u to %#x)", - name_for_port(MACH_REMOTE), req->address, req->size, req->data); + PRINT("vm_read_overwrite(from %s at %#llx size %llu to %#llx)", + name_for_port(MACH_REMOTE), + (ULong)req->address, (ULong)req->size, (ULong)req->data); MACH_ARG(vm_read_overwrite.addr) = req->address; MACH_ARG(vm_read_overwrite.size) = req->size; @@ -5233,9 +5497,10 @@ PRE(vm_copy) Request *req = (Request *)ARG1; - PRINT("vm_copy(%s, %#x, %d, %#x)", + PRINT("vm_copy(%s, %#llx, %lld, %#llx)", name_for_port(MACH_REMOTE), - req->source_address, req->size, req->dest_address); + (ULong)req->source_address, + (ULong)req->size, (ULong)req->dest_address); MACH_ARG(vm_copy.src) = req->source_address; MACH_ARG(vm_copy.dst) = req->dest_address; @@ -5293,9 +5558,9 @@ PRE(vm_map) Request *req = (Request *)ARG1; // GrP fixme check these - PRINT("vm_map(in %s, at %#x, size %d, from %s ...)", + PRINT("vm_map(in %s, at %#llx, size %lld, from %s ...)", name_for_port(MACH_REMOTE), - req->address, req->size, + (ULong)req->address, (ULong)req->size, name_for_port(req->object.name)); MACH_ARG(vm_map.size) = req->size; @@ -5321,7 +5586,7 @@ POST(vm_map) if (!reply->RetCode) { // GrP fixme check src and dest tasks - PRINT("mapped at %#x", reply->address); + PRINT("mapped at %#llx", (ULong)reply->address); // GrP fixme max prot ML_(notify_core_and_tool_of_mmap)( reply->address, VG_PGROUNDUP(MACH_ARG(vm_map.size)), @@ -5361,13 +5626,14 @@ PRE(vm_remap) mach_port_name_t source_task = req->src_task.name; if (source_task == mach_task_self()) { PRINT("vm_remap(mach_task_self(), " - "to %#x size %d, from mach_task_self() at %#x, ...)", - req->target_address, req->size, req->src_address); + "to %#llx size %lld, from mach_task_self() at %#llx, ...)", + (ULong)req->target_address, + (ULong)req->size, (ULong)req->src_address); } else { - PRINT("vm_remap(mach_task_self(), " - "to %#x size %d, from task %u at %#x, ...)", - req->target_address, req->size, - source_task, req->src_address); + PRINT("vm_remap(mach_task_self(), " + "to %#llx size %lld, from task %u at %#llx, ...)", + (ULong)req->target_address, (ULong)req->size, + source_task, (ULong)req->src_address); } } @@ -5399,7 +5665,7 @@ POST(vm_remap) // GrP fixme check src and dest tasks UInt prot = reply->cur_protection & reply->max_protection; // GrP fixme max prot - PRINT("mapped at %#x", reply->target_address); + PRINT("mapped at %#llx", (ULong)reply->target_address); ML_(notify_core_and_tool_of_mmap)( reply->target_address, VG_PGROUNDUP(MACH_ARG(vm_remap.size)), prot, VKI_MAP_SHARED, -1, 0); @@ -5471,9 +5737,9 @@ PRE(vm_purgable_control) Request *req = (Request *)ARG1; - PRINT("vm_purgable_control(%s, %#x, %d, %d)", + PRINT("vm_purgable_control(%s, %#llx, %d, %d)", name_for_port(MACH_REMOTE), - req->address, req->control, req->state); + (ULong)req->address, req->control, req->state); // GrP fixme verify address? @@ -6086,6 +6352,7 @@ POST(bsdthread_create) // GrP fixme semaphore destroy needed when thread creation fails // GrP fixme probably other cleanup too + // GrP fixme spinlocks might be good enough? // DDD: I'm not at all sure this is the right spot for this. It probably // should be in pthread_hijack instead, just before the call to @@ -6204,10 +6471,6 @@ PRE(thread_get_state) } -POST(thread_policy) -{ -} - PRE(thread_policy) { mach_msg_header_t *mh = (mach_msg_header_t *)ARG1; @@ -6222,6 +6485,24 @@ PRE(thread_policy) AFTER = POST_FN(thread_policy); } +POST(thread_policy) +{ +} + + +PRE(thread_policy_set) +{ + mach_msg_header_t *mh = (mach_msg_header_t *)ARG1; + + PRINT("thread_policy_set(%s, ...)", name_for_port(mh->msgh_request_port)); + + AFTER = POST_FN(thread_policy_set); +} + +POST(thread_policy_set) +{ +} + PRE(thread_info) { @@ -6449,12 +6730,18 @@ PRE(mach_msg_task) case 3211: CALL_PRE(mach_port_get_set_status); return; + case 3212: + CALL_PRE(mach_port_move_member); + return; case 3213: CALL_PRE(mach_port_request_notification); return; case 3214: CALL_PRE(mach_port_insert_right); return; + case 3215: + CALL_PRE(mach_port_extract_right); + return; case 3217: CALL_PRE(mach_port_get_attributes); return; @@ -6596,6 +6883,9 @@ PRE(mach_msg_thread) case 3616: CALL_PRE(thread_policy); return; + case 3617: + CALL_PRE(thread_policy_set); + return; default: // unknown message to a thread VG_(printf)("UNKNOWN thread message [id %d, to %s, reply 0x%x]\n", @@ -6760,7 +7050,7 @@ POST(mach_msg) POST(mach_msg_unhandled) { - ML_(sync_mappings)("after", "mach_msg_unhandled", 0); + ML_(sync_mappings)("after", "mach_msg_receive (unhandled)", 0); } @@ -6902,9 +7192,9 @@ PRE(semaphore_timedwait_signal) PRE(__semwait_signal) { - /* args: int cond_sem, int mutex_sem, - int timeout, int relative, - time_t tv_sec, time_t tv_nsec */ + /* 10.5 args: int cond_sem, int mutex_sem, + int timeout, int relative, + time_t tv_sec, time_t tv_nsec */ PRINT("__semwait_signal(wait %s, signal %s, %ld, %ld, %lds:%ldns)", name_for_port(ARG1), name_for_port(ARG2), ARG3, ARG4, ARG5, ARG6); PRE_REG_READ6(long, "__semwait_signal", @@ -6914,7 +7204,33 @@ PRE(__semwait_signal) *flags |= SfMayBlock; } - +// GrP provided this alternative version for 10.6, but NjN +// reckons the 10.5 is is still correct for 10.6. So, retaining +// Greg's version as a comment just in case we need it later. +//PRE(__semwait_signal) +//{ +// /* 10.5 args: int cond_sem, int mutex_sem, +// int timeout, int relative, +// const timespec *ts */ +// PRINT("__semwait_signal(wait %s, signal %s, %ld, %ld, %#lx)", +// name_for_port(ARG1), name_for_port(ARG2), ARG3, ARG4, ARG5); +// PRE_REG_READ5(int, "__semwait_signal", +// int,cond_sem, int,mutex_sem, +// int,timeout, int,relative, +// const struct vki_timespec *,ts); +// +// if (ARG5) PRE_MEM_READ ("__semwait_signal(ts)", +// ARG5, sizeof(struct vki_timespec)); +// +// *flags |= SfMayBlock; +//} + + +PRE(__thread_selfid) +{ + PRINT("__thread_selfid ()"); + PRE_REG_READ0(vki_uint64_t, "__thread_selfid"); +} PRE(task_for_pid) { @@ -6971,10 +7287,10 @@ POST(mach_timebase_info) PRE(mach_wait_until) { #if VG_WORDSIZE == 8 - PRINT("mach_wait_until(%llu)", ARG1); + PRINT("mach_wait_until(%lu)", ARG1); PRE_REG_READ1(long, "mach_wait_until", unsigned long long,"deadline"); -#else +#else PRINT("mach_wait_until(%llu)", LOHI64(ARG1, ARG2)); PRE_REG_READ2(long, "mach_wait_until", int,"deadline_hi", int,"deadline_lo"); @@ -7015,7 +7331,7 @@ POST(mk_timer_destroy) PRE(mk_timer_arm) { #if VG_WORDSIZE == 8 - PRINT("mk_timer_arm(%s, %llu)", name_for_port(ARG1), ARG2); + PRINT("mk_timer_arm(%s, %lu)", name_for_port(ARG1), ARG2); PRE_REG_READ2(long, "mk_timer_arm", mach_port_t,"name", unsigned long,"expire_time"); #else @@ -7338,7 +7654,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { MACXY(__NR_ioctl, ioctl), // _____(__NR_reboot), // _____(__NR_revoke), -// _____(__NR_symlink), + GENX_(__NR_symlink, sys_symlink), // 57 GENX_(__NR_readlink, sys_readlink), GENX_(__NR_execve, sys_execve), GENX_(__NR_umask, sys_umask), // 60 @@ -7468,7 +7784,11 @@ const SyscallTableEntry ML_(syscall_table)[] = { MACX_(__NR_sigreturn, sigreturn), // _____(__NR_chud), _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(186)), // ??? +#if DARWIN_VERS >= DARWIN_10_6 +// _____(__NR_fdatasync), +#else _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(187)), // ??? +#endif GENXY(__NR_stat, sys_newstat), GENXY(__NR_fstat, sys_newfstat), GENXY(__NR_lstat, sys_newlstat), @@ -7495,8 +7815,13 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR_ATPgetreq), // _____(__NR_ATPgetrsp), _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(213)), // Reserved for AppleTalk +#if DARWIN_VERS >= DARWIN_10_6 + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(214)), // old kqueue_from_portset_np + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(215)), // old kqueue_portset_np +#else // _____(__NR_kqueue_from_portset_np), // _____(__NR_kqueue_portset_np), +#endif // _____(__NR_mkcomplex), // _____(__NR_statv), // _____(__NR_lstatv), @@ -7509,8 +7834,13 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR_searchfs), GENX_(__NR_delete, sys_unlink), // _____(__NR_copyfile), +#if DARWIN_VERS >= DARWIN_10_6 +// _____(__NR_fgetattrlist), +// _____(__NR_fsetattrlist), +#else _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(228)), // ?? _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(229)), // ?? +#endif GENXY(__NR_poll, sys_poll), MACX_(__NR_watchevent, watchevent), MACXY(__NR_waitevent, waitevent), @@ -7519,14 +7849,18 @@ const SyscallTableEntry ML_(syscall_table)[] = { MACXY(__NR_fgetxattr, fgetxattr), MACX_(__NR_setxattr, setxattr), MACX_(__NR_fsetxattr, fsetxattr), -// _____(__NR_removexattr), -// _____(__NR_fremovexattr), + MACX_(__NR_removexattr, removexattr), + MACX_(__NR_fremovexattr, fremovexattr), MACXY(__NR_listxattr, listxattr), // 240 MACXY(__NR_flistxattr, flistxattr), MACXY(__NR_fsctl, fsctl), MACX_(__NR_initgroups, initgroups), MACXY(__NR_posix_spawn, posix_spawn), +#if DARWIN_VERS >= DARWIN_10_6 +// _____(__NR_ffsctl), +#else _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(245)), // ??? +#endif _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(246)), // ??? // _____(__NR_nfsclnt), // _____(__NR_fhopen), @@ -7558,7 +7892,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR_sem_getvalue), MACXY(__NR_sem_init, sem_init), MACX_(__NR_sem_destroy, sem_destroy), -// _____(__NR_open_extended), + MACX_(__NR_open_extended, open_extended), // 277 // _____(__NR_umask_extended), MACXY(__NR_stat_extended, stat_extended), MACXY(__NR_lstat_extended, lstat_extended), // 280 @@ -7577,23 +7911,27 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR_identitysvc), // _____(__NR_shared_region_check_np), // _____(__NR_shared_region_map_np), +#if DARWIN_VERS >= DARWIN_10_6 +// _____(__NR_vm_pressure_monitor), +#else _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(296)), // old load_shared_file +#endif _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(297)), // old reset_shared_file _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(298)), // old new_system_shared_regions _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(299)), // old shared_region_map_file_np _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(300)), // old shared_region_make_private_np -// _____(__NR___pthread_mutex_destroy), -// _____(__NR___pthread_mutex_init), -// _____(__NR___pthread_mutex_lock), -// _____(__NR___pthread_mutex_trylock), -// _____(__NR___pthread_mutex_unlock), -// _____(__NR___pthread_cond_init), -// _____(__NR___pthread_cond_destroy), -// _____(__NR___pthread_cond_broadcast), -// _____(__NR___pthread_cond_signal), + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(301)), // ??? + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(302)), // ??? + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(303)), // ??? + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(304)), // ??? + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(305)), // ??? + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(306)), // ??? + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(307)), // ??? + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(308)), // ??? + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(309)), // ??? // _____(__NR_getsid), // _____(__NR_settid_with_pid), -// _____(__NR___pthread_cond_timedwait), + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(312)), // ??? // _____(__NR_aio_fsync), MACXY(__NR_aio_return, aio_return), MACX_(__NR_aio_suspend, aio_suspend), @@ -7602,7 +7940,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { MACXY(__NR_aio_read, aio_read), MACX_(__NR_aio_write, aio_write), // _____(__NR_lio_listio), // 320 -// _____(__NR___pthread_cond_wait), + _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(321)), // ??? // _____(__NR_iopolicysys), _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(323)), // ??? // _____(__NR_mlockall), @@ -7617,7 +7955,9 @@ const SyscallTableEntry ML_(syscall_table)[] = { MACX_(__NR___pthread_canceled, __pthread_canceled), MACX_(__NR___semwait_signal, __semwait_signal), _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(335)), // old utrace -// _____(__NR_proc_info), +#if DARWIN_VERS >= DARWIN_10_6 + MACXY(__NR_proc_info, proc_info), // 336 +#endif MACXY(__NR_sendfile, sendfile), MACXY(__NR_stat64, stat64), MACXY(__NR_fstat64, fstat64), @@ -7645,15 +7985,23 @@ const SyscallTableEntry ML_(syscall_table)[] = { MACX_(__NR_bsdthread_terminate, bsdthread_terminate), MACXY(__NR_kqueue, kqueue), MACXY(__NR_kevent, kevent), -// _____(__NR_lchown), + GENX_(__NR_lchown, sys_lchown), // _____(__NR_stack_snapshot), MACX_(__NR_bsdthread_register, bsdthread_register), MACX_(__NR_workq_open, workq_open), MACXY(__NR_workq_ops, workq_ops), +#if DARWIN_VERS >= DARWIN_10_6 +// _____(__NR_kevent64), +#else _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(369)), // ??? +#endif _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(370)), // ??? _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(371)), // ??? +#if DARWIN_VERS >= DARWIN_10_6 + MACX_(__NR___thread_selfid, __thread_selfid), +#else _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(372)), // ??? +#endif _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(373)), // ??? _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(374)), // ??? _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(375)), // ??? @@ -7709,6 +8057,12 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR___mac_mount), // _____(__NR___mac_get_mount), // _____(__NR___mac_getfsstat), +#if DARWIN_VERS >= DARWIN_10_6 + MACXY(__NR_fsgetpath, fsgetpath), + MACXY(__NR_audit_session_self, audit_session_self), +// _____(__NR_audit_session_join), +#endif + // _____(__NR_MAXSYSCALL) MACX_(__NR_DARWIN_FAKE_SIGRETURN, FAKE_SIGRETURN) }; diff --git a/coregrind/m_syswrap/syswrap-generic.c b/coregrind/m_syswrap/syswrap-generic.c index f6c0a46..1dc905b 100644 --- a/coregrind/m_syswrap/syswrap-generic.c +++ b/coregrind/m_syswrap/syswrap-generic.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -62,6 +62,8 @@ #include "priv_types_n_macros.h" #include "priv_syswrap-generic.h" +#include "config.h" + /* Returns True iff address range is something the client can plausibly mess with: all of it is either already belongs to the @@ -425,6 +427,9 @@ SysRes do_mremap( Addr old_addr, SizeT old_len, /* that failed. Look elsewhere. */ advised = VG_(am_get_advisory_client_simple)( 0, new_len, &ok ); if (ok) { + Bool oldR = old_seg->hasR; + Bool oldW = old_seg->hasW; + Bool oldX = old_seg->hasX; /* assert new area does not overlap old */ vg_assert(advised+new_len-1 < old_addr || advised > old_addr+old_len-1); @@ -435,8 +440,7 @@ SysRes do_mremap( Addr old_addr, SizeT old_len, MIN_SIZET(old_len,new_len) ); if (new_len > old_len) VG_TRACK( new_mem_mmap, advised+old_len, new_len-old_len, - old_seg->hasR, old_seg->hasW, old_seg->hasX, - 0/*di_handle*/ ); + oldR, oldW, oldX, 0/*di_handle*/ ); VG_TRACK(die_mem_munmap, old_addr, old_len); if (d) { VG_(discard_translations)( old_addr, old_len, "do_remap(4)" ); @@ -1715,11 +1719,18 @@ UInt get_shm_size ( Int shmid ) #ifdef __NR_shmctl # ifdef VKI_IPC_64 struct vki_shmid64_ds buf; - SysRes __res = VG_(do_syscall3)(__NR_shmctl, shmid, VKI_IPC_STAT, (UWord)&buf); -# else +# ifdef VGP_amd64_linux + /* See bug 222545 comment 7 */ + SysRes __res = VG_(do_syscall3)(__NR_shmctl, shmid, + VKI_IPC_STAT, (UWord)&buf); +# else + SysRes __res = VG_(do_syscall3)(__NR_shmctl, shmid, + VKI_IPC_STAT|VKI_IPC_64, (UWord)&buf); +# endif +# else /* !def VKI_IPC_64 */ struct vki_shmid_ds buf; SysRes __res = VG_(do_syscall3)(__NR_shmctl, shmid, VKI_IPC_STAT, (UWord)&buf); -# endif +# endif /* def VKI_IPC_64 */ #else struct vki_shmid_ds buf; SysRes __res = VG_(do_syscall5)(__NR_ipc, 24 /* IPCOP_shmctl */, shmid, @@ -1740,9 +1751,26 @@ ML_(generic_PRE_sys_shmat) ( ThreadId tid, UWord tmp; Bool ok; if (arg1 == 0) { + /* arm-linux only: work around the fact that + VG_(am_get_advisory_client_simple) produces something that is + VKI_PAGE_SIZE aligned, whereas what we want is something + VKI_SHMLBA aligned, and VKI_SHMLBA >= VKI_PAGE_SIZE. Hence + increase the request size by VKI_SHMLBA - VKI_PAGE_SIZE and + then round the result up to the next VKI_SHMLBA boundary. + See bug 222545 comment 15. So far, arm-linux is the only + platform where this is known to be necessary. */ + vg_assert(VKI_SHMLBA >= VKI_PAGE_SIZE); + if (VKI_SHMLBA > VKI_PAGE_SIZE) { + segmentSize += VKI_SHMLBA - VKI_PAGE_SIZE; + } tmp = VG_(am_get_advisory_client_simple)(0, segmentSize, &ok); - if (ok) - arg1 = tmp; + if (ok) { + if (VKI_SHMLBA > VKI_PAGE_SIZE) { + arg1 = VG_ROUNDUP(tmp, VKI_SHMLBA); + } else { + arg1 = tmp; + } + } } else if (!ML_(valid_client_addr)(arg1, segmentSize, tid, "shmat")) arg1 = 0; @@ -2116,11 +2144,17 @@ ML_(generic_PRE_sys_mmap) ( ThreadId tid, #define PRE(name) DEFN_PRE_TEMPLATE(generic, name) #define POST(name) DEFN_POST_TEMPLATE(generic, name) -#if VG_WORDSIZE == 4 -// Combine two 32-bit values into a 64-bit value -// Always use with low-numbered arg first (e.g. LOHI64(ARG1,ARG2) ) -// GrP fixme correct for ppc-linux? -#define LOHI64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) ) +// Macros to support 64-bit syscall args split into two 32 bit values +#if defined(VG_LITTLEENDIAN) +#define MERGE64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) ) +#define MERGE64_FIRST(name) name##_low +#define MERGE64_SECOND(name) name##_high +#elif defined(VG_BIGENDIAN) +#define MERGE64(hi,lo) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) ) +#define MERGE64_FIRST(name) name##_high +#define MERGE64_SECOND(name) name##_low +#else +#error Unknown endianness #endif #if !defined(VGO_freebsd) /* On freebsd, exit(2) is all-threads shutdown */ @@ -2380,10 +2414,10 @@ PRE(sys_pwrite64) *flags |= SfMayBlock; #if VG_WORDSIZE == 4 PRINT("sys_pwrite64 ( %ld, %#lx, %llu, %lld )", - ARG1, ARG2, (ULong)ARG3, LOHI64(ARG4,ARG5)); + ARG1, ARG2, (ULong)ARG3, MERGE64(ARG4,ARG5)); PRE_REG_READ5(ssize_t, "pwrite64", unsigned int, fd, const char *, buf, vki_size_t, count, - vki_u32, offset_low32, vki_u32, offset_high32); + vki_u32, MERGE64_FIRST(offset), vki_u32, MERGE64_SECOND(offset)); #elif VG_WORDSIZE == 8 PRINT("sys_pwrite64 ( %ld, %#lx, %llu, %lld )", ARG1, ARG2, (ULong)ARG3, (Long)ARG4); @@ -2443,10 +2477,10 @@ PRE(sys_pread64) *flags |= SfMayBlock; #if VG_WORDSIZE == 4 PRINT("sys_pread64 ( %ld, %#lx, %llu, %lld )", - ARG1, ARG2, (ULong)ARG3, LOHI64(ARG4,ARG5)); + ARG1, ARG2, (ULong)ARG3, MERGE64(ARG4,ARG5)); PRE_REG_READ5(ssize_t, "pread64", unsigned int, fd, char *, buf, vki_size_t, count, - vki_u32, offset_low32, vki_u32, offset_high32); + vki_u32, MERGE64_FIRST(offset), vki_u32, MERGE64_SECOND(offset)); #elif VG_WORDSIZE == 8 PRINT("sys_pread64 ( %ld, %#lx, %llu, %lld )", ARG1, ARG2, (ULong)ARG3, (Long)ARG4); @@ -2527,7 +2561,7 @@ PRE(sys_execve) ThreadState* tst; Int i, j, tot_args; SysRes res; - Bool setuid_allowed; + Bool setuid_allowed, trace_this_child; PRINT("sys_execve ( %#lx(%s), %#lx, %#lx )", ARG1, (char*)ARG1, ARG2, ARG3); PRE_REG_READ3(vki_off_t, "execve", @@ -2549,15 +2583,19 @@ PRE(sys_execve) doing it. */ /* Check that the name at least begins in client-accessible storage. */ - if (!VG_(am_is_valid_for_client)( ARG1, 1, VKI_PROT_READ )) { + if (ARG1 == 0 /* obviously bogus */ + || !VG_(am_is_valid_for_client)( ARG1, 1, VKI_PROT_READ )) { SET_STATUS_Failure( VKI_EFAULT ); return; } + // Decide whether or not we want to follow along + trace_this_child = VG_(should_we_trace_this_child)( (HChar*)ARG1 ); + // Do the important checks: it is a file, is executable, permissions are // ok, etc. We allow setuid executables to run only in the case when // we are not simulating them, that is, they to be run natively. - setuid_allowed = VG_(clo_trace_children) ? False : True; + setuid_allowed = trace_this_child ? False : True; res = VG_(pre_exec_check)((const Char*)ARG1, NULL, setuid_allowed); if (sr_isError(res)) { SET_STATUS_Failure( sr_Err(res) ); @@ -2567,7 +2605,7 @@ PRE(sys_execve) /* If we're tracing the child, and the launcher name looks bogus (possibly because launcher.c couldn't figure it out, see comments therein) then we have no option but to fail. */ - if (VG_(clo_trace_children) + if (trace_this_child && (VG_(name_of_launcher) == NULL || VG_(name_of_launcher)[0] != '/')) { SET_STATUS_Failure( VKI_ECHILD ); /* "No child processes" */ @@ -2585,7 +2623,7 @@ PRE(sys_execve) // Set up the child's exe path. // - if (VG_(clo_trace_children)) { + if (trace_this_child) { // We want to exec the launcher. Get its pre-remembered path. path = VG_(name_of_launcher); @@ -2623,7 +2661,7 @@ PRE(sys_execve) VG_(env_remove_valgrind_env_stuff)( envp ); } - if (VG_(clo_trace_children)) { + if (trace_this_child) { // Set VALGRIND_LIB in ARG3 (the environment) VG_(env_setenv)( &envp, VALGRIND_LIB, VG_(libdir)); } @@ -2636,7 +2674,7 @@ PRE(sys_execve) // except that the first VG_(args_for_valgrind_noexecpass) args // are omitted. // - if (!VG_(clo_trace_children)) { + if (!trace_this_child) { argv = (Char**)ARG2; } else { vg_assert( VG_(args_for_valgrind) ); @@ -3011,10 +3049,10 @@ PRE(sys_ftruncate64) { *flags |= SfMayBlock; #if VG_WORDSIZE == 4 - PRINT("sys_ftruncate64 ( %ld, %lld )", ARG1, LOHI64(ARG2,ARG3)); + PRINT("sys_ftruncate64 ( %ld, %lld )", ARG1, MERGE64(ARG2,ARG3)); PRE_REG_READ3(long, "ftruncate64", unsigned int, fd, - UWord, length_low32, UWord, length_high32); + UWord, MERGE64_FIRST(length), UWord, MERGE64_SECOND(length)); #else PRINT("sys_ftruncate64 ( %ld, %lld )", ARG1, (Long)ARG2); PRE_REG_READ2(long, "ftruncate64", @@ -3026,10 +3064,10 @@ PRE(sys_truncate64) { *flags |= SfMayBlock; #if VG_WORDSIZE == 4 - PRINT("sys_truncate64 ( %#lx, %lld )", ARG1, (Long)LOHI64(ARG2, ARG3)); + PRINT("sys_truncate64 ( %#lx, %lld )", ARG1, (Long)MERGE64(ARG2, ARG3)); PRE_REG_READ3(long, "truncate64", const char *, path, - UWord, length_low32, UWord, length_high32); + UWord, MERGE64_FIRST(length), UWord, MERGE64_SECOND(length)); #else PRINT("sys_truncate64 ( %#lx, %lld )", ARG1, (Long)ARG2); PRE_REG_READ2(long, "truncate64", @@ -3578,7 +3616,7 @@ PRE(sys_open) } PRE_MEM_RASCIIZ( "open(filename)", ARG1 ); -#if HAVE_PROC +#if defined(VGO_linux) /* Handle the case where the open is of /proc/self/cmdline or /proc//cmdline, and just give it a copy of the fd for the fake file we cooked up at startup (in m_main). Also, seek the @@ -3603,7 +3641,7 @@ PRE(sys_open) return; } } -#endif // HAVE_PROC +#endif // defined(VGO_linux) /* Otherwise handle normally */ *flags |= SfMayBlock; @@ -3726,7 +3764,7 @@ PRE(sys_readlink) PRE_MEM_WRITE( "readlink(buf)", ARG2,ARG3 ); { -#if HAVE_PROC +#if defined(VGO_linux) /* * Handle the case where readlink is looking at /proc/self/exe or * /proc//exe. @@ -3742,7 +3780,7 @@ PRE(sys_readlink) SET_STATUS_from_SysRes( VG_(do_syscall3)(saved, (UWord)name, ARG2, ARG3)); } else -#endif // HAVE_PROC +#endif // defined(VGO_linux) { /* Normal case */ SET_STATUS_from_SysRes( VG_(do_syscall3)(saved, ARG1, ARG2, ARG3)); diff --git a/coregrind/m_syswrap/syswrap-linux-variants.c b/coregrind/m_syswrap/syswrap-linux-variants.c index 7c188c0..27463ed 100644 --- a/coregrind/m_syswrap/syswrap-linux-variants.c +++ b/coregrind/m_syswrap/syswrap-linux-variants.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c index 7f81262..b0e5ca3 100644 --- a/coregrind/m_syswrap/syswrap-linux.c +++ b/coregrind/m_syswrap/syswrap-linux.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -83,6 +83,9 @@ static VgSchedReturnCode thread_wrapper(Word /*ThreadId*/ tidW) VG_TRACK(pre_thread_first_insn, tid); tst->os_state.lwpid = VG_(gettid)(); + /* Set the threadgroup for real. This overwrites the provisional + value set in do_clone() syswrap-*-linux.c. See comments in + do_clone for background, also #226116. */ tst->os_state.threadgroup = VG_(getpid)(); /* Thread created with all signals blocked; scheduler will set the @@ -195,6 +198,14 @@ static void run_a_thread_NORETURN ( Word tidW ) : "=m" (tst->status) : "r" (vgts_empty), "n" (__NR_exit), "m" (tst->os_state.exitcode)); } +#elif defined(VGP_arm_linux) + asm volatile ( + "str %1, %0\n" /* set tst->status = VgTs_Empty */ + "mov r7, %2\n" /* set %r7 = __NR_exit */ + "ldr r0, %3\n" /* set %r0 = tst->os_state.exitcode */ + "svc 0x00000000\n" /* exit(tst->os_state.exitcode) */ + : "=m" (tst->status) + : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode)); #else # error Unknown platform #endif @@ -319,7 +330,9 @@ SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, /* Since this is the fork() form of clone, we don't need all that VG_(clone) stuff */ -#if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) +#if defined(VGP_x86_linux) \ + || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ + || defined(VGP_arm_linux) res = VG_(do_syscall5)( __NR_clone, flags, (UWord)NULL, (UWord)parent_tidptr, (UWord)NULL, (UWord)child_tidptr ); @@ -378,8 +391,19 @@ SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, #define PRE(name) DEFN_PRE_TEMPLATE(linux, name) #define POST(name) DEFN_POST_TEMPLATE(linux, name) -// Combine two 32-bit values into a 64-bit value +// Macros to support 64-bit syscall args split into two 32 bit values #define LOHI64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) ) +#if defined(VG_LITTLEENDIAN) +#define MERGE64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) ) +#define MERGE64_FIRST(name) name##_low +#define MERGE64_SECOND(name) name##_high +#elif defined(VG_BIGENDIAN) +#define MERGE64(hi,lo) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) ) +#define MERGE64_FIRST(name) name##_high +#define MERGE64_SECOND(name) name##_low +#else +#error Unknown endianness +#endif /* --------------------------------------------------------------------- *mount wrappers @@ -396,7 +420,8 @@ PRE(sys_mount) PRE_REG_READ5(long, "mount", char *, source, char *, target, char *, type, unsigned long, flags, void *, data); - PRE_MEM_RASCIIZ( "mount(source)", ARG1); + if (ARG1) + PRE_MEM_RASCIIZ( "mount(source)", ARG1); PRE_MEM_RASCIIZ( "mount(target)", ARG2); PRE_MEM_RASCIIZ( "mount(type)", ARG3); } @@ -605,34 +630,39 @@ POST(sys_llseek) POST_MEM_WRITE( ARG4, sizeof(vki_loff_t) ); } -//zz PRE(sys_adjtimex, 0) -//zz { -//zz struct vki_timex *tx = (struct vki_timex *)ARG1; -//zz PRINT("sys_adjtimex ( %p )", ARG1); -//zz PRE_REG_READ1(long, "adjtimex", struct timex *, buf); -//zz PRE_MEM_READ( "adjtimex(timex->modes)", ARG1, sizeof(tx->modes)); -//zz -#if 0 //zz (avoiding warnings about multi-line comments) -zz #define ADJX(bit,field) \ -zz if (tx->modes & bit) \ -zz PRE_MEM_READ( "adjtimex(timex->"#field")", \ -zz (Addr)&tx->field, sizeof(tx->field)) -#endif -//zz ADJX(ADJ_FREQUENCY, freq); -//zz ADJX(ADJ_MAXERROR, maxerror); -//zz ADJX(ADJ_ESTERROR, esterror); -//zz ADJX(ADJ_STATUS, status); -//zz ADJX(ADJ_TIMECONST, constant); -//zz ADJX(ADJ_TICK, tick); -//zz #undef ADJX -//zz -//zz PRE_MEM_WRITE( "adjtimex(timex)", ARG1, sizeof(struct vki_timex)); -//zz } -//zz -//zz POST(sys_adjtimex) -//zz { -//zz POST_MEM_WRITE( ARG1, sizeof(struct vki_timex) ); -//zz } +PRE(sys_adjtimex) +{ + struct vki_timex *tx = (struct vki_timex *)ARG1; + PRINT("sys_adjtimex ( %#lx )", ARG1); + PRE_REG_READ1(long, "adjtimex", struct timex *, buf); + PRE_MEM_READ( "adjtimex(timex->modes)", ARG1, sizeof(tx->modes)); + +#define ADJX(bits,field) \ + if (tx->modes & (bits)) \ + PRE_MEM_READ( "adjtimex(timex->"#field")", \ + (Addr)&tx->field, sizeof(tx->field)) + + if (tx->modes & VKI_ADJ_ADJTIME) { + if (!(tx->modes & VKI_ADJ_OFFSET_READONLY)) + PRE_MEM_READ( "adjtimex(timex->offset)", (Addr)&tx->offset, sizeof(tx->offset)); + } else { + ADJX(VKI_ADJ_OFFSET, offset); + ADJX(VKI_ADJ_FREQUENCY, freq); + ADJX(VKI_ADJ_MAXERROR, maxerror); + ADJX(VKI_ADJ_ESTERROR, esterror); + ADJX(VKI_ADJ_STATUS, status); + ADJX(VKI_ADJ_TIMECONST|VKI_ADJ_TAI, constant); + ADJX(VKI_ADJ_TICK, tick); + } +#undef ADJX + + PRE_MEM_WRITE( "adjtimex(timex)", ARG1, sizeof(struct vki_timex)); +} + +POST(sys_adjtimex) +{ + POST_MEM_WRITE( ARG1, sizeof(struct vki_timex) ); +} PRE(sys_ioperm) { @@ -907,8 +937,6 @@ PRE(sys_futex) break; } - PRE_MEM_READ( "futex(futex)", ARG1, sizeof(Int) ); - *flags |= SfMayBlock; switch(ARG2 & ~(VKI_FUTEX_PRIVATE_FLAG|VKI_FUTEX_CLOCK_REALTIME)) { @@ -916,6 +944,7 @@ PRE(sys_futex) case VKI_FUTEX_LOCK_PI: case VKI_FUTEX_WAIT_BITSET: case VKI_FUTEX_WAIT_REQUEUE_PI: + PRE_MEM_READ( "futex(futex)", ARG1, sizeof(Int) ); if (ARG4 != 0) PRE_MEM_READ( "futex(timeout)", ARG4, sizeof(struct vki_timespec) ); break; @@ -924,14 +953,18 @@ PRE(sys_futex) case VKI_FUTEX_CMP_REQUEUE: case VKI_FUTEX_CMP_REQUEUE_PI: case VKI_FUTEX_WAKE_OP: + PRE_MEM_READ( "futex(futex)", ARG1, sizeof(Int) ); PRE_MEM_READ( "futex(futex2)", ARG5, sizeof(Int) ); break; - case VKI_FUTEX_WAKE: case VKI_FUTEX_FD: - case VKI_FUTEX_WAKE_BITSET: case VKI_FUTEX_TRYLOCK_PI: case VKI_FUTEX_UNLOCK_PI: + PRE_MEM_READ( "futex(futex)", ARG1, sizeof(Int) ); + break; + + case VKI_FUTEX_WAKE: + case VKI_FUTEX_WAKE_BITSET: /* no additional pointers */ break; @@ -1167,14 +1200,24 @@ POST(sys_eventfd2) } } -// 64-bit version. PRE(sys_fallocate) { *flags |= SfMayBlock; +#if VG_WORDSIZE == 4 + PRINT("sys_fallocate ( %ld, %ld, %lld, %lld )", + ARG1, ARG2, MERGE64(ARG3,ARG4), MERGE64(ARG5,ARG6)); + PRE_REG_READ6(long, "fallocate", + int, fd, int, mode, + unsigned, MERGE64_FIRST(offset), unsigned, MERGE64_SECOND(offset), + unsigned, MERGE64_FIRST(len), unsigned, MERGE64_SECOND(len)); +#elif VG_WORDSIZE == 8 PRINT("sys_fallocate ( %ld, %ld, %lld, %lld )", ARG1, ARG2, (Long)ARG3, (Long)ARG4); PRE_REG_READ4(long, "fallocate", int, fd, int, mode, vki_loff_t, offset, vki_loff_t, len); +#else +# error Unexpected word size +#endif if (!ML_(fd_allowed)(ARG1, "fallocate", tid, False)) SET_STATUS_Failure( VKI_EBADF ); } @@ -1286,19 +1329,19 @@ POST(sys_tgkill) PRE(sys_fadvise64) { PRINT("sys_fadvise64 ( %ld, %lld, %lu, %ld )", - ARG1, LOHI64(ARG2,ARG3), ARG4, ARG5); + ARG1, MERGE64(ARG2,ARG3), ARG4, ARG5); PRE_REG_READ5(long, "fadvise64", - int, fd, vki_u32, offset_low, vki_u32, offset_high, + int, fd, vki_u32, MERGE64_FIRST(offset), vki_u32, MERGE64_SECOND(offset), vki_size_t, len, int, advice); } PRE(sys_fadvise64_64) { PRINT("sys_fadvise64_64 ( %ld, %lld, %lld, %ld )", - ARG1, LOHI64(ARG2,ARG3), LOHI64(ARG4,ARG5), ARG6); + ARG1, MERGE64(ARG2,ARG3), MERGE64(ARG4,ARG5), ARG6); PRE_REG_READ6(long, "fadvise64_64", - int, fd, vki_u32, offset_low, vki_u32, offset_high, - vki_u32, len_low, vki_u32, len_high, int, advice); + int, fd, vki_u32, MERGE64_FIRST(offset), vki_u32, MERGE64_SECOND(offset), + vki_u32, MERGE64_FIRST(len), vki_u32, MERGE64_SECOND(len), int, advice); } /* --------------------------------------------------------------------- @@ -1399,10 +1442,35 @@ POST(sys_io_getevents) if (vev->result > 0) POST_MEM_WRITE( cb->aio_buf, vev->result ); break; - + case VKI_IOCB_CMD_PWRITE: break; - + + case VKI_IOCB_CMD_FSYNC: + break; + + case VKI_IOCB_CMD_FDSYNC: + break; + + case VKI_IOCB_CMD_PREADV: + if (vev->result > 0) { + struct vki_iovec * vec = (struct vki_iovec *)(Addr)cb->aio_buf; + Int remains = vev->result; + Int j; + + for (j = 0; j < cb->aio_nbytes; j++) { + Int nReadThisBuf = vec[j].iov_len; + if (nReadThisBuf > remains) nReadThisBuf = remains; + POST_MEM_WRITE( (Addr)vec[j].iov_base, nReadThisBuf ); + remains -= nReadThisBuf; + if (remains < 0) VG_(core_panic)("io_getevents(PREADV): remains < 0"); + } + } + break; + + case VKI_IOCB_CMD_PWRITEV: + break; + default: VG_(message)(Vg_DebugMsg, "Warning: unhandled io_getevents opcode: %u\n", @@ -1415,7 +1483,7 @@ POST(sys_io_getevents) PRE(sys_io_submit) { - Int i; + Int i, j; PRINT("sys_io_submit ( %llu, %ld, %#lx )", (ULong)ARG1,ARG2,ARG3); PRE_REG_READ3(long, "io_submit", @@ -1425,6 +1493,8 @@ PRE(sys_io_submit) if (ARG3 != 0) { for (i = 0; i < ARG2; i++) { struct vki_iocb *cb = ((struct vki_iocb **)ARG3)[i]; + struct vki_iovec *iov; + PRE_MEM_READ( "io_submit(iocb)", (Addr)cb, sizeof(struct vki_iocb) ); switch (cb->aio_lio_opcode) { case VKI_IOCB_CMD_PREAD: @@ -1434,7 +1504,27 @@ PRE(sys_io_submit) case VKI_IOCB_CMD_PWRITE: PRE_MEM_READ( "io_submit(PWRITE)", cb->aio_buf, cb->aio_nbytes ); break; - + + case VKI_IOCB_CMD_FSYNC: + break; + + case VKI_IOCB_CMD_FDSYNC: + break; + + case VKI_IOCB_CMD_PREADV: + iov = (struct vki_iovec *)(Addr)cb->aio_buf; + PRE_MEM_READ( "io_submit(PREADV)", cb->aio_buf, cb->aio_nbytes * sizeof(struct vki_iovec) ); + for (j = 0; j < cb->aio_nbytes; j++) + PRE_MEM_WRITE( "io_submit(PREADV(iov[i]))", (Addr)iov[j].iov_base, iov[j].iov_len ); + break; + + case VKI_IOCB_CMD_PWRITEV: + iov = (struct vki_iovec *)(Addr)cb->aio_buf; + PRE_MEM_READ( "io_submit(PWRITEV)", cb->aio_buf, cb->aio_nbytes * sizeof(struct vki_iovec) ); + for (j = 0; j < cb->aio_nbytes; j++) + PRE_MEM_READ( "io_submit(PWRITEV(iov[i]))", (Addr)iov[j].iov_base, iov[j].iov_len ); + break; + default: VG_(message)(Vg_DebugMsg,"Warning: unhandled io_submit opcode: %u\n", cb->aio_lio_opcode); @@ -1526,6 +1616,24 @@ POST(sys_inotify_init) } } +PRE(sys_inotify_init1) +{ + PRINT("sys_inotify_init ( %ld )", ARG1); + PRE_REG_READ1(long, "inotify_init", int, flag); +} + +POST(sys_inotify_init1) +{ + vg_assert(SUCCESS); + if (!ML_(fd_allowed)(RES, "inotify_init", tid, True)) { + VG_(close)(RES); + SET_STATUS_Failure( VKI_EMFILE ); + } else { + if (VG_(clo_track_fds)) + ML_(record_fd_open_nameless) (tid, RES); + } +} + PRE(sys_inotify_add_watch) { PRINT( "sys_inotify_add_watch ( %ld, %#lx, %lx )", ARG1,ARG2,ARG3); @@ -1619,7 +1727,7 @@ PRE(sys_mq_timedreceive) } POST(sys_mq_timedreceive) { - POST_MEM_WRITE( ARG2, ARG3 ); + POST_MEM_WRITE( ARG2, RES ); if (ARG4 != 0) POST_MEM_WRITE( ARG4, sizeof(unsigned int) ); } @@ -2253,6 +2361,21 @@ PRE(sys_sched_get_priority_min) PRE_REG_READ1(long, "sched_get_priority_min", int, policy); } +PRE(sys_sched_rr_get_interval) +{ + PRINT("sys_sched_rr_get_interval ( %ld, %#lx )", ARG1, ARG2); + PRE_REG_READ2(int, "sched_rr_get_interval", + vki_pid_t, pid, + struct vki_timespec *, tp); + PRE_MEM_WRITE("sched_rr_get_interval(timespec)", + ARG2, sizeof(struct vki_timespec)); +} + +POST(sys_sched_rr_get_interval) +{ + POST_MEM_WRITE(ARG2, sizeof(struct vki_timespec)); +} + PRE(sys_sched_setaffinity) { PRINT("sched_setaffinity ( %ld, %ld, %#lx )", ARG1, ARG2, ARG3); @@ -2346,6 +2469,21 @@ POST(sys_pipe2) } } +PRE(sys_dup3) +{ + PRINT("sys_dup3 ( %ld, %ld, %ld )", ARG1,ARG2,ARG3); + PRE_REG_READ3(long, "dup3", unsigned int, oldfd, unsigned int, newfd, int, flags); + if (!ML_(fd_allowed)(ARG2, "dup3", tid, True)) + SET_STATUS_Failure( VKI_EBADF ); +} + +POST(sys_dup3) +{ + vg_assert(SUCCESS); + if (VG_(clo_track_fds)) + ML_(record_fd_open_named)(tid, RES); +} + PRE(sys_quotactl) { PRINT("sys_quotactl (0x%lx, %#lx, 0x%lx, 0x%lx )", ARG1,ARG2,ARG3, ARG4); @@ -2376,15 +2514,50 @@ POST(sys_waitid) PRE(sys_sync_file_range) { *flags |= SfMayBlock; - PRINT("sys_sync_file_range ( %ld, %ld, %ld, %ld )", - ARG1,ARG2,ARG3,ARG4); +#if VG_WORDSIZE == 4 + PRINT("sys_sync_file_range ( %ld, %lld, %lld, %ld )", + ARG1,MERGE64(ARG2,ARG3),MERGE64(ARG4,ARG5),ARG6); + PRE_REG_READ6(long, "sync_file_range", + int, fd, + unsigned, MERGE64_FIRST(offset), unsigned, MERGE64_SECOND(offset), + unsigned, MERGE64_FIRST(nbytes), unsigned, MERGE64_SECOND(nbytes), + unsigned int, flags); +#elif VG_WORDSIZE == 8 + PRINT("sys_sync_file_range ( %ld, %lld, %lld, %ld )", + ARG1,(Long)ARG2,(Long)ARG3,ARG4); PRE_REG_READ4(long, "sync_file_range", int, fd, vki_loff_t, offset, vki_loff_t, nbytes, unsigned int, flags); +#else +# error Unexpected word size +#endif if (!ML_(fd_allowed)(ARG1, "sync_file_range", tid, False)) SET_STATUS_Failure( VKI_EBADF ); } +PRE(sys_sync_file_range2) +{ + *flags |= SfMayBlock; +#if VG_WORDSIZE == 4 + PRINT("sys_sync_file_range2 ( %ld, %ld, %lld, %lld )", + ARG1,ARG2,MERGE64(ARG3,ARG4),MERGE64(ARG5,ARG6)); + PRE_REG_READ6(long, "sync_file_range2", + int, fd, unsigned int, flags, + unsigned, MERGE64_FIRST(offset), unsigned, MERGE64_SECOND(offset), + unsigned, MERGE64_FIRST(nbytes), unsigned, MERGE64_SECOND(nbytes)); +#elif VG_WORDSIZE == 8 + PRINT("sys_sync_file_range2 ( %ld, %ld, %lld, %lld )", + ARG1,ARG2,(Long)ARG3,(Long)ARG4); + PRE_REG_READ4(long, "sync_file_range2", + int, fd, unsigned int, flags, + vki_loff_t, offset, vki_loff_t, nbytes); +#else +# error Unexpected word size +#endif + if (!ML_(fd_allowed)(ARG1, "sync_file_range2", tid, False)) + SET_STATUS_Failure( VKI_EBADF ); +} + PRE(sys_stime) { PRINT("sys_stime ( %#lx )", ARG1); @@ -2392,6 +2565,53 @@ PRE(sys_stime) PRE_MEM_READ( "stime(t)", ARG1, sizeof(vki_time_t) ); } +PRE(sys_perf_counter_open) +{ + PRINT("sys_perf_counter_open ( %#lx, %ld, %ld, %ld, %ld )", + ARG1,ARG2,ARG3,ARG4,ARG5); + PRE_REG_READ5(long, "perf_counter_open", + struct vki_perf_counter_attr *, attr, + vki_pid_t, pid, int, cpu, int, group_fd, + unsigned long, flags); + PRE_MEM_READ( "perf_counter_open(attr)", + ARG1, sizeof(struct vki_perf_counter_attr) ); +} + +POST(sys_perf_counter_open) +{ + vg_assert(SUCCESS); + if (!ML_(fd_allowed)(RES, "perf_counter_open", tid, True)) { + VG_(close)(RES); + SET_STATUS_Failure( VKI_EMFILE ); + } else { + if (VG_(clo_track_fds)) + ML_(record_fd_open_nameless)(tid, RES); + } +} + +PRE(sys_getcpu) +{ + PRINT("sys_getcpu ( %#lx, %#lx, %#lx )" , ARG1,ARG2,ARG3); + PRE_REG_READ3(int, "getcpu", + unsigned *, cpu, unsigned *, node, struct vki_getcpu_cache *, tcache); + if (ARG1 != 0) + PRE_MEM_WRITE( "getcpu(cpu)", ARG1, sizeof(unsigned) ); + if (ARG2 != 0) + PRE_MEM_WRITE( "getcpu(node)", ARG2, sizeof(unsigned) ); + if (ARG3 != 0) + PRE_MEM_WRITE( "getcpu(tcache)", ARG3, sizeof(struct vki_getcpu_cache) ); +} + +POST(sys_getcpu) +{ + if (ARG1 != 0) + POST_MEM_WRITE( ARG1, sizeof(unsigned) ); + if (ARG2 != 0) + POST_MEM_WRITE( ARG2, sizeof(unsigned) ); + if (ARG3 != 0) + POST_MEM_WRITE( ARG3, sizeof(struct vki_getcpu_cache) ); +} + /* --------------------------------------------------------------------- utime wrapper ------------------------------------------------------------------ */ @@ -2417,6 +2637,29 @@ PRE(sys_lseek) unsigned int, fd, vki_off_t, offset, unsigned int, whence); } +/* --------------------------------------------------------------------- + readahead wrapper + ------------------------------------------------------------------ */ + +PRE(sys_readahead) +{ + *flags |= SfMayBlock; +#if VG_WORDSIZE == 4 + PRINT("sys_readahead ( %ld, %lld, %ld )", ARG1, MERGE64(ARG2,ARG3), ARG4); + PRE_REG_READ4(vki_off_t, "readahead", + int, fd, unsigned, MERGE64_FIRST(offset), + unsigned, MERGE64_SECOND(offset), vki_size_t, count); +#elif VG_WORDSIZE == 8 + PRINT("sys_readahead ( %ld, %lld, %ld )", ARG1, (Long)ARG2, ARG3); + PRE_REG_READ3(vki_off_t, "readahead", + int, fd, vki_loff_t, offset, vki_size_t, count); +#else +# error Unexpected word size +#endif + if (!ML_(fd_allowed)(ARG1, "readahead", tid, False)) + SET_STATUS_Failure( VKI_EBADF ); +} + /* --------------------------------------------------------------------- sig* wrappers ------------------------------------------------------------------ */ @@ -2634,7 +2877,7 @@ PRE(sys_rt_sigqueueinfo) PRE_REG_READ3(long, "rt_sigqueueinfo", int, pid, int, sig, vki_siginfo_t *, uinfo); if (ARG2 != 0) - PRE_MEM_READ( "rt_sigqueueinfo(uinfo)", ARG3, sizeof(vki_siginfo_t) ); + PRE_MEM_READ( "rt_sigqueueinfo(uinfo)", ARG3, VKI_SI_MAX_SIZE ); } POST(sys_rt_sigqueueinfo) { @@ -2642,6 +2885,21 @@ POST(sys_rt_sigqueueinfo) SET_STATUS_Failure( VKI_EINVAL ); } +PRE(sys_rt_tgsigqueueinfo) +{ + PRINT("sys_rt_tgsigqueueinfo(%ld, %ld, %ld, %#lx)", ARG1, ARG2, ARG3, ARG4); + PRE_REG_READ4(long, "rt_tgsigqueueinfo", + int, tgid, int, pid, int, sig, vki_siginfo_t *, uinfo); + if (ARG3 != 0) + PRE_MEM_READ( "rt_tgsigqueueinfo(uinfo)", ARG4, VKI_SI_MAX_SIZE ); +} + +POST(sys_rt_tgsigqueueinfo) +{ + if (!ML_(client_signal_OK)(ARG3)) + SET_STATUS_Failure( VKI_EINVAL ); +} + // XXX: x86-specific? The kernel prototypes for the different archs are // hard to decipher. PRE(sys_rt_sigsuspend) @@ -2962,6 +3220,101 @@ PRE(sys_faccessat) PRE_MEM_RASCIIZ( "faccessat(pathname)", ARG2 ); } +/* --------------------------------------------------------------------- + p{read,write}v wrappers + ------------------------------------------------------------------ */ + +PRE(sys_preadv) +{ + Int i; + struct vki_iovec * vec; + *flags |= SfMayBlock; +#if VG_WORDSIZE == 4 + /* Note that the offset argument here is in lo+hi order on both + big and little endian platforms... */ + PRINT("sys_preadv ( %ld, %#lx, %llu, %lld )",ARG1,ARG2,(ULong)ARG3,LOHI64(ARG4,ARG5)); + PRE_REG_READ5(ssize_t, "preadv", + unsigned long, fd, const struct iovec *, vector, + unsigned long, count, vki_u32, offset_low, + vki_u32, offset_high); +#elif VG_WORDSIZE == 8 + PRINT("sys_preadv ( %ld, %#lx, %llu, %lld )",ARG1,ARG2,(ULong)ARG3,(Long)ARG4); + PRE_REG_READ4(ssize_t, "preadv", + unsigned long, fd, const struct iovec *, vector, + unsigned long, count, Word, offset); +#else +# error Unexpected word size +#endif + if (!ML_(fd_allowed)(ARG1, "preadv", tid, False)) { + SET_STATUS_Failure( VKI_EBADF ); + } else { + PRE_MEM_READ( "preadv(vector)", ARG2, ARG3 * sizeof(struct vki_iovec) ); + + if (ARG2 != 0) { + /* ToDo: don't do any of the following if the vector is invalid */ + vec = (struct vki_iovec *)ARG2; + for (i = 0; i < (Int)ARG3; i++) + PRE_MEM_WRITE( "preadv(vector[...])", + (Addr)vec[i].iov_base, vec[i].iov_len ); + } + } +} + +POST(sys_preadv) +{ + vg_assert(SUCCESS); + if (RES > 0) { + Int i; + struct vki_iovec * vec = (struct vki_iovec *)ARG2; + Int remains = RES; + + /* RES holds the number of bytes read. */ + for (i = 0; i < (Int)ARG3; i++) { + Int nReadThisBuf = vec[i].iov_len; + if (nReadThisBuf > remains) nReadThisBuf = remains; + POST_MEM_WRITE( (Addr)vec[i].iov_base, nReadThisBuf ); + remains -= nReadThisBuf; + if (remains < 0) VG_(core_panic)("preadv: remains < 0"); + } + } +} + +PRE(sys_pwritev) +{ + Int i; + struct vki_iovec * vec; + *flags |= SfMayBlock; +#if VG_WORDSIZE == 4 + /* Note that the offset argument here is in lo+hi order on both + big and little endian platforms... */ + PRINT("sys_pwritev ( %ld, %#lx, %llu, %lld )",ARG1,ARG2,(ULong)ARG3,LOHI64(ARG4,ARG5)); + PRE_REG_READ5(ssize_t, "pwritev", + unsigned long, fd, const struct iovec *, vector, + unsigned long, count, vki_u32, offset_low, + vki_u32, offset_high); +#elif VG_WORDSIZE == 8 + PRINT("sys_pwritev ( %ld, %#lx, %llu, %lld )",ARG1,ARG2,(ULong)ARG3,(Long)ARG4); + PRE_REG_READ4(ssize_t, "pwritev", + unsigned long, fd, const struct iovec *, vector, + unsigned long, count, Word, offset); +#else +# error Unexpected word size +#endif + if (!ML_(fd_allowed)(ARG1, "pwritev", tid, False)) { + SET_STATUS_Failure( VKI_EBADF ); + } else { + PRE_MEM_READ( "pwritev(vector)", + ARG2, ARG3 * sizeof(struct vki_iovec) ); + if (ARG2 != 0) { + /* ToDo: don't do any of the following if the vector is invalid */ + vec = (struct vki_iovec *)ARG2; + for (i = 0; i < (Int)ARG3; i++) + PRE_MEM_READ( "pwritev(vector[...])", + (Addr)vec[i].iov_base, vec[i].iov_len ); + } + } +} + /* --------------------------------------------------------------------- key retention service wrappers ------------------------------------------------------------------ */ @@ -3167,6 +3520,30 @@ PRE(sys_delete_module) PRE_MEM_RASCIIZ("delete_module(name_user)", ARG1); } +/* --------------------------------------------------------------------- + splice wrappers + ------------------------------------------------------------------ */ + +PRE(sys_splice) +{ + *flags |= SfMayBlock; + PRINT("sys_splice ( %ld, %#lx, %ld, %#lx, %ld, %ld )", + ARG1,ARG2,ARG3,ARG4,ARG5,ARG6); + PRE_REG_READ6(int32_t, "splice", + int, fd_in, vki_loff_t *, off_in, + int, fd_out, vki_loff_t *, off_out, + vki_size_t, len, unsigned int, flags); + if (!ML_(fd_allowed)(ARG1, "splice(fd_in)", tid, False) || + !ML_(fd_allowed)(ARG3, "splice(fd_out)", tid, False)) { + SET_STATUS_Failure( VKI_EBADF ); + } else { + if (ARG2 != 0) + PRE_MEM_READ( "splice(off_in)", ARG2, sizeof(vki_loff_t)); + if (ARG4 != 0) + PRE_MEM_READ( "splice(off_out)", ARG4, sizeof(vki_loff_t)); + } +} + /* --------------------------------------------------------------------- oprofile-related wrappers ------------------------------------------------------------------ */ @@ -3175,9 +3552,9 @@ PRE(sys_delete_module) PRE(sys_lookup_dcookie) { PRINT("sys_lookup_dcookie (0x%llx, %#lx, %ld)", - LOHI64(ARG1,ARG2), ARG3, ARG4); + MERGE64(ARG1,ARG2), ARG3, ARG4); PRE_REG_READ4(long, "lookup_dcookie", - vki_u32, cookie_low32, vki_u32, cookie_high32, + vki_u32, MERGE64_FIRST(cookie), vki_u32, MERGE64_SECOND(cookie), char *, buf, vki_size_t, len); PRE_MEM_WRITE( "lookup_dcookie(buf)", ARG3, ARG4); } @@ -3228,6 +3605,7 @@ PRE(sys_fcntl) // These ones use ARG3 as "arg". case VKI_F_DUPFD: + case VKI_F_DUPFD_CLOEXEC: case VKI_F_SETFD: case VKI_F_SETFL: case VKI_F_SETLEASE: @@ -3280,6 +3658,15 @@ POST(sys_fcntl) ML_(record_fd_open_named)(tid, RES); } } + else if (ARG2 == VKI_F_DUPFD_CLOEXEC) { + if (!ML_(fd_allowed)(RES, "fcntl(DUPFD_CLOEXEC)", tid, True)) { + VG_(close)(RES); + SET_STATUS_Failure( VKI_EMFILE ); + } else { + if (VG_(clo_track_fds)) + ML_(record_fd_open_named)(tid, RES); + } + } } // XXX: wrapper only suitable for 32-bit systems @@ -3300,6 +3687,7 @@ PRE(sys_fcntl64) // These ones use ARG3 as "arg". case VKI_F_DUPFD: + case VKI_F_DUPFD_CLOEXEC: case VKI_F_SETFD: case VKI_F_SETFL: case VKI_F_SETLEASE: @@ -3345,6 +3733,15 @@ POST(sys_fcntl64) ML_(record_fd_open_named)(tid, RES); } } + else if (ARG2 == VKI_F_DUPFD_CLOEXEC) { + if (!ML_(fd_allowed)(RES, "fcntl64(DUPFD_CLOEXEC)", tid, True)) { + VG_(close)(RES); + SET_STATUS_Failure( VKI_EMFILE ); + } else { + if (VG_(clo_track_fds)) + ML_(record_fd_open_named)(tid, RES); + } + } } /* --------------------------------------------------------------------- @@ -3732,6 +4129,7 @@ PRE(sys_ioctl) case VKI_SNDCTL_SEQ_NRSYNTHS: case VKI_SNDCTL_SEQ_NRMIDIS: case VKI_SNDCTL_SEQ_GETTIME: + case VKI_SNDCTL_DSP_GETBLKSIZE: case VKI_SNDCTL_DSP_GETFMTS: case VKI_SNDCTL_DSP_GETTRIGGER: case VKI_SNDCTL_DSP_GETODELAY: @@ -3740,9 +4138,6 @@ PRE(sys_ioctl) case VKI_SOUND_PCM_READ_RATE: case VKI_SOUND_PCM_READ_CHANNELS: case VKI_SOUND_PCM_READ_BITS: -#if !defined(VGA_ppc32) && !defined(VGA_ppc64) - case (VKI_SOUND_PCM_READ_BITS|0x40000000): /* what the fuck ? */ -#endif case VKI_SOUND_PCM_READ_FILTER: PRE_MEM_WRITE( "ioctl(SNDCTL_XXX|SOUND_XXX (SIOR, int))", ARG3, sizeof(int)); @@ -3750,11 +4145,11 @@ PRE(sys_ioctl) case VKI_SNDCTL_SEQ_CTRLRATE: case VKI_SNDCTL_DSP_SPEED: case VKI_SNDCTL_DSP_STEREO: - case VKI_SNDCTL_DSP_GETBLKSIZE: case VKI_SNDCTL_DSP_CHANNELS: case VKI_SOUND_PCM_WRITE_FILTER: case VKI_SNDCTL_DSP_SUBDIVIDE: case VKI_SNDCTL_DSP_SETFRAGMENT: + case VKI_SNDCTL_DSP_SETFMT: case VKI_SNDCTL_DSP_GETCHANNELMASK: case VKI_SNDCTL_DSP_BIND_CHANNEL: case VKI_SNDCTL_TMR_TIMEBASE: @@ -3929,7 +4324,7 @@ PRE(sys_ioctl) PRE_MEM_WRITE( "ioctl(FIGETBSZ)", ARG3, sizeof(unsigned long)); break; case VKI_FIBMAP: - PRE_MEM_READ( "ioctl(FIBMAP)", ARG3, sizeof(unsigned long)); + PRE_MEM_READ( "ioctl(FIBMAP)", ARG3, sizeof(int)); break; case VKI_FBIOGET_VSCREENINFO: /* 0x4600 */ @@ -4470,7 +4865,33 @@ PRE(sys_ioctl) break; default: - ML_(PRE_unknown_ioctl)(tid, ARG2, ARG3); + /* EVIOC* are variable length and return size written on success */ + switch (ARG2 & ~(_VKI_IOC_SIZEMASK << _VKI_IOC_SIZESHIFT)) { + case VKI_EVIOCGNAME(0): + case VKI_EVIOCGPHYS(0): + case VKI_EVIOCGUNIQ(0): + case VKI_EVIOCGKEY(0): + case VKI_EVIOCGLED(0): + case VKI_EVIOCGSND(0): + case VKI_EVIOCGSW(0): + case VKI_EVIOCGBIT(VKI_EV_SYN,0): + case VKI_EVIOCGBIT(VKI_EV_KEY,0): + case VKI_EVIOCGBIT(VKI_EV_REL,0): + case VKI_EVIOCGBIT(VKI_EV_ABS,0): + case VKI_EVIOCGBIT(VKI_EV_MSC,0): + case VKI_EVIOCGBIT(VKI_EV_SW,0): + case VKI_EVIOCGBIT(VKI_EV_LED,0): + case VKI_EVIOCGBIT(VKI_EV_SND,0): + case VKI_EVIOCGBIT(VKI_EV_REP,0): + case VKI_EVIOCGBIT(VKI_EV_FF,0): + case VKI_EVIOCGBIT(VKI_EV_PWR,0): + case VKI_EVIOCGBIT(VKI_EV_FF_STATUS,0): + PRE_MEM_WRITE("ioctl(EVIO*)", ARG3, _VKI_IOC_SIZE(ARG2)); + break; + default: + ML_(PRE_unknown_ioctl)(tid, ARG2, ARG3); + break; + } break; } } @@ -4703,7 +5124,9 @@ POST(sys_ioctl) case VKI_SNDCTL_SEQ_NRSYNTHS: case VKI_SNDCTL_SEQ_NRMIDIS: case VKI_SNDCTL_SEQ_GETTIME: + case VKI_SNDCTL_DSP_GETBLKSIZE: case VKI_SNDCTL_DSP_GETFMTS: + case VKI_SNDCTL_DSP_SETFMT: case VKI_SNDCTL_DSP_GETTRIGGER: case VKI_SNDCTL_DSP_GETODELAY: case VKI_SNDCTL_DSP_GETSPDIF: @@ -4711,16 +5134,12 @@ POST(sys_ioctl) case VKI_SOUND_PCM_READ_RATE: case VKI_SOUND_PCM_READ_CHANNELS: case VKI_SOUND_PCM_READ_BITS: -#if !defined(VGA_ppc32) && !defined(VGA_ppc64) - case (VKI_SOUND_PCM_READ_BITS|0x40000000): /* what the fuck ? */ -#endif case VKI_SOUND_PCM_READ_FILTER: POST_MEM_WRITE(ARG3, sizeof(int)); break; case VKI_SNDCTL_SEQ_CTRLRATE: case VKI_SNDCTL_DSP_SPEED: case VKI_SNDCTL_DSP_STEREO: - case VKI_SNDCTL_DSP_GETBLKSIZE: case VKI_SNDCTL_DSP_CHANNELS: case VKI_SOUND_PCM_WRITE_FILTER: case VKI_SNDCTL_DSP_SUBDIVIDE: @@ -4868,7 +5287,7 @@ POST(sys_ioctl) POST_MEM_WRITE(ARG3, sizeof(unsigned long)); break; case VKI_FIBMAP: - POST_MEM_WRITE(ARG3, sizeof(unsigned long)); + POST_MEM_WRITE(ARG3, sizeof(int)); break; case VKI_FBIOGET_VSCREENINFO: //0x4600 @@ -5258,7 +5677,34 @@ POST(sys_ioctl) break; default: - ML_(POST_unknown_ioctl)(tid, RES, ARG2, ARG3); + /* EVIOC* are variable length and return size written on success */ + switch (ARG2 & ~(_VKI_IOC_SIZEMASK << _VKI_IOC_SIZESHIFT)) { + case VKI_EVIOCGNAME(0): + case VKI_EVIOCGPHYS(0): + case VKI_EVIOCGUNIQ(0): + case VKI_EVIOCGKEY(0): + case VKI_EVIOCGLED(0): + case VKI_EVIOCGSND(0): + case VKI_EVIOCGSW(0): + case VKI_EVIOCGBIT(VKI_EV_SYN,0): + case VKI_EVIOCGBIT(VKI_EV_KEY,0): + case VKI_EVIOCGBIT(VKI_EV_REL,0): + case VKI_EVIOCGBIT(VKI_EV_ABS,0): + case VKI_EVIOCGBIT(VKI_EV_MSC,0): + case VKI_EVIOCGBIT(VKI_EV_SW,0): + case VKI_EVIOCGBIT(VKI_EV_LED,0): + case VKI_EVIOCGBIT(VKI_EV_SND,0): + case VKI_EVIOCGBIT(VKI_EV_REP,0): + case VKI_EVIOCGBIT(VKI_EV_FF,0): + case VKI_EVIOCGBIT(VKI_EV_PWR,0): + case VKI_EVIOCGBIT(VKI_EV_FF_STATUS,0): + if (RES > 0) + POST_MEM_WRITE(ARG3, RES); + break; + default: + ML_(POST_unknown_ioctl)(tid, RES, ARG2, ARG3); + break; + } break; } } diff --git a/coregrind/m_syswrap/syswrap-main.c b/coregrind/m_syswrap/syswrap-main.c index 81740fc..2961b0d 100644 --- a/coregrind/m_syswrap/syswrap-main.c +++ b/coregrind/m_syswrap/syswrap-main.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -66,6 +66,7 @@ amd64 rax rdi rsi rdx r10 r8 r9 n/a n/a rax (== NUM) ppc32 r0 r3 r4 r5 r6 r7 r8 n/a n/a r3+CR0.SO (== ARG1) ppc64 r0 r3 r4 r5 r6 r7 r8 n/a n/a r3+CR0.SO (== ARG1) + arm r7 r0 r1 r2 r3 r4 r5 n/a n/a r0 (== ARG1) FreeBSD: x86 eax +4 +8 +12 +16 +20 +24 +28 +32 edx:eax, eflags.c @@ -549,6 +550,18 @@ void getSyscallArgsFromGuestState ( /*OUT*/SyscallArgs* canonical, canonical->arg8 = stack[3]; } +#elif defined(VGP_arm_linux) + VexGuestARMState* gst = (VexGuestARMState*)gst_vanilla; + canonical->sysno = gst->guest_R7; + canonical->arg1 = gst->guest_R0; + canonical->arg2 = gst->guest_R1; + canonical->arg3 = gst->guest_R2; + canonical->arg4 = gst->guest_R3; + canonical->arg5 = gst->guest_R4; + canonical->arg6 = gst->guest_R5; + canonical->arg7 = 0; + canonical->arg8 = 0; + #elif defined(VGP_ppc32_aix5) VexGuestPPC32State* gst = (VexGuestPPC32State*)gst_vanilla; canonical->sysno = gst->guest_GPR2; @@ -813,6 +826,16 @@ void putSyscallArgsIntoGuestState ( /*IN*/ SyscallArgs* canonical, break; } +#elif defined(VGP_arm_linux) + VexGuestARMState* gst = (VexGuestARMState*)gst_vanilla; + gst->guest_R7 = canonical->sysno; + gst->guest_R0 = canonical->arg1; + gst->guest_R1 = canonical->arg2; + gst->guest_R2 = canonical->arg3; + gst->guest_R3 = canonical->arg4; + gst->guest_R4 = canonical->arg5; + gst->guest_R5 = canonical->arg6; + #elif defined(VGP_ppc32_aix5) VexGuestPPC32State* gst = (VexGuestPPC32State*)gst_vanilla; gst->guest_GPR2 = canonical->sysno; @@ -913,6 +936,11 @@ void getSyscallStatusFromGuestState ( /*OUT*/SyscallStatus* canonical, (flags & 1) != 0 ? True : False); canonical->what = SsComplete; +# elif defined(VGP_arm_linux) + VexGuestARMState* gst = (VexGuestARMState*)gst_vanilla; + canonical->sres = VG_(mk_SysRes_arm_linux)( gst->guest_R0 ); + canonical->what = SsComplete; + # elif defined(VGP_amd64_freebsd) /* duplicates logic in m_signals.VG_UCONTEXT_SYSCALL_SYSRES */ VexGuestAMD64State* gst = (VexGuestAMD64State*)gst_vanilla; @@ -1027,7 +1055,7 @@ void putSyscallStatusIntoGuestState ( /*IN*/ ThreadId tid, if (sr_isError(canonical->sres)) { /* This isn't exactly right, in that really a Failure with res not in the range 1 .. 4095 is unrepresentable in the - Linux-x86 scheme. Oh well. */ + Linux-amd64 scheme. Oh well. */ gst->guest_RAX = - (Long)sr_Err(canonical->sres); } else { gst->guest_RAX = sr_Res(canonical->sres); @@ -1070,6 +1098,19 @@ void putSyscallStatusIntoGuestState ( /*IN*/ ThreadId tid, OFFSET_ppc64_GPR3, sizeof(UWord) ); VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, OFFSET_ppc64_CR0_0, sizeof(UChar) ); +# elif defined(VGP_arm_linux) + VexGuestARMState* gst = (VexGuestARMState*)gst_vanilla; + vg_assert(canonical->what == SsComplete); + if (sr_isError(canonical->sres)) { + /* This isn't exactly right, in that really a Failure with res + not in the range 1 .. 4095 is unrepresentable in the + Linux-arm scheme. Oh well. */ + gst->guest_R0 = - (Int)sr_Err(canonical->sres); + } else { + gst->guest_R0 = sr_Res(canonical->sres); + } + VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, + OFFSET_arm_R0, sizeof(UWord) ); #elif defined(VGP_x86_freebsd) VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; @@ -1277,6 +1318,17 @@ void getSyscallArgLayout ( /*OUT*/SyscallArgLayout* layout ) layout->s_arg7 = sizeof(UWord) * 1; layout->s_arg8 = sizeof(UWord) * 2; +#elif defined(VGP_arm_linux) + layout->o_sysno = OFFSET_arm_R7; + layout->o_arg1 = OFFSET_arm_R0; + layout->o_arg2 = OFFSET_arm_R1; + layout->o_arg3 = OFFSET_arm_R2; + layout->o_arg4 = OFFSET_arm_R3; + layout->o_arg5 = OFFSET_arm_R4; + layout->o_arg6 = OFFSET_arm_R5; + layout->uu_arg7 = -1; /* impossible value */ + layout->uu_arg8 = -1; /* impossible value */ + #elif defined(VGP_ppc32_aix5) layout->o_sysno = OFFSET_ppc32_GPR2; layout->o_arg1 = OFFSET_ppc32_GPR3; @@ -1362,10 +1414,8 @@ static const SyscallTableEntry* get_syscall_entry ( Int syscallno ) { const SyscallTableEntry* sys = NULL; -# if defined(VGO_linux) || defined(VGO_freebsd) - if (syscallno < ML_(syscall_table_size) && - ML_(syscall_table)[syscallno].before != NULL) - sys = &ML_(syscall_table)[syscallno]; +# if defined(VGO_linux) + sys = ML_(get_linux_syscall_entry)( syscallno ); # elif defined(VGP_ppc32_aix5) sys = ML_(get_ppc32_aix5_syscall_entry) ( syscallno ); @@ -1373,6 +1423,12 @@ static const SyscallTableEntry* get_syscall_entry ( Int syscallno ) # elif defined(VGP_ppc64_aix5) sys = ML_(get_ppc64_aix5_syscall_entry) ( syscallno ); +# elif defined(VGO_freebsd) + if (syscallno >= 0 && syscallno < ML_(syscall_table_size) && + ML_(syscall_table)[syscallno].before != NULL) + sys = &ML_(syscall_table)[syscallno]; + break; + # elif defined(VGO_darwin) Int idx = VG_DARWIN_SYSNO_INDEX(syscallno); @@ -2059,6 +2115,45 @@ void ML_(fixup_guest_state_to_restart_syscall) ( ThreadArchState* arch ) vg_assert(p[0] == 0x44 && p[1] == 0x0 && p[2] == 0x0 && p[3] == 0x2); } +#elif defined(VGP_arm_linux) + if (arch->vex.guest_R15T & 1) { + // Thumb mode. SVC is a encoded as + // 1101 1111 imm8 + // where imm8 is the SVC number, and we only accept 0. + arch->vex.guest_R15T -= 2; // sizeof(thumb 16 bit insn) + UChar* p = (UChar*)(arch->vex.guest_R15T - 1); + Bool valid = p[0] == 0 && p[1] == 0xDF; + if (!valid) { + VG_(message)(Vg_DebugMsg, + "?! restarting over (Thumb) syscall that is not syscall " + "at %#llx %02x %02x\n", + arch->vex.guest_R15T - 1ULL, p[0], p[1]); + } + vg_assert(valid); + // FIXME: NOTE, this really isn't right. We need to back up + // ITSTATE to what it was before the SVC instruction, but we + // don't know what it was. At least assert that it is now + // zero, because if it is nonzero then it must also have + // been nonzero for the SVC itself, which means it was + // conditional. Urk. + vg_assert(arch->vex.guest_ITSTATE == 0); + } else { + // ARM mode. SVC is encoded as + // cond 1111 imm24 + // where imm24 is the SVC number, and we only accept 0. + arch->vex.guest_R15T -= 4; // sizeof(arm instr) + UChar* p = (UChar*)arch->vex.guest_R15T; + Bool valid = p[0] == 0 && p[1] == 0 && p[2] == 0 + && (p[3] & 0xF) == 0xF; + if (!valid) { + VG_(message)(Vg_DebugMsg, + "?! restarting over (ARM) syscall that is not syscall " + "at %#llx %02x %02x %02x %02x\n", + arch->vex.guest_R15T + 0ULL, p[0], p[1], p[2], p[3]); + } + vg_assert(valid); + } + #elif defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5) /* Hmm. This is problematic, because on AIX the kernel resumes after a syscall at LR, not at the insn following SC. Hence @@ -2257,7 +2352,7 @@ VG_(fixup_guest_state_after_syscall_interrupted)( ThreadId tid, if (VG_(clo_trace_signals)) VG_(message)( Vg_DebugMsg, "interrupted_syscall: tid=%d, ip=0x%llx, " - "restart=%s, sres.isErr=%s, sres.val=%lld", + "restart=%s, sres.isErr=%s, sres.val=%lld\n", (Int)tid, (ULong)ip, restart ? "True" : "False", @@ -2277,7 +2372,7 @@ VG_(fixup_guest_state_after_syscall_interrupted)( ThreadId tid, if (outside_range) { if (VG_(clo_trace_signals)) VG_(message)( Vg_DebugMsg, - " not in syscall at all: hmm, very suspicious" ); + " not in syscall at all: hmm, very suspicious\n" ); /* Looks like we weren't in a syscall at all. Hmm. */ vg_assert(sci->status.what != SsIdle); return; @@ -2294,7 +2389,7 @@ VG_(fixup_guest_state_after_syscall_interrupted)( ThreadId tid, if (in_setup_to_restart) { /* syscall hasn't even started; go around again */ if (VG_(clo_trace_signals)) - VG_(message)( Vg_DebugMsg, " not started: restarting"); + VG_(message)( Vg_DebugMsg, " not started: restarting\n"); vg_assert(sci->status.what == SsHandToKernel); ML_(fixup_guest_state_to_restart_syscall)(th_regs); } @@ -2306,11 +2401,11 @@ VG_(fixup_guest_state_after_syscall_interrupted)( ThreadId tid, EINTR it. */ if (restart) { if (VG_(clo_trace_signals)) - VG_(message)( Vg_DebugMsg, " at syscall instr: restarting"); + VG_(message)( Vg_DebugMsg, " at syscall instr: restarting\n"); ML_(fixup_guest_state_to_restart_syscall)(th_regs); } else { if (VG_(clo_trace_signals)) - VG_(message)( Vg_DebugMsg, " at syscall instr: returning EINTR"); + VG_(message)( Vg_DebugMsg, " at syscall instr: returning EINTR\n"); canonical = convert_SysRes_to_SyscallStatus( VG_(mk_SysRes_Error)( VKI_EINTR ) ); @@ -2328,7 +2423,7 @@ VG_(fixup_guest_state_after_syscall_interrupted)( ThreadId tid, state. */ if (VG_(clo_trace_signals)) VG_(message)( Vg_DebugMsg, - " completed, but uncommitted: committing"); + " completed, but uncommitted: committing\n"); canonical = convert_SysRes_to_SyscallStatus( sres ); if (!(sci->flags & SfNoWriteResult)) putSyscallStatusIntoGuestState( tid, &canonical, &th_regs->vex ); @@ -2361,7 +2456,9 @@ VG_(fixup_guest_state_after_syscall_interrupted)( ThreadId tid, #endif if (VG_(clo_trace_signals)) VG_(message)( Vg_DebugMsg, - " completed and committed: nothing to do"); + " completed and committed: nothing to do\n"); + getSyscallStatusFromGuestState( &sci->status, &th_regs->vex ); + vg_assert(sci->status.what == SsComplete); VG_(post_syscall)(tid); } diff --git a/coregrind/m_syswrap/syswrap-ppc32-aix5.c b/coregrind/m_syswrap/syswrap-ppc32-aix5.c index 1286b79..01c70a1 100644 --- a/coregrind/m_syswrap/syswrap-ppc32-aix5.c +++ b/coregrind/m_syswrap/syswrap-ppc32-aix5.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/syswrap-ppc32-linux.c b/coregrind/m_syswrap/syswrap-ppc32-linux.c index d56eda5..984c7bc 100644 --- a/coregrind/m_syswrap/syswrap-ppc32-linux.c +++ b/coregrind/m_syswrap/syswrap-ppc32-linux.c @@ -7,8 +7,8 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote - Copyright (C) 2005-2009 Cerion Armour-Brown + Copyright (C) 2005-2010 Nicholas Nethercote + Copyright (C) 2005-2010 Cerion Armour-Brown This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -297,6 +297,17 @@ static SysRes do_clone ( ThreadId ptid, ctst->sig_mask = ptst->sig_mask; ctst->tmp_sig_mask = ptst->sig_mask; + /* Start the child with its threadgroup being the same as the + parent's. This is so that any exit_group calls that happen + after the child is created but before it sets its + os_state.threadgroup field for real (in thread_wrapper in + syswrap-linux.c), really kill the new thread. a.k.a this avoids + a race condition in which the thread is unkillable (via + exit_group) because its threadgroup is not set. The race window + is probably only a few hundred or a few thousand cycles long. + See #226116. */ + ctst->os_state.threadgroup = ptst->os_state.threadgroup; + /* We don't really know where the client stack is, because its allocated by the client. The best we can do is look at the memory mappings and try to derive some useful information. We @@ -457,6 +468,13 @@ PRE(sys_socketcall) break; } + case VKI_SYS_ACCEPT4: { + /* int accept(int s, struct sockaddr *addr, int *addrlen, int args); */ + PRE_MEM_READ( "socketcall.accept4(args)", ARG2, 4*sizeof(Addr) ); + ML_(generic_PRE_sys_accept)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + } + case VKI_SYS_SENDTO: /* int sendto(int s, const void *msg, int len, unsigned int flags, @@ -602,6 +620,7 @@ POST(sys_socketcall) break; case VKI_SYS_ACCEPT: + case VKI_SYS_ACCEPT4: /* int accept(int s, struct sockaddr *addr, int *addrlen); */ r = ML_(generic_POST_sys_accept)( tid, VG_(mk_SysRes_Success)(RES), ARG2_0, ARG2_1, ARG2_2 ); @@ -1495,7 +1514,7 @@ POST(sys_spu_run) // arch/OS combination, eg. */* (generic), */Linux (Linux only), ?/? // (unknown). -const SyscallTableEntry ML_(syscall_table)[] = { +static SyscallTableEntry syscall_table[] = { //.. (restart_syscall) // 0 GENX_(__NR_exit, sys_exit), // 1 GENX_(__NR_fork, sys_fork), // 2 @@ -1629,7 +1648,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { //.. // (__NR_olduname, sys_uname), // 109 -- obsolete //.. //.. GENX_(__NR_iopl, sys_iopl), // 110 -//.. LINX_(__NR_vhangup, sys_vhangup), // 111 + LINX_(__NR_vhangup, sys_vhangup), // 111 //.. GENX_(__NR_idle, sys_ni_syscall), // 112 //.. // (__NR_vm86old, sys_vm86old), // 113 x86/Linux-only GENXY(__NR_wait4, sys_wait4), // 114 @@ -1644,8 +1663,8 @@ const SyscallTableEntry ML_(syscall_table)[] = { //.. // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) GENXY(__NR_uname, sys_newuname), // 122 //.. PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 -//.. LINXY(__NR_adjtimex, sys_adjtimex), // 124 -//.. + LINXY(__NR_adjtimex, sys_adjtimex), // 124 + GENXY(__NR_mprotect, sys_mprotect), // 125 LINXY(__NR_sigprocmask, sys_sigprocmask), // 126 GENX_(__NR_create_module, sys_ni_syscall), // 127 @@ -1690,7 +1709,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max),// 159 LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min),// 160 -//.. //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 */* + LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 GENXY(__NR_nanosleep, sys_nanosleep), // 162 GENX_(__NR_mremap, sys_mremap), // 163 LINX_(__NR_setresuid, sys_setresuid), // 164 @@ -1727,7 +1746,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { // Nb: we treat vfork as fork GENX_(__NR_vfork, sys_fork), // 189 GENXY(__NR_ugetrlimit, sys_getrlimit), // 190 -//__NR_readahead // 191 ppc/Linux only? + LINX_(__NR_readahead, sys_readahead), // 191 */Linux PLAX_(__NR_mmap2, sys_mmap2), // 192 GENX_(__NR_truncate64, sys_truncate64), // 193 GENX_(__NR_ftruncate64, sys_ftruncate64), // 194 @@ -1851,27 +1870,46 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_set_robust_list, sys_set_robust_list), // 299 LINXY(__NR_get_robust_list, sys_get_robust_list), // 300 // LINX_(__NR_move_pages, sys_ni_syscall), // 301 -// LINX_(__NR_getcpu, sys_ni_syscall), // 302 + LINXY(__NR_getcpu, sys_getcpu), // 302 LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 303 LINX_(__NR_utimensat, sys_utimensat), // 304 LINXY(__NR_signalfd, sys_signalfd), // 305 LINXY(__NR_timerfd_create, sys_timerfd_create), // 306 LINX_(__NR_eventfd, sys_eventfd), // 307 -// LINX_(__NR_sync_file_range2, sys_ni_syscall), // 308 -// LINX_(__NR_fallocate, sys_fallocate), // 309 + LINX_(__NR_sync_file_range2, sys_sync_file_range2), // 308 + LINX_(__NR_fallocate, sys_fallocate), // 309 // LINXY(__NR_subpage_prot, sys_ni_syscall), // 310 LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 311 LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 312 LINXY(__NR_signalfd4, sys_signalfd4), // 313 LINX_(__NR_eventfd2, sys_eventfd2), // 314 LINXY(__NR_epoll_create1, sys_epoll_create1), // 315 - // (__NR_dup3, sys_ni_syscall) // 316 - LINXY(__NR_pipe2, sys_pipe2) // 317 - // (__NR_inotify_init1, sys_ni_syscall) // 318 + LINXY(__NR_dup3, sys_dup3), // 316 + LINXY(__NR_pipe2, sys_pipe2), // 317 + LINXY(__NR_inotify_init1, sys_inotify_init1), // 318 + LINXY(__NR_perf_counter_open, sys_perf_counter_open),// 319 + LINXY(__NR_preadv, sys_preadv), // 320 + LINX_(__NR_pwritev, sys_pwritev), // 321 + LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo) // 322 }; -const UInt ML_(syscall_table_size) = - sizeof(ML_(syscall_table)) / sizeof(ML_(syscall_table)[0]); +SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno ) +{ + const UInt syscall_table_size + = sizeof(syscall_table) / sizeof(syscall_table[0]); + + /* Is it in the contiguous initial section of the table? */ + if (sysno < syscall_table_size) { + SyscallTableEntry* sys = &syscall_table[sysno]; + if (sys->before == NULL) + return NULL; /* no entry */ + else + return sys; + } + + /* Can't find a wrapper */ + return NULL; +} #endif // defined(VGP_ppc32_linux) diff --git a/coregrind/m_syswrap/syswrap-ppc64-aix5.c b/coregrind/m_syswrap/syswrap-ppc64-aix5.c index 02263f0..494576b 100644 --- a/coregrind/m_syswrap/syswrap-ppc64-aix5.c +++ b/coregrind/m_syswrap/syswrap-ppc64-aix5.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c index a19b3f4..1b064bd 100644 --- a/coregrind/m_syswrap/syswrap-ppc64-linux.c +++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c @@ -7,8 +7,8 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote - Copyright (C) 2005-2009 Cerion Armour-Brown + Copyright (C) 2005-2010 Nicholas Nethercote + Copyright (C) 2005-2010 Cerion Armour-Brown This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -325,6 +325,17 @@ static SysRes do_clone ( ThreadId ptid, ctst->sig_mask = ptst->sig_mask; ctst->tmp_sig_mask = ptst->sig_mask; + /* Start the child with its threadgroup being the same as the + parent's. This is so that any exit_group calls that happen + after the child is created but before it sets its + os_state.threadgroup field for real (in thread_wrapper in + syswrap-linux.c), really kill the new thread. a.k.a this avoids + a race condition in which the thread is unkillable (via + exit_group) because its threadgroup is not set. The race window + is probably only a few hundred or a few thousand cycles long. + See #226116. */ + ctst->os_state.threadgroup = ptst->os_state.threadgroup; + /* We don't really know where the client stack is, because its allocated by the client. The best we can do is look at the memory mappings and try to derive some useful information. We @@ -484,6 +495,13 @@ PRE(sys_socketcall) break; } + case VKI_SYS_ACCEPT4: { + /* int accept4(int s, struct sockaddr *addr, int *addrlen, int flags); */ + PRE_MEM_READ( "socketcall.accept4(args)", ARG2, 4*sizeof(Addr) ); + ML_(generic_PRE_sys_accept)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + } + case VKI_SYS_SENDTO: /* int sendto(int s, const void *msg, int len, unsigned int flags, @@ -629,7 +647,9 @@ POST(sys_socketcall) break; case VKI_SYS_ACCEPT: + case VKI_SYS_ACCEPT4: /* int accept(int s, struct sockaddr *addr, int *addrlen); */ + /* int accept4(int s, struct sockaddr *addr, int *addrlen, int flags); */ r = ML_(generic_POST_sys_accept)( tid, VG_(mk_SysRes_Success)(RES), ARG2_0, ARG2_1, ARG2_2 ); SET_STATUS_from_SysRes(r); @@ -1142,7 +1162,7 @@ PRE(sys_rt_sigreturn) // arch/OS combination, eg. */* (generic), */Linux (Linux only), ?/? // (unknown). -const SyscallTableEntry ML_(syscall_table)[] = { +static SyscallTableEntry syscall_table[] = { // _____(__NR_restart_syscall, sys_restart_syscall), // 0 GENX_(__NR_exit, sys_exit), // 1 GENX_(__NR_fork, sys_fork), // 2 @@ -1191,10 +1211,10 @@ const SyscallTableEntry ML_(syscall_table)[] = { GENX_(__NR_rename, sys_rename), // 38 GENX_(__NR_mkdir, sys_mkdir), // 39 -// _____(__NR_rmdir, sys_rmdir), // 40 + GENX_(__NR_rmdir, sys_rmdir), // 40 GENXY(__NR_dup, sys_dup), // 41 LINXY(__NR_pipe, sys_pipe), // 42 - GENXY(__NR_times, sys_times), // 43 + GENXY(__NR_times, sys_times), // 43 // _____(__NR_prof, sys_prof), // 44 GENX_(__NR_brk, sys_brk), // 45 @@ -1276,7 +1296,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR_olduname, sys_olduname), // 109 // _____(__NR_iopl, sys_iopl), // 110 -// _____(__NR_vhangup, sys_vhangup), // 111 + LINX_(__NR_vhangup, sys_vhangup), // 111 // _____(__NR_idle, sys_idle), // 112 // _____(__NR_vm86, sys_vm86), // 113 GENXY(__NR_wait4, sys_wait4), // 114 @@ -1291,7 +1311,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR_setdomainname, sys_setdomainname), // 121 GENXY(__NR_uname, sys_newuname), // 122 // _____(__NR_modify_ldt, sys_modify_ldt), // 123 -// _____(__NR_adjtimex, sys_adjtimex), // 124 + LINXY(__NR_adjtimex, sys_adjtimex), // 124 GENXY(__NR_mprotect, sys_mprotect), // 125 // _____(__NR_sigprocmask, sys_sigprocmask), // 126 @@ -1336,7 +1356,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max),// 159 LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min),// 160 -// _____(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 + LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 GENXY(__NR_nanosleep, sys_nanosleep), // 162 GENX_(__NR_mremap, sys_mremap), // 163 // _____(__NR_setresuid, sys_setresuid), // 164 @@ -1355,7 +1375,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR_rt_sigpending, sys_rt_sigpending), // 175 LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 176 -// _____(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 177 + LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 177 // _____(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 178 GENXY(__NR_pread64, sys_pread64), // 179 @@ -1372,7 +1392,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { GENX_(__NR_vfork, sys_fork), // 189 treat as fork GENXY(__NR_ugetrlimit, sys_getrlimit), // 190 -// _____(__NR_readahead, sys_readahead), // 191 + LINX_(__NR_readahead, sys_readahead), // 191 // /* #define __NR_mmap2 192 32bit only */ // /* #define __NR_truncate64 193 32bit only */ // /* #define __NR_ftruncate64 194 32bit only */ @@ -1459,7 +1479,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_mq_unlink, sys_mq_unlink), // 263 LINX_(__NR_mq_timedsend, sys_mq_timedsend), // 264 - LINX_(__NR_mq_timedreceive, sys_mq_timedreceive), // 265 + LINXY(__NR_mq_timedreceive, sys_mq_timedreceive), // 265 LINX_(__NR_mq_notify, sys_mq_notify), // 266 LINXY(__NR_mq_getsetattr, sys_mq_getsetattr), // 267 // _____(__NR_kexec_load, sys_kexec_load), // 268 @@ -1491,13 +1511,13 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_set_robust_list, sys_set_robust_list), // 299 LINXY(__NR_get_robust_list, sys_get_robust_list), // 300 // LINX_(__NR_move_pages, sys_ni_syscall), // 301 -// LINX_(__NR_getcpu, sys_ni_syscall), // 302 + LINXY(__NR_getcpu, sys_getcpu), // 302 LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 303 LINX_(__NR_utimensat, sys_utimensat), // 304 LINXY(__NR_signalfd, sys_signalfd), // 305 LINXY(__NR_timerfd_create, sys_timerfd_create), // 306 LINX_(__NR_eventfd, sys_eventfd), // 307 -// LINX_(__NR_sync_file_range2, sys_ni_syscall), // 308 + LINX_(__NR_sync_file_range2, sys_sync_file_range2), // 308 LINX_(__NR_fallocate, sys_fallocate), // 309 // LINXY(__NR_subpage_prot, sys_ni_syscall), // 310 LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 311 @@ -1505,13 +1525,32 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINXY(__NR_signalfd4, sys_signalfd4), // 313 LINX_(__NR_eventfd2, sys_eventfd2), // 314 LINXY(__NR_epoll_create1, sys_epoll_create1), // 315 - // (__NR_dup3, sys_ni_syscall) // 316 - LINXY(__NR_pipe2, sys_pipe2) // 317 - // (__NR_inotify_init1, sys_ni_syscall) // 318 + LINXY(__NR_dup3, sys_dup3), // 316 + LINXY(__NR_pipe2, sys_pipe2), // 317 + LINXY(__NR_inotify_init1, sys_inotify_init1), // 318 + LINXY(__NR_perf_counter_open, sys_perf_counter_open),// 319 + LINXY(__NR_preadv, sys_preadv), // 320 + LINX_(__NR_pwritev, sys_pwritev), // 321 + LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo) // 322 }; -const UInt ML_(syscall_table_size) = - sizeof(ML_(syscall_table)) / sizeof(ML_(syscall_table)[0]); +SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno ) +{ + const UInt syscall_table_size + = sizeof(syscall_table) / sizeof(syscall_table[0]); + + /* Is it in the contiguous initial section of the table? */ + if (sysno < syscall_table_size) { + SyscallTableEntry* sys = &syscall_table[sysno]; + if (sys->before == NULL) + return NULL; /* no entry */ + else + return sys; + } + + /* Can't find a wrapper */ + return NULL; +} #endif // defined(VGP_ppc64_linux) diff --git a/coregrind/m_syswrap/syswrap-x86-darwin.c b/coregrind/m_syswrap/syswrap-x86-darwin.c index 54dac21..1e2e1d8 100644 --- a/coregrind/m_syswrap/syswrap-x86-darwin.c +++ b/coregrind/m_syswrap/syswrap-x86-darwin.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Apple Inc. + Copyright (C) 2005-2010 Apple Inc. Greg Parker gparker@apple.com This program is free software; you can redistribute it and/or diff --git a/coregrind/m_syswrap/syswrap-x86-linux.c b/coregrind/m_syswrap/syswrap-x86-linux.c index bec9c1f..c0a8b2b 100644 --- a/coregrind/m_syswrap/syswrap-x86-linux.c +++ b/coregrind/m_syswrap/syswrap-x86-linux.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -262,6 +262,17 @@ static SysRes do_clone ( ThreadId ptid, ctst->sig_mask = ptst->sig_mask; ctst->tmp_sig_mask = ptst->sig_mask; + /* Start the child with its threadgroup being the same as the + parent's. This is so that any exit_group calls that happen + after the child is created but before it sets its + os_state.threadgroup field for real (in thread_wrapper in + syswrap-linux.c), really kill the new thread. a.k.a this avoids + a race condition in which the thread is unkillable (via + exit_group) because its threadgroup is not set. The race window + is probably only a few hundred or a few thousand cycles long. + See #226116. */ + ctst->os_state.threadgroup = ptst->os_state.threadgroup; + /* We don't really know where the client stack is, because its allocated by the client. The best we can do is look at the memory mappings and try to derive some useful information. We @@ -588,7 +599,7 @@ SysRes write_ldt ( ThreadId tid, void* ptr, UInt bytecount, Int oldmode ) /* If this thread doesn't have an LDT, we'd better allocate it now. */ - if (ldt == (HWord)NULL) { + if (ldt == NULL) { ldt = alloc_zeroed_x86_LDT(); VG_(threads)[tid].arch.vex.guest_LDT = (HWord)ldt; } @@ -1475,6 +1486,13 @@ PRE(sys_socketcall) break; } + case VKI_SYS_ACCEPT4: { + /*int accept(int s, struct sockaddr *add, int *addrlen, int flags)*/ + PRE_MEM_READ( "socketcall.accept4(args)", ARG2, 4*sizeof(Addr) ); + ML_(generic_PRE_sys_accept)( tid, ARG2_0, ARG2_1, ARG2_2 ); + break; + } + case VKI_SYS_SENDTO: /* int sendto(int s, const void *msg, int len, unsigned int flags, @@ -1620,7 +1638,9 @@ POST(sys_socketcall) break; case VKI_SYS_ACCEPT: + case VKI_SYS_ACCEPT4: /* int accept(int s, struct sockaddr *addr, int *addrlen); */ + /* int accept4(int s, struct sockaddr *addr, int *addrlen, int flags); */ r = ML_(generic_POST_sys_accept)( tid, VG_(mk_SysRes_Success)(RES), ARG2_0, ARG2_1, ARG2_2 ); SET_STATUS_from_SysRes(r); @@ -1852,7 +1872,7 @@ POST(sys_syscall223) // arch/OS combination, eg. */* (generic), */Linux (Linux only), ?/? // (unknown). -const SyscallTableEntry ML_(syscall_table)[] = { +static SyscallTableEntry syscall_table[] = { //zz // (restart_syscall) // 0 GENX_(__NR_exit, sys_exit), // 1 GENX_(__NR_fork, sys_fork), // 2 @@ -2001,8 +2021,8 @@ const SyscallTableEntry ML_(syscall_table)[] = { //zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) GENXY(__NR_uname, sys_newuname), // 122 PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 -//zz LINXY(__NR_adjtimex, sys_adjtimex), // 124 -//zz + LINXY(__NR_adjtimex, sys_adjtimex), // 124 + GENXY(__NR_mprotect, sys_mprotect), // 125 LINXY(__NR_sigprocmask, sys_sigprocmask), // 126 //zz // Nb: create_module() was removed 2.4-->2.6 @@ -2048,7 +2068,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max),// 159 LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min),// 160 -//zz //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 */* + LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 GENXY(__NR_nanosleep, sys_nanosleep), // 162 GENX_(__NR_mremap, sys_mremap), // 163 LINX_(__NR_setresuid, sys_setresuid16), // 164 @@ -2126,7 +2146,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { PLAXY(223, sys_syscall223), // 223 // sys_bproc? LINX_(__NR_gettid, sys_gettid), // 224 -//zz // (__NR_readahead, sys_readahead), // 225 */(Linux?) + LINX_(__NR_readahead, sys_readahead), // 225 */Linux LINX_(__NR_setxattr, sys_setxattr), // 226 LINX_(__NR_lsetxattr, sys_lsetxattr), // 227 LINX_(__NR_fsetxattr, sys_fsetxattr), // 228 @@ -2231,20 +2251,20 @@ const SyscallTableEntry ML_(syscall_table)[] = { // LINX_(__NR_unshare, sys_unshare), // 310 LINX_(__NR_set_robust_list, sys_set_robust_list), // 311 LINXY(__NR_get_robust_list, sys_get_robust_list), // 312 -// LINX_(__NR_splice, sys_ni_syscall), // 313 + LINX_(__NR_splice, sys_splice), // 313 LINX_(__NR_sync_file_range, sys_sync_file_range), // 314 // LINX_(__NR_tee, sys_ni_syscall), // 315 // LINX_(__NR_vmsplice, sys_ni_syscall), // 316 // LINX_(__NR_move_pages, sys_ni_syscall), // 317 -// LINX_(__NR_getcpu, sys_ni_syscall), // 318 + LINXY(__NR_getcpu, sys_getcpu), // 318 LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 319 LINX_(__NR_utimensat, sys_utimensat), // 320 LINXY(__NR_signalfd, sys_signalfd), // 321 LINXY(__NR_timerfd_create, sys_timerfd_create), // 322 LINX_(__NR_eventfd, sys_eventfd), // 323 - //LINX_(__NR_fallocate, sys_fallocate), // 324 + LINX_(__NR_fallocate, sys_fallocate), // 324 LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 325 LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 326 @@ -2252,13 +2272,33 @@ const SyscallTableEntry ML_(syscall_table)[] = { LINX_(__NR_eventfd2, sys_eventfd2), // 328 LINXY(__NR_epoll_create1, sys_epoll_create1), // 329 - // (__NR_dup3, sys_ni_syscall) // 330 - LINXY(__NR_pipe2, sys_pipe2) // 331 - // (__NR_inotify_init1, sys_ni_syscall) // 332 + LINXY(__NR_dup3, sys_dup3), // 330 + LINXY(__NR_pipe2, sys_pipe2), // 331 + LINXY(__NR_inotify_init1, sys_inotify_init1), // 332 + LINXY(__NR_preadv, sys_preadv), // 333 + LINX_(__NR_pwritev, sys_pwritev), // 334 + + LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 335 + LINXY(__NR_perf_counter_open, sys_perf_counter_open) // 336 }; -const UInt ML_(syscall_table_size) = - sizeof(ML_(syscall_table)) / sizeof(ML_(syscall_table)[0]); +SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno ) +{ + const UInt syscall_table_size + = sizeof(syscall_table) / sizeof(syscall_table[0]); + + /* Is it in the contiguous initial section of the table? */ + if (sysno < syscall_table_size) { + SyscallTableEntry* sys = &syscall_table[sysno]; + if (sys->before == NULL) + return NULL; /* no entry */ + else + return sys; + } + + /* Can't find a wrapper */ + return NULL; +} #endif // defined(VGP_x86_linux) diff --git a/coregrind/m_threadstate.c b/coregrind/m_threadstate.c index 30a2cf8..d047110 100644 --- a/coregrind/m_threadstate.c +++ b/coregrind/m_threadstate.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_tooliface.c b/coregrind/m_tooliface.c index c59e59b..4bfbce2 100644 --- a/coregrind/m_tooliface.c +++ b/coregrind/m_tooliface.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Nicholas Nethercote + Copyright (C) 2000-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S index 82b7540..3004c5c 100644 --- a/coregrind/m_trampoline.S +++ b/coregrind/m_trampoline.S @@ -7,9 +7,9 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -476,6 +476,151 @@ VG_(trampoline_stuff_end): # undef UD2_1024 # undef UD2_PAGE +/*---------------- ppc32-linux ----------------*/ + +#elif defined(VGP_arm_linux) + +# define UD2_4 .word 0xFFFFFFFF +# define UD2_16 UD2_4 ; UD2_4 ; UD2_4 ; UD2_4 +# define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16 +# define UD2_256 UD2_64 ; UD2_64 ; UD2_64 ; UD2_64 +# define UD2_1024 UD2_256 ; UD2_256 ; UD2_256 ; UD2_256 +# define UD2_PAGE UD2_1024 ; UD2_1024 ; UD2_1024 ; UD2_1024 + + /* a leading page of unexecutable code */ + UD2_PAGE + +.global VG_(trampoline_stuff_start) +VG_(trampoline_stuff_start): + +.global VG_(arm_linux_REDIR_FOR_strlen) +VG_(arm_linux_REDIR_FOR_strlen): + mov r2, r0 + ldrb r0, [r0, #0] @ zero_extendqisi2 + @ lr needed for prologue + cmp r0, #0 + bxeq lr + mov r0, #0 +.L5: + add r0, r0, #1 + ldrb r3, [r0, r2] @ zero_extendqisi2 + cmp r3, #0 + bne .L5 + bx lr + UD2_4 + +//.global VG_(arm_linux_REDIR_FOR_index) +//VG_(arm_linux_REDIR_FOR_index): +// ldrb r3, [r0, #0] @ zero_extendqisi2 +// and r1, r1, #255 +// cmp r3, r1 +// @ lr needed for prologue +// bne .L9 +// bx lr +//.L12: +// ldrb r3, [r0, #1]! @ zero_extendqisi2 +// cmp r3, r1 +// beq .L11 +//.L9: +// cmp r3, #0 +// bne .L12 +// mov r0, #0 +// bx lr +//.L11: +// bx lr +// UD2_4 + +.global VG_(arm_linux_REDIR_FOR_memcpy) +VG_(arm_linux_REDIR_FOR_memcpy): + stmfd sp!, {r4, r5, lr} + subs lr, r2, #0 + mov r5, r0 + beq .L2 + cmp r0, r1 + bls .L4 + add r3, r0, lr + add r1, lr, r1 + cmp lr, #3 + sub r4, r3, #1 + sub r0, r1, #1 + ble .L28 + sub ip, r3, #5 + sub r1, r1, #5 +.L8: + ldrb r3, [r1, #4] @ zero_extendqisi2 + sub lr, lr, #4 + strb r3, [ip, #4] + ldrb r2, [r1, #3] @ zero_extendqisi2 + cmp lr, #3 + strb r2, [ip, #3] + ldrb r3, [r1, #2] @ zero_extendqisi2 + mov r4, ip + strb r3, [ip, #2] + ldrb r2, [r1, #1] @ zero_extendqisi2 + mov r0, r1 + strb r2, [ip, #1] + sub r1, r1, #4 + sub ip, ip, #4 + bgt .L8 + cmp lr, #0 + beq .L2 +.L28: + sub r2, lr, #1 +.L21: + sub r2, r2, #1 + ldrb r3, [r0], #-1 @ zero_extendqisi2 + cmn r2, #1 + strb r3, [r4], #-1 + bne .L21 +.L2: + mov r0, r5 + ldmfd sp!, {r4, r5, pc} +.L4: + bcs .L2 + cmp lr, #3 + mov ip, r0 + ble .L29 +.L19: + ldrb r3, [r1, #0] @ zero_extendqisi2 + sub lr, lr, #4 + strb r3, [ip, #0] + ldrb r2, [r1, #1] @ zero_extendqisi2 + cmp lr, #3 + strb r2, [ip, #1] + ldrb r3, [r1, #2] @ zero_extendqisi2 + strb r3, [ip, #2] + ldrb r2, [r1, #3] @ zero_extendqisi2 + add r1, r1, #4 + strb r2, [ip, #3] + add ip, ip, #4 + bgt .L19 + cmp lr, #0 + beq .L2 +.L29: + sub r2, lr, #1 +.L20: + sub r2, r2, #1 + ldrb r3, [r1], #1 @ zero_extendqisi2 + cmn r2, #1 + strb r3, [ip], #1 + bne .L20 + mov r0, r5 + ldmfd sp!, {r4, r5, pc} + UD2_4 + +.global VG_(trampoline_stuff_end) +VG_(trampoline_stuff_end): + + /* and a trailing page of unexecutable code */ + UD2_PAGE + +# undef UD2_4 +# undef UD2_16 +# undef UD2_64 +# undef UD2_256 +# undef UD2_1024 +# undef UD2_PAGE + /*---------------- ppc32-aix5 ----------------*/ #elif defined(VGP_ppc32_aix5) @@ -827,8 +972,8 @@ VG_(x86_darwin_SUBST_FOR_sigreturn): int $0x80 ud2 -.globl VG_(darwin_REDIR_FOR_strlen) -VG_(darwin_REDIR_FOR_strlen): +.globl VG_(x86_darwin_REDIR_FOR_strlen) +VG_(x86_darwin_REDIR_FOR_strlen): movl 4(%esp), %edx movl %edx, %eax jmp 1f @@ -840,8 +985,8 @@ VG_(darwin_REDIR_FOR_strlen): subl %edx, %eax ret -.globl VG_(darwin_REDIR_FOR_strcat) -VG_(darwin_REDIR_FOR_strcat): +.globl VG_(x86_darwin_REDIR_FOR_strcat) +VG_(x86_darwin_REDIR_FOR_strcat): pushl %esi movl 8(%esp), %esi movl 12(%esp), %ecx @@ -864,8 +1009,8 @@ VG_(darwin_REDIR_FOR_strcat): ret -.globl VG_(darwin_REDIR_FOR_strcmp) -VG_(darwin_REDIR_FOR_strcmp): +.globl VG_(x86_darwin_REDIR_FOR_strcmp) +VG_(x86_darwin_REDIR_FOR_strcmp): movl 4(%esp), %edx movl 8(%esp), %ecx jmp 1f @@ -885,8 +1030,8 @@ VG_(darwin_REDIR_FOR_strcmp): ret -.globl VG_(darwin_REDIR_FOR_strcpy) -VG_(darwin_REDIR_FOR_strcpy): +.globl VG_(x86_darwin_REDIR_FOR_strcpy) +VG_(x86_darwin_REDIR_FOR_strcpy): pushl %ebp movl %esp, %ebp pushl %esi @@ -907,8 +1052,8 @@ VG_(darwin_REDIR_FOR_strcpy): leave ret -.globl VG_(darwin_REDIR_FOR_strlcat) -VG_(darwin_REDIR_FOR_strlcat): +.globl VG_(x86_darwin_REDIR_FOR_strlcat) +VG_(x86_darwin_REDIR_FOR_strlcat): pushl %ebp movl %esp, %ebp pushl %edi @@ -937,7 +1082,7 @@ VG_(darwin_REDIR_FOR_strlcat): 3: movl 12(%ebp), %eax movl %eax, (%esp) - call VG_(darwin_REDIR_FOR_strlen) + call VG_(x86_darwin_REDIR_FOR_strlen) jmp 7f 4: cmpl $1, %esi @@ -978,8 +1123,16 @@ VG_(trampoline_stuff_end): .globl VG_(trampoline_stuff_start) VG_(trampoline_stuff_start): -.globl VG_(darwin_REDIR_FOR_strlen) -VG_(darwin_REDIR_FOR_strlen): +.globl VG_(amd64_darwin_SUBST_FOR_sigreturn) +VG_(amd64_darwin_SUBST_FOR_sigreturn): + /* XXX does this need to have any special form? (cf x86-linux + version) */ + movq $ __NR_DARWIN_FAKE_SIGRETURN, %rax + syscall + ud2 + +.globl VG_(amd64_darwin_REDIR_FOR_strlen) +VG_(amd64_darwin_REDIR_FOR_strlen): movq %rdi, %rax jmp 1f 0: @@ -990,8 +1143,8 @@ VG_(darwin_REDIR_FOR_strlen): subq %rdi, %rax ret -.globl VG_(darwin_REDIR_FOR_strcat) -VG_(darwin_REDIR_FOR_strcat): +.globl VG_(amd64_darwin_REDIR_FOR_strcat) +VG_(amd64_darwin_REDIR_FOR_strcat): movq %rdi, %rdx jmp 1f 0: @@ -1010,8 +1163,8 @@ VG_(darwin_REDIR_FOR_strcat): ret -.globl VG_(darwin_REDIR_FOR_strcmp) -VG_(darwin_REDIR_FOR_strcmp): +.globl VG_(amd64_darwin_REDIR_FOR_strcmp) +VG_(amd64_darwin_REDIR_FOR_strcmp): jmp 1f 0: incq %rdi @@ -1028,8 +1181,8 @@ VG_(darwin_REDIR_FOR_strcmp): subl %edx, %eax ret -.globl VG_(darwin_REDIR_FOR_strcpy) -VG_(darwin_REDIR_FOR_strcpy): +.globl VG_(amd64_darwin_REDIR_FOR_strcpy) +VG_(amd64_darwin_REDIR_FOR_strcpy): pushq %rbp movq %rdi, %rdx movq %rsp, %rbp @@ -1046,8 +1199,8 @@ VG_(darwin_REDIR_FOR_strcpy): movq %rdi, %rax ret -.globl VG_(darwin_REDIR_FOR_strlcat) -VG_(darwin_REDIR_FOR_strlcat): +.globl VG_(amd64_darwin_REDIR_FOR_strlcat) +VG_(amd64_darwin_REDIR_FOR_strlcat): pushq %rbp leaq (%rdx,%rdi), %rax movq %rdi, %rcx @@ -1072,7 +1225,7 @@ VG_(darwin_REDIR_FOR_strlcat): jmp 6f 3: movq %rsi, %rdi - call VG_(darwin_REDIR_FOR_strlen) + call VG_(amd64_darwin_REDIR_FOR_strlen) jmp 7f 4: cmpq $1, %rdi @@ -1095,8 +1248,8 @@ VG_(darwin_REDIR_FOR_strlcat): leave ret -.globl VG_(darwin_REDIR_FOR_arc4random) -VG_(darwin_REDIR_FOR_arc4random): +.globl VG_(amd64_darwin_REDIR_FOR_arc4random) +VG_(amd64_darwin_REDIR_FOR_arc4random): /* not very random, hope dyld won't mind */ movq $0x76616c6772696e64, %rax ret @@ -1114,7 +1267,11 @@ VG_(trampoline_stuff_end): #if defined(VGO_linux) /* Let the linker know we don't need an executable stack */ -.section .note.GNU-stack,"",@progbits +# if defined(VGP_arm_linux) + .section .note.GNU-stack,"",%progbits +# else + .section .note.GNU-stack,"",@progbits +# endif #endif /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c index 39e3e35..2292edc 100644 --- a/coregrind/m_translate.c +++ b/coregrind/m_translate.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -698,7 +698,7 @@ static Bool translations_allowable_from_seg ( NSegment const* seg ) Bool allowR = False; # endif return seg != NULL - && (seg->kind == SkAnonC || seg->kind == SkFileC) + && (seg->kind == SkAnonC || seg->kind == SkFileC || seg->kind == SkShmC) && (seg->hasX || (seg->hasR && allowR)); } @@ -1343,8 +1343,8 @@ Bool VG_(translate) ( ThreadId tid, Char fnname[64] = ""; VG_(get_fnname_w_offset)(addr, fnname, 64); VG_(printf)( - "==== BB %d %s(0x%llx) BBs exec'd %lld ====\n", - VG_(get_bbs_translated)(), fnname, addr, + "==== SB %d [tid %d] %s(0x%llx) SBs exec'd %lld ====\n", + VG_(get_bbs_translated)(), (Int)tid, fnname, addr, bbs_done); } @@ -1510,7 +1510,8 @@ Bool VG_(translate) ( ThreadId tid, VG_(clo_profile_flags) > 0 ? (void*) &VG_(run_innerloop__dispatch_profiled) : (void*) &VG_(run_innerloop__dispatch_unprofiled); -# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# elif defined(VGA_ppc32) || defined(VGA_ppc64) \ + || defined(VGA_arm) vta.dispatch = NULL; # else # error "Unknown arch" diff --git a/coregrind/m_transtab.c b/coregrind/m_transtab.c index c8954eb..4a1547f 100644 --- a/coregrind/m_transtab.c +++ b/coregrind/m_transtab.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -41,6 +41,13 @@ #include "pub_core_aspacemgr.h" #include "pub_core_mallocfree.h" // VG_(out_of_memory_NORETURN) +// JRS FIXME get rid of this somehow +#if defined(VGP_arm_linux) +# include "pub_core_vkiscnums.h" // __ARM_NR_cacheflush +# include "pub_core_syscall.h" // VG_(do_syscallN) +#endif + + /* #define DEBUG_TRANSTAB */ @@ -64,7 +71,7 @@ /* Because each sector contains a hash table of TTEntries, we need to specify the maximum allowable loading, after which the sector is deemed full. */ -#define SECTOR_TT_LIMIT_PERCENT 80 +#define SECTOR_TT_LIMIT_PERCENT 65 /* The sector is deemed full when this many entries are in it. */ #define N_TTES_PER_SECTOR_USABLE \ @@ -200,6 +207,13 @@ static Int youngest_sector = -1; static Int tc_sector_szQ; +/* A list of sector numbers, in the order which they should be + searched to find translations. This is an optimisation to be used + when searching for translations and should not affect + correctness. -1 denotes "no entry". */ +static Int sector_search_order[N_SECTORS]; + + /* Fast helper for the TC. A direct-mapped cache which holds a set of recently used (guest address, host address) pairs. This array is referred to directly from m_dispatch/dispatch-.S. @@ -563,6 +577,44 @@ static Bool sanity_check_eclasses_in_sector ( Sector* sec ) static Bool sanity_check_redir_tt_tc ( void ); static Bool sanity_check_fastcache ( void ); +static Bool sanity_check_sector_search_order ( void ) +{ + Int i, j, nListed; + /* assert the array is the right size */ + vg_assert(N_SECTORS == (sizeof(sector_search_order) + / sizeof(sector_search_order[0]))); + /* Check it's of the form valid_sector_numbers ++ [-1, -1, ..] */ + for (i = 0; i < N_SECTORS; i++) { + if (sector_search_order[i] < 0 || sector_search_order[i] >= N_SECTORS) + break; + } + nListed = i; + for (/* */; i < N_SECTORS; i++) { + if (sector_search_order[i] != -1) + break; + } + if (i != N_SECTORS) + return False; + /* Check each sector number only appears once */ + for (i = 0; i < N_SECTORS; i++) { + if (sector_search_order[i] == -1) + continue; + for (j = i+1; j < N_SECTORS; j++) { + if (sector_search_order[j] == sector_search_order[i]) + return False; + } + } + /* Check that the number of listed sectors equals the number + in use, by counting nListed back down. */ + for (i = 0; i < N_SECTORS; i++) { + if (sectors[i].tc != NULL) + nListed--; + } + if (nListed != 0) + return False; + return True; +} + static Bool sanity_check_all_sectors ( void ) { Int sno; @@ -580,10 +632,13 @@ static Bool sanity_check_all_sectors ( void ) return False; if ( !sanity_check_fastcache() ) return False; + if ( !sanity_check_sector_search_order() ) + return False; return True; } + /*-------------------------------------------------------------*/ /*--- Add/find translations ---*/ /*-------------------------------------------------------------*/ @@ -696,6 +751,9 @@ static void initialiseSector ( Int sno ) Sector* sec; vg_assert(isValidSector(sno)); + { Bool sane = sanity_check_sector_search_order(); + vg_assert(sane); + } sec = §ors[sno]; if (sec->tc == NULL) { @@ -735,6 +793,14 @@ static void initialiseSector ( Int sno ) sec->tt[i].n_tte2ec = 0; } + /* Add an entry in the sector_search_order */ + for (i = 0; i < N_SECTORS; i++) { + if (sector_search_order[i] == -1) + break; + } + vg_assert(i >= 0 && i < N_SECTORS); + sector_search_order[i] = sno; + if (VG_(clo_verbosity) > 2) VG_(message)(Vg_DebugMsg, "TT/TC: initialise sector %d\n", sno); @@ -779,6 +845,14 @@ static void initialiseSector ( Int sno ) } } + /* Sanity check: ensure it is already in + sector_search_order[]. */ + for (i = 0; i < N_SECTORS; i++) { + if (sector_search_order[i] == sno) + break; + } + vg_assert(i >= 0 && i < N_SECTORS); + if (VG_(clo_verbosity) > 2) VG_(message)(Vg_DebugMsg, "TT/TC: recycle sector %d\n", sno); } @@ -787,6 +861,10 @@ static void initialiseSector ( Int sno ) sec->tt_n_inuse = 0; invalidateFastCache(); + + { Bool sane = sanity_check_sector_search_order(); + vg_assert(sane); + } } static void invalidate_icache ( void *ptr, Int nbytes ) @@ -808,12 +886,14 @@ static void invalidate_icache ( void *ptr, Int nbytes ) vg_assert(cls == 32 || cls == 64 || cls == 128); startaddr &= ~(cls - 1); - for (addr = startaddr; addr < endaddr; addr += cls) - asm volatile("dcbst 0,%0" : : "r" (addr)); - asm volatile("sync"); - for (addr = startaddr; addr < endaddr; addr += cls) - asm volatile("icbi 0,%0" : : "r" (addr)); - asm volatile("sync; isync"); + for (addr = startaddr; addr < endaddr; addr += cls) { + __asm__ __volatile__("dcbst 0,%0" : : "r" (addr)); + } + __asm__ __volatile__("sync"); + for (addr = startaddr; addr < endaddr; addr += cls) { + __asm__ __volatile__("icbi 0,%0" : : "r" (addr)); + } + __asm__ __volatile__("sync; isync"); # elif defined(VGA_x86) /* no need to do anything, hardware provides coherence */ @@ -821,6 +901,12 @@ static void invalidate_icache ( void *ptr, Int nbytes ) # elif defined(VGA_amd64) /* no need to do anything, hardware provides coherence */ +# elif defined(VGP_arm_linux) + /* ARM cache flushes are privileged, so we must defer to the kernel. */ + Addr startaddr = (Addr) ptr; + Addr endaddr = startaddr + nbytes; + VG_(do_syscall2)(__NR_ARM_cacheflush, startaddr, endaddr); + # else # error "Unknown ARCH" # endif @@ -971,14 +1057,13 @@ Bool VG_(search_transtab) ( /*OUT*/AddrH* result, kstart = HASH_TT(guest_addr); vg_assert(kstart >= 0 && kstart < N_TTES_PER_SECTOR); - /* Search in all the sectors. Although the order should not matter, - it might be most efficient to search in the order youngest to - oldest. */ - sno = youngest_sector; + /* Search in all the sectors,using sector_search_order[] as a + heuristic guide as to what order to visit the sectors. */ for (i = 0; i < N_SECTORS; i++) { - if (sectors[sno].tc == NULL) - goto notfound; /* sector not in use. */ + sno = sector_search_order[i]; + if (UNLIKELY(sno == -1)) + return False; /* run out of sectors to search */ k = kstart; for (j = 0; j < N_TTES_PER_SECTOR; j++) { @@ -992,6 +1077,14 @@ Bool VG_(search_transtab) ( /*OUT*/AddrH* result, §ors[sno].tt[k].count ); if (result) *result = (AddrH)sectors[sno].tt[k].tcptr; + /* pull this one one step closer to the front. For large + apps this more or less halves the number of required + probes. */ + if (i > 0) { + Int tmp = sector_search_order[i-1]; + sector_search_order[i-1] = sector_search_order[i]; + sector_search_order[i] = tmp; + } return True; } if (sectors[sno].tt[k].status == Empty) @@ -1004,10 +1097,6 @@ Bool VG_(search_transtab) ( /*OUT*/AddrH* result, /* If we fall off the end, all entries are InUse and not matching, or Deleted. In any case we did not find it in this sector. */ - - notfound: - /* move to the next oldest sector */ - sno = sno==0 ? (N_SECTORS-1) : (sno-1); } /* Not found in any sector. */ @@ -1483,6 +1572,10 @@ void VG_(init_tt_tc) ( void ) } } + /* Initialise the sector_search_order hint table. */ + for (i = 0; i < N_SECTORS; i++) + sector_search_order[i] = -1; + /* Initialise the fast caches. If not profiling (the usual case), we have to explicitly invalidate the fastN cache as invalidateFastCache() won't do that for us. */ diff --git a/coregrind/m_ume/elf.c b/coregrind/m_ume/elf.c index fab5a95..441d974 100644 --- a/coregrind/m_ume/elf.c +++ b/coregrind/m_ume/elf.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/m_ume/macho.c b/coregrind/m_ume/macho.c index 4f42ea6..72f26b3 100644 --- a/coregrind/m_ume/macho.c +++ b/coregrind/m_ume/macho.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Apple Inc. + Copyright (C) 2005-2010 Apple Inc. Greg Parker gparker@apple.com This program is free software; you can redistribute it and/or @@ -73,11 +73,11 @@ static void print(const char *str) VG_(printf)("%s", str); } -static void check_mmap(SysRes res, Addr base, SizeT len) +static void check_mmap(SysRes res, Addr base, SizeT len, HChar* who) { if (sr_isError(res)) { - VG_(printf)("valgrind: mmap(0x%llx, %lld) failed in UME.\n", - (ULong)base, (Long)len); + VG_(printf)("valgrind: mmap(0x%llx, %lld) failed in UME (%s).\n", + (ULong)base, (Long)len, who); VG_(exit)(1); } } @@ -173,6 +173,19 @@ load_segment(int fd, vki_off_t offset, vki_off_t size, // GrP fixme mark __UNIXSTACK as SF_STACK + // Don't honour the client's request to map PAGEZERO. Why not? + // Because when the kernel loaded the valgrind tool executable, + // it will have mapped pagezero itself. So further attempts + // to map it when loading the client are guaranteed to fail. +#if VG_WORDSIZE == 4 + if (segcmd->vmaddr == 0 && 0 == VG_(strcmp)(segcmd->segname, SEG_PAGEZERO)) { + if (segcmd->vmsize != 0x1000) { + print("bad executable (__PAGEZERO is not 4 KB)\n"); + return -1; + } + return 0; + } +#endif #if VG_WORDSIZE == 8 if (segcmd->vmaddr == 0 && 0 == VG_(strcmp)(segcmd->segname, SEG_PAGEZERO)) { if (segcmd->vmsize != 0x100000000) { @@ -213,10 +226,11 @@ load_segment(int fd, vki_off_t offset, vki_off_t size, vmsize = VG_PGROUNDUP(segcmd->vmsize); if (filesize > 0) { addr = (Addr)segcmd->vmaddr; + VG_(debugLog)(2, "ume", "mmap fixed (file) (%#lx, %lu)\n", addr, filesize); res = VG_(am_mmap_named_file_fixed_client)(addr, filesize, prot, fd, offset + segcmd->fileoff, filename); - check_mmap(res, addr, filesize); + check_mmap(res, addr, filesize, "load_segment1"); } // Zero-fill the remainder of the segment, if any @@ -229,8 +243,9 @@ load_segment(int fd, vki_off_t offset, vki_off_t size, // page-aligned part SizeT length = vmsize - filesize; addr = (Addr)(filesize + segcmd->vmaddr); + VG_(debugLog)(2, "ume", "mmap fixed (anon) (%#lx, %lu)\n", addr, length); res = VG_(am_mmap_anon_fixed_client)(addr, length, prot); - check_mmap(res, addr, length); + check_mmap(res, addr, length, "load_segment2"); } return 0; @@ -343,7 +358,7 @@ load_unixthread(vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end, SysRes res; res = VG_(am_mmap_anon_fixed_client)(stackbase, stacksize, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC); - check_mmap(res, stackbase, stacksize); + check_mmap(res, stackbase, stacksize, "load_unixthread1"); if (out_stack_start) *out_stack_start = (vki_uint8_t *)stackbase; } else { // custom stack - mapped via __UNIXTHREAD segment diff --git a/coregrind/m_ume/main.c b/coregrind/m_ume/main.c index fe06c15..e4bfa32 100644 --- a/coregrind/m_ume/main.c +++ b/coregrind/m_ume/main.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -189,7 +189,7 @@ static Bool is_binary_file(Char* f) // Something went wrong. This will only happen if we earlier // succeeded in opening the file but fail here (eg. the file was // deleted between then and now). - VG_(printf)("valgrind: %s: unknown error\n", f); + VG_(fmsg)("%s: unknown error\n", f); VG_(exit)(126); // 126 == NOEXEC } } @@ -210,7 +210,7 @@ static Int do_exec_shell_followup(Int ret, HChar* exe_name, ExeInfo* info) // Is it a binary file? if (is_binary_file(exe_name)) { - VG_(printf)("valgrind: %s: cannot execute binary file\n", exe_name); + VG_(fmsg)("%s: cannot execute binary file\n", exe_name); VG_(exit)(126); // 126 == NOEXEC } @@ -226,7 +226,7 @@ static Int do_exec_shell_followup(Int ret, HChar* exe_name, ExeInfo* info) if (0 != ret) { // Something went wrong with executing the default interpreter - VG_(printf)("valgrind: %s: bad interpreter (%s): %s\n", + VG_(fmsg)("%s: bad interpreter (%s): %s\n", exe_name, info->interp_name, VG_(strerror)(ret)); VG_(exit)(126); // 126 == NOEXEC } @@ -238,21 +238,20 @@ static Int do_exec_shell_followup(Int ret, HChar* exe_name, ExeInfo* info) // Was it a directory? res = VG_(stat)(exe_name, &st); if (!sr_isError(res) && VKI_S_ISDIR(st.mode)) { - VG_(printf)("valgrind: %s: is a directory\n", exe_name); + VG_(fmsg)("%s: is a directory\n", exe_name); // Was it not executable? } else if (0 != VG_(check_executable)(NULL, exe_name, False/*allow_setuid*/)) { - VG_(printf)("valgrind: %s: %s\n", exe_name, VG_(strerror)(ret)); + VG_(fmsg)("%s: %s\n", exe_name, VG_(strerror)(ret)); // Did it start with "#!"? If so, it must have been a bad interpreter. } else if (is_hash_bang_file(exe_name)) { - VG_(printf)("valgrind: %s: bad interpreter: %s\n", - exe_name, VG_(strerror)(ret)); + VG_(fmsg)("%s: bad interpreter: %s\n", exe_name, VG_(strerror)(ret)); // Otherwise it was something else. } else { - VG_(printf)("valgrind: %s: %s\n", exe_name, VG_(strerror)(ret)); + VG_(fmsg)("%s: %s\n", exe_name, VG_(strerror)(ret)); } // 126 means NOEXEC; I think this is Posix, and that in some cases we // should be returning 127, meaning NOTFOUND. Oh well. diff --git a/coregrind/m_ume/script.c b/coregrind/m_ume/script.c index 83a250e..13ca991 100644 --- a/coregrind/m_ume/script.c +++ b/coregrind/m_ume/script.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -35,6 +35,8 @@ #include "pub_core_libcassert.h" // VG_(exit), vg_assert #include "pub_core_libcfile.h" // VG_(close) et al #include "pub_core_libcprint.h" +#include "pub_core_xarray.h" +#include "pub_core_clientstate.h" #include "pub_core_mallocfree.h" // VG_(strdup) #include "pub_core_ume.h" // self @@ -133,6 +135,8 @@ Int VG_(load_script)(Int fd, const HChar* name, ExeInfo* info) if (info->argv && info->argv[0] != NULL) info->argv[0] = (char *)name; + VG_(args_the_exename) = name; + if (0) VG_(printf)("#! script: interp_name=\"%s\" interp_args=\"%s\"\n", info->interp_name, info->interp_args); diff --git a/coregrind/m_vki.c b/coregrind/m_vki.c index 567b9ee..3f1de29 100644 --- a/coregrind/m_vki.c +++ b/coregrind/m_vki.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/m_vkiscnums.c b/coregrind/m_vkiscnums.c index 1462c8a..69cb609 100644 --- a/coregrind/m_vkiscnums.c +++ b/coregrind/m_vkiscnums.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -1178,12 +1178,11 @@ Char* VG_(sysnum_string)(Word sysnum, SizeT n_buf, Char* buf) { Char* classname = NULL; switch (VG_DARWIN_SYSNO_CLASS(sysnum)) { - case VG_DARWIN_SYSCALL_CLASS_MACH: classname = "mach"; break; - case VG_DARWIN_SYSCALL_CLASS_UNIX: classname = "unix"; break; - case VG_DARWIN_SYSCALL_CLASS_MDEP: classname = "mdep"; break; - case VG_DARWIN_SYSCALL_CLASS_DIAG: classname = "diag"; break; - default: - VG_(core_panic)("unknown Darwin sysnum class"); + case VG_DARWIN_SYSCALL_CLASS_MACH: classname = "mach"; break; + case VG_DARWIN_SYSCALL_CLASS_UNIX: classname = "unix"; break; + case VG_DARWIN_SYSCALL_CLASS_MDEP: classname = "mdep"; break; + case VG_DARWIN_SYSCALL_CLASS_DIAG: classname = "diag"; break; + default: classname = "UNKNOWN"; break; } VG_(snprintf)(buf, n_buf, "%s:%3ld", classname, VG_DARWIN_SYSNO_INDEX(sysnum)); diff --git a/coregrind/m_wordfm.c b/coregrind/m_wordfm.c index a10ea90..3047f90 100644 --- a/coregrind/m_wordfm.c +++ b/coregrind/m_wordfm.c @@ -9,13 +9,13 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2007-2009 Julian Seward + Copyright (C) 2007-2010 Julian Seward jseward@acm.org This code is based on previous work by Nicholas Nethercote (coregrind/m_oset.c) which is - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org which in turn was derived partially from: diff --git a/coregrind/m_xarray.c b/coregrind/m_xarray.c index eef668b..cdcf978 100644 --- a/coregrind/m_xarray.c +++ b/coregrind/m_xarray.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2007-2009 OpenWorks LLP + Copyright (C) 2007-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -306,6 +306,16 @@ void VG_(dropHeadXA) ( XArray* xao, Word n ) xa->usedsizeE -= n; } +void VG_(getContentsXA_UNSAFE)( XArray* xao, + /*OUT*/void** ctsP, + /*OUT*/Word* usedP ) +{ + struct _XArray* xa = (struct _XArray*)xao; + vg_assert(xa); + *ctsP = (void*)xa->arr; + *usedP = xa->usedsizeE; +} + /* --------- Printeffery --------- */ static void add_char_to_XA ( HChar c, void* opaque ) diff --git a/coregrind/pub_core_aspacehl.h b/coregrind/pub_core_aspacehl.h index c3bf8e4..0ad35ef 100644 --- a/coregrind/pub_core_aspacehl.h +++ b/coregrind/pub_core_aspacehl.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2009-2009 Julian Seward + Copyright (C) 2009-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_aspacemgr.h b/coregrind/pub_core_aspacemgr.h index 974ba31..013ce64 100644 --- a/coregrind/pub_core_aspacemgr.h +++ b/coregrind/pub_core_aspacemgr.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -375,10 +375,10 @@ extern Bool VG_(am_relocate_nooverlap_client)( /*OUT*/Bool* need_discard, #if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) # define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages -# define VG_STACK_ACTIVE_SZB 131072 // 2 or 32 pages +# define VG_STACK_ACTIVE_SZB (4096 * 256) // 1Mb #else # define VG_STACK_GUARD_SZB 8192 // 2 pages -# define VG_STACK_ACTIVE_SZB 65536 // 16 pages +# define VG_STACK_ACTIVE_SZB (4096 * 256) // 1Mb #endif typedef @@ -398,10 +398,10 @@ typedef extern VgStack* VG_(am_alloc_VgStack)( /*OUT*/Addr* initial_sp ); -/* Figure out how many bytes of the stack's active area have not - been used. Used for estimating if we are close to overflowing it. */ - -extern Int VG_(am_get_VgStack_unused_szB)( VgStack* stack ); +/* Figure out how many bytes of the stack's active area have not been + used. Used for estimating if we are close to overflowing it. If + the free area is larger than 'limit', just return 'limit'. */ +extern SizeT VG_(am_get_VgStack_unused_szB)( VgStack* stack, SizeT limit ); // DDD: this is ugly #if defined(VGO_darwin) diff --git a/coregrind/pub_core_basics.h b/coregrind/pub_core_basics.h index eb38f6b..35aba2f 100644 --- a/coregrind/pub_core_basics.h +++ b/coregrind/pub_core_basics.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -56,6 +56,8 @@ # include "libvex_guest_ppc32.h" #elif defined(VGA_ppc64) # include "libvex_guest_ppc64.h" +#elif defined(VGA_arm) +# include "libvex_guest_arm.h" #else # error Unknown arch #endif @@ -63,6 +65,51 @@ // For jmp_buf #include + +/* --------------------------------------------------------------------- + A struct to hold starting values for stack unwinding. + ------------------------------------------------------------------ */ + +/* This really shouldn't be here. But putting it elsewhere leads to a + veritable swamp of new module cycles. */ + +/* To support CFA-based stack unwinding, and stack unwinding in + general, we need to be able to get hold of the values of specific + registers, in order to start the unwinding process. This is + unavoidably arch and platform dependent. Here is a struct which + holds the relevant values. All platforms must have a program + counter and a stack pointer register, but the other fields (frame + pointer? link register? misc other regs?) are ad-hoc. Note, the + common fields are 64-bit, so as to make this host-independent. */ + +typedef + struct { + ULong r_pc; /* x86:EIP, amd64:RIP, ppc:CIA, arm:R15 */ + ULong r_sp; /* x86:ESP, amd64:RSP, ppc:R1, arm:R13 */ + union { + struct { + UInt r_ebp; + } X86; + struct { + ULong r_rbp; + } AMD64; + struct { + UInt r_lr; + } PPC32; + struct { + ULong r_lr; + } PPC64; + struct { + UInt r14; + UInt r12; + UInt r11; + UInt r7; + } ARM; + } misc; + } + UnwindStartRegs; + + #endif // __PUB_CORE_BASICS_H /*--------------------------------------------------------------------*/ diff --git a/coregrind/pub_core_basics_asm.h b/coregrind/pub_core_basics_asm.h index a71e8ff..80ee1a6 100644 --- a/coregrind/pub_core_basics_asm.h +++ b/coregrind/pub_core_basics_asm.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_clientstate.h b/coregrind/pub_core_clientstate.h index 1809074..4742330 100644 --- a/coregrind/pub_core_clientstate.h +++ b/coregrind/pub_core_clientstate.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_clreq.h b/coregrind/pub_core_clreq.h index 563904b..dc349a4 100644 --- a/coregrind/pub_core_clreq.h +++ b/coregrind/pub_core_clreq.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -47,8 +47,11 @@ typedef /* Get the tool's malloc-wrapping functions */ VG_USERREQ__GET_MALLOCFUNCS = 0x3030, - /* Internal equivalent of VALGRIND_PRINTF . */ - VG_USERREQ__INTERNAL_PRINTF = 0x3103, + /* Internal equivalent of VALGRIND_PRINTF_VALIST_BY_REF . */ + VG_USERREQ__INTERNAL_PRINTF_VALIST_BY_REF = 0x3103, + + /* Add a target for an indirect function redirection. */ + VG_USERREQ__ADD_IFUNC_TARGET = 0x3104, } Vg_InternalClientRequest; @@ -64,8 +67,8 @@ static int VALGRIND_INTERNAL_PRINTF(const char *format, ...) va_list vargs; va_start(vargs, format); VALGRIND_DO_CLIENT_REQUEST( - _qzz_res, 0, VG_USERREQ__INTERNAL_PRINTF, - (unsigned long)format, (unsigned long)vargs, 0, 0, 0 + _qzz_res, 0, VG_USERREQ__INTERNAL_PRINTF_VALIST_BY_REF, + (unsigned long)format, (unsigned long)&vargs, 0, 0, 0 ); va_end(vargs); return _qzz_res; diff --git a/coregrind/pub_core_commandline.h b/coregrind/pub_core_commandline.h index aebfe61..80c4c47 100644 --- a/coregrind/pub_core_commandline.h +++ b/coregrind/pub_core_commandline.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_coredump.h b/coregrind/pub_core_coredump.h index e325a42..96d41f8 100644 --- a/coregrind/pub_core_coredump.h +++ b/coregrind/pub_core_coredump.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_cpuid.h b/coregrind/pub_core_cpuid.h index 4712e71..e4bed87 100644 --- a/coregrind/pub_core_cpuid.h +++ b/coregrind/pub_core_cpuid.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_debugger.h b/coregrind/pub_core_debugger.h index 9c224de..e3131a2 100644 --- a/coregrind/pub_core_debugger.h +++ b/coregrind/pub_core_debugger.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_debuginfo.h b/coregrind/pub_core_debuginfo.h index 7d6d776..e4edc0c 100644 --- a/coregrind/pub_core_debuginfo.h +++ b/coregrind/pub_core_debuginfo.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -106,13 +106,32 @@ Bool VG_(get_fnname_raw) ( Addr a, Char* buf, Int nbuf ); extern Bool VG_(get_fnname_no_cxx_demangle) ( Addr a, Char* buf, Int nbuf ); -/* Use DWARF2/3 CFA information to do one step of stack unwinding. */ -extern Bool VG_(use_CF_info) ( /*MOD*/Addr* ipP, - /*MOD*/Addr* spP, - /*MOD*/Addr* fpP, + +/* Use DWARF2/3 CFA information to do one step of stack unwinding. + D3UnwindRegs holds the current register values, and is + arch-specific. Note that the x86 and amd64 definitions are shared + and so the regs are named 'xip' etc rather than 'eip' and 'rip'. */ +#if defined(VGA_amd64) || defined(VGA_x86) +typedef + struct { Addr xip; Addr xsp; Addr xbp; } + D3UnwindRegs; +#elif defined(VGA_arm) +typedef + struct { Addr r15; Addr r14; Addr r13; Addr r12; Addr r11; Addr r7; } + D3UnwindRegs; +#elif defined(VGA_ppc32) || defined(VGA_ppc64) +typedef + UChar /* should be void, but gcc complains at use points */ + D3UnwindRegs; +#else +# error "Unsupported arch" +#endif + +extern Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregs, Addr min_accessible, Addr max_accessible ); + /* Use MSVC FPO data to do one step of stack unwinding. */ extern Bool VG_(use_FPO_info) ( /*MOD*/Addr* ipP, /*MOD*/Addr* spP, diff --git a/coregrind/pub_core_debuglog.h b/coregrind/pub_core_debuglog.h index 489aa0c..9cdcd61 100644 --- a/coregrind/pub_core_debuglog.h +++ b/coregrind/pub_core_debuglog.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -69,9 +69,9 @@ Int VG_(debugLog_getLevel) ( void ); /* Send debugging output. Nothing happens unless 'level' does not exceed the logging threshold level. */ extern -__attribute__((format(__printf__, 3, 4))) void VG_(debugLog) ( Int level, const HChar* modulename, - const HChar* format, ... ); + const HChar* format, ... ) + __attribute__((format(__printf__, 3, 4))); /* A simple vprintf(). For each emitted byte, (*send_fn) is called with diff --git a/coregrind/pub_core_demangle.h b/coregrind/pub_core_demangle.h index bac72c0..71cc4c3 100644 --- a/coregrind/pub_core_demangle.h +++ b/coregrind/pub_core_demangle.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_dispatch.h b/coregrind/pub_core_dispatch.h index e4aa11c..8deaeca 100644 --- a/coregrind/pub_core_dispatch.h +++ b/coregrind/pub_core_dispatch.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -68,8 +68,8 @@ UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling ); following somewhat bogus decls. At least on x86 and amd64. ppc32 and ppc64 use straightforward bl-blr to get from dispatcher to translation and back and so do not need these labels. */ -extern void VG_(run_innerloop__dispatch_unprofiled); -extern void VG_(run_innerloop__dispatch_profiled); +extern Addr VG_(run_innerloop__dispatch_unprofiled); +extern Addr VG_(run_innerloop__dispatch_profiled); #endif @@ -86,7 +86,7 @@ extern void VG_(run_a_noredir_translation) ( volatile UWord* argblock ); /* We need to a label inside VG_(run_a_noredir_translation), so that Vex can add branches to them from generated code. Hence the following somewhat bogus decl. */ -extern void VG_(run_a_noredir_translation__return_point); +extern Addr VG_(run_a_noredir_translation__return_point); #endif diff --git a/coregrind/pub_core_dispatch_asm.h b/coregrind/pub_core_dispatch_asm.h index c1af70a..d08183b 100644 --- a/coregrind/pub_core_dispatch_asm.h +++ b/coregrind/pub_core_dispatch_asm.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_errormgr.h b/coregrind/pub_core_errormgr.h index 6ceeb9b..2b72b03 100644 --- a/coregrind/pub_core_errormgr.h +++ b/coregrind/pub_core_errormgr.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_execontext.h b/coregrind/pub_core_execontext.h index 3cb2ae0..713500e 100644 --- a/coregrind/pub_core_execontext.h +++ b/coregrind/pub_core_execontext.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_hashtable.h b/coregrind/pub_core_hashtable.h index f0d2ab2..4c9c22f 100644 --- a/coregrind/pub_core_hashtable.h +++ b/coregrind/pub_core_hashtable.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_initimg.h b/coregrind/pub_core_initimg.h index 3d61831..e6b7be5 100644 --- a/coregrind/pub_core_initimg.h +++ b/coregrind/pub_core_initimg.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_libcassert.h b/coregrind/pub_core_libcassert.h index 5be3516..3512100 100644 --- a/coregrind/pub_core_libcassert.h +++ b/coregrind/pub_core_libcassert.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -63,8 +63,7 @@ __attribute__ ((__noreturn__)) extern void VG_(core_panic) ( Char* str ); __attribute__ ((__noreturn__)) -extern void VG_(core_panic_at) ( Char* str, - Addr ip, Addr sp, Addr fp, Addr lr ); +extern void VG_(core_panic_at) ( Char* str, UnwindStartRegs* ); /* Called when some unhandleable client behaviour is detected. Prints a msg and aborts. */ diff --git a/coregrind/pub_core_libcbase.h b/coregrind/pub_core_libcbase.h index d8d5f17..4c89627 100644 --- a/coregrind/pub_core_libcbase.h +++ b/coregrind/pub_core_libcbase.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_libcfile.h b/coregrind/pub_core_libcfile.h index 548f1b4..ba8ed8b 100644 --- a/coregrind/pub_core_libcfile.h +++ b/coregrind/pub_core_libcfile.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_libcprint.h b/coregrind/pub_core_libcprint.h index c043c2d..5692972 100644 --- a/coregrind/pub_core_libcprint.h +++ b/coregrind/pub_core_libcprint.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -54,6 +54,16 @@ extern OutputSink VG_(xml_output_sink); m_main during startup. */ void VG_(elapsed_wallclock_time) ( /*OUT*/HChar* buf ); +/* Call this if the executable is missing. This function prints an + error message, then shuts down the entire system. */ +__attribute__((noreturn)) +extern void VG_(err_missing_prog) ( void ); + +/* Similarly - complain and stop if there is some kind of config + error. */ +__attribute__((noreturn)) +extern void VG_(err_config_error) ( Char* msg ); + #endif // __PUB_CORE_LIBCPRINT_H /*--------------------------------------------------------------------*/ diff --git a/coregrind/pub_core_libcproc.h b/coregrind/pub_core_libcproc.h index 549f250..9e6ab99 100644 --- a/coregrind/pub_core_libcproc.h +++ b/coregrind/pub_core_libcproc.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_libcsignal.h b/coregrind/pub_core_libcsignal.h index 684ab00..d82eb36 100644 --- a/coregrind/pub_core_libcsignal.h +++ b/coregrind/pub_core_libcsignal.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h index 1a9cfe2..19fe3d8 100644 --- a/coregrind/pub_core_machine.h +++ b/coregrind/pub_core_machine.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -60,6 +60,11 @@ # define VG_ELF_MACHINE EM_PPC64 # define VG_ELF_CLASS ELFCLASS64 # define VG_PLAT_USES_PPCTOC 1 +#elif defined(VGP_arm_linux) +# define VG_ELF_DATA2XXX ELFDATA2LSB +# define VG_ELF_MACHINE EM_ARM +# define VG_ELF_CLASS ELFCLASS32 +# undef VG_PLAT_USES_PPCTOC #elif defined(VGO_aix5) # undef VG_ELF_DATA2XXX # undef VG_ELF_MACHINE @@ -90,6 +95,10 @@ # define VG_INSTR_PTR guest_CIA # define VG_STACK_PTR guest_GPR1 # define VG_FRAME_PTR guest_GPR1 // No frame ptr for PPC +#elif defined(VGA_arm) +# define VG_INSTR_PTR guest_R15T +# define VG_STACK_PTR guest_R13 +# define VG_FRAME_PTR guest_R11 #else # error Unknown arch #endif @@ -100,6 +109,25 @@ #define VG_O_INSTR_PTR (offsetof(VexGuestArchState, VG_INSTR_PTR)) +//------------------------------------------------------------- +// Guest state accessors that are not visible to tools. The only +// ones that are visible are get_IP and get_SP. + +//Addr VG_(get_IP) ( ThreadId tid ); // in pub_tool_machine.h +//Addr VG_(get_SP) ( ThreadId tid ); // in pub_tool_machine.h +Addr VG_(get_FP) ( ThreadId tid ); + +void VG_(set_IP) ( ThreadId tid, Addr encip ); +void VG_(set_SP) ( ThreadId tid, Addr sp ); + + +//------------------------------------------------------------- +// Get hold of the values needed for a stack unwind, for the specified +// (client) thread. +void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs, + ThreadId tid ); + + //------------------------------------------------------------- /* Details about the capabilities of the underlying (host) CPU. These details are acquired by (1) enquiring with the CPU at startup, or @@ -130,6 +158,11 @@ then safe to use VG_(machine_get_VexArchInfo) and VG_(machine_ppc64_has_VMX) + ------------- + arm: initially: call VG_(machine_get_hwcaps) + call VG_(machine_arm_set_has_NEON) + + then safe to use VG_(machine_get_VexArchInfo) VG_(machine_get_hwcaps) may use signals (although it attempts to leave signal state unchanged) and therefore should only be @@ -154,6 +187,10 @@ extern void VG_(machine_ppc32_set_clszB)( Int ); extern void VG_(machine_ppc64_set_clszB)( Int ); #endif +#if defined(VGA_arm) +extern void VG_(machine_arm_set_has_NEON)( Bool ); +#endif + /* X86: set to 1 if the host is able to do {ld,st}mxcsr (load/store the SSE control/status register), else zero. Is referenced from assembly code, so do not change from a 32-bit int. */ @@ -182,6 +219,10 @@ extern UInt VG_(machine_ppc32_has_VMX); extern ULong VG_(machine_ppc64_has_VMX); #endif +#if defined(VGA_arm) +extern Int VG_(machine_arm_archlevel); +#endif + #endif // __PUB_CORE_MACHINE_H /*--------------------------------------------------------------------*/ diff --git a/coregrind/pub_core_mallocfree.h b/coregrind/pub_core_mallocfree.h index 1af3880..e4c5303 100644 --- a/coregrind/pub_core_mallocfree.h +++ b/coregrind/pub_core_mallocfree.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -71,7 +71,7 @@ typedef Int ArenaId; // greater than 8. #if defined(VGP_x86_linux) || \ defined(VGP_ppc32_linux) || \ - defined(VGP_ppc32_aix5) + defined(VGP_arm_linux) # define VG_MIN_MALLOC_SZB 8 // Nb: We always use 16 bytes for Darwin, even on 32-bits, so it can be used // for any AltiVec- or SSE-related type. This matches the Darwin libc. @@ -80,6 +80,7 @@ typedef Int ArenaId; defined(VGP_ppc64_aix5) || \ defined(VGP_x86_freebsd) || \ defined(VGP_amd64_freebsd) || \ + defined(VGP_ppc32_aix5) || \ defined(VGP_x86_darwin) || \ defined(VGP_amd64_darwin) # define VG_MIN_MALLOC_SZB 16 diff --git a/coregrind/pub_core_options.h b/coregrind/pub_core_options.h index 37242b5..06b5701 100644 --- a/coregrind/pub_core_options.h +++ b/coregrind/pub_core_options.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -42,6 +42,12 @@ /* The max number of suppression files. */ #define VG_CLO_MAX_SFILES 100 +/* The max number of --require-text-symbol= specification strings. */ +#define VG_CLO_MAX_REQ_TSYMS 100 + +/* The max number of --fullpath-after= parameters. */ +#define VG_CLO_MAX_FULLPATH_AFTER 100 + /* Should we stop collecting errors if too many appear? default: YES */ extern Bool VG_(clo_error_limit); /* Alternative exit code to hand to parent if errors were found. @@ -61,6 +67,9 @@ extern Int VG_(clo_sanity_level); extern Bool VG_(clo_demangle); /* Simulate child processes? default: NO */ extern Bool VG_(clo_trace_children); +/* String containing comma-separated patterns for executable names + that should not be traced into even when --trace-children=yes */ +extern HChar* VG_(clo_trace_children_skip); /* After a fork, the child's output can become confusingly intermingled with the parent's output. This is especially problematic when VG_(clo_xml) is True. Setting @@ -79,11 +88,16 @@ extern Bool VG_(clo_time_stamp); /* The file descriptor to read for input. default: 0 == stdin */ extern Int VG_(clo_input_fd); + /* The number of suppression files specified. */ extern Int VG_(clo_n_suppressions); /* The names of the suppression files. */ extern Char* VG_(clo_suppressions)[VG_CLO_MAX_SFILES]; +/* An array of strings harvested from --fullpath-after= flags. */ +extern Int VG_(clo_n_fullpath_after); +extern Char* VG_(clo_fullpath_after)[VG_CLO_MAX_FULLPATH_AFTER]; + /* DEBUG: print generated code? default: 00000000 ( == NO ) */ extern UChar VG_(clo_trace_flags); /* DEBUG: do bb profiling? default: 00000000 ( == NO ) */ @@ -121,6 +135,41 @@ extern Char* VG_(clo_sim_hints); extern Bool VG_(clo_sym_offsets); /* Read DWARF3 variable info even if tool doesn't ask for it? */ extern Bool VG_(clo_read_var_info); +/* Which prefix to strip from full source file paths, if any. */ +extern Char* VG_(clo_prefix_to_strip); + +/* An array of strings harvested from --require-text-symbol= + flags. + + Each string specifies a pair: a soname pattern and a text symbol + name pattern, separated by a colon. The patterns can be written + using the normal "?" and "*" wildcards. For example: + ":*libc.so*:foo?bar". + + These flags take effect when reading debuginfo from objects. If an + object is loaded and the object's soname matches the soname + component of one of the specified pairs, then Valgrind will examine + all the text symbol names in the object. If none of them match the + symbol name component of that same specification, then the run is + aborted, with an error message. + + The purpose of this is to support reliable usage of marked-up + libraries. For example, suppose we have a version of GCC's + libgomp.so which has been marked up with annotations to support + Helgrind. It is only too easy and confusing to load the 'wrong' + libgomp.so into the application. So the idea is: add a text symbol + in the marked-up library (eg), "annotated_for_helgrind_3_6", and + then give the flag + + --require-text-symbol=:*libgomp*so*:annotated_for_helgrind_3_6 + + so that when libgomp.so is loaded, we scan the symbol table, and if + the symbol isn't present the run is aborted, rather than continuing + silently with the un-marked-up library. Note that you should put + the entire flag in quotes to stop shells messing up the * and ? + wildcards. */ +extern Int VG_(clo_n_req_tsyms); +extern HChar* VG_(clo_req_tsyms)[VG_CLO_MAX_REQ_TSYMS]; /* Track open file descriptors? */ extern Bool VG_(clo_track_fds); @@ -170,18 +219,10 @@ extern HChar* VG_(clo_kernel_variant); .dSYM directories as necessary? */ extern Bool VG_(clo_dsymutil); -/* --------- Functions --------- */ - -/* Call this if the executable is missing. This function prints an - error message, then shuts down the entire system. */ -__attribute__((noreturn)) -extern void VG_(err_missing_prog) ( void ); - -/* Similarly - complain and stop if there is some kind of config - error. */ -__attribute__((noreturn)) -extern void VG_(err_config_error) ( Char* msg ); - +/* Should we trace into this child executable (across execve etc) ? + This involves considering --trace-children=, --trace-children-skip= + and the name of the executable. */ +extern Bool VG_(should_we_trace_this_child) ( HChar* child_exe_name ); #endif // __PUB_CORE_OPTIONS_H diff --git a/coregrind/pub_core_oset.h b/coregrind/pub_core_oset.h index d178b7c..8bff1ab 100644 --- a/coregrind/pub_core_oset.h +++ b/coregrind/pub_core_oset.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_redir.h b/coregrind/pub_core_redir.h index c993c27..8bd12f7 100644 --- a/coregrind/pub_core_redir.h +++ b/coregrind/pub_core_redir.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -33,12 +33,25 @@ //-------------------------------------------------------------------- // PURPOSE: This module deals with: +// // - code replacement: intercepting calls to client functions, and // pointing them to a different piece of code. +// // - loading notification: telling the core where certain client-space // functions are when they get loaded. +// // - function wrapping: add calls to code before and after client // functions execute, for inspection and/or modification. +// +// - checking of --require-text-symbol= specifications: when a new +// object is loaded, its symbol table is examined, and if a symbol +// (as required by the specifications) is not found then the run +// is aborted. See comment by VG_(clo_n_req_tsyms) in +// pub_core_options.h for background. This doesn't have anything +// to do with function intercepting or wrapping, but it does have +// to do with examining all symbols at object load time, so this +// module seems like a logical place to put it. +// //-------------------------------------------------------------------- #include "pub_tool_redir.h" @@ -58,6 +71,8 @@ extern void VG_(redir_notify_delete_DebugInfo)( DebugInfo* ); /* Initialise the module, and load initial "hardwired" redirects. */ extern void VG_(redir_initialise)( void ); +/* Notify the module of a new target for an indirect function. */ +extern void VG_(redir_add_ifunc_target)( Addr old_from, Addr new_from ); //-------------------------------------------------------------------- // Queries diff --git a/coregrind/pub_core_replacemalloc.h b/coregrind/pub_core_replacemalloc.h index 1561c20..7a6b26d 100644 --- a/coregrind/pub_core_replacemalloc.h +++ b/coregrind/pub_core_replacemalloc.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_scheduler.h b/coregrind/pub_core_scheduler.h index b295a13..73773d7 100644 --- a/coregrind/pub_core_scheduler.h +++ b/coregrind/pub_core_scheduler.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_seqmatch.h b/coregrind/pub_core_seqmatch.h index c2391f8..04f21e6 100644 --- a/coregrind/pub_core_seqmatch.h +++ b/coregrind/pub_core_seqmatch.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_sigframe.h b/coregrind/pub_core_sigframe.h index 818b261..db6f441 100644 --- a/coregrind/pub_core_sigframe.h +++ b/coregrind/pub_core_sigframe.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_signals.h b/coregrind/pub_core_signals.h index 92875bd..10182bc 100644 --- a/coregrind/pub_core_signals.h +++ b/coregrind/pub_core_signals.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_sparsewa.h b/coregrind/pub_core_sparsewa.h index c382ef9..33a0901 100644 --- a/coregrind/pub_core_sparsewa.h +++ b/coregrind/pub_core_sparsewa.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_stacks.h b/coregrind/pub_core_stacks.h index ffa2db7..97e39ba 100644 --- a/coregrind/pub_core_stacks.h +++ b/coregrind/pub_core_stacks.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_stacktrace.h b/coregrind/pub_core_stacktrace.h index 201bccf..6181405 100644 --- a/coregrind/pub_core_stacktrace.h +++ b/coregrind/pub_core_stacktrace.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -53,8 +53,8 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, /*OUT*/Addr* ips, UInt n_ips, /*OUT*/Addr* sps, /*OUT*/Addr* fps, - Addr ip, Addr sp, Addr fp, Addr lr, - Addr fp_min, Addr fp_max_orig ); + UnwindStartRegs* startRegs, + Addr fp_max_orig ); #endif // __PUB_CORE_STACKTRACE_H diff --git a/coregrind/pub_core_syscall.h b/coregrind/pub_core_syscall.h index db1086b..959601b 100644 --- a/coregrind/pub_core_syscall.h +++ b/coregrind/pub_core_syscall.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -75,6 +75,7 @@ extern SysRes VG_(mk_SysRes_ppc32_linux) ( UInt val, UInt cr0so ); extern SysRes VG_(mk_SysRes_ppc64_linux) ( ULong val, ULong cr0so ); extern SysRes VG_(mk_SysRes_x86_freebsd) ( UInt val, UInt val2, Bool err); extern SysRes VG_(mk_SysRes_amd64_freebsd)( ULong val, ULong val2, Bool err ); +extern SysRes VG_(mk_SysRes_arm_linux) ( Int val ); extern SysRes VG_(mk_SysRes_ppc32_aix5) ( UInt val, UInt err ); extern SysRes VG_(mk_SysRes_ppc64_aix5) ( ULong val, ULong err ); extern SysRes VG_(mk_SysRes_x86_darwin) ( UChar scclass, Bool isErr, diff --git a/coregrind/pub_core_syswrap.h b/coregrind/pub_core_syswrap.h index 43428f6..f3ba464 100644 --- a/coregrind/pub_core_syswrap.h +++ b/coregrind/pub_core_syswrap.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_threadstate.h b/coregrind/pub_core_threadstate.h index 51b4adf..3e63da1 100644 --- a/coregrind/pub_core_threadstate.h +++ b/coregrind/pub_core_threadstate.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -83,6 +83,8 @@ typedef typedef VexGuestPPC32State VexGuestArchState; #elif defined(VGA_ppc64) typedef VexGuestPPC64State VexGuestArchState; +#elif defined(VGA_arm) + typedef VexGuestARMState VexGuestArchState; #else # error Unknown architecture #endif diff --git a/coregrind/pub_core_tooliface.h b/coregrind/pub_core_tooliface.h index e578505..946f323 100644 --- a/coregrind/pub_core_tooliface.h +++ b/coregrind/pub_core_tooliface.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_trampoline.h b/coregrind/pub_core_trampoline.h index c4535e9..1059337 100644 --- a/coregrind/pub_core_trampoline.h +++ b/coregrind/pub_core_trampoline.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -53,8 +53,8 @@ readable, at least. Otherwise Memcheck complains we're jumping to invalid addresses. */ -extern void VG_(trampoline_stuff_start); -extern void VG_(trampoline_stuff_end); +extern Addr VG_(trampoline_stuff_start); +extern Addr VG_(trampoline_stuff_end); #if defined(VGP_x86_freebsd) extern void VG_(x86_freebsd_SUBST_FOR_sigreturn); @@ -65,28 +65,28 @@ extern void VG_(amd64_freebsd_SUBST_FOR_sigreturn); #endif #if defined(VGP_x86_linux) -extern void VG_(x86_linux_SUBST_FOR_sigreturn); -extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn); +extern Addr VG_(x86_linux_SUBST_FOR_sigreturn); +extern Addr VG_(x86_linux_SUBST_FOR_rt_sigreturn); extern Char* VG_(x86_linux_REDIR_FOR_index) ( const Char*, Int ); #endif #if defined(VGP_amd64_linux) -extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn); -extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday); -extern void VG_(amd64_linux_REDIR_FOR_vtime); +extern Addr VG_(amd64_linux_SUBST_FOR_rt_sigreturn); +extern Addr VG_(amd64_linux_REDIR_FOR_vgettimeofday); +extern Addr VG_(amd64_linux_REDIR_FOR_vtime); extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* ); #endif #if defined(VGP_ppc32_linux) -extern void VG_(ppc32_linux_SUBST_FOR_sigreturn); -extern void VG_(ppc32_linux_SUBST_FOR_rt_sigreturn); +extern Addr VG_(ppc32_linux_SUBST_FOR_sigreturn); +extern Addr VG_(ppc32_linux_SUBST_FOR_rt_sigreturn); extern UInt VG_(ppc32_linux_REDIR_FOR_strlen)( void* ); extern UInt VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* ); extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int ); #endif #if defined(VGP_ppc64_linux) -extern void VG_(ppc64_linux_SUBST_FOR_rt_sigreturn); +extern Addr VG_(ppc64_linux_SUBST_FOR_rt_sigreturn); extern UInt VG_(ppc64_linux_REDIR_FOR_strlen)( void* ); extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int ); /* A label (sans dot) marking the ultra-magical return stub via which @@ -96,7 +96,13 @@ extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int ); restore the thread's LR and R2 registers from a small stack in the ppc64 guest state structure, and then branch to LR. Convoluted? Confusing? You betcha. Could I think of anything simpler? No. */ -extern void VG_(ppctoc_magic_redirect_return_stub); +extern Addr VG_(ppctoc_magic_redirect_return_stub); +#endif + +#if defined(VGP_arm_linux) +extern UInt VG_(arm_linux_REDIR_FOR_strlen)( void* ); +//extern void* VG_(arm_linux_REDIR_FOR_index) ( void*, Int ); +extern void* VG_(arm_linux_REDIR_FOR_memcpy)( void*, void*, Int ); #endif #if defined(VGP_ppc32_aix5) @@ -107,28 +113,39 @@ extern void VG_(ppctoc_magic_redirect_return_stub); then it cleans up the register state to be more what it really should be at client startup, and finally it jumps to the client's real entry point. */ -extern void VG_(ppc32_aix5_do_preloads_then_start_client); +extern Addr VG_(ppc32_aix5_do_preloads_then_start_client); /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */ -extern void VG_(ppctoc_magic_redirect_return_stub); +extern Addr VG_(ppctoc_magic_redirect_return_stub); #endif #if defined(VGP_ppc64_aix5) /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */ -extern void VG_(ppctoc_magic_redirect_return_stub); +extern Addr VG_(ppctoc_magic_redirect_return_stub); /* See comment for ppc32_aix5 equivalent above. */ -extern void VG_(ppc64_aix5_do_preloads_then_start_client); +extern Addr VG_(ppc64_aix5_do_preloads_then_start_client); +#endif + +#if defined(VGP_x86_darwin) +extern Addr VG_(x86_darwin_SUBST_FOR_sigreturn); +extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* ); +extern SizeT VG_(x86_darwin_REDIR_FOR_strcmp)( void*, void* ); +extern void* VG_(x86_darwin_REDIR_FOR_strcat)( void*, void * ); +extern char* VG_(x86_darwin_REDIR_FOR_strcpy)( char *s1, char *s2 ); +extern SizeT VG_(x86_darwin_REDIR_FOR_strlcat)( char *s1, const char *s2, + SizeT size ); #endif -#if defined(VGO_darwin) -extern void VG_(x86_darwin_SUBST_FOR_sigreturn); -extern SizeT VG_(darwin_REDIR_FOR_strlen)( void* ); -extern SizeT VG_(darwin_REDIR_FOR_strcmp)( void*, void* ); -extern void* VG_(darwin_REDIR_FOR_strcat)( void*, void * ); -extern char* VG_(darwin_REDIR_FOR_strcpy)( char *s1, char *s2 ); -extern SizeT VG_(darwin_REDIR_FOR_strlcat)( char *s1, const char *s2, SizeT size ); -extern UInt VG_(darwin_REDIR_FOR_arc4random)( void ); +#if defined(VGP_amd64_darwin) +extern Addr VG_(amd64_darwin_SUBST_FOR_sigreturn); +extern SizeT VG_(amd64_darwin_REDIR_FOR_strlen)( void* ); +extern SizeT VG_(amd64_darwin_REDIR_FOR_strcmp)( void*, void* ); +extern void* VG_(amd64_darwin_REDIR_FOR_strcat)( void*, void * ); +extern char* VG_(amd64_darwin_REDIR_FOR_strcpy)( char *s1, char *s2 ); +extern SizeT VG_(amd64_darwin_REDIR_FOR_strlcat)( char *s1, const char *s2, + SizeT size ); +extern UInt VG_(amd64_darwin_REDIR_FOR_arc4random)( void ); #endif #endif // __PUB_CORE_TRAMPOLINE_H diff --git a/coregrind/pub_core_translate.h b/coregrind/pub_core_translate.h index 8e0cea4..02113aa 100644 --- a/coregrind/pub_core_translate.h +++ b/coregrind/pub_core_translate.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_transtab.h b/coregrind/pub_core_transtab.h index 79005f2..d89cbed 100644 --- a/coregrind/pub_core_transtab.h +++ b/coregrind/pub_core_transtab.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_transtab_asm.h b/coregrind/pub_core_transtab_asm.h index 3c96867..d3292f1 100644 --- a/coregrind/pub_core_transtab_asm.h +++ b/coregrind/pub_core_transtab_asm.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -40,7 +40,10 @@ On ppc32/ppc64, the bottom two bits of instruction addresses are zero, which means that function causes only 1/4 of the entries to ever be used. So instead the function is '(address >>u - 2)[VG_TT_FAST_BITS-1 : 0]' on those targets. */ + 2)[VG_TT_FAST_BITS-1 : 0]' on those targets. + + On ARM we do like ppc32/ppc64, although that will have to be + revisited when we come to implement Thumb. */ #define VG_TT_FAST_BITS 15 #define VG_TT_FAST_SIZE (1 << VG_TT_FAST_BITS) @@ -50,7 +53,7 @@ like a good place to put it. */ #if defined(VGA_x86) || defined(VGA_amd64) # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) ) & VG_TT_FAST_MASK) -#elif defined(VGA_ppc32) || defined(VGA_ppc64) +#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm) # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK) #else # error "VG_TT_FAST_HASH: unknown platform" diff --git a/coregrind/pub_core_ume.h b/coregrind/pub_core_ume.h index 7a08963..5d89502 100644 --- a/coregrind/pub_core_ume.h +++ b/coregrind/pub_core_ume.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_vki.h b/coregrind/pub_core_vki.h index c5afeb0..63729a2 100644 --- a/coregrind/pub_core_vki.h +++ b/coregrind/pub_core_vki.h @@ -8,11 +8,11 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_vkiscnums.h b/coregrind/pub_core_vkiscnums.h index e54906f..a682946 100644 --- a/coregrind/pub_core_vkiscnums.h +++ b/coregrind/pub_core_vkiscnums.h @@ -7,11 +7,11 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_vkiscnums_asm.h b/coregrind/pub_core_vkiscnums_asm.h index 14cff8f..661213b 100644 --- a/coregrind/pub_core_vkiscnums_asm.h +++ b/coregrind/pub_core_vkiscnums_asm.h @@ -7,11 +7,11 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/pub_core_wordfm.h b/coregrind/pub_core_wordfm.h index 4365055..30bb9ad 100644 --- a/coregrind/pub_core_wordfm.h +++ b/coregrind/pub_core_wordfm.h @@ -9,13 +9,13 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2007-2009 Julian Seward + Copyright (C) 2007-2010 Julian Seward jseward@acm.org This code is based on previous work by Nicholas Nethercote (coregrind/m_oset.c) which is - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org which in turn was derived partially from: diff --git a/coregrind/pub_core_xarray.h b/coregrind/pub_core_xarray.h index 67231e9..c8e0456 100644 --- a/coregrind/pub_core_xarray.h +++ b/coregrind/pub_core_xarray.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2007-2009 OpenWorks LLP + Copyright (C) 2007-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/coregrind/vg_preloaded.c b/coregrind/vg_preloaded.c index e6c2fd1..4b58375 100644 --- a/coregrind/vg_preloaded.c +++ b/coregrind/vg_preloaded.c @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -47,13 +47,12 @@ #include "pub_core_debuginfo.h" // Needed for pub_core_redir.h #include "pub_core_redir.h" // For VG_NOTIFY_ON_LOAD -#if !defined(VGO_freebsd) +#if defined(VGO_linux) || defined(VGO_aix5) + /* --------------------------------------------------------------------- Hook for running __libc_freeres once the program exits. ------------------------------------------------------------------ */ -#if defined(VGO_linux) || defined(VGO_aix5) - void VG_NOTIFY_ON_LOAD(freeres)( void ); void VG_NOTIFY_ON_LOAD(freeres)( void ) { @@ -66,12 +65,39 @@ void VG_NOTIFY_ON_LOAD(freeres)( void ) VG_USERREQ__LIBC_FREERES_DONE, 0, 0, 0, 0, 0); /*NOTREACHED*/ - *(int *)0 = 'x'; + *(volatile int *)0 = 'x'; +} + +/* --------------------------------------------------------------------- + Wrapper for indirect functions which need to be redirected. + ------------------------------------------------------------------ */ + +void * VG_NOTIFY_ON_LOAD(ifunc_wrapper) (void); +void * VG_NOTIFY_ON_LOAD(ifunc_wrapper) (void) +{ + OrigFn fn; + Addr result = 0; + int res; + + /* Call the original indirect function and get it's result */ + VALGRIND_GET_ORIG_FN(fn); + CALL_FN_W_v(result, fn); + + /* Ask the valgrind core running on the real CPU (as opposed to this + code which runs on the emulated CPU) to update the redirection that + led to this function. This client request eventually gives control to + the function VG_(redir_add_ifunc_target) in m_redir.c */ + VALGRIND_DO_CLIENT_REQUEST(res, 0, + VG_USERREQ__ADD_IFUNC_TARGET, + fn.nraddr, result, 0, 0, 0); + return (void*)result; } #endif #elif defined(VGO_darwin) +#include "config.h" /* VERSION */ + /* --------------------------------------------------------------------- Darwin crash log hints ------------------------------------------------------------------ */ @@ -126,17 +152,18 @@ static void vg_cleanup_env(void) Darwin arc4random (rdar://6166275) ------------------------------------------------------------------ */ -#include +#include +#include int VG_REPLACE_FUNCTION_ZU(libSystemZdZaZddylib, arc4random)(void); int VG_REPLACE_FUNCTION_ZU(libSystemZdZaZddylib, arc4random)(void) { - static FILE *rnd = 0; + static int rnd = -1; int result; - if (!rnd) rnd = fopen("/dev/random", "r"); - - fread(&result, sizeof(result), 1, rnd); + if (rnd < 0) rnd = open("/dev/random", O_RDONLY); + + read(rnd, &result, sizeof(result)); return result; } diff --git a/darwin10-drd.supp b/darwin10-drd.supp new file mode 100644 index 0000000..385d6c9 --- /dev/null +++ b/darwin10-drd.supp @@ -0,0 +1,2 @@ + +# DRD suppressions for Darwin 10.x / Mac OS X 10.6 Snow Leopard diff --git a/darwin10.supp b/darwin10.supp new file mode 100644 index 0000000..55f39fe --- /dev/null +++ b/darwin10.supp @@ -0,0 +1,37 @@ + +# Suppressions for Darwin 10.x / Mac OS X 10.6 Snow Leopard + +##----------------------------------------------------------------------## +# Memcheck +##----------------------------------------------------------------------## + +# afaict this is legit. Might be caused by setenv("VAR=") +# where the value string is empty (not sure) +{ + macos-Cond-7 + Memcheck:Cond + fun:__setenv +} + +# From Jesse Ruderman. +{ + Mac OS X 10.6.4. rdar://8145289. "new[]" paired with "delete" in the DesktopServicesPriv framework. + Memcheck:Free + fun:_ZdlPv + fun:_ZN5TChar18RemovePtrReferenceEv + } + +# From Jesse Ruderman. +{ + Mac OS X 10.6.4. rdar://8145318. Uninitialized memory from HIMenuBarView::MeasureAppMenus is used in HIMenuBarView::SetAdjustTextTitleBoundsAtIndex. + Memcheck:Cond + fun:_ZN13HIMenuBarView31SetAdjustTextTitleBoundsAtIndexEih + fun:_ZN13HIMenuBarView15MeasureAppMenusEv +} + +{ + TFontFeatures::TFontFeatures(CGFont*) (in CoreText.framework) + Memcheck:Cond + fun:_ZN13TFontFeaturesC2EP6CGFont + fun:_ZNK9TBaseFont12CopyFeaturesEv +} diff --git a/darwin9-drd.supp b/darwin9-drd.supp index f9425e7..ea30143 100644 --- a/darwin9-drd.supp +++ b/darwin9-drd.supp @@ -1,3 +1,6 @@ + +# DRD suppressions for Darwin 9.x / Mac OS X 10.5 Leopard + # # Suppression patterns for dyld, the dynamic loader. # diff --git a/darwin9.supp b/darwin9.supp index a389426..f7769c7 100644 --- a/darwin9.supp +++ b/darwin9.supp @@ -103,7 +103,7 @@ macos-Cond-7 Memcheck:Cond fun:__setenv - fun:putenv + fun:putenv* } { @@ -180,6 +180,30 @@ fun:vsnprintf } +{ + macos-TFontFeatures::TFontFeatures(unsigned long)-uninitialised-stack-val + Memcheck:Cond + fun:_ZN13TFontFeaturesC2Em + fun:_ZNK9TBaseFont12CopyFeaturesEv +} + +# Conditional jump or move depends on uninitialised value(s) +# at 0x4E5CD59: _DPSNextEvent (in /System/Library/Frameworks +# /AppKit.framework/Versions/C/AppKit) +# by 0x4E5BF87: -[NSApplication nextEventMatchingMask:untilDate:inMode:dequeue:] +# (in /System/Library/Frameworks/AppKit.framework/Versions/C/AppKit) +# by 0x4E54F9E: -[NSApplication run] (in /System/Library/Frameworks +# /AppKit.framework/Versions/C/AppKit) +# Uninitialised value was created by a stack allocation +# at 0x4E5C450: _DPSNextEvent (in /System/Library/Frameworks +# /AppKit.framework/Versions/C/AppKit) +{ + macos-_DPSNextEvent-stack-allocated-uninit + Memcheck:Cond + fun:_DPSNextEvent +} + + ##----------------------------------------------------------------------## # Helgrind ##----------------------------------------------------------------------## diff --git a/docs/Makefile.am b/docs/Makefile.am index 9e9840c..62dd479 100644 --- a/docs/Makefile.am +++ b/docs/Makefile.am @@ -24,6 +24,7 @@ EXTRA_DIST = \ internals/3_2_BUGSTATUS.txt \ internals/3_3_BUGSTATUS.txt \ internals/3_4_BUGSTATUS.txt \ + internals/3_5_BUGSTATUS.txt \ internals/BIG_APP_NOTES.txt \ internals/Darwin-notes.txt \ internals/directory-structure.txt \ diff --git a/docs/internals/3_5_BUGSTATUS.txt b/docs/internals/3_5_BUGSTATUS.txt new file mode 100644 index 0000000..3276a08 --- /dev/null +++ b/docs/internals/3_5_BUGSTATUS.txt @@ -0,0 +1,15 @@ + +Bug status is now maintained in bugzilla (bugs.kde.org). This file is +merely to keep track of stuff that we currently can't/don't in +bugzilla. + +(post 3.5.0) + +Stuff to merge to 3.5 branch +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +r10878 Add support for the L2 cache on Intel T4200. +r10881 Ashley Mis-matched thread tags in helgrind xml +r10882 Ashley Remove & from exp-ptrcheck description +r10887 rmdir on ppc64-linux (#206903). + diff --git a/docs/internals/register-uses.txt b/docs/internals/register-uses.txt index c5835aa..d7a6ef1 100644 --- a/docs/internals/register-uses.txt +++ b/docs/internals/register-uses.txt @@ -95,6 +95,37 @@ ppc64-linux TBD +arm-linux +~~~~~~~~~ + +Reg Callee Arg +Name Saves? Reg? Comment Vex-uses? +-------------------------------------------------------------- +r0 int#1 int[31:0] retreg? avail +r1 int#2 int[63:32] retreg? avail +r2 int#3 avail +r3 int#4 avail +r4 y avail +r5 y avail +r6 y avail +r7 y avail +r8 y GSP +r9 y (but only on Linux; not in general) avail +r10 y avail +r11 y avail +r12 possibly used by linker? unavail +r13(sp) unavail +r14(lr) unavail +r15(pc) unavail + +VFP: d8-d15 are callee-saved +r12 (IP) is probably available for use as a caller-saved +register; but instead we use it as an intermediate for +holding the address for F32/F64 spills, since the VFP load/store +insns have reg+offset forms for offsets only up to 1020, which +often isn't enough. + + ppc32-aix5 ~~~~~~~~~~ diff --git a/docs/internals/release-HOWTO.txt b/docs/internals/release-HOWTO.txt index 54b98a0..df21522 100644 --- a/docs/internals/release-HOWTO.txt +++ b/docs/internals/release-HOWTO.txt @@ -21,6 +21,9 @@ First of all: release date probably won't be known yet, updating it is in the list below of tasks for the official release.) +- Make sure __VALGRIND_MAJOR__ and __VALGRIND_MINOR__ are correct + for the release. (include/valgrind.h) + - Write release notes, add to NEWS. Include a list of fixed bugs from Bugzilla. It's unclear how to do this consistently. The approach taken for 3.0.0 was to go to this page in KDE's bugzilla: diff --git a/docs/xml/FAQ.xml b/docs/xml/FAQ.xml index 9ee8ea3..983e02a 100644 --- a/docs/xml/FAQ.xml +++ b/docs/xml/FAQ.xml @@ -528,7 +528,10 @@ int main(void) "possibly lost" means your program is leaking - memory, unless you're doing funny things with pointers. + memory, unless you're doing funny things with pointers. + This is sometimes reasonable. Use + if you don't want to see + these reports. "still reachable" means your program is probably ok -- it diff --git a/docs/xml/manual-core-adv.xml b/docs/xml/manual-core-adv.xml index 03d86e1..9eea68c 100644 --- a/docs/xml/manual-core-adv.xml +++ b/docs/xml/manual-core-adv.xml @@ -55,10 +55,10 @@ use the macros in this file. Also, you are not required to link your program with any extra supporting libraries. The code added to your binary has negligible performance impact: -on x86, amd64, ppc32 and ppc64, the overhead is 6 simple integer instructions -and is probably undetectable except in tight loops. -However, if you really wish to compile out the client requests, you can -compile with (analogous to +on x86, amd64, ppc32, ppc64 and ARM, the overhead is 6 simple integer +instructions and is probably undetectable except in tight loops. +However, if you really wish to compile out the client requests, you +can compile with (analogous to 's effect on assert). @@ -106,7 +106,7 @@ tool-specific macros). Alternatively, for transparent self-modifying-code support, use, or run - on ppc32/Linux or ppc64/Linux. + on ppc32/Linux, ppc64/Linux or ARM/Linux. @@ -196,7 +196,7 @@ tool-specific macros). message is prefixed with the PID between a pair of ** markers. (Like all client requests, nothing is output if the client program is not running under Valgrind.) - Output is not produced until a newline is encountered, or subequent + Output is not produced until a newline is encountered, or subsequent Valgrind output is printed; this allows you to build up a single line of output over multiple calls. Returns the number of characters output, excluding the PID prefix. @@ -567,7 +567,7 @@ functions and merely replaced functions malloc etc safely from within wrappers. -The above comments are true for {x86,amd64,ppc32}-linux. On +The above comments are true for {x86,amd64,ppc32,arm}-linux. On ppc64-linux function wrapping is more fragile due to the (arguably poorly designed) ppc64-linux ABI. This mandates the use of a shadow stack which tracks entries/exits of both wrapper and replacement @@ -578,7 +578,7 @@ finite size, recursion between wrapper/replacement functions is only possible to a limited depth, beyond which Valgrind has to abort the run. This depth is currently 16 calls. -For all platforms ({x86,amd64,ppc32,ppc64}-linux) all the above +For all platforms ({x86,amd64,ppc32,ppc64,arm}-linux) all the above comments apply on a per-thread basis. In other words, wrapping is thread-safe: each thread must individually observe the above restrictions, but there is no need for any kind of inter-thread diff --git a/docs/xml/manual-core.xml b/docs/xml/manual-core.xml index 924c75e..59eb787 100644 --- a/docs/xml/manual-core.xml +++ b/docs/xml/manual-core.xml @@ -130,11 +130,11 @@ unaffected by optimisation level, and for profiling tools like Cachegrind it is better to compile your program at its normal optimisation level. Valgrind understands both the older "stabs" debugging format, used -by GCC versions prior to 3.1, and the newer DWARF2 and DWARF3 formats +by GCC versions prior to 3.1, and the newer DWARF2/3/4 formats used by GCC 3.1 and later. We continue to develop our debug-info readers, although the majority of effort will naturally enough go into the newer -DWARF2/3 reader. +DWARF readers. When you're ready to roll, run Valgrind as described above. Note that you should run the real @@ -596,7 +596,8 @@ in most cases. We group the available options by rough categories. Show help for all options, both for the core and for the - selected tool. + selected tool. If the option is repeated it is equivalent to giving + . @@ -660,6 +661,32 @@ in most cases. We group the available options by rough categories. + + + + + + This option only has an effect when + is specified. It allows + for some children to be skipped. The option takes a comma + separated list of patterns for the names of child executables + that Valgrind should not trace into. Patterns may include the + metacharacters ? + and *, which have the usual + meaning. + + This can be useful for pruning uninteresting branches from a + tree of processes being run on Valgrind. But you should be + careful when using it. When Valgrind skips tracing into an + executable, it doesn't just skip tracing that executable, it + also skips tracing any of that executable's child processes. + In other words, the flag doesn't merely cause tracing to stop + at the specified executables -- it skips tracing of entire + process subtrees rooted at any of the specified + executables. + + + @@ -970,6 +997,57 @@ that can report errors, e.g. Memcheck, but not Cachegrind. + + + + + + By default Valgrind only shows the filenames in stack + traces, but not full paths to source files. When using Valgrind + in large projects where the sources reside in multiple different + directories, this can be inconvenient. + provides a flexible solution + to this problem. When this option is present, the path to each + source file is shown, with the following all-important caveat: + if is found in the path, then the path + up to and including is omitted, else the + path is shown unmodified. Note that is + not required to be a prefix of the path. + + For example, consider a file named + /home/janedoe/blah/src/foo/bar/xyzzy.c. + Specifying + will cause Valgrind to show the name + as foo/bar/xyzzy.c. + + Because the string is not required to be a prefix, + will produce the same + output. This is useful when the path contains arbitrary + machine-generated characters. For example, the + path + /my/build/dir/C32A1B47/blah/src/foo/xyzzy + can be pruned to foo/xyzzy + using + . + + If you simply want to see the full path, just specify an + empty string: . This isn't a + special case, merely a logical consequence of the above rules. + + Finally, you can use + multiple times. Any appearance of it causes Valgrind to switch + to producing full paths and applying the above filtering rule. + Each produced path is compared against all + the -specified strings, in the + order specified. The first string to match causes the path to + be truncated as described above. If none match, the full path + is shown. This facilitates chopping off prefixes when the + sources are drawn from a number of unrelated directories. + + + + @@ -1157,7 +1235,7 @@ that can report errors, e.g. Memcheck, but not Cachegrind. Be careful when using , since it will cause pre-existing .dSYM - directories to be silently deleted and re-created. Also note the + directories to be silently deleted and re-created. Also note that dsymutil is quite slow, sometimes excessively so. @@ -1260,7 +1338,7 @@ that can report errors, e.g. Memcheck, but not Cachegrind. -<computeroutput>malloc</computeroutput>-related Options +malloc-related Options For tools that use their own version of @@ -1312,13 +1390,13 @@ need to use these. will likely lead to incorrect behaviour and/or crashes. Valgrind has three levels of self-modifying code detection: - no detection, detect self-modifying code on the stack (which used by + no detection, detect self-modifying code on the stack (which is used by GCC to implement nested functions), or detect self-modifying code everywhere. Note that the default option will catch the vast majority of cases. The main case it will not catch is programs such as JIT compilers that dynamically generate code and subsequently overwrite part or all of it. Running with - all will slow Valgrind down greatly. Running with + all will slow Valgrind down noticeably. Running with none will rarely speed things up, since very little code gets put on the stack for most programs. The VALGRIND_DISCARD_TRANSLATIONS client request is @@ -1330,11 +1408,11 @@ need to use these. --> - Some architectures (including ppc32 and ppc64) require + Some architectures (including ppc32, ppc64 and ARM) require programs which create code at runtime to flush the instruction cache in between code generation and first use. Valgrind - observes and honours such instructions. Hence, on ppc32/Linux - and ppc64/Linux, Valgrind always provides complete, transparent + observes and honours such instructions. Hence, on ppc32/Linux, + ppc64/Linux and ARM/Linux, Valgrind always provides complete, transparent support for self-modifying code. It is only on platforms such as x86/Linux, AMD64/Linux and x86/Darwin that you need to use this option. @@ -1475,6 +1553,55 @@ need to use these. + + + + + + When a shared object whose soname + matches sonamepatt is loaded into the + process, examine all the text symbols it exports. If none of + those match fnnamepatt, print an error + message and abandon the run. This makes it possible to ensure + that the run does not continue unless a given shared object + contains a particular function name. + + + Both sonamepatt and + fnnamepatt can be written using the usual + ? and * wildcards. For + example: ":*libc.so*:foo?bar". You may use + characters other than a colon to separate the two patterns. It + is only important that the first character and the separator + character are the same. For example, the above example could + also be written "Q*libc.so*Qfoo?bar". + Multiple --require-text-symbol flags are + allowed, in which case shared objects that are loaded into + the process will be checked against all of them. + + + The purpose of this is to support reliable usage of marked-up + libraries. For example, suppose we have a version of GCC's + libgomp.so which has been marked up with + annotations to support Helgrind. It is only too easy and + confusing to load the wrong, un-annotated + libgomp.so into the application. So the idea + is: add a text symbol in the marked-up library, for + example annotated_for_helgrind_3_6, and then + give the flag + --require-text-symbol=:*libgomp*so*:annotated_for_helgrind_3_6 + so that when libgomp.so is loaded, Valgrind + scans its symbol table, and if the symbol isn't present the run + is aborted, rather than continuing silently with the + un-marked-up library. Note that you should put the entire flag + in quotes to stop shells expanding up the * + and ? wildcards. + + + + + @@ -1584,8 +1711,7 @@ tools Helgrind and/or DRD to track them down. futex and so on. clone is supported where either everything is shared (a thread) or nothing is shared (fork-like); partial -sharing will fail. Again, any use of atomic instruction sequences in shared -memory between processes will not work reliably. +sharing will fail. @@ -1629,16 +1755,15 @@ will create a core dump in the usual way. We use the standard Unix ./configure, make, make -install mechanism, and we have attempted to -ensure that it works on machines with kernel 2.4 or 2.6 and glibc -2.2.X to 2.10.X. Once you have completed +install mechanism. Once you have completed make install you may then want to run the regression tests with make regtest. -There are five options (in addition to the usual - which affect how Valgrind is built: +In addition to the usual +, there are three + options which affect how Valgrind is built: @@ -1650,25 +1775,17 @@ with make regtest. - - - TLS (Thread Local Storage) is a relatively new mechanism which - requires compiler, linker and kernel support. Valgrind tries to - automatically test if TLS is supported and if so enables this option. - Sometimes it cannot test for TLS, so this option allows you to - override the automatic test. - - - On 64-bit - platforms (amd64-linux, ppc64-linux), Valgrind is by default built - in such a way that both 32-bit and 64-bit executables can be run. - Sometimes this cleverness is a problem for a variety of reasons. - These two options allow for single-target builds in this situation. - If you issue both, the configure script will complain. Note they - are ignored on 32-bit-only platforms (x86-linux, ppc32-linux). + On 64-bit platforms (amd64-linux, ppc64-linux, + amd64-darwin), Valgrind is by default built in such a way that + both 32-bit and 64-bit executables can be run. Sometimes this + cleverness is a problem for a variety of reasons. These two + options allow for single-target builds in this situation. If you + issue both, the configure script will complain. Note they are + ignored on 32-bit-only platforms (x86-linux, ppc32-linux, + arm-linux, x86-darwin). @@ -1732,29 +1849,45 @@ subject to the following constraints: - On x86 and amd64, there is no support for 3DNow! instructions. - If the translator encounters these, Valgrind will generate a SIGILL - when the instruction is executed. Apart from that, on x86 and amd64, - essentially all instructions are supported, up to and including SSSE3. + On x86 and amd64, there is no support for 3DNow! + instructions. If the translator encounters these, Valgrind will + generate a SIGILL when the instruction is executed. Apart from + that, on x86 and amd64, essentially all instructions are supported, + up to and including SSE4.2 in 64-bit mode and SSSE3 in 32-bit mode. + Some exceptions: SSE4.2 AES instructions are not supported in + 64-bit mode, and 32-bit mode does in fact support the bare minimum + SSE4 instructions to needed to run programs on MacOSX 10.6 on + 32-bit targets. - On ppc32 and ppc64, almost all integer, floating point and Altivec - instructions are supported. Specifically: integer and FP insns that are - mandatory for PowerPC, the "General-purpose optional" group (fsqrt, fsqrts, - stfiwx), the "Graphics optional" group (fre, fres, frsqrte, frsqrtes), and - the Altivec (also known as VMX) SIMD instruction set, are supported. + On ppc32 and ppc64, almost all integer, floating point and + Altivec instructions are supported. Specifically: integer and FP + insns that are mandatory for PowerPC, the "General-purpose + optional" group (fsqrt, fsqrts, stfiwx), the "Graphics optional" + group (fre, fres, frsqrte, frsqrtes), and the Altivec (also known + as VMX) SIMD instruction set, are supported. Also, instructions + from the Power ISA 2.05 specification, as present in POWER6 CPUs, + are supported. + + + + On ARM, essentially the entire ARMv7-A instruction set + is supported, in both ARM and Thumb mode. ThumbEE and Jazelle are + not supported. NEON and VFPv3 support is fairly complete. ARMv6 + media instruction support is mostly done but not yet complete. + If your program does its own memory management, rather than using malloc/new/free/delete, it should still work, but Memcheck's - error checking won't be so effective. If you describe your program's - memory management scheme using "client requests" - (see ), Memcheck can do - better. Nevertheless, using malloc/new and free/delete is still the - best approach. + error checking won't be so effective. If you describe your + program's memory management scheme using "client requests" (see + ), Memcheck can do + better. Nevertheless, using malloc/new and free/delete is still + the best approach. @@ -1775,25 +1908,32 @@ subject to the following constraints: - Memory consumption of your program is majorly increased whilst - running under Valgrind. This is due to the large amount of - administrative information maintained behind the scenes. Another - cause is that Valgrind dynamically translates the original - executable. Translated, instrumented code is 12-18 times larger than - the original so you can easily end up with 50+ MB of translations - when running (eg) a web browser. + Memory consumption of your program is majorly increased + whilst running under Valgrind's Memcheck tool. This is due to the + large amount of administrative information maintained behind the + scenes. Another cause is that Valgrind dynamically translates the + original executable. Translated, instrumented code is 12-18 times + larger than the original so you can easily end up with 100+ MB of + translations when running (eg) a web browser. Valgrind can handle dynamically-generated code just fine. If - you regenerate code over the top of old code (ie. at the same memory - addresses), if the code is on the stack Valgrind will realise the - code has changed, and work correctly. This is necessary to handle - the trampolines GCC uses to implemented nested functions. If you - regenerate code somewhere other than the stack, you will need to use - the option, and Valgrind will run more - slowly than normal. Or you can add client requests that tell Valgrind - when your program has overwritten code. + you regenerate code over the top of old code (ie. at the same + memory addresses), if the code is on the stack Valgrind will + realise the code has changed, and work correctly. This is + necessary to handle the trampolines GCC uses to implemented nested + functions. If you regenerate code somewhere other than the stack, + and you are running on an 32- or 64-bit x86 CPU, you will need to + use the option, and Valgrind will + run more slowly than normal. Or you can add client requests that + tell Valgrind when your program has overwritten code. + + On other platforms (ARM, PowerPC) Valgrind observes and + honours the cache invalidation hints that programs are obliged to + emit to notify new code, and so self-modifying-code support should + work automatically, without the need + for . @@ -1869,6 +2009,19 @@ subject to the following constraints: warn about, attempts to enable either mode. + + Valgrind has the following limitations in + its implementation of ARM VFPv3 arithmetic, relative to + IEEE754. + + Essentially the same: no exceptions, and limited observance + of rounding mode. Also, switching the VFP unit into vector mode + will cause Valgrind to abort the program -- it has no way to + emulate vector uses of VFP at a reasonable performance level. This + is no big deal given that non-scalar uses of VFP instructions are + in any case deprecated. + + Valgrind has the following limitations in its implementation of PPC32 and PPC64 floating point diff --git a/docs/xml/manual-intro.xml b/docs/xml/manual-intro.xml index 452effd..3efbdee 100644 --- a/docs/xml/manual-intro.xml +++ b/docs/xml/manual-intro.xml @@ -53,6 +53,12 @@ and without disturbing the existing structure. make your programs use less memory. + + DHAT is a different kind of heap + profiler. It helps you understand issues of block lifetimes, + block utilisation, and layout inefficiencies. + + Ptrcheck is an experimental heap, stack and global array overrun detector. Its functionality overlaps somewhat diff --git a/docs/xml/manual.xml b/docs/xml/manual.xml index 5a01af2..b1ec6d5 100644 --- a/docs/xml/manual.xml +++ b/docs/xml/manual.xml @@ -36,6 +36,8 @@ xmlns:xi="http://www.w3.org/2001/XInclude" /> + -O0 is also a good idea, if you can tolerate the slowdown. With line numbers in error messages can be inaccurate, although generally speaking running Memcheck on code compiled -at works fairly well. +at works fairly well, and the speed improvement +compared to running is quite significant. Use of and above is not recommended as Memcheck occasionally reports uninitialised-value errors which don't diff --git a/docs/xml/vg-entities.xml b/docs/xml/vg-entities.xml index bc6ea16..52c1d0e 100644 --- a/docs/xml/vg-entities.xml +++ b/docs/xml/vg-entities.xml @@ -2,12 +2,12 @@ - + - - + + diff --git a/drd/Makefile.am b/drd/Makefile.am index 60c5ce4..edfd7de 100644 --- a/drd/Makefile.am +++ b/drd/Makefile.am @@ -17,6 +17,7 @@ noinst_HEADERS = \ drd_clientreq.h \ drd_cond.h \ drd_error.h \ + drd_hb.h \ drd_load_store.h \ drd_malloc_wrappers.h \ drd_mutex.h \ @@ -40,6 +41,8 @@ DRD_CFLAGS = \ -Wno-inline \ -Wno-unused-parameter +#DRD_CFLAGS += -DENABLE_DRD_CONSISTENCY_CHECKS + #---------------------------------------------------------------------------- # drd- #---------------------------------------------------------------------------- @@ -55,7 +58,9 @@ DRD_SOURCES_COMMON = \ drd_clientobj.c \ drd_clientreq.c \ drd_cond.c \ + drd_cond_initializer.c \ drd_error.c \ + drd_hb.c \ drd_load_store.c \ drd_main.c \ drd_malloc_wrappers.c \ @@ -64,7 +69,8 @@ DRD_SOURCES_COMMON = \ drd_semaphore.c \ drd_suppression.c -drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(DRD_SOURCES_COMMON) +drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ + $(DRD_SOURCES_COMMON) drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \ @@ -75,8 +81,16 @@ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC -drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(DRD_SOURCES_COMMON) +drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ + $(DRD_SOURCES_COMMON) drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \ @@ -87,6 +101,12 @@ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif #---------------------------------------------------------------------------- @@ -118,6 +138,7 @@ vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \ vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) + if VGCONF_HAVE_PLATFORM_SEC vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = \ $(VGPRELOAD_DRD_SOURCES_COMMON) diff --git a/drd/TODO.txt b/drd/TODO.txt deleted file mode 100644 index da03687..0000000 --- a/drd/TODO.txt +++ /dev/null @@ -1,36 +0,0 @@ -Last updated August 7, 2009. -~~~~~~~~~~~~~~~~~~~~~~~~~~ - - -The DRD tool -~~~~~~~~~~~~ -- Improve the code for suppressing races reported on glibc FILE objects, e.g. by - intercepting all operations on FILE objects and by associating mutex semantics - with FILE objects. Verify that races on unsynchronized *_unlocked() operations - are reported. Remove FILE-I/O suppression patterns from glibc-2.X-drd.supp. - See also http://www.unix.org/whitepapers/reentrant.html. -- Add locking order checking. Start from the following information: - * http://sourceforge.net/mailarchive/message.php?msg_id=alpine.LNX.1.10.0803270822080.17890%40mudge.stoecker.eu - * http://lwn.net/Articles/185605/ - * http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=Documentation/lockdep-design.txt;h=488773018152056ea159685e732e42452a7ae142;hb=HEAD -- Make sure tc14_laog_dinphils is run during drd regression tests - (only possible after locking order checking is implemented). -- Evaluate whether integration of drd with one of the available Valgrind GUI's - makes sense (http://valgrind.org/downloads/guis.html). - - -Testing -~~~~~~~ -- Measure the performance and the memory overhead of drd on the PARSEC - benchmark (http://parsec.cs.princeton.edu/license.htm). -- Test with Synfig Studio (see also http://bugs.kde.org/show_bug.cgi?id=158555) -- Test with a multithreaded Python application. - - -Documentation -~~~~~~~~~~~~~ -- Document the algorithms used in drd. -- Add comment on double checked locking. -- Add comment on lockless algorithms in general and circular buffers in - particular. -- Explain how to handle transactions (with regard to locking order). diff --git a/drd/Testing.txt b/drd/Testing.txt index ed88222..d2428e9 100644 --- a/drd/Testing.txt +++ b/drd/Testing.txt @@ -23,7 +23,10 @@ How to test DRD exist: ( cd drd/tests; - for e in $(awk '/\\$/{n=$0; sub("\\\\$", "", n); if (line != "") { line = line " " n } else { line=n }} /[^\\]$/{if (line != ""){print line;line=""};print}' < Makefile.am | sed -n 's/^EXTRA_DIST *=//p' | sed 's/..noinst_SCRIPTS.//') + for e in $(awk '/\\$/{n=$0; sub("\\\\$", "", n); if (line != "")\ + { line = line " " n } else { line=n }} \ + /[^\\]$/{if (line != ""){print line;line=""};print}' < Makefile.am \ + | sed -n 's/^EXTRA_DIST *=//p' | sed 's/..noinst_SCRIPTS.//') do [ -e "$e" ] || echo "$e" done diff --git a/drd/docs/drd-manual.xml b/drd/docs/drd-manual.xml index 318a750..b1e77ca 100644 --- a/drd/docs/drd-manual.xml +++ b/drd/docs/drd-manual.xml @@ -361,6 +361,20 @@ behavior of the DRD tool itself: + + + + + + + Whether to report accessing freed memory as a race. Helps to detect + memory accesses that occur after memory has been freed but might cause + DRD to run slightly slower. + + + + + + + + + + Trace all memory allocations and deallocations. May produce a huge + amount of output. + + + @@ -923,14 +948,26 @@ available macros and client requests are: - The macros DRD_TRACE_VAR(x), - ANNOTATE_TRACE_MEMORY(&x) - and the corresponding client request - VG_USERREQ__DRD_START_TRACE_ADDR. Trace all - load and store activity on the specified address range. When DRD reports - a data race on a specified variable, and it's not immediately clear - which source code statements triggered the conflicting accesses, it can - be very helpful to trace all activity on the offending memory location. + The macro DRD_TRACE_VAR(x). Trace all load and store + activity for the address range starting at &x and + occupying sizeof(x) bytes. When DRD reports a data + race on a specified variable, and it's not immediately clear which + source code statements triggered the conflicting accesses, it can be + very helpful to trace all activity on the offending memory location. + + + + + The macro ANNOTATE_TRACE_MEMORY(&x). Trace all + load and store activity that touches at least the single byte at the + address &x. + + + + + The client request VG_USERREQ__DRD_START_TRACE_ADDR, + which allows to trace all load and store activity for the specified + address range. @@ -953,9 +990,11 @@ available macros and client requests are: the next access to the variable at the specified address should be considered to have happened after the access just before the latest ANNOTATE_HAPPENS_BEFORE(addr) annotation that - references the same variable. The purpose of these two macros is to - tell DRD about the order of inter-thread memory accesses implemented via - atomic memory operations. + references the same variable. The purpose of these two macros is to tell + DRD about the order of inter-thread memory accesses implemented via + atomic memory operations. See + also drd/tests/annotate_smart_pointer.cpp for an + example. @@ -963,7 +1002,8 @@ available macros and client requests are: The macro ANNOTATE_RWLOCK_CREATE(rwlock) tells DRD that the object at address rwlock is a reader-writer synchronization object that is not a - pthread_rwlock_t synchronization object. + pthread_rwlock_t synchronization object. See + also drd/tests/annotate_rwlock.c for an example. @@ -1021,11 +1061,50 @@ available macros and client requests are: - The macro ANNOTATE_BENIGN_RACE(addr, descr) tells - DRD that any races detected on the specified address are benign and - hence should not be reported. The descr argument is - ignored but can be used to document why data races - on addr are benign. + The macro ANNOTATE_BARRIER_INIT(barrier, count, + reinitialization_allowed) tells DRD that a new barrier object + at the address barrier has been initialized, + that count threads participate in each barrier and + also whether or not barrier reinitialization without intervening + destruction should be reported as an error. See + also drd/tests/annotate_barrier.c for an example. + + + + + The macro ANNOTATE_BARRIER_DESTROY(barrier) + tells DRD that a barrier object is about to be destroyed. + + + + + The macro ANNOTATE_BARRIER_WAIT_BEFORE(barrier) + tells DRD that waiting for a barrier will start. + + + + + The macro ANNOTATE_BARRIER_WAIT_AFTER(barrier) + tells DRD that waiting for a barrier has finished. + + + + + The macro ANNOTATE_BENIGN_RACE_SIZED(addr, size, + descr) tells DRD that any races detected on the specified + address are benign and hence should not be + reported. The descr argument is ignored but can be + used to document why data races on addr are benign. + + + + + The macro ANNOTATE_BENIGN_RACE_STATIC(var, descr) + tells DRD that any races detected on the specified static variable are + benign and hence should not be reported. The descr + argument is ignored but can be used to document why data races + on var are benign. Note: this macro can only be + used in C++ programs and not in C programs. @@ -1090,17 +1169,6 @@ available macros and client requests are: - -For an example of how to use the annotations for user-defined reader-writer -synchronization objects, see -also the source file drd/tests/annotate_rwlock.c in the -Valgrind source archive. And an example of how to -use the ANNOTATE_HAPPENS_BEFORE and -the ANNOTATE_HAPPENS_AFTER annotations can be found -in the source code of the Chromium -web browser. - - Note: if you compiled Valgrind yourself, the header file <valgrind/drd.h> will have been installed in @@ -1566,7 +1634,7 @@ concept. -<function>pthread_cond_timedwait</function> and timeouts +pthread_cond_timedwait and timeouts Historically the function @@ -1607,46 +1675,6 @@ example. - -Assigning names to threads - - -Many applications log information about changes in internal or -external state to a file. When analyzing log files of a multithreaded -application it can be very convenient to know which thread logged -which information. One possible approach is to identify threads in -logging output by including the result of -pthread_self in every log line. However, this approach -has two disadvantages: there is no direct relationship between these -values and the source code and these values can be different in each -run. A better approach is to assign a brief name to each thread and to -include the assigned thread name in each log line. One possible -approach for managing thread names is as follows: - - - - Allocate a key for the pointer to the thread name through - pthread_key_create. - - - - - Just after thread creation, set the thread name through - pthread_setspecific. - - - - - In the code that generates the logging information, query the thread - name by calling pthread_getspecific. - - - - - - - - @@ -1656,18 +1684,6 @@ approach for managing thread names is as follows: DRD currently has the following limitations: - - - DRD has only been tested on Linux and Mac OS X. - - - - - Of the two POSIX threads implementations for Linux, only the - NPTL (Native POSIX Thread Library) is supported. The older - LinuxThreads library is not supported. - - DRD, just like Memcheck, will refuse to start on Linux @@ -1680,12 +1696,19 @@ approach for managing thread names is as follows: url="http://bugs.gentoo.org/214065">214065. + + + With gcc 4.4.3 and before, DRD may report data races on the C++ + class std::string in a multithreaded program. This is + a know libstdc++ issue -- see also GCC bug + 40518 + for more information. + + When address tracing is enabled, no information on atomic stores - will be displayed. This functionality is easy to add - however. Please contact the Valgrind authors if you would like - to see this functionality enabled. + will be displayed. @@ -1694,6 +1717,13 @@ approach for managing thread names is as follows: later. GCC 2.95 is not supported. + + + Of the two POSIX threads implementations for Linux, only the + NPTL (Native POSIX Thread Library) is supported. The older + LinuxThreads library is not supported. + + diff --git a/drd/drd.h b/drd/drd.h index 83720e6..370ef92 100644 --- a/drd/drd.h +++ b/drd/drd.h @@ -14,7 +14,7 @@ This file is part of DRD, a Valgrind tool for verification of multithreaded programs. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . All rights reserved. Redistribution and use in source and binary forms, with or without @@ -65,52 +65,63 @@ #include "valgrind.h" -/** Prefix for the (inline) functions defined in this header file. */ -#define DRDCL_(str) vgDrdCl_##str - - /** Obtain the thread ID assigned by Valgrind's core. */ -#define DRD_GET_VALGRIND_THREADID (DRDCL_(get_valgrind_threadid)()) +#define DRD_GET_VALGRIND_THREADID \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_GET_VALGRIND_THREAD_ID, \ + 0, 0, 0, 0, 0) /** Obtain the thread ID assigned by DRD. */ -#define DRD_GET_DRD_THREADID (DRDCL_(get_drd_threadid)()) +#define DRD_GET_DRD_THREADID \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_GET_DRD_THREAD_ID, \ + 0, 0, 0, 0, 0) + /** Tell DRD not to complain about data races for the specified variable. */ -#define DRD_IGNORE_VAR(x) DRDCL_(ignore_range)(&(x), sizeof(x)) +#define DRD_IGNORE_VAR(x) ANNOTATE_BENIGN_RACE_SIZED(&(x), sizeof(x), "") /** Tell DRD to no longer ignore data races for the specified variable. */ -#define DRD_STOP_IGNORING_VAR(x) DRDCL_(ignore_range)(&(x), sizeof(x)) +#define DRD_STOP_IGNORING_VAR(x) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_FINISH_SUPPRESSION, \ + &(x), sizeof(x), 0, 0, 0) /** - * Tell DRD to trace all memory accesses on the specified variable. + * Tell DRD to trace all memory accesses on the specified variable. * until the memory that was allocated for the variable is freed. */ -#define DRD_TRACE_VAR(x) DRDCL_(trace_range)(&(x), sizeof(x)) +#define DRD_TRACE_VAR(x) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_START_TRACE_ADDR, \ + &(x), sizeof(x), 0, 0, 0) /** * @defgroup RaceDetectionAnnotations Data race detection annotations. * - * @see See also the source file dynamic_annotations.h + * @see See also the source file producer-consumer. @@ -228,48 +285,68 @@ #define ANNOTATE_PCQ_GET(pcq) do { } while(0) /** - * Tell DRD that data races in the specified address range are expected and - * must not be reported. + * Tell DRD that data races at the specified address are expected and must not + * be reported. */ -#define ANNOTATE_BENIGN_RACE(addr, descr) DRDCL_(ignore_range)(addr, 4) +#define ANNOTATE_BENIGN_RACE(addr, descr) \ + ANNOTATE_BENIGN_RACE_SIZED(addr, sizeof(*addr), descr) + +/* Same as ANNOTATE_BENIGN_RACE(addr, descr), but applies to + the memory range [addr, addr + size). */ +#define ANNOTATE_BENIGN_RACE_SIZED(addr, size, descr) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_START_SUPPRESSION, \ + addr, size, 0, 0, 0) /** Tell DRD to ignore all reads performed by the current thread. */ -#define ANNOTATE_IGNORE_READS_BEGIN() DRDCL_(set_record_loads)(0) +#define ANNOTATE_IGNORE_READS_BEGIN() \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_RECORD_LOADS, \ + 0, 0, 0, 0, 0); + /** Tell DRD to no longer ignore the reads performed by the current thread. */ -#define ANNOTATE_IGNORE_READS_END() DRDCL_(set_record_loads)(1) +#define ANNOTATE_IGNORE_READS_END() \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_RECORD_LOADS, \ + 1, 0, 0, 0, 0); /** Tell DRD to ignore all writes performed by the current thread. */ -#define ANNOTATE_IGNORE_WRITES_BEGIN() DRDCL_(set_record_stores)(0) +#define ANNOTATE_IGNORE_WRITES_BEGIN() \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_RECORD_STORES, \ + 0, 0, 0, 0, 0) /** Tell DRD to no longer ignore the writes performed by the current thread. */ -#define ANNOTATE_IGNORE_WRITES_END() DRDCL_(set_record_stores)(1) +#define ANNOTATE_IGNORE_WRITES_END() \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_RECORD_STORES, \ + 1, 0, 0, 0, 0) /** Tell DRD to ignore all memory accesses performed by the current thread. */ #define ANNOTATE_IGNORE_READS_AND_WRITES_BEGIN() \ - do { DRDCL_(set_record_loads)(0); DRDCL_(set_record_stores)(0); } while(0) + do { ANNOTATE_IGNORE_READS_BEGIN(); ANNOTATE_IGNORE_WRITES_BEGIN(); } while(0) /** * Tell DRD to no longer ignore the memory accesses performed by the current * thread. */ #define ANNOTATE_IGNORE_READS_AND_WRITES_END() \ - do { DRDCL_(set_record_loads)(1); DRDCL_(set_record_stores)(1); } while(0) + do { ANNOTATE_IGNORE_READS_END(); ANNOTATE_IGNORE_WRITES_END(); } while(0) /** * Tell DRD that size bytes starting at addr has been allocated by a custom * memory allocator. */ -#define ANNOTATE_NEW_MEMORY(addr, size) DRDCL_(clean_memory)(addr, size) +#define ANNOTATE_NEW_MEMORY(addr, size) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_CLEAN_MEMORY, \ + addr, size, 0, 0, 0) -/** Ask DRD to report every access to the specified address range. */ -#define ANNOTATE_TRACE_MEMORY(addr) DRDCL_(trace_range)(addr, 1) +/** Ask DRD to report every access to the specified address. */ +#define ANNOTATE_TRACE_MEMORY(addr) DRD_TRACE_VAR(*(char*)(addr)) /** * Tell DRD to assign the specified name to the current thread. This name will * be used in error messages printed by DRD. */ -#define ANNOTATE_THREAD_NAME(name) DRDCL_(set_thread_name)(name) +#define ANNOTATE_THREAD_NAME(name) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, VG_USERREQ__DRD_SET_THREAD_NAME, \ + name, 0, 0, 0, 0) /*@}*/ @@ -320,6 +397,10 @@ enum { VG_USERREQ__DRD_SET_THREAD_NAME, /* args: null-terminated character string. */ + /* Tell DRD that a DRD annotation has not yet been implemented. */ + VG_USERREQ__DRD_ANNOTATION_UNIMP, + /* args: Char*. */ + /* Tell DRD that a user-defined reader-writer synchronization object * has been created. */ VG_USERREQ__DRD_ANNOTATE_RWLOCK_CREATE @@ -341,16 +422,16 @@ enum { = VG_USERREQ_TOOL_BASE('H','G') + 256 + 18, /* args: Addr, Int is_rw. */ - /* Tell DRD that an annotation has not yet been implemented. */ - VG_USERREQ__DRD_ANNOTATION_UNIMP + /* Tell DRD that a Helgrind annotation has not yet been implemented. */ + VG_USERREQ__HELGRIND_ANNOTATION_UNIMP = VG_USERREQ_TOOL_BASE('H','G') + 256 + 32, /* args: Char*. */ - /* Tell DRD to insert a happens before annotation. */ + /* Tell DRD to insert a happens-before annotation. */ VG_USERREQ__DRD_ANNOTATE_HAPPENS_BEFORE = VG_USERREQ_TOOL_BASE('H','G') + 256 + 33, /* args: Addr. */ - /* Tell DRD to insert a happens after annotation. */ + /* Tell DRD to insert a happens-after annotation. */ VG_USERREQ__DRD_ANNOTATE_HAPPENS_AFTER = VG_USERREQ_TOOL_BASE('H','G') + 256 + 34, /* args: Addr. */ @@ -358,136 +439,42 @@ enum { }; -/* - * Do not call the inline functions below directly but use the macro's defined - * above. The names of these inline functions may change from one release to - * another. +/** + * @addtogroup RaceDetectionAnnotations */ +/*@{*/ -static __inline__ -void DRDCL_(clean_memory)(const void* const addr, const int size) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_CLEAN_MEMORY, - addr, size, 0, 0, 0); -} - -static __inline__ -int DRDCL_(get_valgrind_threadid)(void) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_GET_VALGRIND_THREAD_ID, - 0, 0, 0, 0, 0); - return res; -} - -static __inline__ -int DRDCL_(get_drd_threadid)(void) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_GET_DRD_THREAD_ID, - 0, 0, 0, 0, 0); - return res; -} - -static __inline__ -void DRDCL_(ignore_range)(const void* const addr, const int size) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_START_SUPPRESSION, - addr, size, 0, 0, 0); -} - -static __inline__ -void DRDCL_(stop_ignoring_range)(const void* const addr, const int size) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_FINISH_SUPPRESSION, - addr, size, 0, 0, 0); -} - -static __inline__ -void DRDCL_(trace_range)(const void* const addr, const int size) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_START_TRACE_ADDR, - addr, size, 0, 0, 0); -} - -static __inline__ -void DRDCL_(set_record_loads)(const int enabled) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_RECORD_LOADS, - enabled, 0, 0, 0, 0); -} - -static __inline__ -void DRDCL_(set_record_stores)(const int enabled) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_RECORD_STORES, - enabled, 0, 0, 0, 0); -} - -static __inline__ -void DRDCL_(set_thread_name)(const char* const name) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_SET_THREAD_NAME, - name, 0, 0, 0, 0); -} - -static __inline__ -void DRDCL_(annotate_happens_before)(const void* const addr) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_ANNOTATE_HAPPENS_BEFORE, - addr, 0, 0, 0, 0); -} - -static __inline__ -void DRDCL_(annotate_happens_after)(const void* const addr) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__DRD_ANNOTATE_HAPPENS_AFTER, - addr, 0, 0, 0, 0); -} - -static __inline__ -void DRDCL_(annotate_rwlock_create)(const void* const rwlock) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, - VG_USERREQ__DRD_ANNOTATE_RWLOCK_CREATE, - rwlock, 0, 0, 0, 0); -} - -static __inline__ -void DRDCL_(annotate_rwlock_destroy)(const void* const rwlock) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, - VG_USERREQ__DRD_ANNOTATE_RWLOCK_DESTROY, - rwlock, 0, 0, 0, 0); -} - -static __inline__ -void DRDCL_(annotate_rwlock_acquired)(const void* const rwlock, const int is_w) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, - VG_USERREQ__DRD_ANNOTATE_RWLOCK_ACQUIRED, - rwlock, is_w, 0, 0, 0); +#ifdef __cplusplus +/* ANNOTATE_UNPROTECTED_READ is the preferred way to annotate racy reads. + + Instead of doing + ANNOTATE_IGNORE_READS_BEGIN(); + ... = x; + ANNOTATE_IGNORE_READS_END(); + one can use + ... = ANNOTATE_UNPROTECTED_READ(x); */ +template +inline T ANNOTATE_UNPROTECTED_READ(const volatile T& x) { + ANNOTATE_IGNORE_READS_BEGIN(); + const T result = x; + ANNOTATE_IGNORE_READS_END(); + return result; } +/* Apply ANNOTATE_BENIGN_RACE_SIZED to a static variable. */ +#define ANNOTATE_BENIGN_RACE_STATIC(static_var, description) \ + namespace { \ + static class static_var##_annotator \ + { \ + public: \ + static_var##_annotator() \ + { \ + ANNOTATE_BENIGN_RACE_SIZED(&static_var, sizeof(static_var), \ + #static_var ": " description); \ + } \ + } the_##static_var##_annotator; \ + } +#endif -static __inline__ -void DRDCL_(annotate_rwlock_released)(const void* const rwlock, const int is_w) -{ - int res; - VALGRIND_DO_CLIENT_REQUEST(res, 0, - VG_USERREQ__DRD_ANNOTATE_RWLOCK_RELEASED, - rwlock, is_w, 0, 0, 0); -} +/*@}*/ #endif /* __VALGRIND_DRD_H */ diff --git a/drd/drd_barrier.c b/drd/drd_barrier.c index 90fa330..a565511 100644 --- a/drd/drd_barrier.c +++ b/drd/drd_barrier.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -42,11 +42,11 @@ struct barrier_thread_info { UWord tid; // A DrdThreadId declared as UWord because - // this member variable is the key of an OSet. + // this member variable is the key of an OSet. Word iteration; // iteration of last pthread_barrier_wait() - // call thread tid participated in. + // call thread tid participated in. Segment* sg[2]; // Segments of the last two - // pthread_barrier() calls by thread tid. + // pthread_barrier() calls by thread tid. ExeContext* wait_call_ctxt;// call stack for *_barrier_wait() call. Segment* post_wait_sg; // Segment created after *_barrier_wait() finished }; @@ -308,7 +308,10 @@ void DRD_(barrier_destroy)(const Addr barrier, const BarrierT barrier_type) if (p == 0) { - GenericErrInfo GEI = { DRD_(thread_get_running_tid)() }; + GenericErrInfo GEI = { + .tid = DRD_(thread_get_running_tid)(), + .addr = barrier, + }; VG_(maybe_record_error)(VG_(get_running_tid)(), GenericErr, VG_(get_IP)(VG_(get_running_tid)()), diff --git a/drd/drd_barrier.h b/drd/drd_barrier.h index 5c019a3..25dacd7 100644 --- a/drd/drd_barrier.h +++ b/drd/drd_barrier.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/drd_basics.h b/drd/drd_basics.h index 78b1794..2d69e5b 100644 --- a/drd/drd_basics.h +++ b/drd/drd_basics.h @@ -2,7 +2,7 @@ /* This file is part of DRD, a thread error detector. - Copyright (C) 2009 Bart Van Assche . + Copyright (C) 2009 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/drd_bitmap.c b/drd/drd_bitmap.c index 82b6a06..309823e 100644 --- a/drd/drd_bitmap.c +++ b/drd/drd_bitmap.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -129,7 +129,7 @@ void DRD_(bm_access_range_load)(struct bitmap* const bm, Addr a1, Addr a2) Addr b, b_next; tl_assert(bm); - tl_assert(a1 < a2); + tl_assert(a1 <= a2); tl_assert(a2 < first_address_with_higher_msb(a2)); tl_assert(a1 == first_address_with_same_lsb(a1)); tl_assert(a2 == first_address_with_same_lsb(a2)); @@ -226,7 +226,7 @@ void DRD_(bm_access_range_store)(struct bitmap* const bm, Addr b, b_next; tl_assert(bm); - tl_assert(a1 < a2); + tl_assert(a1 <= a2); tl_assert(a2 < first_address_with_higher_msb(a2)); tl_assert(a1 == first_address_with_same_lsb(a1)); tl_assert(a2 == first_address_with_same_lsb(a2)); @@ -368,7 +368,7 @@ DRD_(bm_has_any_load)(struct bitmap* const bm, const Addr a1, const Addr a2) tl_assert(a1 <= b_end && b_end <= a2); tl_assert(b_start < b_end); tl_assert(address_lsb(b_start) <= address_lsb(b_end - 1)); - + for (b0 = address_lsb(b_start); b0 <= address_lsb(b_end - 1); b0++) { if (bm0_is_set(p1->bm0_r, b0)) @@ -421,7 +421,7 @@ Bool DRD_(bm_has_any_store)(struct bitmap* const bm, tl_assert(a1 <= b_end && b_end <= a2); tl_assert(b_start < b_end); tl_assert(address_lsb(b_start) <= address_lsb(b_end - 1)); - + for (b0 = address_lsb(b_start); b0 <= address_lsb(b_end - 1); b0++) { if (bm0_is_set(p1->bm0_w, b0)) @@ -476,7 +476,7 @@ Bool DRD_(bm_has_any_access)(struct bitmap* const bm, tl_assert(a1 <= b_end && b_end <= a2); tl_assert(b_start < b_end); tl_assert(address_lsb(b_start) <= address_lsb(b_end - 1)); - + for (b0 = address_lsb(b_start); b0 <= address_lsb(b_end - 1); b0++) { /* @@ -809,7 +809,7 @@ Bool DRD_(bm_has_conflict_with)(struct bitmap* const bm, tl_assert(a1 <= b_end && b_end <= a2); tl_assert(b_start < b_end); tl_assert(address_lsb(b_start) <= address_lsb(b_end - 1)); - + for (b0 = address_lsb(b_start); b0 <= address_lsb(b_end - 1); b0++) { if (access_type == eLoad) diff --git a/drd/drd_bitmap.h b/drd/drd_bitmap.h index 55144c2..57d9423 100644 --- a/drd/drd_bitmap.h +++ b/drd/drd_bitmap.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -31,6 +31,9 @@ #include "pub_tool_basics.h" #include "pub_tool_oset.h" #include "pub_tool_libcbase.h" +#ifdef ENABLE_DRD_CONSISTENCY_CHECKS +#include "pub_tool_libcassert.h" +#endif /* Bitmap representation. A bitmap is a data structure in which two bits are @@ -41,7 +44,7 @@ /* Client addresses are split into bitfields as follows: * ------------------------------------------------------ - * | Address MSB | Address LSB | Ignored bits | + * | Address MSB | Address LSB | Ignored bits | * ------------------------------------------------------ * | Address MSB | UWord MSB | UWord LSB | Ignored bits | * ------------------------------------------------------ @@ -134,7 +137,7 @@ Addr make_address(const UWord a1, const UWord a0) #define BITS_PER_UWORD (8U * sizeof(UWord)) /** Log2 of BITS_PER_UWORD. */ -#if defined(VGA_x86) || defined(VGA_ppc32) +#if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_arm) #define BITS_PER_BITS_PER_UWORD 5 #elif defined(VGA_amd64) || defined(VGA_ppc64) #define BITS_PER_BITS_PER_UWORD 6 @@ -281,7 +284,7 @@ static __inline__ void bm0_clear_range(UWord* bm0, tl_assert(size == 0 || uword_msb(a) == uword_msb(a + size - 1)); #endif /* - * Note: although the expression below yields a correct result even if + * Note: although the expression below yields a correct result even if * size == 0, do not touch bm0[] if size == 0 because this might otherwise * cause an access of memory just past the end of the bm0[] array. */ diff --git a/drd/drd_bitmap2_node.c b/drd/drd_bitmap2_node.c index 6d016da..0241452 100644 --- a/drd/drd_bitmap2_node.c +++ b/drd/drd_bitmap2_node.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -118,7 +118,7 @@ void* DRD_(bm2_alloc_node)(HChar* const ec, const SizeT szB) /* * If szB < sizeof(struct bitmap2) then this function has been called to * allocate an AVL tree root node. Otherwise it has been called to allocate - * an AVL tree branch or leaf node. + * an AVL tree branch or leaf node. */ if (szB < sizeof(struct bitmap2)) return VG_(malloc)(ec, szB); diff --git a/drd/drd_clientobj.c b/drd/drd_clientobj.c index d3f55f0..a09c5c0 100644 --- a/drd/drd_clientobj.c +++ b/drd/drd_clientobj.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -107,13 +107,13 @@ Bool DRD_(clientobj_present)(const Addr a1, const Addr a2) { DrdClientobj *p; - tl_assert(a1 < a2); + tl_assert(a1 <= a2); VG_(OSetGen_ResetIter)(s_clientobj_set); for ( ; (p = VG_(OSetGen_Next)(s_clientobj_set)) != 0; ) { if (a1 <= p->any.a1 && p->any.a1 < a2) { - return True; + return True; } } return False; @@ -144,7 +144,10 @@ DrdClientobj* DRD_(clientobj_add)(const Addr a1, const ObjType t) p->any.first_observed_at = VG_(record_ExeContext)(VG_(get_running_tid)(), 0); VG_(OSetGen_Insert)(s_clientobj_set, p); tl_assert(VG_(OSetGen_Lookup)(s_clientobj_set, &a1) == p); - DRD_(start_suppression)(a1, a1 + 1, "clientobj"); + if (t == ClientHbvar) + DRD_(mark_hbvar)(a1); + else + DRD_(start_suppression)(a1, a1 + 1, "clientobj"); return p; } @@ -208,7 +211,7 @@ void DRD_(clientobj_stop_using_mem)(const Addr a1, const Addr a2) tl_assert(s_clientobj_set); - if (! DRD_(is_any_suppressed)(a1, a2)) + if (! DRD_(range_contains_suppression_or_hbvar)(a1, a2)) return; VG_(OSetGen_ResetIterAt)(s_clientobj_set, &a1); @@ -249,6 +252,7 @@ const char* DRD_(clientobj_type_name)(const ObjType t) { case ClientMutex: return "mutex"; case ClientCondvar: return "cond"; + case ClientHbvar: return "order annotation"; case ClientSemaphore: return "semaphore"; case ClientBarrier: return "barrier"; case ClientRwlock: return "rwlock"; diff --git a/drd/drd_clientobj.h b/drd/drd_clientobj.h index 13941c5..269fed2 100644 --- a/drd/drd_clientobj.h +++ b/drd/drd_clientobj.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -45,9 +45,10 @@ union drd_clientobj; typedef enum { ClientMutex = 1, ClientCondvar = 2, - ClientSemaphore = 3, - ClientBarrier = 4, - ClientRwlock = 5, + ClientHbvar = 3, + ClientSemaphore = 4, + ClientBarrier = 5, + ClientRwlock = 6, } ObjType; struct any @@ -83,7 +84,17 @@ struct cond_info ExeContext* first_observed_at; int waiter_count; Addr mutex; // Client mutex specified in pthread_cond_wait() call, and - // null if no client threads are currently waiting on this cond.var. + // null if no client threads are currently waiting on this cond.var. +}; + +struct hb_info +{ + Addr a1; + ObjType type; + void (*cleanup)(union drd_clientobj*); + void (*delete_thread)(union drd_clientobj*, DrdThreadId); + ExeContext* first_observed_at; + OSet* oset; // Per-thread order annotation information. }; struct semaphore_info @@ -135,6 +146,7 @@ typedef union drd_clientobj struct any any; struct mutex_info mutex; struct cond_info cond; + struct hb_info hb; struct semaphore_info semaphore; struct barrier_info barrier; struct rwlock_info rwlock; diff --git a/drd/drd_clientreq.c b/drd/drd_clientreq.c index 8aa89ff..d08d25e 100644 --- a/drd/drd_clientreq.c +++ b/drd/drd_clientreq.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -27,6 +27,7 @@ #include "drd_clientreq.h" #include "drd_cond.h" #include "drd_error.h" +#include "drd_hb.h" #include "drd_load_store.h" #include "drd_malloc_wrappers.h" #include "drd_mutex.h" @@ -82,7 +83,10 @@ static Bool handle_client_request(ThreadId vg_tid, UWord* arg, UWord* ret) case VG_USERREQ__FREELIKE_BLOCK: if (arg[1] && ! DRD_(freelike_block)(vg_tid, arg[1]/*addr*/)) { - GenericErrInfo GEI = { DRD_(thread_get_running_tid)() }; + GenericErrInfo GEI = { + .tid = DRD_(thread_get_running_tid)(), + .addr = 0, + }; VG_(maybe_record_error)(vg_tid, GenericErr, VG_(get_IP)(vg_tid), @@ -104,36 +108,23 @@ static Bool handle_client_request(ThreadId vg_tid, UWord* arg, UWord* ret) break; case VG_USERREQ__DRD_START_SUPPRESSION: + /*_VG_USERREQ__HG_ARANGE_MAKE_UNTRACKED*/ + case VG_USERREQ_TOOL_BASE('H','G') + 256 + 39: DRD_(start_suppression)(arg[1], arg[1] + arg[2], "client"); break; case VG_USERREQ__DRD_FINISH_SUPPRESSION: + /*_VG_USERREQ__HG_ARANGE_MAKE_TRACKED*/ + case VG_USERREQ_TOOL_BASE('H','G') + 256 + 40: DRD_(finish_suppression)(arg[1], arg[1] + arg[2]); break; case VG_USERREQ__DRD_ANNOTATE_HAPPENS_BEFORE: - { - struct cond_info* const cond_p = DRD_(cond_get)(arg[1]); - if (! cond_p) - { - DRD_(mutex_init)(arg[1], mutex_type_order_annotation); - DRD_(mutex_pre_lock)(arg[1], mutex_type_order_annotation, False); - DRD_(mutex_post_lock)(arg[1], mutex_type_order_annotation, False); - DRD_(mutex_unlock)(arg[1], mutex_type_order_annotation); - } - } + DRD_(hb_happens_before)(drd_tid, arg[1]); break; case VG_USERREQ__DRD_ANNOTATE_HAPPENS_AFTER: - { - struct cond_info* const cond_p = DRD_(cond_get)(arg[1]); - if (! cond_p) - { - DRD_(mutex_pre_lock)(arg[1], mutex_type_order_annotation, False); - DRD_(mutex_post_lock)(arg[1], mutex_type_order_annotation, False); - DRD_(mutex_unlock)(arg[1], mutex_type_order_annotation); - } - } + DRD_(hb_happens_after)(drd_tid, arg[1]); break; case VG_USERREQ__DRD_ANNOTATE_RWLOCK_CREATE: @@ -187,6 +178,11 @@ static Bool handle_client_request(ThreadId vg_tid, UWord* arg, UWord* ret) DRD_(rwlock_pre_unlock)(arg[1], user_rwlock); break; + case VG_USERREQ__SET_PTHREAD_COND_INITIALIZER: + DRD_(pthread_cond_initializer) = (Addr)arg[1]; + DRD_(pthread_cond_initializer_size) = arg[2]; + break; + case VG_USERREQ__DRD_START_NEW_SEGMENT: DRD_(thread_new_segment)(DRD_(PtThreadIdToDrdThreadId)(arg[1])); break; @@ -487,7 +483,7 @@ static Bool handle_client_request(ThreadId vg_tid, UWord* arg, UWord* ret) if (DRD_(thread_enter_synchr)(drd_tid) == 0) DRD_(rwlock_pre_unlock)(arg[1], pthread_rwlock); break; - + case VG_USERREQ__POST_RWLOCK_UNLOCK: DRD_(thread_leave_synchr)(drd_tid); break; @@ -497,6 +493,21 @@ static Bool handle_client_request(ThreadId vg_tid, UWord* arg, UWord* ret) DRD_(clean_memory)(arg[1], arg[2]); break; + case VG_USERREQ__HELGRIND_ANNOTATION_UNIMP: + { + /* Note: it is assumed below that the text arg[1] points to is never + * freed, e.g. because it points to static data. + */ + UnimpClReqInfo UICR = + { DRD_(thread_get_running_tid)(), (Char*)arg[1] }; + VG_(maybe_record_error)(vg_tid, + UnimpHgClReq, + VG_(get_IP)(vg_tid), + "", + &UICR); + } + break; + case VG_USERREQ__DRD_ANNOTATION_UNIMP: { /* Note: it is assumed below that the text arg[1] points to is never @@ -505,7 +516,7 @@ static Bool handle_client_request(ThreadId vg_tid, UWord* arg, UWord* ret) UnimpClReqInfo UICR = { DRD_(thread_get_running_tid)(), (Char*)arg[1] }; VG_(maybe_record_error)(vg_tid, - UnimpClReq, + UnimpDrdClReq, VG_(get_IP)(vg_tid), "", &UICR); diff --git a/drd/drd_clientreq.h b/drd/drd_clientreq.h index 0b55368..57268cb 100644 --- a/drd/drd_clientreq.h +++ b/drd/drd_clientreq.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -45,8 +45,14 @@ * source files. */ enum { + /* Declare the address and size of a variable with value + * PTHREAD_COND_INITIALIZER. + */ + VG_USERREQ__SET_PTHREAD_COND_INITIALIZER = VG_USERREQ_TOOL_BASE('D', 'r'), + /* args: address, size. */ + /* To ask the drd tool to start a new segment in the specified thread. */ - VG_USERREQ__DRD_START_NEW_SEGMENT = VG_USERREQ_TOOL_BASE('D', 'r'), + VG_USERREQ__DRD_START_NEW_SEGMENT, /* args: POSIX thread ID. */ /* Tell drd the pthread_t of the running thread. */ @@ -229,7 +235,6 @@ typedef enum { mutex_type_errorcheck_mutex = 2, mutex_type_default_mutex = 3, mutex_type_spinlock = 4, - mutex_type_order_annotation = 5, } MutexT; /** diff --git a/drd/drd_cond.c b/drd/drd_cond.c index 61f73eb..9565bb7 100644 --- a/drd/drd_cond.c +++ b/drd/drd_cond.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -27,12 +27,11 @@ #include "drd_cond.h" #include "drd_error.h" #include "drd_mutex.h" -#include "drd_suppression.h" #include "pub_tool_errormgr.h" /* VG_(maybe_record_error)() */ #include "pub_tool_libcassert.h" /* tl_assert() */ +#include "pub_tool_libcbase.h" /* VG_(memcmp)() */ #include "pub_tool_libcprint.h" /* VG_(printf)() */ #include "pub_tool_machine.h" /* VG_(get_IP)() */ -#include "pub_tool_options.h" /* VG_(clo_backtrace_size) */ #include "pub_tool_threadstate.h" /* VG_(get_running_tid)() */ @@ -47,6 +46,12 @@ static Bool DRD_(s_report_signal_unlocked) = True; static Bool DRD_(s_trace_cond); +/* Global variables. */ + +Addr DRD_(pthread_cond_initializer); +int DRD_(pthread_cond_initializer_size); + + /* Function definitions. */ void DRD_(cond_set_report_signal_unlocked)(const Bool r) @@ -63,8 +68,8 @@ static void DRD_(cond_initialize)(struct cond_info* const p, const Addr cond) { tl_assert(cond != 0); - tl_assert(p->a1 == cond); - tl_assert(p->type == ClientCondvar); + tl_assert(p->a1 == cond); + tl_assert(p->type == ClientCondvar); p->cleanup = (void(*)(DrdClientobj*))(DRD_(cond_cleanup)); p->delete_thread = 0; @@ -83,10 +88,13 @@ static void DRD_(cond_cleanup)(struct cond_info* p) { struct mutex_info* q; q = &(DRD_(clientobj_get)(p->mutex, ClientMutex)->mutex); - tl_assert(q); { - CondDestrErrInfo cde = { DRD_(thread_get_running_tid)(), - p->a1, q->a1, q->owner }; + CondDestrErrInfo cde = { + DRD_(thread_get_running_tid)(), + p->a1, + q ? q->a1 : 0, + q ? q->owner : DRD_INVALID_THREADID + }; VG_(maybe_record_error)(VG_(get_running_tid)(), CondDestrErr, VG_(get_IP)(VG_(get_running_tid)()), @@ -97,17 +105,40 @@ static void DRD_(cond_cleanup)(struct cond_info* p) } } +/** + * Report that the synchronization object at address 'addr' is of the + * wrong type. + */ +static void wrong_type(const Addr addr) +{ + GenericErrInfo gei = { + .tid = DRD_(thread_get_running_tid)(), + .addr = addr, + }; + VG_(maybe_record_error)(VG_(get_running_tid)(), + GenericErr, + VG_(get_IP)(VG_(get_running_tid)()), + "wrong type of synchronization object", + &gei); +} + static struct cond_info* cond_get_or_allocate(const Addr cond) { struct cond_info *p; tl_assert(offsetof(DrdClientobj, cond) == 0); p = &(DRD_(clientobj_get)(cond, ClientCondvar)->cond); - if (p == 0) + if (p) + return p; + + if (DRD_(clientobj_present)(cond, cond + 1)) { - p = &(DRD_(clientobj_add)(cond, ClientCondvar)->cond); - DRD_(cond_initialize)(p, cond); + wrong_type(cond); + return 0; } + + p = &(DRD_(clientobj_add)(cond, ClientCondvar)->cond); + DRD_(cond_initialize)(p, cond); return p; } @@ -184,10 +215,11 @@ void DRD_(cond_post_destroy)(const Addr cond) DRD_(clientobj_remove)(p->a1, ClientCondvar); } -/** Called before pthread_cond_wait(). Note: before this function is called, - * mutex_unlock() has already been called from drd_clientreq.c. +/** + * Called before pthread_cond_wait(). Note: before this function is called, + * mutex_unlock() has already been called from drd_clientreq.c. */ -int DRD_(cond_pre_wait)(const Addr cond, const Addr mutex) +void DRD_(cond_pre_wait)(const Addr cond, const Addr mutex) { struct cond_info* p; struct mutex_info* q; @@ -201,7 +233,16 @@ int DRD_(cond_pre_wait)(const Addr cond, const Addr mutex) } p = cond_get_or_allocate(cond); - tl_assert(p); + if (!p) + { + CondErrInfo cei = { .tid = DRD_(thread_get_running_tid)(), .cond = cond }; + VG_(maybe_record_error)(VG_(get_running_tid)(), + CondErr, + VG_(get_IP)(VG_(get_running_tid)()), + "not a condition variable", + &cei); + return; + } if (p->waiter_count == 0) { @@ -238,11 +279,13 @@ int DRD_(cond_pre_wait)(const Addr cond, const Addr mutex) DRD_(not_a_mutex)(p->mutex); } - return ++p->waiter_count; + ++p->waiter_count; } -/** Called after pthread_cond_wait(). */ -int DRD_(cond_post_wait)(const Addr cond) +/** + * Called after pthread_cond_wait(). + */ +void DRD_(cond_post_wait)(const Addr cond) { struct cond_info* p; @@ -255,55 +298,89 @@ int DRD_(cond_post_wait)(const Addr cond) } p = DRD_(cond_get)(cond); - if (p) + if (!p) + { + struct mutex_info* q; + q = &(DRD_(clientobj_get)(p->mutex, ClientMutex)->mutex); + { + CondDestrErrInfo cde = { + DRD_(thread_get_running_tid)(), + p->a1, + q ? q->a1 : 0, + q ? q->owner : DRD_INVALID_THREADID + }; + VG_(maybe_record_error)(VG_(get_running_tid)(), + CondDestrErr, + VG_(get_IP)(VG_(get_running_tid)()), + "condition variable has been destroyed while" + " being waited upon", + &cde); + } + return; + } + + if (p->waiter_count > 0) { - if (p->waiter_count > 0) + --p->waiter_count; + if (p->waiter_count == 0) { - --p->waiter_count; - if (p->waiter_count == 0) - { - p->mutex = 0; - } + p->mutex = 0; } - return p->waiter_count; } - return 0; } -static void DRD_(cond_signal)(Addr const cond) +static void cond_signal(const DrdThreadId tid, struct cond_info* const cond_p) { const ThreadId vg_tid = VG_(get_running_tid)(); const DrdThreadId drd_tid = DRD_(VgThreadIdToDrdThreadId)(vg_tid); - struct cond_info* const cond_p = DRD_(cond_get)(cond); - if (cond_p && cond_p->waiter_count > 0) + tl_assert(cond_p); + + if (cond_p->waiter_count > 0) { if (DRD_(s_report_signal_unlocked) - && ! DRD_(mutex_is_locked_by)(cond_p->mutex, drd_tid)) + && ! DRD_(mutex_is_locked_by)(cond_p->mutex, drd_tid)) { - /* A signal is sent while the associated mutex has not been locked. */ - /* This can indicate but is not necessarily a race condition. */ - CondRaceErrInfo cei = { .tid = DRD_(thread_get_running_tid)(), - .cond = cond, - .mutex = cond_p->mutex, - }; - VG_(maybe_record_error)(vg_tid, - CondRaceErr, - VG_(get_IP)(vg_tid), - "CondErr", - &cei); + /* + * A signal is sent while the associated mutex has not been locked. + * This can indicate but is not necessarily a race condition. + */ + CondRaceErrInfo cei = { .tid = DRD_(thread_get_running_tid)(), + .cond = cond_p->a1, + .mutex = cond_p->mutex, + }; + VG_(maybe_record_error)(vg_tid, + CondRaceErr, + VG_(get_IP)(vg_tid), + "CondErr", + &cei); } } else { - /* No other thread is waiting for the signal, hence the signal will be */ - /* lost. This is normal in a POSIX threads application. */ + /* + * No other thread is waiting for the signal, hence the signal will + * be lost. This is normal in a POSIX threads application. + */ } } +static void not_initialized(Addr const cond) +{ + CondErrInfo cei = { .tid = DRD_(thread_get_running_tid)(), .cond = cond }; + VG_(maybe_record_error)(VG_(get_running_tid)(), + CondErr, + VG_(get_IP)(VG_(get_running_tid)()), + "condition variable has not been initialized", + &cei); +} + /** Called before pthread_cond_signal(). */ void DRD_(cond_pre_signal)(Addr const cond) { + struct cond_info* p; + + p = DRD_(cond_get)(cond); if (DRD_(s_trace_cond)) { VG_(message)(Vg_UserMsg, @@ -312,12 +389,25 @@ void DRD_(cond_pre_signal)(Addr const cond) cond); } - DRD_(cond_signal)(cond); + tl_assert(DRD_(pthread_cond_initializer)); + if (!p && VG_(memcmp)((void*)cond, (void*)DRD_(pthread_cond_initializer), + DRD_(pthread_cond_initializer_size)) != 0) + { + not_initialized(cond); + return; + } + + if (!p) + p = cond_get_or_allocate(cond); + + cond_signal(DRD_(thread_get_running_tid)(), p); } /** Called before pthread_cond_broadcast(). */ void DRD_(cond_pre_broadcast)(Addr const cond) { + struct cond_info* p; + if (DRD_(s_trace_cond)) { VG_(message)(Vg_UserMsg, @@ -326,5 +416,17 @@ void DRD_(cond_pre_broadcast)(Addr const cond) cond); } - DRD_(cond_signal)(cond); + p = DRD_(cond_get)(cond); + tl_assert(DRD_(pthread_cond_initializer)); + if (!p && VG_(memcmp)((void*)cond, (void*)DRD_(pthread_cond_initializer), + DRD_(pthread_cond_initializer_size)) != 0) + { + not_initialized(cond); + return; + } + + if (!p) + p = cond_get_or_allocate(cond); + + cond_signal(DRD_(thread_get_running_tid)(), p); } diff --git a/drd/drd_cond.h b/drd/drd_cond.h index be98b96..7e386ae 100644 --- a/drd/drd_cond.h +++ b/drd/drd_cond.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -36,6 +36,12 @@ struct cond_info; +/* Variable declarations. */ + +extern Addr DRD_(pthread_cond_initializer); +extern int DRD_(pthread_cond_initializer_size); + + /* Function declarations. */ void DRD_(cond_set_report_signal_unlocked)(const Bool r); @@ -43,8 +49,8 @@ void DRD_(cond_set_trace)(const Bool trace_cond); struct cond_info* DRD_(cond_get)(const Addr cond); void DRD_(cond_pre_init)(const Addr cond); void DRD_(cond_post_destroy)(const Addr cond); -int DRD_(cond_pre_wait)(const Addr cond, const Addr mutex); -int DRD_(cond_post_wait)(const Addr cond); +void DRD_(cond_pre_wait)(const Addr cond, const Addr mutex); +void DRD_(cond_post_wait)(const Addr cond); void DRD_(cond_pre_signal)(const Addr cond); void DRD_(cond_pre_broadcast)(const Addr cond); diff --git a/drd/drd_cond_initializer.c b/drd/drd_cond_initializer.c new file mode 100644 index 0000000..ab041f0 --- /dev/null +++ b/drd/drd_cond_initializer.c @@ -0,0 +1,8 @@ +/* Make the value of PTHREAD_COND_INITIALIZER available to DRD. */ + +#include "drd_cond.h" +#include + +static pthread_cond_t pthread_cond_initializer = PTHREAD_COND_INITIALIZER; +Addr DRD_(pthread_cond_initializer) = (Addr)&pthread_cond_initializer; +int DRD_(pthread_cond_initializer_size) = sizeof(pthread_cond_initializer); diff --git a/drd/drd_error.c b/drd/drd_error.c index 7b1b8a5..88452bf 100644 --- a/drd/drd_error.c +++ b/drd/drd_error.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -190,7 +190,7 @@ void drd_report_data_race(Error* const err, const DataRaceErrInfo* const dri) /** * Compare two error contexts. The core function VG_(maybe_record_error)() * calls this function to compare error contexts such that errors that occur - * repeatedly are only printed once. This function is only called by the core + * repeatedly are only printed once. This function is only called by the core * if the error kind of e1 and e2 matches and if the ExeContext's of e1 and * e2 also match. */ @@ -371,9 +371,11 @@ static void drd_tool_error_pp(Error* const e) break; } case GenericErr: { - //GenericErrInfo* gei =(GenericErrInfo*)(VG_(get_error_extra)(e)); + GenericErrInfo* gei = (GenericErrInfo*)(VG_(get_error_extra)(e)); VG_(message)(Vg_UserMsg, "%s\n", VG_(get_error_string)(e)); VG_(pp_ExeContext)(VG_(get_error_where)(e)); + if (gei->addr) + first_observed(gei->addr); break; } case InvalidThreadId: { @@ -383,15 +385,24 @@ static void drd_tool_error_pp(Error* const e) VG_(pp_ExeContext)(VG_(get_error_where)(e)); break; } - case UnimpClReq: { + case UnimpHgClReq: { UnimpClReqInfo* uicr =(UnimpClReqInfo*)(VG_(get_error_extra)(e)); VG_(message)(Vg_UserMsg, "The annotation macro %s has not yet been implemented in" - " \n", + " \n", /*VG_(get_error_string)(e),*/ uicr->descr); VG_(pp_ExeContext)(VG_(get_error_where)(e)); break; } + case UnimpDrdClReq: { + UnimpClReqInfo* uicr =(UnimpClReqInfo*)(VG_(get_error_extra)(e)); + VG_(message)(Vg_UserMsg, + "The annotation macro %s has not yet been implemented in" + " \n", + uicr->descr); + VG_(pp_ExeContext)(VG_(get_error_where)(e)); + break; + } default: VG_(message)(Vg_UserMsg, "%s\n", @@ -429,7 +440,9 @@ static UInt drd_tool_error_update_extra(Error* e) return sizeof(GenericErrInfo); case InvalidThreadId: return sizeof(InvalidThreadIdInfo); - case UnimpClReq: + case UnimpHgClReq: + return sizeof(UnimpClReqInfo); + case UnimpDrdClReq: return sizeof(UnimpClReqInfo); default: tl_assert(False); @@ -472,8 +485,10 @@ static Bool drd_is_recognized_suppression(Char* const name, Supp* const supp) skind = GenericErr; else if (VG_(strcmp)(name, STR_InvalidThreadId) == 0) skind = InvalidThreadId; - else if (VG_(strcmp)(name, STR_UnimpClReq) == 0) - skind = UnimpClReq; + else if (VG_(strcmp)(name, STR_UnimpHgClReq) == 0) + skind = UnimpHgClReq; + else if (VG_(strcmp)(name, STR_UnimpDrdClReq) == 0) + skind = UnimpDrdClReq; else return False; @@ -520,7 +535,8 @@ static Char* drd_get_error_name(Error* e) case HoldtimeErr: return VGAPPEND(STR_, HoldtimeErr); case GenericErr: return VGAPPEND(STR_, GenericErr); case InvalidThreadId: return VGAPPEND(STR_, InvalidThreadId); - case UnimpClReq: return VGAPPEND(STR_, UnimpClReq); + case UnimpHgClReq: return VGAPPEND(STR_, UnimpHgClReq); + case UnimpDrdClReq: return VGAPPEND(STR_, UnimpDrdClReq); default: tl_assert(0); } diff --git a/drd/drd_error.h b/drd/drd_error.h index 6af6cdd..a900291 100644 --- a/drd/drd_error.h +++ b/drd/drd_error.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -61,18 +61,20 @@ typedef enum { GenericErr = 11, #define STR_InvalidThreadId "InvalidThreadId" InvalidThreadId = 12, -#define STR_UnimpClReq "UnimpClReq" - UnimpClReq = 13, +#define STR_UnimpHgClReq "UnimpHgClReq" + UnimpHgClReq = 13, +#define STR_UnimpDrdClReq "UnimpDrdClReq" + UnimpDrdClReq = 14, } DrdErrorKind; /* The classification of a faulting address. */ -typedef -enum { +typedef +enum { //Undescribed, // as-yet unclassified - eStack, + eStack, eUnknown, // classification yielded nothing useful //Freed, - eMallocd, + eMallocd, eSegment, // in a segment (as defined in pub_tool_debuginfo.h) //UserG, // in a user-defined block //Mempool, // in a mempool @@ -163,6 +165,7 @@ typedef struct { typedef struct { DrdThreadId tid; + Addr addr; } GenericErrInfo; typedef struct { diff --git a/drd/drd_hb.c b/drd/drd_hb.c new file mode 100644 index 0000000..6b7151f --- /dev/null +++ b/drd/drd_hb.c @@ -0,0 +1,261 @@ +/* -*- mode: C; c-basic-offset: 3; -*- */ +/* + This file is part of drd, a thread error detector. + + Copyright (C) 2006-2010 Bart Van Assche . + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + + +#include "drd_clientobj.h" +#include "drd_hb.h" +#include "drd_error.h" +#include "pub_tool_errormgr.h" /* VG_(maybe_record_error)() */ +#include "pub_tool_libcassert.h" /* tl_assert() */ +#include "pub_tool_libcprint.h" /* VG_(printf)() */ +#include "pub_tool_machine.h" /* VG_(get_IP)() */ +#include "pub_tool_mallocfree.h" /* VG_(malloc)(), VG_(free)()*/ +#include "pub_tool_threadstate.h" /* VG_(get_running_tid)() */ + + +/* Type definitions. */ + +/** Per-thread hb information. */ +struct hb_thread_info +{ + UWord tid; // A DrdThreadId declared as UWord because + // this member variable is the key of an OSet. + Segment* sg; // Segment created before most recent + // ANNOTATE_HAPPENS_BEFORE(). +}; + + +/* Local functions. */ + +static void DRD_(hb_cleanup)(struct hb_info* p); + + +/* Local variables. */ + +static Bool DRD_(s_trace_hb); + + +/* Function definitions. */ + +void DRD_(hb_set_trace)(const Bool trace_hb) +{ + DRD_(s_trace_hb) = trace_hb; +} + +/** + * Initialize the structure *p with the specified thread ID. + */ +static +void DRD_(hb_thread_initialize)(struct hb_thread_info* const p, + const DrdThreadId tid) +{ + p->tid = tid; + p->sg = 0; +} + +/** + * Deallocate the memory that is owned by members of struct hb_thread_info. + */ +static void DRD_(hb_thread_destroy)(struct hb_thread_info* const p) +{ + tl_assert(p); + DRD_(sg_put)(p->sg); +} + +static +void DRD_(hb_initialize)(struct hb_info* const p, const Addr hb) +{ + tl_assert(hb != 0); + tl_assert(p->a1 == hb); + tl_assert(p->type == ClientHbvar); + + p->cleanup = (void(*)(DrdClientobj*))(DRD_(hb_cleanup)); + p->delete_thread = 0; + p->oset = VG_(OSetGen_Create)(0, 0, VG_(malloc), "drd.hb", + VG_(free)); +} + +/** + * Free the memory that was allocated by hb_initialize(). Called by + * DRD_(clientobj_remove)(). + */ +static void DRD_(hb_cleanup)(struct hb_info* p) +{ + struct hb_thread_info* r; + + tl_assert(p); + VG_(OSetGen_ResetIter)(p->oset); + for ( ; (r = VG_(OSetGen_Next)(p->oset)) != 0; ) + DRD_(hb_thread_destroy)(r); + VG_(OSetGen_Destroy)(p->oset); +} + +/** + * Report that the synchronization object at address 'addr' is of the + * wrong type. + */ +static void wrong_type(const Addr addr) +{ + GenericErrInfo gei = { + .tid = DRD_(thread_get_running_tid)(), + .addr = addr, + }; + VG_(maybe_record_error)(VG_(get_running_tid)(), + GenericErr, + VG_(get_IP)(VG_(get_running_tid)()), + "wrong type of synchronization object", + &gei); +} + +struct hb_info* DRD_(hb_get_or_allocate)(const Addr hb) +{ + struct hb_info *p; + + tl_assert(offsetof(DrdClientobj, hb) == 0); + p = &(DRD_(clientobj_get)(hb, ClientHbvar)->hb); + if (p) + return p; + + if (DRD_(clientobj_present)(hb, hb + 1)) + { + wrong_type(hb); + return 0; + } + + p = &(DRD_(clientobj_add)(hb, ClientHbvar)->hb); + DRD_(hb_initialize)(p, hb); + return p; +} + +struct hb_info* DRD_(hb_get)(const Addr hb) +{ + tl_assert(offsetof(DrdClientobj, hb) == 0); + return &(DRD_(clientobj_get)(hb, ClientHbvar)->hb); +} + +/** Called because of a happens-before annotation. */ +void DRD_(hb_happens_before)(const DrdThreadId tid, Addr const hb) +{ + const ThreadId vg_tid = VG_(get_running_tid)(); + const DrdThreadId drd_tid = DRD_(VgThreadIdToDrdThreadId)(vg_tid); + const UWord word_tid = tid; + struct hb_info* p; + struct hb_thread_info* q; + + p = DRD_(hb_get_or_allocate)(hb); + if (DRD_(s_trace_hb)) + { + VG_(message)(Vg_UserMsg, + "[%d] happens_before 0x%lx\n", + DRD_(thread_get_running_tid)(), + hb); + } + + if (!p) + return; + + /* Allocate the per-thread data structure if necessary. */ + q = VG_(OSetGen_Lookup)(p->oset, &word_tid); + if (!q) + { + q = VG_(OSetGen_AllocNode)(p->oset, sizeof(*q)); + DRD_(hb_thread_initialize)(q, tid); + VG_(OSetGen_Insert)(p->oset, q); + tl_assert(VG_(OSetGen_Lookup)(p->oset, &word_tid) == q); + } + + /* + * Store a pointer to the latest segment of the current thread in the + * per-thread data structure. + */ + DRD_(thread_get_latest_segment)(&q->sg, tid); + DRD_(thread_new_segment)(drd_tid); +} + +/** Called because of a happens-after annotation. */ +void DRD_(hb_happens_after)(const DrdThreadId tid, const Addr hb) +{ + struct hb_info* p; + struct hb_thread_info* q; + VectorClock old_vc; + + p = DRD_(hb_get_or_allocate)(hb); + + if (DRD_(s_trace_hb)) + { + VG_(message)(Vg_UserMsg, "[%d] happens_after 0x%lx\n", + DRD_(thread_get_running_tid)(), hb); + } + + if (!p) + return; + + DRD_(thread_new_segment)(tid); + + /* + * Combine all vector clocks that were stored because of happens-before + * annotations with the vector clock of the current thread. + */ + DRD_(vc_copy)(&old_vc, &DRD_(g_threadinfo)[tid].last->vc); + VG_(OSetGen_ResetIter)(p->oset); + for ( ; (q = VG_(OSetGen_Next)(p->oset)) != 0; ) + { + if (q->tid != tid) + { + tl_assert(q->sg); + DRD_(vc_combine)(&DRD_(g_threadinfo)[tid].last->vc, &q->sg->vc); + } + } + DRD_(thread_update_conflict_set)(tid, &old_vc); + DRD_(vc_cleanup)(&old_vc); +} + +/** Called because of a happens-done annotation. */ +void DRD_(hb_happens_done)(const DrdThreadId tid, const Addr hb) +{ + struct hb_info* p; + + if (DRD_(s_trace_hb)) + { + VG_(message)(Vg_UserMsg, "[%d] happens_done 0x%lx\n", + DRD_(thread_get_running_tid)(), hb); + } + + p = DRD_(hb_get)(hb); + if (!p) + { + GenericErrInfo gei = { + .tid = DRD_(thread_get_running_tid)(), + .addr = hb, + }; + VG_(maybe_record_error)(VG_(get_running_tid)(), + GenericErr, + VG_(get_IP)(VG_(get_running_tid)()), + "missing happens-before annotation", + &gei); + return; + } + + DRD_(clientobj_remove)(p->a1, ClientHbvar); +} diff --git a/drd/drd_hb.h b/drd/drd_hb.h new file mode 100644 index 0000000..62c6477 --- /dev/null +++ b/drd/drd_hb.h @@ -0,0 +1,51 @@ +/* -*- mode: C; c-basic-offset: 3; -*- */ +/* + This file is part of drd, a thread error detector. + + Copyright (C) 2006-2010 Bart Van Assche . + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + + +#ifndef __DRD_HB_H +#define __DRD_HB_H + + +#include "drd_thread.h" /* DrdThreadid */ +#include "pub_tool_basics.h" /* Addr */ + + +/* Forward declarations. */ + +struct hb_info; + + +/* Function declarations. */ + +void DRD_(hb_set_trace)(const Bool trace_hb); +struct hb_info* DRD_(hb_get)(const Addr hb); +struct hb_info* DRD_(hb_get_or_allocate)(const Addr hb); +void DRD_(hb_init)(const Addr hb); +void DRD_(hb_destroy)(const Addr hb); +void DRD_(hb_happens_after)(const DrdThreadId tid, const Addr hb); +void DRD_(hb_happens_before)(const DrdThreadId tid, const Addr hb); +void DRD_(hb_happens_done)(const DrdThreadId tid, const Addr hb); + + +#endif /* __DRD_HB_H */ diff --git a/drd/drd_load_store.c b/drd/drd_load_store.c index 930827e..74ef230 100644 --- a/drd/drd_load_store.c +++ b/drd/drd_load_store.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -43,9 +43,11 @@ #elif defined(VGA_amd64) #define STACK_POINTER_OFFSET OFFSET_amd64_RSP #elif defined(VGA_ppc32) -#define STACK_POINTER_OFFSET ((OFFSET_ppc32_GPR0 + OFFSET_ppc32_GPR2) / 2) +#define STACK_POINTER_OFFSET OFFSET_ppc32_GPR1 #elif defined(VGA_ppc64) -#define STACK_POINTER_OFFSET ((OFFSET_ppc64_GPR0 + OFFSET_ppc64_GPR2) / 2) +#define STACK_POINTER_OFFSET OFFSET_ppc64_GPR1 +#elif defined(VGA_arm) +#define STACK_POINTER_OFFSET OFFSET_arm_R13 #else #error Unknown architecture. #endif @@ -147,8 +149,8 @@ VG_REGPARM(2) void DRD_(trace_load)(Addr addr, SizeT size) { #ifdef ENABLE_DRD_CONSISTENCY_CHECKS /* The assert below has been commented out because of performance reasons.*/ - tl_assert(thread_get_running_tid() - == VgThreadIdToDrdThreadId(VG_(get_running_tid()))); + tl_assert(DRD_(thread_get_running_tid)() + == DRD_(VgThreadIdToDrdThreadId)(VG_(get_running_tid()))); #endif if (DRD_(running_thread_is_recording_loads)() @@ -213,8 +215,8 @@ VG_REGPARM(2) void DRD_(trace_store)(Addr addr, SizeT size) { #ifdef ENABLE_DRD_CONSISTENCY_CHECKS /* The assert below has been commented out because of performance reasons.*/ - tl_assert(thread_get_running_tid() - == VgThreadIdToDrdThreadId(VG_(get_running_tid()))); + tl_assert(DRD_(thread_get_running_tid)() + == DRD_(VgThreadIdToDrdThreadId)(VG_(get_running_tid()))); #endif if (DRD_(running_thread_is_recording_stores)() @@ -440,7 +442,7 @@ static void instrument_store(IRSB* const bb, IRSB* DRD_(instrument)(VgCallbackClosure* const closure, IRSB* const bb_in, VexGuestLayout* const layout, - VexGuestExtents* const vge, + VexGuestExtents* const vge, IRType const gWordTy, IRType const hWordTy) { @@ -460,8 +462,7 @@ IRSB* DRD_(instrument)(VgCallbackClosure* const closure, { IRStmt* const st = bb_in->stmts[i]; tl_assert(st); - if (st->tag == Ist_NoOp) - continue; + tl_assert(isFlatIRStmt(st)); switch (st->tag) { @@ -489,8 +490,7 @@ IRSB* DRD_(instrument)(VgCallbackClosure* const closure, break; case Ist_Store: - if (instrument && /* ignore stores resulting from st{d,w}cx. */ - st->Ist.Store.resSC == IRTemp_INVALID) + if (instrument) { instrument_store(bb, st->Ist.Store.addr, @@ -576,10 +576,42 @@ IRSB* DRD_(instrument)(VgCallbackClosure* const closure, addStmtToIRSB(bb, st); break; - default: + case Ist_LLSC: { + /* Ignore store-conditionals, and handle load-linked's + exactly like normal loads. */ + IRType dataTy; + if (st->Ist.LLSC.storedata == NULL) + { + /* LL */ + dataTy = typeOfIRTemp(bb_in->tyenv, st->Ist.LLSC.result); + if (instrument) { + instrument_load(bb, + st->Ist.LLSC.addr, + sizeofIRType(dataTy)); + } + } + else + { + /* SC */ + /*ignore */ + } addStmtToIRSB(bb, st); break; } + + case Ist_NoOp: + case Ist_AbiHint: + case Ist_Put: + case Ist_PutI: + case Ist_Exit: + /* None of these can contain any memory references. */ + addStmtToIRSB(bb, st); + break; + + default: + ppIRStmt(st); + tl_assert(0); + } } return bb; diff --git a/drd/drd_load_store.h b/drd/drd_load_store.h index 974defc..46b763f 100644 --- a/drd/drd_load_store.h +++ b/drd/drd_load_store.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -43,7 +43,7 @@ void DRD_(set_first_race_only)(const Bool fro); IRSB* DRD_(instrument)(VgCallbackClosure* const closure, IRSB* const bb_in, VexGuestLayout* const layout, - VexGuestExtents* const vge, + VexGuestExtents* const vge, IRType const gWordTy, IRType const hWordTy); void DRD_(trace_mem_access)(const Addr addr, const SizeT size, diff --git a/drd/drd_main.c b/drd/drd_main.c index f3a5db0..e3751eb 100644 --- a/drd/drd_main.c +++ b/drd/drd_main.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -55,9 +55,11 @@ /* Local variables. */ -static Bool DRD_(s_print_stats) = False; -static Bool DRD_(s_var_info) = False; -static Bool DRD_(s_show_stack_usage) = False; +static Bool s_free_is_write = False; +static Bool s_print_stats = False; +static Bool s_var_info = False; +static Bool s_show_stack_usage = False; +static Bool s_trace_alloc = False; /** @@ -88,16 +90,17 @@ static Bool DRD_(process_cmd_line_option)(Char* arg) Char* trace_address = 0; if VG_BOOL_CLO(arg, "--check-stack-var", check_stack_accesses) {} - else if VG_BOOL_CLO(arg, "--drd-stats", DRD_(s_print_stats)) {} + else if VG_BOOL_CLO(arg, "--drd-stats", s_print_stats) {} else if VG_BOOL_CLO(arg, "--first-race-only", first_race_only) {} + else if VG_BOOL_CLO(arg, "--free-is-write", s_free_is_write) {} else if VG_BOOL_CLO(arg,"--report-signal-unlocked",report_signal_unlocked) {} else if VG_BOOL_CLO(arg, "--segment-merging", segment_merging) {} else if VG_INT_CLO (arg, "--segment-merging-interval", segment_merge_interval) {} else if VG_BOOL_CLO(arg, "--show-confl-seg", show_confl_seg) {} - else if VG_BOOL_CLO(arg, "--show-stack-usage", - DRD_(s_show_stack_usage)) {} + else if VG_BOOL_CLO(arg, "--show-stack-usage", s_show_stack_usage) {} + else if VG_BOOL_CLO(arg, "--trace-alloc", s_trace_alloc) {} else if VG_BOOL_CLO(arg, "--trace-barrier", trace_barrier) {} else if VG_BOOL_CLO(arg, "--trace-clientobj", trace_clientobj) {} else if VG_BOOL_CLO(arg, "--trace-cond", trace_cond) {} @@ -110,7 +113,7 @@ static Bool DRD_(process_cmd_line_option)(Char* arg) else if VG_BOOL_CLO(arg, "--trace-segment", trace_segment) {} else if VG_BOOL_CLO(arg, "--trace-semaphore", trace_semaphore) {} else if VG_BOOL_CLO(arg, "--trace-suppr", trace_suppression) {} - else if VG_BOOL_CLO(arg, "--var-info", DRD_(s_var_info)) {} + else if VG_BOOL_CLO(arg, "--var-info", s_var_info) {} else if VG_INT_CLO (arg, "--exclusive-threshold", exclusive_threshold_ms) {} else if VG_INT_CLO (arg, "--shared-threshold", shared_threshold_ms) {} else if VG_STR_CLO (arg, "--trace-addr", trace_address) {} @@ -184,6 +187,8 @@ static void DRD_(print_usage)(void) " writer lock is held longer than the specified time (in milliseconds).\n" " --first-race-only=yes|no Only report the first data race that occurs on\n" " a memory location instead of all races [no].\n" +" --free-is-write=yes|no Whether to report races between freeing memory\n" +" and subsequent accesses of that memory[no].\n" " --report-signal-unlocked=yes|no Whether to report calls to\n" " pthread_cond_signal() where the mutex associated\n" " with the signal via pthread_cond_wait() is not\n" @@ -203,6 +208,7 @@ static void DRD_(print_usage)(void) " drd options for monitoring process behavior:\n" " --trace-addr=
Trace all load and store activity for the.\n" " specified address [off].\n" +" --trace-alloc=yes|no Trace all memory allocations and deallocations\n"" [no].\n" " --trace-barrier=yes|no Trace all barrier activity [no].\n" " --trace-cond=yes|no Trace all condition variable activity [no].\n" " --trace-fork-join=yes|no Trace all thread fork/join activity [no].\n" @@ -214,7 +220,7 @@ DRD_(thread_get_segment_merge_interval)() } static void DRD_(print_debug_usage)(void) -{ +{ VG_(printf)( " --drd-stats=yes|no Print statistics about DRD activity [no].\n" " --trace-clientobj=yes|no Trace all client object activity [no].\n" @@ -260,8 +266,6 @@ static void drd_pre_mem_read_asciiz(const CorePart part, p++; size++; } - // To do: find out what a reasonable upper limit on 'size' is. - tl_assert(size < 4096); if (size > 0) { DRD_(trace_load)(a, size); @@ -281,15 +285,21 @@ static void drd_post_mem_write(const CorePart part, } static __inline__ -void drd_start_using_mem(const Addr a1, const SizeT len) +void drd_start_using_mem(const Addr a1, const SizeT len, + const Bool is_stack_mem) { - tl_assert(a1 < a1 + len); + tl_assert(a1 <= a1 + len); + + if (!is_stack_mem && s_trace_alloc) + VG_(message)(Vg_UserMsg, "Started using memory range 0x%lx + %ld%s\n", + a1, len, DRD_(running_thread_inside_pthread_create)() + ? " (inside pthread_create())" : ""); if (UNLIKELY(DRD_(any_address_is_traced)())) { DRD_(trace_mem_access)(a1, len, eStart); } - + if (UNLIKELY(DRD_(running_thread_inside_pthread_create)())) { DRD_(start_suppression)(a1, a1 + len, "pthread_create()"); @@ -300,14 +310,14 @@ static void drd_start_using_mem_w_ecu(const Addr a1, const SizeT len, UInt ec_uniq) { - drd_start_using_mem(a1, len); + drd_start_using_mem(a1, len, False); } static void drd_start_using_mem_w_tid(const Addr a1, const SizeT len, ThreadId tid) { - drd_start_using_mem(a1, len); + drd_start_using_mem(a1, len, False); } static __inline__ @@ -316,18 +326,23 @@ void drd_stop_using_mem(const Addr a1, const SizeT len, { const Addr a2 = a1 + len; - tl_assert(a1 < a2); + tl_assert(a1 <= a2); if (UNLIKELY(DRD_(any_address_is_traced)())) - { DRD_(trace_mem_access)(a1, len, eEnd); - } - if (! is_stack_mem || DRD_(get_check_stack_accesses)()) + + if (!is_stack_mem && s_trace_alloc) + VG_(message)(Vg_UserMsg, "Stopped using memory range 0x%lx + %ld\n", + a1, len); + + if (!is_stack_mem || DRD_(get_check_stack_accesses)()) { - DRD_(thread_stop_using_mem)(a1, a2); + DRD_(thread_stop_using_mem)(a1, a2, !is_stack_mem && s_free_is_write); DRD_(clientobj_stop_using_mem)(a1, a2); DRD_(suppression_stop_using_mem)(a1, a2); } + if (!is_stack_mem && s_free_is_write) + DRD_(trace_store)(a1, len); } static __inline__ @@ -344,7 +359,7 @@ void DRD_(clean_memory)(const Addr a1, const SizeT len) { const Bool is_stack_memory = DRD_(thread_address_on_any_stack)(a1); drd_stop_using_mem(a1, len, is_stack_memory); - drd_start_using_mem(a1, len); + drd_start_using_mem(a1, len, is_stack_memory); } /** @@ -403,7 +418,7 @@ void drd_start_using_mem_w_perms(const Addr a, const SizeT len, { DRD_(thread_set_vg_running_tid)(VG_(get_running_tid)()); - drd_start_using_mem(a, len); + drd_start_using_mem(a, len, False); DRD_(suppress_relocation_conflicts)(a, len); } @@ -416,8 +431,9 @@ void drd_start_using_mem_stack(const Addr a, const SizeT len) { DRD_(thread_set_stack_min)(DRD_(thread_get_running_tid)(), a - VG_STACK_REDZONE_SZB); - drd_start_using_mem(a - VG_STACK_REDZONE_SZB, - len + VG_STACK_REDZONE_SZB); + drd_start_using_mem(a - VG_STACK_REDZONE_SZB, + len + VG_STACK_REDZONE_SZB, + True); } /* Called by the core when the stack of a thread shrinks, to indicate that */ @@ -432,6 +448,74 @@ void drd_stop_using_mem_stack(const Addr a, const SizeT len) True); } +static +Bool on_alt_stack(const Addr a) +{ + ThreadId vg_tid; + Addr alt_min; + SizeT alt_size; + + vg_tid = VG_(get_running_tid)(); + alt_min = VG_(thread_get_altstack_min)(vg_tid); + alt_size = VG_(thread_get_altstack_size)(vg_tid); + return (SizeT)(a - alt_min) < alt_size; +} + +static +void drd_start_using_mem_alt_stack(const Addr a, const SizeT len) +{ + if (!on_alt_stack(a)) + drd_start_using_mem_stack(a, len); +} + +static +void drd_stop_using_mem_alt_stack(const Addr a, const SizeT len) +{ + if (!on_alt_stack(a)) + drd_stop_using_mem_stack(a, len); +} + +/** + * Callback function invoked by the Valgrind core before a signal is delivered. + */ +static +void drd_pre_deliver_signal(const ThreadId vg_tid, const Int sigNo, + const Bool alt_stack) +{ + DrdThreadId drd_tid; + + drd_tid = DRD_(VgThreadIdToDrdThreadId)(vg_tid); + DRD_(thread_set_on_alt_stack)(drd_tid, alt_stack); + if (alt_stack) + { + /* + * As soon a signal handler has been invoked on the alternate stack, + * switch to stack memory handling functions that can handle the + * alternate stack. + */ + VG_(track_new_mem_stack)(drd_start_using_mem_alt_stack); + VG_(track_die_mem_stack)(drd_stop_using_mem_alt_stack); + } +} + +/** + * Callback function invoked by the Valgrind core after a signal is delivered, + * at least if the signal handler did not longjmp(). + */ +static +void drd_post_deliver_signal(const ThreadId vg_tid, const Int sigNo) +{ + DrdThreadId drd_tid; + + drd_tid = DRD_(VgThreadIdToDrdThreadId)(vg_tid); + DRD_(thread_set_on_alt_stack)(drd_tid, False); + if (DRD_(thread_get_threads_on_alt_stack)() == 0) + { + VG_(track_new_mem_stack)(drd_start_using_mem_stack); + VG_(track_die_mem_stack)(drd_stop_using_mem_stack); + } +} + /** * Callback function called by the Valgrind core before a stack area is * being used by a signal handler. @@ -445,7 +529,7 @@ static void drd_start_using_mem_stack_signal(const Addr a, const SizeT len, ThreadId tid) { DRD_(thread_set_vg_running_tid)(VG_(get_running_tid)()); - drd_start_using_mem(a, len); + drd_start_using_mem(a, len, True); } static void drd_stop_using_mem_stack_signal(Addr a, SizeT len) @@ -514,7 +598,7 @@ static void drd_thread_finished(ThreadId vg_tid) ? "" : " (which is a detached thread)"); } - if (DRD_(s_show_stack_usage)) + if (s_show_stack_usage) { const SizeT stack_size = DRD_(thread_get_stack_size)(drd_tid); const SizeT used_stack @@ -553,7 +637,7 @@ static void DRD_(post_clo_init)(void) VG_(printf)("\nWARNING: DRD has not yet been tested on this operating system.\n\n"); # endif - if (DRD_(s_var_info)) + if (s_var_info) { VG_(needs_var_info)(); } @@ -569,12 +653,12 @@ static void DRD_(fini)(Int exitcode) { // thread_print_all(); if (VG_(clo_verbosity) == 1 && !VG_(clo_xml)) { - VG_(message)(Vg_UserMsg, + VG_(message)(Vg_UserMsg, "For counts of detected and suppressed errors, " "rerun with: -v\n"); } - if (VG_(clo_stats) || DRD_(s_print_stats)) + if (VG_(clo_stats) || s_print_stats) { ULong pu = DRD_(thread_get_update_conflict_set_count)(); ULong pu_seg_cr = DRD_(thread_get_update_conflict_set_new_sg_count)(); @@ -635,7 +719,7 @@ void drd_pre_clo_init(void) VG_(details_name) ("drd"); VG_(details_version) (NULL); VG_(details_description) ("a thread error detector"); - VG_(details_copyright_author)("Copyright (C) 2006-2009, and GNU GPL'd," + VG_(details_copyright_author)("Copyright (C) 2006-2010, and GNU GPL'd," " by Bart Van Assche."); VG_(details_bug_reports_to) (VG_BUGS_TO); @@ -664,6 +748,8 @@ void drd_pre_clo_init(void) VG_(track_die_mem_munmap) (drd_stop_using_nonstack_mem); VG_(track_die_mem_stack) (drd_stop_using_mem_stack); VG_(track_die_mem_stack_signal) (drd_stop_using_mem_stack_signal); + VG_(track_pre_deliver_signal) (drd_pre_deliver_signal); + VG_(track_post_deliver_signal) (drd_post_deliver_signal); VG_(track_start_client_code) (drd_start_client_code); VG_(track_pre_thread_ll_create) (drd_pre_thread_create); VG_(track_pre_thread_first_insn)(drd_post_thread_create); diff --git a/drd/drd_malloc_wrappers.c b/drd/drd_malloc_wrappers.c index d380ecc..6eeffdb 100644 --- a/drd/drd_malloc_wrappers.c +++ b/drd/drd_malloc_wrappers.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -225,7 +225,7 @@ static void* drd_realloc(ThreadId tid, void* p_old, SizeT new_size) { /* Copy from old to new. */ VG_(memcpy)(p_new, p_old, mc->size); - + /* Free old memory. */ VG_(cli_free)(p_old); if (mc->size > 0) @@ -243,7 +243,7 @@ static void* drd_realloc(ThreadId tid, void* p_old, SizeT new_size) { /* Allocation failed -- leave original block untouched. */ } - } + } return p_new; } @@ -346,7 +346,7 @@ void DRD_(print_malloc_stats)(void) DRD_Chunk* mc; SizeT nblocks = 0; SizeT nbytes = 0; - + if (VG_(clo_verbosity) == 0) return; if (VG_(clo_xml)) @@ -360,10 +360,10 @@ void DRD_(print_malloc_stats)(void) nbytes += mc->size; } - VG_(message)(Vg_DebugMsg, + VG_(message)(Vg_DebugMsg, "malloc/free: in use at exit: %lu bytes in %lu blocks.\n", nbytes, nblocks); - VG_(message)(Vg_DebugMsg, + VG_(message)(Vg_DebugMsg, "malloc/free: %lu allocs, %lu frees, %lu bytes allocated.\n", s_cmalloc_n_mallocs, s_cmalloc_n_frees, s_cmalloc_bs_mallocd); diff --git a/drd/drd_malloc_wrappers.h b/drd/drd_malloc_wrappers.h index eecbe58..2f9c2ce 100644 --- a/drd/drd_malloc_wrappers.h +++ b/drd/drd_malloc_wrappers.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/drd_mutex.c b/drd/drd_mutex.c index 65cf046..87494f8 100644 --- a/drd/drd_mutex.c +++ b/drd/drd_mutex.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -114,7 +114,7 @@ static void mutex_cleanup(struct mutex_info* p) p->last_locked_segment = 0; } -/** Let Valgrind report that there is no mutex object at address 'mutex'. */ +/** Report that address 'mutex' is not the address of a mutex object. */ void DRD_(not_a_mutex)(const Addr mutex) { MutexErrInfo MEI = { DRD_(thread_get_running_tid)(), @@ -126,6 +126,21 @@ void DRD_(not_a_mutex)(const Addr mutex) &MEI); } +/** + * Report that address 'mutex' is not the address of a mutex object of the + * expected type. + */ +static void wrong_mutex_type(const Addr mutex) +{ + MutexErrInfo MEI = { DRD_(thread_get_running_tid)(), + mutex, -1, DRD_INVALID_THREADID }; + VG_(maybe_record_error)(VG_(get_running_tid)(), + MutexErr, + VG_(get_IP)(VG_(get_running_tid)()), + "Mutex type mismatch", + &MEI); +} + static struct mutex_info* DRD_(mutex_get_or_allocate)(const Addr mutex, const MutexT mutex_type) @@ -136,7 +151,13 @@ DRD_(mutex_get_or_allocate)(const Addr mutex, const MutexT mutex_type) p = &(DRD_(clientobj_get)(mutex, ClientMutex)->mutex); if (p) { - return p; + if (mutex_type == mutex_type_unknown || p->mutex_type == mutex_type) + return p; + else + { + wrong_mutex_type(mutex); + return 0; + } } if (DRD_(clientobj_present)(mutex, mutex + 1)) @@ -211,10 +232,11 @@ void DRD_(mutex_post_destroy)(const Addr mutex) DRD_(clientobj_remove)(mutex, ClientMutex); } -/** Called before pthread_mutex_lock() is invoked. If a data structure for - * the client-side object was not yet created, do this now. Also check whether - * an attempt is made to lock recursively a synchronization object that must - * not be locked recursively. +/** + * Called before pthread_mutex_lock() is invoked. If a data structure for the + * client-side object was not yet created, do this now. Also check whether an + * attempt is made to lock recursively a synchronization object that must not + * be locked recursively. */ void DRD_(mutex_pre_lock)(const Addr mutex, MutexT mutex_type, const Bool trylock) @@ -222,7 +244,7 @@ void DRD_(mutex_pre_lock)(const Addr mutex, MutexT mutex_type, struct mutex_info* p; p = DRD_(mutex_get_or_allocate)(mutex, mutex_type); - if (mutex_type == mutex_type_unknown) + if (p && mutex_type == mutex_type_unknown) mutex_type = p->mutex_type; if (s_trace_mutex) @@ -464,9 +486,8 @@ const char* DRD_(mutex_type_name)(const MutexT mt) return "mutex"; case mutex_type_spinlock: return "spinlock"; - default: - tl_assert(0); } + tl_assert(0); return "?"; } diff --git a/drd/drd_mutex.h b/drd/drd_mutex.h index 5096a8e..c619ff5 100644 --- a/drd/drd_mutex.h +++ b/drd/drd_mutex.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/drd_pthread_intercepts.c b/drd/drd_pthread_intercepts.c index 2193ed7..44da42d 100644 --- a/drd/drd_pthread_intercepts.c +++ b/drd/drd_pthread_intercepts.c @@ -7,7 +7,7 @@ /* This file is part of DRD, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -28,7 +28,7 @@ */ /* --------------------------------------------------------------------- - ALL THE CODE IN THIS FILE RUNS ON THE SIMULATED CPU. + ALL THE CODE IN THIS FILE RUNS ON THE SIMULATED CPU. These functions are not called directly - they're the targets of code redirection or load notifications (see pub_core_redir.h for info). @@ -51,6 +51,7 @@ #include /* assert() */ #include /* pthread_mutex_t */ #include /* sem_t */ +#include /* uintptr_t */ #include /* fprintf() */ #include /* malloc(), free() */ #include /* confstr() */ @@ -181,6 +182,8 @@ static MutexT DRD_(pthread_to_drd_mutex_type)(const int kind) } } +#define IS_ALIGNED(p) (((uintptr_t)(p) & (sizeof(*(p)) - 1)) == 0) + /** * Read the mutex type stored in the client memory used for the mutex * implementation. @@ -198,19 +201,25 @@ static __always_inline MutexT DRD_(mutex_type)(pthread_mutex_t* mutex) { #if defined(HAVE_PTHREAD_MUTEX_T__M_KIND) /* glibc + LinuxThreads. */ - const int kind = mutex->__m_kind & 3; - return DRD_(pthread_to_drd_mutex_type)(kind); + if (IS_ALIGNED(&mutex->__m_kind)) + { + const int kind = mutex->__m_kind & 3; + return DRD_(pthread_to_drd_mutex_type)(kind); + } #elif defined(HAVE_PTHREAD_MUTEX_T__DATA__KIND) /* glibc + NPTL. */ - const int kind = mutex->__data.__kind & 3; - return DRD_(pthread_to_drd_mutex_type)(kind); + if (IS_ALIGNED(&mutex->__data.__kind)) + { + const int kind = mutex->__data.__kind & 3; + return DRD_(pthread_to_drd_mutex_type)(kind); + } #else /* * Another POSIX threads implementation. The mutex type won't be printed * when enabling --trace-mutex=yes. */ - return mutex_type_unknown; #endif + return mutex_type_unknown; } /** @@ -339,10 +348,8 @@ static void DRD_(set_main_thread_state)(void) // Make sure that DRD knows about the main thread's POSIX thread ID. VALGRIND_DO_CLIENT_REQUEST(res, -1, VG_USERREQ__SET_PTHREADID, pthread_self(), 0, 0, 0, 0); - } - /* * Note: as of today there exist three different versions of pthread_create * in Linux: diff --git a/drd/drd_qtcore_intercepts.c b/drd/drd_qtcore_intercepts.c index cddfef9..5a6a5ed 100644 --- a/drd/drd_qtcore_intercepts.c +++ b/drd/drd_qtcore_intercepts.c @@ -7,7 +7,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -28,7 +28,7 @@ */ /* --------------------------------------------------------------------- - ALL THE CODE IN THIS FILE RUNS ON THE SIMULATED CPU. + ALL THE CODE IN THIS FILE RUNS ON THE SIMULATED CPU. These functions are not called directly - they're the targets of code redirection or load notifications (see pub_core_redir.h for info). diff --git a/drd/drd_rwlock.c b/drd/drd_rwlock.c index a6edfdd..ad2968e 100644 --- a/drd/drd_rwlock.c +++ b/drd/drd_rwlock.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -294,7 +294,10 @@ DRD_(rwlock_get_or_allocate)(const Addr rwlock, const RwLockT rwlock_type) if (DRD_(clientobj_present)(rwlock, rwlock + 1)) { - GenericErrInfo GEI = { DRD_(thread_get_running_tid)() }; + GenericErrInfo GEI = { + .tid = DRD_(thread_get_running_tid)(), + .addr = rwlock, + }; VG_(maybe_record_error)(VG_(get_running_tid)(), GenericErr, VG_(get_IP)(VG_(get_running_tid)()), @@ -358,7 +361,10 @@ void DRD_(rwlock_post_destroy)(const Addr rwlock, const RwLockT rwlock_type) p = DRD_(rwlock_get)(rwlock); if (p == 0) { - GenericErrInfo GEI = { DRD_(thread_get_running_tid)() }; + GenericErrInfo GEI = { + .tid = DRD_(thread_get_running_tid)(), + .addr = rwlock, + }; VG_(maybe_record_error)(VG_(get_running_tid)(), GenericErr, VG_(get_IP)(VG_(get_running_tid)()), @@ -542,7 +548,10 @@ void DRD_(rwlock_pre_unlock)(const Addr rwlock, const RwLockT rwlock_type) p = DRD_(rwlock_get)(rwlock); if (p == 0) { - GenericErrInfo GEI = { DRD_(thread_get_running_tid)() }; + GenericErrInfo GEI = { + .tid = DRD_(thread_get_running_tid)(), + .addr = rwlock, + }; VG_(maybe_record_error)(VG_(get_running_tid)(), GenericErr, VG_(get_IP)(VG_(get_running_tid)()), diff --git a/drd/drd_rwlock.h b/drd/drd_rwlock.h index d30a6b5..855ad3d 100644 --- a/drd/drd_rwlock.h +++ b/drd/drd_rwlock.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/drd_segment.c b/drd/drd_segment.c index e2c0990..e4a0680 100644 --- a/drd/drd_segment.c +++ b/drd/drd_segment.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -91,7 +91,7 @@ static void sg_init(Segment* const sg, char* vc; vc = DRD_(vc_aprint)(&sg->vc); - VG_(message)(Vg_DebugMsg, "New segment for thread %d with vc %s", + VG_(message)(Vg_DebugMsg, "New segment for thread %d with vc %s\n", created, vc); VG_(free)(vc); } @@ -130,7 +130,7 @@ static void DRD_(sg_delete)(Segment* const sg) char* vc; vc = DRD_(vc_aprint)(&sg->vc); - VG_(message)(Vg_DebugMsg, "Discarding the segment with vector clock %s", + VG_(message)(Vg_DebugMsg, "Discarding the segment with vector clock %s\n", vc); VG_(free)(vc); } @@ -166,7 +166,7 @@ void DRD_(sg_put)(Segment* const sg) vc = DRD_(vc_aprint)(&sg->vc); VG_(message)(Vg_DebugMsg, - "Decrementing segment reference count %d -> %d with vc %s", + "Decrementing segment reference count %d -> %d with vc %s\n", sg->refcnt, sg->refcnt - 1, vc); VG_(free)(vc); } @@ -194,8 +194,8 @@ void DRD_(sg_merge)(Segment* const sg1, Segment* const sg2) vc1 = DRD_(vc_aprint)(&sg1->vc); vc2 = DRD_(vc_aprint)(&sg2->vc); - VG_(message)(Vg_DebugMsg, "Merging segments with vector clocks %s and %s", - vc1, vc2); + VG_(message)(Vg_DebugMsg, + "Merging segments with vector clocks %s and %s\n", vc1, vc2); VG_(free)(vc1); VG_(free)(vc2); } diff --git a/drd/drd_segment.h b/drd/drd_segment.h index 09f248c..b90e9f3 100644 --- a/drd/drd_segment.h +++ b/drd/drd_segment.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -28,7 +28,7 @@ /* - * Segments and segment lists. A segment represents information about + * Segments and segment lists. A segment represents information about * a contiguous group of statements of a specific thread. There is a vector * clock associated with each segment. */ diff --git a/drd/drd_semaphore.c b/drd/drd_semaphore.c index d7a9ebf..388b3b2 100644 --- a/drd/drd_semaphore.c +++ b/drd/drd_semaphore.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -202,7 +202,7 @@ struct semaphore_info* DRD_(semaphore_init)(const Addr semaphore, { #if defined(VGO_darwin) const ThreadId vg_tid = VG_(get_running_tid)(); - GenericErrInfo GEI = { DRD_(thread_get_running_tid)() }; + GenericErrInfo GEI = { DRD_(thread_get_running_tid)(), NULL }; VG_(maybe_record_error)(vg_tid, GenericErr, VG_(get_IP)(vg_tid), @@ -237,7 +237,10 @@ void DRD_(semaphore_destroy)(const Addr semaphore) if (p == 0) { - GenericErrInfo GEI = { DRD_(thread_get_running_tid)() }; + GenericErrInfo GEI = { + .tid = DRD_(thread_get_running_tid)(), + .addr = semaphore, + }; VG_(maybe_record_error)(VG_(get_running_tid)(), GenericErr, VG_(get_IP)(VG_(get_running_tid)()), @@ -314,7 +317,10 @@ void DRD_(semaphore_close)(const Addr semaphore) if (p == 0) { - GenericErrInfo GEI = { DRD_(thread_get_running_tid)() }; + GenericErrInfo GEI = { + .tid = DRD_(thread_get_running_tid)(), + .addr = semaphore, + }; VG_(maybe_record_error)(VG_(get_running_tid)(), GenericErr, VG_(get_IP)(VG_(get_running_tid)()), @@ -331,6 +337,7 @@ void DRD_(semaphore_pre_wait)(const Addr semaphore) { struct semaphore_info* p; + tl_assert(semaphore < semaphore + 1); p = drd_semaphore_get_or_allocate(semaphore); tl_assert(p); p->waiters++; @@ -445,12 +452,12 @@ void DRD_(semaphore_post_post)(const DrdThreadId tid, const Addr semaphore, const Bool succeeded) { /* - * Note: it is hard to implement the sem_post() wrapper correctly in - * case sem_post() returns an error code. This is because handling this - * case correctly requires restoring the vector clock associated with + * Note: it is hard to implement the sem_post() wrapper correctly in + * case sem_post() returns an error code. This is because handling this + * case correctly requires restoring the vector clock associated with * the semaphore to its original value here. In order to do that without - * introducing a race condition, extra locking has to be added around - * each semaphore call. Such extra locking would have to be added in + * introducing a race condition, extra locking has to be added around + * each semaphore call. Such extra locking would have to be added in * drd_pthread_intercepts.c. However, it is hard to implement * synchronization in drd_pthread_intercepts.c in a portable way without * calling already redirected functions. diff --git a/drd/drd_semaphore.h b/drd/drd_semaphore.h index 3f2b805..8b0b7f3 100644 --- a/drd/drd_semaphore.h +++ b/drd/drd_semaphore.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/drd_strmem_intercepts.c b/drd/drd_strmem_intercepts.c index 621cfa0..1a87f42 100644 --- a/drd/drd_strmem_intercepts.c +++ b/drd/drd_strmem_intercepts.c @@ -11,7 +11,7 @@ from memchec/mc_replace_strmem.c, which has the following copyright notice: - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -49,7 +49,7 @@ } STRNLEN(VG_Z_LIBC_SONAME, strnlen) - + // Note that this replacement often doesn't get used because gcc inlines // calls to strlen() with its own built-in version. This can be very diff --git a/drd/drd_suppression.c b/drd/drd_suppression.c index 8261ce0..eb4f44e 100644 --- a/drd/drd_suppression.c +++ b/drd/drd_suppression.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -39,6 +39,7 @@ Bool DRD_(g_any_address_traced) = False; /* Local variables. */ static struct bitmap* DRD_(s_suppressed); +static struct bitmap* DRD_(s_traced); static Bool DRD_(s_trace_suppression); @@ -52,8 +53,11 @@ void DRD_(suppression_set_trace)(const Bool trace_suppression) void DRD_(suppression_init)(void) { tl_assert(DRD_(s_suppressed) == 0); + tl_assert(DRD_(s_traced) == 0); DRD_(s_suppressed) = DRD_(bm_new)(); + DRD_(s_traced) = DRD_(bm_new)(); tl_assert(DRD_(s_suppressed)); + tl_assert(DRD_(s_traced)); } void DRD_(start_suppression)(const Addr a1, const Addr a2, @@ -65,8 +69,7 @@ void DRD_(start_suppression)(const Addr a1, const Addr a2, a1, a2 - a1, reason); } - tl_assert(a1 < a2); - // tl_assert(! drd_is_any_suppressed(a1, a2)); + tl_assert(a1 <= a2); DRD_(bm_access_range_store)(DRD_(s_suppressed), a1, a2); } @@ -76,18 +79,10 @@ void DRD_(finish_suppression)(const Addr a1, const Addr a2) { VG_(message)(Vg_DebugMsg, "finish suppression of 0x%lx sz %ld\n", a1, a2 - a1); - VG_(get_and_pp_StackTrace)(VG_(get_running_tid)(), 12); - } - - tl_assert(a1 < a2); -#if 0 - if (! DRD_(is_suppressed)(a1, a2)) - { - VG_(message)(Vg_DebugMsg, "?? [0x%lx,0x%lx[ not suppressed ??\n", a1, a2); VG_(get_and_pp_StackTrace)(VG_(get_running_tid)(), 12); - tl_assert(False); } -#endif + + tl_assert(a1 <= a2); DRD_(bm_clear_store)(DRD_(s_suppressed), a1, a2); } @@ -111,11 +106,21 @@ Bool DRD_(is_any_suppressed)(const Addr a1, const Addr a2) return DRD_(bm_has_any_store)(DRD_(s_suppressed), a1, a2); } +void DRD_(mark_hbvar)(const Addr a1) +{ + DRD_(bm_access_range_load)(DRD_(s_suppressed), a1, a1 + 1); +} + +Bool DRD_(range_contains_suppression_or_hbvar)(const Addr a1, const Addr a2) +{ + return DRD_(bm_has_any_access)(DRD_(s_suppressed), a1, a2); +} + void DRD_(start_tracing_address_range)(const Addr a1, const Addr a2) { - tl_assert(a1 < a2); + tl_assert(a1 <= a2); - DRD_(bm_access_range_load)(DRD_(s_suppressed), a1, a2); + DRD_(bm_access_range_load)(DRD_(s_traced), a1, a2); if (! DRD_(g_any_address_traced)) { DRD_(g_any_address_traced) = True; @@ -124,19 +129,19 @@ void DRD_(start_tracing_address_range)(const Addr a1, const Addr a2) void DRD_(stop_tracing_address_range)(const Addr a1, const Addr a2) { - tl_assert(a1 < a2); + tl_assert(a1 <= a2); - DRD_(bm_clear_load)(DRD_(s_suppressed), a1, a2); + DRD_(bm_clear_load)(DRD_(s_traced), a1, a2); if (DRD_(g_any_address_traced)) { DRD_(g_any_address_traced) - = DRD_(bm_has_any_load)(DRD_(s_suppressed), 0, ~(Addr)0); + = DRD_(bm_has_any_load)(DRD_(s_traced), 0, ~(Addr)0); } } Bool DRD_(is_any_traced)(const Addr a1, const Addr a2) { - return DRD_(bm_has_any_load)(DRD_(s_suppressed), a1, a2); + return DRD_(bm_has_any_load)(DRD_(s_traced), a1, a2); } void DRD_(suppression_stop_using_mem)(const Addr a1, const Addr a2) @@ -155,6 +160,7 @@ void DRD_(suppression_stop_using_mem)(const Addr a1, const Addr a2) } } tl_assert(a1); - tl_assert(a1 < a2); + tl_assert(a1 <= a2); DRD_(bm_clear)(DRD_(s_suppressed), a1, a2); + DRD_(bm_clear)(DRD_(s_traced), a1, a2); } diff --git a/drd/drd_suppression.h b/drd/drd_suppression.h index 9d93b94..40e0f4c 100644 --- a/drd/drd_suppression.h +++ b/drd/drd_suppression.h @@ -17,6 +17,8 @@ void DRD_(start_suppression)(const Addr a1, const Addr a2, void DRD_(finish_suppression)(const Addr a1, const Addr a2); Bool DRD_(is_suppressed)(const Addr a1, const Addr a2); Bool DRD_(is_any_suppressed)(const Addr a1, const Addr a2); +void DRD_(mark_hbvar)(const Addr a1); +Bool DRD_(range_contains_suppression_or_hbvar)(const Addr a1, const Addr a2); void DRD_(start_tracing_address_range)(const Addr a1, const Addr a2); void DRD_(stop_tracing_address_range)(const Addr a1, const Addr a2); Bool DRD_(is_any_traced)(const Addr a1, const Addr a2); diff --git a/drd/drd_thread.c b/drd/drd_thread.c index 2c759c1..909bb45 100644 --- a/drd/drd_thread.c +++ b/drd/drd_thread.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -181,6 +181,7 @@ static DrdThreadId DRD_(VgThreadIdToNewDrdThreadId)(const ThreadId tid) DRD_(g_threadinfo)[i].stack_startup = 0; DRD_(g_threadinfo)[i].stack_max = 0; DRD_(thread_set_name)(i, ""); + DRD_(g_threadinfo)[i].on_alt_stack = False; DRD_(g_threadinfo)[i].is_recording_loads = True; DRD_(g_threadinfo)[i].is_recording_stores = True; DRD_(g_threadinfo)[i].pthread_create_nesting_level = 0; @@ -420,8 +421,33 @@ SizeT DRD_(thread_get_stack_size)(const DrdThreadId tid) return DRD_(g_threadinfo)[tid].stack_size; } +Bool DRD_(thread_get_on_alt_stack)(const DrdThreadId tid) +{ + tl_assert(0 <= (int)tid && tid < DRD_N_THREADS + && tid != DRD_INVALID_THREADID); + return DRD_(g_threadinfo)[tid].on_alt_stack; +} + +void DRD_(thread_set_on_alt_stack)(const DrdThreadId tid, + const Bool on_alt_stack) +{ + tl_assert(0 <= (int)tid && tid < DRD_N_THREADS + && tid != DRD_INVALID_THREADID); + tl_assert(on_alt_stack == !!on_alt_stack); + DRD_(g_threadinfo)[tid].on_alt_stack = on_alt_stack; +} + +Int DRD_(thread_get_threads_on_alt_stack)(void) +{ + int i, n = 0; + + for (i = 1; i < DRD_N_THREADS; i++) + n += DRD_(g_threadinfo)[i].on_alt_stack; + return n; +} + /** - * Clean up thread-specific data structures. Call this just after + * Clean up thread-specific data structures. Call this just after * pthread_join(). */ void DRD_(thread_delete)(const DrdThreadId tid) @@ -561,7 +587,7 @@ void DRD_(thread_set_name)(const DrdThreadId tid, const char* const name) { tl_assert(0 <= (int)tid && tid < DRD_N_THREADS && tid != DRD_INVALID_THREADID); - + if (name == NULL || name[0] == 0) VG_(snprintf)(DRD_(g_threadinfo)[tid].name, sizeof(DRD_(g_threadinfo)[tid].name), @@ -602,7 +628,7 @@ void DRD_(thread_set_running_tid)(const ThreadId vg_tid, { tl_assert(vg_tid != VG_INVALID_THREADID); tl_assert(drd_tid != DRD_INVALID_THREADID); - + if (vg_tid != s_vg_running_tid) { if (s_trace_context_switches @@ -1104,7 +1130,8 @@ void DRD_(thread_new_segment_and_combine_vc)(DrdThreadId tid, const Segment* sg) * [ a1, a2 [, e.g. because of a call to free() or a stack pointer * increase. */ -void DRD_(thread_stop_using_mem)(const Addr a1, const Addr a2) +void DRD_(thread_stop_using_mem)(const Addr a1, const Addr a2, + const Bool dont_clear_access) { DrdThreadId other_user; unsigned i; @@ -1119,13 +1146,18 @@ void DRD_(thread_stop_using_mem)(const Addr a1, const Addr a2) if (other_user == DRD_INVALID_THREADID && i != DRD_(g_drd_running_tid)) { - if (UNLIKELY(DRD_(bm_test_and_clear)(DRD_(sg_bm)(p), a1, a2))) + if (UNLIKELY((!dont_clear_access + && DRD_(bm_test_and_clear)(DRD_(sg_bm)(p), a1, a2)) + || (dont_clear_access + && DRD_(bm_has_any_access)(DRD_(sg_bm)(p), a1, a2)) + )) { other_user = i; } continue; } - DRD_(bm_clear)(DRD_(sg_bm)(p), a1, a2); + if (!dont_clear_access) + DRD_(bm_clear)(DRD_(sg_bm)(p), a1, a2); } } @@ -1241,8 +1273,8 @@ thread_report_conflicting_segments_segment(const DrdThreadId tid, for (q = DRD_(g_threadinfo)[i].last; q; q = q->prev) { /* - * Since q iterates over the segments of thread i in order of - * decreasing vector clocks, if q->vc <= p->vc, then + * Since q iterates over the segments of thread i in order of + * decreasing vector clocks, if q->vc <= p->vc, then * q->next->vc <= p->vc will also hold. Hence, break out of the * loop once this condition is met. */ diff --git a/drd/drd_thread.h b/drd/drd_thread.h index ea352b9..cb4853b 100644 --- a/drd/drd_thread.h +++ b/drd/drd_thread.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -77,6 +77,7 @@ typedef struct Addr stack_max; /**< Top of stack. */ SizeT stack_size; /**< Maximum size of stack. */ char name[64]; /**< User-assigned thread name. */ + Bool on_alt_stack; /** Indicates whether the Valgrind core knows about this thread. */ Bool vg_thread_exists; /** Indicates whether there is an associated POSIX thread ID. */ @@ -142,6 +143,10 @@ Addr DRD_(thread_get_stack_min)(const DrdThreadId tid); Addr DRD_(thread_get_stack_min_min)(const DrdThreadId tid); Addr DRD_(thread_get_stack_max)(const DrdThreadId tid); SizeT DRD_(thread_get_stack_size)(const DrdThreadId tid); +Bool DRD_(thread_get_on_alt_stack)(const DrdThreadId tid); +void DRD_(thread_set_on_alt_stack)(const DrdThreadId tid, + const Bool on_alt_stack); +Int DRD_(thread_get_threads_on_alt_stack)(void); void DRD_(thread_set_pthreadid)(const DrdThreadId tid, const PThreadId ptid); Bool DRD_(thread_get_joinable)(const DrdThreadId tid); void DRD_(thread_set_joinable)(const DrdThreadId tid, const Bool joinable); @@ -165,7 +170,8 @@ void DRD_(thread_new_segment_and_combine_vc)(DrdThreadId tid, void DRD_(thread_update_conflict_set)(const DrdThreadId tid, const VectorClock* const old_vc); -void DRD_(thread_stop_using_mem)(const Addr a1, const Addr a2); +void DRD_(thread_stop_using_mem)(const Addr a1, const Addr a2, + const Bool dont_clear_access); void DRD_(thread_set_record_loads)(const DrdThreadId tid, const Bool enabled); void DRD_(thread_set_record_stores)(const DrdThreadId tid, const Bool enabled); void DRD_(thread_print_all)(void); @@ -238,7 +244,7 @@ Bool DRD_(running_thread_inside_pthread_create)(void) } /** - * Reports whether or not recording of memory loads is enabled for the + * Reports whether or not recording of memory loads is enabled for the * currently running client thread. */ static __inline__ @@ -254,7 +260,7 @@ Bool DRD_(running_thread_is_recording_loads)(void) } /** - * Reports whether or not recording memory stores is enabled for the + * Reports whether or not recording memory stores is enabled for the * currently running client thread. */ static __inline__ diff --git a/drd/drd_thread_bitmap.h b/drd/drd_thread_bitmap.h index c795df4..596a773 100644 --- a/drd/drd_thread_bitmap.h +++ b/drd/drd_thread_bitmap.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/drd_vc.c b/drd/drd_vc.c index b1f3c66..d90d66f 100644 --- a/drd/drd_vc.c +++ b/drd/drd_vc.c @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/drd_vc.h b/drd/drd_vc.h index a598514..a7d67d0 100644 --- a/drd/drd_vc.h +++ b/drd/drd_vc.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -39,7 +39,7 @@ * - Vector clocks are compared by comparing all counters of all threads. * - When a thread synchronization action is performed that guarantees that * new actions of the current thread are executed after the actions of the - * other thread, the vector clock of the synchronization object and the + * other thread, the vector clock of the synchronization object and the * current thread are combined (by taking the component-wise maximum). * - A vector clock is incremented during actions such as * pthread_create(), pthread_mutex_unlock(), sem_post(). (Actions where @@ -108,14 +108,14 @@ Bool DRD_(vc_lte)(const VectorClock* const vc1, const VectorClock* const vc2) for (i = 0; i < vc1->size; i++) { while (j < vc2->size && vc2->vc[j].threadid < vc1->vc[i].threadid) - { j++; - } if (j >= vc2->size || vc2->vc[j].threadid > vc1->vc[i].threadid) return False; #ifdef ENABLE_DRD_CONSISTENCY_CHECKS - /* This assert statement has been commented out because of performance */ - /* reasons.*/ + /* + * This assert statement has been commented out because of performance + * reasons. + */ tl_assert(j < vc2->size && vc2->vc[j].threadid == vc1->vc[i].threadid); #endif if (vc1->vc[i].count > vc2->vc[j].count) diff --git a/drd/pub_drd_bitmap.h b/drd/pub_drd_bitmap.h index 360b38c..761a049 100644 --- a/drd/pub_drd_bitmap.h +++ b/drd/pub_drd_bitmap.h @@ -2,7 +2,7 @@ /* This file is part of drd, a thread error detector. - Copyright (C) 2006-2009 Bart Van Assche . + Copyright (C) 2006-2010 Bart Van Assche . This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as diff --git a/drd/scripts/download-and-build-firefox b/drd/scripts/download-and-build-firefox old mode 100644 new mode 100755 diff --git a/drd/scripts/download-and-build-gcc b/drd/scripts/download-and-build-gcc old mode 100644 new mode 100755 index 85989f0..8b8cd4d --- a/drd/scripts/download-and-build-gcc +++ b/drd/scripts/download-and-build-gcc @@ -6,7 +6,7 @@ # are called gmp-devel and mpfr-devel. -GCC_VERSION=4.4.1 +GCC_VERSION=4.5.0 FSF_MIRROR=ftp://ftp.easynet.be/gnu SRCDIR=$HOME/software DOWNLOADS=$SRCDIR/downloads @@ -14,19 +14,30 @@ SRC=$HOME/software/gcc-${GCC_VERSION} BUILD=${SRC}-build TAR=gcc-${GCC_VERSION}.tar.bz2 PREFIX=$HOME/gcc-${GCC_VERSION} +GMP_PREFIX=/usr +#GMP_PREFIX=$HOME/gmp-5.0.1 +MPFR_PREFIX=/usr +#MPFR_PREFIX=$HOME/mpfr-2.4.2 +MPC_PREFIX=/usr +#MPC_PREFIX=$HOME/mpc-0.8.1 export LC_ALL=C export MAKEFLAGS="-j$(($(grep -c '^processor' /proc/cpuinfo) + 1))" -if [ ! -e /usr/include/gmp.h ]; then +if [ ! -e $GMP_PREFIX/include/gmp.h ]; then echo "Please install the gmp library development package first." exit 1 fi -if [ ! -e /usr/include/mpfr.h ]; then +if [ ! -e $MPFR_PREFIX/include/mpfr.h ]; then echo "Please install the mpfr library development package first." exit 1 fi +if [ ! -e $MPC_PREFIX/include/mpc.h ]; then + echo "Please install the mpc library development package first." + exit 1 +fi + rm -rf ${BUILD} || exit $? rm -rf ${PREFIX} || exit $? mkdir -p ${DOWNLOADS} || exit $? @@ -54,6 +65,9 @@ ${SRC}/configure \ --enable-languages=c,c++ \ --enable-threads=posix \ --enable-tls \ - --prefix=$PREFIX + --prefix=$PREFIX \ + --with-gmp=$GMP_PREFIX \ + --with-mpfr=$MPFR_PREFIX \ + --with-mpc=$MPC_PREFIX time { make -s && make -s install; } diff --git a/drd/scripts/download-and-build-splash2.in b/drd/scripts/download-and-build-splash2.in old mode 100644 new mode 100755 diff --git a/drd/scripts/ppc-cross/crosstool-patches/powerpc-kernel-compilation.patch b/drd/scripts/ppc-cross/crosstool-patches/powerpc-kernel-compilation.patch new file mode 100644 index 0000000..0e0d1df --- /dev/null +++ b/drd/scripts/ppc-cross/crosstool-patches/powerpc-kernel-compilation.patch @@ -0,0 +1,13 @@ +--- orig/crosstool-0.43/crosstool.sh 2006-12-07 01:17:40.000000000 +0100 ++++ crosstool-0.43/crosstool.sh 2009-08-29 09:46:10.000000000 +0200 +@@ -226,8 +226,8 @@ + ia64*) ARCH=ia64 ;; + mips*) ARCH=mips ;; + m68k*) ARCH=m68k ;; +- powerpc64*) ARCH=ppc64 ;; +- powerpc*) ARCH=ppc ;; ++ powerpc64*) ARCH=powerpc ;; ++ powerpc*) ARCH=powerpc ;; + ppc*) abort "Target $TARGET incompatible with binutils and gcc regression tests; use target powerpc-* or powerpc64-* instead";; + s390*) ARCH=s390 ;; + sh*) ARCH=sh ;; diff --git a/drd/scripts/ppc-cross/download-and-build-ppc-crosscompiler b/drd/scripts/ppc-cross/download-and-build-ppc-crosscompiler new file mode 100755 index 0000000..8b132bb --- /dev/null +++ b/drd/scripts/ppc-cross/download-and-build-ppc-crosscompiler @@ -0,0 +1,167 @@ +#!/bin/bash + +############################################################################ +# +# Script for generating a PowerPC cross compiler using crosstool. +# +# Copyright (C) 2009 Bart Van Assche . +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation, version 2 +# of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +############################################################################ + +######################### +# Function definitions # +######################### + +# Print an error message and exit. +abort() { + echo "build failed: $@" + exit 1 +} + +# Print command-line help. +usage() { + cat < kernelspace linker +# +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=m +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=m +CONFIG_MTD_PCI=m +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +# CONFIG_MTD_PMC551_BUGFIX is not set +# CONFIG_MTD_PMC551_DEBUG is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=m +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +CONFIG_MTD_NAND_ECC_SMC=y +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=m +CONFIG_MTD_NAND_DISKONCHIP=m +# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 +# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set +# CONFIG_MTD_NAND_CAFE is not set +CONFIG_MTD_NAND_NANDSIM=m +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set + +# +# Parallel port support +# +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_SERIAL=m +# CONFIG_PARPORT_PC_FIFO is not set +# CONFIG_PARPORT_PC_SUPERIO is not set +CONFIG_PARPORT_PC_PCMCIA=m +# CONFIG_PARPORT_GSC is not set +# CONFIG_PARPORT_AX88796 is not set +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +CONFIG_BLK_DEV_FD=m +CONFIG_PARIDE=m + +# +# Parallel IDE high-level drivers +# +CONFIG_PARIDE_PD=m +CONFIG_PARIDE_PCD=m +CONFIG_PARIDE_PF=m +CONFIG_PARIDE_PT=m +CONFIG_PARIDE_PG=m + +# +# Parallel IDE protocol modules +# +CONFIG_PARIDE_ATEN=m +CONFIG_PARIDE_BPCK=m +CONFIG_PARIDE_COMM=m +CONFIG_PARIDE_DSTR=m +CONFIG_PARIDE_FIT2=m +CONFIG_PARIDE_FIT3=m +CONFIG_PARIDE_EPAT=m +CONFIG_PARIDE_EPATC8=y +CONFIG_PARIDE_EPIA=m +CONFIG_PARIDE_FRIQ=m +CONFIG_PARIDE_FRPW=m +CONFIG_PARIDE_KBIC=m +CONFIG_PARIDE_KTTI=m +CONFIG_PARIDE_ON20=m +CONFIG_PARIDE_ON26=m +# CONFIG_BLK_CPQ_DA is not set +CONFIG_BLK_CPQ_CISS_DA=m +CONFIG_CISS_SCSI_TAPE=y +CONFIG_BLK_DEV_DAC960=m +CONFIG_BLK_DEV_UMEM=m +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_SX8=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=4096 +CONFIG_BLK_DEV_SYSTEMSIM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_ATA_OVER_ETH=m + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +CONFIG_EEPROM_93CX6=m +# CONFIG_SGI_IOC4 is not set +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_BLK_DEV_IDECS is not set +CONFIG_BLK_DEV_DELKIN=m +CONFIG_BLK_DEV_IDECD=m +# CONFIG_BLK_DEV_IDETAPE is not set +CONFIG_BLK_DEV_IDEFLOPPY=m +# CONFIG_BLK_DEV_IDESCSI is not set +CONFIG_IDE_TASK_IOCTL=y +# CONFIG_IDE_PROC_FS is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_ONLYDISK is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SL82C105 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_BLK_DEV_CELLEB is not set +CONFIG_BLK_DEV_IDE_PMAC=y +CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y +CONFIG_BLK_DEV_IDEDMA_PMAC=y +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=m +CONFIG_SCSI_TGT=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set + +# +# SCSI low-level drivers +# +CONFIG_ISCSI_TCP=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=4 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set +CONFIG_SCSI_AIC7XXX_OLD=m +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=4 +CONFIG_AIC79XX_RESET_DELAY_MS=15000 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_ARCMSR=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_HPTIOP=m +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +CONFIG_SCSI_GDTH=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_IBMVSCSI=m +CONFIG_SCSI_IBMVSCSIS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_PPA=m +CONFIG_SCSI_IMM=m +# CONFIG_SCSI_IZIP_EPP16 is not set +# CONFIG_SCSI_IZIP_SLOW_CTR is not set +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_LPFC=m +CONFIG_SCSI_DC395x=m +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_DEBUG is not set +CONFIG_SCSI_SRP=m + +# +# PCMCIA SCSI adapter support +# +# CONFIG_PCMCIA_FDOMAIN is not set +CONFIG_PCMCIA_QLOGIC=m +CONFIG_PCMCIA_SYM53C500=m +CONFIG_ATA=m +CONFIG_ATA_NONSTANDARD=y +CONFIG_SATA_AHCI=m +CONFIG_SATA_SVW=m +CONFIG_ATA_PIIX=m +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SX4=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIL24=m +CONFIG_SATA_SIS=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +CONFIG_SATA_INIC162X=m +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CS5520=m +CONFIG_PATA_CS5530=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_ATA_GENERIC=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_IT8213=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PCMCIA=m +CONFIG_PATA_PDC_OLD=m +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +# CONFIG_PATA_SCC is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_RAID5_RESHAPE=y +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_DEBUG=y +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=40 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m + +# +# IEEE 1394 (FireWire) support +# +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +CONFIG_MACINTOSH_DRIVERS=y +CONFIG_ADB_PMU=y +CONFIG_ADB_PMU_LED=y +CONFIG_ADB_PMU_LED_IDE=y +CONFIG_PMAC_SMU=y +CONFIG_MAC_EMUMOUSEBTN=y +CONFIG_THERM_PM72=y +CONFIG_WINDFARM=y +CONFIG_WINDFARM_PM81=y +CONFIG_WINDFARM_PM91=y +CONFIG_WINDFARM_PM112=y +CONFIG_PMAC_RACKMETER=m +CONFIG_NETDEVICES=y +CONFIG_IFB=m +CONFIG_DUMMY=m +CONFIG_BONDING=m +CONFIG_EQUALIZER=m +CONFIG_TUN=m +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=m + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_SMSC_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_FIXED_PHY=m +CONFIG_FIXED_MII_10_FDX=y +CONFIG_FIXED_MII_100_FDX=y +CONFIG_NET_ETHERNET=y +CONFIG_MII=m +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +CONFIG_TULIP_MMIO=y +# CONFIG_TULIP_NAPI is not set +CONFIG_DE4X5=m +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +# CONFIG_HP100 is not set +CONFIG_IBMVETH=m +CONFIG_SYSTEMSIM_NET=m +CONFIG_NET_PCI=y +CONFIG_PCNET32=m +CONFIG_PCNET32_NAPI=y +CONFIG_AMD8111_ETH=m +CONFIG_AMD8111E_NAPI=y +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_ADAPTEC_STARFIRE_NAPI=y +CONFIG_B44=m +CONFIG_FORCEDETH=m +CONFIG_FORCEDETH_NAPI=y +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=m +CONFIG_FEALNX=m +CONFIG_NATSEMI=m +CONFIG_NE2K_PCI=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_SIS900=m +CONFIG_EPIC100=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_RHINE_NAPI=y +CONFIG_SC92031=m +CONFIG_NET_POCKET=y +CONFIG_DE600=m +CONFIG_DE620=m +CONFIG_NETDEV_1000=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +CONFIG_DL2K=m +CONFIG_E1000=m +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +CONFIG_NS83820=m +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_R8169=m +CONFIG_R8169_NAPI=y +CONFIG_R8169_VLAN=y +CONFIG_SIS190=m +CONFIG_SKGE=m +CONFIG_SKY2=m +# CONFIG_SK98LIN is not set +CONFIG_VIA_VELOCITY=m +CONFIG_TIGON3=m +CONFIG_BNX2=m +CONFIG_SPIDER_NET=m +CONFIG_GELIC_NET=m +CONFIG_GELIC_WIRELESS=y +CONFIG_QLA3XXX=m +CONFIG_ATL1=m +CONFIG_NETDEV_10000=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T1_NAPI=y +CONFIG_CHELSIO_T3=m +CONFIG_EHEA=m +CONFIG_IXGB=m +CONFIG_IXGB_NAPI=y +CONFIG_S2IO=m +CONFIG_S2IO_NAPI=y +CONFIG_MYRI10GE=m +CONFIG_NETXEN_NIC=m +# CONFIG_PASEMI_MAC is not set +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_TR=y +CONFIG_IBMOL=m +CONFIG_3C359=m +# CONFIG_TMS380TR is not set + +# +# Wireless LAN +# +CONFIG_WLAN_PRE80211=y +# CONFIG_STRIP is not set +CONFIG_PCMCIA_WAVELAN=m +CONFIG_PCMCIA_NETWAVE=m +CONFIG_WLAN_80211=y +# CONFIG_PCMCIA_RAYCS is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_LIBERTAS is not set +CONFIG_AIRO=m +CONFIG_HERMES=m +CONFIG_APPLE_AIRPORT=m +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_PCMCIA_HERMES=m +CONFIG_PCMCIA_SPECTRUM=m +CONFIG_AIRO_CS=m +CONFIG_PCMCIA_ATMEL=m +CONFIG_PCMCIA_WL3501=m +CONFIG_PRISM54=m +CONFIG_USB_ZD1201=m +CONFIG_RTL8187=m +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HOSTAP_CS=m +CONFIG_BCM43XX=m +CONFIG_BCM43XX_DEBUG=y +CONFIG_BCM43XX_DMA=y +CONFIG_BCM43XX_PIO=y +CONFIG_BCM43XX_DMA_AND_PIO_MODE=y +# CONFIG_BCM43XX_DMA_MODE is not set +# CONFIG_BCM43XX_PIO_MODE is not set +# CONFIG_ZD1211RW is not set + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET_MII=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=m +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_PCMCIA_PCNET=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_PCMCIA_SMC91C92=m +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_PCMCIA_AXNET=m +# CONFIG_WAN is not set +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +# CONFIG_ATM_FIRESTREAM is not set +# CONFIG_ATM_ZATM is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +# CONFIG_ATM_AMBASSADOR is not set +# CONFIG_ATM_HORIZON is not set +CONFIG_ATM_FORE200E_MAYBE=m +# CONFIG_ATM_FORE200E_PCA is not set +CONFIG_ATM_HE=m +# CONFIG_ATM_HE_USE_SUNI is not set +CONFIG_ISERIES_VETH=m +CONFIG_FDDI=y +# CONFIG_DEFXX is not set +CONFIG_SKFP=m +# CONFIG_HIPPI is not set +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOATM=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_NET_FC=y +# CONFIG_SHAPER is not set +CONFIG_NETCONSOLE=m +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y + +# +# ISDN subsystem +# +CONFIG_ISDN=m + +# +# Old ISDN4Linux +# +CONFIG_ISDN_I4L=m +CONFIG_ISDN_PPP=y +CONFIG_ISDN_PPP_VJ=y +CONFIG_ISDN_MPP=y +CONFIG_IPPP_FILTER=y +# CONFIG_ISDN_PPP_BSDCOMP is not set +CONFIG_ISDN_AUDIO=y +CONFIG_ISDN_TTY_FAX=y + +# +# ISDN feature submodules +# +CONFIG_ISDN_DIVERSION=m + +# +# ISDN4Linux hardware drivers +# + +# +# Passive cards +# +CONFIG_ISDN_DRV_HISAX=m + +# +# D-channel protocol features +# +CONFIG_HISAX_EURO=y +CONFIG_DE_AOC=y +CONFIG_HISAX_NO_SENDCOMPLETE=y +CONFIG_HISAX_NO_LLC=y +CONFIG_HISAX_NO_KEYPAD=y +CONFIG_HISAX_1TR6=y +CONFIG_HISAX_NI1=y +CONFIG_HISAX_MAX_CARDS=8 + +# +# HiSax supported cards +# +CONFIG_HISAX_16_3=y +CONFIG_HISAX_S0BOX=y +CONFIG_HISAX_AVM_A1_PCMCIA=y +CONFIG_HISAX_ELSA=y +CONFIG_HISAX_DIEHLDIVA=y +CONFIG_HISAX_SEDLBAUER=y +CONFIG_HISAX_NICCY=y +CONFIG_HISAX_BKM_A4T=y +CONFIG_HISAX_SCT_QUADRO=y +CONFIG_HISAX_GAZEL=y +CONFIG_HISAX_W6692=y +CONFIG_HISAX_HFC_SX=y +# CONFIG_HISAX_DEBUG is not set + +# +# HiSax PCMCIA card service modules +# +CONFIG_HISAX_SEDLBAUER_CS=m +CONFIG_HISAX_ELSA_CS=m +CONFIG_HISAX_AVM_A1_CS=m +CONFIG_HISAX_TELES_CS=m + +# +# HiSax sub driver modules +# +CONFIG_HISAX_ST5481=m +# CONFIG_HISAX_HFCUSB is not set +CONFIG_HISAX_HFC4S8S=m +CONFIG_HISAX_FRITZ_PCIPNP=m +CONFIG_HISAX_HDLC=y + +# +# Active cards +# + +# +# Siemens Gigaset +# +CONFIG_ISDN_DRV_GIGASET=m +CONFIG_GIGASET_BASE=m +CONFIG_GIGASET_M105=m +CONFIG_GIGASET_M101=m +# CONFIG_GIGASET_DEBUG is not set +# CONFIG_GIGASET_UNDOCREQ is not set + +# +# CAPI subsystem +# +CONFIG_ISDN_CAPI=m +CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y +# CONFIG_CAPI_TRACE is not set +CONFIG_ISDN_CAPI_MIDDLEWARE=y +CONFIG_ISDN_CAPI_CAPI20=m +CONFIG_ISDN_CAPI_CAPIFS_BOOL=y +CONFIG_ISDN_CAPI_CAPIFS=m +CONFIG_ISDN_CAPI_CAPIDRV=m + +# +# CAPI hardware drivers +# + +# +# Active AVM cards +# +CONFIG_CAPI_AVM=y +CONFIG_ISDN_DRV_AVMB1_B1PCI=m +CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y +CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m +CONFIG_ISDN_DRV_AVMB1_AVM_CS=m +CONFIG_ISDN_DRV_AVMB1_T1PCI=m +CONFIG_ISDN_DRV_AVMB1_C4=m + +# +# Active Eicon DIVA Server cards +# +CONFIG_CAPI_EICON=y +CONFIG_ISDN_DIVAS=m +CONFIG_ISDN_DIVAS_BRIPCI=y +CONFIG_ISDN_DIVAS_PRIPCI=y +CONFIG_ISDN_DIVAS_DIVACAPI=m +CONFIG_ISDN_DIVAS_USERIDI=m +CONFIG_ISDN_DIVAS_MAINT=m + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=m + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=y +CONFIG_JOYSTICK_IFORCE_232=y +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_GTCO=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_WACOM=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_UCB1400=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_PCSPKR is not set +CONFIG_INPUT_ATI_REMOTE=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_UINPUT=m + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +CONFIG_ROCKETPORT=m +CONFIG_CYCLADES=m +# CONFIG_CYZ_INTR is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_MOXA_SMARTIO_NEW is not set +# CONFIG_ISI is not set +CONFIG_SYNCLINK=m +CONFIG_SYNCLINKMP=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_PMACZILOG=m +CONFIG_SERIAL_ICOM=m +CONFIG_SERIAL_TXX9=y +CONFIG_HAS_TXX9_SERIAL=y +CONFIG_SERIAL_TXX9_NR_UARTS=6 +CONFIG_SERIAL_TXX9_CONSOLE=y +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_OF_PLATFORM=m +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_CRASH is not set +CONFIG_PRINTER=m +CONFIG_LP_CONSOLE=y +CONFIG_PPDEV=m +CONFIG_TIPAR=m +CONFIG_HVC_DRIVER=y +CONFIG_HVC_CONSOLE=y +CONFIG_HVC_ISERIES=y +# CONFIG_HVC_FSS is not set +# CONFIG_PPC_EARLY_DEBUG_FSS is not set +CONFIG_HVC_RTAS=y +CONFIG_HVC_BEAT=y +CONFIG_HVCS=m + +# +# IPMI +# +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +CONFIG_WATCHDOG_RTAS=m + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m +CONFIG_WDT_501_PCI=y + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_HW_RANDOM=y +CONFIG_GEN_RTC=y +# CONFIG_GEN_RTC_X is not set +CONFIG_R3964=m +# CONFIG_APPLICOM is not set +CONFIG_AGP=y +CONFIG_AGP_UNINORTH=y +CONFIG_DRM=m +CONFIG_DRM_TDFX=m +CONFIG_DRM_R128=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_MGA=m +CONFIG_DRM_SIS=m +CONFIG_DRM_VIA=m +CONFIG_DRM_SAVAGE=m + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +CONFIG_CARDMAN_4000=m +CONFIG_CARDMAN_4040=m +# CONFIG_RAW_DRIVER is not set +CONFIG_HANGCHECK_TIMER=m + +# +# TPM devices +# +CONFIG_TCG_TPM=m +CONFIG_TCG_ATMEL=m +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +CONFIG_I2C_ISA=m +CONFIG_I2C_POWERMAC=y +CONFIG_I2C_NFORCE2=m +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PARPORT_LIGHT=m +CONFIG_I2C_PROSAVAGE=m +CONFIG_I2C_SAVAGE4=m +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +CONFIG_I2C_STUB=m +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +CONFIG_I2C_VOODOO3=m + +# +# Miscellaneous I2C Chip support +# +CONFIG_SENSORS_DS1337=m +CONFIG_SENSORS_DS1374=m +CONFIG_SENSORS_EEPROM=m +CONFIG_SENSORS_PCF8574=m +CONFIG_SENSORS_PCA9539=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_MAX6875=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=m +CONFIG_HWMON_VID=m +CONFIG_SENSORS_ABITUGURU=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ASB100=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_FSCHER=m +CONFIG_SENSORS_FSCPOS=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_SM501=m + +# +# Multimedia devices +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TDA9875=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_WM8739=m + +# +# Video decoders +# +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_SAA7111=m +CONFIG_VIDEO_SAA7114=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_SAA7191=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_VPX3220=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_CX25840=m + +# +# MPEG video encoders +# +CONFIG_VIDEO_CX2341X=m + +# +# Video encoders +# +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m + +# +# Video improvement chips +# +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +# CONFIG_VIDEO_VIVI is not set +CONFIG_VIDEO_BT848=m +CONFIG_VIDEO_BT848_DVB=y +CONFIG_VIDEO_SAA6588=m +CONFIG_VIDEO_BWQCAM=m +CONFIG_VIDEO_CQCAM=m +CONFIG_VIDEO_W9966=m +CONFIG_VIDEO_CPIA=m +CONFIG_VIDEO_CPIA_PP=m +CONFIG_VIDEO_CPIA_USB=m +CONFIG_VIDEO_CPIA2=m +CONFIG_VIDEO_SAA5246A=m +CONFIG_VIDEO_SAA5249=m +CONFIG_TUNER_3036=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_DPC=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_IVTV=m +# CONFIG_VIDEO_CAFE_CCIC is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_29XXX=y +CONFIG_VIDEO_PVRUSB2_24XXX=y +CONFIG_VIDEO_PVRUSB2_SYSFS=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_USBVIDEO=m +CONFIG_USB_VICAM=m +CONFIG_USB_IBMCAM=m +CONFIG_USB_KONICAWC=m +CONFIG_USB_QUICKCAM_MESSENGER=m +CONFIG_USB_ET61X251=m +CONFIG_VIDEO_OVCAMCHIP=m +CONFIG_USB_W9968CF=m +CONFIG_USB_OV511=m +CONFIG_USB_SE401=m +CONFIG_USB_SN9C102=m +CONFIG_USB_STV680=m +CONFIG_USB_ZC0301=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_ZR364XX=m +# CONFIG_RADIO_ADAPTERS is not set +CONFIG_DVB_CORE=m +CONFIG_DVB_CORE_ATTACH=y +CONFIG_DVB_CAPTURE_DRIVERS=y + +# +# Supported SAA7146 based PCI Adapters +# +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_PATCH=m + +# +# Supported USB Adapters +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_CINERGYT2=m +CONFIG_DVB_CINERGYT2_TUNING=y +CONFIG_DVB_CINERGYT2_STREAM_URB_COUNT=32 +CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512 +CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250 +CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y +CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100 + +# +# Supported FlexCopII (B2C2) Adapters +# +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set + +# +# Supported BT878 Adapters +# +CONFIG_DVB_BT8XX=m + +# +# Supported Pluto2 Adapters +# +CONFIG_DVB_PLUTO2=m + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_STV0299=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_MT312=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_TDA10086=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m + +# +# Tuners/PLL support +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TDA827X=m +CONFIG_DVB_TUNER_QT1010=m +CONFIG_DVB_TUNER_MT2060=m + +# +# Miscellaneous devices +# +CONFIG_DVB_LNBP21=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_TUA6100=m +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_BUF=m +CONFIG_VIDEO_BUF_DVB=m +CONFIG_VIDEO_BTCX=m +CONFIG_VIDEO_IR=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_DAB=y +CONFIG_USB_DABUSB=m + +# +# Graphics support +# +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_LCD_CLASS_DEVICE=m + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=m + +# +# Display hardware drivers +# +CONFIG_VGASTATE=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_DDC=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_SVGALIB=m +CONFIG_FB_MACMODES=y +CONFIG_FB_BACKLIGHT=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +CONFIG_FB_CIRRUS=m +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +CONFIG_FB_OF=y +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_NVIDIA=y +CONFIG_FB_NVIDIA_I2C=y +# CONFIG_FB_NVIDIA_DEBUG is not set +CONFIG_FB_NVIDIA_BACKLIGHT=y +CONFIG_FB_RIVA=m +# CONFIG_FB_RIVA_I2C is not set +# CONFIG_FB_RIVA_DEBUG is not set +CONFIG_FB_RIVA_BACKLIGHT=y +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_FB_MATROX_G=y +CONFIG_FB_MATROX_I2C=m +CONFIG_FB_MATROX_MAVEN=m +CONFIG_FB_MATROX_MULTIHEAD=y +CONFIG_FB_RADEON=y +CONFIG_FB_RADEON_I2C=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +CONFIG_FB_S3=m +CONFIG_FB_SAVAGE=m +CONFIG_FB_SAVAGE_I2C=y +CONFIG_FB_SAVAGE_ACCEL=y +# CONFIG_FB_SIS is not set +CONFIG_FB_NEOMAGIC=m +CONFIG_FB_KYRO=m +CONFIG_FB_3DFX=m +CONFIG_FB_3DFX_ACCEL=y +CONFIG_FB_VOODOO1=m +# CONFIG_FB_VT8623 is not set +CONFIG_FB_TRIDENT=m +CONFIG_FB_TRIDENT_ACCEL=y +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +CONFIG_FB_SM501=m +CONFIG_FB_IBM_GXT4500=y +CONFIG_FB_PS3=y +CONFIG_FB_PS3_DEFAULT_SIZE_M=18 +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DUMMY=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +# CONFIG_SND_SERIAL_U16550 is not set +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m + +# +# PCI devices +# +CONFIG_SND_AD1889=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALS4000=m +CONFIG_SND_ALI5451=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AZT3328=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_FM801_TEA575X=m +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_KORG1212_FIRMWARE_IN_KERNEL=y +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL=y +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_SONICVIBES=m +CONFIG_SND_TRIDENT=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m +CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y +CONFIG_SND_AC97_POWER_SAVE=y + +# +# ALSA PowerMac devices +# +CONFIG_SND_POWERMAC=m +CONFIG_SND_POWERMAC_AUTO_DRC=y + +# +# ALSA PowerPC devices +# +CONFIG_SND_PS3=m +CONFIG_SND_PS3_DEFAULT_START_DELAY=1000 + +# +# Apple Onboard Audio driver +# +CONFIG_SND_AOA=m +CONFIG_SND_AOA_FABRIC_LAYOUT=m +CONFIG_SND_AOA_ONYX=m +CONFIG_SND_AOA_TAS=m +CONFIG_SND_AOA_TOONIE=m +CONFIG_SND_AOA_SOUNDBUS=m +CONFIG_SND_AOA_SOUNDBUS_I2S=m + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_USX2Y=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y + +# +# PCMCIA devices +# +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_PDAUDIOCF is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +CONFIG_USB_HIDINPUT_POWERBOOK=y +CONFIG_HID_FF=y +CONFIG_HID_PID=y +CONFIG_LOGITECH_FF=y +CONFIG_PANTHERLORD_FF=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_ZEROPLUS_FF=y +CONFIG_USB_HIDDEV=y + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PPC_OF=y +CONFIG_USB_OHCI_HCD_PPC_OF_BE=y +CONFIG_USB_OHCI_HCD_PPC_OF_LE=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y +CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_U132_HCD=m +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_CS=m + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_KARMA=y +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MON=y + +# +# USB port drivers +# +CONFIG_USB_USS720=m + +# +# USB Serial Converter support +# +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_AIRPRIME=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP2101=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_FUNSOFT=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_MPR=y +CONFIG_USB_SERIAL_KEYSPAN_USA28=y +CONFIG_USB_SERIAL_KEYSPAN_USA28X=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +CONFIG_USB_SERIAL_KEYSPAN_USA19=y +CONFIG_USB_SERIAL_KEYSPAN_USA18X=y +CONFIG_USB_SERIAL_KEYSPAN_USA19W=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y +CONFIG_USB_SERIAL_KEYSPAN_USA49W=y +CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_HP4X=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EZUSB=y + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_AUERSWALD=m +CONFIG_USB_RIO500=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_BERRY_CHARGE=m +CONFIG_USB_LED=m +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_PHIDGET=m +CONFIG_USB_PHIDGETKIT=m +CONFIG_USB_PHIDGETMOTORCONTROL=m +CONFIG_USB_PHIDGETSERVO=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=m + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_SDHCI=m +CONFIG_MMC_WBSD=m +CONFIG_MMC_TIFM_SD=m + +# +# LED devices +# +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m + +# +# InfiniBand support +# +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_IPATH=m +CONFIG_INFINIBAND_EHCA=m +CONFIG_INFINIBAND_AMSO1100=m +# CONFIG_INFINIBAND_AMSO1100_DEBUG is not set +CONFIG_INFINIBAND_CXGB3=m +# CONFIG_INFINIBAND_CXGB3_DEBUG is not set +CONFIG_MLX4_INFINIBAND=m +CONFIG_INFINIBAND_IPOIB=m +# CONFIG_INFINIBAND_IPOIB_CM is not set +CONFIG_INFINIBAND_IPOIB_DEBUG=y +CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_ISER=m + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# +CONFIG_EDAC=m + +# +# Reporting subsystems +# +CONFIG_EDAC_DEBUG=y +CONFIG_EDAC_MM_EDAC=m +CONFIG_EDAC_CELL=m +CONFIG_EDAC_POLL=y + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_M48T86 is not set +CONFIG_RTC_DRV_V3020=m + +# +# on-CPU RTC drivers +# + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +CONFIG_INTEL_IOATDMA=m + +# +# Auxiliary Display support +# +CONFIG_KS0108=m +CONFIG_KS0108_PORT=0x378 +CONFIG_KS0108_DELAY=2 + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT2_FS_XIP=y +CONFIG_FS_XIP=y +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_PROC_INFO=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_SECURITY=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_NOLOCK=m +CONFIG_GFS2_FS_LOCKING_DLM=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_MINIX_FS=m +CONFIG_ROMFS_FS=m +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_DNOTIFY=y +CONFIG_AUTOFS_FS=m +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_RAMFS=y +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_SQUASHFS_VMALLOC is not set +CONFIG_VXFS_FS=m +# CONFIG_HPFS_FS is not set +CONFIG_QNX4FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_DIRECTIO=y +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_TCP=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BIND34=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_SPKM3=m +# CONFIG_SMB_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +CONFIG_NCPFS_SMALLDOS=y +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +# CONFIG_CODA_FS_OLD_API is not set +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +CONFIG_DLM=m +CONFIG_DLM_DEBUG=y +# CONFIG_UCC_SLOW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y + +# +# Instrumentation Support +# +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_OPROFILE_CELL=y +CONFIG_KPROBES=y + +# +# Kernel hacking +# +# CONFIG_DEBUG_IGNORE_QUIET is not set +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +CONFIG_HEADERS_CHECK=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +CONFIG_DEBUG_LIST=y +# CONFIG_FORCED_INLINING is not set +CONFIG_BOOT_DELAY=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_DEBUG_STACKOVERFLOW=y +CONFIG_DEBUG_STACK_USAGE=y +CONFIG_HCALL_STATS=y +CONFIG_DEBUGGER=y +CONFIG_XMON=y +CONFIG_XMON_DEFAULT=y +CONFIG_XMON_DISASSEMBLY=y +CONFIG_IRQSTACKS=y +CONFIG_BOOTX_TEXT=y +# CONFIG_PPC_EARLY_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_CAPABILITIES=y +# CONFIG_SECURITY_ROOTPLUG is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +CONFIG_KEYS_COMPAT=y + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_LRW=m +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_CAMELLIA=m +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_MPILIB=y +CONFIG_CRYPTO_SIGNATURE=y +CONFIG_CRYPTO_SIGNATURE_DSA=y + +# +# Hardware crypto devices +# diff --git a/drd/scripts/run-matinv b/drd/scripts/run-matinv old mode 100644 new mode 100755 diff --git a/drd/scripts/run-splash2 b/drd/scripts/run-splash2 old mode 100644 new mode 100755 diff --git a/drd/scripts/run-splash2-water-input b/drd/scripts/run-splash2-water-input old mode 100644 new mode 100755 diff --git a/drd/tests/Makefile.am b/drd/tests/Makefile.am index c58e2ed..fb565a9 100644 --- a/drd/tests/Makefile.am +++ b/drd/tests/Makefile.am @@ -11,9 +11,16 @@ dist_noinst_SCRIPTS = \ supported_sem_init noinst_HEADERS = \ - tsan_thread_wrappers_pthread.h + tsan_thread_wrappers_pthread.h \ + unified_annotations.h EXTRA_DIST = \ + annotate_barrier.stderr.exp \ + annotate_barrier.vgtest \ + annotate_hb_err.stderr.exp \ + annotate_hb_err.vgtest \ + annotate_hb_race.stderr.exp \ + annotate_hb_race.vgtest \ annotate_hbefore.stderr.exp \ annotate_hbefore.vgtest \ annotate_order_1.stderr.exp \ @@ -24,6 +31,8 @@ EXTRA_DIST = \ annotate_order_3.vgtest \ annotate_publish_hg.stderr.exp \ annotate_publish_hg.vgtest \ + annotate_smart_pointer.stderr.exp \ + annotate_smart_pointer.vgtest \ annotate_spinlock.stderr.exp \ annotate_spinlock.vgtest \ annotate_rwlock.stderr.exp \ @@ -42,6 +51,8 @@ EXTRA_DIST = \ annotate_ignore_write2.vgtest \ annotate_trace_memory.stderr.exp \ annotate_trace_memory.vgtest \ + annotate_static.stderr.exp \ + annotate_static.vgtest \ atomic_var.stderr.exp \ atomic_var.vgtest \ bar_bad.stderr.exp \ @@ -51,6 +62,8 @@ EXTRA_DIST = \ bar_trivial.vgtest \ boost_thread.stderr.exp \ boost_thread.vgtest \ + bug-235681.stderr.exp \ + bug-235681.vgtest \ circular_buffer.stderr.exp \ circular_buffer.vgtest \ custom_alloc.stderr.exp \ @@ -147,12 +160,18 @@ EXTRA_DIST = \ pth_process_shared_mutex.vgtest \ pth_spinlock.stderr.exp \ pth_spinlock.vgtest \ + pth_uninitialized_cond.stderr.exp \ + pth_uninitialized_cond.vgtest \ + qt4_atomic.stderr.exp \ + qt4_atomic.vgtest \ qt4_mutex.stderr.exp \ qt4_mutex.vgtest \ qt4_rwlock.stderr.exp \ qt4_rwlock.vgtest \ qt4_semaphore.stderr.exp \ qt4_semaphore.vgtest \ + read_after_free.stderr.exp \ + read_after_free.vgtest \ recursive_mutex.stderr.exp-linux \ recursive_mutex.stderr.exp-darwin \ recursive_mutex.vgtest \ @@ -179,6 +198,8 @@ EXTRA_DIST = \ sem_open_traced.vgtest \ sigalrm.stderr.exp \ sigalrm.vgtest \ + sigaltstack.stderr.exp \ + sigaltstack.vgtest \ tc01_simple_race.stderr.exp \ tc01_simple_race.vgtest \ tc02_simple_tls.stderr.exp \ @@ -242,9 +263,13 @@ EXTRA_DIST = \ check_PROGRAMS = \ + annotate_hb_err \ + annotate_hb_race \ annotate_ignore_rw \ annotate_ignore_write \ annotate_publish_hg \ + annotate_static \ + bug-235681 \ custom_alloc \ fp_race \ hold_lock \ @@ -262,6 +287,7 @@ check_PROGRAMS = \ pth_inconsistent_cond_wait \ pth_mutex_reinit \ pth_process_shared_mutex \ + pth_uninitialized_cond \ recursive_mutex \ rwlock_race \ rwlock_test \ @@ -279,9 +305,14 @@ check_PROGRAMS += boost_thread endif if HAVE_BUILTIN_ATOMIC -check_PROGRAMS += annotate_rwlock atomic_var circular_buffer -if !VGCONF_OS_IS_FREEBSD -check_PROGRAMS += tsan_unittest +check_PROGRAMS += \ + annotate_barrier \ + annotate_rwlock \ + annotate_smart_pointer \ + atomic_var \ + circular_buffer \ + read_after_free \ + tsan_unittest endif endif @@ -305,6 +336,10 @@ if HAVE_QTCORE check_PROGRAMS += qt4_mutex qt4_rwlock qt4_semaphore endif +if HAVE_QTCORE_QATOMICINT +check_PROGRAMS += qt4_atomic +endif + AM_CFLAGS += $(AM_FLAG_M3264_PRI) @FLAG_W_EXTRA@ -Wno-inline -Wno-unused-parameter AM_CXXFLAGS += $(AM_FLAG_M3264_PRI) @FLAG_W_EXTRA@ -Wno-inline -Wno-unused-parameter @@ -335,6 +370,12 @@ boost_thread_CXXFLAGS = $(AM_CXXFLAGS) $(BOOST_CFLAGS) boost_thread_LDADD = $(BOOST_LIBS) endif +if HAVE_BUILTIN_ATOMIC +annotate_smart_pointer_SOURCES = annotate_smart_pointer.cpp +endif + +annotate_static_SOURCES = annotate_static.cpp + if HAVE_OPENMP omp_matinv_CFLAGS = $(AM_CFLAGS) -fopenmp omp_matinv_LDFLAGS = -fopenmp @@ -366,3 +407,9 @@ qt4_semaphore_SOURCES = qt4_semaphore.cpp qt4_semaphore_CXXFLAGS = $(AM_CXXFLAGS) $(QTCORE_CFLAGS) qt4_semaphore_LDADD = $(LDADD) $(QTCORE_LIBS) endif + +if HAVE_QTCORE_QATOMICINT +qt4_atomic_SOURCES = qt4_atomic.cpp +qt4_atomic_CXXFLAGS = $(AM_CXXFLAGS) $(QTCORE_CFLAGS) +qt4_atomic_LDADD = $(LDADD) $(QTCORE_LIBS) +endif diff --git a/drd/tests/annotate_barrier.c b/drd/tests/annotate_barrier.c new file mode 100644 index 0000000..5db1763 --- /dev/null +++ b/drd/tests/annotate_barrier.c @@ -0,0 +1,172 @@ +/* + * Test whether all data races are detected in a multithreaded program with + * user-annotated barriers. See also pth_barrier.c. + */ + + +#define _GNU_SOURCE + + +#include /* pthread_create() */ +#include /* fprintf() */ +#include /* atoi() */ +#include /* memset() */ +#include /* usleep() */ +#include "../../drd/drd.h" +#include "../../config.h" + + +#define BARRIER_SERIAL_THREAD -1 + + +/* Local datatypes. */ + +typedef struct +{ + /* + * number of threads that must call barrier_wait() before any of them + * successfully return from the call. + */ + unsigned thread_count; + /* number of barrier_wait() calls since last barrier. */ + volatile unsigned wait_count; + /* + * barrier count. Only the least significant bit matters -- a single bit + * counter would be sufficient. + */ + volatile unsigned barrier_count; +} barrier_t; + +struct threadinfo +{ + int thread_num; + barrier_t* b; + pthread_t tid; + int* array; + int iterations; +}; + + +/* Local variables. */ + +static int s_silent; + + +/* Local functions. */ + +static void barrier_init(barrier_t* b, unsigned count) +{ + b->thread_count = count; + b->wait_count = 0; + b->barrier_count = 0; + ANNOTATE_BARRIER_INIT(b, count, 0); +} + +static void barrier_destroy(barrier_t* b) +{ + ANNOTATE_BARRIER_DESTROY(b); + memset(b, 0, sizeof(*b)); +} + +static int barrier_wait(barrier_t* b) +{ + int res; + unsigned barrier_count; + + res = 0; + ANNOTATE_BARRIER_WAIT_BEFORE(b); + barrier_count = b->barrier_count; + if (__sync_add_and_fetch(&b->wait_count, 1) == b->thread_count) + { + __sync_sub_and_fetch(&b->wait_count, b->thread_count); + __sync_add_and_fetch(&b->barrier_count, 1); + res = BARRIER_SERIAL_THREAD; + } + else + { + while (b->barrier_count == barrier_count) + { +#ifndef HAVE_PTHREAD_YIELD + /* Darwin doesn't have an implementation of pthread_yield(). */ + usleep(100 * 1000); +#else + pthread_yield(); +#endif + } + } + ANNOTATE_BARRIER_WAIT_AFTER(b); + return res; +} + +/* + * Single thread, which touches p->iterations elements of array p->array. + * Each modification of an element of p->array is a data race. + */ +static void* threadfunc(struct threadinfo* p) +{ + int i; + int* const array = p->array; + barrier_t* const b = p->b; + if (! s_silent) + printf("thread %d iteration 0\n", p->thread_num); + barrier_wait(b); + for (i = 0; i < p->iterations; i++) + { + if (! s_silent) + printf("thread %d iteration %d; writing to %p\n", + p->thread_num, i + 1, &array[i]); + array[i] = i; + barrier_wait(b); + } + return 0; +} + +/* Actual test, consisting of nthread threads. */ +static void barriers_and_races(const int nthread, const int iterations) +{ + int i; + struct threadinfo* t; + barrier_t b; + int* array; + + t = malloc(nthread * sizeof(struct threadinfo)); + array = malloc(iterations * sizeof(array[0])); + + if (! s_silent) + printf("&array[0] = %p\n", array); + + barrier_init(&b, nthread); + + for (i = 0; i < nthread; i++) + { + t[i].thread_num = i + 1; + t[i].b = &b; + t[i].array = array; + t[i].iterations = iterations; + pthread_create(&t[i].tid, 0, (void*(*)(void*))threadfunc, &t[i]); + } + + for (i = 0; i < nthread; i++) + pthread_join(t[i].tid, 0); + + barrier_destroy(&b); + + free(array); + free(t); +} + +int main(int argc, char** argv) +{ + int nthread; + int iterations; + + nthread = (argc > 1) ? atoi(argv[1]) : 2; + iterations = (argc > 2) ? atoi(argv[2]) : 3; + s_silent = (argc > 3) ? atoi(argv[3]) : 0; + + barriers_and_races(nthread, iterations); + + fprintf(stderr, "Done.\n"); + + return 0; +} diff --git a/drd/tests/annotate_barrier.stderr.exp b/drd/tests/annotate_barrier.stderr.exp new file mode 100644 index 0000000..1ae8934 --- /dev/null +++ b/drd/tests/annotate_barrier.stderr.exp @@ -0,0 +1,47 @@ + +The annotation macro ANNOTATE_BARRIER_INIT has not yet been implemented in + at 0x........: barrier_init (annotate_barrier.c:?) + by 0x........: barriers_and_races (annotate_barrier.c:?) + by 0x........: main (annotate_barrier.c:?) + +Thread 2: +The annotation macro ANNOTATE_BARRIER_WAIT_BEFORE has not yet been implemented in + at 0x........: barrier_wait (annotate_barrier.c:?) + by 0x........: threadfunc (annotate_barrier.c:?) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) + +Thread 3: +The annotation macro ANNOTATE_BARRIER_WAIT_AFTER has not yet been implemented in + at 0x........: barrier_wait (annotate_barrier.c:?) + by 0x........: threadfunc (annotate_barrier.c:?) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) + +The annotation macro ANNOTATE_BARRIER_WAIT_BEFORE has not yet been implemented in + at 0x........: barrier_wait (annotate_barrier.c:?) + by 0x........: threadfunc (annotate_barrier.c:?) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) + +Thread 2: +Conflicting store by thread 2 at 0x........ size 4 + at 0x........: threadfunc (annotate_barrier.c:?) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) + by 0x........: (within libpthread-?.?.so) +Address 0x........ is at offset 0 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (annotate_barrier.c:?) + by 0x........: main (annotate_barrier.c:?) + +The annotation macro ANNOTATE_BARRIER_WAIT_AFTER has not yet been implemented in + at 0x........: barrier_wait (annotate_barrier.c:?) + by 0x........: threadfunc (annotate_barrier.c:?) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) + +Thread 1: +The annotation macro ANNOTATE_BARRIER_DESTROY has not yet been implemented in + at 0x........: barrier_destroy (annotate_barrier.c:?) + by 0x........: barriers_and_races (annotate_barrier.c:?) + by 0x........: main (annotate_barrier.c:?) + +Done. + +ERROR SUMMARY: 11 errors from 7 contexts (suppressed: 0 from 0) diff --git a/drd/tests/annotate_barrier.vgtest b/drd/tests/annotate_barrier.vgtest new file mode 100644 index 0000000..c3491e5 --- /dev/null +++ b/drd/tests/annotate_barrier.vgtest @@ -0,0 +1,4 @@ +prereq: test -e annotate_barrier && ./supported_libpthread +vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no --num-callers=3 +prog: annotate_barrier 2 1 1 +stderr_filter: filter_stderr diff --git a/drd/tests/annotate_hb_err.c b/drd/tests/annotate_hb_err.c new file mode 100644 index 0000000..3ed15b9 --- /dev/null +++ b/drd/tests/annotate_hb_err.c @@ -0,0 +1,53 @@ +/* Test program that triggers several happens-before usage errors. */ + + +#include +#include +#include +#include "unified_annotations.h" + + +int main(int argc, char** argv) +{ + pthread_mutex_t m; + pthread_cond_t cv; + int i[64]; + + pthread_mutex_init(&m, NULL); + pthread_cond_init(&cv, NULL); + + /* happens-after without preceding happens-before. */ + U_ANNOTATE_HAPPENS_AFTER(&i); + + /* happens-after on a mutex. */ + U_ANNOTATE_HAPPENS_BEFORE(&m); + + /* happens-after on a condition variable. */ + U_ANNOTATE_HAPPENS_BEFORE(&cv); + + /* condition variable operation on a h.b. annotated object. */ + U_ANNOTATE_HAPPENS_BEFORE(&i); + pthread_cond_init((pthread_cond_t*)&i, NULL); + + /* The sequence below is fine. */ + U_ANNOTATE_NEW_MEMORY(&i, sizeof(i)); + U_ANNOTATE_HAPPENS_BEFORE(&i); + U_ANNOTATE_HAPPENS_AFTER(&i); + U_ANNOTATE_NEW_MEMORY(&i, sizeof(i)); + U_ANNOTATE_HAPPENS_BEFORE(&i); + U_ANNOTATE_NEW_MEMORY(&i, sizeof(i)); + + /* happens-before after happens-after. */ + U_ANNOTATE_HAPPENS_BEFORE(&i); + U_ANNOTATE_HAPPENS_AFTER(&i); + U_ANNOTATE_HAPPENS_BEFORE(&i); + + fprintf(stderr, "Done.\n"); + return 0; +} + +/* + * Local variables: + * c-basic-offset: 2 + * End: + */ diff --git a/drd/tests/annotate_hb_err.stderr.exp b/drd/tests/annotate_hb_err.stderr.exp new file mode 100644 index 0000000..b52069b --- /dev/null +++ b/drd/tests/annotate_hb_err.stderr.exp @@ -0,0 +1,25 @@ + +wrong type of synchronization object + at 0x........: U_AnnotateHappensBefore (unified_annotations.h:?) + by 0x........: main (annotate_hb_err.c:?) +mutex 0x........ was first observed at: + at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?) + by 0x........: main (annotate_hb_err.c:?) + +wrong type of synchronization object + at 0x........: U_AnnotateHappensBefore (unified_annotations.h:?) + by 0x........: main (annotate_hb_err.c:?) +cond 0x........ was first observed at: + at 0x........: pthread_cond_init (drd_pthread_intercepts.c:?) + by 0x........: main (annotate_hb_err.c:?) + +wrong type of synchronization object + at 0x........: pthread_cond_init (drd_pthread_intercepts.c:?) + by 0x........: main (annotate_hb_err.c:?) +order annotation 0x........ was first observed at: + at 0x........: U_AnnotateHappensAfter (unified_annotations.h:?) + by 0x........: main (annotate_hb_err.c:?) + +Done. + +ERROR SUMMARY: 3 errors from 3 contexts (suppressed: 0 from 0) diff --git a/drd/tests/annotate_hb_err.vgtest b/drd/tests/annotate_hb_err.vgtest new file mode 100644 index 0000000..eab9704 --- /dev/null +++ b/drd/tests/annotate_hb_err.vgtest @@ -0,0 +1,4 @@ +prereq: test -e annotate_hb_err && ./supported_libpthread +vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no +prog: annotate_hb_err +stderr_filter: filter_stderr_and_thread_no diff --git a/drd/tests/annotate_hb_race.c b/drd/tests/annotate_hb_race.c new file mode 100644 index 0000000..0c2b450 --- /dev/null +++ b/drd/tests/annotate_hb_race.c @@ -0,0 +1,50 @@ +/* + * Test program with happens-before / happens-after annotations that triggers + * a data race. The data race will only be reported if happens-after + * annotations that occur in different threads are not totally ordered. Or: + * this is a test for the implementation of ordering annotations. + */ + + +#include +#include +#include "unified_annotations.h" + + +static int s_i; + + +static void* thread_func(void* arg) +{ + int i; + + U_ANNOTATE_HAPPENS_AFTER(&s_i); + i = s_i; + U_ANNOTATE_HAPPENS_AFTER(&s_i); + *(int*)arg = i; + return NULL; +} + +int main(int argc, char** argv) +{ + pthread_t tid[2]; + int result[2]; + + U_ANNOTATE_HAPPENS_BEFORE(&s_i); + pthread_create(&tid[0], 0, thread_func, &result[0]); + pthread_create(&tid[1], 0, thread_func, &result[1]); + s_i = 1; + + pthread_join(tid[0], NULL); + pthread_join(tid[1], NULL); + + fprintf(stderr, "Done.\n"); + + return 0; +} + +/* + * Local variables: + * c-basic-offset: 2 + * End: + */ diff --git a/drd/tests/annotate_hb_race.stderr.exp b/drd/tests/annotate_hb_race.stderr.exp new file mode 100644 index 0000000..bcb275b --- /dev/null +++ b/drd/tests/annotate_hb_race.stderr.exp @@ -0,0 +1,8 @@ + +Conflicting store by thread x at 0x........ size 4 + at 0x........: main (annotate_hb_race.c:?) +Allocation context: BSS section of annotate_hb_race + +Done. + +ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0) diff --git a/drd/tests/annotate_hb_race.vgtest b/drd/tests/annotate_hb_race.vgtest new file mode 100644 index 0000000..38f75e9 --- /dev/null +++ b/drd/tests/annotate_hb_race.vgtest @@ -0,0 +1,4 @@ +prereq: test -e annotate_hb_race && ./supported_libpthread +vgopts: --check-stack-var=yes --show-confl-seg=no +prog: annotate_hb_race +stderr_filter: filter_stderr_and_thread_no diff --git a/drd/tests/annotate_ignore_rw.c b/drd/tests/annotate_ignore_rw.c index e4eba06..f6a63b6 100644 --- a/drd/tests/annotate_ignore_rw.c +++ b/drd/tests/annotate_ignore_rw.c @@ -26,7 +26,7 @@ int main(int argc, char** argv) int ign_rw = 1; int tmp; pthread_t tid; - + while ((optchar = getopt(argc, argv, "r")) != EOF) { switch (optchar) diff --git a/drd/tests/annotate_ignore_write.c b/drd/tests/annotate_ignore_write.c index 16efe03..2b71eb2 100644 --- a/drd/tests/annotate_ignore_write.c +++ b/drd/tests/annotate_ignore_write.c @@ -25,7 +25,7 @@ int main(int argc, char** argv) int optchar; int ign_rw = 1; pthread_t tid; - + while ((optchar = getopt(argc, argv, "r")) != EOF) { switch (optchar) diff --git a/drd/tests/annotate_publish_hg.stderr.exp b/drd/tests/annotate_publish_hg.stderr.exp index 66eea7c..b46c0ed 100644 --- a/drd/tests/annotate_publish_hg.stderr.exp +++ b/drd/tests/annotate_publish_hg.stderr.exp @@ -1,5 +1,5 @@ -The annotation macro ANNOTATE_PUBLISH_MEMORY_RANGE has not yet been implemented in +The annotation macro ANNOTATE_PUBLISH_MEMORY_RANGE has not yet been implemented in at 0x........: main (annotate_publish_hg.c:?) Done. diff --git a/drd/tests/annotate_rwlock.c b/drd/tests/annotate_rwlock.c index bc290ee..5ebb5fd 100644 --- a/drd/tests/annotate_rwlock.c +++ b/drd/tests/annotate_rwlock.c @@ -60,7 +60,7 @@ static void rwlock_rdlock(rwlock_t* p) ; if (p->writer_count == 0) break; -#ifdef __APPLE__ +#ifndef HAVE_PTHREAD_YIELD /* Darwin doesn't have an implementation of pthread_yield(). */ usleep(100 * 1000); #else @@ -84,7 +84,7 @@ static void rwlock_wrlock(rwlock_t* p) ; if (p->reader_count == 0) break; -#ifdef __APPLE__ +#ifndef HAVE_PTHREAD_YIELD /* Darwin doesn't have an implementation of pthread_yield(). */ usleep(100 * 1000); #else diff --git a/drd/tests/annotate_smart_pointer.cpp b/drd/tests/annotate_smart_pointer.cpp new file mode 100755 index 0000000..7ef5e7c --- /dev/null +++ b/drd/tests/annotate_smart_pointer.cpp @@ -0,0 +1,330 @@ +/* + * Test program that illustrates how to annotate a smart pointer + * implementation. In a multithreaded program the following is relevant when + * working with smart pointers: + * - whether or not the objects pointed at are shared over threads. + * - whether or not the methods of the objects pointed at are thread-safe. + * - whether or not the smart pointer objects are shared over threads. + * - whether or not the smart pointer object itself is thread-safe. + * + * Most smart pointer implemenations are not thread-safe + * (e.g. boost::shared_ptr<>, tr1::shared_ptr<> and the smart_ptr<> + * implementation below). This means that it is not safe to modify a shared + * pointer object that is shared over threads without proper synchronization. + * + * Even for non-thread-safe smart pointers it is possible to have different + * threads access the same object via smart pointers without triggering data + * races on the smart pointer objects. + * + * A smart pointer implementation guarantees that the destructor of the object + * pointed at is invoked after the last smart pointer that points to that + * object has been destroyed or reset. Data race detection tools cannot detect + * this ordering without explicit annotation for smart pointers that track + * references without invoking synchronization operations recognized by data + * race detection tools. + */ + + +#include // assert() +#include // PTHREAD_STACK_MIN +#include // std::cerr +#include // atoi() +#ifdef _WIN32 +#include // _beginthreadex() +#include // CRITICAL_SECTION +#else +#include // pthread_mutex_t +#endif +#include "unified_annotations.h" + + +static bool s_enable_annotations = true; + + +#ifdef _WIN32 + +class AtomicInt32 +{ +public: + AtomicInt32(const int value = 0) : m_value(value) { } + ~AtomicInt32() { } + LONG operator++() { return InterlockedIncrement(&m_value); } + LONG operator--() { return InterlockedDecrement(&m_value); } + +private: + volatile LONG m_value; +}; + +class Mutex +{ +public: + Mutex() : m_mutex() + { InitializeCriticalSection(&m_mutex); } + ~Mutex() + { DeleteCriticalSection(&m_mutex); } + void Lock() + { EnterCriticalSection(&m_mutex); } + void Unlock() + { LeaveCriticalSection(&m_mutex); } + +private: + CRITICAL_SECTION m_mutex; +}; + +class Thread +{ +public: + Thread() : m_thread(INVALID_HANDLE_VALUE) { } + ~Thread() { } + void Create(void* (*pf)(void*), void* arg) + { + WrapperArgs* wrapper_arg_p = new WrapperArgs(pf, arg); + m_thread = reinterpret_cast(_beginthreadex(NULL, 0, wrapper, + wrapper_arg_p, 0, NULL)); + } + void Join() + { WaitForSingleObject(m_thread, INFINITE); } + +private: + struct WrapperArgs + { + WrapperArgs(void* (*pf)(void*), void* arg) : m_pf(pf), m_arg(arg) { } + + void* (*m_pf)(void*); + void* m_arg; + }; + static unsigned int __stdcall wrapper(void* arg) + { + WrapperArgs* wrapper_arg_p = reinterpret_cast(arg); + WrapperArgs wa = *wrapper_arg_p; + delete wrapper_arg_p; + return reinterpret_cast((wa.m_pf)(wa.m_arg)); + } + HANDLE m_thread; +}; + +#else // _WIN32 + +class AtomicInt32 +{ +public: + AtomicInt32(const int value = 0) : m_value(value) { } + ~AtomicInt32() { } + int operator++() { return __sync_add_and_fetch(&m_value, 1); } + int operator--() { return __sync_sub_and_fetch(&m_value, 1); } +private: + volatile int m_value; +}; + +class Mutex +{ +public: + Mutex() : m_mutex() + { pthread_mutex_init(&m_mutex, NULL); } + ~Mutex() + { pthread_mutex_destroy(&m_mutex); } + void Lock() + { pthread_mutex_lock(&m_mutex); } + void Unlock() + { pthread_mutex_unlock(&m_mutex); } + +private: + pthread_mutex_t m_mutex; +}; + +class Thread +{ +public: + Thread() : m_tid() { } + ~Thread() { } + void Create(void* (*pf)(void*), void* arg) + { + pthread_attr_t attr; + pthread_attr_init(&attr); + pthread_attr_setstacksize(&attr, PTHREAD_STACK_MIN + 4096); + pthread_create(&m_tid, &attr, pf, arg); + pthread_attr_destroy(&attr); + } + void Join() + { pthread_join(m_tid, NULL); } +private: + pthread_t m_tid; +}; + +#endif // !defined(_WIN32) + + +template +class smart_ptr +{ +public: + typedef AtomicInt32 counter_t; + + template friend class smart_ptr; + + explicit smart_ptr() + : m_ptr(NULL), m_count_ptr(NULL) + { } + + explicit smart_ptr(T* const pT) + : m_ptr(NULL), m_count_ptr(NULL) + { + set(pT, pT ? new counter_t(0) : NULL); + } + + template + explicit smart_ptr(Q* const q) + : m_ptr(NULL), m_count_ptr(NULL) + { + set(q, q ? new counter_t(0) : NULL); + } + + ~smart_ptr() + { + set(NULL, NULL); + } + + smart_ptr(const smart_ptr& sp) + : m_ptr(NULL), m_count_ptr(NULL) + { + set(sp.m_ptr, sp.m_count_ptr); + } + + template + smart_ptr(const smart_ptr& sp) + : m_ptr(NULL), m_count_ptr(NULL) + { + set(sp.m_ptr, sp.m_count_ptr); + } + + smart_ptr& operator=(const smart_ptr& sp) + { + set(sp.m_ptr, sp.m_count_ptr); + return *this; + } + + smart_ptr& operator=(T* const p) + { + set(p, p ? new counter_t(0) : NULL); + return *this; + } + + template + smart_ptr& operator=(Q* const q) + { + set(q, q ? new counter_t(0) : NULL); + return *this; + } + + T* operator->() const + { + assert(m_ptr); + return m_ptr; + } + + T& operator*() const + { + assert(m_ptr); + return *m_ptr; + } + +private: + void set(T* const pT, counter_t* const count_ptr) + { + if (m_ptr != pT) + { + if (m_count_ptr) + { + if (s_enable_annotations) + U_ANNOTATE_HAPPENS_BEFORE(m_count_ptr); + if (--(*m_count_ptr) == 0) + { + if (s_enable_annotations) + U_ANNOTATE_HAPPENS_AFTER(m_count_ptr); + delete m_ptr; + m_ptr = NULL; + delete m_count_ptr; + m_count_ptr = NULL; + } + } + m_ptr = pT; + m_count_ptr = count_ptr; + if (count_ptr) + ++(*m_count_ptr); + } + } + + T* m_ptr; + counter_t* m_count_ptr; +}; + +class counter +{ +public: + counter() + : m_mutex(), m_count() + { } + ~counter() + { + // Data race detection tools that do not recognize the + // ANNOTATE_HAPPENS_BEFORE() / ANNOTATE_HAPPENS_AFTER() annotations in the + // smart_ptr<> implementation will report that the assignment below + // triggers a data race. + m_count = -1; + } + int get() const + { + int result; + m_mutex.Lock(); + result = m_count; + m_mutex.Unlock(); + return result; + } + int post_increment() + { + int result; + m_mutex.Lock(); + result = m_count++; + m_mutex.Unlock(); + return result; + } + +private: + mutable Mutex m_mutex; + int m_count; +}; + +static void* thread_func(void* arg) +{ + smart_ptr* pp = reinterpret_cast*>(arg); + (*pp)->post_increment(); + *pp = NULL; + delete pp; + return NULL; +} + +int main(int argc, char** argv) +{ + const int nthreads = std::max(argc > 1 ? atoi(argv[1]) : 1, 1); + const int iterations = std::max(argc > 2 ? atoi(argv[2]) : 1, 1); + s_enable_annotations = argc > 3 ? !!atoi(argv[3]) : true; + + for (int j = 0; j < iterations; ++j) + { + Thread T[nthreads]; + + smart_ptr p(new counter); + p->post_increment(); + for (int i = 0; i < nthreads; ++i) + T[i].Create(thread_func, new smart_ptr(p)); + p = NULL; + for (int i = 0; i < nthreads; ++i) + T[i].Join(); + } + std::cerr << "Done.\n"; + return 0; +} + +// Local variables: +// c-basic-offset: 2 +// End: diff --git a/drd/tests/annotate_smart_pointer.stderr.exp b/drd/tests/annotate_smart_pointer.stderr.exp new file mode 100644 index 0000000..d16127f --- /dev/null +++ b/drd/tests/annotate_smart_pointer.stderr.exp @@ -0,0 +1,4 @@ + +Done. + +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/drd/tests/annotate_smart_pointer.vgtest b/drd/tests/annotate_smart_pointer.vgtest new file mode 100644 index 0000000..a103ef5 --- /dev/null +++ b/drd/tests/annotate_smart_pointer.vgtest @@ -0,0 +1,5 @@ +prereq: test -e annotate_smart_pointer && ./supported_libpthread +vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no +prog: annotate_smart_pointer +args: 50 5 +stderr_filter: filter_stderr_and_thread_no diff --git a/drd/tests/annotate_static.cpp b/drd/tests/annotate_static.cpp new file mode 100644 index 0000000..25ffd47 --- /dev/null +++ b/drd/tests/annotate_static.cpp @@ -0,0 +1,48 @@ +// Test for ANNOTATE_BENIGN_RACE_STATIC() and ANNOTATE_UNPROTECTED_READ(). + + +#include /* pthread_create() */ +#include /* fprintf() */ +#include "../../drd/drd.h" + + +/* Local variables. */ + +static int s_i; +static volatile int s_j; + +ANNOTATE_BENIGN_RACE_STATIC(s_i, "Benign because duplicate assignment."); + + +/* Local functions. */ + +static inline void AnnotateIgnoreReadsBegin() { ANNOTATE_IGNORE_READS_BEGIN(); } +static inline void AnnotateIgnoreReadsEnd() { ANNOTATE_IGNORE_READS_END(); } + +static void* thread_func(void*) +{ +#if defined(__powerpc__) && __GNUC__ -0 == 4 && __GNUC_MINOR__ -0 == 3 \ + && __GNUC_PATCHLEVEL__ -0 == 0 + AnnotateIgnoreReadsBegin(); + int i = s_j; + AnnotateIgnoreReadsEnd(); + s_i = i; +#else + s_i = ANNOTATE_UNPROTECTED_READ(s_j); +#endif + return 0; +} + +int main(int argc, char** argv) +{ + pthread_t tid; + + pthread_create(&tid, 0, thread_func, NULL); + s_j++; + s_i = s_j; + pthread_join(tid, NULL); + + fprintf(stderr, "Done.\n"); + + return 0; +} diff --git a/drd/tests/annotate_static.stderr.exp b/drd/tests/annotate_static.stderr.exp new file mode 100644 index 0000000..d16127f --- /dev/null +++ b/drd/tests/annotate_static.stderr.exp @@ -0,0 +1,4 @@ + +Done. + +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/drd/tests/annotate_static.vgtest b/drd/tests/annotate_static.vgtest new file mode 100644 index 0000000..32ec4cc --- /dev/null +++ b/drd/tests/annotate_static.vgtest @@ -0,0 +1,4 @@ +prereq: test -e annotate_static && ./supported_libpthread +vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no +prog: annotate_static +stderr_filter: filter_stderr diff --git a/drd/tests/bug-235681.c b/drd/tests/bug-235681.c new file mode 100644 index 0000000..99114eb --- /dev/null +++ b/drd/tests/bug-235681.c @@ -0,0 +1,94 @@ +/* + * pthread_cond_wait() test program. + * See also https://bugs.kde.org/show_bug.cgi?id=235681. + */ + +#include +#include +#include +#include +#include +#include + +pthread_mutex_t mutex; +pthread_cond_t cond_var; +int status; +int silent; + +static void *run_fn(void *v) +{ + int rc; + + if (!silent) + fprintf(stderr, "run_fn starting\n"); + + rc = pthread_mutex_lock(&mutex); + assert(!rc); + + while (!status) { + if (!silent) + fprintf(stderr, "run_fn(): status==0\n"); + rc = pthread_cond_wait(&cond_var, &mutex); + assert(!rc); + if (!silent) + fprintf(stderr, "run_fn(): woke up\n"); + } + if (!silent) + fprintf(stderr, "run_fn(): status==1\n"); + + rc = pthread_mutex_unlock(&mutex); + assert(!rc); + + if (!silent) + fprintf(stderr, "run_fn done\n"); + + return NULL; +} + +int main(int argc, char **argv) +{ + int rc; + pthread_t other_thread; + + if (argc > 1) + silent = 1; + + rc = pthread_mutex_init(&mutex, NULL); + assert(!rc); + rc = pthread_cond_init(&cond_var, NULL); + assert(!rc); + + status = 0; + + rc = pthread_create(&other_thread, NULL, run_fn, NULL); + assert(!rc); + + /* yield the processor, and give the other thread a chance to get into the while loop */ + if (!silent) + fprintf(stderr, "main(): sleeping...\n"); + sleep(1); + + rc = pthread_mutex_lock(&mutex); + assert(!rc); + /**** BEGIN CS *****/ + + if (!silent) + fprintf(stderr, "main(): status=1\n"); + status = 1; + rc = pthread_cond_broadcast(&cond_var); + assert(!rc); + + /**** END CS *****/ + rc = pthread_mutex_unlock(&mutex); + assert(!rc); + + if (!silent) + fprintf(stderr, "joining...\n"); + + rc = pthread_join(other_thread, NULL); + assert(!rc); + + fprintf(stderr, "Done.\n"); + + return 0; +} diff --git a/drd/tests/bug-235681.stderr.exp b/drd/tests/bug-235681.stderr.exp new file mode 100644 index 0000000..d16127f --- /dev/null +++ b/drd/tests/bug-235681.stderr.exp @@ -0,0 +1,4 @@ + +Done. + +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/drd/tests/bug-235681.vgtest b/drd/tests/bug-235681.vgtest new file mode 100644 index 0000000..f6051b7 --- /dev/null +++ b/drd/tests/bug-235681.vgtest @@ -0,0 +1,5 @@ +prereq: test -e bug-235681 && ./supported_libpthread +vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no --num-callers=3 +prog: bug-235681 +args: -q +stderr_filter: filter_stderr diff --git a/drd/tests/circular_buffer.c b/drd/tests/circular_buffer.c index 9a7238c..6803521 100644 --- a/drd/tests/circular_buffer.c +++ b/drd/tests/circular_buffer.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "../../config.h" diff --git a/drd/tests/custom_alloc.c b/drd/tests/custom_alloc.c index 8032ba2..9faead5 100644 --- a/drd/tests/custom_alloc.c +++ b/drd/tests/custom_alloc.c @@ -33,14 +33,14 @@ static void* custom_alloc(int size) if (hp + size2 > hp_lim) { hp = get_superblock(); hp_lim = hp + SUPERBLOCK_SIZE - 1; - } + } p = hp + RZ; hp += size2; VALGRIND_MALLOCLIKE_BLOCK( p, size, RZ, /*is_zeroed*/1 ); return (void*)p; -} +} static void custom_free(void* p) { @@ -85,6 +85,6 @@ int main(void) // unfortunately not identified as being in a free'd // block because the freeing of the block and shadow // chunk isn't postponed. - + // leak from make_leak() } diff --git a/drd/tests/filter_stderr b/drd/tests/filter_stderr index feff981..05f54d0 100755 --- a/drd/tests/filter_stderr +++ b/drd/tests/filter_stderr @@ -2,6 +2,8 @@ dir=`dirname $0` +sed -e "s:_pthread_start (in /usr/lib/libSystem.B.dylib):(within libpthread-?.?.so):" | + $dir/../../tests/filter_stderr_basic | # Remove "drd, ..." line and the following copyright line. @@ -13,11 +15,11 @@ sed \ -e "s/^Allocation context: stack of thread \([0-9]*\), offset -[0-9]*$/Allocation context: stack of thread \1, offset .../" \ -e "/^warning: evaluate_Dwarf3_Expr: unhandled DW_OP_.*/d" \ -e '/^warning: addVar:.*/d' \ --e 's/^Allocation context: Data section of ..tsan_unittest/Allocation context: BSS section of tsan_unittest/' \ +-e 's/^Allocation context: Data section of .\//Allocation context: BSS section of /' \ -e '/^run: \/usr\/bin\/dsymutil.*/d' \ -e "s/, in frame #[0-9]* of thread /, in frame #? of thread /" \ -e "s/(tc20_verifywrap.c:261)/(tc20_verifywrap.c:262)/" \ --e "/^Copyright (C) 2006-200., and GNU GPL'd, by Bart Van Assche.$/d" \ +-e "/^Copyright (C) 2006-201., and GNU GPL'd, by Bart Van Assche.$/d" \ -e "s/\([A-Za-z_]*\) (clone.S:[0-9]*)/\1 (in \/...libc...)/" \ -e "s/[A-Za-z_]* (pthread_create.c:[0-9]*)/(within libpthread-?.?.so)/" \ -e "s/[A-Za-z_]* (in [^ ]*libpthread-[0-9.]*\.so)/(within libpthread-?.?.so)/" \ diff --git a/drd/tests/fp_race.c b/drd/tests/fp_race.c index ad0168e..65d13a3 100644 --- a/drd/tests/fp_race.c +++ b/drd/tests/fp_race.c @@ -55,7 +55,7 @@ int main(int argc, char** argv) pthread_mutex_init(&s_mutex, 0); /* - * Switch to line-buffered mode, such that timing information can be + * Switch to line-buffered mode, such that timing information can be * obtained for each printf() call with strace. */ setlinebuf(stdout); diff --git a/drd/tests/matinv.c b/drd/tests/matinv.c index 7ef4cb7..a63649b 100644 --- a/drd/tests/matinv.c +++ b/drd/tests/matinv.c @@ -161,7 +161,7 @@ static elem_t* multiply_matrices(const elem_t* const a1, /** Apply the Gauss-Jordan elimination algorithm on the matrix p->a starting * at row r0 and up to but not including row r1. It is assumed that as many - * threads execute this function concurrently as the count barrier p->b was + * threads execute this function concurrently as the count barrier p->b was * initialized with. If the matrix p->a is nonsingular, and if matrix p->a * has at least as many columns as rows, the result of this algorithm is that * submatrix p->a[0..p->rows-1,0..p->rows-1] is the identity matrix. diff --git a/drd/tests/omp_matinv.c b/drd/tests/omp_matinv.c index 4678740..cd402ab 100644 --- a/drd/tests/omp_matinv.c +++ b/drd/tests/omp_matinv.c @@ -149,7 +149,7 @@ static elem_t* multiply_matrices(const elem_t* const a1, /** Apply the Gauss-Jordan elimination algorithm on the matrix p->a starting * at row r0 and up to but not including row r1. It is assumed that as many - * threads execute this function concurrently as the count barrier p->b was + * threads execute this function concurrently as the count barrier p->b was * initialized with. If the matrix p->a is nonsingular, and if matrix p->a * has at least as many columns as rows, the result of this algorithm is that * submatrix p->a[0..p->rows-1,0..p->rows-1] is the identity matrix. diff --git a/drd/tests/pth_broadcast.c b/drd/tests/pth_broadcast.c index a2ddcfd..5276a34 100644 --- a/drd/tests/pth_broadcast.c +++ b/drd/tests/pth_broadcast.c @@ -1,4 +1,4 @@ -/** Broadcast a (POSIX threads) signal to all running threads, where the +/** Broadcast a (POSIX threads) signal to all running threads, where the * number of threads can be specified on the command line. This test program * is intended not only to test the correctness of drd but also to test * whether performance does not degrade too much when the number of threads @@ -96,7 +96,7 @@ static void thread_func(struct cthread* thread_info) printf("thread %d [%d] (1)\n", thread_info->m_threadnum, i); } csema_v(thread_info->m_sema); - + // Wait until the main thread signals us via pthread_cond_broadcast(). pthread_cond_wait(&s_cond, &s_mutex); if (s_trace) diff --git a/drd/tests/pth_detached.c b/drd/tests/pth_detached.c index 18bbfeb..696cd4b 100644 --- a/drd/tests/pth_detached.c +++ b/drd/tests/pth_detached.c @@ -56,13 +56,13 @@ int main(int argc, char** argv) thread_arg[i] = i; pthread_mutex_init(&s_mutex, 0); - + pthread_attr_init(&attr); pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); assert(pthread_attr_getdetachstate(&attr, &detachstate) == 0); assert(detachstate == PTHREAD_CREATE_DETACHED); pthread_attr_setstacksize(&attr, 16384); - // Create count1 detached threads by setting the "detached" property via + // Create count1 detached threads by setting the "detached" property via // thread attributes. for (i = 0; i < count1; i++) { diff --git a/drd/tests/pth_detached_sem.c b/drd/tests/pth_detached_sem.c index 4d0223c..c91be67 100644 --- a/drd/tests/pth_detached_sem.c +++ b/drd/tests/pth_detached_sem.c @@ -51,13 +51,13 @@ int main(int argc, char** argv) thread_arg[i] = i; sem_init(&s_sem, 0, 0); - + pthread_attr_init(&attr); pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); assert(pthread_attr_getdetachstate(&attr, &detachstate) == 0); assert(detachstate == PTHREAD_CREATE_DETACHED); pthread_attr_setstacksize(&attr, 16384); - // Create count1 detached threads by setting the "detached" property via + // Create count1 detached threads by setting the "detached" property via // thread attributes. for (i = 0; i < count1; i++) { diff --git a/drd/tests/pth_inconsistent_cond_wait.c b/drd/tests/pth_inconsistent_cond_wait.c index f7501cc..618b540 100644 --- a/drd/tests/pth_inconsistent_cond_wait.c +++ b/drd/tests/pth_inconsistent_cond_wait.c @@ -13,7 +13,9 @@ #include // memset() #include // gettimeofday() #include // struct timespec +#include // O_CREAT #include +#include "../../config.h" #define PTH_CALL(expr) \ diff --git a/drd/tests/pth_uninitialized_cond.c b/drd/tests/pth_uninitialized_cond.c new file mode 100644 index 0000000..6acfbc7 --- /dev/null +++ b/drd/tests/pth_uninitialized_cond.c @@ -0,0 +1,28 @@ +/* Test program to verify whether DRD only complains about uninitialized + * condition variables for dynamically allocated memory. + */ + + +#include +#include + + +static pthread_cond_t s_cond1 = PTHREAD_COND_INITIALIZER; +static pthread_cond_t s_cond2 = PTHREAD_COND_INITIALIZER; + + +int main(int argc, char** argv) +{ + fprintf(stderr, "Statically initialized condition variable.\n"); + + pthread_cond_signal(&s_cond1); + + fprintf(stderr, "Uninitialized condition variable.\n"); + + *((char*)&s_cond2 + sizeof(s_cond2) - 1) ^= 1; + pthread_cond_signal(&s_cond2); + + fprintf(stderr, "Done.\n"); + + return 0; +} diff --git a/drd/tests/pth_uninitialized_cond.stderr.exp b/drd/tests/pth_uninitialized_cond.stderr.exp new file mode 100644 index 0000000..a693944 --- /dev/null +++ b/drd/tests/pth_uninitialized_cond.stderr.exp @@ -0,0 +1,10 @@ + +Statically initialized condition variable. +Uninitialized condition variable. +condition variable has not been initialized: cond 0x........ + at 0x........: pthread_cond_signal (drd_pthread_intercepts.c:?) + by 0x........: main (pth_uninitialized_cond.c:?) + +Done. + +ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0) diff --git a/drd/tests/pth_uninitialized_cond.vgtest b/drd/tests/pth_uninitialized_cond.vgtest new file mode 100644 index 0000000..fe03139 --- /dev/null +++ b/drd/tests/pth_uninitialized_cond.vgtest @@ -0,0 +1,3 @@ +prereq: test -e pth_uninitialized_cond && ./supported_libpthread +vgopts: --read-var-info=yes --check-stack-var=yes +prog: pth_uninitialized_cond diff --git a/drd/tests/qt4_atomic.cpp b/drd/tests/qt4_atomic.cpp new file mode 100644 index 0000000..b3b84f6 --- /dev/null +++ b/drd/tests/qt4_atomic.cpp @@ -0,0 +1,65 @@ +/// Test program that uses the QAtomicInt class. + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif + +#include "config.h" +#include // class QAtomicInt +#include +#include // fprintf() +#include // atoi() +#include +#include // pthread_barrier_t +#include + + +static pthread_barrier_t s_barrier; +static QAtomicInt* s_pAtomicInt; + + +void* thread_func(void* pArg) +{ + const int iArg = *reinterpret_cast(pArg); + + pthread_barrier_wait(&s_barrier); + + while (! s_pAtomicInt->testAndSetOrdered(iArg, iArg + 1)) + ; + + return NULL; +} + +int main(int argc, char** argv) +{ + int i; + const int n_threads = 10; + std::vector thread_arg(n_threads); + std::vector tid(n_threads); + + fprintf(stderr, "Start of test.\n"); + + pthread_barrier_init(&s_barrier, 0, n_threads); + s_pAtomicInt = new QAtomicInt(); + for (i = 0; i < n_threads; i++) + { + thread_arg[i] = i; + pthread_create(&tid[i], 0, thread_func, &thread_arg[i]); + } + for (i = 0; i < n_threads; i++) + { + pthread_join(tid[i], NULL); + } + pthread_barrier_destroy(&s_barrier); + + if (*s_pAtomicInt == n_threads) + fprintf(stderr, "Test successful.\n"); + else + fprintf(stderr, "Test failed: counter = %d, should be %d\n", + static_cast(*s_pAtomicInt), n_threads); + + delete s_pAtomicInt; + s_pAtomicInt = 0; + + return 0; +} diff --git a/drd/tests/qt4_atomic.stderr.exp b/drd/tests/qt4_atomic.stderr.exp new file mode 100644 index 0000000..21dba22 --- /dev/null +++ b/drd/tests/qt4_atomic.stderr.exp @@ -0,0 +1,5 @@ + +Start of test. +Test successful. + +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/drd/tests/qt4_atomic.vgtest b/drd/tests/qt4_atomic.vgtest new file mode 100644 index 0000000..a35435a --- /dev/null +++ b/drd/tests/qt4_atomic.vgtest @@ -0,0 +1,3 @@ +prereq: test -e qt4_atomic +vgopts: --check-stack-var=yes +prog: qt4_atomic diff --git a/drd/tests/read_after_free.c b/drd/tests/read_after_free.c new file mode 100644 index 0000000..1319cb2 --- /dev/null +++ b/drd/tests/read_after_free.c @@ -0,0 +1,45 @@ +#define _GNU_SOURCE 1 + +#include +#include +#include +#include + +static char* s_mem; +static volatile int s_freed; + +static void* thread_func(void* arg) +{ + // Busy-wait until pthread_create() has finished. + while (s_freed == 0) + pthread_yield(); + free(s_mem); + __sync_add_and_fetch(&s_freed, 1); + return NULL; +} + +int main(int argc, char** argv) +{ + pthread_t tid; + int quiet; + char result; + + quiet = argc > 1; + + s_mem = malloc(10); + if (!quiet) + fprintf(stderr, "Pointer to allocated memory: %p\n", s_mem); + assert(s_mem); + pthread_create(&tid, NULL, thread_func, NULL); + __sync_add_and_fetch(&s_freed, 1); + // Busy-wait until the memory has been freed. + while (s_freed == 1) + pthread_yield(); + // Read-after-free. + result = s_mem[0]; + if (!quiet) + fprintf(stderr, "Read-after-free result: %d\n", result); + pthread_join(tid, NULL); + fprintf(stderr, "Done.\n"); + return 0; +} diff --git a/drd/tests/read_after_free.stderr.exp b/drd/tests/read_after_free.stderr.exp new file mode 100644 index 0000000..7463c72 --- /dev/null +++ b/drd/tests/read_after_free.stderr.exp @@ -0,0 +1,8 @@ + +Conflicting load by thread 1 at 0x........ size 1 + at 0x........: main (read_after_free.c:?) +Allocation context: unknown. + +Done. + +ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0) diff --git a/drd/tests/read_after_free.vgtest b/drd/tests/read_after_free.vgtest new file mode 100644 index 0000000..c8b1c2b --- /dev/null +++ b/drd/tests/read_after_free.vgtest @@ -0,0 +1,4 @@ +prereq: test -e read_after_free && ./supported_libpthread +vgopts: --read-var-info=yes --check-stack-var=yes --free-is-write=yes --show-confl-seg=no +prog: read_after_free +args: -q diff --git a/drd/tests/rwlock_type_checking.stderr.exp b/drd/tests/rwlock_type_checking.stderr.exp index c1ee6db..b3d2dc9 100644 --- a/drd/tests/rwlock_type_checking.stderr.exp +++ b/drd/tests/rwlock_type_checking.stderr.exp @@ -3,12 +3,10 @@ Attempt to use a user-defined rwlock as a POSIX rwlock: rwlock 0x......... at 0x........: pthread_rwlock_init (drd_pthread_intercepts.c:?) by 0x........: main (rwlock_type_checking.c:?) rwlock 0x........ was first observed at: - at 0x........: vgDrdCl_annotate_rwlock_create (drd.h:?) - by 0x........: main (rwlock_type_checking.c:?) + at 0x........: main (rwlock_type_checking.c:?) Attempt to use a POSIX rwlock as a user-defined rwlock: rwlock 0x......... - at 0x........: vgDrdCl_annotate_rwlock_released (drd.h:?) - by 0x........: main (rwlock_type_checking.c:?) + at 0x........: main (rwlock_type_checking.c:?) rwlock 0x........ was first observed at: at 0x........: pthread_rwlock_init (drd_pthread_intercepts.c:?) by 0x........: main (rwlock_type_checking.c:?) diff --git a/drd/tests/sem_as_mutex.c b/drd/tests/sem_as_mutex.c index 1fb79f2..5a8cb13 100644 --- a/drd/tests/sem_as_mutex.c +++ b/drd/tests/sem_as_mutex.c @@ -56,7 +56,7 @@ int main(int argc, char** argv) sem_init(&s_sem, 0, 1); /* - * Switch to line-buffered mode, such that timing information can be + * Switch to line-buffered mode, such that timing information can be * obtained for each printf() call with strace. */ setlinebuf(stdout); diff --git a/drd/tests/sem_open.c b/drd/tests/sem_open.c index 1960704..d452009 100644 --- a/drd/tests/sem_open.c +++ b/drd/tests/sem_open.c @@ -68,7 +68,7 @@ int main(int argc, char** argv) } /* - * Switch to line-buffered mode, such that timing information can be + * Switch to line-buffered mode, such that timing information can be * obtained for each printf() call with strace. */ setlinebuf(stdout); diff --git a/drd/tests/sigaltstack.stderr.exp b/drd/tests/sigaltstack.stderr.exp new file mode 100644 index 0000000..b95833f --- /dev/null +++ b/drd/tests/sigaltstack.stderr.exp @@ -0,0 +1,6 @@ +calling sigaltstack, stack base is 0x........ +setting sigaction +res = 0 +raising the signal +caught signal, local var is on 0x........ +done diff --git a/drd/tests/sigaltstack.vgtest b/drd/tests/sigaltstack.vgtest new file mode 100644 index 0000000..a079d60 --- /dev/null +++ b/drd/tests/sigaltstack.vgtest @@ -0,0 +1,2 @@ +prog: ../../memcheck/tests/sigaltstack +vgopts: -q diff --git a/drd/tests/tc23_bogus_condwait.stderr.exp-linux-ppc b/drd/tests/tc23_bogus_condwait.stderr.exp-linux-ppc index d6f9885..3854362 100644 --- a/drd/tests/tc23_bogus_condwait.stderr.exp-linux-ppc +++ b/drd/tests/tc23_bogus_condwait.stderr.exp-linux-ppc @@ -8,6 +8,6 @@ Process terminating with default action of signal 7 (SIGBUS) Invalid address alignment at address 0x........ at 0x........: (within libpthread-?.?.so) by 0x........: pthread_cond_wait@@GLIBC_2.3.2(within libpthread-?.?.so) - by 0x........: main (tc23_bogus_condwait.c:69) + by 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?) ERROR SUMMARY: 2 errors from 1 contexts (suppressed: 0 from 0) diff --git a/drd/tests/tsan_thread_wrappers_pthread.h b/drd/tests/tsan_thread_wrappers_pthread.h index 81e3b31..cfb9b3c 100644 --- a/drd/tests/tsan_thread_wrappers_pthread.h +++ b/drd/tests/tsan_thread_wrappers_pthread.h @@ -3,7 +3,7 @@ framework. Copyright (C) 2008-2008 Google Inc - opensource@google.com + opensource@google.com This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -23,22 +23,22 @@ The GNU General Public License is contained in the file COPYING. */ -// Author: Konstantin Serebryany +// Author: Konstantin Serebryany // -// Here we define few simple classes that wrap pthread primitives. +// Here we define few simple classes that wrap pthread primitives. // -// We need this to create unit tests for helgrind (or similar tool) -// that will work with different threading frameworks. +// We need this to create unit tests for helgrind (or similar tool) +// that will work with different threading frameworks. // -// If one needs to test helgrind's support for another threading library, -// he/she can create a copy of this file and replace pthread_ calls -// with appropriate calls to his/her library. +// If one needs to test helgrind's support for another threading library, +// he/she can create a copy of this file and replace pthread_ calls +// with appropriate calls to his/her library. // -// Note, that some of the methods defined here are annotated with -// ANNOTATE_* macros defined in dynamic_annotations.h. +// Note, that some of the methods defined here are annotated with +// ANNOTATE_* macros defined in dynamic_annotations.h. // -// DISCLAIMER: the classes defined in this header file -// are NOT intended for general use -- only for unit tests. +// DISCLAIMER: the classes defined in this header file +// are NOT intended for general use -- only for unit tests. // #ifndef THREAD_WRAPPERS_PTHREAD_H @@ -65,29 +65,30 @@ using namespace std; #include "../../drd/drd.h" #define ANNOTATE_NO_OP(arg) do { } while(0) -#define ANNOTATE_EXPECT_RACE(addr, descr) DRDCL_(ignore_range)(addr, 4) +#define ANNOTATE_EXPECT_RACE(addr, descr) \ + ANNOTATE_BENIGN_RACE_SIZED(addr, 4, "expected race") static inline bool RunningOnValgrind() { return RUNNING_ON_VALGRIND; } #include #ifdef NDEBUG # error "Pleeease, do not define NDEBUG" -#endif +#endif #define CHECK assert /// Set this to true if malloc() uses mutex on your platform as this may /// introduce a happens-before arc for a pure happens-before race detector. const bool kMallocUsesMutex = false; -/// Current time in milliseconds. +/// Current time in milliseconds. static inline int64_t GetCurrentTimeMillis() { struct timeval now; gettimeofday(&now, NULL); return now.tv_sec * 1000 + now.tv_usec / 1000; } -/// Copy tv to ts adding offset in milliseconds. -static inline void timeval2timespec(timeval *const tv, - timespec *ts, +/// Copy tv to ts adding offset in milliseconds. +static inline void timeval2timespec(timeval *const tv, + timespec *ts, int64_t offset_milli) { const int64_t ten_9 = 1000000000LL; const int64_t ten_6 = 1000000LL; @@ -154,16 +155,16 @@ class SpinLock { #endif // NO_SPINLOCK -/// Just a boolean condition. Used by Mutex::LockWhen and similar. +/// Just a boolean condition. Used by Mutex::LockWhen and similar. class Condition { public: typedef bool (*func_t)(void*); template - Condition(bool (*func)(T*), T* arg) + Condition(bool (*func)(T*), T* arg) : func_(reinterpret_cast(func)), arg_(arg) {} - Condition(bool (*func)()) + Condition(bool (*func)()) : func_(reinterpret_cast(func)), arg_(NULL) {} bool Eval() { return func_(arg_); } @@ -176,22 +177,22 @@ class Condition { /// Wrapper for pthread_mutex_t. /// -/// pthread_mutex_t is *not* a reader-writer lock, -/// so the methods like ReaderLock() aren't really reader locks. -/// We can not use pthread_rwlock_t because it +/// pthread_mutex_t is *not* a reader-writer lock, +/// so the methods like ReaderLock() aren't really reader locks. +/// We can not use pthread_rwlock_t because it /// does not work with pthread_cond_t. -/// -/// TODO: We still need to test reader locks with this class. -/// Implement a mode where pthread_rwlock_t will be used -/// instead of pthread_mutex_t (only when not used with CondVar or LockWhen). -/// +/// +/// TODO: We still need to test reader locks with this class. +/// Implement a mode where pthread_rwlock_t will be used +/// instead of pthread_mutex_t (only when not used with CondVar or LockWhen). +/// class Mutex { friend class CondVar; - public: + public: Mutex() { CHECK(0 == pthread_mutex_init(&mu_, NULL)); CHECK(0 == pthread_cond_init(&cv_, NULL)); - signal_at_unlock_ = true; // Always signal at Unlock to make + signal_at_unlock_ = true; // Always signal at Unlock to make // Mutex more friendly to hybrid detectors. } ~Mutex() { @@ -202,7 +203,7 @@ class Mutex { bool TryLock() { return (0 == pthread_mutex_trylock(&mu_));} void Unlock() { if (signal_at_unlock_) { - CHECK(0 == pthread_cond_signal(&cv_)); + CHECK(0 == pthread_cond_signal(&cv_)); } CHECK(0 == pthread_mutex_unlock(&mu_)); } @@ -214,11 +215,11 @@ class Mutex { void ReaderLockWhen(Condition cond) { Lock(); WaitLoop(cond); } void Await(Condition cond) { WaitLoop(cond); } - bool ReaderLockWhenWithTimeout(Condition cond, int millis) + bool ReaderLockWhenWithTimeout(Condition cond, int millis) { Lock(); return WaitLoopWithTimeout(cond, millis); } - bool LockWhenWithTimeout(Condition cond, int millis) + bool LockWhenWithTimeout(Condition cond, int millis) { Lock(); return WaitLoopWithTimeout(cond, millis); } - bool AwaitWithTimeout(Condition cond, int millis) + bool AwaitWithTimeout(Condition cond, int millis) { return WaitLoopWithTimeout(cond, millis); } private: @@ -248,10 +249,10 @@ class Mutex { return cond.Eval(); } - // A hack. cv_ should be the first data member so that - // ANNOTATE_CONDVAR_WAIT(&MU, &MU) and ANNOTATE_CONDVAR_SIGNAL(&MU) works. + // A hack. cv_ should be the first data member so that + // ANNOTATE_CONDVAR_WAIT(&MU, &MU) and ANNOTATE_CONDVAR_SIGNAL(&MU) works. // (See also racecheck_unittest.cc) - pthread_cond_t cv_; + pthread_cond_t cv_; pthread_mutex_t mu_; bool signal_at_unlock_; // Set to true if Wait was called. }; @@ -259,7 +260,7 @@ class Mutex { class MutexLock { // Scoped Mutex Locker/Unlocker public: - MutexLock(Mutex *mu) + MutexLock(Mutex *mu) : mu_(mu) { mu_->Lock(); } @@ -271,13 +272,13 @@ class MutexLock { // Scoped Mutex Locker/Unlocker }; -/// Wrapper for pthread_cond_t. +/// Wrapper for pthread_cond_t. class CondVar { public: CondVar() { CHECK(0 == pthread_cond_init(&cv_, NULL)); } ~CondVar() { CHECK(0 == pthread_cond_destroy(&cv_)); } void Wait(Mutex *mu) { CHECK(0 == pthread_cond_wait(&cv_, &mu->mu_)); } - bool WaitWithTimeout(Mutex *mu, int millis) { + bool WaitWithTimeout(Mutex *mu, int millis) { struct timeval now; struct timespec timeout; gettimeofday(&now, NULL); @@ -293,7 +294,7 @@ class CondVar { // pthreads do not allow to use condvar with rwlock so we can't make // ReaderLock method of Mutex to be the real rw-lock. -// So, we need a special lock class to test reader locks. +// So, we need a special lock class to test reader locks. #define NEEDS_SEPERATE_RW_LOCK class RWLock { public: @@ -310,7 +311,7 @@ class RWLock { class ReaderLockScoped { // Scoped RWLock Locker/Unlocker public: - ReaderLockScoped(RWLock *mu) + ReaderLockScoped(RWLock *mu) : mu_(mu) { mu_->ReaderLock(); } @@ -323,7 +324,7 @@ class ReaderLockScoped { // Scoped RWLock Locker/Unlocker class WriterLockScoped { // Scoped RWLock Locker/Unlocker public: - WriterLockScoped(RWLock *mu) + WriterLockScoped(RWLock *mu) : mu_(mu) { mu_->Lock(); } @@ -339,14 +340,14 @@ class WriterLockScoped { // Scoped RWLock Locker/Unlocker /// Wrapper for pthread_create()/pthread_join(). class MyThread { - public: + public: typedef void *(*worker_t)(void*); - MyThread(worker_t worker, void *arg = NULL, const char *name = NULL) + MyThread(worker_t worker, void *arg = NULL, const char *name = NULL) :w_(worker), arg_(arg), name_(name) {} - MyThread(void (*worker)(void), void *arg = NULL, const char *name = NULL) + MyThread(void (*worker)(void), void *arg = NULL, const char *name = NULL) :w_(reinterpret_cast(worker)), arg_(arg), name_(name) {} - MyThread(void (*worker)(void *), void *arg = NULL, const char *name = NULL) + MyThread(void (*worker)(void *), void *arg = NULL, const char *name = NULL) :w_(reinterpret_cast(worker)), arg_(arg), name_(name) {} ~MyThread(){ w_ = NULL; arg_ = NULL;} @@ -378,7 +379,7 @@ class ProducerConsumerQueue { //ANNOTATE_PCQ_DESTROY(this); } - // Put. + // Put. void Put(void *item) { mu_.Lock(); q_.push(item); @@ -387,18 +388,18 @@ class ProducerConsumerQueue { mu_.Unlock(); } - // Get. - // Blocks if the queue is empty. - void *Get() { + // Get. + // Blocks if the queue is empty. + void *Get() { mu_.LockWhen(Condition(IsQueueNotEmpty, &q_)); void * item = NULL; bool ok = TryGetInternal(&item); - CHECK(ok); + CHECK(ok); mu_.Unlock(); return item; } - // If queue is not empty, + // If queue is not empty, // remove an element from queue, put it into *res and return true. // Otherwise return false. bool TryGet(void **res) { @@ -411,9 +412,9 @@ class ProducerConsumerQueue { private: Mutex mu_; std::queue q_; // protected by mu_ - + // Requires mu_ - bool TryGetInternal(void ** item_ptr) { + bool TryGetInternal(void ** item_ptr) { if (q_.empty()) return false; *item_ptr = q_.front(); @@ -421,7 +422,7 @@ class ProducerConsumerQueue { //ANNOTATE_PCQ_GET(this); return true; } - + static bool IsQueueNotEmpty(std::queue * queue) { return !queue->empty(); } @@ -429,15 +430,15 @@ class ProducerConsumerQueue { -/// Function pointer with zero, one or two parameters. +/// Function pointer with zero, one or two parameters. struct Closure { typedef void (*F0)(); typedef void (*F1)(void *arg1); typedef void (*F2)(void *arg1, void *arg2); - int n_params; - void *f; - void *param1; - void *param2; + int n_params; + void *f; + void *param1; + void *param2; void Execute() { if (n_params == 0) { @@ -450,7 +451,7 @@ struct Closure { } delete this; } -}; +}; Closure *NewCallback(void (*f)()) { Closure *res = new Closure; @@ -483,24 +484,24 @@ Closure *NewCallback(void (*f)(P1, P2), P1 p1, P2 p2) { return res; } -/*! A thread pool that uses ProducerConsumerQueue. - Usage: +/*! A thread pool that uses ProducerConsumerQueue. + Usage: { ThreadPool pool(n_workers); pool.StartWorkers(); pool.Add(NewCallback(func_with_no_args)); pool.Add(NewCallback(func_with_one_arg, arg)); pool.Add(NewCallback(func_with_two_args, arg1, arg2)); - ... // more calls to pool.Add() - - // the ~ThreadPool() is called: we wait workers to finish - // and then join all threads in the pool. + ... // more calls to pool.Add() + + // the ~ThreadPool() is called: we wait workers to finish + // and then join all threads in the pool. } */ class ThreadPool { - public: - //! Create n_threads threads, but do not start. - explicit ThreadPool(int n_threads) + public: + //! Create n_threads threads, but do not start. + explicit ThreadPool(int n_threads) : queue_(INT_MAX) { for (int i = 0; i < n_threads; i++) { MyThread *thread = new MyThread(&ThreadPool::Worker, this); @@ -508,14 +509,14 @@ class ThreadPool { } } - //! Start all threads. + //! Start all threads. void StartWorkers() { for (size_t i = 0; i < workers_.size(); i++) { workers_[i]->Start(); } } - //! Add a closure. + //! Add a closure. void Add(Closure *closure) { queue_.Put(closure); } @@ -541,22 +542,22 @@ class ThreadPool { while (true) { Closure *closure = reinterpret_cast(pool->queue_.Get()); if(closure == NULL) { - return NULL; + return NULL; } - closure->Execute(); + closure->Execute(); } } }; #ifndef NO_BARRIER -/// Wrapper for pthread_barrier_t. +/// Wrapper for pthread_barrier_t. class Barrier{ public: explicit Barrier(int n_threads) {CHECK(0 == pthread_barrier_init(&b_, 0, n_threads));} ~Barrier() {CHECK(0 == pthread_barrier_destroy(&b_));} void Block() { // helgrind 3.3.0 does not have an interceptor for barrier. - // but our current local version does. + // but our current local version does. // ANNOTATE_CONDVAR_SIGNAL(this); pthread_barrier_wait(&b_); // ANNOTATE_CONDVAR_WAIT(this, this); diff --git a/drd/tests/tsan_unittest.cpp b/drd/tests/tsan_unittest.cpp index eb45621..6ba123d 100644 --- a/drd/tests/tsan_unittest.cpp +++ b/drd/tests/tsan_unittest.cpp @@ -6620,8 +6620,8 @@ void Getter() { } usleep(1000); } - printf("T=%d: non_zero_received=%d\n", - (int)pthread_self(), non_zero_received); + printf("T=%zd: non_zero_received=%d\n", + (size_t)pthread_self(), non_zero_received); } void Run() { diff --git a/drd/tests/unified_annotations.h b/drd/tests/unified_annotations.h new file mode 100644 index 0000000..13259d6 --- /dev/null +++ b/drd/tests/unified_annotations.h @@ -0,0 +1,70 @@ +#ifndef _UNIFIED_ANNOTATIONS_H_ +#define _UNIFIED_ANNOTATIONS_H_ + + +#include "../../drd/drd.h" + + +/* + * Define annotation macros such that these can be intercepted by DRD, Helgrind + * and ThreadSanitizer. See also + * http://code.google.com/p/data-race-test/source/browse/trunk/dynamic_annotations/dynamic_annotations.h + */ +#define U_ANNOTATE_NEW_MEMORY(addr, size) ANNOTATE_NEW_MEMORY(addr, size) +#define U_ANNOTATE_HAPPENS_BEFORE(addr) U_AnnotateHappensBefore(addr) +#define U_ANNOTATE_HAPPENS_AFTER(addr) U_AnnotateHappensAfter(addr) +#define U_ANNOTATE_HAPPENS_DONE(addr) \ + do { \ + ANNOTATE_HAPPENS_DONE(addr); \ + } while(0) + + +#ifdef __cplusplus +extern "C" { +#endif +#if 0 +} +#endif + + +void __attribute__((weak,noinline)) +AnnotateCondVarSignal(const char *file, int line, const volatile void *cv) +{ + asm(""); +} + +void __attribute__((weak,noinline)) +AnnotateCondVarWait(const char *file, int line, const volatile void *cv, + const volatile void *lock) +{ + asm(""); +} + +static __inline__ void U_AnnotateHappensBefore(void* addr) +{ + ANNOTATE_HAPPENS_BEFORE(addr); + AnnotateCondVarSignal(__FILE__, __LINE__, addr); +} + +static __inline__ void U_AnnotateHappensAfter(void *addr) +{ + ANNOTATE_HAPPENS_AFTER(addr); + AnnotateCondVarWait(__FILE__, __LINE__, addr, NULL); +} + + +#if 0 +{ +#endif +#ifdef __cplusplus +} +#endif + + +#endif /* _UNIFIED_ANNOTATIONS_H_ */ + +/* + * Local variables: + * c-basic-offset: 2 + * End: + */ diff --git a/drd/tests/unit_bitmap.c b/drd/tests/unit_bitmap.c index 280943c..236cf06 100644 --- a/drd/tests/unit_bitmap.c +++ b/drd/tests/unit_bitmap.c @@ -63,6 +63,7 @@ static int s_verbose = 1; static struct { Addr address; SizeT size; BmAccessTypeT access_type; } s_test1_args[] = { + { 0, 0, eLoad }, { 0, 1, eLoad }, { 666, 4, eLoad }, { 667, 2, eStore }, diff --git a/exp-bbv/Makefile.am b/exp-bbv/Makefile.am index aa7f40b..78d9e53 100644 --- a/exp-bbv/Makefile.am +++ b/exp-bbv/Makefile.am @@ -13,7 +13,8 @@ endif BBV_SOURCES_COMMON = bbv_main.c -exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(BBV_SOURCES_COMMON) +exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ + $(BBV_SOURCES_COMMON) exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \ @@ -24,8 +25,16 @@ exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC -exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(BBV_SOURCES_COMMON) +exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ + $(BBV_SOURCES_COMMON) exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \ @@ -36,4 +45,10 @@ exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif diff --git a/exp-bbv/bbv_main.c b/exp-bbv/bbv_main.c index 7629bf8..34020e0 100644 --- a/exp-bbv/bbv_main.c +++ b/exp-bbv/bbv_main.c @@ -6,10 +6,10 @@ This file is part of BBV, a Valgrind tool for generating SimPoint basic block vectors. - Copyright (C) 2006-2009 Vince Weaver + Copyright (C) 2006-2010 Vince Weaver vince _at_ csl.cornell.edu - pcfile code is Copyright (C) 2006-2009 Oriol Prat + pcfile code is Copyright (C) 2006-2010 Oriol Prat oriol.prat _at _ bsc.es This program is free software; you can redistribute it and/or @@ -607,7 +607,7 @@ static void bbv_pre_clo_init(void) VG_(details_version) (NULL); VG_(details_description) ("a SimPoint basic block vector generator"); VG_(details_copyright_author)( - "Copyright (C) 2006-2009 Vince Weaver"); + "Copyright (C) 2006-2010 Vince Weaver"); VG_(details_bug_reports_to) (VG_BUGS_TO); VG_(basic_tool_funcs) (bbv_post_clo_init, diff --git a/exp-bbv/tests/Makefile.am b/exp-bbv/tests/Makefile.am index 1a5b526..359ba22 100644 --- a/exp-bbv/tests/Makefile.am +++ b/exp-bbv/tests/Makefile.am @@ -16,8 +16,11 @@ endif if VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX SUBDIRS += ppc32-linux endif +if VGCONF_PLATFORMS_INCLUDE_ARM_LINUX +SUBDIRS += arm-linux +endif -DIST_SUBDIRS = x86 x86-linux amd64-linux ppc32-linux . +DIST_SUBDIRS = x86 x86-linux amd64-linux ppc32-linux arm-linux . dist_noinst_SCRIPTS = \ filter_bb \ diff --git a/exp-bbv/tests/arm-linux/Makefile.am b/exp-bbv/tests/arm-linux/Makefile.am new file mode 100644 index 0000000..d022cf7 --- /dev/null +++ b/exp-bbv/tests/arm-linux/Makefile.am @@ -0,0 +1,22 @@ +include $(top_srcdir)/Makefile.tool-tests.am + +dist_noinst_SCRIPTS = filter_stderr + +check_PROGRAMS = \ + million ll + +EXTRA_DIST = \ + ll.stderr.exp \ + ll.stdout.exp \ + ll.post.exp \ + ll.vgtest \ + million.stderr.exp \ + million.post.exp \ + million.vgtest + +AM_CCASFLAGS += -ffreestanding + +LDFLAGS += -nostartfiles -nodefaultlibs + +ll_SOURCES = ll.S +million_SOURCES = million.S diff --git a/exp-bbv/tests/arm-linux/filter_stderr b/exp-bbv/tests/arm-linux/filter_stderr new file mode 100755 index 0000000..1c07666 --- /dev/null +++ b/exp-bbv/tests/arm-linux/filter_stderr @@ -0,0 +1,5 @@ +#! /bin/sh + +../filter_stderr + + diff --git a/exp-bbv/tests/arm-linux/ll.S b/exp-bbv/tests/arm-linux/ll.S new file mode 100644 index 0000000..0fd896a --- /dev/null +++ b/exp-bbv/tests/arm-linux/ll.S @@ -0,0 +1,493 @@ +# +# linux_logo in ARM assembly language +# based on the code from ll_asm-0.41 +# +# By Vince Weaver +# +# Modified to remove non-deterministic system calls +# And to avoid reading from /proc + +.include "../logo.include" + +# offsets into the results returned by the uname syscall +.equ U_SYSNAME,0 +.equ U_NODENAME,65 +.equ U_RELEASE,65*2 +.equ U_VERSION,(65*3) +.equ U_MACHINE,(65*4) +.equ U_DOMAINNAME,65*5 + +# offset into the results returned by the sysinfo syscall +.equ S_TOTALRAM,16 + +# Sycscalls +.equ SYSCALL_EXIT, 1 +.equ SYSCALL_WRITE, 4 + +# +.equ STDIN,0 +.equ STDOUT,1 +.equ STDERR,2 + + .globl _start +_start: + ldr r11,data_addr + ldr r12,bss_addr + + #========================= + # PRINT LOGO + #========================= + +# LZSS decompression algorithm implementation +# by Stephan Walter 2002, based on LZSS.C by Haruhiko Okumura 1989 +# optimized some more by Vince Weaver + + ldr r1,out_addr @ buffer we are printing to + + mov r2,#(N-F) @ R + + add r3,r11,#(logo-data_begin) + @ r3 points to logo data + ldr r8,logo_end_addr + @ r8 points to logo end + ldr r9,text_addr @ r9 points to text buf + +decompression_loop: + ldrb r4,[r3],#+1 @ load a byte, increment pointer + + mov r5,#0xff @ load top as a hackish 8-bit counter + orr r5,r4,r5,LSL #8 @ shift 0xff left by 8 and or in the byte we loaded + +test_flags: + cmp r3,r8 @ have we reached the end? + bge done_logo @ if so, exit + + lsrs r5,#1 @ shift bottom bit into carry flag + bcs discrete_char @ if set, we jump to discrete char + +offset_length: + ldrb r0,[r3],#+1 @ load a byte, increment pointer + ldrb r4,[r3],#+1 @ load a byte, increment pointer + @ we can't load halfword as no unaligned loads on arm + + orr r4,r0,r4,LSL #8 @ merge back into 16 bits + @ this has match_length and match_position + + mov r7,r4 @ copy r4 to r7 + @ no need to mask r7, as we do it + @ by default in output_loop + + mov r0,#(THRESHOLD+1) + add r6,r0,r4,LSR #(P_BITS) + @ r6 = (r4 >> P_BITS) + THRESHOLD + 1 + @ (=match_length) + +output_loop: + ldr r0,pos_mask @ urgh, can't handle simple constants + and r7,r7,r0 @ mask it + ldrb r4,[r9,r7] @ load byte from text_buf[] + add r7,r7,#1 @ advance pointer in text_buf + +store_byte: + strb r4,[r1],#+1 @ store a byte, increment pointer + strb r4,[r9,r2] @ store a byte to text_buf[r] + add r2,r2,#1 @ r++ + mov r0,#(N) + sub r0,r0,#1 @ grrr no way to get this easier + and r2,r2,r0 @ mask r + + subs r6,r6,#1 @ decement count + bne output_loop @ repeat until k>j + + tst r5,#0xff00 @ are the top bits 0? + bne test_flags @ if not, re-load flags + + b decompression_loop + +discrete_char: + ldrb r4,[r3],#+1 @ load a byte, increment pointer + mov r6,#1 @ we set r6 to one so byte + @ will be output once + + b store_byte @ and store it + + +# end of LZSS code + +done_logo: + ldr r1,out_addr @ buffer we are printing to + + bl write_stdout @ print the logo + + #========================== + # PRINT VERSION + #========================== +first_line: + + mov r0,#0 + add r1,r11,#(uname_info-data_begin) + @ os-name from uname "Linux" + + ldr r10,out_addr @ point r10 to out_buffer + + bl strcat @ call strcat + + + add r1,r11,#(ver_string-data_begin) @ source is " Version " + bl strcat @ call strcat + + add r1,r11,#((uname_info-data_begin)+U_RELEASE) + @ version from uname, ie "2.6.20" + bl strcat @ call strcat + + add r1,r11,#(compiled_string-data_begin) + @ source is ", Compiled " + bl strcat @ call strcat + + add r1,r11,#((uname_info-data_begin)+U_VERSION) + @ compiled date + bl strcat @ call strcat + + mov r3,#0xa + strb r3,[r10],#+1 @ store a linefeed, increment pointer + strb r0,[r10],#+1 @ NUL terminate, increment pointer + + bl center_and_print @ center and print + + @=============================== + @ Middle-Line + @=============================== +middle_line: + @========= + @ Load /proc/cpuinfo into buffer + @========= + + ldr r10,out_addr @ point r10 to out_buffer + + @============= + @ Number of CPUs + @============= +number_of_cpus: + + add r1,r11,#(one-data_begin) + # cheat. Who has an SMP arm? + bl strcat + + @========= + @ MHz + @========= +print_mhz: + + @ the arm system I have does not report MHz + + @========= + @ Chip Name + @========= +chip_name: + mov r0,#'s' + mov r1,#'o' + mov r2,#'r' + mov r3,#' ' + bl find_string + @ find 'sor\t: ' and grab up to ' ' + + add r1,r11,#(processor-data_begin) + @ print " Processor, " + bl strcat + + @======== + @ RAM + @======== + + + ldr r3,[r11,#((sysinfo_buff-data_begin)+S_TOTALRAM)] + @ size in bytes of RAM + movs r3,r3,lsr #20 @ divide by 1024*1024 to get M + adc r3,r3,#0 @ round + + mov r0,#1 + bl num_to_ascii + + add r1,r11,#(ram_comma-data_begin) + @ print 'M RAM, ' + bl strcat @ call strcat + + + @======== + @ Bogomips + @======== + + mov r0,#'I' + mov r1,#'P' + mov r2,#'S' + mov r3,#'\n' + bl find_string + + add r1,r11,#(bogo_total-data_begin) + bl strcat @ print bogomips total + + bl center_and_print @ center and print + + #================================= + # Print Host Name + #================================= +last_line: + ldr r10,out_addr @ point r10 to out_buffer + + add r1,r11,#((uname_info-data_begin)+U_NODENAME) + @ host name from uname() + bl strcat @ call strcat + + bl center_and_print @ center and print + + add r1,r11,#(default_colors-data_begin) + @ restore colors, print a few linefeeds + bl write_stdout + + + @================================ + @ Exit + @================================ +exit: + mov r0,#0 @ result is zero + mov r7,#SYSCALL_EXIT + swi 0x0 @ and exit + + + @================================= + @ FIND_STRING + @================================= + @ r0,r1,r2 = string to find + @ r3 = char to end at + @ r5 trashed +find_string: + ldr r7,disk_addr @ look in cpuinfo buffer +find_loop: + ldrb r5,[r7],#+1 @ load a byte, increment pointer + cmp r5,r0 @ compare against first byte + ldrb r5,[r7] @ load next byte + cmpeq r5,r1 @ if first byte matched, comp this one + ldrb r5,[r7,#+1] @ load next byte + cmpeq r5,r2 @ if first two matched, comp this one + beq find_colon @ if all 3 matched, we are found + + cmp r5,#0 @ are we at EOF? + beq done @ if so, done + + b find_loop + +find_colon: + ldrb r5,[r7],#+1 @ load a byte, increment pointer + cmp r5,#':' + bne find_colon @ repeat till we find colon + + add r7,r7,#1 @ skip the space + +store_loop: + ldrb r5,[r7],#+1 @ load a byte, increment pointer + strb r5,[r10],#+1 @ store a byte, increment pointer + cmp r5,r3 + bne store_loop + +almost_done: + mov r0,#0 + strb r0,[r10],#-1 @ replace last value with NUL + +done: + bx r14 @ return + + #================================ + # strcat + #================================ + # value to cat in r1 + # output buffer in r10 + # r3 trashed +strcat: + ldrb r3,[r1],#+1 @ load a byte, increment pointer + strb r3,[r10],#+1 @ store a byte, increment pointer + cmp r3,#0 @ is it zero? + bne strcat @ if not loop + sub r10,r10,#1 @ point to one less than null + bx r14 @ return + + + #============================== + # center_and_print + #============================== + # string to center in at output_buffer + +center_and_print: + + stmfd SP!,{LR} @ store return address on stack + + add r1,r11,#(escape-data_begin) + @ we want to output ^[[ + bl write_stdout + +str_loop2: + ldr r2,out_addr @ point r2 to out_buffer + sub r2,r10,r2 @ get length by subtracting + + rsb r2,r2,#81 @ reverse subtract! r2=81-r2 + @ we use 81 to not count ending \n + + bne done_center @ if result negative, don't center + + lsrs r3,r2,#1 @ divide by 2 + adc r3,r3,#0 @ round? + + mov r0,#0 @ print to stdout + bl num_to_ascii @ print number of spaces + + add r1,r11,#(C-data_begin) + @ we want to output C + bl write_stdout + +done_center: + ldr r1,out_addr @ point r1 to out_buffer + ldmfd SP!,{LR} @ restore return address from stack + + #================================ + # WRITE_STDOUT + #================================ + # r1 has string + # r0,r2,r3 trashed +write_stdout: + mov r2,#0 @ clear count + +str_loop1: + add r2,r2,#1 + ldrb r3,[r1,r2] + cmp r3,#0 + bne str_loop1 @ repeat till zero + +write_stdout_we_know_size: + mov r0,#STDOUT @ print to stdout + mov r7,#SYSCALL_WRITE + swi 0x0 @ run the syscall + bx r14 @ return + + + @############################# + @ num_to_ascii + @############################# + @ r3 = value to print + @ r0 = 0=stdout, 1=strcat + +num_to_ascii: + stmfd SP!,{r10,LR} @ store return address on stack + add r10,r12,#((ascii_buffer-bss_begin)) + add r10,r10,#10 + @ point to end of our buffer + + mov r4,#10 @ we'll be dividing by 10 +div_by_10: + bl divide @ Q=r7,$0, R=r8,$1 + add r8,r8,#0x30 @ convert to ascii + strb r8,[r10],#-1 @ store a byte, decrement pointer + adds r3,r7,#0 @ move Q in for next divide, update flags + bne div_by_10 @ if Q not zero, loop + +write_out: + add r1,r10,#1 @ adjust pointer + ldmfd SP!,{r10,LR} @ restore return address from stack + + cmp r0,#0 + bne strcat @ if 1, strcat + + b write_stdout @ else, fallthrough to stdout + + + @=================================================== + @ Divide - because ARM has no hardware int divide + @ yes this is an awful algorithm, but simple + @ and uses few registers + @================================================== + @ r3=numerator r4=denominator + @ r7=quotient r8=remainder + @ r5=trashed +divide: + + mov r7,#0 @ zero out quotient +divide_loop: + mul r5,r7,r4 @ multiply Q by denominator + add r7,r7,#1 @ increment quotient + cmp r5,r3 @ is it greater than numerator? + ble divide_loop @ if not, loop + sub r7,r7,#2 @ otherwise went too far, decrement + @ and done + + mul r5,r7,r4 @ calculate remainder + sub r8,r3,r5 @ R=N-(Q*D) + bx r14 @ return + + +bss_addr: .word bss_begin +data_addr: .word data_begin +out_addr: .word out_buffer +disk_addr: .word disk_buffer +logo_end_addr: .word logo_end +pos_mask: .word ((POSITION_MASK<<8)+0xff) +text_addr: .word text_buf + +#=========================================================================== +# section .data +#=========================================================================== +.data +data_begin: +ver_string: .ascii " Version \0" +compiled_string: .ascii ", Compiled \0" +processor: .ascii " Processor, \0" +ram_comma: .ascii "M RAM, \0" +bogo_total: .ascii " Bogomips Total\n\0" + +default_colors: .ascii "\033[0m\n\n\0" +escape: .ascii "\033[\0" +C: .ascii "C\0" + +one: .ascii "One \0" + +uname_info: +.ascii "Linux\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "lindt\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "2.6.32\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "#1 Wed May 13 15:51:54 UTC 2009\0" +.ascii "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +.ascii "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" + + +disk_buffer: +.ascii "Processor : Feroceon 88FR131 rev 1 (v5l)\n" +.ascii "BogoMIPS : 1192.75\n" +.ascii "Features : swp half thumb fastmult edsp \n" +.ascii "CPU implementer : 0x56\n" +.ascii "CPU architecture: 5TE\n" +.ascii "CPU variant : 0x2\n" +.ascii "CPU part : 0x131\n" +.ascii "CPU revision : 1\n" +.ascii "\n" +.ascii "Hardware : Marvell SheevaPlug Reference Board\n" +.ascii "Revision : 0000\n" +.ascii "Serial : 0000000000000000\n\0" + + +sysinfo_buff: +.long 0,0,0,0,512*1024*1024,0,0,0 + +.include "../logo.lzss_new" + + +#============================================================================ +# section .bss +#============================================================================ +.bss +bss_begin: +.lcomm ascii_buffer,10 +.lcomm text_buf, (N+F-1) +.lcomm out_buffer,16384 diff --git a/exp-bbv/tests/arm-linux/ll.post.exp b/exp-bbv/tests/arm-linux/ll.post.exp new file mode 100644 index 0000000..99fbf4e --- /dev/null +++ b/exp-bbv/tests/arm-linux/ll.post.exp @@ -0,0 +1,56 @@ +T:1:12 :8:5 :6:24 :2:28 :9:18 :10:744 :4:104 :5:26 :7:1 :3:39 +T:8:10 :6:26 :2:30 :9:108 :10:695 :4:72 :5:30 :7:2 :3:27 +T:6:6 :2:6 :9:54 :10:928 :5:6 +T:8:5 :6:12 :2:14 :9:36 :10:863 :4:40 :5:14 :7:1 :3:15 +T:8:5 :6:10 :2:12 :9:90 :10:859 :4:8 :5:12 :7:1 :3:3 +T:8:5 :6:6 :2:8 :9:72 :10:900 :5:8 :7:1 +T:6:12 :2:12 :9:90 :10:863 :4:8 :5:12 :3:3 +T:8:5 :6:4 :2:6 :9:54 :10:924 :5:6 :7:1 +T:6:4 :2:4 :9:36 :10:952 :5:4 +T:6:8 :2:8 :9:72 :10:904 :5:8 +T:8:5 :6:10 :2:12 :9:108 :10:852 :5:12 :7:1 +T:8:5 :6:6 :2:8 :9:72 :10:900 :5:8 :7:1 +T:6:6 :2:6 :9:54 :10:928 :5:6 +T:6:6 :2:6 :9:54 :10:928 :5:6 +T:8:5 :6:4 :2:6 :9:54 :10:924 :5:6 :7:1 +T:6:6 :2:6 :9:54 :10:928 :5:6 +T:6:4 :2:4 :9:36 :10:952 :5:4 +T:8:5 :6:4 :2:6 :9:54 :10:924 :5:6 :7:1 +T:6:4 :2:4 :9:36 :10:952 :5:4 +T:6:6 :2:6 :9:54 :10:928 :5:6 +T:8:5 :6:2 :2:4 :9:36 :10:948 :5:4 :7:1 +T:6:2 :2:2 :9:18 :10:976 :5:2 +T:6:10 :2:10 :9:55 :10:904 :4:8 :5:10 :3:3 +T:8:5 :6:4 :2:6 :9:71 :10:907 :5:6 :7:1 +T:6:4 :2:4 :9:36 :10:952 :5:4 +T:6:6 :2:6 :9:54 :10:928 :5:6 +T:8:5 :6:14 :2:16 :9:126 :10:811 :4:8 :5:16 :7:1 :3:3 +T:8:5 :6:2 :2:4 :9:36 :10:948 :5:4 :7:1 +T:6:4 :2:4 :9:36 :10:952 :5:4 +T:6:6 :2:6 :9:54 :10:928 :5:6 +T:8:5 :6:8 :2:10 :9:90 :10:876 :5:10 :7:1 +T:6:8 :2:8 :9:72 :10:904 :5:8 +T:8:5 :6:4 :2:6 :9:54 :10:924 :5:6 :7:1 +T:8:5 :6:10 :2:12 :9:108 :10:852 :5:12 :7:1 +T:6:8 :2:6 :9:36 :10:434 :4:8 :5:8 :3:3 :11:2 :12:5 :13:490 +T:13:1000 +T:13:1000 +T:13:1000 +T:13:1000 +T:13:1000 +T:13:1000 +T:13:1000 +T:13:1000 +T:13:1000 +T:13:1000 +T:16:4 :19:2 :20:2 :21:2 :22:2 :23:4 :17:268 :18:10 :24:3 :25:4 :26:4 :34:2 :35:7 :12:15 :13:628 :14:12 :15:4 :27:5 :31:4 :32:4 :33:1 :28:5 :29:4 :30:4 +T:36:3 :37:5 :46:2 :47:5 :49:2 :50:5 :38:16 :41:280 :39:80 :40:40 :42:18 :43:5 :44:32 :45:3 :17:120 :18:8 :13:86 :14:3 :15:1 :27:5 :48:2 :31:12 :32:4 :28:15 :29:236 :30:12 + + +# Thread 1 +# Total intervals: 47 (Interval Size 1000) +# Total instructions: 47799 +# Total reps: 0 +# Unique reps: 0 +# Total fldcw instructions: 0 + diff --git a/exp-bbv/tests/arm-linux/ll.stderr.exp b/exp-bbv/tests/arm-linux/ll.stderr.exp new file mode 100644 index 0000000..1ec5a2c --- /dev/null +++ b/exp-bbv/tests/arm-linux/ll.stderr.exp @@ -0,0 +1,6 @@ +# Thread 1 +# Total intervals: 47 (Interval Size 1000) +# Total instructions: 47799 +# Total reps: 0 +# Unique reps: 0 +# Total fldcw instructions: 0 diff --git a/exp-bbv/tests/arm-linux/ll.stdout.exp b/exp-bbv/tests/arm-linux/ll.stdout.exp new file mode 100644 index 0000000..e63e153 --- /dev/null +++ b/exp-bbv/tests/arm-linux/ll.stdout.exp @@ -0,0 +1,17 @@ +############################################################################### +############################################################################### +##################################################################O#O########## +############################################################################### +############################################################################### +############################################################################### +############################################################################### +############################################################################### +############################################################################### +############################################################################### +############################################################################### +############################################################################### + +Linux Version 2.6.32, Compiled #1 Wed May 13 15:51:54 UTC 2009 +One Feroceon Processor, 512M RAM, 1192.75 Bogomips Total +lindt + diff --git a/exp-bbv/tests/arm-linux/ll.vgtest b/exp-bbv/tests/arm-linux/ll.vgtest new file mode 100644 index 0000000..6031a58 --- /dev/null +++ b/exp-bbv/tests/arm-linux/ll.vgtest @@ -0,0 +1,5 @@ +prog: ll +vgopts: --interval-size=1000 --bb-out-file=ll.out.bb +post: cat ll.out.bb +cleanup: rm ll.out.bb + diff --git a/exp-bbv/tests/arm-linux/million.S b/exp-bbv/tests/arm-linux/million.S new file mode 100644 index 0000000..a522f83 --- /dev/null +++ b/exp-bbv/tests/arm-linux/million.S @@ -0,0 +1,27 @@ + + # count for 1 million instructions + # total is 1 + 333332*3 + 2 + + +# Sycscalls +.equ SYSCALL_EXIT, 1 + + .globl _start +_start: + + ldr r2,count @ set count + +big_loop: + add r2,r2,#-1 + cmp r2,#0 + bne big_loop @ repeat till zero + + @================================ + @ Exit + @================================ +exit: + mov r0,#0 @ result is zero + mov r7,#SYSCALL_EXIT + swi 0x0 @ and exit + +count: .word 333332 diff --git a/exp-bbv/tests/arm-linux/million.post.exp b/exp-bbv/tests/arm-linux/million.post.exp new file mode 100644 index 0000000..6eb56fc --- /dev/null +++ b/exp-bbv/tests/arm-linux/million.post.exp @@ -0,0 +1,18 @@ +T:1:4 :2:99997 +T:2:100000 +T:2:100000 +T:2:100000 +T:2:100000 +T:2:100000 +T:2:100000 +T:2:100000 +T:2:100000 + + +# Thread 1 +# Total intervals: 10 (Interval Size 100000) +# Total instructions: 1000000 +# Total reps: 0 +# Unique reps: 0 +# Total fldcw instructions: 0 + diff --git a/exp-bbv/tests/arm-linux/million.stderr.exp b/exp-bbv/tests/arm-linux/million.stderr.exp new file mode 100644 index 0000000..adeb35d --- /dev/null +++ b/exp-bbv/tests/arm-linux/million.stderr.exp @@ -0,0 +1,6 @@ +# Thread 1 +# Total intervals: 10 (Interval Size 100000) +# Total instructions: 1000000 +# Total reps: 0 +# Unique reps: 0 +# Total fldcw instructions: 0 diff --git a/exp-bbv/tests/arm-linux/million.vgtest b/exp-bbv/tests/arm-linux/million.vgtest new file mode 100644 index 0000000..c366a8b --- /dev/null +++ b/exp-bbv/tests/arm-linux/million.vgtest @@ -0,0 +1,5 @@ +prog: million +vgopts: --interval-size=100000 --bb-out-file=million.out.bb +post: cat million.out.bb +cleanup: rm million.out.bb + diff --git a/exp-bbv/tests/ppc32-linux/Makefile.am b/exp-bbv/tests/ppc32-linux/Makefile.am index d022cf7..c094959 100644 --- a/exp-bbv/tests/ppc32-linux/Makefile.am +++ b/exp-bbv/tests/ppc32-linux/Makefile.am @@ -14,9 +14,9 @@ EXTRA_DIST = \ million.post.exp \ million.vgtest -AM_CCASFLAGS += -ffreestanding +AM_CCASFLAGS += -ffreestanding -m32 -LDFLAGS += -nostartfiles -nodefaultlibs +LDFLAGS += -nostartfiles -nodefaultlibs -m32 ll_SOURCES = ll.S million_SOURCES = million.S diff --git a/exp-dhat/Makefile.am b/exp-dhat/Makefile.am new file mode 100644 index 0000000..9ee6497 --- /dev/null +++ b/exp-dhat/Makefile.am @@ -0,0 +1,100 @@ +include $(top_srcdir)/Makefile.tool.am + +#SUBDIRS += perf + +EXTRA_DIST = docs/dh-manual.xml + +#---------------------------------------------------------------------------- +# Headers, etc +#---------------------------------------------------------------------------- + +#bin_SCRIPTS = dh_print + +#---------------------------------------------------------------------------- +# exp_dhat- +#---------------------------------------------------------------------------- + +noinst_PROGRAMS = exp-dhat-@VGCONF_ARCH_PRI@-@VGCONF_OS@ +if VGCONF_HAVE_PLATFORM_SEC +noinst_PROGRAMS += exp-dhat-@VGCONF_ARCH_SEC@-@VGCONF_OS@ +endif + +EXP_DHAT_SOURCES_COMMON = dh_main.c + +exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ + $(EXP_DHAT_SOURCES_COMMON) +exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \ + $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \ + $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES = \ + $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) +exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ + $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) +exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ + $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + +if VGCONF_HAVE_PLATFORM_SEC +exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ + $(EXP_DHAT_SOURCES_COMMON) +exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \ + $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \ + $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES = \ + $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) +exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ + $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) +exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ + $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) +endif + +#---------------------------------------------------------------------------- +# vgpreload_exp_dhat-.so +#---------------------------------------------------------------------------- + +noinst_PROGRAMS += vgpreload_exp-dhat-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so +if VGCONF_HAVE_PLATFORM_SEC +noinst_PROGRAMS += vgpreload_exp-dhat-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so +endif + +if VGCONF_OS_IS_DARWIN +noinst_DSYMS = $(noinst_PROGRAMS) +endif + +vgpreload_exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = +vgpreload_exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \ + $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +vgpreload_exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS = \ + $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(AM_CFLAGS_PIC) +vgpreload_exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \ + $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_PRI_CAPS@) +vgpreload_exp_dhat_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \ + $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ + $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) + +if VGCONF_HAVE_PLATFORM_SEC +vgpreload_exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = +vgpreload_exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS = \ + $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +vgpreload_exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS = \ + $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(AM_CFLAGS_PIC) +vgpreload_exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES = \ + $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_SEC_CAPS@) +vgpreload_exp_dhat_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS = \ + $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \ + $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +endif + diff --git a/exp-dhat/dh_main.c b/exp-dhat/dh_main.c new file mode 100644 index 0000000..28e6d8c --- /dev/null +++ b/exp-dhat/dh_main.c @@ -0,0 +1,1261 @@ + +//--------------------------------------------------------------------*/ +//--- DHAT: a Dynamic Heap Analysis Tool dh_main.c ---*/ +//--------------------------------------------------------------------*/ + +/* + This file is part of DHAT, a Valgrind tool for profiling the + heap usage of programs. + + Copyright (C) 2010-2010 Mozilla Inc + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +/* Contributed by Julian Seward */ + + +#include "pub_tool_basics.h" +#include "pub_tool_libcbase.h" +#include "pub_tool_libcassert.h" +#include "pub_tool_libcprint.h" +#include "pub_tool_machine.h" // VG_(fnptr_to_fnentry) +#include "pub_tool_mallocfree.h" +#include "pub_tool_options.h" +#include "pub_tool_replacemalloc.h" +#include "pub_tool_tooliface.h" +#include "pub_tool_wordfm.h" + +#define HISTOGRAM_SIZE_LIMIT 4096 //1024 + + +//------------------------------------------------------------// +//--- Globals ---// +//------------------------------------------------------------// + +// Number of guest instructions executed so far. This is +// incremented directly from the generated code. +static ULong g_guest_instrs_executed = 0; + +// Summary statistics for the entire run. +static ULong g_tot_blocks = 0; // total blocks allocated +static ULong g_tot_bytes = 0; // total bytes allocated + +static ULong g_cur_blocks_live = 0; // curr # blocks live +static ULong g_cur_bytes_live = 0; // curr # bytes live + +static ULong g_max_blocks_live = 0; // bytes and blocks at +static ULong g_max_bytes_live = 0; // the max residency point + + +//------------------------------------------------------------// +//--- an Interval Tree of live blocks ---// +//------------------------------------------------------------// + +/* Tracks information about live blocks. */ +typedef + struct { + Addr payload; + SizeT req_szB; + ExeContext* ap; /* allocation ec */ + ULong allocd_at; /* instruction number */ + ULong n_reads; + ULong n_writes; + /* Approx histogram, one byte per payload byte. Counts latch up + therefore at 0xFFFF. Can be NULL if the block is resized or if + the block is larger than HISTOGRAM_SIZE_LIMIT. */ + UShort* histoW; /* [0 .. req_szB-1] */ + } + Block; + +/* May not contain zero-sized blocks. May not contain + overlapping blocks. */ +static WordFM* interval_tree = NULL; /* WordFM* Block* void */ + +/* Here's the comparison function. Since the tree is required +to contain non-zero sized, non-overlapping blocks, it's good +enough to consider any overlap as a match. */ +static Word interval_tree_Cmp ( UWord k1, UWord k2 ) +{ + Block* b1 = (Block*)k1; + Block* b2 = (Block*)k2; + tl_assert(b1->req_szB > 0); + tl_assert(b2->req_szB > 0); + if (b1->payload + b1->req_szB <= b2->payload) return -1; + if (b2->payload + b2->req_szB <= b1->payload) return 1; + return 0; +} + +static Block* find_Block_containing ( Addr a ) +{ + Block fake; + fake.payload = a; + fake.req_szB = 1; + UWord foundkey = 1; + UWord foundval = 1; + Bool found = VG_(lookupFM)( interval_tree, + &foundkey, &foundval, (UWord)&fake ); + if (!found) + return NULL; + tl_assert(foundval == 0); // we don't store vals in the interval tree + tl_assert(foundkey != 1); + Block* res = (Block*)foundkey; + tl_assert(res != &fake); + return res; +} + +// delete a block; asserts if not found. (viz, 'a' must be +// known to be present.) +static void delete_Block_starting_at ( Addr a ) +{ + Block fake; + fake.payload = a; + fake.req_szB = 1; + Bool found = VG_(delFromFM)( interval_tree, + NULL, NULL, (Addr)&fake ); + tl_assert(found); +} + + +//------------------------------------------------------------// +//--- a FM of allocation points (APs) ---// +//------------------------------------------------------------// + +typedef + struct { + // the allocation point that we're summarising stats for + ExeContext* ap; + // used when printing results + Bool shown; + // The current number of blocks and bytes live for this AP + ULong cur_blocks_live; + ULong cur_bytes_live; + // The number of blocks and bytes live at the max-liveness + // point. Note this is a bit subtle. max_blocks_live is not + // the maximum number of live blocks, but rather the number of + // blocks live at the point of maximum byte liveness. These are + // not necessarily the same thing. + ULong max_blocks_live; + ULong max_bytes_live; + // Total number of blocks and bytes allocated by this AP. + ULong tot_blocks; + ULong tot_bytes; + // Sum of death ages for all blocks allocated by this AP, + // that have subsequently been freed. + ULong death_ages_sum; + ULong deaths; + // Total number of reads and writes in all blocks allocated + // by this AP. + ULong n_reads; + ULong n_writes; + /* Histogram information. We maintain a histogram aggregated for + all retiring Blocks allocated by this AP, but only if: + - this AP has only ever allocated objects of one size + - that size is <= HISTOGRAM_SIZE_LIMIT + What we need therefore is a mechanism to see if this AP + has only ever allocated blocks of one size. + + 3 states: + Unknown because no retirement yet + Exactly xsize all retiring blocks are of this size + Mixed multiple different sizes seen + */ + enum { Unknown=999, Exactly, Mixed } xsize_tag; + SizeT xsize; + UInt* histo; /* [0 .. xsize-1] */ + } + APInfo; + +/* maps ExeContext*'s to APInfo*'s. Note that the keys must match the + .ap field in the values. */ +static WordFM* apinfo = NULL; /* WordFM* ExeContext* APInfo* */ + + +/* 'bk' is being introduced (has just been allocated). Find the + relevant APInfo entry for it, or create one, based on the block's + allocation EC. Then, update the APInfo to the extent that we + actually can, to reflect the allocation. */ +static void intro_Block ( Block* bk ) +{ + tl_assert(bk); + tl_assert(bk->ap); + + APInfo* api = NULL; + UWord keyW = 0; + UWord valW = 0; + Bool found = VG_(lookupFM)( apinfo, + &keyW, &valW, (UWord)bk->ap ); + if (found) { + api = (APInfo*)valW; + tl_assert(keyW == (UWord)bk->ap); + } else { + api = VG_(malloc)( "dh.main.intro_Block.1", sizeof(APInfo) ); + VG_(memset)(api, 0, sizeof(*api)); + api->ap = bk->ap; + Bool present = VG_(addToFM)( apinfo, + (UWord)bk->ap, (UWord)api ); + tl_assert(!present); + // histo stuff + tl_assert(api->deaths == 0); + api->xsize_tag = Unknown; + api->xsize = 0; + if (0) VG_(printf)("api %p --> Unknown\n", api); + } + + tl_assert(api->ap == bk->ap); + + /* So: update stats to reflect an allocation */ + + // # live blocks + api->cur_blocks_live++; + + // # live bytes + api->cur_bytes_live += bk->req_szB; + if (api->cur_bytes_live > api->max_bytes_live) { + api->max_bytes_live = api->cur_bytes_live; + api->max_blocks_live = api->cur_blocks_live; + } + + // total blocks and bytes allocated here + api->tot_blocks++; + api->tot_bytes += bk->req_szB; + + // update summary globals + g_tot_blocks++; + g_tot_bytes += bk->req_szB; + + g_cur_blocks_live++; + g_cur_bytes_live += bk->req_szB; + if (g_cur_bytes_live > g_max_bytes_live) { + g_max_bytes_live = g_cur_bytes_live; + g_max_blocks_live = g_cur_blocks_live; + } +} + + +/* 'bk' is retiring (being freed). Find the relevant APInfo entry for + it, which must already exist. Then, fold info from 'bk' into that + entry. */ +static void retire_Block ( Block* bk ) +{ + tl_assert(bk); + tl_assert(bk->ap); + + APInfo* api = NULL; + UWord keyW = 0; + UWord valW = 0; + Bool found = VG_(lookupFM)( apinfo, + &keyW, &valW, (UWord)bk->ap ); + + tl_assert(found); + api = (APInfo*)valW; + tl_assert(api->ap == bk->ap); + + // update stats following this free. + if (0) + VG_(printf)("ec %p api->c_by_l %llu bk->rszB %llu\n", + bk->ap, api->cur_bytes_live, (ULong)bk->req_szB); + + tl_assert(api->cur_blocks_live >= 1); + tl_assert(api->cur_bytes_live >= bk->req_szB); + api->cur_blocks_live--; + api->cur_bytes_live -= bk->req_szB; + + api->deaths++; + + tl_assert(bk->allocd_at <= g_guest_instrs_executed); + api->death_ages_sum += (g_guest_instrs_executed - bk->allocd_at); + + api->n_reads += bk->n_reads; + api->n_writes += bk->n_writes; + + // update global summary stats + tl_assert(g_cur_blocks_live > 0); + g_cur_blocks_live--; + tl_assert(g_cur_bytes_live >= bk->req_szB); + g_cur_bytes_live -= bk->req_szB; + + // histo stuff. First, do state transitions for xsize/xsize_tag. + switch (api->xsize_tag) { + + case Unknown: + tl_assert(api->xsize == 0); + tl_assert(api->deaths == 1); + tl_assert(!api->histo); + api->xsize_tag = Exactly; + api->xsize = bk->req_szB; + if (0) VG_(printf)("api %p --> Exactly(%lu)\n", api, api->xsize); + // and allocate the histo + if (bk->histoW) { + api->histo = VG_(malloc)("dh.main.retire_Block.1", api->xsize * sizeof(UInt)); + VG_(memset)(api->histo, 0, api->xsize * sizeof(UInt)); + } + break; + + case Exactly: + tl_assert(api->deaths > 1); + if (bk->req_szB != api->xsize) { + if (0) VG_(printf)("api %p --> Mixed(%lu -> %lu)\n", + api, api->xsize, bk->req_szB); + api->xsize_tag = Mixed; + api->xsize = 0; + // deallocate the histo, if any + if (api->histo) { + VG_(free)(api->histo); + api->histo = NULL; + } + } + break; + + case Mixed: + tl_assert(api->deaths > 1); + break; + + default: + tl_assert(0); + } + + // See if we can fold the histo data from this block into + // the data for the AP + if (api->xsize_tag == Exactly && api->histo && bk->histoW) { + tl_assert(api->xsize == bk->req_szB); + UWord i; + for (i = 0; i < api->xsize; i++) { + // FIXME: do something better in case of overflow of api->histo[..] + // Right now, at least don't let it overflow/wrap around + if (api->histo[i] <= 0xFFFE0000) + api->histo[i] += (UInt)bk->histoW[i]; + } + if (0) VG_(printf)("fold in, AP = %p\n", api); + } + + + +#if 0 + if (bk->histoB) { + VG_(printf)("block retiring, histo %lu: ", bk->req_szB); + UWord i; + for (i = 0; i < bk->req_szB; i++) + VG_(printf)("%u ", (UInt)bk->histoB[i]); + VG_(printf)("\n"); + } else { + VG_(printf)("block retiring, no histo %lu\n", bk->req_szB); + } +#endif +} + +/* This handles block resizing. When a block with AP 'ec' has a + size change of 'delta', call here to update the APInfo. */ +static void apinfo_change_cur_bytes_live( ExeContext* ec, Long delta ) +{ + APInfo* api = NULL; + UWord keyW = 0; + UWord valW = 0; + Bool found = VG_(lookupFM)( apinfo, + &keyW, &valW, (UWord)ec ); + + tl_assert(found); + api = (APInfo*)valW; + tl_assert(api->ap == ec); + + if (delta < 0) { + tl_assert(api->cur_bytes_live >= -delta); + tl_assert(g_cur_bytes_live >= -delta); + } + + // adjust current live size + api->cur_bytes_live += delta; + g_cur_bytes_live += delta; + + if (delta > 0 && api->cur_bytes_live > api->max_bytes_live) { + api->max_bytes_live = api->cur_bytes_live; + api->max_blocks_live = api->cur_blocks_live; + } + + // update global summary stats + if (delta > 0 && g_cur_bytes_live > g_max_bytes_live) { + g_max_bytes_live = g_cur_bytes_live; + g_max_blocks_live = g_cur_blocks_live; + } + + // adjust total allocation size + if (delta > 0) + api->tot_bytes += delta; +} + + +//------------------------------------------------------------// +//--- update both Block and APInfos after {m,re}alloc/free ---// +//------------------------------------------------------------// + +static +void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB, + Bool is_zeroed ) +{ + tl_assert(p == NULL); // don't handle custom allocators right now + SizeT actual_szB, slop_szB; + + if ((SSizeT)req_szB < 0) return NULL; + + if (req_szB == 0) + req_szB = 1; /* can't allow zero-sized blocks in the interval tree */ + + // Allocate and zero if necessary + if (!p) { + p = VG_(cli_malloc)( req_alignB, req_szB ); + if (!p) { + return NULL; + } + if (is_zeroed) VG_(memset)(p, 0, req_szB); + actual_szB = VG_(malloc_usable_size)(p); + tl_assert(actual_szB >= req_szB); + slop_szB = actual_szB - req_szB; + } else { + slop_szB = 0; + } + + // Make new HP_Chunk node, add to malloc_list + Block* bk = VG_(malloc)("dh.new_block.1", sizeof(Block)); + bk->payload = (Addr)p; + bk->req_szB = req_szB; + bk->ap = VG_(record_ExeContext)(tid, 0/*first word delta*/); + bk->allocd_at = g_guest_instrs_executed; + bk->n_reads = 0; + bk->n_writes = 0; + // set up histogram array, if the block isn't too large + bk->histoW = NULL; + if (req_szB <= HISTOGRAM_SIZE_LIMIT) { + bk->histoW = VG_(malloc)("dh.new_block.2", req_szB * sizeof(UShort)); + VG_(memset)(bk->histoW, 0, req_szB * sizeof(UShort)); + } + + Bool present = VG_(addToFM)( interval_tree, (UWord)bk, (UWord)0/*no val*/); + tl_assert(!present); + + intro_Block(bk); + + if (0) VG_(printf)("ALLOC %ld -> %p\n", req_szB, p); + + return p; +} + +static +void die_block ( void* p, Bool custom_free ) +{ + tl_assert(!custom_free); // at least for now + + Block* bk = find_Block_containing( (Addr)p ); + + if (!bk) { + return; // bogus free + } + + tl_assert(bk->req_szB > 0); + // assert the block finder is behaving sanely + tl_assert(bk->payload <= (Addr)p); + tl_assert( (Addr)p < bk->payload + bk->req_szB ); + + if (bk->payload != (Addr)p) { + return; // bogus free + } + + if (0) VG_(printf)(" FREE %p %llu\n", + p, g_guest_instrs_executed - bk->allocd_at); + + retire_Block(bk); + + VG_(cli_free)( (void*)bk->payload ); + delete_Block_starting_at( bk->payload ); + if (bk->histoW) { + VG_(free)( bk->histoW ); + bk->histoW = NULL; + } + VG_(free)( bk ); +} + + +static +void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB ) +{ + if (0) VG_(printf)("REALL %p %ld\n", p_old, new_req_szB); + void* p_new = NULL; + + tl_assert(new_req_szB > 0); // map 0 to 1 + + // Find the old block. + Block* bk = find_Block_containing( (Addr)p_old ); + if (!bk) { + return NULL; // bogus realloc + } + + tl_assert(bk->req_szB > 0); + // assert the block finder is behaving sanely + tl_assert(bk->payload <= (Addr)p_old); + tl_assert( (Addr)p_old < bk->payload + bk->req_szB ); + + if (bk->payload != (Addr)p_old) { + return NULL; // bogus realloc + } + + // Keeping the histogram alive in any meaningful way across + // block resizing is too darn complicated. Just throw it away. + if (bk->histoW) { + VG_(free)(bk->histoW); + bk->histoW = NULL; + } + + // Actually do the allocation, if necessary. + if (new_req_szB <= bk->req_szB) { + + // New size is smaller or same; block not moved. + apinfo_change_cur_bytes_live(bk->ap, + (Long)new_req_szB - (Long)bk->req_szB); + bk->req_szB = new_req_szB; + return p_old; + + } else { + + // New size is bigger; make new block, copy shared contents, free old. + p_new = VG_(cli_malloc)(VG_(clo_alignment), new_req_szB); + if (!p_new) { + // Nb: if realloc fails, NULL is returned but the old block is not + // touched. What an awful function. + return NULL; + } + tl_assert(p_new != p_old); + + VG_(memcpy)(p_new, p_old, bk->req_szB); + VG_(cli_free)(p_old); + + // Since the block has moved, we need to re-insert it into the + // interval tree at the new place. Do this by removing + // and re-adding it. + delete_Block_starting_at( (Addr)p_old ); + // now 'bk' is no longer in the tree, but the Block itself + // is still alive + + // Update the metadata. + apinfo_change_cur_bytes_live(bk->ap, + (Long)new_req_szB - (Long)bk->req_szB); + bk->payload = (Addr)p_new; + bk->req_szB = new_req_szB; + + // and re-add + Bool present + = VG_(addToFM)( interval_tree, (UWord)bk, (UWord)0/*no val*/); + tl_assert(!present); + + return p_new; + } + /*NOTREACHED*/ + tl_assert(0); +} + + +//------------------------------------------------------------// +//--- malloc() et al replacement wrappers ---// +//------------------------------------------------------------// + +static void* dh_malloc ( ThreadId tid, SizeT szB ) +{ + return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False ); +} + +static void* dh___builtin_new ( ThreadId tid, SizeT szB ) +{ + return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False ); +} + +static void* dh___builtin_vec_new ( ThreadId tid, SizeT szB ) +{ + return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False ); +} + +static void* dh_calloc ( ThreadId tid, SizeT m, SizeT szB ) +{ + return new_block( tid, NULL, m*szB, VG_(clo_alignment), /*is_zeroed*/True ); +} + +static void *dh_memalign ( ThreadId tid, SizeT alignB, SizeT szB ) +{ + return new_block( tid, NULL, szB, alignB, False ); +} + +static void dh_free ( ThreadId tid __attribute__((unused)), void* p ) +{ + die_block( p, /*custom_free*/False ); +} + +static void dh___builtin_delete ( ThreadId tid, void* p ) +{ + die_block( p, /*custom_free*/False); +} + +static void dh___builtin_vec_delete ( ThreadId tid, void* p ) +{ + die_block( p, /*custom_free*/False ); +} + +static void* dh_realloc ( ThreadId tid, void* p_old, SizeT new_szB ) +{ + if (p_old == NULL) { + return dh_malloc(tid, new_szB); + } + if (new_szB == 0) { + dh_free(tid, p_old); + return NULL; + } + return renew_block(tid, p_old, new_szB); +} + +static SizeT dh_malloc_usable_size ( ThreadId tid, void* p ) +{ + tl_assert(0); +//zz HP_Chunk* hc = VG_(HT_lookup)( malloc_list, (UWord)p ); +//zz +//zz return ( hc ? hc->req_szB + hc->slop_szB : 0 ); +} + +//------------------------------------------------------------// +//--- memory references ---// +//------------------------------------------------------------// + +static +void inc_histo_for_block ( Block* bk, Addr addr, UWord szB ) +{ + UWord i, offMin, offMax1; + offMin = addr - bk->payload; + tl_assert(offMin < bk->req_szB); + offMax1 = offMin + szB; + if (offMax1 > bk->req_szB) + offMax1 = bk->req_szB; + //VG_(printf)("%lu %lu (size of block %lu)\n", offMin, offMax1, bk->req_szB); + for (i = offMin; i < offMax1; i++) { + UShort n = bk->histoW[i]; + if (n < 0xFFFF) n++; + bk->histoW[i] = n; + } +} + +static VG_REGPARM(2) +void dh_handle_write ( Addr addr, UWord szB ) +{ + Block* bk = find_Block_containing(addr); + if (bk) { + bk->n_writes += szB; + if (bk->histoW) + inc_histo_for_block(bk, addr, szB); + } +} + +static VG_REGPARM(2) +void dh_handle_read ( Addr addr, UWord szB ) +{ + Block* bk = find_Block_containing(addr); + if (bk) { + bk->n_reads += szB; + if (bk->histoW) + inc_histo_for_block(bk, addr, szB); + } +} + + +// Handle reads and writes by syscalls (read == kernel +// reads user space, write == kernel writes user space). +// Assumes no such read or write spans a heap block +// boundary and so we can treat it just as one giant +// read or write. +static +void dh_handle_noninsn_read ( CorePart part, ThreadId tid, Char* s, + Addr base, SizeT size ) +{ + switch (part) { + case Vg_CoreSysCall: + dh_handle_read(base, size); + break; + case Vg_CoreSysCallArgInMem: + break; + case Vg_CoreTranslate: + break; + default: + tl_assert(0); + } +} + +static +void dh_handle_noninsn_write ( CorePart part, ThreadId tid, + Addr base, SizeT size ) +{ + switch (part) { + case Vg_CoreSysCall: + dh_handle_write(base, size); + break; + case Vg_CoreSignal: + break; + default: + tl_assert(0); + } +} + + +//------------------------------------------------------------// +//--- Instrumentation ---// +//------------------------------------------------------------// + +static +void add_counter_update(IRSB* sbOut, Int n) +{ + #if defined(VG_BIGENDIAN) + # define END Iend_BE + #elif defined(VG_LITTLEENDIAN) + # define END Iend_LE + #else + # error "Unknown endianness" + #endif + // Add code to increment 'g_guest_instrs_executed' by 'n', like this: + // WrTmp(t1, Load64(&g_guest_instrs_executed)) + // WrTmp(t2, Add64(RdTmp(t1), Const(n))) + // Store(&g_guest_instrs_executed, t2) + IRTemp t1 = newIRTemp(sbOut->tyenv, Ity_I64); + IRTemp t2 = newIRTemp(sbOut->tyenv, Ity_I64); + IRExpr* counter_addr = mkIRExpr_HWord( (HWord)&g_guest_instrs_executed ); + + IRStmt* st1 = IRStmt_WrTmp(t1, IRExpr_Load(END, Ity_I64, counter_addr)); + IRStmt* st2 = + IRStmt_WrTmp(t2, + IRExpr_Binop(Iop_Add64, IRExpr_RdTmp(t1), + IRExpr_Const(IRConst_U64(n)))); + IRStmt* st3 = IRStmt_Store(END, counter_addr, IRExpr_RdTmp(t2)); + + addStmtToIRSB( sbOut, st1 ); + addStmtToIRSB( sbOut, st2 ); + addStmtToIRSB( sbOut, st3 ); +} + +static +void addMemEvent(IRSB* sbOut, Bool isWrite, Int szB, IRExpr* addr ) +{ + IRType tyAddr = Ity_INVALID; + HChar* hName = NULL; + void* hAddr = NULL; + IRExpr** argv = NULL; + IRDirty* di = NULL; + + tyAddr = typeOfIRExpr( sbOut->tyenv, addr ); + tl_assert(tyAddr == Ity_I32 || tyAddr == Ity_I64); + + if (isWrite) { + hName = "dh_handle_write"; + hAddr = &dh_handle_write; + } else { + hName = "dh_handle_read"; + hAddr = &dh_handle_read; + } + + argv = mkIRExprVec_2( addr, mkIRExpr_HWord(szB) ); + + /* Add the helper. */ + tl_assert(hName); + tl_assert(hAddr); + tl_assert(argv); + di = unsafeIRDirty_0_N( 2/*regparms*/, + hName, VG_(fnptr_to_fnentry)( hAddr ), + argv ); + + addStmtToIRSB( sbOut, IRStmt_Dirty(di) ); +} + +static +IRSB* dh_instrument ( VgCallbackClosure* closure, + IRSB* sbIn, + VexGuestLayout* layout, + VexGuestExtents* vge, + IRType gWordTy, IRType hWordTy ) +{ + Int i, n = 0; + IRSB* sbOut; + IRTypeEnv* tyenv = sbIn->tyenv; + + // We increment the instruction count in two places: + // - just before any Ist_Exit statements; + // - just before the IRSB's end. + // In the former case, we zero 'n' and then continue instrumenting. + + sbOut = deepCopyIRSBExceptStmts(sbIn); + + // Copy verbatim any IR preamble preceding the first IMark + i = 0; + while (i < sbIn->stmts_used && sbIn->stmts[i]->tag != Ist_IMark) { + addStmtToIRSB( sbOut, sbIn->stmts[i] ); + i++; + } + + for (/*use current i*/; i < sbIn->stmts_used; i++) { + IRStmt* st = sbIn->stmts[i]; + + if (!st || st->tag == Ist_NoOp) continue; + + switch (st->tag) { + + case Ist_IMark: { + n++; + break; + } + + case Ist_Exit: { + if (n > 0) { + // Add an increment before the Exit statement, then reset 'n'. + add_counter_update(sbOut, n); + n = 0; + } + break; + } + + case Ist_WrTmp: { + IRExpr* data = st->Ist.WrTmp.data; + if (data->tag == Iex_Load) { + IRExpr* aexpr = data->Iex.Load.addr; + // Note also, endianness info is ignored. I guess + // that's not interesting. + addMemEvent( sbOut, False/*!isWrite*/, + sizeofIRType(data->Iex.Load.ty), aexpr ); + } + break; + } + + case Ist_Store: { + IRExpr* data = st->Ist.Store.data; + IRExpr* aexpr = st->Ist.Store.addr; + addMemEvent( sbOut, True/*isWrite*/, + sizeofIRType(typeOfIRExpr(tyenv, data)), aexpr ); + break; + } + + case Ist_Dirty: { + Int dataSize; + IRDirty* d = st->Ist.Dirty.details; + if (d->mFx != Ifx_None) { + /* This dirty helper accesses memory. Collect the details. */ + tl_assert(d->mAddr != NULL); + tl_assert(d->mSize != 0); + dataSize = d->mSize; + // Large (eg. 28B, 108B, 512B on x86) data-sized + // instructions will be done inaccurately, but they're + // very rare and this avoids errors from hitting more + // than two cache lines in the simulation. + if (d->mFx == Ifx_Read || d->mFx == Ifx_Modify) + addMemEvent( sbOut, False/*!isWrite*/, + dataSize, d->mAddr ); + if (d->mFx == Ifx_Write || d->mFx == Ifx_Modify) + addMemEvent( sbOut, True/*isWrite*/, + dataSize, d->mAddr ); + } else { + tl_assert(d->mAddr == NULL); + tl_assert(d->mSize == 0); + } + break; + } + + case Ist_CAS: { + /* We treat it as a read and a write of the location. I + think that is the same behaviour as it was before IRCAS + was introduced, since prior to that point, the Vex + front ends would translate a lock-prefixed instruction + into a (normal) read followed by a (normal) write. */ + Int dataSize; + IRCAS* cas = st->Ist.CAS.details; + tl_assert(cas->addr != NULL); + tl_assert(cas->dataLo != NULL); + dataSize = sizeofIRType(typeOfIRExpr(tyenv, cas->dataLo)); + if (cas->dataHi != NULL) + dataSize *= 2; /* since it's a doubleword-CAS */ + addMemEvent( sbOut, False/*!isWrite*/, dataSize, cas->addr ); + addMemEvent( sbOut, True/*isWrite*/, dataSize, cas->addr ); + break; + } + + case Ist_LLSC: { + IRType dataTy; + if (st->Ist.LLSC.storedata == NULL) { + /* LL */ + dataTy = typeOfIRTemp(tyenv, st->Ist.LLSC.result); + addMemEvent( sbOut, False/*!isWrite*/, + sizeofIRType(dataTy), st->Ist.LLSC.addr ); + } else { + /* SC */ + dataTy = typeOfIRExpr(tyenv, st->Ist.LLSC.storedata); + addMemEvent( sbOut, True/*isWrite*/, + sizeofIRType(dataTy), st->Ist.LLSC.addr ); + } + break; + } + + default: + break; + } + + addStmtToIRSB( sbOut, st ); + } + + if (n > 0) { + // Add an increment before the SB end. + add_counter_update(sbOut, n); + } + return sbOut; +} + + +//------------------------------------------------------------// +//--- Command line args ---// +//------------------------------------------------------------// + +// FORWARDS +static Bool identify_metric ( /*OUT*/ULong(**get_metricP)(APInfo*), + /*OUT*/Bool* increasingP, + Char* metric_name ); + +static Int clo_show_top_n = 10; +static HChar* clo_sort_by = "max-bytes-live"; + +static Bool dh_process_cmd_line_option(Char* arg) +{ + if VG_BINT_CLO(arg, "--show-top-n", clo_show_top_n, 1, 100000) {} + + else if VG_STR_CLO(arg, "--sort-by", clo_sort_by) { + ULong (*dummyFn)(APInfo*); + Bool dummyB; + Bool ok = identify_metric( &dummyFn, &dummyB, clo_sort_by); + if (!ok) + return False; + // otherwise it's OK, in which case leave it alone. + // show_top_n_apinfos will later convert the string by a + // second call to identify_metric. + } + + else + return VG_(replacement_malloc_process_cmd_line_option)(arg); + + return True; +} + + +static void dh_print_usage(void) +{ + VG_(printf)( +" --show-top-n=number show the top alloc points [10]\n" +" --sort-by=string\n" +" sort the allocation points by the metric\n" +" defined by , thusly:\n" +" max-bytes-live maximum live bytes [default]\n" +" tot-bytes-allocd total allocation (turnover)\n" +" max-blocks-live maximum live blocks\n" + ); +} + +static void dh_print_debug_usage(void) +{ + VG_(printf)( +" (none)\n" + ); +} + + +//------------------------------------------------------------// +//--- Finalisation ---// +//------------------------------------------------------------// + +static void show_N_div_100( /*OUT*/HChar* buf, ULong n ) +{ + ULong nK = n / 100; + ULong nR = n % 100; + VG_(sprintf)(buf, "%llu.%s%llu", nK, + nR < 10 ? "0" : "", + nR); +} + +static void show_APInfo ( APInfo* api ) +{ + HChar bufA[80]; + VG_(memset)(bufA, 0, sizeof(bufA)); + if (api->tot_blocks > 0) { + show_N_div_100( bufA, ((ULong)api->tot_bytes * 100ULL) + / (ULong)api->tot_blocks ); + } else { + bufA[0] = 'N'; bufA[1] = 'a'; bufA[2] = 'N'; + } + + VG_(umsg)("max-live: %'llu in %'llu blocks\n", + api->max_bytes_live, api->max_blocks_live); + VG_(umsg)("tot-alloc: %'llu in %'llu blocks (avg size %s)\n", + api->tot_bytes, api->tot_blocks, bufA); + + tl_assert(api->tot_blocks >= api->max_blocks_live); + tl_assert(api->tot_bytes >= api->max_bytes_live); + + if (api->deaths > 0) { + VG_(umsg)("deaths: %'llu, at avg age %'llu\n", + api->deaths, + api->deaths == 0 + ? 0 : (api->death_ages_sum / api->deaths)); + } else { + VG_(umsg)("deaths: none (none of these blocks were freed)\n"); + } + + HChar bufR[80], bufW[80]; + VG_(memset)(bufR, 0, sizeof(bufR)); + VG_(memset)(bufW, 0, sizeof(bufW)); + if (api->tot_bytes > 0) { + show_N_div_100(bufR, (100ULL * api->n_reads) / api->tot_bytes); + show_N_div_100(bufW, (100ULL * api->n_writes) / api->tot_bytes); + } else { + VG_(strcat)(bufR, "Inf"); + VG_(strcat)(bufW, "Inf"); + } + + VG_(umsg)("acc-ratios: %s rd, %s wr " + " (%'llu b-read, %'llu b-written)\n", + bufR, bufW, + api->n_reads, api->n_writes); + + VG_(pp_ExeContext)(api->ap); + + if (api->histo && api->xsize_tag == Exactly) { + VG_(umsg)("\nAggregated access counts by offset:\n"); + VG_(umsg)("\n"); + UWord i; + if (api->xsize > 0) + VG_(umsg)("[ 0] "); + for (i = 0; i < api->xsize; i++) { + if (i > 0 && (i % 16) == 0 && i != api->xsize-1) { + VG_(umsg)("\n"); + VG_(umsg)("[%4lu] ", i); + } + VG_(umsg)("%u ", api->histo[i]); + } + VG_(umsg)("\n"); + } +} + + +/* Metric-access functions for APInfos. */ +static ULong get_metric__max_bytes_live ( APInfo* api ) { + return api->max_bytes_live; +} +static ULong get_metric__tot_bytes ( APInfo* api ) { + return api->tot_bytes; +} +static ULong get_metric__max_blocks_live ( APInfo* api ) { + return api->max_blocks_live; +} + +/* Given a string, return the metric-access function and also a Bool + indicating whether we want increasing or decreasing values of the + metric. This is used twice, once in command line processing, and + then again in show_top_n_apinfos. Returns False if the given + string could not be identified.*/ +static Bool identify_metric ( /*OUT*/ULong(**get_metricP)(APInfo*), + /*OUT*/Bool* increasingP, + Char* metric_name ) +{ + if (0 == VG_(strcmp)(metric_name, "max-bytes-live")) { + *get_metricP = get_metric__max_bytes_live; + *increasingP = False; + return True; + } + if (0 == VG_(strcmp)(metric_name, "tot-bytes-allocd")) { + *get_metricP = get_metric__tot_bytes; + *increasingP = False; + return True; + } + if (0 == VG_(strcmp)(metric_name, "max-blocks-live")) { + *get_metricP = get_metric__max_blocks_live; + *increasingP = False; + return True; + } + return False; +} + + +static void show_top_n_apinfos ( void ) +{ + Int i; + UWord keyW, valW; + ULong (*get_metric)(APInfo*); + Bool increasing; + + HChar* metric_name = clo_sort_by; + tl_assert(metric_name); // ensured by clo processing + + Bool ok = identify_metric( &get_metric, &increasing, metric_name ); + tl_assert(ok); // ensured by clo processing + + VG_(umsg)("\n"); + VG_(umsg)("======== ORDERED BY %s \"%s\": " + "top %d allocators ========\n", + increasing ? "increasing" : "decreasing", + metric_name, clo_show_top_n ); + + // Clear all .shown bits + VG_(initIterFM)( apinfo ); + while (VG_(nextIterFM)( apinfo, &keyW, &valW )) { + APInfo* api = (APInfo*)valW; + tl_assert(api && api->ap == (ExeContext*)keyW); + api->shown = False; + } + VG_(doneIterFM)( apinfo ); + + // Now print the top N entries. Each one requires a + // complete scan of the set. Duh. + for (i = 0; i < clo_show_top_n; i++) { + ULong best_metric = increasing ? ~0ULL : 0ULL; + APInfo* best_api = NULL; + + VG_(initIterFM)( apinfo ); + while (VG_(nextIterFM)( apinfo, &keyW, &valW )) { + APInfo* api = (APInfo*)valW; + if (api->shown) + continue; + ULong metric = get_metric(api); + if (increasing ? (metric < best_metric) : (metric > best_metric)) { + best_metric = metric; + best_api = api; + } + } + VG_(doneIterFM)( apinfo ); + + if (!best_api) + break; // all APIs have been shown. Stop. + + VG_(umsg)("\n"); + VG_(umsg)("-------------------- %d of %d --------------------\n", + i+1, clo_show_top_n ); + show_APInfo(best_api); + best_api->shown = True; + } + + VG_(umsg)("\n"); +} + + +static void dh_fini(Int exit_status) +{ + VG_(umsg)("======== SUMMARY STATISTICS ========\n"); + VG_(umsg)("\n"); + VG_(umsg)("guest_insns: %'llu\n", g_guest_instrs_executed); + VG_(umsg)("\n"); + VG_(umsg)("max_live: %'llu in %'llu blocks\n", + g_max_bytes_live, g_max_blocks_live); + VG_(umsg)("\n"); + VG_(umsg)("tot_alloc: %'llu in %'llu blocks\n", + g_tot_bytes, g_tot_blocks); + VG_(umsg)("\n"); + if (g_tot_bytes > 0) { + VG_(umsg)("insns per allocated byte: %'llu\n", + g_guest_instrs_executed / g_tot_bytes); + VG_(umsg)("\n"); + } + + show_top_n_apinfos(); + + VG_(umsg)("\n"); + VG_(umsg)("\n"); + VG_(umsg)("==============================================================\n"); + VG_(umsg)("\n"); + VG_(umsg)("Some hints: (see --help for command line option details):\n"); + VG_(umsg)("\n"); + VG_(umsg)("* summary stats for whole program are at the top of this output\n"); + VG_(umsg)("\n"); + VG_(umsg)("* --show-top-n= controls how many alloc points are shown.\n"); + VG_(umsg)(" You probably want to set it much higher than\n"); + VG_(umsg)(" the default value (10)\n"); + VG_(umsg)("\n"); + VG_(umsg)("* --sort-by= specifies the sort key for output.\n"); + VG_(umsg)(" See --help for details.\n"); + VG_(umsg)("\n"); + VG_(umsg)("* Each allocation stack, by default 12 frames, counts as\n"); + VG_(umsg)(" a separate alloc point. This causes the data to be spread out\n"); + VG_(umsg)(" over far too many alloc points. I strongly suggest using\n"); + VG_(umsg)(" --num-callers=4 or some such, to reduce the spreading.\n"); + VG_(umsg)("\n"); +} + + +//------------------------------------------------------------// +//--- Initialisation ---// +//------------------------------------------------------------// + +static void dh_post_clo_init(void) +{ +} + +static void dh_pre_clo_init(void) +{ + VG_(details_name) ("DHAT"); + VG_(details_version) (NULL); + VG_(details_description) ("a dynamic heap analysis tool"); + VG_(details_copyright_author)( + "Copyright (C) 2010-2010, and GNU GPL'd, by Mozilla Inc"); + VG_(details_bug_reports_to) (VG_BUGS_TO); + + // Basic functions. + VG_(basic_tool_funcs) (dh_post_clo_init, + dh_instrument, + dh_fini); +//zz + // Needs. + VG_(needs_libc_freeres)(); + VG_(needs_command_line_options)(dh_process_cmd_line_option, + dh_print_usage, + dh_print_debug_usage); +//zz VG_(needs_client_requests) (dh_handle_client_request); +//zz VG_(needs_sanity_checks) (dh_cheap_sanity_check, +//zz dh_expensive_sanity_check); + VG_(needs_malloc_replacement) (dh_malloc, + dh___builtin_new, + dh___builtin_vec_new, + dh_memalign, + dh_calloc, + dh_free, + dh___builtin_delete, + dh___builtin_vec_delete, + dh_realloc, + dh_malloc_usable_size, + 0 ); + + VG_(track_pre_mem_read) ( dh_handle_noninsn_read ); + //VG_(track_pre_mem_read_asciiz) ( check_mem_is_defined_asciiz ); + VG_(track_post_mem_write) ( dh_handle_noninsn_write ); + + tl_assert(!interval_tree); + + interval_tree = VG_(newFM)( VG_(malloc), + "dh.main.interval_tree.1", + VG_(free), + interval_tree_Cmp ); + + apinfo = VG_(newFM)( VG_(malloc), + "dh.main.apinfo.1", + VG_(free), + NULL/*unboxedcmp*/ ); +} + +VG_DETERMINE_INTERFACE_VERSION(dh_pre_clo_init) + +//--------------------------------------------------------------------// +//--- end dh_main.c ---// +//--------------------------------------------------------------------// diff --git a/exp-dhat/docs/dh-manual.xml b/exp-dhat/docs/dh-manual.xml new file mode 100644 index 0000000..49df7a6 --- /dev/null +++ b/exp-dhat/docs/dh-manual.xml @@ -0,0 +1,400 @@ + + %vg-entities; ]> + + + + DHAT: a dynamic heap analysis tool + +To use this tool, you must specify + on the Valgrind +command line. + + + + +Overview + +DHAT is a tool for examining how programs use their heap +allocations. + +It tracks the allocated blocks, and inspects every memory access +to find which block, if any, it is to. The following data is +collected and presented per allocation point (allocation +stack): + + + Total allocation (number of bytes and + blocks) + + maximum live volume (number of bytes and + blocks) + + average block lifetime (number of instructions + between allocation and freeing) + + average number of reads and writes to each byte in + the block ("access ratios") + + for allocation points which always allocate blocks + only of one size, and that size is 4096 bytes or less: counts + showing how often each byte offset inside the block is + accessed. + + +Using these statistics it is possible to identify allocation +points with the following characteristics: + + + + potential process-lifetime leaks: blocks allocated + by the point just accumulate, and are freed only at the end of the + run. + + excessive turnover: points which chew through a lot + of heap, even if it is not held onto for very long + + excessively transient: points which allocate very + short lived blocks + + useless or underused allocations: blocks which are + allocated but not completely filled in, or are filled in but not + subsequently read. + + blocks with inefficient layout -- areas never + accessed, or with hot fields scattered throughout the + block. + + +As with the Massif heap profiler, DHAT measures program progress +by counting instructions, and so presents all age/time related figures +as instruction counts. This sounds a little odd at first, but it +makes runs repeatable in a way which is not possible if CPU time is +used. + + + + + + + +Understanding DHAT's output + + +DHAT provides a lot of useful information on dynamic heap usage. +Most of the art of using it is in interpretation of the resulting +numbers. That is best illustrated via a set of examples. + + + +Interpreting the max-live, tot-alloc and deaths fields + +A simple example + + + +Over the entire run of the program, this stack (allocation +point) allocated 29,520 blocks in total, containing 1,904,700 bytes in +total. By looking at the max-live data, we see that not many blocks +were simultaneously live, though: at the peak, there were 63,490 +allocated bytes in 984 blocks. This tells us that the program is +steadily freeing such blocks as it runs, rather than hanging on to all +of them until the end and freeing them all. + +The deaths entry tells us that 29,520 blocks allocated by this stack +died (were freed) during the run of the program. Since 29,520 is +also the number of blocks allocated in total, that tells us that +all allocated blocks were freed by the end of the program. + +It also tells us that the average age at death was 22,227,424 +instructions. From the summary statistics we see that the program ran +for 1,045,339,534 instructions, and so the average age at death is +about 2% of the program's total run time. + +Example of a potential process-lifetime leak + +This next example (from a different program than the above) +shows a potential process lifetime leak. A process lifetime leak +occurs when a program keeps allocating data, but only frees the +data just before it exits. Hence the program's heap grows constantly +in size, yet Memcheck reports no leak, because the program has +freed up everything at exit. This is particularly a hazard for +long running programs. + + + +There are two tell-tale signs that this might be a +process-lifetime leak. Firstly, the max-live and tot-alloc numbers +are identical. The only way that can happen is if these blocks are +all allocated and then all deallocated. + +Secondly, the average age at death (300 million insns) is 71% of +the total program lifetime (419 million insns), hence this is not a +transient allocation-free spike -- rather, it is spread out over a +large part of the entire run. One interpretation is, roughly, that +all 254 blocks were allocated in the first half of the run, held onto +for the second half, and then freed just before exit. + + + + + +Interpreting the acc-ratios fields + + +A fairly harmless allocation point record + + + +The acc-ratios field tells us that each byte in the blocks +allocated here is read an average of 2.13 times before the block is +deallocated. Given that the blocks have an average age at death of +34,611,026, that's one read per block per approximately every 15 +million instructions. So from that standpoint the blocks aren't +"working" very hard. + +More interesting is the write ratio: each byte is written an +average of 0.91 times. This tells us that some parts of the allocated +blocks are never written, at least 9% on average. To completely +initialise the block would require writing each byte at least once, +and that would give a write ratio of 1.0. The fact that some block +areas are evidently unused might point to data alignment holes or +other layout inefficiencies. + +Well, at least all the blocks are freed (24,240 allocations, +24,240 deaths). + +If all the blocks had been the same size, DHAT would also show +the access counts by block offset, so we could see where exactly these +unused areas are. However, that isn't the case: the blocks have +varying sizes, so DHAT can't perform such an analysis. We can see +that they must have varying sizes since the average block size, 61.13, +isn't a whole number. + + +A more suspicious looking example + + + +Here, both the read and write access ratios are zero. Hence +this point is allocating blocks which are never used, neither read nor +written. Indeed, they are also not freed ("deaths: none") and are +simply leaked. So, here is 180k of completely useless allocation that +could be removed. + +Re-running with Memcheck does indeed report the same leak. What +DHAT can tell us, that Memcheck can't, is that not only are the blocks +leaked, they are also never used. + +Another suspicious example + +Here's one where blocks are allocated, written to, +but never read from. We see this immediately from the zero read +access ratio. They do get freed, though: + + + +In the previous two examples, it is easy to see blocks that are +never written to, or never read from, or some combination of both. +Unfortunately, in C++ code, the situation is less clear. That's +because an object's constructor will write to the underlying block, +and its destructor will read from it. So the block's read and write +ratios will be non-zero even if the object, once constructed, is never +used, but only eventually destructed. + +Really, what we want is to measure only memory accesses in +between the end of an object's construction and the start of its +destruction. Unfortunately I do not know of a reliable way to +determine when those transitions are made. + + + + + +Interpreting "Aggregated access counts by offset" data + +For allocation points that always allocate blocks of the same +size, and which are 4096 bytes or smaller, DHAT counts accesses +per offset, for example: + + + +This is fairly typical, for C++ code running on a 64-bit +platform. Here, we have aggregated access statistics for 5668 blocks, +all of size 56 bytes. Each byte has been accessed at least 5668 +times, except for offsets 12--15, 36--39 and 52--55. These are likely +to be alignment holes. + +Careful interpretation of the numbers reveals useful information. +Groups of N consecutive identical numbers that begin at an N-aligned +offset, for N being 2, 4 or 8, are likely to indicate an N-byte object +in the structure at that point. For example, the first 32 bytes of +this object are likely to have the layout + + + +As a counterexample, it's also clear that, whatever is at offset 32, +it is not a 32-bit value. That's because the last number of the group +(37422) is not the same as the first three (18883 18883 18883). + +This example leads one to enquire (by reading the source code) +whether the zeroes at 12--15 and 52--55 are alignment holes, and +whether 48--51 is indeed a 32-bit type. If so, it might be possible +to place what's at 48--51 at 12--15 instead, which would reduce +the object size from 56 to 48 bytes. + +Bear in mind that the above inferences are all only "maybes". That's +because they are based on dynamic data, not static analysis of the +object layout. For example, the zeroes might not be alignment +holes, but rather just parts of the structure which were not used +at all for this particular run. Experience shows that's unlikely +to be the case, but it could happen. + + + + + + + + + + + + +DHAT Command-line Options + +DHAT-specific command-line options are: + + + + + + + + + + At the end of the run, DHAT sorts the accumulated + allocation points according to some metric, and shows the + highest scoring entries. --show-top-n + controls how many entries are shown. The default of 10 is + quite small. For realistic applications you will probably need + to set it much higher, at least several hundred. + + + + + + + + + At the end of the run, DHAT sorts the accumulated + allocation points according to some metric, and shows the + highest scoring entries. --sort-by + selects the metric used for sorting: + max-bytes-live maximum live bytes [default] + tot-bytes-allocd total allocation (turnover) + max-blocks-live maximum live blocks + This controls the order in which allocation points are + displayed. You can choose to look at allocation points with + the highest maximum liveness, or the highest total turnover, or + by the highest number of live blocks. These give usefully + different pictures of program behaviour. For example, sorting + by maximum live blocks tends to show up allocation points + creating large numbers of small objects. + + + + + +One important point to note is that each allocation stack counts +as a seperate allocation point. Because stacks by default have 12 +frames, this tends to spread data out over multiple allocation points. +You may want to use the flag --num-callers=4 or some such small +number, to reduce the spreading. + + + + + + diff --git a/exp-dhat/tests/Makefile.am b/exp-dhat/tests/Makefile.am new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/exp-dhat/tests/Makefile.am @@ -0,0 +1 @@ + diff --git a/exp-ptrcheck.supp b/exp-ptrcheck.supp index 83dcf29..fd077d6 100644 --- a/exp-ptrcheck.supp +++ b/exp-ptrcheck.supp @@ -55,3 +55,33 @@ fun:(below main) } + +# Invalid read of size 16 +# at 0x5643A5C: ??? (strcpy.S:94) +# by 0x50C6A99: XtResolvePathname (in /usr/lib/libXt.so.6.0.0) +# by 0x50C3856: XtScreenDatabase (in /usr/lib/libXt.so.6.0.0) +# by 0x50C4386: _XtDisplayInitialize (in /usr/lib/libXt.so.6.0.0) +{ + Ubuntu 10.04 x86_64, SSEised strcpy, can't intercept + exp-ptrcheck:Heap + obj:/*lib*/libc-2.*so* + obj:/*lib*/libX*so* +} +{ + Ubuntu 10.04 x86_64, SSEised strcpy, can't intercept - 2 + exp-ptrcheck:Heap + obj:/*lib*/libc-2.*so* + obj:/*lib*/libICE*so* +} +{ + Ubuntu 10.04 x86_64, SSEised strcpy, can't intercept - 3 + exp-ptrcheck:Heap + obj:/*lib*/libc-2.*so* + obj:/*lib*/libglib*so* +} +{ + Ubuntu 10.04 x86_64, SSEised strcpy, can't intercept - 4 + exp-ptrcheck:Heap + obj:/*lib*/libc-2.*so* + obj:/*lib*/libfontconfig*so* +} diff --git a/exp-ptrcheck/Makefile.am b/exp-ptrcheck/Makefile.am index 5a9ffa4..3ccc478 100644 --- a/exp-ptrcheck/Makefile.am +++ b/exp-ptrcheck/Makefile.am @@ -38,6 +38,13 @@ exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ $(EXP_PTRCHECK_SOURCES_COMMON) @@ -51,6 +58,12 @@ exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif #---------------------------------------------------------------------------- @@ -79,6 +92,7 @@ vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \ vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) + if VGCONF_HAVE_PLATFORM_SEC vgpreload_exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = \ $(VGPRELOAD_EXP_PTRCHECK_SOURCES_COMMON) diff --git a/exp-ptrcheck/h_intercepts.c b/exp-ptrcheck/h_intercepts.c index 2b2cc19..54fbc62 100644 --- a/exp-ptrcheck/h_intercepts.c +++ b/exp-ptrcheck/h_intercepts.c @@ -7,7 +7,7 @@ This file is part of Ptrcheck, a Valgrind tool for checking pointer use in programs. - Copyright (C) 2003-2009 Nicholas Nethercote + Copyright (C) 2003-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -45,6 +45,60 @@ them in the same order as in mc_replace_strmem.c. */ +#define STRRCHR(soname, fnname) \ + char* VG_REPLACE_FUNCTION_ZU(soname,fnname)( const char* s, int c ); \ + char* VG_REPLACE_FUNCTION_ZU(soname,fnname)( const char* s, int c ) \ + { \ + UChar ch = (UChar)((UInt)c); \ + UChar* p = (UChar*)s; \ + UChar* last = NULL; \ + while (True) { \ + if (*p == ch) last = p; \ + if (*p == 0) return last; \ + p++; \ + } \ + } + +// Apparently rindex() is the same thing as strrchr() +STRRCHR(VG_Z_LIBC_SONAME, strrchr) +STRRCHR(VG_Z_LIBC_SONAME, rindex) +#if defined(VGO_linux) +STRRCHR(VG_Z_LIBC_SONAME, __GI_strrchr) +STRRCHR(VG_Z_LD_LINUX_SO_2, rindex) +#elif defined(VGO_darwin) +STRRCHR(VG_Z_DYLD, strrchr) +STRRCHR(VG_Z_DYLD, rindex) +#endif + + +#define STRCHR(soname, fnname) \ + char* VG_REPLACE_FUNCTION_ZU(soname,fnname) ( const char* s, int c ); \ + char* VG_REPLACE_FUNCTION_ZU(soname,fnname) ( const char* s, int c ) \ + { \ + UChar ch = (UChar)((UInt)c); \ + UChar* p = (UChar*)s; \ + while (True) { \ + if (*p == ch) return p; \ + if (*p == 0) return NULL; \ + p++; \ + } \ + } + +// Apparently index() is the same thing as strchr() +STRCHR(VG_Z_LIBC_SONAME, strchr) +STRCHR(VG_Z_LIBC_SONAME, index) +#if defined(VGO_linux) +STRCHR(VG_Z_LIBC_SONAME, __GI_strchr) +STRCHR(VG_Z_LD_LINUX_SO_2, strchr) +STRCHR(VG_Z_LD_LINUX_SO_2, index) +STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, strchr) +STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, index) +#elif defined(VGO_darwin) +STRCHR(VG_Z_DYLD, strchr) +STRCHR(VG_Z_DYLD, index) +#endif + + #define STRNLEN(soname, fnname) \ SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname) ( const char* str, SizeT n ); \ SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname) ( const char* str, SizeT n ) \ @@ -72,12 +126,61 @@ STRNLEN(VG_Z_LIBC_SONAME, strnlen) STRLEN(VG_Z_LIBC_SONAME, strlen) #if defined(VGO_linux) +STRLEN(VG_Z_LIBC_SONAME, __GI_strlen) STRLEN(VG_Z_LD_LINUX_SO_2, strlen) STRLEN(VG_Z_LD_LINUX_X86_64_SO_2, strlen) STRLEN(VG_Z_LD_SO_1, strlen) #endif +#define STRCPY(soname, fnname) \ + char* VG_REPLACE_FUNCTION_ZU(soname, fnname) ( char* dst, const char* src ); \ + char* VG_REPLACE_FUNCTION_ZU(soname, fnname) ( char* dst, const char* src ) \ + { \ + Char* dst_orig = dst; \ + \ + while (*src) *dst++ = *src++; \ + *dst = 0; \ + \ + return dst_orig; \ + } + +STRCPY(VG_Z_LIBC_SONAME, strcpy) +#if defined(VGO_linux) +STRCPY(VG_Z_LIBC_SONAME, __GI_strcpy) +#elif defined(VGO_darwin) +STRCPY(VG_Z_DYLD, strcpy) +#endif + + +#define STRNCMP(soname, fnname) \ + int VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + ( const char* s1, const char* s2, SizeT nmax ); \ + int VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + ( const char* s1, const char* s2, SizeT nmax ) \ + { \ + SizeT n = 0; \ + while (True) { \ + if (n >= nmax) return 0; \ + if (*s1 == 0 && *s2 == 0) return 0; \ + if (*s1 == 0) return -1; \ + if (*s2 == 0) return 1; \ + \ + if (*(unsigned char*)s1 < *(unsigned char*)s2) return -1; \ + if (*(unsigned char*)s1 > *(unsigned char*)s2) return 1; \ + \ + s1++; s2++; n++; \ + } \ + } + +STRNCMP(VG_Z_LIBC_SONAME, strncmp) +#if defined(VGO_linux) +STRNCMP(VG_Z_LIBC_SONAME, __GI_strncmp) +#elif defined(VGO_darwin) +STRNCMP(VG_Z_DYLD, strncmp) +#endif + + #define STRCMP(soname, fnname) \ int VG_REPLACE_FUNCTION_ZU(soname,fnname) \ ( const char* s1, const char* s2 ); \ @@ -100,11 +203,30 @@ STRLEN(VG_Z_LD_SO_1, strlen) STRCMP(VG_Z_LIBC_SONAME, strcmp) #if defined(VGO_linux) +STRCMP(VG_Z_LIBC_SONAME, __GI_strcmp) STRCMP(VG_Z_LD_LINUX_X86_64_SO_2, strcmp) STRCMP(VG_Z_LD64_SO_1, strcmp) #endif +#define MEMCHR(soname, fnname) \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) (const void *s, int c, SizeT n); \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) (const void *s, int c, SizeT n) \ + { \ + SizeT i; \ + UChar c0 = (UChar)c; \ + UChar* p = (UChar*)s; \ + for (i = 0; i < n; i++) \ + if (p[i] == c0) return (void*)(&p[i]); \ + return NULL; \ + } + +MEMCHR(VG_Z_LIBC_SONAME, memchr) +#if defined(VGO_darwin) +MEMCHR(VG_Z_DYLD, memchr) +#endif + + #define MEMCPY(soname, fnname) \ void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ ( void *dst, const void *src, SizeT sz ); \ @@ -173,6 +295,104 @@ STPCPY(VG_Z_LD_LINUX_X86_64_SO_2, stpcpy) #endif +/* Find the first occurrence of C in S. */ +#define GLIBC232_RAWMEMCHR(soname, fnname) \ + char* VG_REPLACE_FUNCTION_ZU(soname,fnname) (const char* s, int c_in); \ + char* VG_REPLACE_FUNCTION_ZU(soname,fnname) (const char* s, int c_in) \ + { \ + unsigned char c = (unsigned char) c_in; \ + unsigned char* char_ptr = (unsigned char *)s; \ + while (1) { \ + if (*char_ptr == c) return char_ptr; \ + char_ptr++; \ + } \ + } + +GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, rawmemchr) +#if defined (VGO_linux) +GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, __GI___rawmemchr) +#endif + + +#define STRSTR(soname, fnname) \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* haystack, void* needle); \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* haystack, void* needle) \ + { \ + UChar* h = (UChar*)haystack; \ + UChar* n = (UChar*)needle; \ + \ + /* find the length of n, not including terminating zero */ \ + UWord nlen = 0; \ + while (n[nlen]) nlen++; \ + \ + /* if n is the empty string, match immediately. */ \ + if (nlen == 0) return h; \ + \ + /* assert(nlen >= 1); */ \ + UChar n0 = n[0]; \ + \ + while (1) { \ + UChar hh = *h; \ + if (hh == 0) return NULL; \ + if (hh != n0) { h++; continue; } \ + \ + UWord i; \ + for (i = 0; i < nlen; i++) { \ + if (n[i] != h[i]) \ + break; \ + } \ + /* assert(i >= 0 && i <= nlen); */ \ + if (i == nlen) \ + return h; \ + \ + h++; \ + } \ + } + +#if defined(VGO_linux) +STRSTR(VG_Z_LIBC_SONAME, strstr) +#endif + + +#define STRPBRK(soname, fnname) \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* sV, void* acceptV); \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* sV, void* acceptV) \ + { \ + UChar* s = (UChar*)sV; \ + UChar* accept = (UChar*)acceptV; \ + \ + /* find the length of 'accept', not including terminating zero */ \ + UWord nacc = 0; \ + while (accept[nacc]) nacc++; \ + \ + /* if n is the empty string, fail immediately. */ \ + if (nacc == 0) return NULL; \ + \ + /* assert(nacc >= 1); */ \ + while (1) { \ + UWord i; \ + UChar sc = *s; \ + if (sc == 0) \ + break; \ + for (i = 0; i < nacc; i++) { \ + if (sc == accept[i]) \ + return s; \ + } \ + s++; \ + } \ + \ + return NULL; \ + } + +#if defined(VGO_linux) +STRPBRK(VG_Z_LIBC_SONAME, strpbrk) +#endif + + /*--------------------------------------------------------------------*/ /*--- end pc_intercepts.c ---*/ /*--------------------------------------------------------------------*/ diff --git a/exp-ptrcheck/h_main.c b/exp-ptrcheck/h_main.c index 3865ae6..a481616 100644 --- a/exp-ptrcheck/h_main.c +++ b/exp-ptrcheck/h_main.c @@ -11,12 +11,12 @@ Initial version (Annelid): - Copyright (C) 2003-2009 Nicholas Nethercote + Copyright (C) 2003-2010 Nicholas Nethercote njn@valgrind.org Valgrind-3.X port: - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -559,7 +559,7 @@ static void pp_curr_ExeContext(void) } #endif -#if defined(VGA_x86) || defined(VGA_ppc32) +#if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_arm) # define SHMEM_SECMAP_MASK 0xFFFC # define SHMEM_SECMAP_SHIFT 2 # define SHMEM_IS_WORD_ALIGNED(_a) VG_IS_4_ALIGNED(_a) @@ -1271,24 +1271,29 @@ typedef #if defined(VGA_x86) # include "libvex_guest_x86.h" -# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestX86State) +# define PC_SIZEOF_GUEST_STATE sizeof(VexGuestX86State) #endif #if defined(VGA_amd64) # include "libvex_guest_amd64.h" -# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestAMD64State) +# define PC_SIZEOF_GUEST_STATE sizeof(VexGuestAMD64State) # define PC_OFF_FS_ZERO offsetof(VexGuestAMD64State,guest_FS_ZERO) # define PC_SZB_FS_ZERO sizeof( ((VexGuestAMD64State*)0)->guest_FS_ZERO) #endif #if defined(VGA_ppc32) # include "libvex_guest_ppc32.h" -# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC32State) +# define PC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC32State) #endif #if defined(VGA_ppc64) # include "libvex_guest_ppc64.h" -# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC64State) +# define PC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC64State) +#endif + +#if defined(VGA_arm) +# include "libvex_guest_arm.h" +# define PC_SIZEOF_GUEST_STATE sizeof(VexGuestARMState) #endif @@ -1806,6 +1811,27 @@ static void get_IntRegInfo ( /*OUT*/IntRegInfo* iii, Int offset, Int szB ) tl_assert(0); # undef GOF + /* -------------------- arm -------------------- */ + +# elif defined(VGA_arm) + +# define GOF(_fieldname) \ + (offsetof(VexGuestARMState,guest_##_fieldname)) + + Int o = offset; + Int sz = szB; + Bool is4 = sz == 4; + Bool is8 = sz == 8; + + tl_assert(sz > 0); + tl_assert(host_is_big_endian()); + + /* Set default state to "does not intersect any int register". */ + VG_(memset)( iii, 0, sizeof(*iii) ); + + VG_(printf)("get_IntRegInfo(arm):failing on (%d,%d)\n", o, sz); + tl_assert(0); + # else # error "FIXME: not implemented for this architecture" @@ -1888,6 +1914,14 @@ static Bool is_integer_guest_reg_array ( IRRegArray* arr ) VG_(printf)("\n"); tl_assert(0); + /* -------------------- arm -------------------- */ +# elif defined(VGA_arm) + /* There are no rotating register sections on ARM. */ + VG_(printf)("is_integer_guest_reg_array(arm): unhandled: "); + ppIRRegArray(arr); + VG_(printf)("\n"); + tl_assert(0); + # else # error "FIXME: not implemented for this architecture" # endif @@ -1939,7 +1973,7 @@ static void put_guest_intreg ( ThreadId tid, Int shadowNo, static void init_shadow_registers ( ThreadId tid ) { Int i, wordSzB = sizeof(UWord); - for (i = 0; i < MC_SIZEOF_GUEST_STATE-wordSzB; i += wordSzB) { + for (i = 0; i < PC_SIZEOF_GUEST_STATE-wordSzB; i += wordSzB) { put_guest_intreg( tid, 1, i, wordSzB, (UWord)UNKNOWN ); } } @@ -2207,7 +2241,14 @@ static void setup_post_syscall_table ( void ) ADD(0, __NR_dup); ADD(0, __NR_dup2); ADD(0, __NR_epoll_create); +# if defined(__NR_epoll_create1) ADD(0, __NR_epoll_create1); +# endif + ADD(0, __NR_epoll_ctl); +# if defined(__NR_epoll_pwait) + ADD(0, __NR_epoll_pwait); +# endif + ADD(0, __NR_epoll_wait); ADD(0, __NR_execve); /* presumably we see this because the call failed? */ ADD(0, __NR_exit); /* hmm, why are we still alive? */ ADD(0, __NR_exit_group); @@ -2275,6 +2316,7 @@ static void setup_post_syscall_table ( void ) # endif ADD(0, __NR_getrlimit); ADD(0, __NR_getrusage); + ADD(0, __NR_getsid); # if defined(__NR_getsockname) ADD(0, __NR_getsockname); # endif @@ -2288,12 +2330,19 @@ static void setup_post_syscall_table ( void ) ADD(0, __NR_getuid32); # endif ADD(0, __NR_getxattr); +# if defined(__NR_ioperm) + ADD(0, __NR_ioperm); +# endif ADD(0, __NR_inotify_add_watch); ADD(0, __NR_inotify_init); +# if defined(__NR_inotify_init1) + ADD(0, __NR_inotify_init1); +# endif ADD(0, __NR_inotify_rm_watch); ADD(0, __NR_ioctl); // ioctl -- assuming no pointers returned ADD(0, __NR_ioprio_get); ADD(0, __NR_kill); + ADD(0, __NR_lgetxattr); ADD(0, __NR_link); # if defined(__NR_listen) ADD(0, __NR_listen); @@ -2306,12 +2355,24 @@ static void setup_post_syscall_table ( void ) ADD(0, __NR_madvise); ADD(0, __NR_mkdir); ADD(0, __NR_mlock); + ADD(0, __NR_mlockall); ADD(0, __NR_mprotect); +# if defined(__NR_mq_open) + ADD(0, __NR_mq_open); + ADD(0, __NR_mq_unlink); + ADD(0, __NR_mq_timedsend); + ADD(0, __NR_mq_timedreceive); + ADD(0, __NR_mq_notify); + ADD(0, __NR_mq_getsetattr); +# endif ADD(0, __NR_munmap); // die_mem_munmap already called, segment remove); ADD(0, __NR_nanosleep); ADD(0, __NR_open); ADD(0, __NR_personality); ADD(0, __NR_pipe); +# if defined(__NR_pipe2) + ADD(0, __NR_pipe2); +# endif ADD(0, __NR_poll); ADD(0, __NR_prctl); ADD(0, __NR_pread64); @@ -2350,6 +2411,7 @@ static void setup_post_syscall_table ( void ) # if defined(__NR_semop) ADD(0, __NR_semop); # endif + ADD(0, __NR_sendfile); # if defined(__NR_sendto) ADD(0, __NR_sendto); # endif @@ -2361,9 +2423,11 @@ static void setup_post_syscall_table ( void ) ADD(0, __NR_set_thread_area); # endif ADD(0, __NR_set_tid_address); + ADD(0, __NR_setgid); ADD(0, __NR_setfsgid); ADD(0, __NR_setfsuid); ADD(0, __NR_setgid); + ADD(0, __NR_setgroups); ADD(0, __NR_setitimer); ADD(0, __NR_setpgid); ADD(0, __NR_setpriority); @@ -2681,10 +2745,19 @@ static inline Bool looks_like_a_pointer(Addr a) { # if defined(VGA_x86) || defined(VGA_ppc32) tl_assert(sizeof(UWord) == 4); - return (a > 0x01000000UL && a < 0xFF000000UL); + return (a > 0x800000UL && a < 0xFF000000UL); + # elif defined(VGA_amd64) || defined(VGA_ppc64) tl_assert(sizeof(UWord) == 8); return (a >= 16 * 0x10000UL && a < 0xFF00000000000000UL); + +# elif defined(VGA_arm) + /* Unfortunately arm-linux seems to load the exe at very low, at + 0x8000, so we have to assume any value above that is a pointer, + which is pretty dismal. */ + tl_assert(sizeof(UWord) == 4); + return (a >= 0x00008000UL && a < 0xFF000000UL); + # else # error "Unsupported architecture" # endif @@ -4139,19 +4212,19 @@ void instrument_arithop ( PCEnv* pce, /* FIXME: for Shl/Shr/Sar, really should do a test on the 2nd arg, so that shift by zero preserves the original value. */ - case Iop_Shl32: goto n32; - case Iop_Sar32: goto n32; - case Iop_Shr32: goto n32; - case Iop_16Uto32: goto n32; - case Iop_16Sto32: goto n32; - case Iop_F64toI32: goto n32; - case Iop_16HLto32: goto n32; - case Iop_MullS16: goto n32; - case Iop_MullU16: goto n32; + case Iop_Shl32: goto n32; + case Iop_Sar32: goto n32; + case Iop_Shr32: goto n32; + case Iop_16Uto32: goto n32; + case Iop_16Sto32: goto n32; + case Iop_F64toI32S: goto n32; + case Iop_16HLto32: goto n32; + case Iop_MullS16: goto n32; + case Iop_MullU16: goto n32; case Iop_PRemC3210F64: goto n32; - case Iop_DivU32: goto n32; - case Iop_DivS32: goto n32; - case Iop_V128to32: goto n32; + case Iop_DivU32: goto n32; + case Iop_DivS32: goto n32; + case Iop_V128to32: goto n32; /* cases where result range is very limited and clearly cannot be a pointer */ @@ -4254,7 +4327,7 @@ void instrument_arithop ( PCEnv* pce, case Iop_32HLto64: goto n64; case Iop_DivModU64to32: goto n64; case Iop_DivModS64to32: goto n64; - case Iop_F64toI64: goto n64; + case Iop_F64toI64S: goto n64; case Iop_MullS32: goto n64; case Iop_MullU32: goto n64; case Iop_DivU64: goto n64; @@ -4281,7 +4354,7 @@ void instrument_arithop ( PCEnv* pce, case Iop_CmpEQ32x2: case Iop_CmpEQ16x4: case Iop_CmpGT8Sx8: case Iop_CmpGT32Sx2: case Iop_CmpGT16Sx4: case Iop_MulHi16Sx4: case Iop_Mul16x4: case Iop_ShlN32x2: case Iop_ShlN16x4: - case Iop_SarN32x2: case Iop_SarN16x4: case Iop_ShrN32x2: + case Iop_SarN32x2: case Iop_SarN16x4: case Iop_ShrN32x2: case Iop_ShrN8x8: case Iop_ShrN16x4: case Iop_Sub8x8: case Iop_Sub32x2: case Iop_QSub8Sx8: case Iop_QSub16Sx4: case Iop_QSub8Ux8: case Iop_QSub16Ux4: case Iop_Sub16x4: case Iop_InterleaveHI8x8: @@ -4330,6 +4403,323 @@ static void gen_nonptr_or_unknown_for_III( PCEnv* pce, IntRegInfo* iii ) } } + +/* schemeS helper for doing stores, pulled out into a function because + it needs to handle both normal stores and store-conditionals. + Returns False if we see a case we don't know how to handle. +*/ +static Bool schemeS_store ( PCEnv* pce, + IRExpr* data, IRExpr* addr, IRTemp resSC ) +{ + /* We have: STle(addr) = data + if data is int-word sized, do + check_store4(addr, addr#, data, data#) + for all other stores + check_store{1,2}(addr, addr#, data) + + The helper actually *does* the store, so that it can do the + post-hoc ugly hack of inspecting and "improving" the shadow data + after the store, in the case where it isn't an aligned word + store. + + Only word-sized values are shadowed. If this is a + store-conditional, .resSC will denote a non-word-typed temp, and + so we don't need to shadow it. Assert about the type, tho. + However, since we're not re-emitting the original IRStmt_Store, + but rather doing it as part of the helper function, we need to + actually do a SC in the helper, and assign the result bit to + .resSC. Ugly. + */ + IRType d_ty = typeOfIRExpr(pce->sb->tyenv, data); + IRExpr* addrv = schemeEw_Atom( pce, addr ); + if (resSC != IRTemp_INVALID) { + tl_assert(typeOfIRTemp(pce->sb->tyenv, resSC) == Ity_I1); + /* viz, not something we want to shadow */ + /* also, throw out all store-conditional cases that + we can't handle */ + if (pce->gWordTy == Ity_I32 && d_ty != Ity_I32) + return False; + if (pce->gWordTy == Ity_I64 && d_ty != Ity_I32 && d_ty != Ity_I64) + return False; + } + if (pce->gWordTy == Ity_I32) { + /* ------ 32 bit host/guest (cough, cough) ------ */ + switch (d_ty) { + /* Integer word case */ + case Ity_I32: { + IRExpr* datav = schemeEw_Atom( pce, data ); + if (resSC == IRTemp_INVALID) { + /* "normal" store */ + gen_dirty_v_WWWW( pce, + &check_store4_P, "check_store4_P", + addr, addrv, data, datav ); + } else { + /* store-conditional; need to snarf the success bit */ + IRTemp resSC32 + = gen_dirty_W_WWWW( pce, + &check_store4C_P, + "check_store4C_P", + addr, addrv, data, datav ); + /* presumably resSC32 will really be Ity_I32. In + any case we'll get jumped by the IR sanity + checker if it's not, when it sees the + following statement. */ + assign( 'I', pce, resSC, unop(Iop_32to1, mkexpr(resSC32)) ); + } + break; + } + /* Integer subword cases */ + case Ity_I16: + gen_dirty_v_WWW( pce, + &check_store2, "check_store2", + addr, addrv, + uwiden_to_host_word( pce, data )); + break; + case Ity_I8: + gen_dirty_v_WWW( pce, + &check_store1, "check_store1", + addr, addrv, + uwiden_to_host_word( pce, data )); + break; + /* 64-bit float. Pass store data in 2 32-bit pieces. */ + case Ity_F64: { + IRAtom* d64 = assignNew( 'I', pce, Ity_I64, + unop(Iop_ReinterpF64asI64, data) ); + IRAtom* dLo32 = assignNew( 'I', pce, Ity_I32, + unop(Iop_64to32, d64) ); + IRAtom* dHi32 = assignNew( 'I', pce, Ity_I32, + unop(Iop_64HIto32, d64) ); + gen_dirty_v_WWWW( pce, + &check_store8_ms4B_ls4B, + "check_store8_ms4B_ls4B", + addr, addrv, dHi32, dLo32 ); + break; + } + /* 32-bit float. We can just use _store4, but need + to futz with the argument type. */ + case Ity_F32: { + IRAtom* i32 = assignNew( 'I', pce, Ity_I32, + unop(Iop_ReinterpF32asI32, + data ) ); + gen_dirty_v_WWW( pce, + &check_store4, + "check_store4", + addr, addrv, i32 ); + break; + } + /* 64-bit int. Pass store data in 2 32-bit pieces. */ + case Ity_I64: { + IRAtom* dLo32 = assignNew( 'I', pce, Ity_I32, + unop(Iop_64to32, data) ); + IRAtom* dHi32 = assignNew( 'I', pce, Ity_I32, + unop(Iop_64HIto32, data) ); + gen_dirty_v_WWWW( pce, + &check_store8_ms4B_ls4B, + "check_store8_ms4B_ls4B", + addr, addrv, dHi32, dLo32 ); + break; + } + /* 128-bit vector. Pass store data in 4 32-bit pieces. + This is all very ugly and inefficient, but it is + hard to better without considerably complicating the + store-handling schemes. */ + case Ity_V128: { + IRAtom* dHi64 = assignNew( 'I', pce, Ity_I64, + unop(Iop_V128HIto64, data) ); + IRAtom* dLo64 = assignNew( 'I', pce, Ity_I64, + unop(Iop_V128to64, data) ); + IRAtom* w3 = assignNew( 'I', pce, Ity_I32, + unop(Iop_64HIto32, dHi64) ); + IRAtom* w2 = assignNew( 'I', pce, Ity_I32, + unop(Iop_64to32, dHi64) ); + IRAtom* w1 = assignNew( 'I', pce, Ity_I32, + unop(Iop_64HIto32, dLo64) ); + IRAtom* w0 = assignNew( 'I', pce, Ity_I32, + unop(Iop_64to32, dLo64) ); + gen_dirty_v_6W( pce, + &check_store16_ms4B_4B_4B_ls4B, + "check_store16_ms4B_4B_4B_ls4B", + addr, addrv, w3, w2, w1, w0 ); + break; + } + default: + ppIRType(d_ty); tl_assert(0); + } + } else { + /* ------ 64 bit host/guest (cough, cough) ------ */ + switch (d_ty) { + /* Integer word case */ + case Ity_I64: { + IRExpr* datav = schemeEw_Atom( pce, data ); + if (resSC == IRTemp_INVALID) { + /* "normal" store */ + gen_dirty_v_WWWW( pce, + &check_store8_P, "check_store8_P", + addr, addrv, data, datav ); + } else { + IRTemp resSC64 + = gen_dirty_W_WWWW( pce, + &check_store8C_P, + "check_store8C_P", + addr, addrv, data, datav ); + assign( 'I', pce, resSC, unop(Iop_64to1, mkexpr(resSC64)) ); + } + break; + } + /* Integer subword cases */ + case Ity_I32: + if (resSC == IRTemp_INVALID) { + /* "normal" store */ + gen_dirty_v_WWW( pce, + &check_store4, "check_store4", + addr, addrv, + uwiden_to_host_word( pce, data )); + } else { + /* store-conditional; need to snarf the success bit */ + IRTemp resSC64 + = gen_dirty_W_WWW( pce, + &check_store4C, + "check_store4C", + addr, addrv, + uwiden_to_host_word( pce, data )); + assign( 'I', pce, resSC, unop(Iop_64to1, mkexpr(resSC64)) ); + } + break; + case Ity_I16: + gen_dirty_v_WWW( pce, + &check_store2, "check_store2", + addr, addrv, + uwiden_to_host_word( pce, data )); + break; + case Ity_I8: + gen_dirty_v_WWW( pce, + &check_store1, "check_store1", + addr, addrv, + uwiden_to_host_word( pce, data )); + break; + /* 128-bit vector. Pass store data in 2 64-bit pieces. */ + case Ity_V128: { + IRAtom* dHi64 = assignNew( 'I', pce, Ity_I64, + unop(Iop_V128HIto64, data) ); + IRAtom* dLo64 = assignNew( 'I', pce, Ity_I64, + unop(Iop_V128to64, data) ); + gen_dirty_v_WWWW( pce, + &check_store16_ms8B_ls8B, + "check_store16_ms8B_ls8B", + addr, addrv, dHi64, dLo64 ); + break; + } + /* 64-bit float. */ + case Ity_F64: { + IRAtom* dI = assignNew( 'I', pce, Ity_I64, + unop(Iop_ReinterpF64asI64, + data ) ); + gen_dirty_v_WWW( pce, + &check_store8_all8B, + "check_store8_all8B", + addr, addrv, dI ); + break; + } + /* 32-bit float. We can just use _store4, but need + to futz with the argument type. */ + case Ity_F32: { + IRAtom* i32 = assignNew( 'I', pce, Ity_I32, + unop(Iop_ReinterpF32asI32, + data ) ); + IRAtom* i64 = assignNew( 'I', pce, Ity_I64, + unop(Iop_32Uto64, + i32 ) ); + gen_dirty_v_WWW( pce, + &check_store4, + "check_store4", + addr, addrv, i64 ); + break; + } + default: + ppIRType(d_ty); tl_assert(0); + } + } + /* And don't copy the original, since the helper does the store. + Ick. */ + return True; /* store was successfully instrumented */ +} + + +/* schemeS helper for doing loads, pulled out into a function because + it needs to handle both normal loads and load-linked's. +*/ +static void schemeS_load ( PCEnv* pce, IRExpr* addr, IRType e_ty, IRTemp dstv ) +{ + HChar* h_nm = NULL; + void* h_fn = NULL; + IRExpr* addrv = NULL; + if (e_ty == pce->gWordTy) { + tl_assert(dstv != IRTemp_INVALID); + } else { + tl_assert(dstv == IRTemp_INVALID); + } + if (pce->gWordTy == Ity_I32) { + /* 32 bit host/guest (cough, cough) */ + switch (e_ty) { + /* Ity_I32: helper returns shadow value. */ + case Ity_I32: h_fn = &check_load4_P; + h_nm = "check_load4_P"; break; + /* all others: helper does not return a shadow + value. */ + case Ity_V128: h_fn = &check_load16; + h_nm = "check_load16"; break; + case Ity_I64: + case Ity_F64: h_fn = &check_load8; + h_nm = "check_load8"; break; + case Ity_F32: h_fn = &check_load4; + h_nm = "check_load4"; break; + case Ity_I16: h_fn = &check_load2; + h_nm = "check_load2"; break; + case Ity_I8: h_fn = &check_load1; + h_nm = "check_load1"; break; + default: ppIRType(e_ty); tl_assert(0); + } + addrv = schemeEw_Atom( pce, addr ); + if (e_ty == Ity_I32) { + assign( 'I', pce, dstv, + mkexpr( gen_dirty_W_WW( pce, h_fn, h_nm, + addr, addrv )) ); + } else { + gen_dirty_v_WW( pce, NULL, h_fn, h_nm, addr, addrv ); + } + } else { + /* 64 bit host/guest (cough, cough) */ + switch (e_ty) { + /* Ity_I64: helper returns shadow value. */ + case Ity_I64: h_fn = &check_load8_P; + h_nm = "check_load8_P"; break; + /* all others: helper does not return a shadow + value. */ + case Ity_V128: h_fn = &check_load16; + h_nm = "check_load16"; break; + case Ity_F64: h_fn = &check_load8; + h_nm = "check_load8"; break; + case Ity_F32: + case Ity_I32: h_fn = &check_load4; + h_nm = "check_load4"; break; + case Ity_I16: h_fn = &check_load2; + h_nm = "check_load2"; break; + case Ity_I8: h_fn = &check_load1; + h_nm = "check_load1"; break; + default: ppIRType(e_ty); tl_assert(0); + } + addrv = schemeEw_Atom( pce, addr ); + if (e_ty == Ity_I64) { + assign( 'I', pce, dstv, + mkexpr( gen_dirty_W_WW( pce, h_fn, h_nm, + addr, addrv )) ); + } else { + gen_dirty_v_WW( pce, NULL, h_fn, h_nm, addr, addrv ); + } + } +} + + /* Generate into 'pce', instrumentation for 'st'. Also copy 'st' itself into 'pce' (the caller does not do so). This is somewhat complex and relies heavily on the assumption that the incoming IR @@ -4569,6 +4959,29 @@ static void schemeS ( PCEnv* pce, IRStmt* st ) break; } + case Ist_LLSC: { + if (st->Ist.LLSC.storedata == NULL) { + /* LL */ + IRTemp dst = st->Ist.LLSC.result; + IRType dataTy = typeOfIRTemp(pce->sb->tyenv, dst); + Bool isWord = dataTy == pce->gWordTy; + IRTemp dstv = isWord ? newShadowTmp( pce, dst ) + : IRTemp_INVALID; + schemeS_load( pce, st->Ist.LLSC.addr, dataTy, dstv ); + /* copy the original -- must happen after the helper call */ + stmt( 'C', pce, st ); + } else { + /* SC */ + schemeS_store( pce, + st->Ist.LLSC.storedata, + st->Ist.LLSC.addr, + st->Ist.LLSC.result ); + /* Don't copy the original, since the helper does the + store itself. */ + } + break; + } + case Ist_Dirty: { Int i; IRDirty* di; @@ -4700,244 +5113,15 @@ static void schemeS ( PCEnv* pce, IRStmt* st ) } /* case Ist_Put */ case Ist_Store: { - /* We have: STle(addr) = data - if data is int-word sized, do - check_store4(addr, addr#, data, data#) - for all other stores - check_store{1,2}(addr, addr#, data) - - The helper actually *does* the store, so that it can do - the post-hoc ugly hack of inspecting and "improving" the - shadow data after the store, in the case where it isn't an - aligned word store. - - Only word-sized values are shadowed. If this is a - store-conditional, .resSC will denote a non-word-typed - temp, and so we don't need to shadow it. Assert about the - type, tho. However, since we're not re-emitting the - original IRStmt_Store, but rather doing it as part of the - helper function, we need to actually do a SC in the - helper, and assign the result bit to .resSC. Ugly. - */ - IRExpr* data = st->Ist.Store.data; - IRExpr* addr = st->Ist.Store.addr; - IRType d_ty = typeOfIRExpr(pce->sb->tyenv, data); - IRExpr* addrv = schemeEw_Atom( pce, addr ); - IRTemp resSC = st->Ist.Store.resSC; - if (resSC != IRTemp_INVALID) { - tl_assert(typeOfIRTemp(pce->sb->tyenv, resSC) == Ity_I1); - /* viz, not something we want to shadow */ - /* also, throw out all store-conditional cases that - we can't handle */ - if (pce->gWordTy == Ity_I32 && d_ty != Ity_I32) - goto unhandled; - if (pce->gWordTy == Ity_I64 && d_ty != Ity_I32 && d_ty != Ity_I64) - goto unhandled; - } - if (pce->gWordTy == Ity_I32) { - /* ------ 32 bit host/guest (cough, cough) ------ */ - switch (d_ty) { - /* Integer word case */ - case Ity_I32: { - IRExpr* datav = schemeEw_Atom( pce, data ); - if (resSC == IRTemp_INVALID) { - /* "normal" store */ - gen_dirty_v_WWWW( pce, - &check_store4_P, "check_store4_P", - addr, addrv, data, datav ); - } else { - /* store-conditional; need to snarf the success bit */ - IRTemp resSC32 - = gen_dirty_W_WWWW( pce, - &check_store4C_P, - "check_store4C_P", - addr, addrv, data, datav ); - /* presumably resSC32 will really be Ity_I32. In - any case we'll get jumped by the IR sanity - checker if it's not, when it sees the - following statement. */ - assign( 'I', pce, resSC, unop(Iop_32to1, mkexpr(resSC32)) ); - } - break; - } - /* Integer subword cases */ - case Ity_I16: - gen_dirty_v_WWW( pce, - &check_store2, "check_store2", - addr, addrv, - uwiden_to_host_word( pce, data )); - break; - case Ity_I8: - gen_dirty_v_WWW( pce, - &check_store1, "check_store1", - addr, addrv, - uwiden_to_host_word( pce, data )); - break; - /* 64-bit float. Pass store data in 2 32-bit pieces. */ - case Ity_F64: { - IRAtom* d64 = assignNew( 'I', pce, Ity_I64, - unop(Iop_ReinterpF64asI64, data) ); - IRAtom* dLo32 = assignNew( 'I', pce, Ity_I32, - unop(Iop_64to32, d64) ); - IRAtom* dHi32 = assignNew( 'I', pce, Ity_I32, - unop(Iop_64HIto32, d64) ); - gen_dirty_v_WWWW( pce, - &check_store8_ms4B_ls4B, - "check_store8_ms4B_ls4B", - addr, addrv, dHi32, dLo32 ); - break; - } - /* 32-bit float. We can just use _store4, but need - to futz with the argument type. */ - case Ity_F32: { - IRAtom* i32 = assignNew( 'I', pce, Ity_I32, - unop(Iop_ReinterpF32asI32, - data ) ); - gen_dirty_v_WWW( pce, - &check_store4, - "check_store4", - addr, addrv, i32 ); - break; - } - /* 64-bit int. Pass store data in 2 32-bit pieces. */ - case Ity_I64: { - IRAtom* dLo32 = assignNew( 'I', pce, Ity_I32, - unop(Iop_64to32, data) ); - IRAtom* dHi32 = assignNew( 'I', pce, Ity_I32, - unop(Iop_64HIto32, data) ); - gen_dirty_v_WWWW( pce, - &check_store8_ms4B_ls4B, - "check_store8_ms4B_ls4B", - addr, addrv, dHi32, dLo32 ); - break; - } - - /* 128-bit vector. Pass store data in 4 32-bit pieces. - This is all very ugly and inefficient, but it is - hard to better without considerably complicating the - store-handling schemes. */ - case Ity_V128: { - IRAtom* dHi64 = assignNew( 'I', pce, Ity_I64, - unop(Iop_V128HIto64, data) ); - IRAtom* dLo64 = assignNew( 'I', pce, Ity_I64, - unop(Iop_V128to64, data) ); - IRAtom* w3 = assignNew( 'I', pce, Ity_I32, - unop(Iop_64HIto32, dHi64) ); - IRAtom* w2 = assignNew( 'I', pce, Ity_I32, - unop(Iop_64to32, dHi64) ); - IRAtom* w1 = assignNew( 'I', pce, Ity_I32, - unop(Iop_64HIto32, dLo64) ); - IRAtom* w0 = assignNew( 'I', pce, Ity_I32, - unop(Iop_64to32, dLo64) ); - gen_dirty_v_6W( pce, - &check_store16_ms4B_4B_4B_ls4B, - "check_store16_ms4B_4B_4B_ls4B", - addr, addrv, w3, w2, w1, w0 ); - break; - } - - - default: - ppIRType(d_ty); tl_assert(0); - } - } else { - /* ------ 64 bit host/guest (cough, cough) ------ */ - switch (d_ty) { - /* Integer word case */ - case Ity_I64: { - IRExpr* datav = schemeEw_Atom( pce, data ); - if (resSC == IRTemp_INVALID) { - /* "normal" store */ - gen_dirty_v_WWWW( pce, - &check_store8_P, "check_store8_P", - addr, addrv, data, datav ); - } else { - IRTemp resSC64 - = gen_dirty_W_WWWW( pce, - &check_store8C_P, - "check_store8C_P", - addr, addrv, data, datav ); - assign( 'I', pce, resSC, unop(Iop_64to1, mkexpr(resSC64)) ); - } - break; - } - /* Integer subword cases */ - case Ity_I32: - if (resSC == IRTemp_INVALID) { - /* "normal" store */ - gen_dirty_v_WWW( pce, - &check_store4, "check_store4", - addr, addrv, - uwiden_to_host_word( pce, data )); - } else { - /* store-conditional; need to snarf the success bit */ - IRTemp resSC64 - = gen_dirty_W_WWW( pce, - &check_store4C, - "check_store4C", - addr, addrv, - uwiden_to_host_word( pce, data )); - assign( 'I', pce, resSC, unop(Iop_64to1, mkexpr(resSC64)) ); - } - break; - case Ity_I16: - gen_dirty_v_WWW( pce, - &check_store2, "check_store2", - addr, addrv, - uwiden_to_host_word( pce, data )); - break; - case Ity_I8: - gen_dirty_v_WWW( pce, - &check_store1, "check_store1", - addr, addrv, - uwiden_to_host_word( pce, data )); - break; - /* 128-bit vector. Pass store data in 2 64-bit pieces. */ - case Ity_V128: { - IRAtom* dHi64 = assignNew( 'I', pce, Ity_I64, - unop(Iop_V128HIto64, data) ); - IRAtom* dLo64 = assignNew( 'I', pce, Ity_I64, - unop(Iop_V128to64, data) ); - gen_dirty_v_WWWW( pce, - &check_store16_ms8B_ls8B, - "check_store16_ms8B_ls8B", - addr, addrv, dHi64, dLo64 ); - break; - } - /* 64-bit float. */ - case Ity_F64: { - IRAtom* dI = assignNew( 'I', pce, Ity_I64, - unop(Iop_ReinterpF64asI64, - data ) ); - gen_dirty_v_WWW( pce, - &check_store8_all8B, - "check_store8_all8B", - addr, addrv, dI ); - break; - } - /* 32-bit float. We can just use _store4, but need - to futz with the argument type. */ - case Ity_F32: { - IRAtom* i32 = assignNew( 'I', pce, Ity_I32, - unop(Iop_ReinterpF32asI32, - data ) ); - IRAtom* i64 = assignNew( 'I', pce, Ity_I64, - unop(Iop_32Uto64, - i32 ) ); - gen_dirty_v_WWW( pce, - &check_store4, - "check_store4", - addr, addrv, i64 ); - break; - } - default: - ppIRType(d_ty); tl_assert(0); - } - } - /* And don't copy the original, since the helper does the - store. Ick. */ + Bool ok = schemeS_store( pce, + st->Ist.Store.data, + st->Ist.Store.addr, + IRTemp_INVALID/*not a SC*/ ); + if (!ok) goto unhandled; + /* Don't copy the original, since the helper does the store + itself. */ break; - } /* case Ist_Store */ + } case Ist_WrTmp: { /* This is the only place we have to deal with the full @@ -4990,69 +5174,7 @@ static void schemeS ( PCEnv* pce, IRStmt* st ) } case Iex_Load: { - IRExpr* addr = e->Iex.Load.addr; - HChar* h_nm = NULL; - void* h_fn = NULL; - IRExpr* addrv = NULL; - if (pce->gWordTy == Ity_I32) { - /* 32 bit host/guest (cough, cough) */ - switch (e_ty) { - /* Ity_I32: helper returns shadow value. */ - case Ity_I32: h_fn = &check_load4_P; - h_nm = "check_load4_P"; break; - /* all others: helper does not return a shadow - value. */ - case Ity_V128: h_fn = &check_load16; - h_nm = "check_load16"; break; - case Ity_I64: - case Ity_F64: h_fn = &check_load8; - h_nm = "check_load8"; break; - case Ity_F32: h_fn = &check_load4; - h_nm = "check_load4"; break; - case Ity_I16: h_fn = &check_load2; - h_nm = "check_load2"; break; - case Ity_I8: h_fn = &check_load1; - h_nm = "check_load1"; break; - default: ppIRType(e_ty); tl_assert(0); - } - addrv = schemeEw_Atom( pce, addr ); - if (e_ty == Ity_I32) { - assign( 'I', pce, dstv, - mkexpr( gen_dirty_W_WW( pce, h_fn, h_nm, - addr, addrv )) ); - } else { - gen_dirty_v_WW( pce, NULL, h_fn, h_nm, addr, addrv ); - } - } else { - /* 64 bit host/guest (cough, cough) */ - switch (e_ty) { - /* Ity_I64: helper returns shadow value. */ - case Ity_I64: h_fn = &check_load8_P; - h_nm = "check_load8_P"; break; - /* all others: helper does not return a shadow - value. */ - case Ity_V128: h_fn = &check_load16; - h_nm = "check_load16"; break; - case Ity_F64: h_fn = &check_load8; - h_nm = "check_load8"; break; - case Ity_F32: - case Ity_I32: h_fn = &check_load4; - h_nm = "check_load4"; break; - case Ity_I16: h_fn = &check_load2; - h_nm = "check_load2"; break; - case Ity_I8: h_fn = &check_load1; - h_nm = "check_load1"; break; - default: ppIRType(e_ty); tl_assert(0); - } - addrv = schemeEw_Atom( pce, addr ); - if (e_ty == Ity_I64) { - assign( 'I', pce, dstv, - mkexpr( gen_dirty_W_WW( pce, h_fn, h_nm, - addr, addrv )) ); - } else { - gen_dirty_v_WW( pce, NULL, h_fn, h_nm, addr, addrv ); - } - } + schemeS_load( pce, e->Iex.Load.addr, e_ty, dstv ); /* copy the original -- must happen after the helper call */ stmt( 'C', pce, st ); break; @@ -5229,7 +5351,7 @@ IRSB* h_instrument ( VgCallbackClosure* closure, (void*)&pce ); /* Stay sane. These two should agree! */ - tl_assert(layout->total_sizeB == MC_SIZEOF_GUEST_STATE); + tl_assert(layout->total_sizeB == PC_SIZEOF_GUEST_STATE); /* Copy verbatim any IR preamble preceding the first IMark */ diff --git a/exp-ptrcheck/h_main.h b/exp-ptrcheck/h_main.h index 8bbe07a..37324fa 100644 --- a/exp-ptrcheck/h_main.h +++ b/exp-ptrcheck/h_main.h @@ -9,9 +9,9 @@ This file is part of Ptrcheck, a Valgrind tool for checking pointer use in programs. - Copyright (C) 2003-2009 Nicholas Nethercote + Copyright (C) 2003-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/exp-ptrcheck/pc_common.c b/exp-ptrcheck/pc_common.c index a45c416..f6aa3b3 100644 --- a/exp-ptrcheck/pc_common.c +++ b/exp-ptrcheck/pc_common.c @@ -9,7 +9,7 @@ This file is part of Ptrcheck, a Valgrind tool for checking pointer use in programs. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/exp-ptrcheck/pc_common.h b/exp-ptrcheck/pc_common.h index 4772008..7fb98f8 100644 --- a/exp-ptrcheck/pc_common.h +++ b/exp-ptrcheck/pc_common.h @@ -9,7 +9,7 @@ This file is part of Ptrcheck, a Valgrind tool for checking pointer use in programs. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/exp-ptrcheck/pc_main.c b/exp-ptrcheck/pc_main.c index 47bd13d..cdfa82b 100644 --- a/exp-ptrcheck/pc_main.c +++ b/exp-ptrcheck/pc_main.c @@ -9,7 +9,7 @@ This file is part of Ptrcheck, a Valgrind tool for checking pointer use in programs. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -127,10 +127,10 @@ static void pc_post_clo_init ( void ) sg_post_clo_init(); # if defined(VGA_x86) || defined(VGA_amd64) /* nothing */ -# elif defined(VGA_ppc32) || defined(VGA_ppc64) +# elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm) if (VG_(clo_verbosity) >= 1 && sg_clo_enable_sg_checks) { VG_(message)(Vg_UserMsg, - "WARNING: exp-ptrcheck on ppc32/ppc64 platforms: " + "WARNING: exp-ptrcheck on ppc32/ppc64/arm platforms: " "stack and global array\n"); VG_(message)(Vg_UserMsg, "WARNING: checking is not currently supported. " @@ -160,10 +160,10 @@ static void pc_pre_clo_init(void) VG_(details_name) ("exp-ptrcheck"); VG_(details_version) (NULL); - VG_(details_description) ("a heap, stack & global array " + VG_(details_description) ("a heap, stack and global array " "overrun detector"); VG_(details_copyright_author)( - "Copyright (C) 2003-2009, and GNU GPL'd, by OpenWorks Ltd et al."); + "Copyright (C) 2003-2010, and GNU GPL'd, by OpenWorks Ltd et al."); VG_(details_bug_reports_to) (VG_BUGS_TO); VG_(details_avg_translation_sizeB) ( 496 ); diff --git a/exp-ptrcheck/sg_main.c b/exp-ptrcheck/sg_main.c index 5d324ca..3f0a675 100644 --- a/exp-ptrcheck/sg_main.c +++ b/exp-ptrcheck/sg_main.c @@ -9,7 +9,7 @@ This file is part of Ptrcheck, a Valgrind tool for checking pointer use in programs. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/exp-ptrcheck/sg_main.h b/exp-ptrcheck/sg_main.h index ad3c58e..31d2fb6 100644 --- a/exp-ptrcheck/sg_main.h +++ b/exp-ptrcheck/sg_main.h @@ -9,7 +9,7 @@ This file is part of Ptrcheck, a Valgrind tool for checking pointer use in programs. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/exp-ptrcheck/tests/Makefile.am b/exp-ptrcheck/tests/Makefile.am index 666c340..71dad98 100644 --- a/exp-ptrcheck/tests/Makefile.am +++ b/exp-ptrcheck/tests/Makefile.am @@ -5,6 +5,7 @@ dist_noinst_SCRIPTS = filter_stderr filter_add filter_suppgen \ sh_script EXTRA_DIST = \ + is_arch_supported \ add.vgtest-disabled add.stderr.exp \ and.vgtest-disabled and.stderr.exp \ arith.vgtest-disabled arith.stderr.exp \ diff --git a/exp-ptrcheck/tests/bad_percentify.vgtest b/exp-ptrcheck/tests/bad_percentify.vgtest index ab3e21d..1f390b0 100644 --- a/exp-ptrcheck/tests/bad_percentify.vgtest +++ b/exp-ptrcheck/tests/bad_percentify.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: bad_percentify diff --git a/exp-ptrcheck/tests/base.vgtest b/exp-ptrcheck/tests/base.vgtest index 4359690..7aa99d0 100644 --- a/exp-ptrcheck/tests/base.vgtest +++ b/exp-ptrcheck/tests/base.vgtest @@ -1,2 +1,3 @@ +prereq: ./is_arch_supported prog: base stderr_filter: filter_add diff --git a/exp-ptrcheck/tests/ccc.vgtest b/exp-ptrcheck/tests/ccc.vgtest index 7c0c728..d6d7ae1 100644 --- a/exp-ptrcheck/tests/ccc.vgtest +++ b/exp-ptrcheck/tests/ccc.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: ccc diff --git a/exp-ptrcheck/tests/filter_stderr b/exp-ptrcheck/tests/filter_stderr index 78b292a..f315d9e 100755 --- a/exp-ptrcheck/tests/filter_stderr +++ b/exp-ptrcheck/tests/filter_stderr @@ -16,9 +16,9 @@ sed "s/__libc_\(.*\) (.*)$/__libc_\1 (...libc...)/" | # Remove preambly stuff; also postambly stuff sed \ --e "/^exp-ptrcheck, a heap, stack & global array overrun detector$/d" \ +-e "/^exp-ptrcheck, a heap, stack and global array overrun detector$/d" \ -e "/^NOTE: This is an Experimental-Class Valgrind Tool$/d" \ --e "/^Copyright (C) 2003-200., and GNU GPL'd, by OpenWorks Ltd et al.$/d" \ +-e "/^Copyright (C) 2003-201., and GNU GPL'd, by OpenWorks Ltd et al.$/d" \ -e "/^For counts of detected and suppressed errors, rerun with: -v$/d" | # Tidy up in cases where glibc (+ libdl + libpthread + ld) have @@ -30,7 +30,8 @@ sed \ -e "s/ printf (.*)/ .../" \ -e "s/ strdup (.*)/ .../" \ -e "s/(pthread_key_create.c:[0-9]*)/(in \/...libpthread...)/" \ --e "s/(genops.c:[0-9]*)/(in \/...libc...)/" | +-e "s/(genops.c:[0-9]*)/(in \/...libc...)/" \ +-e "s/(syscall-template.S:[0-9]*)/(in \/...libc...)/" | # Anonymise line numbers in h_intercepts.c. sed "s/h_intercepts.c:[0-9]*/h_intercepts.c:.../" diff --git a/exp-ptrcheck/tests/fp.vgtest b/exp-ptrcheck/tests/fp.vgtest index d178745..bd93cf8 100644 --- a/exp-ptrcheck/tests/fp.vgtest +++ b/exp-ptrcheck/tests/fp.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: fp diff --git a/exp-ptrcheck/tests/globalerr.vgtest b/exp-ptrcheck/tests/globalerr.vgtest index f75fcee..c6749cb 100644 --- a/exp-ptrcheck/tests/globalerr.vgtest +++ b/exp-ptrcheck/tests/globalerr.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: globalerr diff --git a/exp-ptrcheck/tests/hackedbz2.vgtest b/exp-ptrcheck/tests/hackedbz2.vgtest index 41d1772..ea8f5e8 100644 --- a/exp-ptrcheck/tests/hackedbz2.vgtest +++ b/exp-ptrcheck/tests/hackedbz2.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: hackedbz2 diff --git a/exp-ptrcheck/tests/hp_bounds.vgtest b/exp-ptrcheck/tests/hp_bounds.vgtest index f92fc54..96a983e 100644 --- a/exp-ptrcheck/tests/hp_bounds.vgtest +++ b/exp-ptrcheck/tests/hp_bounds.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: hp_bounds diff --git a/exp-ptrcheck/tests/hp_dangle.vgtest b/exp-ptrcheck/tests/hp_dangle.vgtest index 82785c9..42cbe6c 100644 --- a/exp-ptrcheck/tests/hp_dangle.vgtest +++ b/exp-ptrcheck/tests/hp_dangle.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: hp_dangle diff --git a/exp-ptrcheck/tests/hsg.vgtest b/exp-ptrcheck/tests/hsg.vgtest index 663a523..b6f6536 100644 --- a/exp-ptrcheck/tests/hsg.vgtest +++ b/exp-ptrcheck/tests/hsg.vgtest @@ -1,3 +1,4 @@ +prereq: ./is_arch_supported prog: hsg vgopts: --xml=yes --xml-fd=2 --log-file=/dev/null stderr_filter: ../../memcheck/tests/filter_xml diff --git a/exp-ptrcheck/tests/is_arch_supported b/exp-ptrcheck/tests/is_arch_supported new file mode 100755 index 0000000..ca9bd16 --- /dev/null +++ b/exp-ptrcheck/tests/is_arch_supported @@ -0,0 +1,15 @@ +#!/bin/sh +# +# Not all architectures are supported by exp-ptr. Currently, PowerPC and ARM +# are not supported and will fail these tests as follows: +# WARNING: exp-ptrcheck on platforms: stack and global array +# WARNING: checking is not currently supported. Only heap checking is +# WARNING: supported. +# +# So we use this script to prevent these tests from running on unsupported +# architectures. + +case `uname -i` in + ppc*|arm*) exit 1;; + *) exit 0;; +esac diff --git a/exp-ptrcheck/tests/justify.vgtest b/exp-ptrcheck/tests/justify.vgtest index aef13f6..3052c7e 100644 --- a/exp-ptrcheck/tests/justify.vgtest +++ b/exp-ptrcheck/tests/justify.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: justify diff --git a/exp-ptrcheck/tests/partial_bad.vgtest b/exp-ptrcheck/tests/partial_bad.vgtest index 86e13e8..094946b 100644 --- a/exp-ptrcheck/tests/partial_bad.vgtest +++ b/exp-ptrcheck/tests/partial_bad.vgtest @@ -1,2 +1,3 @@ +prereq: ./is_arch_supported prog: partial vgopts: --partial-loads-ok=no diff --git a/exp-ptrcheck/tests/partial_good.vgtest b/exp-ptrcheck/tests/partial_good.vgtest index 29fd892..ea7d285 100644 --- a/exp-ptrcheck/tests/partial_good.vgtest +++ b/exp-ptrcheck/tests/partial_good.vgtest @@ -1,2 +1,3 @@ +prereq: ./is_arch_supported prog: partial vgopts: --partial-loads-ok=yes diff --git a/exp-ptrcheck/tests/preen_invars.vgtest b/exp-ptrcheck/tests/preen_invars.vgtest index c654c18..49da4bb 100644 --- a/exp-ptrcheck/tests/preen_invars.vgtest +++ b/exp-ptrcheck/tests/preen_invars.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: preen_invars diff --git a/exp-ptrcheck/tests/pth_create.vgtest b/exp-ptrcheck/tests/pth_create.vgtest index c98abc6..91fa9b1 100644 --- a/exp-ptrcheck/tests/pth_create.vgtest +++ b/exp-ptrcheck/tests/pth_create.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: pth_create diff --git a/exp-ptrcheck/tests/pth_specific.vgtest b/exp-ptrcheck/tests/pth_specific.vgtest index f2a2a34..5e6789b 100644 --- a/exp-ptrcheck/tests/pth_specific.vgtest +++ b/exp-ptrcheck/tests/pth_specific.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: pth_specific diff --git a/exp-ptrcheck/tests/realloc.vgtest b/exp-ptrcheck/tests/realloc.vgtest index 0b9a00c..1cc74ed 100644 --- a/exp-ptrcheck/tests/realloc.vgtest +++ b/exp-ptrcheck/tests/realloc.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: realloc diff --git a/exp-ptrcheck/tests/sh_script b/exp-ptrcheck/tests/sh_script old mode 100644 new mode 100755 diff --git a/exp-ptrcheck/tests/stackerr.vgtest b/exp-ptrcheck/tests/stackerr.vgtest index b81660b..0a1139d 100644 --- a/exp-ptrcheck/tests/stackerr.vgtest +++ b/exp-ptrcheck/tests/stackerr.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: stackerr diff --git a/exp-ptrcheck/tests/strcpy.vgtest b/exp-ptrcheck/tests/strcpy.vgtest index 809bbf6..d686e9f 100644 --- a/exp-ptrcheck/tests/strcpy.vgtest +++ b/exp-ptrcheck/tests/strcpy.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: strcpy diff --git a/exp-ptrcheck/tests/supp.vgtest b/exp-ptrcheck/tests/supp.vgtest index c0d71e7..b991f57 100644 --- a/exp-ptrcheck/tests/supp.vgtest +++ b/exp-ptrcheck/tests/supp.vgtest @@ -1,2 +1,3 @@ +prereq: ./is_arch_supported vgopts: --suppressions=supp.supp prog: supp diff --git a/exp-ptrcheck/tests/tricky.vgtest b/exp-ptrcheck/tests/tricky.vgtest index 3f22f2b..8ebfc09 100644 --- a/exp-ptrcheck/tests/tricky.vgtest +++ b/exp-ptrcheck/tests/tricky.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: tricky diff --git a/exp-ptrcheck/tests/unaligned.vgtest b/exp-ptrcheck/tests/unaligned.vgtest index e5076d2..240dc60 100644 --- a/exp-ptrcheck/tests/unaligned.vgtest +++ b/exp-ptrcheck/tests/unaligned.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: unaligned diff --git a/exp-ptrcheck/tests/zero.vgtest b/exp-ptrcheck/tests/zero.vgtest index d5af1b4..3d6333c 100644 --- a/exp-ptrcheck/tests/zero.vgtest +++ b/exp-ptrcheck/tests/zero.vgtest @@ -1 +1,2 @@ +prereq: ./is_arch_supported prog: zero diff --git a/glibc-2.34567-NPTL-helgrind.supp b/glibc-2.34567-NPTL-helgrind.supp index 3703eff..2e2abee 100644 --- a/glibc-2.34567-NPTL-helgrind.supp +++ b/glibc-2.34567-NPTL-helgrind.supp @@ -134,12 +134,6 @@ Helgrind:Race fun:__lll_*lock_* } -{ - helgrind-glibc2X-112 - Helgrind:Race - fun:pthread_create_WRK - fun:pthread_create@* -} { helgrind-glibc2X-113 Helgrind:Race diff --git a/glibc-2.X-drd.supp b/glibc-2.X-drd.supp index 2a34594..441e7a8 100644 --- a/glibc-2.X-drd.supp +++ b/glibc-2.X-drd.supp @@ -41,6 +41,14 @@ # fun:_ZNSsC1ERKSs # } +{ + drd-libstdc++-cxa_guard_release + drd:CondErr + fun:pthread_cond_broadcast@* + fun:__cxa_guard_release +} + + # # Suppression patterns for libpthread. # @@ -63,30 +71,60 @@ ... fun:__deallocate_stack } +{ + drd-libpthread-__free_stacks + drd:ConflictingAccess + fun:__free_stacks +} { drd-libpthread-__free_tcb drd:ConflictingAccess ... fun:__free_tcb } +{ + drd-libpthread-__nptl_deallocate_tsd + drd:ConflictingAccess + fun:__nptl_deallocate_tsd +} { drd-libpthread-pthread_detach drd:ConflictingAccess fun:pthread_detach fun:pthread_detach } +{ + drd-libpthread-pthread_once + drd:ConflictingAccess + fun:pthread_once +} +{ + drd-libpthread-pthread_cancel_init + drd:ConflictingAccess + fun:pthread_cancel_init +} { drd-libpthread-_Unwind_ForcedUnwind drd:ConflictingAccess ... fun:_Unwind_ForcedUnwind } +{ + drd-libpthread-_Unwind_GetCFA + drd:ConflictingAccess + fun:_Unwind_GetCFA +} { drd-libpthread-_Unwind_Resume drd:ConflictingAccess ... fun:_Unwind_Resume } +{ + drd-libpthread-? + drd:ConflictingAccess + obj:/lib/libgcc_s.so.1 +} { drd-libpthread-nanosleep drd:ConflictingAccess @@ -146,6 +184,7 @@ { drd-libglib-access-g_threads_got_initialized drd:ConflictingAccess + ... fun:_ZN27QEventDispatcherGlibPrivateC1EP13_GMainContext fun:_ZN20QEventDispatcherGlibC1EP7QObject obj:/usr/lib*/libQtCore.so.4.* @@ -187,7 +226,6 @@ drd-libQtCore-deref-that-calls-QThreadData-destructor drd:ConflictingAccess fun:_ZN11QThreadDataD1Ev - fun:_ZN11QThreadData5derefEv obj:/usr/lib*/libQtCore.so.4.* } { @@ -221,10 +259,9 @@ fun:_ZN10QMutexPool3getEPKv } { - drd-libQtCore-QThread::QThread(QObject*) + drd-libQtCore-qt_gettime_is_monotonic() drd:ConflictingAccess - ... - fun:_ZN7QThreadC2EP7QObject + fun:_Z23qt_gettime_is_monotonicv } # @@ -232,8 +269,9 @@ # # Suppress the races on boost::once_flag::epoch and on -# boost::detail::once_global_epoch. See also the source file -# boost/thread/pthread/once.hpp in the Boost source tree. +# boost::detail::this_thread_epoch. See also the source file +# boost/thread/pthread/once.hpp in the Boost source tree +# (https://svn.boost.org/trac/boost/browser/trunk/boost/thread/pthread/once.hpp). { drd-libboost-boost::call_once(boost::once_flag&, void (*)()) drd:ConflictingAccess @@ -245,9 +283,18 @@ drd:ConflictingAccess fun:_ZN5boost6detail25get_once_per_thread_epochEv } +# Suppress the race reports on boost::detail::current_thread_tls_key. See also +# https://svn.boost.org/trac/boost/ticket/3526 for more information about why +# the access pattern of current_thread_tls_key is safe. { drd-libboost-boost::detail::get_current_thread_data() drd:ConflictingAccess ... fun:_ZN5boost6detail23get_current_thread_dataEv } +{ + drd-libboost-boost::detail::set_current_thread_data(boost::detail::thread_data_base*) + drd:ConflictingAccess + ... + fun:_ZN5boost6detail23set_current_thread_dataEPNS0_16thread_data_baseE +} diff --git a/glibc-2.X.supp.in b/glibc-2.X.supp.in index ef85328..935bd74 100644 --- a/glibc-2.X.supp.in +++ b/glibc-2.X.supp.in @@ -228,3 +228,11 @@ obj:/lib/libpthread-0.10.so fun:pthread_create } + +##----------------------------------------------------------------------## +# Ubuntu 10.04 on ARM (Thumb). Not sure why this is necessary. +{ + U1004-ARM-_dl_relocate_object + Memcheck:Cond + fun:_dl_relocate_object +} diff --git a/helgrind/Makefile.am b/helgrind/Makefile.am index 795266a..300e25b 100644 --- a/helgrind/Makefile.am +++ b/helgrind/Makefile.am @@ -35,7 +35,8 @@ HELGRIND_SOURCES_COMMON = \ hg_wordset.c \ libhb_core.c -helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(HELGRIND_SOURCES_COMMON) +helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ + $(HELGRIND_SOURCES_COMMON) helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \ @@ -46,8 +47,16 @@ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC -helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(HELGRIND_SOURCES_COMMON) +helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ + $(HELGRIND_SOURCES_COMMON) helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \ @@ -58,6 +67,12 @@ helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif #---------------------------------------------------------------------------- @@ -86,6 +101,7 @@ vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \ vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) + if VGCONF_HAVE_PLATFORM_SEC vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = \ $(VGPRELOAD_HELGRIND_SOURCES_COMMON) diff --git a/helgrind/helgrind.h b/helgrind/helgrind.h index 317695b..2c30a5a 100644 --- a/helgrind/helgrind.h +++ b/helgrind/helgrind.h @@ -11,7 +11,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks LLP + Copyright (C) 2007-2010 OpenWorks LLP info@open-works.co.uk Redistribution and use in source and binary forms, with or without @@ -97,7 +97,7 @@ typedef _VG_USERREQ__HG_POSIX_SEM_DESTROY_PRE, /* sem_t* */ _VG_USERREQ__HG_POSIX_SEM_POST_PRE, /* sem_t* */ _VG_USERREQ__HG_POSIX_SEM_WAIT_POST, /* sem_t* */ - _VG_USERREQ__HG_PTHREAD_BARRIER_INIT_PRE, /* pth_bar_t*, ulong */ + _VG_USERREQ__HG_PTHREAD_BARRIER_INIT_PRE, /* pth_bar_t*, ulong, ulong */ _VG_USERREQ__HG_PTHREAD_BARRIER_WAIT_PRE, /* pth_bar_t* */ _VG_USERREQ__HG_PTHREAD_BARRIER_DESTROY_PRE, /* pth_bar_t* */ _VG_USERREQ__HG_PTHREAD_SPIN_INIT_OR_UNLOCK_PRE, /* pth_slk_t* */ @@ -109,29 +109,204 @@ typedef _VG_USERREQ__HG_USERSO_SEND_PRE, /* arbitrary UWord SO-tag */ _VG_USERREQ__HG_USERSO_RECV_POST, /* arbitrary UWord SO-tag */ _VG_USERREQ__HG_RESERVED1, /* Do not use */ - _VG_USERREQ__HG_RESERVED2 /* Do not use */ + _VG_USERREQ__HG_RESERVED2, /* Do not use */ + _VG_USERREQ__HG_RESERVED3, /* Do not use */ + _VG_USERREQ__HG_RESERVED4, /* Do not use */ + _VG_USERREQ__HG_ARANGE_MAKE_UNTRACKED, /* Addr a, ulong len */ + _VG_USERREQ__HG_ARANGE_MAKE_TRACKED, /* Addr a, ulong len */ + _VG_USERREQ__HG_PTHREAD_BARRIER_RESIZE_PRE, /* pth_bar_t*, ulong */ + _VG_USERREQ__HG_CLEAN_MEMORY_HEAPBLOCK /* Addr start_of_block */ } Vg_TCheckClientRequest; /*----------------------------------------------------------------*/ -/*--- An implementation-only request -- not for end user use ---*/ +/*--- ---*/ +/*--- Implementation-only facilities. Not for end-user use. ---*/ +/*--- For end-user facilities see below (the next section in ---*/ +/*--- this file.) ---*/ +/*--- ---*/ /*----------------------------------------------------------------*/ -#define _HG_CLIENTREQ_UNIMP(_qzz_str) \ - do { \ - unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, \ - _VG_USERREQ__HG_CLIENTREQ_UNIMP, \ - _qzz_str, 0, 0, 0, 0); \ - (void)0; \ - } while(0) +/* Do a client request. These are macros rather than a functions so + as to avoid having an extra frame in stack traces. + + NB: these duplicate definitions in hg_intercepts.c. But here, we + have to make do with weaker typing (no definition of Word etc) and + no assertions, whereas in helgrind.h we can use those facilities. + Obviously it's important the two sets of definitions are kept in + sync. + + The commented-out asserts should actually hold, but unfortunately + they can't be allowed to be visible here, because that would + require the end-user code to #include . +*/ + +#define DO_CREQ_v_W(_creqF, _ty1F,_arg1F) \ + do { \ + long int _unused_res, _arg1; \ + /* assert(sizeof(_ty1F) == sizeof(long int)); */ \ + _arg1 = (long int)(_arg1F); \ + VALGRIND_DO_CLIENT_REQUEST(_unused_res, 0, \ + (_creqF), \ + _arg1, 0,0,0,0); \ + } while (0) + +#define DO_CREQ_W_W(_resF, _dfltF, _creqF, _ty1F,_arg1F) \ + do { \ + long int _qzz_res, _arg1; \ + /* assert(sizeof(_ty1F) == sizeof(long int)); */ \ + _arg1 = (long int)(_arg1F); \ + VALGRIND_DO_CLIENT_REQUEST(_qzz_res, (_dfltF), \ + (_creqF), \ + _arg1, 0,0,0,0); \ + _resF = _qzz_res; \ + } while (0) + +#define DO_CREQ_v_WW(_creqF, _ty1F,_arg1F, _ty2F,_arg2F) \ + do { \ + long int _unused_res, _arg1, _arg2; \ + /* assert(sizeof(_ty1F) == sizeof(long int)); */ \ + /* assert(sizeof(_ty2F) == sizeof(long int)); */ \ + _arg1 = (long int)(_arg1F); \ + _arg2 = (long int)(_arg2F); \ + VALGRIND_DO_CLIENT_REQUEST(_unused_res, 0, \ + (_creqF), \ + _arg1,_arg2,0,0,0); \ + } while (0) + +#define DO_CREQ_v_WWW(_creqF, _ty1F,_arg1F, \ + _ty2F,_arg2F, _ty3F, _arg3F) \ + do { \ + long int _unused_res, _arg1, _arg2, _arg3; \ + /* assert(sizeof(_ty1F) == sizeof(long int)); */ \ + /* assert(sizeof(_ty2F) == sizeof(long int)); */ \ + /* assert(sizeof(_ty3F) == sizeof(long int)); */ \ + _arg1 = (long int)(_arg1F); \ + _arg2 = (long int)(_arg2F); \ + _arg3 = (long int)(_arg3F); \ + VALGRIND_DO_CLIENT_REQUEST(_unused_res, 0, \ + (_creqF), \ + _arg1,_arg2,_arg3,0,0); \ + } while (0) + + +#define _HG_CLIENTREQ_UNIMP(_qzz_str) \ + DO_CREQ_v_W(_VG_USERREQ__HG_CLIENTREQ_UNIMP, \ + (char*),(_qzz_str)) /*----------------------------------------------------------------*/ -/*--- Misc requests ---*/ +/*--- ---*/ +/*--- Helgrind-native requests. These allow access to ---*/ +/*--- the same set of annotation primitives that are used ---*/ +/*--- to build the POSIX pthread wrappers. ---*/ +/*--- ---*/ /*----------------------------------------------------------------*/ +/* ---------------------------------------------------------- + For describing ordinary mutexes (non-rwlocks). For rwlock + descriptions see ANNOTATE_RWLOCK_* below. + ---------------------------------------------------------- */ + +/* Notify here immediately after mutex creation. _mbRec == 0 for a + non-recursive mutex, 1 for a recursive mutex. */ +#define VALGRIND_HG_MUTEX_INIT_POST(_mutex, _mbRec) \ + DO_CREQ_v_WW(_VG_USERREQ__HG_PTHREAD_MUTEX_INIT_POST, \ + void*,(_mutex), long,(_mbRec)) + +/* Notify here immediately before mutex acquisition. _isTryLock == 0 + for a normal acquisition, 1 for a "try" style acquisition. */ +#define VALGRIND_HG_MUTEX_LOCK_PRE(_mutex, _isTryLock) \ + DO_CREQ_v_WW(_VG_USERREQ__HG_PTHREAD_MUTEX_LOCK_PRE, \ + void*,(_mutex), long,(_isTryLock)) + +/* Notify here immediately after a successful mutex acquisition. */ +#define VALGRIND_HG_MUTEX_LOCK_POST(_mutex) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_MUTEX_LOCK_POST, \ + void*,(_mutex)) + +/* Notify here immediately before a mutex release. */ +#define VALGRIND_HG_MUTEX_UNLOCK_PRE(_mutex) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_MUTEX_UNLOCK_PRE, \ + void*,(_mutex)) + +/* Notify here immediately after a mutex release. */ +#define VALGRIND_HG_MUTEX_UNLOCK_POST(_mutex) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_MUTEX_UNLOCK_POST, \ + void*,(_mutex)) + +/* Notify here immediately before mutex destruction. */ +#define VALGRIND_HG_MUTEX_DESTROY_PRE(_mutex) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_MUTEX_DESTROY_PRE, \ + void*,(_mutex)) + +/* ---------------------------------------------------------- + For describing semaphores. + ---------------------------------------------------------- */ + +/* Notify here immediately after semaphore creation. */ +#define VALGRIND_HG_SEM_INIT_POST(_sem, _value) \ + DO_CREQ_v_WW(_VG_USERREQ__HG_POSIX_SEM_INIT_POST, \ + void*, (_sem), unsigned long, (_value)) + +/* Notify here immediately after a semaphore wait (an acquire-style + operation) */ +#define VALGRIND_HG_SEM_WAIT_POST(_sem) \ + DO_CREQ_v_W(_VG_USERREQ__HG_POSIX_SEM_WAIT_POST, \ + void*,(_sem)) + +/* Notify here immediately before semaphore post (a release-style + operation) */ +#define VALGRIND_HG_SEM_POST_PRE(_sem) \ + DO_CREQ_v_W(_VG_USERREQ__HG_POSIX_SEM_POST_PRE, \ + void*,(_sem)) + +/* Notify here immediately before semaphore destruction. */ +#define VALGRIND_HG_SEM_DESTROY_PRE(_sem) \ + DO_CREQ_v_W(_VG_USERREQ__HG_POSIX_SEM_DESTROY_PRE, \ + void*, (_sem)) + +/* ---------------------------------------------------------- + For describing barriers. + ---------------------------------------------------------- */ + +/* Notify here immediately before barrier creation. _count is the + capacity. _resizable == 0 means the barrier may not be resized, 1 + means it may be. */ +#define VALGRIND_HG_BARRIER_INIT_PRE(_bar, _count, _resizable) \ + DO_CREQ_v_WWW(_VG_USERREQ__HG_PTHREAD_BARRIER_INIT_PRE, \ + void*,(_bar), \ + unsigned long,(_count), \ + unsigned long,(_resizable)) + +/* Notify here immediately before arrival at a barrier. */ +#define VALGRIND_HG_BARRIER_WAIT_PRE(_bar) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_BARRIER_WAIT_PRE, \ + void*,(_bar)) + +/* Notify here immediately before a resize (change of barrier + capacity). If _newcount >= the existing capacity, then there is no + change in the state of any threads waiting at the barrier. If + _newcount < the existing capacity, and >= _newcount threads are + currently waiting at the barrier, then this notification is + considered to also have the effect of telling the checker that all + waiting threads have now moved past the barrier. (I can't think of + any other sane semantics.) */ +#define VALGRIND_HG_BARRIER_RESIZE_PRE(_bar, _newcount) \ + DO_CREQ_v_WW(_VG_USERREQ__HG_PTHREAD_BARRIER_RESIZE_PRE, \ + void*,(_bar), \ + unsigned long,(_newcount)) + +/* Notify here immediately before barrier destruction. */ +#define VALGRIND_HG_BARRIER_DESTROY_PRE(_bar) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_BARRIER_DESTROY_PRE, \ + void*,(_bar)) + +/* ---------------------------------------------------------- + For describing memory ownership changes. + ---------------------------------------------------------- */ + /* Clean memory state. This makes Helgrind forget everything it knew about the specified memory range. Effectively this announces that the specified memory range now "belongs" to the calling thread, so @@ -139,27 +314,68 @@ typedef synchronisation, and (2) all other threads must sync with this one to access it safely. This is particularly useful for memory allocators that wish to recycle memory. */ -#define VALGRIND_HG_CLEAN_MEMORY(_qzz_start, _qzz_len) \ - do { \ - unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST( \ - (_qzz_res), 0, VG_USERREQ__HG_CLEAN_MEMORY, \ - (_qzz_start), (_qzz_len), 0, 0, 0 \ - ); \ - (void)0; \ - } while(0) +#define VALGRIND_HG_CLEAN_MEMORY(_qzz_start, _qzz_len) \ + DO_CREQ_v_WW(VG_USERREQ__HG_CLEAN_MEMORY, \ + void*,(_qzz_start), \ + unsigned long,(_qzz_len)) + +/* The same, but for the heap block starting at _qzz_blockstart. This + allows painting when we only know the address of an object, but not + its size, which is sometimes the case in C++ code involving + inheritance, and in which RTTI is not, for whatever reason, + available. Returns the number of bytes painted, which can be zero + for a zero-sized block. Hence, return values >= 0 indicate success + (the block was found), and the value -1 indicates block not + found, and -2 is returned when not running on Helgrind. */ +#define VALGRIND_HG_CLEAN_MEMORY_HEAPBLOCK(_qzz_blockstart) \ + (__extension__ \ + ({long int _npainted; \ + DO_CREQ_W_W(_npainted, (-2)/*default*/, \ + _VG_USERREQ__HG_CLEAN_MEMORY_HEAPBLOCK, \ + void*,(_qzz_blockstart)); \ + _npainted; \ + })) + +/* ---------------------------------------------------------- + For error control. + ---------------------------------------------------------- */ + +/* Tell H that an address range is not to be "tracked" until further + notice. This puts it in the NOACCESS state, in which case we + ignore all reads and writes to it. Useful for ignoring ranges of + memory where there might be races we don't want to see. If the + memory is subsequently reallocated via malloc/new/stack allocation, + then it is put back in the trackable state. Hence it is safe in + the situation where checking is disabled, the containing area is + deallocated and later reallocated for some other purpose. */ +#define VALGRIND_HG_DISABLE_CHECKING(_qzz_start, _qzz_len) \ + DO_CREQ_v_WW(_VG_USERREQ__HG_ARANGE_MAKE_UNTRACKED, \ + void*,(_qzz_start), \ + unsigned long,(_qzz_len)) + +/* And put it back into the normal "tracked" state, that is, make it + once again subject to the normal race-checking machinery. This + puts it in the same state as new memory allocated by this thread -- + that is, basically owned exclusively by this thread. */ +#define VALGRIND_HG_ENABLE_CHECKING(_qzz_start, _qzz_len) \ + DO_CREQ_v_WW(_VG_USERREQ__HG_ARANGE_MAKE_TRACKED, \ + void*,(_qzz_start), \ + unsigned long,(_qzz_len)) /*----------------------------------------------------------------*/ +/*--- ---*/ /*--- ThreadSanitizer-compatible requests ---*/ +/*--- (mostly unimplemented) ---*/ +/*--- ---*/ /*----------------------------------------------------------------*/ /* A quite-broad set of annotations, as used in the ThreadSanitizer project. This implementation aims to be a (source-level) compatible implementation of the macros defined in: - http://code.google.com/p/google-perftools/source \ - /browse/trunk/src/base/dynamic_annotations.h + http://code.google.com/p/data-race-test/source + /browse/trunk/dynamic_annotations/dynamic_annotations.h (some of the comments below are taken from the above file) @@ -240,22 +456,10 @@ typedef ---------------------------------------------------------------- */ #define ANNOTATE_HAPPENS_BEFORE(obj) \ - do { \ - unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, \ - _VG_USERREQ__HG_USERSO_SEND_PRE, \ - obj, 0, 0, 0, 0); \ - (void)0; \ - } while (0) + DO_CREQ_v_W(_VG_USERREQ__HG_USERSO_SEND_PRE, void*,(obj)) #define ANNOTATE_HAPPENS_AFTER(obj) \ - do { \ - unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, \ - _VG_USERREQ__HG_USERSO_RECV_POST, \ - obj, 0, 0, 0, 0); \ - (void)0; \ - } while (0) + DO_CREQ_v_W(_VG_USERREQ__HG_USERSO_RECV_POST, void*,(obj)) /* ---------------------------------------------------------------- @@ -274,6 +478,12 @@ typedef #define ANNOTATE_PUBLISH_MEMORY_RANGE(pointer, size) \ _HG_CLIENTREQ_UNIMP("ANNOTATE_PUBLISH_MEMORY_RANGE") +/* DEPRECATED. Don't use it. */ +/* #define ANNOTATE_UNPUBLISH_MEMORY_RANGE(pointer, size) */ + +/* DEPRECATED. Don't use it. */ +/* #define ANNOTATE_SWAP_MEMORY_RANGE(pointer, size) */ + /* ---------------------------------------------------------------- TSan sources say: @@ -289,8 +499,11 @@ typedef behaviour. ---------------------------------------------------------------- */ -#define ANNOTATE_MUTEX_IS_USED_AS_CONDVAR(mu) \ - _HG_CLIENTREQ_UNIMP("ANNOTATE_MUTEX_IS_USED_AS_CONDVAR") +#define ANNOTATE_PURE_HAPPENS_BEFORE_MUTEX(mu) \ + _HG_CLIENTREQ_UNIMP("ANNOTATE_PURE_HAPPENS_BEFORE_MUTEX") + +/* Deprecated. Use ANNOTATE_PURE_HAPPENS_BEFORE_MUTEX. */ +/* #define ANNOTATE_MUTEX_IS_USED_AS_CONDVAR(mu) */ /* ---------------------------------------------------------------- @@ -354,16 +567,21 @@ typedef ---------------------------------------------------------------- */ -/* Report that we may have a benign race on ADDRESS. Insert at the - point where ADDRESS has been allocated, preferably close to the - point where the race happens. See also ANNOTATE_BENIGN_RACE_STATIC. +/* Report that we may have a benign race at "pointer", with size + "sizeof(*(pointer))". "pointer" must be a non-void* pointer. Insert at the + point where "pointer" has been allocated, preferably close to the point + where the race happens. See also ANNOTATE_BENIGN_RACE_STATIC. XXX: what's this actually supposed to do? And what's the type of DESCRIPTION? When does the annotation stop having an effect? */ -#define ANNOTATE_BENIGN_RACE(address, description) \ +#define ANNOTATE_BENIGN_RACE(pointer, description) \ _HG_CLIENTREQ_UNIMP("ANNOTATE_BENIGN_RACE") - + +/* Same as ANNOTATE_BENIGN_RACE(address, description), but applies to + the memory range [address, address+size). */ +#define ANNOTATE_BENIGN_RACE_SIZED(address, size, description) \ + _HG_CLIENTREQ_UNIMP("ANNOTATE_BENIGN_RACE_SIZED") /* Request the analysis tool to ignore all reads in the current thread until ANNOTATE_IGNORE_READS_END is called. Useful to ignore @@ -429,49 +647,51 @@ typedef ---------------------------------------------------------------- */ /* Report that a lock has just been created at address LOCK. */ -#define ANNOTATE_RWLOCK_CREATE(lock) \ - do { \ - unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST( \ - _qzz_res, 0, _VG_USERREQ__HG_PTHREAD_RWLOCK_INIT_POST, \ - lock, 0, 0, 0, 0 \ - ); \ - (void)0; \ - } while(0) +#define ANNOTATE_RWLOCK_CREATE(lock) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_RWLOCK_INIT_POST, \ + void*,(lock)) /* Report that the lock at address LOCK is about to be destroyed. */ -#define ANNOTATE_RWLOCK_DESTROY(lock) \ - do { \ - unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST( \ - _qzz_res, 0, _VG_USERREQ__HG_PTHREAD_RWLOCK_DESTROY_PRE, \ - lock, 0, 0, 0, 0 \ - ); \ - (void)0; \ - } while(0) +#define ANNOTATE_RWLOCK_DESTROY(lock) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_RWLOCK_DESTROY_PRE, \ + void*,(lock)) /* Report that the lock at address LOCK has just been acquired. is_w=1 for writer lock, is_w=0 for reader lock. */ -#define ANNOTATE_RWLOCK_ACQUIRED(lock, is_w) \ - do { \ - unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST( \ - _qzz_res, 0, _VG_USERREQ__HG_PTHREAD_RWLOCK_LOCK_POST, \ - lock, is_w ? 1 : 0, 0, 0, 0 \ - ); \ - (void)0; \ - } while(0) +#define ANNOTATE_RWLOCK_ACQUIRED(lock, is_w) \ + DO_CREQ_v_WW(_VG_USERREQ__HG_PTHREAD_RWLOCK_LOCK_POST, \ + void*,(lock), unsigned long,(is_w)) /* Report that the lock at address LOCK is about to be released. */ - #define ANNOTATE_RWLOCK_RELEASED(lock, is_w) \ - do { \ - unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST( \ - _qzz_res, 0, _VG_USERREQ__HG_PTHREAD_RWLOCK_UNLOCK_PRE, \ - lock, 0, 0, 0, 0 \ - ); \ - (void)0; \ - } while(0) +#define ANNOTATE_RWLOCK_RELEASED(lock, is_w) \ + DO_CREQ_v_W(_VG_USERREQ__HG_PTHREAD_RWLOCK_UNLOCK_PRE, \ + void*,(lock)) /* is_w is ignored */ + + +/* ------------------------------------------------------------- + Annotations useful when implementing barriers. They are not + normally needed by modules that merely use barriers. + The "barrier" argument is a pointer to the barrier object. + ---------------------------------------------------------------- +*/ + +/* Report that the "barrier" has been initialized with initial + "count". If 'reinitialization_allowed' is true, initialization is + allowed to happen multiple times w/o calling barrier_destroy() */ +#define ANNOTATE_BARRIER_INIT(barrier, count, reinitialization_allowed) \ + _HG_CLIENTREQ_UNIMP("ANNOTATE_BARRIER_INIT") + +/* Report that we are about to enter barrier_wait("barrier"). */ +#define ANNOTATE_BARRIER_WAIT_BEFORE(barrier) \ + _HG_CLIENTREQ_UNIMP("ANNOTATE_BARRIER_DESTROY") + +/* Report that we just exited barrier_wait("barrier"). */ +#define ANNOTATE_BARRIER_WAIT_AFTER(barrier) \ + _HG_CLIENTREQ_UNIMP("ANNOTATE_BARRIER_DESTROY") + +/* Report that the "barrier" has been destroyed. */ +#define ANNOTATE_BARRIER_DESTROY(barrier) \ + _HG_CLIENTREQ_UNIMP("ANNOTATE_BARRIER_DESTROY") /* ---------------------------------------------------------------- @@ -488,5 +708,9 @@ typedef #define ANNOTATE_NO_OP(arg) \ _HG_CLIENTREQ_UNIMP("ANNOTATE_NO_OP") +/* Force the race detector to flush its state. The actual effect depends on + * the implementation of the detector. */ +#define ANNOTATE_FLUSH_STATE() \ + _HG_CLIENTREQ_UNIMP("ANNOTATE_FLUSH_STATE") #endif /* __HELGRIND_H */ diff --git a/helgrind/hg_basics.c b/helgrind/hg_basics.c index 8dd82ac..7cef39d 100644 --- a/helgrind/hg_basics.c +++ b/helgrind/hg_basics.c @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks Ltd + Copyright (C) 2007-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/helgrind/hg_basics.h b/helgrind/hg_basics.h index 9580f13..fc34a39 100644 --- a/helgrind/hg_basics.h +++ b/helgrind/hg_basics.h @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks Ltd + Copyright (C) 2007-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/helgrind/hg_errors.c b/helgrind/hg_errors.c index f5649bc..497fe58 100644 --- a/helgrind/hg_errors.c +++ b/helgrind/hg_errors.c @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks Ltd + Copyright (C) 2007-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -178,8 +178,15 @@ typedef Int szB; Bool isWrite; Thread* thr; + /* descr1/2 provide a description of stack/global locs */ XArray* descr1; /* XArray* of HChar */ XArray* descr2; /* XArray* of HChar */ + /* halloc/haddr/hszB describe the addr if it is a heap block. */ + ExeContext* hctxt; + Addr haddr; + SizeT hszB; + /* h1_* and h2_* provide some description of a previously + observed access with which we are conflicting. */ Thread* h1_ct; /* non-NULL means h1 info present */ ExeContext* h1_ct_mbsegstartEC; ExeContext* h1_ct_mbsegendEC; @@ -215,8 +222,10 @@ typedef ExeContext* after_ec; } LockOrder; struct { - Thread* thr; - HChar* errstr; /* persistent, in tool-arena */ + Thread* thr; + HChar* errstr; /* persistent, in tool-arena */ + HChar* auxstr; /* optional, persistent, in tool-arena */ + ExeContext* auxctx; /* optional */ } Misc; } XE; } @@ -263,33 +272,52 @@ UInt HG_(update_extra) ( Error* err ) if (0) VG_(printf)("HG_(update_extra): " "%d conflicting-event queries\n", xxx); + + tl_assert(!xe->XE.Race.hctxt); tl_assert(!xe->XE.Race.descr1); tl_assert(!xe->XE.Race.descr2); - xe->XE.Race.descr1 - = VG_(newXA)( HG_(zalloc), "hg.update_extra.Race.descr1", - HG_(free), sizeof(HChar) ); - xe->XE.Race.descr2 - = VG_(newXA)( HG_(zalloc), "hg.update_extra.Race.descr2", - HG_(free), sizeof(HChar) ); - - (void) VG_(get_data_description)( xe->XE.Race.descr1, - xe->XE.Race.descr2, - xe->XE.Race.data_addr ); - - /* If there's nothing in descr1/2, free it. Why is it safe to - to VG_(indexXA) at zero here? Because - VG_(get_data_description) guarantees to zero terminate - descr1/2 regardless of the outcome of the call. So there's - always at least one element in each XA after the call. - */ - if (0 == VG_(strlen)( VG_(indexXA)( xe->XE.Race.descr1, 0 ))) { - VG_(deleteXA)( xe->XE.Race.descr1 ); - xe->XE.Race.descr1 = NULL; - } - if (0 == VG_(strlen)( VG_(indexXA)( xe->XE.Race.descr2, 0 ))) { - VG_(deleteXA)( xe->XE.Race.descr2 ); - xe->XE.Race.descr2 = NULL; + /* First, see if it's in any heap block. Unfortunately this + means a linear search through all allocated heap blocks. The + assertion says that if it's detected as a heap block, then we + must have an allocation context for it, since all heap blocks + should have an allocation context. */ + Bool is_heapblock + = HG_(mm_find_containing_block)( + &xe->XE.Race.hctxt, &xe->XE.Race.haddr, &xe->XE.Race.hszB, + xe->XE.Race.data_addr + ); + tl_assert(is_heapblock == (xe->XE.Race.hctxt != NULL)); + + if (!xe->XE.Race.hctxt) { + /* It's not in any heap block. See if we can map it to a + stack or global symbol. */ + + xe->XE.Race.descr1 + = VG_(newXA)( HG_(zalloc), "hg.update_extra.Race.descr1", + HG_(free), sizeof(HChar) ); + xe->XE.Race.descr2 + = VG_(newXA)( HG_(zalloc), "hg.update_extra.Race.descr2", + HG_(free), sizeof(HChar) ); + + (void) VG_(get_data_description)( xe->XE.Race.descr1, + xe->XE.Race.descr2, + xe->XE.Race.data_addr ); + + /* If there's nothing in descr1/2, free it. Why is it safe to + to VG_(indexXA) at zero here? Because + VG_(get_data_description) guarantees to zero terminate + descr1/2 regardless of the outcome of the call. So there's + always at least one element in each XA after the call. + */ + if (0 == VG_(strlen)( VG_(indexXA)( xe->XE.Race.descr1, 0 ))) { + VG_(deleteXA)( xe->XE.Race.descr1 ); + xe->XE.Race.descr1 = NULL; + } + if (0 == VG_(strlen)( VG_(indexXA)( xe->XE.Race.descr2, 0 ))) { + VG_(deleteXA)( xe->XE.Race.descr2 ); + xe->XE.Race.descr2 = NULL; + } } /* And poke around in the conflicting-event map, to see if we @@ -481,7 +509,8 @@ void HG_(record_error_PthAPIerror) ( Thread* thr, HChar* fnname, XE_PthAPIerror, 0, NULL, &xe ); } -void HG_(record_error_Misc) ( Thread* thr, HChar* errstr ) +void HG_(record_error_Misc_w_aux) ( Thread* thr, HChar* errstr, + HChar* auxstr, ExeContext* auxctx ) { XError xe; tl_assert( HG_(is_sane_Thread)(thr) ); @@ -490,6 +519,8 @@ void HG_(record_error_Misc) ( Thread* thr, HChar* errstr ) xe.tag = XE_Misc; xe.XE.Misc.thr = thr; xe.XE.Misc.errstr = string_table_strdup(errstr); + xe.XE.Misc.auxstr = auxstr ? string_table_strdup(auxstr) : NULL; + xe.XE.Misc.auxctx = auxctx; // FIXME: tid vs thr tl_assert( HG_(is_sane_ThreadId)(thr->coretid) ); tl_assert( thr->coretid != VG_INVALID_THREADID ); @@ -497,6 +528,11 @@ void HG_(record_error_Misc) ( Thread* thr, HChar* errstr ) XE_Misc, 0, NULL, &xe ); } +void HG_(record_error_Misc) ( Thread* thr, HChar* errstr ) +{ + HG_(record_error_Misc_w_aux)(thr, errstr, NULL, NULL); +} + Bool HG_(eq_Error) ( VgRes not_used, Error* e1, Error* e2 ) { XError *xe1, *xe2; @@ -591,7 +627,7 @@ static Bool announce_one_thread ( Thread* thr ) if (VG_(clo_xml)) { VG_(printf_xml)("\n"); - VG_(printf_xml)(" %d\n", thr->errmsg_index); + VG_(printf_xml)(" %d\n", thr->errmsg_index); if (thr->errmsg_index == 1) { tl_assert(thr->created_at == NULL); VG_(printf_xml)(" \n"); @@ -690,6 +726,11 @@ void HG_(pp_Error) ( Error* err ) (Int)xe->XE.Misc.thr->errmsg_index ); emit( " \n" ); VG_(pp_ExeContext)( VG_(get_error_where)(err) ); + if (xe->XE.Misc.auxstr) { + emit(" %s\n", xe->XE.Misc.auxstr); + if (xe->XE.Misc.auxctx) + VG_(pp_ExeContext)( xe->XE.Misc.auxctx ); + } } else { @@ -697,6 +738,11 @@ void HG_(pp_Error) ( Error* err ) (Int)xe->XE.Misc.thr->errmsg_index, xe->XE.Misc.errstr ); VG_(pp_ExeContext)( VG_(get_error_where)(err) ); + if (xe->XE.Misc.auxstr) { + emit(" %s\n", xe->XE.Misc.auxstr); + if (xe->XE.Misc.auxctx) + VG_(pp_ExeContext)( xe->XE.Misc.auxctx ); + } } break; @@ -993,6 +1039,23 @@ void HG_(pp_Error) ( Error* err ) } + /* If we have a description of the address in terms of a heap + block, show it. */ + if (xe->XE.Race.hctxt) { + SizeT delta = err_ga - xe->XE.Race.haddr; + if (xml) { + emit(" Address %#lx is %ld bytes inside a block " + "of size %ld alloc'd\n", err_ga, delta, + xe->XE.Race.hszB); + VG_(pp_ExeContext)( xe->XE.Race.hctxt ); + } else { + emit(" Address %#lx is %ld bytes inside a block " + "of size %ld alloc'd\n", err_ga, delta, + xe->XE.Race.hszB); + VG_(pp_ExeContext)( xe->XE.Race.hctxt ); + } + } + /* If we have a better description of the address, show it. Note that in XML mode, it will already by nicely wrapped up in tags, either or , so we can just emit diff --git a/helgrind/hg_errors.h b/helgrind/hg_errors.h index ee49491..2a19fe3 100644 --- a/helgrind/hg_errors.h +++ b/helgrind/hg_errors.h @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks Ltd + Copyright (C) 2007-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -59,7 +59,10 @@ void HG_(record_error_UnlockBogus) ( Thread*, Addr ); void HG_(record_error_PthAPIerror) ( Thread*, HChar*, Word, HChar* ); void HG_(record_error_LockOrder) ( Thread*, Addr, Addr, ExeContext*, ExeContext* ); -void HG_(record_error_Misc) ( Thread*, HChar* ); +void HG_(record_error_Misc_w_aux) ( Thread*, HChar* errstr, + HChar* auxstr, ExeContext* auxctx ); +void HG_(record_error_Misc) ( Thread* thr, HChar* errstr ); + /* Statistics pertaining to error management. */ extern ULong HG_(stats__LockN_to_P_queries); @@ -67,6 +70,18 @@ extern ULong HG_(stats__LockN_to_P_get_map_size) ( void ); extern ULong HG_(stats__string_table_queries); extern ULong HG_(stats__string_table_get_map_size) ( void ); +/* For error creation: map 'data_addr' to a malloc'd chunk, if any. + Slow linear search accelerated in some special cases normal hash + search of the mallocmeta table. This is an abuse of the normal file + structure since this is exported by hg_main.c, not hg_errors.c. Oh + Well. Returns True if found, False if not. Zero-sized blocks are + considered to contain the searched-for address if they equal that + address. */ +Bool HG_(mm_find_containing_block)( /*OUT*/ExeContext** where, + /*OUT*/Addr* payload, + /*OUT*/SizeT* szB, + Addr data_addr ); + #endif /* ! __HG_ERRORS_H */ /*--------------------------------------------------------------------*/ diff --git a/helgrind/hg_intercepts.c b/helgrind/hg_intercepts.c index 6f8a465..854e07a 100644 --- a/helgrind/hg_intercepts.c +++ b/helgrind/hg_intercepts.c @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks LLP + Copyright (C) 2007-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -56,6 +56,7 @@ #include "pub_tool_redir.h" #include "valgrind.h" #include "helgrind.h" +#include "config.h" #define TRACE_PTH_FNS 0 #define TRACE_QT4_FNS 0 @@ -69,8 +70,19 @@ ret_ty I_WRAP_SONAME_FNNAME_ZZ(VG_Z_LIBPTHREAD_SONAME,f)(args); \ ret_ty I_WRAP_SONAME_FNNAME_ZZ(VG_Z_LIBPTHREAD_SONAME,f)(args) -// Do a client request. This is a macro rather than a function -// so as to avoid having an extra function in the stack trace. +// Do a client request. These are macros rather than a functions so +// as to avoid having an extra frame in stack traces. + +// NB: these duplicate definitions in helgrind.h. But here, we +// can have better typing (Word etc) and assertions, whereas +// in helgrind.h we can't. Obviously it's important the two +// sets of definitions are kept in sync. + +// nuke the previous definitions +#undef DO_CREQ_v_W +#undef DO_CREQ_v_WW +#undef DO_CREQ_W_WW +#undef DO_CREQ_v_WWW #define DO_CREQ_v_W(_creqF, _ty1F,_arg1F) \ do { \ @@ -181,8 +193,6 @@ static char* lame_strerror ( long err ) /*--- pthread_create, pthread_join, pthread_exit ---*/ /*----------------------------------------------------------------*/ -/* Do not rename this function. It contains an unavoidable race and - so is mentioned by name in glibc-*helgrind*.supp. */ static void* mythread_wrapper ( void* xargsV ) { volatile Word* xargs = (volatile Word*) xargsV; @@ -195,7 +205,17 @@ static void* mythread_wrapper ( void* xargsV ) we're ready because (1) we need to make sure it doesn't exit and hence deallocate xargs[] while we still need it, and (2) we don't want either parent nor child to proceed until the tool has - been notified of the child's pthread_t. */ + been notified of the child's pthread_t. + + Note that parent and child access args[] without a lock, + effectively using args[2] as a spinlock in order to get the + parent to wait until the child passes this point. The parent + disables checking on xargs[] before creating the child and + re-enables it once the child goes past this point, so the user + never sees the race. The previous approach (suppressing the + resulting error) was flawed, because it could leave shadow + memory for args[] in a state in which subsequent use of it by + the parent would report further races. */ xargs[2] = 0; /* Now we can no longer safely use xargs[]. */ return (void*) fn( (void*)arg ); @@ -225,6 +245,14 @@ static int pthread_create_WRK(pthread_t *thread, const pthread_attr_t *attr, xargs[0] = (Word)start; xargs[1] = (Word)arg; xargs[2] = 1; /* serves as a spinlock -- sigh */ + /* Disable checking on the spinlock and the two words used to + convey args to the child. Basically we need to make it appear + as if the child never accessed this area, since merely + suppressing the resulting races does not address the issue that + that piece of the parent's stack winds up in the "wrong" state + and therefore may give rise to mysterious races when the parent + comes to re-use this piece of stack in some other frame. */ + VALGRIND_HG_DISABLE_CHECKING(&xargs, sizeof(xargs)); CALL_FN_W_WWWW(ret, fn, thread,attr,mythread_wrapper,&xargs[0]); @@ -244,6 +272,10 @@ static int pthread_create_WRK(pthread_t *thread, const pthread_attr_t *attr, DO_PthAPIerror( "pthread_create", ret ); } + /* Reenable checking on the area previously used to communicate + with the child. */ + VALGRIND_HG_ENABLE_CHECKING(&xargs, sizeof(xargs)); + if (TRACE_PTH_FNS) { fprintf(stderr, " :: pth_create -> %d >>\n", ret); } @@ -993,9 +1025,10 @@ PTH_FUNC(int, pthreadZubarrierZuinit, // pthread_barrier_init fflush(stderr); } - DO_CREQ_v_WW(_VG_USERREQ__HG_PTHREAD_BARRIER_INIT_PRE, - pthread_barrier_t*,bar, - unsigned long,count); + DO_CREQ_v_WWW(_VG_USERREQ__HG_PTHREAD_BARRIER_INIT_PRE, + pthread_barrier_t*, bar, + unsigned long, count, + unsigned long, 0/*!resizable*/); CALL_FN_W_WWW(ret, fn, bar,attr,count); diff --git a/helgrind/hg_lock_n_thread.c b/helgrind/hg_lock_n_thread.c index bcdb236..49aa742 100644 --- a/helgrind/hg_lock_n_thread.c +++ b/helgrind/hg_lock_n_thread.c @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks Ltd + Copyright (C) 2007-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/helgrind/hg_lock_n_thread.h b/helgrind/hg_lock_n_thread.h index 01ae3aa..dc983a5 100644 --- a/helgrind/hg_lock_n_thread.h +++ b/helgrind/hg_lock_n_thread.h @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks Ltd + Copyright (C) 2007-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/helgrind/hg_main.c b/helgrind/hg_main.c index 48d1010..799a8b0 100644 --- a/helgrind/hg_main.c +++ b/helgrind/hg_main.c @@ -8,10 +8,10 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks LLP + Copyright (C) 2007-2010 OpenWorks LLP info@open-works.co.uk - Copyright (C) 2007-2009 Apple, Inc. + Copyright (C) 2007-2010 Apple, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -1084,6 +1084,13 @@ static void shadow_mem_make_NoAccess ( Thread* thr, Addr aIN, SizeT len ) libhb_srange_noaccess( thr->hbthr, aIN, len ); } +static void shadow_mem_make_Untracked ( Thread* thr, Addr aIN, SizeT len ) +{ + if (0 && len > 500) + VG_(printf)("make Untracked ( %#lx, %ld )\n", aIN, len ); + libhb_srange_untrack( thr->hbthr, aIN, len ); +} + /*----------------------------------------------------------------*/ /*--- Event handlers (evh__* functions) ---*/ @@ -1493,6 +1500,16 @@ void evh__new_mem ( Addr a, SizeT len ) { all__sanity_check("evh__new_mem-post"); } +static +void evh__new_mem_stack ( Addr a, SizeT len ) { + if (SHOW_EVENTS >= 2) + VG_(printf)("evh__new_mem_stack(%p, %lu)\n", (void*)a, len ); + shadow_mem_make_New( get_current_Thread(), + -VG_STACK_REDZONE_SZB + a, len ); + if (len >= SCE_BIGRANGE_T && (HG_(clo_sanity_flags) & SCE_BIGRANGE)) + all__sanity_check("evh__new_mem_stack-post"); +} + static void evh__new_mem_w_tid ( Addr a, SizeT len, ThreadId tid ) { if (SHOW_EVENTS >= 2) @@ -1531,6 +1548,7 @@ void evh__set_perms ( Addr a, SizeT len, static void evh__die_mem ( Addr a, SizeT len ) { + // urr, libhb ignores this. if (SHOW_EVENTS >= 2) VG_(printf)("evh__die_mem(%p, %lu)\n", (void*)a, len ); shadow_mem_make_NoAccess( get_current_Thread(), a, len ); @@ -1538,6 +1556,16 @@ void evh__die_mem ( Addr a, SizeT len ) { all__sanity_check("evh__die_mem-post"); } +static +void evh__untrack_mem ( Addr a, SizeT len ) { + // whereas it doesn't ignore this + if (SHOW_EVENTS >= 2) + VG_(printf)("evh__untrack_mem(%p, %lu)\n", (void*)a, len ); + shadow_mem_make_Untracked( get_current_Thread(), a, len ); + if (len >= SCE_BIGRANGE_T && (HG_(clo_sanity_flags) & SCE_BIGRANGE)) + all__sanity_check("evh__untrack_mem-post"); +} + static void evh__copy_mem ( Addr src, Addr dst, SizeT len ) { if (SHOW_EVENTS >= 2) @@ -1952,8 +1980,14 @@ static void evh__HG_PTHREAD_MUTEX_LOCK_PRE ( ThreadId tid, this is a real lock operation (not a speculative "tryLock" kind of thing). Duh. Deadlock coming up; but at least produce an error message. */ - HG_(record_error_Misc)( thr, "Attempt to re-lock a " - "non-recursive lock I already hold" ); + HChar* errstr = "Attempt to re-lock a " + "non-recursive lock I already hold"; + HChar* auxstr = "Lock was previously acquired"; + if (lk->acquired_at) { + HG_(record_error_Misc_w_aux)( thr, errstr, auxstr, lk->acquired_at ); + } else { + HG_(record_error_Misc)( thr, errstr ); + } } } @@ -2004,7 +2038,7 @@ static void evh__HG_PTHREAD_MUTEX_UNLOCK_POST ( ThreadId tid, void* mutex ) /* ------------------------------------------------------- */ -/* -------------- events to do with mutexes -------------- */ +/* -------------- events to do with spinlocks ------------ */ /* ------------------------------------------------------- */ /* All a bit of a kludge. Pretend we're really dealing with ordinary @@ -2701,6 +2735,7 @@ static void evh__HG_POSIX_SEM_WAIT_POST ( ThreadId tid, void* sem ) typedef struct { Bool initted; /* has it yet been initted by guest? */ + Bool resizable; /* is resizing allowed? */ UWord size; /* declared size */ XArray* waiting; /* XA of Thread*. # present is 0 .. .size */ } @@ -2760,15 +2795,16 @@ static void map_barrier_to_Bar_delete ( void* barrier ) { static void evh__HG_PTHREAD_BARRIER_INIT_PRE ( ThreadId tid, void* barrier, - UWord count ) + UWord count, + UWord resizable ) { Thread* thr; Bar* bar; if (SHOW_EVENTS >= 1) VG_(printf)("evh__HG_PTHREAD_BARRIER_INIT_PRE" - "(tid=%d, barrier=%p, count=%lu)\n", - (Int)tid, (void*)barrier, count ); + "(tid=%d, barrier=%p, count=%lu, resizable=%lu)\n", + (Int)tid, (void*)barrier, count, resizable ); thr = map_threads_maybe_lookup( tid ); tl_assert(thr); /* cannot fail - Thread* must already exist */ @@ -2779,6 +2815,12 @@ static void evh__HG_PTHREAD_BARRIER_INIT_PRE ( ThreadId tid, ); } + if (resizable != 0 && resizable != 1) { + HG_(record_error_Misc)( + thr, "pthread_barrier_init: invalid 'resizable' argument" + ); + } + bar = map_barrier_to_Bar_lookup_or_alloc(barrier); tl_assert(bar); @@ -2802,8 +2844,9 @@ static void evh__HG_PTHREAD_BARRIER_INIT_PRE ( ThreadId tid, tl_assert(bar->waiting); tl_assert(VG_(sizeXA)(bar->waiting) == 0); - bar->initted = True; - bar->size = count; + bar->initted = True; + bar->resizable = resizable == 1 ? True : False; + bar->size = count; } @@ -2851,6 +2894,43 @@ static void evh__HG_PTHREAD_BARRIER_DESTROY_PRE ( ThreadId tid, } +/* All the threads have arrived. Now do the Interesting Bit. Get a + new synchronisation object and do a weak send to it from all the + participating threads. This makes its vector clocks be the join of + all the individual threads' vector clocks. Then do a strong + receive from it back to all threads, so that their VCs are a copy + of it (hence are all equal to the join of their original VCs.) */ +static void do_barrier_cross_sync_and_empty ( Bar* bar ) +{ + /* XXX check bar->waiting has no duplicates */ + UWord i; + SO* so = libhb_so_alloc(); + + tl_assert(bar->waiting); + tl_assert(VG_(sizeXA)(bar->waiting) == bar->size); + + /* compute the join ... */ + for (i = 0; i < bar->size; i++) { + Thread* t = *(Thread**)VG_(indexXA)(bar->waiting, i); + Thr* hbthr = t->hbthr; + libhb_so_send( hbthr, so, False/*weak send*/ ); + } + /* ... and distribute to all threads */ + for (i = 0; i < bar->size; i++) { + Thread* t = *(Thread**)VG_(indexXA)(bar->waiting, i); + Thr* hbthr = t->hbthr; + libhb_so_recv( hbthr, so, True/*strong recv*/ ); + } + + /* finally, we must empty out the waiting vector */ + VG_(dropTailXA)(bar->waiting, VG_(sizeXA)(bar->waiting)); + + /* and we don't need this any more. Perhaps a stack-allocated + SO would be better? */ + libhb_so_dealloc(so); +} + + static void evh__HG_PTHREAD_BARRIER_WAIT_PRE ( ThreadId tid, void* barrier ) { @@ -2896,8 +2976,7 @@ static void evh__HG_PTHREAD_BARRIER_WAIT_PRE ( ThreadId tid, */ Thread* thr; Bar* bar; - SO* so; - UWord present, i; + UWord present; if (SHOW_EVENTS >= 1) VG_(printf)("evh__HG_PTHREAD_BARRIER_WAIT_PRE" @@ -2930,39 +3009,74 @@ static void evh__HG_PTHREAD_BARRIER_WAIT_PRE ( ThreadId tid, if (present < bar->size) return; - /* All the threads have arrived. Now do the Interesting Bit. Get - a new synchronisation object and do a weak send to it from all - the participating threads. This makes its vector clocks be the - join of all the individual threads' vector clocks. Then do a - strong receive from it back to all threads, so that their VCs - are a copy of it (hence are all equal to the join of their - original VCs.) */ - so = libhb_so_alloc(); + do_barrier_cross_sync_and_empty(bar); +} - /* XXX check ->waiting has no duplicates */ - tl_assert(bar->waiting); - tl_assert(VG_(sizeXA)(bar->waiting) == bar->size); +static void evh__HG_PTHREAD_BARRIER_RESIZE_PRE ( ThreadId tid, + void* barrier, + UWord newcount ) +{ + Thread* thr; + Bar* bar; + UWord present; - /* compute the join ... */ - for (i = 0; i < bar->size; i++) { - Thread* t = *(Thread**)VG_(indexXA)(bar->waiting, i); - Thr* hbthr = t->hbthr; - libhb_so_send( hbthr, so, False/*weak send*/ ); + if (SHOW_EVENTS >= 1) + VG_(printf)("evh__HG_PTHREAD_BARRIER_RESIZE_PRE" + "(tid=%d, barrier=%p, newcount=%lu)\n", + (Int)tid, (void*)barrier, newcount ); + + thr = map_threads_maybe_lookup( tid ); + tl_assert(thr); /* cannot fail - Thread* must already exist */ + + bar = map_barrier_to_Bar_lookup_or_alloc(barrier); + tl_assert(bar); + + if (!bar->initted) { + HG_(record_error_Misc)( + thr, "pthread_barrier_resize: barrier is uninitialised" + ); + return; /* client is broken .. avoid assertions below */ } - /* ... and distribute to all threads */ - for (i = 0; i < bar->size; i++) { - Thread* t = *(Thread**)VG_(indexXA)(bar->waiting, i); - Thr* hbthr = t->hbthr; - libhb_so_recv( hbthr, so, True/*strong recv*/ ); + + if (!bar->resizable) { + HG_(record_error_Misc)( + thr, "pthread_barrier_resize: barrier is may not be resized" + ); + return; /* client is broken .. avoid assertions below */ } - /* finally, we must empty out the waiting vector */ - VG_(dropTailXA)(bar->waiting, VG_(sizeXA)(bar->waiting)); + if (newcount == 0) { + HG_(record_error_Misc)( + thr, "pthread_barrier_resize: 'newcount' argument is zero" + ); + return; /* client is broken .. avoid assertions below */ + } - /* and we don't need this any more. Perhaps a stack-allocated - SO would be better? */ - libhb_so_dealloc(so); + /* guaranteed by _INIT_PRE above */ + tl_assert(bar->size > 0); + tl_assert(bar->waiting); + /* Guaranteed by this fn */ + tl_assert(newcount > 0); + + if (newcount >= bar->size) { + /* Increasing the capacity. There's no possibility of threads + moving on from the barrier in this situation, so just note + the fact and do nothing more. */ + bar->size = newcount; + } else { + /* Decreasing the capacity. If we decrease it to be equal or + below the number of waiting threads, they will now move past + the barrier, so need to mess with dep edges in the same way + as if the barrier had filled up normally. */ + present = VG_(sizeXA)(bar->waiting); + tl_assert(present >= 0 && present <= bar->size); + if (newcount <= present) { + bar->size = present; /* keep the cross_sync call happy */ + do_barrier_cross_sync_and_empty(bar); + } + bar->size = newcount; + } } @@ -3770,6 +3884,66 @@ static SizeT hg_cli_malloc_usable_size ( ThreadId tid, void* p ) } +/* For error creation: map 'data_addr' to a malloc'd chunk, if any. + Slow linear search. With a bit of hash table help if 'data_addr' + is either the start of a block or up to 15 word-sized steps along + from the start of a block. */ + +static inline Bool addr_is_in_MM_Chunk( MallocMeta* mm, Addr a ) +{ + /* Accept 'a' as within 'mm' if 'mm's size is zero and 'a' points + right at it. */ + if (UNLIKELY(mm->szB == 0 && a == mm->payload)) + return True; + /* else normal interval rules apply */ + if (LIKELY(a < mm->payload)) return False; + if (LIKELY(a >= mm->payload + mm->szB)) return False; + return True; +} + +Bool HG_(mm_find_containing_block)( /*OUT*/ExeContext** where, + /*OUT*/Addr* payload, + /*OUT*/SizeT* szB, + Addr data_addr ) +{ + MallocMeta* mm; + Int i; + const Int n_fast_check_words = 16; + + /* First, do a few fast searches on the basis that data_addr might + be exactly the start of a block or up to 15 words inside. This + can happen commonly via the creq + _VG_USERREQ__HG_CLEAN_MEMORY_HEAPBLOCK. */ + for (i = 0; i < n_fast_check_words; i++) { + mm = VG_(HT_lookup)( hg_mallocmeta_table, + data_addr - (UWord)(UInt)i * sizeof(UWord) ); + if (UNLIKELY(mm && addr_is_in_MM_Chunk(mm, data_addr))) + goto found; + } + + /* Well, this totally sucks. But without using an interval tree or + some such, it's hard to see how to do better. We have to check + every block in the entire table. */ + VG_(HT_ResetIter)(hg_mallocmeta_table); + while ( (mm = VG_(HT_Next)(hg_mallocmeta_table)) ) { + if (UNLIKELY(addr_is_in_MM_Chunk(mm, data_addr))) + goto found; + } + + /* Not found. Bah. */ + return False; + /*NOTREACHED*/ + + found: + tl_assert(mm); + tl_assert(addr_is_in_MM_Chunk(mm, data_addr)); + if (where) *where = mm->where; + if (payload) *payload = mm->payload; + if (szB) *szB = mm->szB; + return True; +} + + /*--------------------------------------------------------------*/ /*--- Instrumentation ---*/ /*--------------------------------------------------------------*/ @@ -3885,6 +4059,7 @@ static Bool is_in_dynamic_linker_shared_object( Addr64 ga ) if (0) VG_(printf)("%s\n", soname); # if defined(VGO_linux) + if (VG_STREQ(soname, VG_U_LD_LINUX_SO_3)) return True; if (VG_STREQ(soname, VG_U_LD_LINUX_SO_2)) return True; if (VG_STREQ(soname, VG_U_LD_LINUX_X86_64_SO_2)) return True; if (VG_STREQ(soname, VG_U_LD64_SO_1)) return True; @@ -4011,19 +4186,41 @@ IRSB* hg_instrument ( VgCallbackClosure* closure, break; } - case Ist_Store: - /* It seems we pretend that store-conditionals don't - exist, viz, just ignore them ... */ - if (st->Ist.Store.resSC == IRTemp_INVALID) { + case Ist_LLSC: { + /* We pretend store-conditionals don't exist, viz, ignore + them. Whereas load-linked's are treated the same as + normal loads. */ + IRType dataTy; + if (st->Ist.LLSC.storedata == NULL) { + /* LL */ + dataTy = typeOfIRTemp(bbIn->tyenv, st->Ist.LLSC.result); if (!inLDSO) { - instrument_mem_access( - bbOut, - st->Ist.Store.addr, - sizeofIRType(typeOfIRExpr(bbIn->tyenv, st->Ist.Store.data)), - True/*isStore*/, + instrument_mem_access( + bbOut, + st->Ist.LLSC.addr, + sizeofIRType(dataTy), + False/*!isStore*/, sizeofIRType(hWordTy) ); } + } else { + /* SC */ + /*ignore */ + } + break; + } + + case Ist_Store: + /* It seems we pretend that store-conditionals don't + exist, viz, just ignore them ... */ + if (!inLDSO) { + instrument_mem_access( + bbOut, + st->Ist.Store.addr, + sizeofIRType(typeOfIRExpr(bbIn->tyenv, st->Ist.Store.data)), + True/*isStore*/, + sizeofIRType(hWordTy) + ); } break; @@ -4137,6 +4334,39 @@ Bool hg_handle_client_request ( ThreadId tid, UWord* args, UWord* ret) } break; + case _VG_USERREQ__HG_CLEAN_MEMORY_HEAPBLOCK: { + Addr payload = 0; + SizeT pszB = 0; + if (0) VG_(printf)("VG_USERREQ__HG_CLEAN_MEMORY_HEAPBLOCK(%#lx)\n", + args[1]); + if (HG_(mm_find_containing_block)(NULL, &payload, &pszB, args[1])) { + if (pszB > 0) { + evh__die_mem(payload, pszB); + evh__new_mem(payload, pszB); + } + *ret = pszB; + } else { + *ret = (UWord)-1; + } + break; + } + + case _VG_USERREQ__HG_ARANGE_MAKE_UNTRACKED: + if (0) VG_(printf)("HG_ARANGE_MAKE_UNTRACKED(%#lx,%ld)\n", + args[1], args[2]); + if (args[2] > 0) { /* length */ + evh__untrack_mem(args[1], args[2]); + } + break; + + case _VG_USERREQ__HG_ARANGE_MAKE_TRACKED: + if (0) VG_(printf)("HG_ARANGE_MAKE_TRACKED(%#lx,%ld)\n", + args[1], args[2]); + if (args[2] > 0) { /* length */ + evh__new_mem(args[1], args[2]); + } + break; + /* --- --- Client requests for Helgrind's use only --- --- */ /* Some thread is telling us its pthread_t value. Record the @@ -4307,8 +4537,15 @@ Bool hg_handle_client_request ( ThreadId tid, UWord* args, UWord* ret) break; case _VG_USERREQ__HG_PTHREAD_BARRIER_INIT_PRE: - /* pth_bar_t*, ulong */ - evh__HG_PTHREAD_BARRIER_INIT_PRE( tid, (void*)args[1], args[2] ); + /* pth_bar_t*, ulong count, ulong resizable */ + evh__HG_PTHREAD_BARRIER_INIT_PRE( tid, (void*)args[1], + args[2], args[3] ); + break; + + case _VG_USERREQ__HG_PTHREAD_BARRIER_RESIZE_PRE: + /* pth_bar_t*, ulong newcount */ + evh__HG_PTHREAD_BARRIER_RESIZE_PRE ( tid, (void*)args[1], + args[2] ); break; case _VG_USERREQ__HG_PTHREAD_BARRIER_WAIT_PRE: @@ -4586,7 +4823,7 @@ static void hg_pre_clo_init ( void ) VG_(details_version) (NULL); VG_(details_description) ("a thread error detector"); VG_(details_copyright_author)( - "Copyright (C) 2007-2009, and GNU GPL'd, by OpenWorks LLP et al."); + "Copyright (C) 2007-2010, and GNU GPL'd, by OpenWorks LLP et al."); VG_(details_bug_reports_to) (VG_BUGS_TO); VG_(details_avg_translation_sizeB) ( 200 ); @@ -4639,7 +4876,7 @@ static void hg_pre_clo_init ( void ) VG_(track_new_mem_stack_signal)( evh__new_mem_w_tid ); VG_(track_new_mem_brk) ( evh__new_mem_w_tid ); VG_(track_new_mem_mmap) ( evh__new_mem_w_perms ); - VG_(track_new_mem_stack) ( evh__new_mem ); + VG_(track_new_mem_stack) ( evh__new_mem_stack ); // FIXME: surely this isn't thread-aware VG_(track_copy_mem_remap) ( evh__copy_mem ); diff --git a/helgrind/hg_wordset.c b/helgrind/hg_wordset.c index 5d33004..330c2e6 100644 --- a/helgrind/hg_wordset.c +++ b/helgrind/hg_wordset.c @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks LLP + Copyright (C) 2007-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/helgrind/hg_wordset.h b/helgrind/hg_wordset.h index 1d1a72f..54a175a 100644 --- a/helgrind/hg_wordset.h +++ b/helgrind/hg_wordset.h @@ -8,7 +8,7 @@ This file is part of Helgrind, a Valgrind tool for detecting errors in threaded programs. - Copyright (C) 2007-2009 OpenWorks LLP + Copyright (C) 2007-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/helgrind/libhb.h b/helgrind/libhb.h index 9ba465d..8d88de6 100644 --- a/helgrind/libhb.h +++ b/helgrind/libhb.h @@ -9,7 +9,7 @@ This file is part of LibHB, a library for implementing and checking the happens-before relationship in concurrent programs. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -126,7 +126,8 @@ void libhb_Thr_resumes ( Thr* thr ); /* Set memory address ranges to new (freshly allocated), or noaccess (no longer accessible). */ void libhb_srange_new ( Thr*, Addr, SizeT ); -void libhb_srange_noaccess ( Thr*, Addr, SizeT ); +void libhb_srange_noaccess ( Thr*, Addr, SizeT ); /* IS IGNORED */ +void libhb_srange_untrack ( Thr*, Addr, SizeT ); /* For the convenience of callers, we offer to store one void* item in a Thr, which we ignore, but the caller can get or set any time. */ diff --git a/helgrind/libhb_core.c b/helgrind/libhb_core.c index 0a07f4b..ce3f889 100644 --- a/helgrind/libhb_core.c +++ b/helgrind/libhb_core.c @@ -9,7 +9,7 @@ This file is part of LibHB, a library for implementing and checking the happens-before relationship in concurrent programs. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -341,6 +341,16 @@ static UWord stats__cline_16to8splits = 0; // # 16-bit accesses split static UWord stats__cline_64to32pulldown = 0; // # calls to pulldown_to_32 static UWord stats__cline_32to16pulldown = 0; // # calls to pulldown_to_16 static UWord stats__cline_16to8pulldown = 0; // # calls to pulldown_to_8 +static UWord stats__vts__tick = 0; // # calls to VTS__tick +static UWord stats__vts__join = 0; // # calls to VTS__join +static UWord stats__vts__cmpLEQ = 0; // # calls to VTS__cmpLEQ +static UWord stats__vts__cmp_structural = 0; // # calls to VTS__cmp_structural +static UWord stats__vts__cmp_structural_slow = 0; // # calls to VTS__cmp_structural w/ slow case +static UWord stats__vts__indexat_slow = 0; // # calls to VTS__indexAt_SLOW +static UWord stats__vts_set__fadoa = 0; // # calls to vts_set__find_and_dealloc__or_add +static UWord stats__vts_set__fadoa_d = 0; // # calls to vts_set__find_and_dealloc__or_add + // that lead to a deallocation + static inline Addr shmem__round_to_SecMap_base ( Addr a ) { return a & ~(N_SECMAP_ARANGE - 1); @@ -1660,6 +1670,9 @@ VTS* VTS__tick ( Thr* me, VTS* vts ) ScalarTS tmp; VTS* res; Word i, n; + + stats__vts__tick++; + tl_assert(me); tl_assert(is_sane_VTS(vts)); //if (0) VG_(printf)("tick vts thrno %ld szin %d\n", @@ -1730,6 +1743,8 @@ VTS* VTS__join ( VTS* a, VTS* b ) Thr* thr; VTS* res; + stats__vts__join++; + tl_assert(a && a->ts); tl_assert(b && b->ts); useda = VG_(sizeXA)( a->ts ); @@ -1821,6 +1836,8 @@ static Thr* VTS__cmpLEQ ( VTS* a, VTS* b ) Word ia, ib, useda, usedb; ULong tyma, tymb; + stats__vts__cmpLEQ++; + tl_assert(a && a->ts); tl_assert(b && b->ts); useda = VG_(sizeXA)( a->ts ); @@ -1903,37 +1920,59 @@ static Thr* VTS__cmpLEQ ( VTS* a, VTS* b ) /* Compute an arbitrary structural (total) ordering on the two args, based on their VCs, so they can be looked up in a table, tree, etc. - Returns -1, 0 or 1. (really just 'deriving Ord' :-) + Returns -1, 0 or 1. (really just 'deriving Ord' :-) This can be + performance critical so there is some effort expended to make it sa + fast as possible. */ Word VTS__cmp_structural ( VTS* a, VTS* b ) { /* We just need to generate an arbitrary total ordering based on a->ts and b->ts. Preferably do it in a way which comes across likely differences relatively quickly. */ - Word i, useda, usedb; - ScalarTS *tmpa, *tmpb; - - tl_assert(a && a->ts); - tl_assert(b && b->ts); - useda = VG_(sizeXA)( a->ts ); - usedb = VG_(sizeXA)( b->ts ); + Word i; + Word useda = 0, usedb = 0; + ScalarTS *ctsa = NULL, *ctsb = NULL; + + stats__vts__cmp_structural++; + + tl_assert(a); + tl_assert(b); + + VG_(getContentsXA_UNSAFE)( a->ts, (void**)&ctsa, &useda ); + VG_(getContentsXA_UNSAFE)( b->ts, (void**)&ctsb, &usedb ); + + if (LIKELY(useda == usedb)) { + ScalarTS *tmpa = NULL, *tmpb = NULL; + stats__vts__cmp_structural_slow++; + /* Same length vectors. Find the first difference, if any, as + fast as possible. */ + for (i = 0; i < useda; i++) { + tmpa = &ctsa[i]; + tmpb = &ctsb[i]; + if (LIKELY(tmpa->tym == tmpb->tym && tmpa->thr == tmpb->thr)) + continue; + else + break; + } + if (UNLIKELY(i == useda)) { + /* They're identical. */ + return 0; + } else { + tl_assert(i >= 0 && i < useda); + if (tmpa->tym < tmpb->tym) return -1; + if (tmpa->tym > tmpb->tym) return 1; + if (tmpa->thr < tmpb->thr) return -1; + if (tmpa->thr > tmpb->thr) return 1; + /* we just established them as non-identical, hence: */ + } + /*NOTREACHED*/ + tl_assert(0); + } if (useda < usedb) return -1; if (useda > usedb) return 1; - - /* Same length vectors, so let's step through them together. */ - tl_assert(useda == usedb); - for (i = 0; i < useda; i++) { - tmpa = VG_(indexXA)( a->ts, i ); - tmpb = VG_(indexXA)( b->ts, i ); - if (tmpa->tym < tmpb->tym) return -1; - if (tmpa->tym > tmpb->tym) return 1; - if (tmpa->thr < tmpb->thr) return -1; - if (tmpa->thr > tmpb->thr) return 1; - } - - /* They're identical. */ - return 0; + /*NOTREACHED*/ + tl_assert(0); } @@ -1972,6 +2011,7 @@ void VTS__show ( HChar* buf, Int nBuf, VTS* vts ) { */ ULong VTS__indexAt_SLOW ( VTS* vts, Thr* idx ) { UWord i, n; + stats__vts__indexat_slow++; tl_assert(vts && vts->ts); n = VG_(sizeXA)( vts->ts ); for (i = 0; i < n; i++) { @@ -2029,12 +2069,14 @@ static void vts_set_init ( void ) static VTS* vts_set__find_and_dealloc__or_add ( VTS* cand ) { UWord keyW, valW; + stats__vts_set__fadoa++; /* lookup cand (by value) */ if (VG_(lookupFM)( vts_set, &keyW, &valW, (UWord)cand )) { /* found it */ tl_assert(valW == 0); /* if this fails, cand (by ref) was already present (!) */ tl_assert(keyW != (UWord)cand); + stats__vts_set__fadoa_d++; VTS__delete(cand); return (VTS*)keyW; } else { @@ -3183,7 +3225,7 @@ static UWord stats__ctxt_tab_cmps = 0; /////////////////////////////////////////////////////// -//// Part (1): An OSet of RCECs +//// Part (1): A hash table of RCECs /// #define N_FRAMES 8 @@ -3250,7 +3292,7 @@ static void free_RCEC ( RCEC* rcec ) { tl_assert(rcec->magic == RCEC_MAGIC); gal_Free( &rcec_group_allocator, rcec ); } -//////////// END OldRef group allocator +//////////// END RCEC group allocator /* Find 'ec' in the RCEC list whose head pointer lives at 'headp' and @@ -5469,15 +5511,25 @@ void libhb_shutdown ( Bool show_stats ) VG_(printf)("%s","\n"); - VG_(printf)(" libhb: %'13llu msmcread (%'llu changed)\n", + VG_(printf)(" libhb: %'13llu msmcread (%'llu dragovers)\n", stats__msmcread, stats__msmcread_change); - VG_(printf)(" libhb: %'13llu msmcwrite (%'llu changed)\n", + VG_(printf)(" libhb: %'13llu msmcwrite (%'llu dragovers)\n", stats__msmcwrite, stats__msmcwrite_change); VG_(printf)(" libhb: %'13llu cmpLEQ queries (%'llu misses)\n", stats__cmpLEQ_queries, stats__cmpLEQ_misses); VG_(printf)(" libhb: %'13llu join2 queries (%'llu misses)\n", stats__join2_queries, stats__join2_misses); + VG_(printf)("%s","\n"); + VG_(printf)( " libhb: VTSops: tick %'lu, join %'lu, cmpLEQ %'lu\n", + stats__vts__tick, stats__vts__join, stats__vts__cmpLEQ ); + VG_(printf)( " libhb: VTSops: cmp_structural %'lu (%'lu slow)\n", + stats__vts__cmp_structural, stats__vts__cmp_structural_slow ); + VG_(printf)( " libhb: VTSset: find_and_dealloc__or_add %'lu (%'lu deallocd)\n", + stats__vts_set__fadoa, stats__vts_set__fadoa_d ); + VG_(printf)( " libhb: VTSops: indexAt_SLOW %'lu\n", + stats__vts__indexat_slow ); + VG_(printf)("%s","\n"); VG_(printf)( " libhb: %ld entries in vts_table (approximately %lu bytes)\n", @@ -5659,7 +5711,8 @@ void libhb_so_recv ( Thr* thr, SO* so, Bool strong_recv ) //VtsID__rcinc(thr->viW); } - Filter__clear(thr->filter, "libhb_so_recv"); + if (thr->filter) + Filter__clear(thr->filter, "libhb_so_recv"); note_local_Kw_n_stack_for(thr); if (strong_recv) @@ -5716,6 +5769,16 @@ void libhb_srange_noaccess ( Thr* thr, Addr a, SizeT szB ) /* do nothing */ } +void libhb_srange_untrack ( Thr* thr, Addr a, SizeT szB ) +{ + SVal sv = SVal_NOACCESS; + tl_assert(is_sane_SVal_C(sv)); + if (0 && TRACEME(a,szB)) trace(thr,a,szB,"untrack-before"); + zsm_sset_range( a, szB, sv ); + Filter__clear_range( thr->filter, a, szB ); + if (0 && TRACEME(a,szB)) trace(thr,a,szB,"untrack-after "); +} + void* libhb_get_Thr_opaque ( Thr* thr ) { tl_assert(thr); return thr->opaque; diff --git a/helgrind/tests/Makefile.am b/helgrind/tests/Makefile.am index a56bc3c..ff8bcb3 100644 --- a/helgrind/tests/Makefile.am +++ b/helgrind/tests/Makefile.am @@ -129,6 +129,16 @@ if ! VGCONF_PLATFORMS_INCLUDE_X86_DARWIN tc22_exit_w_lock endif +if VGCONF_PLATFORMS_INCLUDE_ARM_LINUX +annotate_hbefore_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8 +tc07_hbl1_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8 +tc08_hbl2_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8 +else +annotate_hbefore_CFLAGS = $(AM_CFLAGS) +tc07_hbl1_CFLAGS = $(AM_CFLAGS) +tc08_hbl2_CFLAGS = $(AM_CFLAGS) +endif + if HAVE_PTHREAD_BARRIER check_PROGRAMS += bar_bad bar_trivial endif diff --git a/helgrind/tests/annotate_hbefore.c b/helgrind/tests/annotate_hbefore.c index 2df2982..704e4ae 100644 --- a/helgrind/tests/annotate_hbefore.c +++ b/helgrind/tests/annotate_hbefore.c @@ -117,21 +117,56 @@ UWord do_acasW ( UWord* addr, UWord expected, UWord nyu ) { UWord block[4] = { (UWord)addr, expected, nyu, 2 }; __asm__ __volatile__( + "pushl %%ebx" "\n\t" "movl 0(%%esi), %%edi" "\n\t" // addr "movl 4(%%esi), %%eax" "\n\t" // expected "movl 8(%%esi), %%ebx" "\n\t" // nyu "xorl %%ecx,%%ecx" "\n\t" "lock; cmpxchgl %%ebx,(%%edi)" "\n\t" "setz %%cl" "\n\t" - "movl %%ecx, 12(%%esi)" "\n" + "movl %%ecx, 12(%%esi)" "\n\t" + "popl %%ebx" "\n" : /*out*/ : /*in*/ "S"(&block[0]) - : /*trash*/"memory","cc","edi","eax","ebx","ecx" + : /*trash*/"memory","cc","edi","eax","ecx" ); assert(block[3] == 0 || block[3] == 1); return block[3] & 1; } +#elif defined(VGA_arm) + +// arm +/* return 1 if success, 0 if failure */ +UWord do_acasW ( UWord* addr, UWord expected, UWord nyu ) +{ + UWord old, success; + UWord block[2] = { (UWord)addr, nyu }; + + /* Fetch the old value, and set the reservation */ + __asm__ __volatile__ ( + "ldrex %0, [%1]" "\n" + : /*out*/ "=r"(old) + : /*in*/ "r"(addr) + ); + + /* If the old value isn't as expected, we've had it */ + if (old != expected) return 0; + + /* otherwise try to stuff the new value in */ + __asm__ __volatile__( + "ldr r4, [%1, #0]" "\n\t" + "ldr r5, [%1, #4]" "\n\t" + "strex r6, r5, [r4, #0]" "\n\t" + "eor %0, r6, #1" "\n\t" + : /*out*/ "=r"(success) + : /*in*/ "r"(&block[0]) + : /*trash*/ "r4","r5","r6","memory" + ); + assert(success == 0 || success == 1); + return success; +} + #endif void atomic_incW ( UWord* w ) diff --git a/helgrind/tests/pth_barrier1.stderr.exp b/helgrind/tests/pth_barrier1.stderr.exp index a277480..b16e71f 100644 --- a/helgrind/tests/pth_barrier1.stderr.exp +++ b/helgrind/tests/pth_barrier1.stderr.exp @@ -18,4 +18,8 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 0 bytes inside a block of size 4 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) diff --git a/helgrind/tests/pth_barrier2.stderr.exp b/helgrind/tests/pth_barrier2.stderr.exp index f5a4952..8330af9 100644 --- a/helgrind/tests/pth_barrier2.stderr.exp +++ b/helgrind/tests/pth_barrier2.stderr.exp @@ -18,6 +18,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 0 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -27,6 +31,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -36,6 +44,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -45,6 +57,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -54,6 +70,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -63,6 +83,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -72,6 +96,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -81,6 +109,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -90,6 +122,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -99,6 +135,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -108,6 +148,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -117,6 +161,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -126,6 +174,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -135,6 +187,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -144,6 +200,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -153,6 +213,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -162,6 +226,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -171,6 +239,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -180,6 +252,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -189,6 +265,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -198,6 +278,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -207,6 +291,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -216,6 +304,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -225,6 +317,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -234,6 +330,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -243,6 +343,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 100 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -252,6 +356,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 104 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -261,6 +369,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 108 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -270,6 +382,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 112 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -279,6 +395,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 116 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -288,6 +408,10 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 120 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) @@ -297,4 +421,8 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 124 bytes inside a block of size 128 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) diff --git a/helgrind/tests/pth_barrier3.stderr.exp b/helgrind/tests/pth_barrier3.stderr.exp index a277480..b16e71f 100644 --- a/helgrind/tests/pth_barrier3.stderr.exp +++ b/helgrind/tests/pth_barrier3.stderr.exp @@ -18,4 +18,8 @@ Possible data race during write of size 4 at 0x........ by thread #x at 0x........: threadfunc (pth_barrier.c:57) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 0 bytes inside a block of size 4 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: barriers_and_races (pth_barrier.c:72) + by 0x........: main (pth_barrier.c:107) diff --git a/helgrind/tests/pth_spinlock.vgtest b/helgrind/tests/pth_spinlock.vgtest index 512b287..90280a5 100644 --- a/helgrind/tests/pth_spinlock.vgtest +++ b/helgrind/tests/pth_spinlock.vgtest @@ -1,3 +1,7 @@ -prereq: test -e ../../drd/tests/pth_spinlock +# Disabled this test because it fails intermittently. +# See also https://bugs.kde.org/show_bug.cgi?id=205452. + +#prereq: test -e ../../drd/tests/pth_spinlock +prereq: false vgopts: -q prog: ../../drd/tests/pth_spinlock diff --git a/helgrind/tests/tc06_two_races_xml.stderr.exp b/helgrind/tests/tc06_two_races_xml.stderr.exp index 1999375..eed0cc8 100644 --- a/helgrind/tests/tc06_two_races_xml.stderr.exp +++ b/helgrind/tests/tc06_two_races_xml.stderr.exp @@ -29,12 +29,12 @@ - 1 + 1 - 2 + 2 0x........ @@ -294,6 +294,7 @@ declared at tc06_two_races.c:9 tc06_two_races.c ... + FINISHED diff --git a/helgrind/tests/tc07_hbl1.c b/helgrind/tests/tc07_hbl1.c index 12253aa..d48f7bb 100644 --- a/helgrind/tests/tc07_hbl1.c +++ b/helgrind/tests/tc07_hbl1.c @@ -6,28 +6,38 @@ /* Simple test program, no race. Parent and child both modify x and use the hardware bus lock. */ +#undef PLAT_ppc64_aix5 +#undef PLAT_ppc32_aix5 +#undef PLAT_x86_darwin +#undef PLAT_amd64_darwin #undef PLAT_x86_linux #undef PLAT_amd64_linux #undef PLAT_ppc32_linux #undef PLAT_ppc64_linux -#undef PLAT_ppc32_aix5 -#undef PLAT_ppc64_aix5 +#undef PLAT_arm_linux -#if !defined(_AIX) && defined(__i386__) +#if defined(_AIX) && defined(__64BIT__) +# define PLAT_ppc64_aix5 1 +#elif defined(_AIX) && !defined(__64BIT__) +# define PLAT_ppc32_aix5 1 +#elif defined(__APPLE__) && defined(__i386__) +# define PLAT_x86_darwin 1 +#elif defined(__APPLE__) && defined(__x86_64__) +# define PLAT_amd64_darwin 1 +#elif defined(__linux__) && defined(__i386__) # define PLAT_x86_linux 1 -#elif !defined(_AIX) && defined(__x86_64__) +#elif defined(__linux__) && defined(__x86_64__) # define PLAT_amd64_linux 1 -#elif !defined(_AIX) && defined(__powerpc__) && !defined(__powerpc64__) +#elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__) # define PLAT_ppc32_linux 1 -#elif !defined(_AIX) && defined(__powerpc__) && defined(__powerpc64__) +#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) # define PLAT_ppc64_linux 1 -#elif defined(_AIX) && defined(__64BIT__) -# define PLAT_ppc64_aix5 1 -#elif defined(_AIX) && !defined(__64BIT__) -# define PLAT_ppc32_aix5 1 +#elif defined(__linux__) && defined(__arm__) +# define PLAT_arm_linux 1 #endif -#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) +#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) \ + || defined(PLAT_amd64_darwin) || defined(PLAT_x86_darwin) # define INC(_lval,_lqual) \ __asm__ __volatile__ ( \ "lock ; incl (%0)" : /*out*/ : /*in*/"r"(&(_lval)) : "memory", "cc" ) @@ -43,6 +53,18 @@ : /*out*/ : /*in*/ "b"(&(_lval)) \ : /*trash*/ "r15", "cr0", "memory" \ ) +#elif defined(PLAT_arm_linux) +# define INC(_lval,_lqual) \ + __asm__ __volatile__( \ + "L1xyzzy1" _lqual ":\n" \ + " ldrex r8, [%0, #0]\n" \ + " add r8, r8, #1\n" \ + " strex r9, r8, [%0, #0]\n" \ + " cmp r9, #0\n" \ + " bne L1xyzzy1" _lqual \ + : /*out*/ : /*in*/ "r"(&(_lval)) \ + : /*trash*/ "r8", "r9", "cc", "memory" \ + ); #else # error "Fix Me for this platform" #endif diff --git a/helgrind/tests/tc08_hbl2.c b/helgrind/tests/tc08_hbl2.c index d67435a..0ca3f3a 100644 --- a/helgrind/tests/tc08_hbl2.c +++ b/helgrind/tests/tc08_hbl2.c @@ -22,29 +22,39 @@ child joins back to parent. Parent (writer) uses hardware bus lock; child is only reading and so does not need to use a bus lock. */ - +#undef PLAT_ppc64_aix5 +#undef PLAT_ppc32_aix5 +#undef PLAT_x86_darwin +#undef PLAT_amd64_darwin #undef PLAT_x86_linux #undef PLAT_amd64_linux #undef PLAT_ppc32_linux #undef PLAT_ppc64_linux -#undef PLAT_ppc32_aix5 -#undef PLAT_ppc64_aix5 +#undef PLAT_arm_linux -#if !defined(_AIX) && defined(__i386__) +#if defined(_AIX) && defined(__64BIT__) +# define PLAT_ppc64_aix5 1 +#elif defined(_AIX) && !defined(__64BIT__) +# define PLAT_ppc32_aix5 1 +#elif defined(__APPLE__) && defined(__i386__) +# define PLAT_x86_darwin 1 +#elif defined(__APPLE__) && defined(__x86_64__) +# define PLAT_amd64_darwin 1 +#elif defined(__linux__) && defined(__i386__) # define PLAT_x86_linux 1 -#elif !defined(_AIX) && defined(__x86_64__) +#elif defined(__linux__) && defined(__x86_64__) # define PLAT_amd64_linux 1 -#elif !defined(_AIX) && defined(__powerpc__) && !defined(__powerpc64__) +#elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__) # define PLAT_ppc32_linux 1 -#elif !defined(_AIX) && defined(__powerpc__) && defined(__powerpc64__) +#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) # define PLAT_ppc64_linux 1 -#elif defined(_AIX) && defined(__64BIT__) -# define PLAT_ppc64_aix5 1 -#elif defined(_AIX) && !defined(__64BIT__) -# define PLAT_ppc32_aix5 1 +#elif defined(__linux__) && defined(__arm__) +# define PLAT_arm_linux 1 #endif -#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) + +#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) \ + || defined(PLAT_amd64_darwin) || defined(PLAT_x86_darwin) # define INC(_lval,_lqual) \ __asm__ __volatile__ ( \ "lock ; incl (%0)" : /*out*/ : /*in*/"r"(&(_lval)) : "memory", "cc" ) @@ -60,6 +70,18 @@ : /*out*/ : /*in*/ "b"(&(_lval)) \ : /*trash*/ "r15", "cr0", "memory" \ ) +#elif defined(PLAT_arm_linux) +# define INC(_lval,_lqual) \ + __asm__ __volatile__( \ + "L1xyzzy1" _lqual ":\n" \ + " ldrex r8, [%0, #0]\n" \ + " add r8, r8, #1\n" \ + " strex r9, r8, [%0, #0]\n" \ + " cmp r9, #0\n" \ + " bne L1xyzzy1" _lqual \ + : /*out*/ : /*in*/ "r"(&(_lval)) \ + : /*trash*/ "r8", "r9", "cc", "memory" \ + ); #else # error "Fix Me for this platform" #endif diff --git a/helgrind/tests/tc09_bad_unlock.stderr.exp-glibc25-amd64 b/helgrind/tests/tc09_bad_unlock.stderr.exp-glibc25-amd64 index 5c6a8fc..f8e4a50 100644 --- a/helgrind/tests/tc09_bad_unlock.stderr.exp-glibc25-amd64 +++ b/helgrind/tests/tc09_bad_unlock.stderr.exp-glibc25-amd64 @@ -51,6 +51,10 @@ Thread #x: Attempt to re-lock a non-recursive lock I already hold at 0x........: pthread_mutex_lock (hg_intercepts.c:...) by 0x........: nearly_main (tc09_bad_unlock.c:32) by 0x........: main (tc09_bad_unlock.c:50) + Lock was previously acquired + at 0x........: pthread_mutex_lock (hg_intercepts.c:...) + by 0x........: nearly_main (tc09_bad_unlock.c:32) + by 0x........: main (tc09_bad_unlock.c:49) Thread #x: Bug in libpthread: recursive write lock granted on mutex/wrlock which does not support recursion at 0x........: pthread_mutex_lock (hg_intercepts.c:...) diff --git a/helgrind/tests/tc11_XCHG.c b/helgrind/tests/tc11_XCHG.c index 22c6baf..54cb494 100644 --- a/helgrind/tests/tc11_XCHG.c +++ b/helgrind/tests/tc11_XCHG.c @@ -9,29 +9,39 @@ use the hardware bus lock (implicitly, since XCHG r,m on x86/amd64 does not require an explicit LOCK prefix.). */ +#undef PLAT_ppc64_aix5 +#undef PLAT_ppc32_aix5 +#undef PLAT_x86_darwin +#undef PLAT_amd64_darwin #undef PLAT_x86_linux #undef PLAT_amd64_linux #undef PLAT_ppc32_linux #undef PLAT_ppc64_linux -#undef PLAT_ppc32_aix5 -#undef PLAT_ppc64_aix5 +#undef PLAT_arm_linux -#if !defined(_AIX) && defined(__i386__) +#if defined(_AIX) && defined(__64BIT__) +# define PLAT_ppc64_aix5 1 +#elif defined(_AIX) && !defined(__64BIT__) +# define PLAT_ppc32_aix5 1 +#elif defined(__APPLE__) && defined(__i386__) +# define PLAT_x86_darwin 1 +#elif defined(__APPLE__) && defined(__x86_64__) +# define PLAT_amd64_darwin 1 +#elif defined(__linux__) && defined(__i386__) # define PLAT_x86_linux 1 -#elif !defined(_AIX) && defined(__x86_64__) +#elif defined(__linux__) && defined(__x86_64__) # define PLAT_amd64_linux 1 -#elif !defined(_AIX) && defined(__powerpc__) && !defined(__powerpc64__) +#elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__) # define PLAT_ppc32_linux 1 -#elif !defined(_AIX) && defined(__powerpc__) && defined(__powerpc64__) +#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) # define PLAT_ppc64_linux 1 -#elif defined(_AIX) && defined(__64BIT__) -# define PLAT_ppc64_aix5 1 -#elif defined(_AIX) && !defined(__64BIT__) -# define PLAT_ppc32_aix5 1 +#elif defined(__linux__) && defined(__arm__) +# define PLAT_arm_linux 1 #endif -#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) +#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) \ + || defined(PLAT_amd64_darwin) || defined(PLAT_x86_darwin) # define XCHG_M_R(_addr,_lval) \ __asm__ __volatile__( \ "xchgl %0, %1" \ @@ -48,7 +58,8 @@ ) #elif defined(PLAT_ppc32_linux) || defined(PLAT_ppc64_linux) \ - || defined(PLAT_ppc32_aix5) || defined(PLAT_ppc64_aix5) + || defined(PLAT_ppc32_aix5) || defined(PLAT_ppc64_aix5) \ + || defined(PLAT_arm_linux) # if defined(HAVE_BUILTIN_ATOMIC) # define XCHG_M_R(_addr,_lval) \ do { \ diff --git a/helgrind/tests/tc19_shadowmem.stderr.exp b/helgrind/tests/tc19_shadowmem.stderr.exp index e9504fe..378c7f8 100644 --- a/helgrind/tests/tc19_shadowmem.stderr.exp +++ b/helgrind/tests/tc19_shadowmem.stderr.exp @@ -25,6 +25,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:288) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 0 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 1 ---------- Thread #x was created @@ -47,6 +50,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 1 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 2 ---------- Thread #x was created @@ -69,6 +75,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:292) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 2 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 3 ---------- Thread #x was created @@ -91,6 +100,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 3 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 4 ---------- Thread #x was created @@ -113,6 +125,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:296) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 5 ---------- Thread #x was created @@ -135,6 +150,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 5 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 6 ---------- Thread #x was created @@ -157,6 +175,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:300) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 7 ---------- Thread #x was created @@ -179,6 +200,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 7 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 8 ---------- Thread #x was created @@ -201,6 +225,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:304) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 9 ---------- Thread #x was created @@ -223,6 +250,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 9 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 10 ---------- Thread #x was created @@ -245,6 +275,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:308) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 11 ---------- Thread #x was created @@ -267,6 +300,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 11 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 12 ---------- Thread #x was created @@ -289,6 +325,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:312) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 13 ---------- Thread #x was created @@ -311,6 +350,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 13 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 14 ---------- Thread #x was created @@ -333,6 +375,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:316) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 15 ---------- Thread #x was created @@ -355,6 +400,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 15 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 16 ---------- Thread #x was created @@ -377,6 +425,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:320) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 17 ---------- Thread #x was created @@ -399,6 +450,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 17 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 18 ---------- Thread #x was created @@ -421,6 +475,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:324) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 19 ---------- Thread #x was created @@ -443,6 +500,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 19 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 20 ---------- Thread #x was created @@ -465,6 +525,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:328) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 21 ---------- Thread #x was created @@ -487,6 +550,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 21 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 22 ---------- Thread #x was created @@ -509,6 +575,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:332) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 23 ---------- Thread #x was created @@ -531,6 +600,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 23 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 24 ---------- Thread #x was created @@ -553,6 +625,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:336) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 25 ---------- Thread #x was created @@ -575,6 +650,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 25 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 26 ---------- Thread #x was created @@ -597,6 +675,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:340) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 27 ---------- Thread #x was created @@ -619,6 +700,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 27 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 28 ---------- Thread #x was created @@ -641,6 +725,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:344) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 29 ---------- Thread #x was created @@ -663,6 +750,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 29 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 30 ---------- Thread #x was created @@ -685,6 +775,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:348) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 31 ---------- Thread #x was created @@ -707,6 +800,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 31 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 32 ---------- Thread #x was created @@ -729,6 +825,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:352) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 33 ---------- Thread #x was created @@ -751,6 +850,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 33 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 34 ---------- Thread #x was created @@ -773,6 +875,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:356) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 35 ---------- Thread #x was created @@ -795,6 +900,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 35 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 36 ---------- Thread #x was created @@ -817,6 +925,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:360) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 37 ---------- Thread #x was created @@ -839,6 +950,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 37 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 38 ---------- Thread #x was created @@ -861,6 +975,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:364) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 39 ---------- Thread #x was created @@ -883,6 +1000,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 39 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 40 ---------- Thread #x was created @@ -905,6 +1025,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:368) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 41 ---------- Thread #x was created @@ -927,6 +1050,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 41 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 42 ---------- Thread #x was created @@ -949,6 +1075,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:372) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 43 ---------- Thread #x was created @@ -971,6 +1100,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 43 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 44 ---------- Thread #x was created @@ -993,6 +1125,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:376) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 45 ---------- Thread #x was created @@ -1015,6 +1150,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 45 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 46 ---------- Thread #x was created @@ -1037,6 +1175,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:380) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 47 ---------- Thread #x was created @@ -1059,6 +1200,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 47 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 48 ---------- Thread #x was created @@ -1081,6 +1225,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:384) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 49 ---------- Thread #x was created @@ -1103,6 +1250,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 49 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 50 ---------- Thread #x was created @@ -1125,6 +1275,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:388) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 51 ---------- Thread #x was created @@ -1147,6 +1300,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 51 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 52 ---------- Thread #x was created @@ -1169,6 +1325,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:392) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 53 ---------- Thread #x was created @@ -1191,6 +1350,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 53 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 54 ---------- Thread #x was created @@ -1213,6 +1375,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:396) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 55 ---------- Thread #x was created @@ -1235,6 +1400,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 55 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 56 ---------- Thread #x was created @@ -1257,6 +1425,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:400) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 57 ---------- Thread #x was created @@ -1279,6 +1450,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 57 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 58 ---------- Thread #x was created @@ -1301,6 +1475,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:404) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 59 ---------- Thread #x was created @@ -1323,6 +1500,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 59 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 60 ---------- Thread #x was created @@ -1345,6 +1525,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:408) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 61 ---------- Thread #x was created @@ -1367,6 +1550,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 61 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 62 ---------- Thread #x was created @@ -1389,6 +1575,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:412) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 63 ---------- Thread #x was created @@ -1411,6 +1600,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 63 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 64 ---------- Thread #x was created @@ -1433,6 +1625,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:416) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 65 ---------- Thread #x was created @@ -1455,6 +1650,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 65 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 66 ---------- Thread #x was created @@ -1477,6 +1675,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:420) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 67 ---------- Thread #x was created @@ -1499,6 +1700,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 67 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 68 ---------- Thread #x was created @@ -1521,6 +1725,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:424) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 69 ---------- Thread #x was created @@ -1543,6 +1750,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 69 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 70 ---------- Thread #x was created @@ -1565,6 +1775,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:428) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 71 ---------- Thread #x was created @@ -1587,6 +1800,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 71 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 72 ---------- Thread #x was created @@ -1609,6 +1825,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:432) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 73 ---------- Thread #x was created @@ -1631,6 +1850,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 73 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 74 ---------- Thread #x was created @@ -1653,6 +1875,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:436) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 75 ---------- Thread #x was created @@ -1675,6 +1900,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 75 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 76 ---------- Thread #x was created @@ -1697,6 +1925,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:440) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 77 ---------- Thread #x was created @@ -1719,6 +1950,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 77 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 78 ---------- Thread #x was created @@ -1741,6 +1975,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:444) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 79 ---------- Thread #x was created @@ -1763,6 +2000,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 79 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 80 ---------- Thread #x was created @@ -1785,6 +2025,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:448) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 81 ---------- Thread #x was created @@ -1807,6 +2050,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 81 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 82 ---------- Thread #x was created @@ -1829,6 +2075,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:452) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 83 ---------- Thread #x was created @@ -1851,6 +2100,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 83 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 84 ---------- Thread #x was created @@ -1873,6 +2125,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:456) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 85 ---------- Thread #x was created @@ -1895,6 +2150,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 85 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 86 ---------- Thread #x was created @@ -1917,6 +2175,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:460) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 87 ---------- Thread #x was created @@ -1939,6 +2200,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 87 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 88 ---------- Thread #x was created @@ -1961,6 +2225,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:464) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 89 ---------- Thread #x was created @@ -1983,6 +2250,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 89 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 90 ---------- Thread #x was created @@ -2005,6 +2275,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:468) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 91 ---------- Thread #x was created @@ -2027,6 +2300,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 91 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 92 ---------- Thread #x was created @@ -2049,6 +2325,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:472) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 93 ---------- Thread #x was created @@ -2071,6 +2350,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:474) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 93 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 94 ---------- Thread #x was created @@ -2093,6 +2375,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:476) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 95 ---------- Thread #x was created @@ -2115,6 +2400,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:478) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 95 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 96 ---------- Thread #x was created @@ -2137,6 +2425,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:480) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 97 ---------- Thread #x was created @@ -2159,6 +2450,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:482) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 97 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- char gran, 0 .. 99, skip 98 ---------- Thread #x was created @@ -2181,6 +2475,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:484) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 98 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ========================================================== @@ -2208,6 +2505,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:288) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 0 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) More than 100 errors detected. Subsequent errors @@ -2233,6 +2533,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 1 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2244,6 +2547,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 2 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 2 ---------- Thread #x was created @@ -2266,6 +2572,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:292) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 2 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 3 ---------- Thread #x was created @@ -2288,6 +2597,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 3 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2299,6 +2611,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 4 ---------- Thread #x was created @@ -2321,6 +2636,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:296) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 5 ---------- Thread #x was created @@ -2343,6 +2661,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 5 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2354,6 +2675,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 6 ---------- Thread #x was created @@ -2376,6 +2700,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:300) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 7 ---------- Thread #x was created @@ -2398,6 +2725,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 7 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2409,6 +2739,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 8 ---------- Thread #x was created @@ -2431,6 +2764,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:304) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 9 ---------- Thread #x was created @@ -2453,6 +2789,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 9 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2464,6 +2803,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 10 ---------- Thread #x was created @@ -2486,6 +2828,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:308) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 11 ---------- Thread #x was created @@ -2508,6 +2853,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 11 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2519,6 +2867,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 12 ---------- Thread #x was created @@ -2541,6 +2892,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:312) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 13 ---------- Thread #x was created @@ -2563,6 +2917,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 13 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2574,6 +2931,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 14 ---------- Thread #x was created @@ -2596,6 +2956,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:316) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 15 ---------- Thread #x was created @@ -2618,6 +2981,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 15 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2629,6 +2995,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 16 ---------- Thread #x was created @@ -2651,6 +3020,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:320) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 17 ---------- Thread #x was created @@ -2673,6 +3045,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 17 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2684,6 +3059,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 18 ---------- Thread #x was created @@ -2706,6 +3084,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:324) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 19 ---------- Thread #x was created @@ -2728,6 +3109,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 19 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2739,6 +3123,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 20 ---------- Thread #x was created @@ -2761,6 +3148,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:328) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 21 ---------- Thread #x was created @@ -2783,6 +3173,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 21 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2794,6 +3187,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 22 ---------- Thread #x was created @@ -2816,6 +3212,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:332) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 23 ---------- Thread #x was created @@ -2838,6 +3237,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 23 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2849,6 +3251,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 24 ---------- Thread #x was created @@ -2871,6 +3276,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:336) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 25 ---------- Thread #x was created @@ -2893,6 +3301,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 25 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2904,6 +3315,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 26 ---------- Thread #x was created @@ -2926,6 +3340,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:340) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 27 ---------- Thread #x was created @@ -2948,6 +3365,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 27 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -2959,6 +3379,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 28 ---------- Thread #x was created @@ -2981,6 +3404,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:344) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 29 ---------- Thread #x was created @@ -3003,6 +3429,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 29 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3014,6 +3443,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 30 ---------- Thread #x was created @@ -3036,6 +3468,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:348) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 31 ---------- Thread #x was created @@ -3058,6 +3493,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 31 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3069,6 +3507,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 32 ---------- Thread #x was created @@ -3091,6 +3532,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:352) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 33 ---------- Thread #x was created @@ -3113,6 +3557,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 33 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3124,6 +3571,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 34 ---------- Thread #x was created @@ -3146,6 +3596,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:356) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 35 ---------- Thread #x was created @@ -3168,6 +3621,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 35 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3179,6 +3635,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 36 ---------- Thread #x was created @@ -3201,6 +3660,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:360) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 37 ---------- Thread #x was created @@ -3223,6 +3685,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 37 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3234,6 +3699,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 38 ---------- Thread #x was created @@ -3256,6 +3724,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:364) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 39 ---------- Thread #x was created @@ -3278,6 +3749,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 39 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3289,6 +3763,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 40 ---------- Thread #x was created @@ -3311,6 +3788,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:368) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 41 ---------- Thread #x was created @@ -3333,6 +3813,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 41 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3344,6 +3827,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 42 ---------- Thread #x was created @@ -3366,6 +3852,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:372) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 43 ---------- Thread #x was created @@ -3388,6 +3877,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 43 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3399,6 +3891,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 44 ---------- Thread #x was created @@ -3421,6 +3916,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:376) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 45 ---------- Thread #x was created @@ -3443,6 +3941,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 45 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3454,6 +3955,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 46 ---------- Thread #x was created @@ -3476,6 +3980,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:380) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 47 ---------- Thread #x was created @@ -3498,6 +4005,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 47 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3509,6 +4019,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 48 ---------- Thread #x was created @@ -3531,6 +4044,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:384) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 49 ---------- Thread #x was created @@ -3553,6 +4069,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 49 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3564,6 +4083,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 50 ---------- Thread #x was created @@ -3586,6 +4108,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:388) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 51 ---------- Thread #x was created @@ -3608,6 +4133,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 51 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3619,6 +4147,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 52 ---------- Thread #x was created @@ -3641,6 +4172,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:392) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 53 ---------- Thread #x was created @@ -3663,6 +4197,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 53 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3674,6 +4211,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 54 ---------- Thread #x was created @@ -3696,6 +4236,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:396) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 55 ---------- Thread #x was created @@ -3718,6 +4261,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 55 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3729,6 +4275,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 56 ---------- Thread #x was created @@ -3751,6 +4300,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:400) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 57 ---------- Thread #x was created @@ -3773,6 +4325,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 57 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3784,6 +4339,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 58 ---------- Thread #x was created @@ -3806,6 +4364,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:404) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 59 ---------- Thread #x was created @@ -3828,6 +4389,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 59 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3839,6 +4403,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 60 ---------- Thread #x was created @@ -3861,6 +4428,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:408) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 61 ---------- Thread #x was created @@ -3883,6 +4453,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 61 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3894,6 +4467,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 62 ---------- Thread #x was created @@ -3916,6 +4492,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:412) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 63 ---------- Thread #x was created @@ -3938,6 +4517,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 63 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -3949,6 +4531,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 64 ---------- Thread #x was created @@ -3971,6 +4556,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:416) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 65 ---------- Thread #x was created @@ -3993,6 +4581,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 65 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4004,6 +4595,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 66 ---------- Thread #x was created @@ -4026,6 +4620,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:420) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 67 ---------- Thread #x was created @@ -4048,6 +4645,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 67 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4059,6 +4659,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 68 ---------- Thread #x was created @@ -4081,6 +4684,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:424) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 69 ---------- Thread #x was created @@ -4103,6 +4709,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 69 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4114,6 +4723,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 70 ---------- Thread #x was created @@ -4136,6 +4748,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:428) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 71 ---------- Thread #x was created @@ -4158,6 +4773,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 71 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4169,6 +4787,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 72 ---------- Thread #x was created @@ -4191,6 +4812,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:432) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 73 ---------- Thread #x was created @@ -4213,6 +4837,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 73 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4224,6 +4851,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 74 ---------- Thread #x was created @@ -4246,6 +4876,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:436) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 75 ---------- Thread #x was created @@ -4268,6 +4901,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 75 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4279,6 +4915,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 76 ---------- Thread #x was created @@ -4301,6 +4940,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:440) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 77 ---------- Thread #x was created @@ -4323,6 +4965,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 77 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4334,6 +4979,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 78 ---------- Thread #x was created @@ -4356,6 +5004,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:444) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 79 ---------- Thread #x was created @@ -4378,6 +5029,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 79 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4389,6 +5043,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 80 ---------- Thread #x was created @@ -4411,6 +5068,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:448) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 81 ---------- Thread #x was created @@ -4433,6 +5093,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 81 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4444,6 +5107,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 82 ---------- Thread #x was created @@ -4466,6 +5132,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:452) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 83 ---------- Thread #x was created @@ -4488,6 +5157,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 83 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4499,6 +5171,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 84 ---------- Thread #x was created @@ -4521,6 +5196,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:456) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 85 ---------- Thread #x was created @@ -4543,6 +5221,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 85 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4554,6 +5235,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 86 ---------- Thread #x was created @@ -4576,6 +5260,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:460) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 87 ---------- Thread #x was created @@ -4598,6 +5285,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 87 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4609,6 +5299,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 88 ---------- Thread #x was created @@ -4631,6 +5324,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:464) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 89 ---------- Thread #x was created @@ -4653,6 +5349,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 89 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4664,6 +5363,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 90 ---------- Thread #x was created @@ -4686,6 +5388,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:468) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 91 ---------- Thread #x was created @@ -4708,6 +5413,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 91 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4719,6 +5427,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 92 ---------- Thread #x was created @@ -4741,6 +5452,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:472) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 93 ---------- Thread #x was created @@ -4763,6 +5477,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:474) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 93 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4774,6 +5491,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:474) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 94 ---------- Thread #x was created @@ -4796,6 +5516,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:476) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 95 ---------- Thread #x was created @@ -4818,6 +5541,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:478) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 95 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4829,6 +5555,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:478) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 0 .. 98, skip 96 ---------- Thread #x was created @@ -4851,6 +5580,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:480) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- short gran, 1 .. 98, skip 97 ---------- Thread #x was created @@ -4873,6 +5605,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:482) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 97 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child16 (tc19_shadowmem.c:57) @@ -4884,6 +5619,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:482) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 98 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ========================================================== @@ -4911,6 +5649,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:288) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 0 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 1 ---------- Thread #x was created @@ -4933,6 +5674,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 1 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -4944,6 +5688,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 2 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -4955,6 +5702,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 3 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -4966,6 +5716,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 2 ---------- Thread #x was created @@ -4988,6 +5741,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:292) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 2 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -4999,6 +5755,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:292) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 3 ---------- Thread #x was created @@ -5021,6 +5780,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 3 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5032,6 +5794,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5043,6 +5808,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 5 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5054,6 +5822,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 4 ---------- Thread #x was created @@ -5076,6 +5847,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:296) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 5 ---------- Thread #x was created @@ -5098,6 +5872,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 5 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5109,6 +5886,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5120,6 +5900,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 7 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5131,6 +5914,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 6 ---------- Thread #x was created @@ -5153,6 +5939,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:300) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5164,6 +5953,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:300) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 7 ---------- Thread #x was created @@ -5186,6 +5978,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 7 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5197,6 +5992,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5208,6 +6006,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 9 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5219,6 +6020,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 8 ---------- Thread #x was created @@ -5241,6 +6045,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:304) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 9 ---------- Thread #x was created @@ -5263,6 +6070,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 9 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5274,6 +6084,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5285,6 +6098,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 11 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5296,6 +6112,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 10 ---------- Thread #x was created @@ -5318,6 +6137,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:308) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5329,6 +6151,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:308) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 11 ---------- Thread #x was created @@ -5351,6 +6176,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 11 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5362,6 +6190,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5373,6 +6204,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 13 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5384,6 +6218,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 12 ---------- Thread #x was created @@ -5406,6 +6243,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:312) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 13 ---------- Thread #x was created @@ -5428,6 +6268,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 13 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5439,6 +6282,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5450,6 +6296,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 15 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5461,6 +6310,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 14 ---------- Thread #x was created @@ -5483,6 +6335,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:316) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5494,6 +6349,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:316) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 15 ---------- Thread #x was created @@ -5516,6 +6374,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 15 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5527,6 +6388,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5538,6 +6402,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 17 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5549,6 +6416,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 16 ---------- Thread #x was created @@ -5571,6 +6441,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:320) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 17 ---------- Thread #x was created @@ -5593,6 +6466,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 17 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5604,6 +6480,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5615,6 +6494,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 19 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5626,6 +6508,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 18 ---------- Thread #x was created @@ -5648,6 +6533,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:324) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5659,6 +6547,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:324) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 19 ---------- Thread #x was created @@ -5681,6 +6572,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 19 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5692,6 +6586,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5703,6 +6600,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 21 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5714,6 +6614,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 20 ---------- Thread #x was created @@ -5736,6 +6639,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:328) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 21 ---------- Thread #x was created @@ -5758,6 +6664,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 21 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5769,6 +6678,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5780,6 +6692,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 23 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5791,6 +6706,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 22 ---------- Thread #x was created @@ -5813,6 +6731,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:332) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5824,6 +6745,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:332) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 23 ---------- Thread #x was created @@ -5846,6 +6770,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 23 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5857,6 +6784,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5868,6 +6798,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 25 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5879,6 +6812,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 24 ---------- Thread #x was created @@ -5901,6 +6837,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:336) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 25 ---------- Thread #x was created @@ -5923,6 +6862,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 25 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5934,6 +6876,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5945,6 +6890,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 27 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5956,6 +6904,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 26 ---------- Thread #x was created @@ -5978,6 +6929,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:340) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -5989,6 +6943,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:340) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 27 ---------- Thread #x was created @@ -6011,6 +6968,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 27 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6022,6 +6982,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6033,6 +6996,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 29 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6044,6 +7010,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 28 ---------- Thread #x was created @@ -6066,6 +7035,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:344) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 29 ---------- Thread #x was created @@ -6088,6 +7060,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 29 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6099,6 +7074,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6110,6 +7088,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 31 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6121,6 +7102,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 30 ---------- Thread #x was created @@ -6143,6 +7127,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:348) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6154,6 +7141,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:348) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 31 ---------- Thread #x was created @@ -6176,6 +7166,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 31 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6187,6 +7180,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6198,6 +7194,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 33 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6209,6 +7208,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 32 ---------- Thread #x was created @@ -6231,6 +7233,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:352) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 33 ---------- Thread #x was created @@ -6253,6 +7258,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 33 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6264,6 +7272,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6275,6 +7286,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 35 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6286,6 +7300,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 34 ---------- Thread #x was created @@ -6308,6 +7325,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:356) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6319,6 +7339,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:356) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 35 ---------- Thread #x was created @@ -6341,6 +7364,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 35 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6352,6 +7378,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6363,6 +7392,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 37 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6374,6 +7406,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 36 ---------- Thread #x was created @@ -6396,6 +7431,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:360) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 37 ---------- Thread #x was created @@ -6418,6 +7456,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 37 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6429,6 +7470,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6440,6 +7484,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 39 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6451,6 +7498,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 38 ---------- Thread #x was created @@ -6473,6 +7523,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:364) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6484,6 +7537,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:364) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 39 ---------- Thread #x was created @@ -6506,6 +7562,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 39 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6517,6 +7576,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6528,6 +7590,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 41 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6539,6 +7604,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 40 ---------- Thread #x was created @@ -6561,6 +7629,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:368) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 41 ---------- Thread #x was created @@ -6583,6 +7654,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 41 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6594,6 +7668,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6605,6 +7682,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 43 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6616,6 +7696,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 42 ---------- Thread #x was created @@ -6638,6 +7721,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:372) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6649,6 +7735,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:372) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 43 ---------- Thread #x was created @@ -6671,6 +7760,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 43 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6682,6 +7774,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6693,6 +7788,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 45 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6704,6 +7802,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 44 ---------- Thread #x was created @@ -6726,6 +7827,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:376) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 45 ---------- Thread #x was created @@ -6748,6 +7852,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 45 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6759,6 +7866,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6770,6 +7880,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 47 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6781,6 +7894,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 46 ---------- Thread #x was created @@ -6803,6 +7919,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:380) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6814,6 +7933,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:380) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 47 ---------- Thread #x was created @@ -6836,6 +7958,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 47 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6847,6 +7972,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6858,6 +7986,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 49 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6869,6 +8000,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 48 ---------- Thread #x was created @@ -6891,6 +8025,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:384) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 49 ---------- Thread #x was created @@ -6913,6 +8050,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 49 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6924,6 +8064,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6935,6 +8078,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 51 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6946,6 +8092,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 50 ---------- Thread #x was created @@ -6968,6 +8117,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:388) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -6979,6 +8131,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:388) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 51 ---------- Thread #x was created @@ -7001,6 +8156,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 51 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7012,6 +8170,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7023,6 +8184,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 53 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7034,6 +8198,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 52 ---------- Thread #x was created @@ -7056,6 +8223,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:392) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 53 ---------- Thread #x was created @@ -7078,6 +8248,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 53 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7089,6 +8262,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7100,6 +8276,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 55 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7111,6 +8290,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 54 ---------- Thread #x was created @@ -7133,6 +8315,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:396) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7144,6 +8329,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:396) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 55 ---------- Thread #x was created @@ -7166,6 +8354,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 55 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7177,6 +8368,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7188,6 +8382,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 57 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7199,6 +8396,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 56 ---------- Thread #x was created @@ -7221,6 +8421,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:400) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 57 ---------- Thread #x was created @@ -7243,6 +8446,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 57 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7254,6 +8460,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7265,6 +8474,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 59 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7276,6 +8488,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 58 ---------- Thread #x was created @@ -7298,6 +8513,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:404) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7309,6 +8527,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:404) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 59 ---------- Thread #x was created @@ -7331,6 +8552,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 59 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7342,6 +8566,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7353,6 +8580,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 61 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7364,6 +8594,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 60 ---------- Thread #x was created @@ -7386,6 +8619,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:408) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 61 ---------- Thread #x was created @@ -7408,6 +8644,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 61 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7419,6 +8658,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7430,6 +8672,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 63 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7441,6 +8686,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 62 ---------- Thread #x was created @@ -7463,6 +8711,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:412) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7474,6 +8725,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:412) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 63 ---------- Thread #x was created @@ -7496,6 +8750,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 63 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7507,6 +8764,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7518,6 +8778,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 65 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7529,6 +8792,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 64 ---------- Thread #x was created @@ -7551,6 +8817,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:416) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 65 ---------- Thread #x was created @@ -7573,6 +8842,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 65 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7584,6 +8856,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7595,6 +8870,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 67 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7606,6 +8884,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 66 ---------- Thread #x was created @@ -7628,6 +8909,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:420) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7639,6 +8923,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:420) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 67 ---------- Thread #x was created @@ -7661,6 +8948,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 67 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7672,6 +8962,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7683,6 +8976,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 69 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7694,6 +8990,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 68 ---------- Thread #x was created @@ -7716,6 +9015,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:424) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 69 ---------- Thread #x was created @@ -7738,6 +9040,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 69 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7749,6 +9054,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7760,6 +9068,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 71 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7771,6 +9082,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 70 ---------- Thread #x was created @@ -7793,6 +9107,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:428) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7804,6 +9121,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:428) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 71 ---------- Thread #x was created @@ -7826,6 +9146,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 71 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7837,6 +9160,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7848,6 +9174,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 73 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7859,6 +9188,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 72 ---------- Thread #x was created @@ -7881,6 +9213,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:432) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 73 ---------- Thread #x was created @@ -7903,6 +9238,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 73 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7914,6 +9252,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7925,6 +9266,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 75 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7936,6 +9280,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 74 ---------- Thread #x was created @@ -7958,6 +9305,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:436) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -7969,6 +9319,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:436) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 75 ---------- Thread #x was created @@ -7991,6 +9344,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 75 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8002,6 +9358,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8013,6 +9372,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 77 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8024,6 +9386,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 76 ---------- Thread #x was created @@ -8046,6 +9411,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:440) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 77 ---------- Thread #x was created @@ -8068,6 +9436,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 77 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8079,6 +9450,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8090,6 +9464,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 79 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8101,6 +9478,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 78 ---------- Thread #x was created @@ -8123,6 +9503,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:444) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8134,6 +9517,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:444) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 79 ---------- Thread #x was created @@ -8156,6 +9542,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 79 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8167,6 +9556,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8178,6 +9570,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 81 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8189,6 +9584,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 80 ---------- Thread #x was created @@ -8211,6 +9609,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:448) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 81 ---------- Thread #x was created @@ -8233,6 +9634,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 81 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8244,6 +9648,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8255,6 +9662,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 83 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8266,6 +9676,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 82 ---------- Thread #x was created @@ -8288,6 +9701,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:452) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8299,6 +9715,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:452) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 83 ---------- Thread #x was created @@ -8321,6 +9740,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 83 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8332,6 +9754,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8343,6 +9768,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 85 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8354,6 +9782,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 84 ---------- Thread #x was created @@ -8376,6 +9807,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:456) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 85 ---------- Thread #x was created @@ -8398,6 +9832,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 85 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8409,6 +9846,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8420,6 +9860,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 87 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8431,6 +9874,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 86 ---------- Thread #x was created @@ -8453,6 +9899,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:460) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8464,6 +9913,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:460) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 87 ---------- Thread #x was created @@ -8486,6 +9938,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 87 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8497,6 +9952,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8508,6 +9966,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 89 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8519,6 +9980,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 88 ---------- Thread #x was created @@ -8541,6 +10005,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:464) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 89 ---------- Thread #x was created @@ -8563,6 +10030,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 89 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8574,6 +10044,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8585,6 +10058,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 91 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8596,6 +10072,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 90 ---------- Thread #x was created @@ -8618,6 +10097,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:468) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8629,6 +10111,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:468) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 91 ---------- Thread #x was created @@ -8651,6 +10136,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 91 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8662,6 +10150,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8673,6 +10164,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 93 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8684,6 +10178,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 0 .. 96, skip 92 ---------- Thread #x was created @@ -8706,6 +10203,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:472) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 1 .. 96, skip 93 ---------- Thread #x was created @@ -8728,6 +10228,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:474) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 93 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8739,6 +10242,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:474) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8750,6 +10256,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:474) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 95 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8761,6 +10270,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:474) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 2 .. 96, skip 94 ---------- Thread #x was created @@ -8783,6 +10295,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:476) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8794,6 +10309,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:476) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- int gran, 3 .. 96, skip 95 ---------- Thread #x was created @@ -8816,6 +10334,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:478) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 95 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8827,6 +10348,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:478) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8838,6 +10362,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:478) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 97 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child32 (tc19_shadowmem.c:81) @@ -8849,6 +10376,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:478) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 98 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ========================================================== @@ -8876,6 +10406,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:288) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 0 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 1 ---------- Thread #x was created @@ -8898,6 +10431,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 1 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -8909,6 +10445,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 2 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -8920,6 +10459,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 3 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -8931,6 +10473,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -8942,6 +10487,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 5 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -8953,6 +10501,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -8964,6 +10515,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 7 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -8975,6 +10529,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:290) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 2 ---------- Thread #x was created @@ -8997,6 +10554,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:292) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 2 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9008,6 +10568,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:292) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9019,6 +10582,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:292) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9030,6 +10596,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:292) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 3 ---------- Thread #x was created @@ -9052,6 +10621,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 3 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9063,6 +10635,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9074,6 +10649,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 5 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9085,6 +10663,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9096,6 +10677,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 7 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9107,6 +10691,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9118,6 +10705,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 9 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9129,6 +10719,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:294) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 4 ---------- Thread #x was created @@ -9151,6 +10744,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:296) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 4 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9162,6 +10758,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:296) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 5 ---------- Thread #x was created @@ -9184,6 +10783,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 5 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9195,6 +10797,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9206,6 +10811,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 7 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9217,6 +10825,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9228,6 +10839,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 9 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9239,6 +10853,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9250,6 +10867,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 11 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9261,6 +10881,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:298) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 6 ---------- Thread #x was created @@ -9283,6 +10906,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:300) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 6 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9294,6 +10920,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:300) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9305,6 +10934,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:300) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9316,6 +10948,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:300) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 7 ---------- Thread #x was created @@ -9338,6 +10973,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 7 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9349,6 +10987,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9360,6 +11001,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 9 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9371,6 +11015,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9382,6 +11029,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 11 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9393,6 +11043,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9404,6 +11057,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 13 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9415,6 +11071,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:302) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 8 ---------- Thread #x was created @@ -9437,6 +11096,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:304) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 8 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 9 ---------- Thread #x was created @@ -9459,6 +11121,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 9 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9470,6 +11135,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9481,6 +11149,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 11 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9492,6 +11163,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9503,6 +11177,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 13 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9514,6 +11191,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9525,6 +11205,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 15 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9536,6 +11219,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:306) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 10 ---------- Thread #x was created @@ -9558,6 +11244,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:308) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 10 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9569,6 +11258,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:308) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9580,6 +11272,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:308) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9591,6 +11286,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:308) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 11 ---------- Thread #x was created @@ -9613,6 +11311,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 11 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9624,6 +11325,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9635,6 +11339,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 13 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9646,6 +11353,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9657,6 +11367,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 15 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9668,6 +11381,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9679,6 +11395,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 17 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9690,6 +11409,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:310) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 12 ---------- Thread #x was created @@ -9712,6 +11434,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:312) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 12 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9723,6 +11448,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:312) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 13 ---------- Thread #x was created @@ -9745,6 +11473,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 13 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9756,6 +11487,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9767,6 +11501,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 15 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9778,6 +11515,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9789,6 +11529,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 17 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9800,6 +11543,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9811,6 +11557,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 19 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9822,6 +11571,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:314) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 14 ---------- Thread #x was created @@ -9844,6 +11596,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:316) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 14 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9855,6 +11610,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:316) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9866,6 +11624,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:316) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9877,6 +11638,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:316) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 15 ---------- Thread #x was created @@ -9899,6 +11663,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 15 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9910,6 +11677,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9921,6 +11691,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 17 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9932,6 +11705,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9943,6 +11719,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 19 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9954,6 +11733,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9965,6 +11747,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 21 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -9976,6 +11761,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:318) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 16 ---------- Thread #x was created @@ -9998,6 +11786,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:320) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 16 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 17 ---------- Thread #x was created @@ -10020,6 +11811,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 17 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10031,6 +11825,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10042,6 +11839,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 19 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10053,6 +11853,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10064,6 +11867,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 21 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10075,6 +11881,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10086,6 +11895,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 23 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10097,6 +11909,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:322) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 18 ---------- Thread #x was created @@ -10119,6 +11934,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:324) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 18 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10130,6 +11948,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:324) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10141,6 +11962,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:324) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10152,6 +11976,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:324) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 19 ---------- Thread #x was created @@ -10174,6 +12001,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 19 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10185,6 +12015,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10196,6 +12029,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 21 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10207,6 +12043,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10218,6 +12057,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 23 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10229,6 +12071,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10240,6 +12085,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 25 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10251,6 +12099,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:326) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 20 ---------- Thread #x was created @@ -10273,6 +12124,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:328) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 20 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10284,6 +12138,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:328) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 21 ---------- Thread #x was created @@ -10306,6 +12163,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 21 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10317,6 +12177,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10328,6 +12191,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 23 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10339,6 +12205,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10350,6 +12219,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 25 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10361,6 +12233,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10372,6 +12247,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 27 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10383,6 +12261,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:330) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 22 ---------- Thread #x was created @@ -10405,6 +12286,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:332) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 22 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10416,6 +12300,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:332) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10427,6 +12314,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:332) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10438,6 +12328,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:332) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 23 ---------- Thread #x was created @@ -10460,6 +12353,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 23 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10471,6 +12367,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10482,6 +12381,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 25 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10493,6 +12395,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10504,6 +12409,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 27 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10515,6 +12423,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10526,6 +12437,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 29 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10537,6 +12451,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:334) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 24 ---------- Thread #x was created @@ -10559,6 +12476,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:336) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 24 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 25 ---------- Thread #x was created @@ -10581,6 +12501,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 25 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10592,6 +12515,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10603,6 +12529,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 27 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10614,6 +12543,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10625,6 +12557,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 29 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10636,6 +12571,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10647,6 +12585,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 31 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10658,6 +12599,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:338) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 26 ---------- Thread #x was created @@ -10680,6 +12624,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:340) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 26 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10691,6 +12638,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:340) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10702,6 +12652,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:340) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10713,6 +12666,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:340) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 27 ---------- Thread #x was created @@ -10735,6 +12691,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 27 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10746,6 +12705,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10757,6 +12719,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 29 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10768,6 +12733,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10779,6 +12747,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 31 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10790,6 +12761,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10801,6 +12775,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 33 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10812,6 +12789,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:342) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 28 ---------- Thread #x was created @@ -10834,6 +12814,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:344) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 28 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10845,6 +12828,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:344) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 29 ---------- Thread #x was created @@ -10867,6 +12853,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 29 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10878,6 +12867,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10889,6 +12881,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 31 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10900,6 +12895,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10911,6 +12909,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 33 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10922,6 +12923,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10933,6 +12937,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 35 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10944,6 +12951,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:346) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 30 ---------- Thread #x was created @@ -10966,6 +12976,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:348) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 30 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10977,6 +12990,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:348) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10988,6 +13004,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:348) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -10999,6 +13018,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:348) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 31 ---------- Thread #x was created @@ -11021,6 +13043,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 31 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11032,6 +13057,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11043,6 +13071,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 33 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11054,6 +13085,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11065,6 +13099,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 35 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11076,6 +13113,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11087,6 +13127,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 37 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11098,6 +13141,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:350) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 32 ---------- Thread #x was created @@ -11120,6 +13166,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:352) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 32 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 33 ---------- Thread #x was created @@ -11142,6 +13191,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 33 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11153,6 +13205,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11164,6 +13219,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 35 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11175,6 +13233,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11186,6 +13247,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 37 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11197,6 +13261,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11208,6 +13275,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 39 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11219,6 +13289,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:354) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 34 ---------- Thread #x was created @@ -11241,6 +13314,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:356) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 34 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11252,6 +13328,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:356) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11263,6 +13342,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:356) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11274,6 +13356,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:356) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 35 ---------- Thread #x was created @@ -11296,6 +13381,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 35 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11307,6 +13395,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11318,6 +13409,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 37 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11329,6 +13423,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11340,6 +13437,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 39 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11351,6 +13451,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11362,6 +13465,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 41 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11373,6 +13479,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:358) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 36 ---------- Thread #x was created @@ -11395,6 +13504,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:360) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 36 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11406,6 +13518,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:360) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 37 ---------- Thread #x was created @@ -11428,6 +13543,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 37 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11439,6 +13557,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11450,6 +13571,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 39 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11461,6 +13585,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11472,6 +13599,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 41 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11483,6 +13613,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11494,6 +13627,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 43 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11505,6 +13641,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:362) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 38 ---------- Thread #x was created @@ -11527,6 +13666,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:364) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 38 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11538,6 +13680,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:364) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11549,6 +13694,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:364) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11560,6 +13708,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:364) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 39 ---------- Thread #x was created @@ -11582,6 +13733,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 39 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11593,6 +13747,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11604,6 +13761,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 41 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11615,6 +13775,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11626,6 +13789,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 43 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11637,6 +13803,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11648,6 +13817,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 45 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11659,6 +13831,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:366) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 40 ---------- Thread #x was created @@ -11681,6 +13856,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:368) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 40 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 41 ---------- Thread #x was created @@ -11703,6 +13881,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 41 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11714,6 +13895,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11725,6 +13909,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 43 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11736,6 +13923,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11747,6 +13937,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 45 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11758,6 +13951,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11769,6 +13965,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 47 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11780,6 +13979,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:370) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 42 ---------- Thread #x was created @@ -11802,6 +14004,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:372) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 42 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11813,6 +14018,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:372) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11824,6 +14032,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:372) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11835,6 +14046,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:372) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 43 ---------- Thread #x was created @@ -11857,6 +14071,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 43 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11868,6 +14085,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11879,6 +14099,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 45 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11890,6 +14113,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11901,6 +14127,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 47 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11912,6 +14141,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11923,6 +14155,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 49 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11934,6 +14169,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:374) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 44 ---------- Thread #x was created @@ -11956,6 +14194,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:376) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 44 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -11967,6 +14208,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:376) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 45 ---------- Thread #x was created @@ -11989,6 +14233,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 45 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12000,6 +14247,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12011,6 +14261,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 47 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12022,6 +14275,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12033,6 +14289,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 49 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12044,6 +14303,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12055,6 +14317,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 51 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12066,6 +14331,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:378) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 46 ---------- Thread #x was created @@ -12088,6 +14356,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:380) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 46 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12099,6 +14370,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:380) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12110,6 +14384,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:380) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12121,6 +14398,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:380) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 47 ---------- Thread #x was created @@ -12143,6 +14423,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 47 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12154,6 +14437,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12165,6 +14451,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 49 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12176,6 +14465,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12187,6 +14479,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 51 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12198,6 +14493,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12209,6 +14507,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 53 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12220,6 +14521,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:382) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 48 ---------- Thread #x was created @@ -12242,6 +14546,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:384) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 48 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 49 ---------- Thread #x was created @@ -12264,6 +14571,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 49 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12275,6 +14585,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12286,6 +14599,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 51 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12297,6 +14613,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12308,6 +14627,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 53 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12319,6 +14641,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12330,6 +14655,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 55 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12341,6 +14669,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:386) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 50 ---------- Thread #x was created @@ -12363,6 +14694,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:388) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 50 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12374,6 +14708,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:388) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12385,6 +14722,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:388) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12396,6 +14736,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:388) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 51 ---------- Thread #x was created @@ -12418,6 +14761,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 51 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12429,6 +14775,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12440,6 +14789,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 53 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12451,6 +14803,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12462,6 +14817,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 55 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12473,6 +14831,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12484,6 +14845,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 57 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12495,6 +14859,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:390) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 52 ---------- Thread #x was created @@ -12517,6 +14884,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:392) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 52 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12528,6 +14898,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:392) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 53 ---------- Thread #x was created @@ -12550,6 +14923,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 53 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12561,6 +14937,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12572,6 +14951,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 55 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12583,6 +14965,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12594,6 +14979,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 57 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12605,6 +14993,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12616,6 +15007,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 59 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12627,6 +15021,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:394) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 54 ---------- Thread #x was created @@ -12649,6 +15046,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:396) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 54 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12660,6 +15060,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:396) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12671,6 +15074,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:396) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12682,6 +15088,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:396) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 55 ---------- Thread #x was created @@ -12704,6 +15113,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 55 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12715,6 +15127,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12726,6 +15141,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 57 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12737,6 +15155,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12748,6 +15169,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 59 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12759,6 +15183,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12770,6 +15197,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 61 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12781,6 +15211,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:398) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 56 ---------- Thread #x was created @@ -12803,6 +15236,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:400) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 56 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 57 ---------- Thread #x was created @@ -12825,6 +15261,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 57 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12836,6 +15275,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12847,6 +15289,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 59 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12858,6 +15303,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12869,6 +15317,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 61 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12880,6 +15331,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12891,6 +15345,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 63 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12902,6 +15359,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:402) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 58 ---------- Thread #x was created @@ -12924,6 +15384,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:404) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 58 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12935,6 +15398,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:404) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12946,6 +15412,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:404) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12957,6 +15426,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:404) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 59 ---------- Thread #x was created @@ -12979,6 +15451,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 59 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -12990,6 +15465,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13001,6 +15479,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 61 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13012,6 +15493,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13023,6 +15507,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 63 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13034,6 +15521,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13045,6 +15535,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 65 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13056,6 +15549,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:406) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 60 ---------- Thread #x was created @@ -13078,6 +15574,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:408) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 60 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13089,6 +15588,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:408) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 61 ---------- Thread #x was created @@ -13111,6 +15613,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 61 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13122,6 +15627,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13133,6 +15641,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 63 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13144,6 +15655,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13155,6 +15669,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 65 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13166,6 +15683,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13177,6 +15697,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 67 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13188,6 +15711,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:410) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 62 ---------- Thread #x was created @@ -13210,6 +15736,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:412) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 62 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13221,6 +15750,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:412) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13232,6 +15764,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:412) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13243,6 +15778,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:412) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 63 ---------- Thread #x was created @@ -13265,6 +15803,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 63 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13276,6 +15817,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13287,6 +15831,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 65 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13298,6 +15845,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13309,6 +15859,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 67 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13320,6 +15873,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13331,6 +15887,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 69 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13342,6 +15901,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:414) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 64 ---------- Thread #x was created @@ -13364,6 +15926,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:416) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 64 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 65 ---------- Thread #x was created @@ -13386,6 +15951,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 65 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13397,6 +15965,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13408,6 +15979,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 67 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13419,6 +15993,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13430,6 +16007,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 69 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13441,6 +16021,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13452,6 +16035,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 71 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13463,6 +16049,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:418) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 66 ---------- Thread #x was created @@ -13485,6 +16074,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:420) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 66 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13496,6 +16088,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:420) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13507,6 +16102,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:420) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13518,6 +16116,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:420) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 67 ---------- Thread #x was created @@ -13540,6 +16141,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 67 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13551,6 +16155,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13562,6 +16169,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 69 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13573,6 +16183,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13584,6 +16197,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 71 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13595,6 +16211,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13606,6 +16225,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 73 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13617,6 +16239,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:422) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 68 ---------- Thread #x was created @@ -13639,6 +16264,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:424) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 68 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13650,6 +16278,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:424) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 69 ---------- Thread #x was created @@ -13672,6 +16303,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 69 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13683,6 +16317,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13694,6 +16331,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 71 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13705,6 +16345,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13716,6 +16359,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 73 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13727,6 +16373,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13738,6 +16387,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 75 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13749,6 +16401,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:426) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 70 ---------- Thread #x was created @@ -13771,6 +16426,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:428) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 70 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13782,6 +16440,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:428) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13793,6 +16454,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:428) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13804,6 +16468,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:428) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 71 ---------- Thread #x was created @@ -13826,6 +16493,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 71 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13837,6 +16507,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13848,6 +16521,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 73 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13859,6 +16535,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13870,6 +16549,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 75 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13881,6 +16563,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13892,6 +16577,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 77 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13903,6 +16591,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:430) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 72 ---------- Thread #x was created @@ -13925,6 +16616,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:432) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 72 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 73 ---------- Thread #x was created @@ -13947,6 +16641,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 73 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13958,6 +16655,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13969,6 +16669,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 75 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13980,6 +16683,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -13991,6 +16697,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 77 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14002,6 +16711,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14013,6 +16725,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 79 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14024,6 +16739,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:434) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 74 ---------- Thread #x was created @@ -14046,6 +16764,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:436) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 74 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14057,6 +16778,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:436) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14068,6 +16792,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:436) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14079,6 +16806,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:436) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 75 ---------- Thread #x was created @@ -14101,6 +16831,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 75 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14112,6 +16845,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14123,6 +16859,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 77 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14134,6 +16873,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14145,6 +16887,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 79 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14156,6 +16901,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14167,6 +16915,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 81 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14178,6 +16929,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:438) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 76 ---------- Thread #x was created @@ -14200,6 +16954,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:440) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 76 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14211,6 +16968,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:440) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 77 ---------- Thread #x was created @@ -14233,6 +16993,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 77 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14244,6 +17007,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14255,6 +17021,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 79 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14266,6 +17035,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14277,6 +17049,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 81 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14288,6 +17063,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14299,6 +17077,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 83 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14310,6 +17091,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:442) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 78 ---------- Thread #x was created @@ -14332,6 +17116,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:444) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 78 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14343,6 +17130,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:444) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14354,6 +17144,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:444) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14365,6 +17158,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:444) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 79 ---------- Thread #x was created @@ -14387,6 +17183,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 79 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14398,6 +17197,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14409,6 +17211,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 81 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14420,6 +17225,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14431,6 +17239,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 83 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14442,6 +17253,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14453,6 +17267,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 85 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14464,6 +17281,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:446) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 80 ---------- Thread #x was created @@ -14486,6 +17306,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:448) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 80 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 81 ---------- Thread #x was created @@ -14508,6 +17331,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 81 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14519,6 +17345,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14530,6 +17359,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 83 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14541,6 +17373,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14552,6 +17387,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 85 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14563,6 +17401,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14574,6 +17415,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 87 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14585,6 +17429,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:450) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 82 ---------- Thread #x was created @@ -14607,6 +17454,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:452) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 82 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14618,6 +17468,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:452) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14629,6 +17482,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:452) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14640,6 +17496,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:452) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 83 ---------- Thread #x was created @@ -14662,6 +17521,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 83 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14673,6 +17535,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14684,6 +17549,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 85 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14695,6 +17563,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14706,6 +17577,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 87 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14717,6 +17591,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14728,6 +17605,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 89 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14739,6 +17619,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:454) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 4 .. 92, skip 84 ---------- Thread #x was created @@ -14761,6 +17644,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:456) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 84 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 4 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14772,6 +17658,9 @@ Possible data race during write of size 4 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:456) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 5 .. 92, skip 85 ---------- Thread #x was created @@ -14794,6 +17683,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 85 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14805,6 +17697,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14816,6 +17711,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 87 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14827,6 +17725,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14838,6 +17739,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 89 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14849,6 +17753,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14860,6 +17767,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 91 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14871,6 +17781,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:458) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 6 .. 92, skip 86 ---------- Thread #x was created @@ -14893,6 +17806,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:460) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 86 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14904,6 +17820,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:460) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14915,6 +17834,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:460) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14926,6 +17848,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:460) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 7 .. 92, skip 87 ---------- Thread #x was created @@ -14948,6 +17873,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 87 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14959,6 +17887,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14970,6 +17901,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 89 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14981,6 +17915,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -14992,6 +17929,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 91 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15003,6 +17943,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15014,6 +17957,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 93 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15025,6 +17971,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:462) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 0 .. 92, skip 88 ---------- Thread #x was created @@ -15047,6 +17996,9 @@ Possible data race during write of size 8 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:464) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 88 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 1 .. 92, skip 89 ---------- Thread #x was created @@ -15069,6 +18021,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 89 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15080,6 +18035,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15091,6 +18049,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 91 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15102,6 +18063,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15113,6 +18077,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 93 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15124,6 +18091,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15135,6 +18105,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 95 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15146,6 +18119,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:466) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 2 .. 92, skip 90 ---------- Thread #x was created @@ -15168,6 +18144,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:468) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 90 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15179,6 +18158,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:468) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15190,6 +18172,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:468) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 2 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15201,6 +18186,9 @@ Possible data race during write of size 2 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:468) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ---------- double gran, 3 .. 92, skip 91 ---------- Thread #x was created @@ -15223,6 +18211,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 91 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15234,6 +18225,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 92 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15245,6 +18239,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 93 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15256,6 +18253,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 94 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15267,6 +18267,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 95 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15278,6 +18281,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 96 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15289,6 +18295,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 97 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) Possible data race during write of size 1 at 0x........ by thread #x at 0x........: child64 (tc19_shadowmem.c:105) @@ -15300,6 +18309,9 @@ Possible data race during write of size 1 at 0x........ by thread #x by 0x........: steer (tc19_shadowmem.c:470) by 0x........: mythread_wrapper (hg_intercepts.c:...) ... + Address 0x........ is 98 bytes inside a block of size 100 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) ERROR SUMMARY: 1004 errors from 1004 contexts (suppressed: 0 from 0) diff --git a/helgrind/tests/tc20_verifywrap.stderr.exp-glibc27-amd64 b/helgrind/tests/tc20_verifywrap.stderr.exp-glibc27-amd64 index ad3758a..cf042ec 100644 --- a/helgrind/tests/tc20_verifywrap.stderr.exp-glibc27-amd64 +++ b/helgrind/tests/tc20_verifywrap.stderr.exp-glibc27-amd64 @@ -71,12 +71,14 @@ Thread #x's call to pthread_mutex_unlock failed ---------------- pthread_cond_wait et al ---------------- Thread #x: pthread_cond_{timed}wait called with un-held mutex - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc20_verifywrap.c:147) Thread #x's call to pthread_cond_wait failed with error code 1 (EPERM: Operation not permitted) - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc20_verifywrap.c:147) @@ -86,12 +88,14 @@ FIXME: can't figure out how to verify wrap of pthread_cond_signal FIXME: can't figure out how to verify wrap of pthread_broadcast_signal Thread #x: pthread_cond_{timed}wait called with un-held mutex - at 0x........: pthread_cond_timedwait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_timedwait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_timedwait@* (hg_intercepts.c:...) by 0x........: main (tc20_verifywrap.c:165) Thread #x's call to pthread_cond_timedwait failed with error code 22 (EINVAL: Invalid argument) - at 0x........: pthread_cond_timedwait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_timedwait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_timedwait@* (hg_intercepts.c:...) by 0x........: main (tc20_verifywrap.c:165) diff --git a/helgrind/tests/tc23_bogus_condwait.stderr.exp b/helgrind/tests/tc23_bogus_condwait.stderr.exp index fbe0238..15f48a5 100644 --- a/helgrind/tests/tc23_bogus_condwait.stderr.exp +++ b/helgrind/tests/tc23_bogus_condwait.stderr.exp @@ -2,31 +2,38 @@ Thread #x is the program's root thread Thread #x: pthread_cond_{timed}wait called with invalid mutex - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc23_bogus_condwait.c:69) Thread #x: pthread_cond_{timed}wait called with un-held mutex - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc23_bogus_condwait.c:72) Thread #x: pthread_cond_{timed}wait: cond is associated with a different mutex - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc23_bogus_condwait.c:72) Thread #x: pthread_cond_{timed}wait called with mutex of type pthread_rwlock_t* - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc23_bogus_condwait.c:75) Thread #x: pthread_cond_{timed}wait: cond is associated with a different mutex - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc23_bogus_condwait.c:75) Thread #x: pthread_cond_{timed}wait called with mutex held by a different thread - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc23_bogus_condwait.c:78) Thread #x: pthread_cond_{timed}wait: cond is associated with a different mutex - at 0x........: pthread_cond_wait@* (hg_intercepts.c:...) + at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) + by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) by 0x........: main (tc23_bogus_condwait.c:78) diff --git a/include/Makefile.am b/include/Makefile.am index f1cd54d..b93ba14 100644 --- a/include/Makefile.am +++ b/include/Makefile.am @@ -40,21 +40,24 @@ nobase_pkginclude_HEADERS = \ vki/vki-linux.h \ vki/vki-freebsd.h \ vki/vki-darwin.h \ - vki/vki-posixtypes-amd64-linux.h\ - vki/vki-posixtypes-ppc32-linux.h\ - vki/vki-posixtypes-ppc64-linux.h\ - vki/vki-posixtypes-x86-linux.h \ + vki/vki-posixtypes-amd64-linux.h \ + vki/vki-posixtypes-ppc32-linux.h \ + vki/vki-posixtypes-ppc64-linux.h \ + vki/vki-posixtypes-x86-linux.h \ + vki/vki-posixtypes-arm-linux.h \ vki/vki-amd64-linux.h \ vki/vki-ppc32-linux.h \ vki/vki-ppc64-linux.h \ vki/vki-x86-linux.h \ vki/vki-amd64-freebsd.h \ vki/vki-x86-freebsd.h \ + vki/vki-arm-linux.h \ vki/vki-scnums-amd64-linux.h \ vki/vki-scnums-ppc32-linux.h \ vki/vki-scnums-ppc64-linux.h \ vki/vki-scnums-x86-linux.h \ vki/vki-scnums-freebsd.h \ + vki/vki-scnums-arm-linux.h \ vki/vki-scnums-darwin.h noinst_HEADERS = \ diff --git a/include/pub_tool_aspacehl.h b/include/pub_tool_aspacehl.h index 6df2376..00f0093 100644 --- a/include/pub_tool_aspacehl.h +++ b/include/pub_tool_aspacehl.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2009-2009 Julian Seward + Copyright (C) 2009-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_aspacemgr.h b/include/pub_tool_aspacemgr.h index f84dfa6..100b632 100644 --- a/include/pub_tool_aspacemgr.h +++ b/include/pub_tool_aspacemgr.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_basics.h b/include/pub_tool_basics.h index 3372b3f..7d98917 100644 --- a/include/pub_tool_basics.h +++ b/include/pub_tool_basics.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -49,9 +49,6 @@ // For varargs types #include -/* For HAVE_BUILTIN_EXPECT */ -#include "config.h" - /* --------------------------------------------------------------------- symbol prefixing @@ -194,16 +191,21 @@ typedef } SysRes; #elif defined(VGO_darwin) +typedef + enum { + SysRes_MACH=40, // MACH, result is _wLO + SysRes_MDEP, // MDEP, result is _wLO + SysRes_UNIX_OK, // UNIX, success, result is _wHI:_wLO + SysRes_UNIX_ERR // UNIX, error, error is _wHI:_wLO + } + SysResMode; typedef struct { UWord _wLO; UWord _wHI; - enum { - SysRes_MACH=40, // MACH, result is _wLO - SysRes_MDEP, // MDEP, result is _wLO - SysRes_UNIX_OK, // UNIX, success, result is _wHI:_wLO - SysRes_UNIX_ERR // UNIX, error, error is _wHI:_wLO - } _mode; + SysResMode _mode; + } + SysRes; #elif defined(VGO_freebsd) typedef struct { @@ -318,7 +320,7 @@ static inline Bool sr_EQ ( SysRes sr1, SysRes sr2 ) { #undef VG_BIGENDIAN #undef VG_LITTLEENDIAN -#if defined(VGA_x86) || defined(VGA_amd64) +#if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) # define VG_LITTLEENDIAN 1 #elif defined(VGA_ppc32) || defined(VGA_ppc64) # define VG_BIGENDIAN 1 @@ -329,7 +331,8 @@ static inline Bool sr_EQ ( SysRes sr1, SysRes sr2 ) { /* Regparmness */ #if defined(VGA_x86) # define VG_REGPARM(n) __attribute__((regparm(n))) -#elif defined(VGA_amd64) || defined(VGA_ppc32) || defined(VGA_ppc64) +#elif defined(VGA_amd64) || defined(VGA_ppc32) \ + || defined(VGA_ppc64) || defined(VGA_arm) # define VG_REGPARM(n) /* */ #else # error Unknown arch @@ -343,7 +346,7 @@ static inline Bool sr_EQ ( SysRes sr1, SysRes sr2 ) { #define VG_BUGS_TO "www.valgrind.org" /* Branch prediction hints. */ -#if HAVE_BUILTIN_EXPECT +#if 1 /*HAVE_BUILTIN_EXPECT*/ # define LIKELY(x) __builtin_expect(!!(x), 1) # define UNLIKELY(x) __builtin_expect((x), 0) #else diff --git a/include/pub_tool_basics_asm.h b/include/pub_tool_basics_asm.h index b1cf2f7..81921f3 100644 --- a/include/pub_tool_basics_asm.h +++ b/include/pub_tool_basics_asm.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_clientstate.h b/include/pub_tool_clientstate.h index 9a47fcc..81df4e5 100644 --- a/include/pub_tool_clientstate.h +++ b/include/pub_tool_clientstate.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -60,7 +60,7 @@ extern Int VG_(args_for_valgrind_noexecpass); /* The name of the client executable, as specified on the command line. */ -extern HChar* VG_(args_the_exename); +extern const HChar* VG_(args_the_exename); #endif // __PUB_TOOL_CLIENTSTATE_H diff --git a/include/pub_tool_clreq.h b/include/pub_tool_clreq.h index f200d12..33ae9bb 100644 --- a/include/pub_tool_clreq.h +++ b/include/pub_tool_clreq.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_cpuid.h b/include/pub_tool_cpuid.h index 9e994c5..51a7b12 100644 --- a/include/pub_tool_cpuid.h +++ b/include/pub_tool_cpuid.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_debuginfo.h b/include/pub_tool_debuginfo.h index a02b790..2259047 100644 --- a/include/pub_tool_debuginfo.h +++ b/include/pub_tool_debuginfo.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -212,7 +212,8 @@ void VG_(DebugInfo_syms_getidx) ( const DebugInfo *di, /*OUT*/Addr* tocptr, /*OUT*/UInt* size, /*OUT*/HChar** name, - /*OUT*/Bool* isText ); + /*OUT*/Bool* isText, + /*OUT*/Bool* isIFunc ); /* A simple enumeration to describe the 'kind' of various kinds of segments that arise from the mapping of object files. */ diff --git a/include/pub_tool_errormgr.h b/include/pub_tool_errormgr.h index a473c6b..42e6b8e 100644 --- a/include/pub_tool_errormgr.h +++ b/include/pub_tool_errormgr.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_execontext.h b/include/pub_tool_execontext.h index 3506026..19c6d75 100644 --- a/include/pub_tool_execontext.h +++ b/include/pub_tool_execontext.h @@ -6,7 +6,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_hashtable.h b/include/pub_tool_hashtable.h index 4c83cf9..50c0844 100644 --- a/include/pub_tool_hashtable.h +++ b/include/pub_tool_hashtable.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_libcassert.h b/include/pub_tool_libcassert.h index 6e4f69a..af92112 100644 --- a/include/pub_tool_libcassert.h +++ b/include/pub_tool_libcassert.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -33,15 +33,17 @@ #define tl_assert(expr) \ ((void) ((expr) ? 0 : \ - (VG_(assert_fail) (/*isCore?*/False, #expr, \ - __FILE__, __LINE__, __PRETTY_FUNCTION__, \ - ""), \ + (VG_(assert_fail) (/*isCore?*/False, (const Char*)#expr, \ + (const Char*)__FILE__, __LINE__, \ + (const Char*)__PRETTY_FUNCTION__, \ + (const HChar*)""), \ 0))) #define tl_assert2(expr, format, args...) \ ((void) ((expr) ? 0 : \ - (VG_(assert_fail) (/*isCore?*/False, #expr, \ - __FILE__, __LINE__, __PRETTY_FUNCTION__, \ + (VG_(assert_fail) (/*isCore?*/False, (const Char*)#expr, \ + (const Char*)__FILE__, __LINE__, \ + (const Char*)__PRETTY_FUNCTION__, \ format, ##args), \ 0))) diff --git a/include/pub_tool_libcbase.h b/include/pub_tool_libcbase.h index 0460112..2897235 100644 --- a/include/pub_tool_libcbase.h +++ b/include/pub_tool_libcbase.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -110,6 +110,36 @@ extern void* VG_(memmove)( void *d, const void *s, SizeT sz ); extern void* VG_(memset) ( void *s, Int c, SizeT sz ); extern Int VG_(memcmp) ( const void* s1, const void* s2, SizeT n ); +/* Zero out up to 8 words quickly in-line. Do not use this for blocks + of size which are unknown at compile time, since the whole point is + for it to be inlined, and then for gcc to remove all code except + for the relevant 'sz' case. */ +inline __attribute__((always_inline)) +static void VG_(bzero_inline) ( void* s, SizeT sz ) +{ + if (LIKELY(0 == (((Addr)sz) & (Addr)(sizeof(UWord)-1))) + && LIKELY(0 == (((Addr)s) & (Addr)(sizeof(UWord)-1)))) { + UWord* p = (UWord*)s; + switch (sz / (SizeT)sizeof(UWord)) { + case 8: p[0] = p[1] = p[2] = p[3] + = p[4] = p[5] = p[6] = p[7] = 0UL; return; + case 7: p[0] = p[1] = p[2] = p[3] + = p[4] = p[5] = p[6] = 0UL; return; + case 6: p[0] = p[1] = p[2] = p[3] + = p[4] = p[5] = 0UL; return; + case 5: p[0] = p[1] = p[2] = p[3] = p[4] = 0UL; return; + case 4: p[0] = p[1] = p[2] = p[3] = 0UL; return; + case 3: p[0] = p[1] = p[2] = 0UL; return; + case 2: p[0] = p[1] = 0UL; return; + case 1: p[0] = 0UL; return; + case 0: return; + default: break; + } + } + VG_(memset)(s, 0, sz); +} + + /* --------------------------------------------------------------------- Address computation helpers ------------------------------------------------------------------ */ diff --git a/include/pub_tool_libcfile.h b/include/pub_tool_libcfile.h index 5e04c96..8f08cd2 100644 --- a/include/pub_tool_libcfile.h +++ b/include/pub_tool_libcfile.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_libcprint.h b/include/pub_tool_libcprint.h index 0e057cb..1621851 100644 --- a/include/pub_tool_libcprint.h +++ b/include/pub_tool_libcprint.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -32,19 +32,9 @@ #define __PUB_TOOL_LIBCPRINT_H /* --------------------------------------------------------------------- - Basic printing + Formatting functions ------------------------------------------------------------------ */ -/* Note that they all output to the file descriptor given by the - --log-fd/--log-file/--log-socket argument, which defaults to 2 - (stderr). Hence no need for VG_(fprintf)(). -*/ -extern UInt VG_(printf) ( const HChar *format, ... ) - PRINTF_CHECK(1, 2); - -extern UInt VG_(vprintf) ( const HChar *format, va_list vargs ) - PRINTF_CHECK(1, 0); - extern UInt VG_(sprintf) ( Char* buf, const HChar* format, ... ) PRINTF_CHECK(2, 3); @@ -59,65 +49,93 @@ extern UInt VG_(vsnprintf)( Char* buf, Int size, const HChar *format, va_list vargs ) PRINTF_CHECK(3, 0); -/* Yet another, totally general, version of vprintf, which hands all - output bytes to CHAR_SINK, passing it OPAQUE as the second arg. */ -extern void VG_(vcbprintf)( void(*char_sink)(HChar, void* opaque), - void* opaque, - const HChar* format, va_list vargs ); - -/* These are the same as the non "_xml" versions above, except the - output goes on the selected XML output channel instead of the - normal one. -*/ -extern UInt VG_(printf_xml) ( const HChar *format, ... ) - PRINTF_CHECK(1, 2); - -extern UInt VG_(vprintf_xml) ( const HChar *format, va_list vargs ) - PRINTF_CHECK(1, 0); - -extern UInt VG_(printf_xml_no_f_c) ( const HChar *format, ... ); - // Percentify n/m with d decimal places. Includes the '%' symbol at the end. // Right justifies in 'buf'. extern void VG_(percentify)(ULong n, ULong m, UInt d, Int n_buf, char buf[]); /* --------------------------------------------------------------------- - Messages for the user + Output-printing functions ------------------------------------------------------------------ */ +// Note that almost all output goes to the file descriptor given by the +// --log-fd/--log-file/--log-socket argument, which defaults to 2 (stderr). +// (Except that some text always goes to stdout/stderr at startup, and +// debugging messages always go to stderr.) Hence no need for +// VG_(fprintf)(). + /* No, really. I _am_ that strange. */ #define OINK(nnn) VG_(message)(Vg_DebugMsg, "OINK %d\n",nnn) -/* Print a message prefixed by "???? "; '?' depends on the VgMsgKind. +/* Print a message with a prefix that depends on the VgMsgKind. Should be used for all user output. */ typedef - enum { Vg_UserMsg, /* '?' == '=' */ - Vg_DebugMsg, /* '?' == '-' */ - Vg_DebugExtraMsg, /* '?' == '+' */ - Vg_ClientMsg /* '?' == '*' */ + enum { // Prefix + Vg_FailMsg, // "valgrind:" + Vg_UserMsg, // "==pid==" + Vg_DebugMsg, // "--pid--" + Vg_ClientMsg // "**pid**" } VgMsgKind; -/* Send a single-part message. The format specification may contain - any ISO C format specifier or %t. No attempt is made to let the - compiler verify consistency of the format string and the argument - list. */ +// These print output that isn't prefixed with anything, and should be +// used in very few cases, such as printing usage messages. +extern UInt VG_(printf) ( const HChar *format, ... ) + PRINTF_CHECK(1, 2); +extern UInt VG_(vprintf) ( const HChar *format, va_list vargs ) + PRINTF_CHECK(1, 0); + +// The "_no_f_c" functions here are just like their non-"_no_f_c" counterparts +// but without the PRINTF_CHECK, so they can be used with our non-standard %t +// format specifier. + +// These are the same as the non "_xml" versions above, except the +// output goes on the selected XML output channel instead of the +// normal one. +extern UInt VG_(printf_xml) ( const HChar *format, ... ) + PRINTF_CHECK(1, 2); + +extern UInt VG_(vprintf_xml) ( const HChar *format, va_list vargs ) + PRINTF_CHECK(1, 0); + +extern UInt VG_(printf_xml_no_f_c) ( const HChar *format, ... ); + +/* Yet another, totally general, version of vprintf, which hands all + output bytes to CHAR_SINK, passing it OPAQUE as the second arg. */ +extern void VG_(vcbprintf)( void(*char_sink)(HChar, void* opaque), + void* opaque, + const HChar* format, va_list vargs ); + extern UInt VG_(message_no_f_c)( VgMsgKind kind, const HChar* format, ... ); -/* Send a single-part message. The format specification may contain - any ISO C format specifier. The gcc compiler will verify - consistency of the format string and the argument list. */ extern UInt VG_(message)( VgMsgKind kind, const HChar* format, ... ) - PRINTF_CHECK(2, 3); + PRINTF_CHECK(2, 3); extern UInt VG_(vmessage)( VgMsgKind kind, const HChar* format, va_list vargs ) - PRINTF_CHECK(2, 0); + PRINTF_CHECK(2, 0); // Short-cuts for VG_(message)(). + +// This is used for messages printed due to start-up failures that occur +// before the preamble is printed, eg. due a bad executable. +extern UInt VG_(fmsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2); + +// This is used if an option was bad for some reason. Note: don't use it just +// because an option was unrecognised -- return 'False' from +// VG_(tdict).tool_process_cmd_line_option) to indicate that -- use it if eg. +// an option was given an inappropriate argument. This function prints an +// error message, then shuts down the entire system. +__attribute__((noreturn)) +extern void VG_(fmsg_bad_option) ( HChar* opt, const HChar* format, ... ) + PRINTF_CHECK(2, 3); + +// This is used for messages that are interesting to the user: info about +// their program (eg. preamble, tool error messages, postamble) or stuff they +// requested. extern UInt VG_(umsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2); + +// This is used for debugging messages that are only of use to developers. extern UInt VG_(dmsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2); -extern UInt VG_(emsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2); /* Flush any output cached by previous calls to VG_(message) et al. */ extern void VG_(message_flush) ( void ); diff --git a/include/pub_tool_libcproc.h b/include/pub_tool_libcproc.h index cd668b1..2770dda 100644 --- a/include/pub_tool_libcproc.h +++ b/include/pub_tool_libcproc.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -44,6 +44,10 @@ extern Char* VG_(getenv) ( Char* name ); /* Path to all our library/aux files */ extern const Char *VG_(libdir); +// The name of the LD_PRELOAD-equivalent variable. It varies across +// platforms. +extern const Char* VG_(LD_PRELOAD_var_name); + /* --------------------------------------------------------------------- Important syscalls ------------------------------------------------------------------ */ diff --git a/include/pub_tool_libcsignal.h b/include/pub_tool_libcsignal.h index d8aa0f5..025c84a 100644 --- a/include/pub_tool_libcsignal.h +++ b/include/pub_tool_libcsignal.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_machine.h b/include/pub_tool_machine.h index 28b90ba..0835369 100644 --- a/include/pub_tool_machine.h +++ b/include/pub_tool_machine.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -37,22 +37,33 @@ # define VG_CLREQ_SZB 14 // length of a client request, may // be larger than VG_MAX_INSTR_SZB # define VG_STACK_REDZONE_SZB 0 // number of addressable bytes below %RSP + #elif defined(VGP_amd64_linux) || defined(VGP_amd64_freebsd) # define VG_MIN_INSTR_SZB 1 # define VG_MAX_INSTR_SZB 16 # define VG_CLREQ_SZB 19 # define VG_STACK_REDZONE_SZB 128 + #elif defined(VGP_ppc32_linux) # define VG_MIN_INSTR_SZB 4 # define VG_MAX_INSTR_SZB 4 # define VG_CLREQ_SZB 20 # define VG_STACK_REDZONE_SZB 0 + #elif defined(VGP_ppc64_linux) # define VG_MIN_INSTR_SZB 4 # define VG_MAX_INSTR_SZB 4 # define VG_CLREQ_SZB 20 # define VG_STACK_REDZONE_SZB 288 // number of addressable bytes below R1 - // from 64-bit PowerPC ELF ABI Supplement 1.7 + // from 64-bit PowerPC ELF ABI + // Supplement 1.7 + +#elif defined(VGP_arm_linux) +# define VG_MIN_INSTR_SZB 2 +# define VG_MAX_INSTR_SZB 4 +# define VG_CLREQ_SZB 20 +# define VG_STACK_REDZONE_SZB 0 + #elif defined(VGP_ppc32_aix5) # define VG_MIN_INSTR_SZB 4 # define VG_MAX_INSTR_SZB 4 @@ -63,34 +74,36 @@ 8-alignment of the area to be messed with. So let's just say 224 instead. Gdb has a similar kludge. */ # define VG_STACK_REDZONE_SZB 224 + #elif defined(VGP_ppc64_aix5) # define VG_MIN_INSTR_SZB 4 # define VG_MAX_INSTR_SZB 4 # define VG_CLREQ_SZB 20 # define VG_STACK_REDZONE_SZB 288 // is this right? + #elif defined(VGP_x86_darwin) # define VG_MIN_INSTR_SZB 1 // min length of native instruction # define VG_MAX_INSTR_SZB 16 // max length of native instruction # define VG_CLREQ_SZB 14 // length of a client request, may // be larger than VG_MAX_INSTR_SZB # define VG_STACK_REDZONE_SZB 0 // number of addressable bytes below %RSP + #elif defined(VGP_amd64_darwin) # define VG_MIN_INSTR_SZB 1 # define VG_MAX_INSTR_SZB 16 # define VG_CLREQ_SZB 19 # define VG_STACK_REDZONE_SZB 128 + #else # error Unknown platform #endif // Guest state accessors -extern Addr VG_(get_SP) ( ThreadId tid ); -extern Addr VG_(get_IP) ( ThreadId tid ); -extern Addr VG_(get_FP) ( ThreadId tid ); -extern Addr VG_(get_LR) ( ThreadId tid ); +// Are mostly in the core_ header. +// Only these two are available to tools. +Addr VG_(get_IP) ( ThreadId tid ); +Addr VG_(get_SP) ( ThreadId tid ); -extern void VG_(set_SP) ( ThreadId tid, Addr sp ); -extern void VG_(set_IP) ( ThreadId tid, Addr ip ); // For get/set, 'area' is where the asked-for guest state will be copied // into/from. If shadowNo == 0, the real (non-shadow) guest state is @@ -133,7 +146,15 @@ extern Bool VG_(thread_stack_next) ( /*MOD*/ThreadId* tid, extern Addr VG_(thread_get_stack_max) ( ThreadId tid ); // Returns how many bytes have been allocated for the stack of the given thread -extern Addr VG_(thread_get_stack_size) ( ThreadId tid ); +extern SizeT VG_(thread_get_stack_size) ( ThreadId tid ); + +// Returns the bottommost address of the alternate signal stack. +// See also the man page of sigaltstack(). +extern Addr VG_(thread_get_altstack_min) ( ThreadId tid ); + +// Returns how many bytes have been allocated for the alternate signal stack. +// See also the man page of sigaltstack(). +extern SizeT VG_(thread_get_altstack_size) ( ThreadId tid ); // Given a pointer to a function as obtained by "& functionname" in C, // produce a pointer to the actual entry point for the function. For diff --git a/include/pub_tool_mallocfree.h b/include/pub_tool_mallocfree.h index fc3649f..694e1f5 100644 --- a/include/pub_tool_mallocfree.h +++ b/include/pub_tool_mallocfree.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_options.h b/include/pub_tool_options.h index f9e1b00..7f85492 100644 --- a/include/pub_tool_options.h +++ b/include/pub_tool_options.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -77,7 +77,7 @@ Long n = VG_(strtoll10)( val, &s ); \ (qq_var) = n; \ /* Check for non-numeralness, or overflow. */ \ - if ('\0' != s[0] || (qq_var) != n) VG_(err_bad_option)(qq_arg); \ + if ('\0' != s[0] || (qq_var) != n) VG_(fmsg_bad_option)(qq_arg, ""); \ True; \ }) \ ) @@ -91,15 +91,16 @@ Char* s; \ Long n = VG_(strtoll##qq_base)( val, &s ); \ (qq_var) = n; \ + /* MMM: separate the two cases, and explain the problem; likewise */ \ + /* for all the other macros in this file. */ \ /* Check for non-numeralness, or overflow. */ \ /* Nb: it will overflow if qq_var is unsigned and qq_val is negative! */ \ - if ('\0' != s[0] || (qq_var) != n) VG_(err_bad_option)(qq_arg); \ + if ('\0' != s[0] || (qq_var) != n) VG_(fmsg_bad_option)(qq_arg, ""); \ /* Check bounds. */ \ if ((qq_var) < (qq_lo) || (qq_var) > (qq_hi)) { \ - VG_(message)(Vg_UserMsg, \ - "'%s' argument must be between %lld and %lld\n", \ - (qq_option), (Long)(qq_lo), (Long)(qq_hi)); \ - VG_(err_bad_option)(qq_arg); \ + VG_(fmsg_bad_option)(qq_arg, \ + "'%s' argument must be between %lld and %lld\n", \ + (qq_option), (Long)(qq_lo), (Long)(qq_hi)); \ } \ True; \ }) \ @@ -124,7 +125,7 @@ double n = VG_(strtod)( val, &s ); \ (qq_var) = n; \ /* Check for non-numeralness */ \ - if ('\0' != s[0]) VG_(err_bad_option)(qq_arg); \ + if ('\0' != s[0]) VG_(fmsg_bad_option)(qq_arg, ""); \ True; \ }) \ ) @@ -165,15 +166,6 @@ extern Int VG_(clo_backtrace_size); extern Bool VG_(clo_show_below_main); -/* Call this if a recognised option was bad for some reason. Note: - don't use it just because an option was unrecognised -- return - 'False' from VG_(tdict).tool_process_cmd_line_option) to indicate that -- - use it if eg. an option was given an inappropriate argument. - This function prints an error message, then shuts down the entire system. - It returns a Bool so it can be used in the _CLO_ macros. */ -__attribute__((noreturn)) -extern void VG_(err_bad_option) ( Char* opt ); - /* Used to expand file names. "option_name" is the option name, eg. "--log-file". 'format' is what follows, eg. "cachegrind.out.%p". In 'format': diff --git a/include/pub_tool_oset.h b/include/pub_tool_oset.h index 2e79448..bc71daa 100644 --- a/include/pub_tool_oset.h +++ b/include/pub_tool_oset.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -77,7 +77,7 @@ typedef struct _OSet OSet; // - Free: frees a chunk of memory allocated with Alloc. typedef Word (*OSetCmp_t) ( const void* key, const void* elem ); -typedef void* (*OSetAlloc_t) ( HChar* ec, SizeT szB ); +typedef void* (*OSetAlloc_t) ( HChar* cc, SizeT szB ); typedef void (*OSetFree_t) ( void* p ); /*--------------------------------------------------------------------*/ @@ -87,6 +87,7 @@ typedef void (*OSetFree_t) ( void* p ); // * Create: allocates and initialises the OSet. Arguments: // - alloc The allocation function used internally for allocating the // OSet and all its nodes. +// - cc Cost centre string used by 'alloc'. // - free The deallocation function used internally for freeing nodes // called by VG_(OSetWord_Destroy)(). // @@ -98,7 +99,7 @@ typedef void (*OSetFree_t) ( void* p ); // to allow the destruction of any attached resources; if NULL it is not // called. -extern OSet* VG_(OSetWord_Create) ( OSetAlloc_t alloc, HChar* ec, +extern OSet* VG_(OSetWord_Create) ( OSetAlloc_t alloc, HChar* cc, OSetFree_t _free ); extern void VG_(OSetWord_Destroy) ( OSet* os ); @@ -161,6 +162,7 @@ extern Bool VG_(OSetWord_Next) ( OSet* os, /*OUT*/UWord* val ); // - alloc The allocation function used for allocating the OSet itself; // it's also called for each invocation of // VG_(OSetGen_AllocNode)(). +// - cc Cost centre string used by 'alloc'. // - free The deallocation function used by VG_(OSetGen_FreeNode)() and // VG_(OSetGen_Destroy)(). // @@ -184,7 +186,7 @@ extern Bool VG_(OSetWord_Next) ( OSet* os, /*OUT*/UWord* val ); // lead to assertions in Valgrind's allocator. extern OSet* VG_(OSetGen_Create) ( PtrdiffT keyOff, OSetCmp_t cmp, - OSetAlloc_t alloc, HChar* ec, + OSetAlloc_t alloc, HChar* cc, OSetFree_t _free ); extern void VG_(OSetGen_Destroy) ( OSet* os ); extern void* VG_(OSetGen_AllocNode) ( OSet* os, SizeT elemSize ); diff --git a/include/pub_tool_redir.h b/include/pub_tool_redir.h index bd581a1..a13f864 100644 --- a/include/pub_tool_redir.h +++ b/include/pub_tool_redir.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -217,6 +217,9 @@ #if defined(VGO_linux) +#define VG_Z_LD_LINUX_SO_3 ldZhlinuxZdsoZd3 // ld-linux.so.3 +#define VG_U_LD_LINUX_SO_3 "ld-linux.so.3" + #define VG_Z_LD_LINUX_SO_2 ldZhlinuxZdsoZd2 // ld-linux.so.2 #define VG_U_LD_LINUX_SO_2 "ld-linux.so.2" diff --git a/include/pub_tool_replacemalloc.h b/include/pub_tool_replacemalloc.h index 067b7ff..7db215d 100644 --- a/include/pub_tool_replacemalloc.h +++ b/include/pub_tool_replacemalloc.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_seqmatch.h b/include/pub_tool_seqmatch.h index a1763b7..acce3be 100644 --- a/include/pub_tool_seqmatch.h +++ b/include/pub_tool_seqmatch.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_signals.h b/include/pub_tool_signals.h index bb96018..3ffefd5 100644 --- a/include/pub_tool_signals.h +++ b/include/pub_tool_signals.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_sparsewa.h b/include/pub_tool_sparsewa.h index 29bb336..d037043 100644 --- a/include/pub_tool_sparsewa.h +++ b/include/pub_tool_sparsewa.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_stacktrace.h b/include/pub_tool_stacktrace.h index 6792c69..d22a824 100644 --- a/include/pub_tool_stacktrace.h +++ b/include/pub_tool_stacktrace.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_threadstate.h b/include/pub_tool_threadstate.h index d572e87..993abfd 100644 --- a/include/pub_tool_threadstate.h +++ b/include/pub_tool_threadstate.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -36,7 +36,7 @@ scheduler algorithms is surely O(N) in the number of threads, since that's simple, at least. And (in practice) we hope that most programs do not need many threads. */ -#define VG_N_THREADS 300 +#define VG_N_THREADS 500 /* Special magic value for an invalid ThreadId. It corresponds to LinuxThreads using zero as the initial value for diff --git a/include/pub_tool_tooliface.h b/include/pub_tool_tooliface.h index fa8d104..ac346b9 100644 --- a/include/pub_tool_tooliface.h +++ b/include/pub_tool_tooliface.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -374,10 +374,17 @@ extern void VG_(needs_superblock_discards) ( /* Tool defines its own command line options? */ extern void VG_(needs_command_line_options) ( - // Return True if option was recognised. Presumably sets some state to - // record the option as well. Nb: tools can assume that the argv will - // never disappear. So they can, for example, store a pointer to a string - // within an option, rather than having to make a copy. + // Return True if option was recognised, False if it wasn't (but also see + // below). Presumably sets some state to record the option as well. + // + // Nb: tools can assume that the argv will never disappear. So they can, + // for example, store a pointer to a string within an option, rather than + // having to make a copy. + // + // Options (and combinations of options) should be checked in this function + // if possible rather than in post_clo_init(), and if they are bad then + // VG_(fmsg_bad_option)() should be called. This ensures that the + // messaging is consistent with command line option errors from the core. Bool (*process_cmd_line_option)(Char* argv), // Print out command line usage for options for normal tool operation. diff --git a/include/pub_tool_vki.h b/include/pub_tool_vki.h index 27113af..9c74b05 100644 --- a/include/pub_tool_vki.h +++ b/include/pub_tool_vki.h @@ -8,11 +8,11 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_vkiscnums.h b/include/pub_tool_vkiscnums.h index 38f2c85..fa93a9c 100644 --- a/include/pub_tool_vkiscnums.h +++ b/include/pub_tool_vkiscnums.h @@ -7,9 +7,9 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/include/pub_tool_vkiscnums_asm.h b/include/pub_tool_vkiscnums_asm.h index b07de68..8c0f5d5 100644 --- a/include/pub_tool_vkiscnums_asm.h +++ b/include/pub_tool_vkiscnums_asm.h @@ -7,9 +7,9 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -45,6 +45,9 @@ #elif defined(VGP_ppc64_linux) # include "vki/vki-scnums-ppc64-linux.h" +#elif defined(VGP_arm_linux) +# include "vki/vki-scnums-arm-linux.h" + #elif defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) # include "vki/vki-scnums-freebsd.h" diff --git a/include/pub_tool_wordfm.h b/include/pub_tool_wordfm.h index 57c57db..77027ad 100644 --- a/include/pub_tool_wordfm.h +++ b/include/pub_tool_wordfm.h @@ -9,13 +9,13 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2007-2009 Julian Seward + Copyright (C) 2007-2010 Julian Seward jseward@acm.org This code is based on previous work by Nicholas Nethercote (coregrind/m_oset.c) which is - Copyright (C) 2005-2009 Nicholas Nethercote + Copyright (C) 2005-2010 Nicholas Nethercote njn@valgrind.org which in turn was derived partially from: diff --git a/include/pub_tool_xarray.h b/include/pub_tool_xarray.h index d9147f8..cd1b02e 100644 --- a/include/pub_tool_xarray.h +++ b/include/pub_tool_xarray.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2007-2009 OpenWorks LLP + Copyright (C) 2007-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -125,6 +125,16 @@ extern void VG_(dropHeadXA) ( XArray*, Word ); is NULL, in which case the parent's cost-center is used. */ extern XArray* VG_(cloneXA)( HChar* cc, XArray* xa ); +/* Get the raw array and size so callers can index it really fast. + This is dangerous in the sense that there's no range or + anything-else checking. It's also dangerous in that if + VG_(addToXA) is used, the contents may be re-located without + warning, hence making the contents address returned here + invalid. */ +extern void VG_(getContentsXA_UNSAFE)( XArray* sr, + /*OUT*/void** ctsP, + /*OUT*/Word* usedP ); + /* Convenience function: printf into an XArray of HChar, adding stuff at the end. This is very convenient for concocting arbitrary length printf output in an XArray. Note that the resulting string diff --git a/include/valgrind.h b/include/valgrind.h index 64897a8..0bae0aa 100644 --- a/include/valgrind.h +++ b/include/valgrind.h @@ -12,7 +12,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward. All rights reserved. + Copyright (C) 2000-2010 Julian Seward. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions @@ -73,6 +73,25 @@ #ifndef __VALGRIND_H #define __VALGRIND_H + +/* ------------------------------------------------------------------ */ +/* VERSION NUMBER OF VALGRIND */ +/* ------------------------------------------------------------------ */ + +/* Specify Valgrind's version number, so that user code can + conditionally compile based on our version number. Note that these + were introduced at version 3.6 and so do not exist in version 3.5 + or earlier. The recommended way to use them to check for "version + X.Y or later" is (eg) + +#if defined(__VALGRIND_MAJOR__) && defined(__VALGRIND_MINOR__) \ + && (__VALGRIND_MAJOR__ > 3 \ + || (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6)) +*/ +#define __VALGRIND_MAJOR__ 3 +#define __VALGRIND_MINOR__ 6 + + #include /* Nb: this file might be included in a file compiled with -ansi. So @@ -84,14 +103,21 @@ identifying architectures, which are different to the ones we use within the rest of Valgrind. Note, __powerpc__ is active for both 32 and 64-bit PPC, whereas __powerpc64__ is only active for the - latter (on Linux, that is). */ + latter (on Linux, that is). + + Misc note: how to find out what's predefined in gcc by default: + gcc -Wp,-dM somefile.c +*/ +#undef PLAT_ppc64_aix5 +#undef PLAT_ppc32_aix5 +#undef PLAT_x86_darwin +#undef PLAT_amd64_darwin +#undef PLAT_x86_win32 #undef PLAT_x86_linux #undef PLAT_amd64_linux #undef PLAT_ppc32_linux #undef PLAT_ppc64_linux -#undef PLAT_ppc32_aix5 -#undef PLAT_ppc64_aix5 - +#undef PLAT_arm_linux #if defined(_AIX) && defined(__64BIT__) # define PLAT_ppc64_aix5 1 @@ -101,14 +127,18 @@ # define PLAT_x86_darwin 1 #elif defined(__APPLE__) && defined(__x86_64__) # define PLAT_amd64_darwin 1 -#elif defined(__i386__) +#elif defined(__MINGW32__) || defined(__CYGWIN32__) || defined(_WIN32) && defined(_M_IX86) +# define PLAT_x86_win32 1 +#elif defined(__linux__) && defined(__i386__) # define PLAT_x86_linux 1 -#elif defined(__x86_64__) +#elif defined(__linux__) && defined(__x86_64__) # define PLAT_amd64_linux 1 -#elif defined(__powerpc__) && !defined(__powerpc64__) +#elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__) # define PLAT_ppc32_linux 1 -#elif defined(__powerpc__) && defined(__powerpc64__) +#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) # define PLAT_ppc64_linux 1 +#elif defined(__linux__) && defined(__arm__) +# define PLAT_arm_linux 1 #else /* If we're not compiling for our target platform, don't generate any inline asms. */ @@ -174,7 +204,8 @@ /* ------------------------- x86-{linux,darwin} ---------------- */ -#if defined(PLAT_x86_linux) || defined(PLAT_x86_darwin) +#if defined(PLAT_x86_linux) || defined(PLAT_x86_darwin) \ + || (defined(PLAT_x86_win32) && defined(__GNUC__)) typedef struct { @@ -224,7 +255,62 @@ typedef __SPECIAL_INSTRUCTION_PREAMBLE \ /* call-noredir *%EAX */ \ "xchgl %%edx,%%edx\n\t" -#endif /* PLAT_x86_linux || PLAT_x86_darwin */ +#endif /* PLAT_x86_linux || PLAT_x86_darwin || (PLAT_x86_win32 && __GNUC__) */ + +/* ------------------------- x86-Win32 ------------------------- */ + +#if defined(PLAT_x86_win32) && !defined(__GNUC__) + +typedef + struct { + unsigned int nraddr; /* where's the code? */ + } + OrigFn; + +#if defined(_MSC_VER) + +#define __SPECIAL_INSTRUCTION_PREAMBLE \ + __asm rol edi, 3 __asm rol edi, 13 \ + __asm rol edi, 29 __asm rol edi, 19 + +#define VALGRIND_DO_CLIENT_REQUEST( \ + _zzq_rlval, _zzq_default, _zzq_request, \ + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ + { volatile uintptr_t _zzq_args[6]; \ + volatile unsigned int _zzq_result; \ + _zzq_args[0] = (uintptr_t)(_zzq_request); \ + _zzq_args[1] = (uintptr_t)(_zzq_arg1); \ + _zzq_args[2] = (uintptr_t)(_zzq_arg2); \ + _zzq_args[3] = (uintptr_t)(_zzq_arg3); \ + _zzq_args[4] = (uintptr_t)(_zzq_arg4); \ + _zzq_args[5] = (uintptr_t)(_zzq_arg5); \ + __asm { __asm lea eax, _zzq_args __asm mov edx, _zzq_default \ + __SPECIAL_INSTRUCTION_PREAMBLE \ + /* %EDX = client_request ( %EAX ) */ \ + __asm xchg ebx,ebx \ + __asm mov _zzq_result, edx \ + } \ + _zzq_rlval = _zzq_result; \ + } + +#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \ + { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \ + volatile unsigned int __addr; \ + __asm { __SPECIAL_INSTRUCTION_PREAMBLE \ + /* %EAX = guest_NRADDR */ \ + __asm xchg ecx,ecx \ + __asm mov __addr, eax \ + } \ + _zzq_orig->nraddr = __addr; \ + } + +#define VALGRIND_CALL_NOREDIR_EAX ERROR + +#else +#error Unsupported compiler. +#endif + +#endif /* PLAT_x86_win32 */ /* ------------------------ amd64-{linux,darwin} --------------- */ @@ -406,6 +492,65 @@ typedef #endif /* PLAT_ppc64_linux */ +/* ------------------------- arm-linux ------------------------- */ + +#if defined(PLAT_arm_linux) + +typedef + struct { + unsigned int nraddr; /* where's the code? */ + } + OrigFn; + +#define __SPECIAL_INSTRUCTION_PREAMBLE \ + "mov r12, r12, ror #3 ; mov r12, r12, ror #13 \n\t" \ + "mov r12, r12, ror #29 ; mov r12, r12, ror #19 \n\t" + +#define VALGRIND_DO_CLIENT_REQUEST( \ + _zzq_rlval, _zzq_default, _zzq_request, \ + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ + \ + { volatile unsigned int _zzq_args[6]; \ + volatile unsigned int _zzq_result; \ + _zzq_args[0] = (unsigned int)(_zzq_request); \ + _zzq_args[1] = (unsigned int)(_zzq_arg1); \ + _zzq_args[2] = (unsigned int)(_zzq_arg2); \ + _zzq_args[3] = (unsigned int)(_zzq_arg3); \ + _zzq_args[4] = (unsigned int)(_zzq_arg4); \ + _zzq_args[5] = (unsigned int)(_zzq_arg5); \ + __asm__ volatile("mov r3, %1\n\t" /*default*/ \ + "mov r4, %2\n\t" /*ptr*/ \ + __SPECIAL_INSTRUCTION_PREAMBLE \ + /* R3 = client_request ( R4 ) */ \ + "orr r10, r10, r10\n\t" \ + "mov %0, r3" /*result*/ \ + : "=r" (_zzq_result) \ + : "r" (_zzq_default), "r" (&_zzq_args[0]) \ + : "cc","memory", "r3", "r4"); \ + _zzq_rlval = _zzq_result; \ + } + +#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \ + { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \ + unsigned int __addr; \ + __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ + /* R3 = guest_NRADDR */ \ + "orr r11, r11, r11\n\t" \ + "mov %0, r3" \ + : "=r" (__addr) \ + : \ + : "cc", "memory", "r3" \ + ); \ + _zzq_orig->nraddr = __addr; \ + } + +#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + __SPECIAL_INSTRUCTION_PREAMBLE \ + /* branch-and-link-to-noredir *%R4 */ \ + "orr r12, r12, r12\n\t" + +#endif /* PLAT_arm_linux */ + /* ------------------------ ppc32-aix5 ------------------------- */ #if defined(PLAT_ppc32_aix5) @@ -667,10 +812,11 @@ typedef _argvec[0] = (unsigned long)_orig.nraddr; \ _argvec[1] = (unsigned long)(arg1); \ __asm__ volatile( \ + "subl $12, %%esp\n\t" \ "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $4, %%esp\n" \ + "addl $16, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -687,11 +833,12 @@ typedef _argvec[1] = (unsigned long)(arg1); \ _argvec[2] = (unsigned long)(arg2); \ __asm__ volatile( \ + "subl $8, %%esp\n\t" \ "pushl 8(%%eax)\n\t" \ "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $8, %%esp\n" \ + "addl $16, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -709,12 +856,13 @@ typedef _argvec[2] = (unsigned long)(arg2); \ _argvec[3] = (unsigned long)(arg3); \ __asm__ volatile( \ + "subl $4, %%esp\n\t" \ "pushl 12(%%eax)\n\t" \ "pushl 8(%%eax)\n\t" \ "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $12, %%esp\n" \ + "addl $16, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -759,6 +907,7 @@ typedef _argvec[4] = (unsigned long)(arg4); \ _argvec[5] = (unsigned long)(arg5); \ __asm__ volatile( \ + "subl $12, %%esp\n\t" \ "pushl 20(%%eax)\n\t" \ "pushl 16(%%eax)\n\t" \ "pushl 12(%%eax)\n\t" \ @@ -766,7 +915,7 @@ typedef "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $20, %%esp\n" \ + "addl $32, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -787,6 +936,7 @@ typedef _argvec[5] = (unsigned long)(arg5); \ _argvec[6] = (unsigned long)(arg6); \ __asm__ volatile( \ + "subl $8, %%esp\n\t" \ "pushl 24(%%eax)\n\t" \ "pushl 20(%%eax)\n\t" \ "pushl 16(%%eax)\n\t" \ @@ -795,7 +945,7 @@ typedef "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $24, %%esp\n" \ + "addl $32, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -818,6 +968,7 @@ typedef _argvec[6] = (unsigned long)(arg6); \ _argvec[7] = (unsigned long)(arg7); \ __asm__ volatile( \ + "subl $4, %%esp\n\t" \ "pushl 28(%%eax)\n\t" \ "pushl 24(%%eax)\n\t" \ "pushl 20(%%eax)\n\t" \ @@ -827,7 +978,7 @@ typedef "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $28, %%esp\n" \ + "addl $32, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -886,6 +1037,7 @@ typedef _argvec[8] = (unsigned long)(arg8); \ _argvec[9] = (unsigned long)(arg9); \ __asm__ volatile( \ + "subl $12, %%esp\n\t" \ "pushl 36(%%eax)\n\t" \ "pushl 32(%%eax)\n\t" \ "pushl 28(%%eax)\n\t" \ @@ -897,7 +1049,7 @@ typedef "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $36, %%esp\n" \ + "addl $48, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -923,6 +1075,7 @@ typedef _argvec[9] = (unsigned long)(arg9); \ _argvec[10] = (unsigned long)(arg10); \ __asm__ volatile( \ + "subl $8, %%esp\n\t" \ "pushl 40(%%eax)\n\t" \ "pushl 36(%%eax)\n\t" \ "pushl 32(%%eax)\n\t" \ @@ -935,7 +1088,7 @@ typedef "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $40, %%esp\n" \ + "addl $48, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -963,6 +1116,7 @@ typedef _argvec[10] = (unsigned long)(arg10); \ _argvec[11] = (unsigned long)(arg11); \ __asm__ volatile( \ + "subl $4, %%esp\n\t" \ "pushl 44(%%eax)\n\t" \ "pushl 40(%%eax)\n\t" \ "pushl 36(%%eax)\n\t" \ @@ -976,7 +1130,7 @@ typedef "pushl 4(%%eax)\n\t" \ "movl (%%eax), %%eax\n\t" /* target->%eax */ \ VALGRIND_CALL_NOREDIR_EAX \ - "addl $44, %%esp\n" \ + "addl $48, %%esp\n" \ : /*out*/ "=a" (_res) \ : /*in*/ "a" (&_argvec[0]) \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ @@ -1039,6 +1193,78 @@ typedef #define __CALLER_SAVED_REGS /*"rax",*/ "rcx", "rdx", "rsi", \ "rdi", "r8", "r9", "r10", "r11" +/* This is all pretty complex. It's so as to make stack unwinding + work reliably. See bug 243270. The basic problem is the sub and + add of 128 of %rsp in all of the following macros. If gcc believes + the CFA is in %rsp, then unwinding may fail, because what's at the + CFA is not what gcc "expected" when it constructs the CFIs for the + places where the macros are instantiated. + + But we can't just add a CFI annotation to increase the CFA offset + by 128, to match the sub of 128 from %rsp, because we don't know + whether gcc has chosen %rsp as the CFA at that point, or whether it + has chosen some other register (eg, %rbp). In the latter case, + adding a CFI annotation to change the CFA offset is simply wrong. + + So the solution is to get hold of the CFA using + __builtin_dwarf_cfa(), put it in a known register, and add a + CFI annotation to say what the register is. We choose %rbp for + this (perhaps perversely), because: + + (1) %rbp is already subject to unwinding. If a new register was + chosen then the unwinder would have to unwind it in all stack + traces, which is expensive, and + + (2) %rbp is already subject to precise exception updates in the + JIT. If a new register was chosen, we'd have to have precise + exceptions for it too, which reduces performance of the + generated code. + + However .. one extra complication. We can't just whack the result + of __builtin_dwarf_cfa() into %rbp and then add %rbp to the + list of trashed registers at the end of the inline assembly + fragments; gcc won't allow %rbp to appear in that list. Hence + instead we need to stash %rbp in %r15 for the duration of the asm, + and say that %r15 is trashed instead. gcc seems happy to go with + that. + + Oh .. and this all needs to be conditionalised so that it is + unchanged from before this commit, when compiled with older gccs + that don't support __builtin_dwarf_cfa. Furthermore, since + this header file is freestanding, it has to be independent of + config.h, and so the following conditionalisation cannot depend on + configure time checks. + + Although it's not clear from + 'defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)', + this expression excludes Darwin. + .cfi directives in Darwin assembly appear to be completely + different and I haven't investigated how they work. + + For even more entertainment value, note we have to use the + completely undocumented __builtin_dwarf_cfa(), which appears to + really compute the CFA, whereas __builtin_frame_address(0) claims + to but actually doesn't. See + https://bugs.kde.org/show_bug.cgi?id=243270#c47 +*/ +#if defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM) +# define __FRAME_POINTER \ + ,"r"(__builtin_dwarf_cfa()) +# define VALGRIND_CFI_PROLOGUE \ + "movq %%rbp, %%r15\n\t" \ + "movq %2, %%rbp\n\t" \ + ".cfi_remember_state\n\t" \ + ".cfi_def_cfa rbp, 0\n\t" +# define VALGRIND_CFI_EPILOGUE \ + "movq %%r15, %%rbp\n\t" \ + ".cfi_restore_state\n\t" +#else +# define __FRAME_POINTER +# define VALGRIND_CFI_PROLOGUE +# define VALGRIND_CFI_EPILOGUE +#endif + + /* These CALL_FN_ macros assume that on amd64-linux, sizeof(unsigned long) == 8. */ @@ -1070,13 +1296,15 @@ typedef volatile unsigned long _res; \ _argvec[0] = (unsigned long)_orig.nraddr; \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1089,14 +1317,16 @@ typedef _argvec[0] = (unsigned long)_orig.nraddr; \ _argvec[1] = (unsigned long)(arg1); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "movq 8(%%rax), %%rdi\n\t" \ "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1110,15 +1340,17 @@ typedef _argvec[1] = (unsigned long)(arg1); \ _argvec[2] = (unsigned long)(arg2); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "movq 16(%%rax), %%rsi\n\t" \ "movq 8(%%rax), %%rdi\n\t" \ "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1133,6 +1365,7 @@ typedef _argvec[2] = (unsigned long)(arg2); \ _argvec[3] = (unsigned long)(arg3); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "movq 24(%%rax), %%rdx\n\t" \ "movq 16(%%rax), %%rsi\n\t" \ @@ -1140,9 +1373,10 @@ typedef "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1158,6 +1392,7 @@ typedef _argvec[3] = (unsigned long)(arg3); \ _argvec[4] = (unsigned long)(arg4); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "movq 32(%%rax), %%rcx\n\t" \ "movq 24(%%rax), %%rdx\n\t" \ @@ -1166,9 +1401,10 @@ typedef "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1185,6 +1421,7 @@ typedef _argvec[4] = (unsigned long)(arg4); \ _argvec[5] = (unsigned long)(arg5); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "movq 40(%%rax), %%r8\n\t" \ "movq 32(%%rax), %%rcx\n\t" \ @@ -1194,9 +1431,10 @@ typedef "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1214,6 +1452,7 @@ typedef _argvec[5] = (unsigned long)(arg5); \ _argvec[6] = (unsigned long)(arg6); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "movq 48(%%rax), %%r9\n\t" \ "movq 40(%%rax), %%r8\n\t" \ @@ -1222,11 +1461,12 @@ typedef "movq 16(%%rax), %%rsi\n\t" \ "movq 8(%%rax), %%rdi\n\t" \ "movq (%%rax), %%rax\n\t" /* target->%rax */ \ - "addq $128,%%rsp\n\t" \ VALGRIND_CALL_NOREDIR_RAX \ + "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1246,7 +1486,8 @@ typedef _argvec[6] = (unsigned long)(arg6); \ _argvec[7] = (unsigned long)(arg7); \ __asm__ volatile( \ - "subq $128,%%rsp\n\t" \ + VALGRIND_CFI_PROLOGUE \ + "subq $136,%%rsp\n\t" \ "pushq 56(%%rax)\n\t" \ "movq 48(%%rax), %%r9\n\t" \ "movq 40(%%rax), %%r8\n\t" \ @@ -1257,10 +1498,11 @@ typedef "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $8, %%rsp\n" \ - "addq $128,%%rsp\n\t" \ + "addq $136,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1281,6 +1523,7 @@ typedef _argvec[7] = (unsigned long)(arg7); \ _argvec[8] = (unsigned long)(arg8); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "pushq 64(%%rax)\n\t" \ "pushq 56(%%rax)\n\t" \ @@ -1294,9 +1537,10 @@ typedef VALGRIND_CALL_NOREDIR_RAX \ "addq $16, %%rsp\n" \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1318,7 +1562,8 @@ typedef _argvec[8] = (unsigned long)(arg8); \ _argvec[9] = (unsigned long)(arg9); \ __asm__ volatile( \ - "subq $128,%%rsp\n\t" \ + VALGRIND_CFI_PROLOGUE \ + "subq $136,%%rsp\n\t" \ "pushq 72(%%rax)\n\t" \ "pushq 64(%%rax)\n\t" \ "pushq 56(%%rax)\n\t" \ @@ -1331,10 +1576,11 @@ typedef "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $24, %%rsp\n" \ - "addq $128,%%rsp\n\t" \ + "addq $136,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1357,6 +1603,7 @@ typedef _argvec[9] = (unsigned long)(arg9); \ _argvec[10] = (unsigned long)(arg10); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "pushq 80(%%rax)\n\t" \ "pushq 72(%%rax)\n\t" \ @@ -1372,9 +1619,10 @@ typedef VALGRIND_CALL_NOREDIR_RAX \ "addq $32, %%rsp\n" \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1398,7 +1646,8 @@ typedef _argvec[10] = (unsigned long)(arg10); \ _argvec[11] = (unsigned long)(arg11); \ __asm__ volatile( \ - "subq $128,%%rsp\n\t" \ + VALGRIND_CFI_PROLOGUE \ + "subq $136,%%rsp\n\t" \ "pushq 88(%%rax)\n\t" \ "pushq 80(%%rax)\n\t" \ "pushq 72(%%rax)\n\t" \ @@ -1413,10 +1662,11 @@ typedef "movq (%%rax), %%rax\n\t" /* target->%rax */ \ VALGRIND_CALL_NOREDIR_RAX \ "addq $40, %%rsp\n" \ - "addq $128,%%rsp\n\t" \ + "addq $136,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -1441,6 +1691,7 @@ typedef _argvec[11] = (unsigned long)(arg11); \ _argvec[12] = (unsigned long)(arg12); \ __asm__ volatile( \ + VALGRIND_CFI_PROLOGUE \ "subq $128,%%rsp\n\t" \ "pushq 96(%%rax)\n\t" \ "pushq 88(%%rax)\n\t" \ @@ -1458,9 +1709,10 @@ typedef VALGRIND_CALL_NOREDIR_RAX \ "addq $48, %%rsp\n" \ "addq $128,%%rsp\n\t" \ + VALGRIND_CFI_EPILOGUE \ : /*out*/ "=a" (_res) \ - : /*in*/ "a" (&_argvec[0]) \ - : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \ ); \ lval = (__typeof__(lval)) _res; \ } while (0) @@ -2458,6 +2710,422 @@ typedef #endif /* PLAT_ppc64_linux */ +/* ------------------------- arm-linux ------------------------- */ + +#if defined(PLAT_arm_linux) + +/* These regs are trashed by the hidden call. */ +#define __CALLER_SAVED_REGS "r0", "r1", "r2", "r3","r4","r14" + +/* These CALL_FN_ macros assume that on arm-linux, sizeof(unsigned + long) == 4. */ + +#define CALL_FN_W_v(lval, orig) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[1]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + __asm__ volatile( \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "mov %0, r0\n" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_W(lval, orig, arg1) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[2]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + __asm__ volatile( \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "mov %0, r0\n" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WW(lval, orig, arg1,arg2) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[3]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + __asm__ volatile( \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "mov %0, r0\n" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[4]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + __asm__ volatile( \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "mov %0, r0\n" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[5]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + __asm__ volatile( \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[6]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + __asm__ volatile( \ + "ldr r0, [%1, #20] \n\t" \ + "push {r0} \n\t" \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "add sp, sp, #4 \n\t" \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[7]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + __asm__ volatile( \ + "ldr r0, [%1, #20] \n\t" \ + "ldr r1, [%1, #24] \n\t" \ + "push {r0, r1} \n\t" \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "add sp, sp, #8 \n\t" \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ + arg7) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[8]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + __asm__ volatile( \ + "ldr r0, [%1, #20] \n\t" \ + "ldr r1, [%1, #24] \n\t" \ + "ldr r2, [%1, #28] \n\t" \ + "push {r0, r1, r2} \n\t" \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "add sp, sp, #12 \n\t" \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ + arg7,arg8) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[9]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + __asm__ volatile( \ + "ldr r0, [%1, #20] \n\t" \ + "ldr r1, [%1, #24] \n\t" \ + "ldr r2, [%1, #28] \n\t" \ + "ldr r3, [%1, #32] \n\t" \ + "push {r0, r1, r2, r3} \n\t" \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "add sp, sp, #16 \n\t" \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ + arg7,arg8,arg9) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[10]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + __asm__ volatile( \ + "ldr r0, [%1, #20] \n\t" \ + "ldr r1, [%1, #24] \n\t" \ + "ldr r2, [%1, #28] \n\t" \ + "ldr r3, [%1, #32] \n\t" \ + "ldr r4, [%1, #36] \n\t" \ + "push {r0, r1, r2, r3, r4} \n\t" \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "add sp, sp, #20 \n\t" \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ + arg7,arg8,arg9,arg10) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[11]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + __asm__ volatile( \ + "ldr r0, [%1, #40] \n\t" \ + "push {r0} \n\t" \ + "ldr r0, [%1, #20] \n\t" \ + "ldr r1, [%1, #24] \n\t" \ + "ldr r2, [%1, #28] \n\t" \ + "ldr r3, [%1, #32] \n\t" \ + "ldr r4, [%1, #36] \n\t" \ + "push {r0, r1, r2, r3, r4} \n\t" \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "add sp, sp, #24 \n\t" \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \ + arg6,arg7,arg8,arg9,arg10, \ + arg11) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[12]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + _argvec[11] = (unsigned long)(arg11); \ + __asm__ volatile( \ + "ldr r0, [%1, #40] \n\t" \ + "ldr r1, [%1, #44] \n\t" \ + "push {r0, r1} \n\t" \ + "ldr r0, [%1, #20] \n\t" \ + "ldr r1, [%1, #24] \n\t" \ + "ldr r2, [%1, #28] \n\t" \ + "ldr r3, [%1, #32] \n\t" \ + "ldr r4, [%1, #36] \n\t" \ + "push {r0, r1, r2, r3, r4} \n\t" \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "add sp, sp, #28 \n\t" \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory",__CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \ + arg6,arg7,arg8,arg9,arg10, \ + arg11,arg12) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[13]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + _argvec[11] = (unsigned long)(arg11); \ + _argvec[12] = (unsigned long)(arg12); \ + __asm__ volatile( \ + "ldr r0, [%1, #40] \n\t" \ + "ldr r1, [%1, #44] \n\t" \ + "ldr r2, [%1, #48] \n\t" \ + "push {r0, r1, r2} \n\t" \ + "ldr r0, [%1, #20] \n\t" \ + "ldr r1, [%1, #24] \n\t" \ + "ldr r2, [%1, #28] \n\t" \ + "ldr r3, [%1, #32] \n\t" \ + "ldr r4, [%1, #36] \n\t" \ + "push {r0, r1, r2, r3, r4} \n\t" \ + "ldr r0, [%1, #4] \n\t" \ + "ldr r1, [%1, #8] \n\t" \ + "ldr r2, [%1, #12] \n\t" \ + "ldr r3, [%1, #16] \n\t" \ + "ldr r4, [%1] \n\t" /* target->r4 */ \ + VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \ + "add sp, sp, #32 \n\t" \ + "mov %0, r0" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "0" (&_argvec[0]) \ + : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#endif /* PLAT_arm_linux */ + /* ------------------------ ppc32-aix5 ------------------------- */ #if defined(PLAT_ppc32_aix5) @@ -3639,8 +4307,17 @@ typedef VG_USERREQ__MEMPOOL_EXISTS = 0x130a, /* Allow printfs to valgrind log. */ + /* The first two pass the va_list argument by value, which + assumes it is the same size as or smaller than a UWord, + which generally isn't the case. Hence are deprecated. + The second two pass the vargs by reference and so are + immune to this problem. */ + /* both :: char* fmt, va_list vargs (DEPRECATED) */ VG_USERREQ__PRINTF = 0x1401, VG_USERREQ__PRINTF_BACKTRACE = 0x1402, + /* both :: char* fmt, va_list* vargs */ + VG_USERREQ__PRINTF_VALIST_BY_REF = 0x1403, + VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF = 0x1404, /* Stack support. */ VG_USERREQ__STACK_REGISTER = 0x1501, @@ -3648,24 +4325,77 @@ typedef VG_USERREQ__STACK_CHANGE = 0x1503, /* Wine support */ - VG_USERREQ__LOAD_PDB_DEBUGINFO = 0x1601 + VG_USERREQ__LOAD_PDB_DEBUGINFO = 0x1601, + + /* Querying of debug info. */ + VG_USERREQ__MAP_IP_TO_SRCLOC = 0x1701 } Vg_ClientRequest; #if !defined(__GNUC__) # define __extension__ /* */ #endif + +/* + * VALGRIND_DO_CLIENT_REQUEST_EXPR(): a C expression that invokes a Valgrind + * client request and whose value equals the client request result. + */ + +#if defined(NVALGRIND) + +#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ + _zzq_default, _zzq_request, \ + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ + (_zzq_default) + +#else /*defined(NVALGRIND)*/ + +#if defined(_MSC_VER) + +#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ + _zzq_default, _zzq_request, \ + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ + (vg_VALGRIND_DO_CLIENT_REQUEST_EXPR((uintptr_t)(_zzq_default), \ + (_zzq_request), (uintptr_t)(_zzq_arg1), (uintptr_t)(_zzq_arg2), \ + (uintptr_t)(_zzq_arg3), (uintptr_t)(_zzq_arg4), \ + (uintptr_t)(_zzq_arg5))) + +static __inline unsigned +vg_VALGRIND_DO_CLIENT_REQUEST_EXPR(uintptr_t _zzq_default, + unsigned _zzq_request, uintptr_t _zzq_arg1, + uintptr_t _zzq_arg2, uintptr_t _zzq_arg3, + uintptr_t _zzq_arg4, uintptr_t _zzq_arg5) +{ + unsigned _zzq_rlval; + VALGRIND_DO_CLIENT_REQUEST(_zzq_rlval, _zzq_default, _zzq_request, + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5); + return _zzq_rlval; +} + +#else /*defined(_MSC_VER)*/ + +#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ + _zzq_default, _zzq_request, \ + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ + (__extension__({unsigned int _zzq_rlval; \ + VALGRIND_DO_CLIENT_REQUEST(_zzq_rlval, _zzq_default, _zzq_request, \ + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ + _zzq_rlval; \ + })) + +#endif /*defined(_MSC_VER)*/ + +#endif /*defined(NVALGRIND)*/ + + /* Returns the number of Valgrinds this code is running under. That is, 0 if running natively, 1 if running under Valgrind, 2 if running under Valgrind which is running under another Valgrind, etc. */ -#define RUNNING_ON_VALGRIND __extension__ \ - ({unsigned int _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* if not */, \ - VG_USERREQ__RUNNING_ON_VALGRIND, \ - 0, 0, 0, 0, 0); \ - _qzz_res; \ - }) +#define RUNNING_ON_VALGRIND \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* if not */, \ + VG_USERREQ__RUNNING_ON_VALGRIND, \ + 0, 0, 0, 0, 0) \ /* Discard translation of code in the range [_qzz_addr .. _qzz_addr + @@ -3692,34 +4422,64 @@ typedef #else /* NVALGRIND */ +#if !defined(_MSC_VER) /* Modern GCC will optimize the static routine out if unused, and unused attribute will shut down warnings about it. */ static int VALGRIND_PRINTF(const char *format, ...) __attribute__((format(__printf__, 1, 2), __unused__)); +#endif static int +#if defined(_MSC_VER) +__inline +#endif VALGRIND_PRINTF(const char *format, ...) { unsigned long _qzz_res; va_list vargs; va_start(vargs, format); - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, VG_USERREQ__PRINTF, - (unsigned long)format, (unsigned long)vargs, +#if defined(_MSC_VER) + VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, + VG_USERREQ__PRINTF_VALIST_BY_REF, + (uintptr_t)format, + (uintptr_t)&vargs, + 0, 0, 0); +#else + VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, + VG_USERREQ__PRINTF_VALIST_BY_REF, + (unsigned long)format, + (unsigned long)&vargs, 0, 0, 0); +#endif va_end(vargs); return (int)_qzz_res; } +#if !defined(_MSC_VER) static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...) __attribute__((format(__printf__, 1, 2), __unused__)); +#endif static int +#if defined(_MSC_VER) +__inline +#endif VALGRIND_PRINTF_BACKTRACE(const char *format, ...) { unsigned long _qzz_res; va_list vargs; va_start(vargs, format); - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, VG_USERREQ__PRINTF_BACKTRACE, - (unsigned long)format, (unsigned long)vargs, +#if defined(_MSC_VER) + VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, + VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF, + (uintptr_t)format, + (uintptr_t)&vargs, 0, 0, 0); +#else + VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, + VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF, + (unsigned long)format, + (unsigned long)&vargs, + 0, 0, 0); +#endif va_end(vargs); return (int)_qzz_res; } @@ -4009,11 +4769,23 @@ VALGRIND_PRINTF_BACKTRACE(const char *format, ...) fd, ptr, total_size, delta, 0); \ } +/* Map a code address to a source file name and line number. buf64 + must point to a 64-byte buffer in the caller's address space. The + result will be dumped in there and is guaranteed to be zero + terminated. If no info is found, the first byte is set to zero. */ +#define VALGRIND_MAP_IP_TO_SRCLOC(addr, buf64) \ + {unsigned int _qzz_res; \ + VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, \ + VG_USERREQ__MAP_IP_TO_SRCLOC, \ + addr, buf64, 0, 0, 0); \ + } + #undef PLAT_x86_linux #undef PLAT_amd64_linux #undef PLAT_ppc32_linux #undef PLAT_ppc64_linux +#undef PLAT_arm_linux #undef PLAT_ppc32_aix5 #undef PLAT_ppc64_aix5 diff --git a/include/vki/vki-amd64-linux.h b/include/vki/vki-amd64-linux.h index bc5c455..de3fd41 100644 --- a/include/vki/vki-amd64-linux.h +++ b/include/vki/vki-amd64-linux.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -62,6 +62,12 @@ typedef unsigned int vki_u32; #define VKI_MAX_PAGE_SHIFT VKI_PAGE_SHIFT #define VKI_MAX_PAGE_SIZE VKI_PAGE_SIZE +//---------------------------------------------------------------------- +// From linux-2.6.35.4/arch/x86/include/asm/shmparam.h +//---------------------------------------------------------------------- + +#define VKI_SHMLBA VKI_PAGE_SIZE + //---------------------------------------------------------------------- // From linux-2.6.9/include/asm-x86_64/signal.h //---------------------------------------------------------------------- diff --git a/include/vki/vki-arm-linux.h b/include/vki/vki-arm-linux.h new file mode 100644 index 0000000..678e268 --- /dev/null +++ b/include/vki/vki-arm-linux.h @@ -0,0 +1,893 @@ + +/*--------------------------------------------------------------------*/ +/*--- arm/Linux-specific kernel interface. vki-arm-linux.h ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2000-2008 Julian Seward + jseward@acm.org + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#ifndef __VKI_ARM_LINUX_H +#define __VKI_ARM_LINUX_H + +// arm is little-endian. +#define VKI_LITTLE_ENDIAN 1 + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/types.h +//---------------------------------------------------------------------- + +typedef unsigned char __vki_u8; + +typedef __signed__ short __vki_s16; +typedef unsigned short __vki_u16; + +typedef __signed__ int __vki_s32; +typedef unsigned int __vki_u32; + +typedef __signed__ long long __vki_s64; +typedef unsigned long long __vki_u64; + +typedef unsigned short vki_u16; + +typedef unsigned int vki_u32; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/page.h +//---------------------------------------------------------------------- + +/* PAGE_SHIFT determines the page size */ +#define VKI_PAGE_SHIFT 12 +#define VKI_PAGE_SIZE (1UL << VKI_PAGE_SHIFT) +#define VKI_MAX_PAGE_SHIFT VKI_PAGE_SHIFT +#define VKI_MAX_PAGE_SIZE VKI_PAGE_SIZE + +//---------------------------------------------------------------------- +// From linux-2.6.35.4/arch/arm/include/asm/shmparam.h +//---------------------------------------------------------------------- + +#define VKI_SHMLBA (4 * VKI_PAGE_SIZE) + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/signal.h +//---------------------------------------------------------------------- + +#define VKI_MINSIGSTKSZ 2048 + +#define VKI_SIG_BLOCK 0 /* for blocking signals */ +#define VKI_SIG_UNBLOCK 1 /* for unblocking signals */ +#define VKI_SIG_SETMASK 2 /* for setting the signal mask */ + +/* Type of a signal handler. */ +typedef void __vki_signalfn_t(int); +typedef __vki_signalfn_t __user *__vki_sighandler_t; + +typedef void __vki_restorefn_t(void); +typedef __vki_restorefn_t __user *__vki_sigrestore_t; + +#define VKI_SIG_DFL ((__vki_sighandler_t)0) /* default signal handling */ +#define VKI_SIG_IGN ((__vki_sighandler_t)1) /* ignore signal */ + +#define _VKI_NSIG 64 +#define _VKI_NSIG_BPW 32 +#define _VKI_NSIG_WORDS (_VKI_NSIG / _VKI_NSIG_BPW) + +typedef unsigned long vki_old_sigset_t; /* at least 32 bits */ + +typedef struct { + unsigned long sig[_VKI_NSIG_WORDS]; +} vki_sigset_t; + +#define VKI_SIGHUP 1 +#define VKI_SIGINT 2 +#define VKI_SIGQUIT 3 +#define VKI_SIGILL 4 +#define VKI_SIGTRAP 5 +#define VKI_SIGABRT 6 +//#define VKI_SIGIOT 6 +#define VKI_SIGBUS 7 +#define VKI_SIGFPE 8 +#define VKI_SIGKILL 9 +#define VKI_SIGUSR1 10 +#define VKI_SIGSEGV 11 +#define VKI_SIGUSR2 12 +#define VKI_SIGPIPE 13 +#define VKI_SIGALRM 14 +#define VKI_SIGTERM 15 +#define VKI_SIGSTKFLT 16 +#define VKI_SIGCHLD 17 +#define VKI_SIGCONT 18 +#define VKI_SIGSTOP 19 +#define VKI_SIGTSTP 20 +#define VKI_SIGTTIN 21 +#define VKI_SIGTTOU 22 +#define VKI_SIGURG 23 +#define VKI_SIGXCPU 24 +#define VKI_SIGXFSZ 25 +#define VKI_SIGVTALRM 26 +#define VKI_SIGPROF 27 +#define VKI_SIGWINCH 28 +#define VKI_SIGIO 29 +#define VKI_SIGPWR 30 +#define VKI_SIGSYS 31 +#define VKI_SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define VKI_SIGRTMIN 32 +// [[This was (_NSIG-1) in 2.4.X... not sure if it matters.]] +#define VKI_SIGRTMAX _VKI_NSIG + +#define VKI_SA_NOCLDSTOP 0x00000001u +#define VKI_SA_NOCLDWAIT 0x00000002u +#define VKI_SA_SIGINFO 0x00000004u +#define VKI_SA_ONSTACK 0x08000000u +#define VKI_SA_RESTART 0x10000000u +#define VKI_SA_NODEFER 0x40000000u +#define VKI_SA_RESETHAND 0x80000000u + +#define VKI_SA_NOMASK VKI_SA_NODEFER +#define VKI_SA_ONESHOT VKI_SA_RESETHAND +//#define VKI_SA_INTERRUPT 0x20000000 /* dummy -- ignored */ + +#define VKI_SA_RESTORER 0x04000000 + +#define VKI_SS_ONSTACK 1 +#define VKI_SS_DISABLE 2 + +struct vki_old_sigaction { + // [[Nb: a 'k' prefix is added to "sa_handler" because + // bits/sigaction.h (which gets dragged in somehow via signal.h) + // #defines it as something else. Since that is done for glibc's + // purposes, which we don't care about here, we use our own name.]] + __vki_sighandler_t ksa_handler; + vki_old_sigset_t sa_mask; + unsigned long sa_flags; + __vki_sigrestore_t sa_restorer; +}; + +struct vki_sigaction_base { + // [[See comment about extra 'k' above]] + __vki_sighandler_t ksa_handler; + unsigned long sa_flags; + __vki_sigrestore_t sa_restorer; + vki_sigset_t sa_mask; /* mask last for extensibility */ +}; + +/* On Linux we use the same type for passing sigactions to + and from the kernel. Hence: */ +typedef struct vki_sigaction_base vki_sigaction_toK_t; +typedef struct vki_sigaction_base vki_sigaction_fromK_t; + + +typedef struct vki_sigaltstack { + void __user *ss_sp; + int ss_flags; + vki_size_t ss_size; +} vki_stack_t; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/sigcontext.h +//---------------------------------------------------------------------- + +struct _vki_fpreg { + unsigned short significand[4]; + unsigned short exponent; +}; + +struct _vki_fpxreg { + unsigned short significand[4]; + unsigned short exponent; + unsigned short padding[3]; +}; + +struct _vki_xmmreg { + unsigned long element[4]; +}; + +struct _vki_fpstate { + /* Regular FPU environment */ + unsigned long cw; + unsigned long sw; + unsigned long tag; + unsigned long ipoff; + unsigned long cssel; + unsigned long dataoff; + unsigned long datasel; + struct _vki_fpreg _st[8]; + unsigned short status; + unsigned short magic; /* 0xffff = regular FPU data only */ + + /* FXSR FPU environment */ + unsigned long _fxsr_env[6]; /* FXSR FPU env is ignored */ + unsigned long mxcsr; + unsigned long reserved; + struct _vki_fpxreg _fxsr_st[8]; /* FXSR FPU reg data is ignored */ + struct _vki_xmmreg _xmm[8]; + unsigned long padding[56]; +}; + +struct vki_sigcontext { + unsigned long trap_no; + unsigned long error_code; + unsigned long oldmask; + unsigned long arm_r0; + unsigned long arm_r1; + unsigned long arm_r2; + unsigned long arm_r3; + unsigned long arm_r4; + unsigned long arm_r5; + unsigned long arm_r6; + unsigned long arm_r7; + unsigned long arm_r8; + unsigned long arm_r9; + unsigned long arm_r10; + unsigned long arm_fp; + unsigned long arm_ip; + unsigned long arm_sp; + unsigned long arm_lr; + unsigned long arm_pc; + unsigned long arm_cpsr; + unsigned long fault_address; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/mman.h +//---------------------------------------------------------------------- + +#define VKI_PROT_NONE 0x0 /* No page permissions */ +#define VKI_PROT_READ 0x1 /* page can be read */ +#define VKI_PROT_WRITE 0x2 /* page can be written */ +#define VKI_PROT_EXEC 0x4 /* page can be executed */ +#define VKI_PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ +#define VKI_PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ + +#define VKI_MAP_SHARED 0x01 /* Share changes */ +#define VKI_MAP_PRIVATE 0x02 /* Changes are private */ +//#define VKI_MAP_TYPE 0x0f /* Mask for type of mapping */ +#define VKI_MAP_FIXED 0x10 /* Interpret addr exactly */ +#define VKI_MAP_ANONYMOUS 0x20 /* don't use a file */ +#define VKI_MAP_NORESERVE 0x4000 /* don't check for reservations */ + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/fcntl.h +//---------------------------------------------------------------------- + +#define VKI_O_RDONLY 00 +#define VKI_O_WRONLY 01 +#define VKI_O_RDWR 02 +#define VKI_O_CREAT 0100 /* not fcntl */ +#define VKI_O_EXCL 0200 /* not fcntl */ +#define VKI_O_TRUNC 01000 /* not fcntl */ +#define VKI_O_APPEND 02000 +#define VKI_O_NONBLOCK 04000 +#define VKI_O_LARGEFILE 0100000 + +#define VKI_AT_FDCWD -100 + +#define VKI_F_DUPFD 0 /* dup */ +#define VKI_F_GETFD 1 /* get close_on_exec */ +#define VKI_F_SETFD 2 /* set/clear close_on_exec */ +#define VKI_F_GETFL 3 /* get file->f_flags */ +#define VKI_F_SETFL 4 /* set file->f_flags */ +#define VKI_F_GETLK 5 +#define VKI_F_SETLK 6 +#define VKI_F_SETLKW 7 + +#define VKI_F_SETOWN 8 /* for sockets. */ +#define VKI_F_GETOWN 9 /* for sockets. */ +#define VKI_F_SETSIG 10 /* for sockets. */ +#define VKI_F_GETSIG 11 /* for sockets. */ + +#define VKI_F_GETLK64 12 /* using 'struct flock64' */ +#define VKI_F_SETLK64 13 +#define VKI_F_SETLKW64 14 + +/* for F_[GET|SET]FL */ +#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */ + +#define VKI_F_LINUX_SPECIFIC_BASE 1024 + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/resource.h +//---------------------------------------------------------------------- + +#define VKI_RLIMIT_DATA 2 /* max data size */ +#define VKI_RLIMIT_STACK 3 /* max stack size */ +#define VKI_RLIMIT_CORE 4 /* max core file size */ +#define VKI_RLIMIT_NOFILE 7 /* max number of open files */ + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/socket.h +//---------------------------------------------------------------------- + +#define VKI_SOL_SOCKET 1 + +#define VKI_SO_TYPE 3 + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/sockios.h +//---------------------------------------------------------------------- + +#define VKI_SIOCSPGRP 0x8902 +#define VKI_SIOCGPGRP 0x8904 +#define VKI_SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ +#define VKI_SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/stat.h +//---------------------------------------------------------------------- + +struct vki_stat { + unsigned long st_dev; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned long st_rdev; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long st_atime_nsec; + unsigned long st_mtime; + unsigned long st_mtime_nsec; + unsigned long st_ctime; + unsigned long st_ctime_nsec; + unsigned long __unused4; + unsigned long __unused5; +}; + +struct vki_stat64 { + unsigned long long st_dev; + unsigned char __pad0[4]; + +#define STAT64_HAS_BROKEN_ST_INO 1 + unsigned long __st_ino; + + unsigned int st_mode; + unsigned int st_nlink; + + unsigned long st_uid; + unsigned long st_gid; + + unsigned long long st_rdev; + unsigned char __pad3[4]; + + long long st_size; + unsigned long st_blksize; + + unsigned long st_blocks; /* Number 512-byte blocks allocated. */ + unsigned long __pad4; /* future possible st_blocks high bits */ + + unsigned long st_atime; + unsigned long st_atime_nsec; + + unsigned long st_mtime; + unsigned int st_mtime_nsec; + + unsigned long st_ctime; + unsigned long st_ctime_nsec; + + unsigned long long st_ino; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/statfs.h +//---------------------------------------------------------------------- + +// [[Nb: asm-i386/statfs.h just #include asm-generic/statfs.h directly]] +struct vki_statfs { + __vki_u32 f_type; + __vki_u32 f_bsize; + __vki_u32 f_blocks; + __vki_u32 f_bfree; + __vki_u32 f_bavail; + __vki_u32 f_files; + __vki_u32 f_ffree; + __vki_kernel_fsid_t f_fsid; + __vki_u32 f_namelen; + __vki_u32 f_frsize; + __vki_u32 f_spare[5]; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/termios.h +//---------------------------------------------------------------------- + +struct vki_winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define VKI_NCC 8 +struct vki_termio { + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + unsigned char c_line; /* line discipline */ + unsigned char c_cc[VKI_NCC]; /* control characters */ +}; + + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/termbits.h +//---------------------------------------------------------------------- + +typedef unsigned char vki_cc_t; +typedef unsigned int vki_tcflag_t; + +#define VKI_NCCS 19 +struct vki_termios { + vki_tcflag_t c_iflag; /* input mode flags */ + vki_tcflag_t c_oflag; /* output mode flags */ + vki_tcflag_t c_cflag; /* control mode flags */ + vki_tcflag_t c_lflag; /* local mode flags */ + vki_cc_t c_line; /* line discipline */ + vki_cc_t c_cc[VKI_NCCS]; /* control characters */ +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/ioctl.h +//---------------------------------------------------------------------- + +#define _VKI_IOC_NRBITS 8 +#define _VKI_IOC_TYPEBITS 8 +#define _VKI_IOC_SIZEBITS 14 +#define _VKI_IOC_DIRBITS 2 + +#define _VKI_IOC_NRMASK ((1 << _VKI_IOC_NRBITS)-1) +#define _VKI_IOC_TYPEMASK ((1 << _VKI_IOC_TYPEBITS)-1) +#define _VKI_IOC_SIZEMASK ((1 << _VKI_IOC_SIZEBITS)-1) +#define _VKI_IOC_DIRMASK ((1 << _VKI_IOC_DIRBITS)-1) + +#define _VKI_IOC_NRSHIFT 0 +#define _VKI_IOC_TYPESHIFT (_VKI_IOC_NRSHIFT+_VKI_IOC_NRBITS) +#define _VKI_IOC_SIZESHIFT (_VKI_IOC_TYPESHIFT+_VKI_IOC_TYPEBITS) +#define _VKI_IOC_DIRSHIFT (_VKI_IOC_SIZESHIFT+_VKI_IOC_SIZEBITS) + +#define _VKI_IOC_NONE 0U +#define _VKI_IOC_WRITE 1U +#define _VKI_IOC_READ 2U + +#define _VKI_IOC(dir,type,nr,size) \ + (((dir) << _VKI_IOC_DIRSHIFT) | \ + ((type) << _VKI_IOC_TYPESHIFT) | \ + ((nr) << _VKI_IOC_NRSHIFT) | \ + ((size) << _VKI_IOC_SIZESHIFT)) + +/* used to create numbers */ +#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0) +#define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size))) +#define _VKI_IOW(type,nr,size) _VKI_IOC(_VKI_IOC_WRITE,(type),(nr),(_VKI_IOC_TYPECHECK(size))) +#define _VKI_IOWR(type,nr,size) _VKI_IOC(_VKI_IOC_READ|_VKI_IOC_WRITE,(type),(nr),(_VKI_IOC_TYPECHECK(size))) + +/* used to decode ioctl numbers.. */ +#define _VKI_IOC_DIR(nr) (((nr) >> _VKI_IOC_DIRSHIFT) & _VKI_IOC_DIRMASK) +#define _VKI_IOC_TYPE(nr) (((nr) >> _VKI_IOC_TYPESHIFT) & _VKI_IOC_TYPEMASK) +#define _VKI_IOC_NR(nr) (((nr) >> _VKI_IOC_NRSHIFT) & _VKI_IOC_NRMASK) +#define _VKI_IOC_SIZE(nr) (((nr) >> _VKI_IOC_SIZESHIFT) & _VKI_IOC_SIZEMASK) + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/ioctls.h +//---------------------------------------------------------------------- + +#define VKI_TCGETS 0x5401 +#define VKI_TCSETS 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */ +#define VKI_TCSETSW 0x5403 +#define VKI_TCSETSF 0x5404 +#define VKI_TCGETA 0x5405 +#define VKI_TCSETA 0x5406 +#define VKI_TCSETAW 0x5407 +#define VKI_TCSETAF 0x5408 +#define VKI_TCSBRK 0x5409 +#define VKI_TCXONC 0x540A +#define VKI_TCFLSH 0x540B +#define VKI_TIOCSCTTY 0x540E +#define VKI_TIOCGPGRP 0x540F +#define VKI_TIOCSPGRP 0x5410 +#define VKI_TIOCOUTQ 0x5411 +#define VKI_TIOCGWINSZ 0x5413 +#define VKI_TIOCSWINSZ 0x5414 +#define VKI_TIOCMGET 0x5415 +#define VKI_TIOCMBIS 0x5416 +#define VKI_TIOCMBIC 0x5417 +#define VKI_TIOCMSET 0x5418 +#define VKI_FIONREAD 0x541B +#define VKI_TIOCLINUX 0x541C +#define VKI_FIONBIO 0x5421 +#define VKI_TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ +#define VKI_TIOCGPTN _VKI_IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ +#define VKI_TIOCSPTLCK _VKI_IOW('T',0x31, int) /* Lock/unlock Pty */ + +#define VKI_FIOASYNC 0x5452 +#define VKI_TIOCSERGETLSR 0x5459 /* Get line status register */ + +#define VKI_TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ + +//---------------------------------------------------------------------- +// From asm-generic/poll.h +//---------------------------------------------------------------------- + +/* These are specified by iBCS2 */ +#define VKI_POLLIN 0x0001 + +struct vki_pollfd { + int fd; + short events; + short revents; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/user.h +//---------------------------------------------------------------------- + +struct vki_user_i387_struct { + long cwd; + long swd; + long twd; + long fip; + long fcs; + long foo; + long fos; + long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ +}; + +struct vki_user_fxsr_struct { + unsigned short cwd; + unsigned short swd; + unsigned short twd; + unsigned short fop; + long fip; + long fcs; + long foo; + long fos; + long mxcsr; + long reserved; + long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ + long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ + long padding[56]; +}; + +struct vki_user_regs_struct { + long uregs[18]; +}; +#define ARM_cpsr uregs[16] +#define ARM_pc uregs[15] +#define ARM_lr uregs[14] +#define ARM_sp uregs[13] +#define ARM_ip uregs[12] +#define ARM_fp uregs[11] +#define ARM_r10 uregs[10] +#define ARM_r9 uregs[9] +#define ARM_r8 uregs[8] +#define ARM_r7 uregs[7] +#define ARM_r6 uregs[6] +#define ARM_r5 uregs[5] +#define ARM_r4 uregs[4] +#define ARM_r3 uregs[3] +#define ARM_r2 uregs[2] +#define ARM_r1 uregs[1] +#define ARM_r0 uregs[0] +#define ARM_ORIG_r0 uregs[17] +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/elf.h +//---------------------------------------------------------------------- + +typedef unsigned long vki_elf_greg_t; + +#define VKI_ELF_NGREG (sizeof (struct vki_user_regs_struct) / sizeof(vki_elf_greg_t)) +typedef vki_elf_greg_t vki_elf_gregset_t[VKI_ELF_NGREG]; + +typedef struct vki_user_i387_struct vki_elf_fpregset_t; +typedef struct vki_user_fxsr_struct vki_elf_fpxregset_t; + +#define VKI_AT_SYSINFO 32 + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/ucontext.h +//---------------------------------------------------------------------- + +struct vki_ucontext { + unsigned long uc_flags; + struct vki_ucontext *uc_link; + vki_stack_t uc_stack; + struct vki_sigcontext uc_mcontext; + vki_sigset_t uc_sigmask; /* mask last for extensibility */ + int __unused[32 - (sizeof (vki_sigset_t) / sizeof (int))]; + unsigned long uc_regspace[128] __attribute__((__aligned__(8))); + +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/segment.h +//---------------------------------------------------------------------- + +#define VKI_GDT_ENTRY_TLS_ENTRIES 3 +#define VKI_GDT_ENTRY_TLS_MIN 6 +#define VKI_GDT_ENTRY_TLS_MAX (VKI_GDT_ENTRY_TLS_MIN + VKI_GDT_ENTRY_TLS_ENTRIES - 1) + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/ldt.h +//---------------------------------------------------------------------- + +/* [[Nb: This is the structure passed to the modify_ldt syscall. Just so as + to confuse and annoy everyone, this is _not_ the same as an + VgLdtEntry and has to be translated into such. The logic for doing + so, in vg_ldt.c, is copied from the kernel sources.]] */ +struct vki_user_desc { + unsigned int entry_number; + unsigned long base_addr; + unsigned int limit; + unsigned int seg_32bit:1; + unsigned int contents:2; + unsigned int read_exec_only:1; + unsigned int limit_in_pages:1; + unsigned int seg_not_present:1; + unsigned int useable:1; + // [[Nb: this field is not in the kernel sources, but it has always + // been in the Valgrind sources so I will keep it there in case it's + // important... this is an x86-defined data structure so who + // knows; maybe it's important to set this field to zero at some + // point. --njn]] + unsigned int reserved:25; +}; + +// [[Nb: for our convenience within Valgrind, use a more specific name]] +typedef struct vki_user_desc vki_modify_ldt_t; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/ipcbuf.h +//---------------------------------------------------------------------- + +struct vki_ipc64_perm +{ + __vki_kernel_key_t key; + __vki_kernel_uid32_t uid; + __vki_kernel_gid32_t gid; + __vki_kernel_uid32_t cuid; + __vki_kernel_gid32_t cgid; + __vki_kernel_mode_t mode; + unsigned short __pad1; + unsigned short seq; + unsigned short __pad2; + unsigned long __unused1; + unsigned long __unused2; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/sembuf.h +//---------------------------------------------------------------------- + +struct vki_semid64_ds { + struct vki_ipc64_perm sem_perm; /* permissions .. see ipc.h */ + __vki_kernel_time_t sem_otime; /* last semop time */ + unsigned long __unused1; + __vki_kernel_time_t sem_ctime; /* last change time */ + unsigned long __unused2; + unsigned long sem_nsems; /* no. of semaphores in array */ + unsigned long __unused3; + unsigned long __unused4; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/msgbuf.h +//---------------------------------------------------------------------- + +struct vki_msqid64_ds { + struct vki_ipc64_perm msg_perm; + __vki_kernel_time_t msg_stime; /* last msgsnd time */ + unsigned long __unused1; + __vki_kernel_time_t msg_rtime; /* last msgrcv time */ + unsigned long __unused2; + __vki_kernel_time_t msg_ctime; /* last change time */ + unsigned long __unused3; + unsigned long msg_cbytes; /* current number of bytes on queue */ + unsigned long msg_qnum; /* number of messages in queue */ + unsigned long msg_qbytes; /* max number of bytes on queue */ + __vki_kernel_pid_t msg_lspid; /* pid of last msgsnd */ + __vki_kernel_pid_t msg_lrpid; /* last receive pid */ + unsigned long __unused4; + unsigned long __unused5; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/ipc.h +//---------------------------------------------------------------------- + +struct vki_ipc_kludge { + struct vki_msgbuf __user *msgp; + long msgtyp; +}; + +#define VKI_SEMOP 1 +#define VKI_SEMGET 2 +#define VKI_SEMCTL 3 +#define VKI_SEMTIMEDOP 4 +#define VKI_MSGSND 11 +#define VKI_MSGRCV 12 +#define VKI_MSGGET 13 +#define VKI_MSGCTL 14 +#define VKI_SHMAT 21 +#define VKI_SHMDT 22 +#define VKI_SHMGET 23 +#define VKI_SHMCTL 24 + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/shmbuf.h +//---------------------------------------------------------------------- + +struct vki_shmid64_ds { + struct vki_ipc64_perm shm_perm; /* operation perms */ + vki_size_t shm_segsz; /* size of segment (bytes) */ + __vki_kernel_time_t shm_atime; /* last attach time */ + unsigned long __unused1; + __vki_kernel_time_t shm_dtime; /* last detach time */ + unsigned long __unused2; + __vki_kernel_time_t shm_ctime; /* last change time */ + unsigned long __unused3; + __vki_kernel_pid_t shm_cpid; /* pid of creator */ + __vki_kernel_pid_t shm_lpid; /* pid of last operator */ + unsigned long shm_nattch; /* no. of current attaches */ + unsigned long __unused4; + unsigned long __unused5; +}; + +struct vki_shminfo64 { + unsigned long shmmax; + unsigned long shmmin; + unsigned long shmmni; + unsigned long shmseg; + unsigned long shmall; + unsigned long __unused1; + unsigned long __unused2; + unsigned long __unused3; + unsigned long __unused4; +}; + +//---------------------------------------------------------------------- +// DRM ioctls +//---------------------------------------------------------------------- + +// jrs 20050207: where did all this stuff come from? Is it really +// i386 specific, or should it go into the linux-generic category? +//struct vki_drm_buf_pub { +// Int idx; /**< Index into the master buffer list */ +// Int total; /**< Buffer size */ +// Int used; /**< Amount of buffer in use (for DMA) */ +// void __user *address; /**< Address of buffer */ +//}; +// +//struct vki_drm_buf_map { +// Int count; /**< Length of the buffer list */ +// void __user *virtual; /**< Mmap'd area in user-virtual */ +// struct vki_drm_buf_pub __user *list; /**< Buffer information */ +//}; +// +///* We need to pay attention to this, because it mmaps memory */ +//#define VKI_DRM_IOCTL_MAP_BUFS _VKI_IOWR('d', 0x19, struct vki_drm_buf_map) + +//---------------------------------------------------------------------- +// From linux-2.6.9/include/asm-i386/ptrace.h +//---------------------------------------------------------------------- + +#define VKI_PTRACE_GETREGS 12 +#define VKI_PTRACE_SETREGS 13 +#define VKI_PTRACE_GETFPREGS 14 +#define VKI_PTRACE_SETFPREGS 15 +#define VKI_PTRACE_GETFPXREGS 18 +#define VKI_PTRACE_SETFPXREGS 19 + +//---------------------------------------------------------------------- +// From linux-2.6.15.4/include/asm-i386/vm86.h +//---------------------------------------------------------------------- + +#define VKI_VM86_PLUS_INSTALL_CHECK 0 +#define VKI_VM86_ENTER 1 +#define VKI_VM86_ENTER_NO_BYPASS 2 +#define VKI_VM86_REQUEST_IRQ 3 +#define VKI_VM86_FREE_IRQ 4 +#define VKI_VM86_GET_IRQ_BITS 5 +#define VKI_VM86_GET_AND_RESET_IRQ 6 + +struct vki_vm86_regs { +/* + * normal regs, with special meaning for the segment descriptors.. + */ + long ebx; + long ecx; + long edx; + long esi; + long edi; + long ebp; + long eax; + long __null_ds; + long __null_es; + long __null_fs; + long __null_gs; + long orig_eax; + long eip; + unsigned short cs, __csh; + long eflags; + long esp; + unsigned short ss, __ssh; +/* + * these are specific to v86 mode: + */ + unsigned short es, __esh; + unsigned short ds, __dsh; + unsigned short fs, __fsh; + unsigned short gs, __gsh; +}; + +struct vki_revectored_struct { + unsigned long __map[8]; /* 256 bits */ +}; + +struct vki_vm86_struct { + struct vki_vm86_regs regs; + unsigned long flags; + unsigned long screen_bitmap; + unsigned long cpu_type; + struct vki_revectored_struct int_revectored; + struct vki_revectored_struct int21_revectored; +}; + +struct vki_vm86plus_info_struct { + unsigned long force_return_for_pic:1; + unsigned long vm86dbg_active:1; /* for debugger */ + unsigned long vm86dbg_TFpendig:1; /* for debugger */ + unsigned long unused:28; + unsigned long is_vm86pus:1; /* for vm86 internal use */ + unsigned char vm86dbg_intxxtab[32]; /* for debugger */ +}; + +struct vki_vm86plus_struct { + struct vki_vm86_regs regs; + unsigned long flags; + unsigned long screen_bitmap; + unsigned long cpu_type; + struct vki_revectored_struct int_revectored; + struct vki_revectored_struct int21_revectored; + struct vki_vm86plus_info_struct vm86plus; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.35.4/arch/arm/include/asm/hwcap.h +//---------------------------------------------------------------------- + +#define VKI_HWCAP_NEON 4096 + +//---------------------------------------------------------------------- +// And that's it! +//---------------------------------------------------------------------- + +#endif // __VKI_ARM_LINUX_H + +/*--------------------------------------------------------------------*/ +/*--- end vki-arm-linux.h ---*/ +/*--------------------------------------------------------------------*/ diff --git a/include/vki/vki-darwin.h b/include/vki/vki-darwin.h index b586887..e4d28d7 100644 --- a/include/vki/vki-darwin.h +++ b/include/vki/vki-darwin.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2007-2009 Apple Inc. + Copyright (C) 2007-2010 Apple Inc. Greg Parker gparker@apple.com This program is free software; you can redistribute it and/or @@ -706,6 +706,7 @@ typedef #define VKI_SHM_RDONLY SHM_RDONLY #define VKI_SHM_RND SHM_RND +#define VKI_SHMLBA SHMLBA #define vki_shmid_ds shmid_ds @@ -792,6 +793,11 @@ typedef typedef struct eventreq vki_eventreq; +#include + +#define vki_kauth_filesec kauth_filesec + + #include #define VKI_PTRACE_TRACEME PT_TRACE_ME @@ -1021,6 +1027,10 @@ struct ByteRangeLockPB2 #define VKI_A_GETPINFO_ADDR A_GETPINFO_ADDR #define VKI_A_GETKAUDIT A_GETKAUDIT #define VKI_A_SETKAUDIT A_SETKAUDIT +#if DARWIN_VERS >= DARWIN_10_6 +#define VKI_A_SENDTRIGGER A_SENDTRIGGER +#define VKI_A_GETSINFO_ADDR A_GETSINFO_ADDR +#endif #include diff --git a/include/vki/vki-linux.h b/include/vki/vki-linux.h index 90bffe6..537f0e0 100644 --- a/include/vki/vki-linux.h +++ b/include/vki/vki-linux.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -87,10 +87,40 @@ # include "vki-posixtypes-ppc32-linux.h" #elif defined(VGA_ppc64) # include "vki-posixtypes-ppc64-linux.h" +#elif defined(VGA_arm) +# include "vki-posixtypes-arm-linux.h" #else # error Unknown platform #endif +//---------------------------------------------------------------------- +// VKI_STATIC_ASSERT(). Inspired by BUILD_BUG_ON() from +// linux-2.6.34/include/linux/kernel.h +//---------------------------------------------------------------------- + +/* + * Evaluates to zero if 'expr' is true and forces a compilation error if + * 'expr' is false. Can be used in a context where no comma expressions + * are allowed. + */ +#ifdef __cplusplus +template struct vki_static_assert { int m_bitfield:(2*b-1); }; +#define VKI_STATIC_ASSERT(expr) \ + (sizeof(vki_static_assert<(expr)>) - sizeof(int)) +#else +#define VKI_STATIC_ASSERT(expr) (sizeof(struct { int:-!(expr); })) +#endif + +//---------------------------------------------------------------------- +// Based on _IOC_TYPECHECK() from linux-2.6.34/asm-generic/ioctl.h +//---------------------------------------------------------------------- + +/* provoke compile error for invalid uses of size argument */ +#define _VKI_IOC_TYPECHECK(t) \ + (VKI_STATIC_ASSERT((sizeof(t) == sizeof(t[1]) \ + && sizeof(t) < (1 << _VKI_IOC_SIZEBITS))) \ + + sizeof(t)) + //---------------------------------------------------------------------- // From linux-2.6.8.1/include/linux/compiler.h //---------------------------------------------------------------------- @@ -169,6 +199,8 @@ typedef unsigned int vki_uint; # include "vki-ppc32-linux.h" #elif defined(VGA_ppc64) # include "vki-ppc64-linux.h" +#elif defined(VGA_arm) +# include "vki-arm-linux.h" #else # error Unknown platform #endif @@ -277,14 +309,17 @@ struct vki_timex { int :32; int :32; int :32; int :32; }; -//#define ADJ_OFFSET 0x0001 /* time offset */ -#define ADJ_FREQUENCY 0x0002 /* frequency offset */ -#define ADJ_MAXERROR 0x0004 /* maximum time error */ -#define ADJ_ESTERROR 0x0008 /* estimated time error */ -#define ADJ_STATUS 0x0010 /* clock status */ -#define ADJ_TIMECONST 0x0020 /* pll time constant */ -#define ADJ_TICK 0x4000 /* tick value */ -//#define ADJ_OFFSET_SINGLESHOT 0x8001 /* old-fashioned adjtime */ +#define VKI_ADJ_OFFSET 0x0001 /* time offset */ +#define VKI_ADJ_FREQUENCY 0x0002 /* frequency offset */ +#define VKI_ADJ_MAXERROR 0x0004 /* maximum time error */ +#define VKI_ADJ_ESTERROR 0x0008 /* estimated time error */ +#define VKI_ADJ_STATUS 0x0010 /* clock status */ +#define VKI_ADJ_TIMECONST 0x0020 /* pll time constant */ +#define VKI_ADJ_TAI 0x0080 /* set TAI offset */ +#define VKI_ADJ_TICK 0x4000 /* tick value */ +#define VKI_ADJ_ADJTIME 0x8000 /* switch between adjtime/adjtimex modes */ +//#define VKI_ADJ_OFFSET_SINGLESHOT 0x8001 /* old-fashioned adjtime */ +#define VKI_ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */ //---------------------------------------------------------------------- // From linux-2.6.8.1/include/linux/times.h @@ -525,6 +560,7 @@ typedef struct vki_sigevent { #define VKI_SYS_GETSOCKOPT 15 /* sys_getsockopt(2) */ #define VKI_SYS_SENDMSG 16 /* sys_sendmsg(2) */ #define VKI_SYS_RECVMSG 17 /* sys_recvmsg(2) */ +#define VKI_SYS_ACCEPT4 18 /* sys_accept4(2) */ enum vki_sock_type { VKI_SOCK_STREAM = 1, @@ -1260,10 +1296,17 @@ struct vki_dirent { // From linux-2.6.8.1/include/linux/fcntl.h //---------------------------------------------------------------------- -#define VKI_F_SETLEASE (VKI_F_LINUX_SPECIFIC_BASE+0) -#define VKI_F_GETLEASE (VKI_F_LINUX_SPECIFIC_BASE+1) +#define VKI_F_SETLEASE (VKI_F_LINUX_SPECIFIC_BASE + 0) +#define VKI_F_GETLEASE (VKI_F_LINUX_SPECIFIC_BASE + 1) + +#define VKI_F_CANCELLK (VKI_F_LINUX_SPECIFIC_BASE + 5) + +#define VKI_F_DUPFD_CLOEXEC (VKI_F_LINUX_SPECIFIC_BASE + 6) -#define VKI_F_NOTIFY (VKI_F_LINUX_SPECIFIC_BASE+2) +#define VKI_F_NOTIFY (VKI_F_LINUX_SPECIFIC_BASE + 2) + +#define VKI_F_SETPIPE_SZ (VKI_F_LINUX_SPECIFIC_BASE + 7) +#define VKI_F_GETPIPE_SZ (VKI_F_LINUX_SPECIFIC_BASE + 8) //---------------------------------------------------------------------- // From linux-2.6.8.1/include/linux/sysctl.h @@ -1288,6 +1331,10 @@ typedef unsigned long vki_aio_context_t; enum { VKI_IOCB_CMD_PREAD = 0, VKI_IOCB_CMD_PWRITE = 1, + VKI_IOCB_CMD_FSYNC = 2, + VKI_IOCB_CMD_FDSYNC = 3, + VKI_IOCB_CMD_PREADV = 7, + VKI_IOCB_CMD_PWRITEV = 8, }; /* read() from /dev/aio returns these structures. */ @@ -1404,6 +1451,7 @@ struct vki_shmid_ds { }; #define VKI_SHM_RDONLY 010000 /* read-only access */ +#define VKI_SHM_RND 020000 /* round attach address to SHMLBA boundary */ #define VKI_SHM_STAT 13 #define VKI_SHM_INFO 14 @@ -1856,6 +1904,7 @@ struct vki_cdrom_generic_command #define VKI_SNDCTL_DSP_SETFRAGMENT _VKI_SIOWR('P',10, int) #define VKI_SNDCTL_DSP_GETFMTS _VKI_SIOR ('P',11, int) /* Returns a mask */ +#define VKI_SNDCTL_DSP_SETFMT _VKI_SIOWR('P', 5, int) /* Selects ONE fmt */ typedef struct vki_audio_buf_info { int fragments; /* # of available fragments (partially usend ones not counted) */ @@ -2570,6 +2619,103 @@ struct vki_iwreq union vki_iwreq_data u; }; +/*--------------------------------------------------------------------*/ +// From linux-2.6.31.5/include/linux/perf_counter.h +/*--------------------------------------------------------------------*/ + +struct vki_perf_counter_attr { + + /* + * Major type: hardware/software/tracepoint/etc. + */ + __vki_u32 type; + + /* + * Size of the attr structure, for fwd/bwd compat. + */ + __vki_u32 size; + + /* + * Type specific configuration information. + */ + __vki_u64 config; + + union { + __vki_u64 sample_period; + __vki_u64 sample_freq; + }; + + __vki_u64 sample_type; + __vki_u64 read_format; + + __vki_u64 disabled : 1, /* off by default */ + inherit : 1, /* children inherit it */ + pinned : 1, /* must always be on PMU */ + exclusive : 1, /* only group on PMU */ + exclude_user : 1, /* don't count user */ + exclude_kernel : 1, /* ditto kernel */ + exclude_hv : 1, /* ditto hypervisor */ + exclude_idle : 1, /* don't count when idle */ + mmap : 1, /* include mmap data */ + comm : 1, /* include comm data */ + freq : 1, /* use freq, not period */ + inherit_stat : 1, /* per task counts */ + enable_on_exec : 1, /* next exec enables */ + task : 1, /* trace fork/exit */ + + __reserved_1 : 50; + + __vki_u32 wakeup_events; /* wakeup every n events */ + __vki_u32 __reserved_2; + + __vki_u64 __reserved_3; +}; + +/*--------------------------------------------------------------------*/ +// From linux-2.6.32.4/include/linux/getcpu.h +/*--------------------------------------------------------------------*/ + +struct vki_getcpu_cache { + unsigned long blob[128 / sizeof(long)]; +}; + +//---------------------------------------------------------------------- +// From linux-2.6.33.3/include/linux/input.h +//---------------------------------------------------------------------- + +/* + * IOCTLs (0x00 - 0x7f) + */ + +#define VKI_EVIOCGNAME(len) _VKI_IOC(_VKI_IOC_READ, 'E', 0x06, len) /* get device name */ +#define VKI_EVIOCGPHYS(len) _VKI_IOC(_VKI_IOC_READ, 'E', 0x07, len) /* get physical location */ +#define VKI_EVIOCGUNIQ(len) _VKI_IOC(_VKI_IOC_READ, 'E', 0x08, len) /* get unique identifier */ + +#define VKI_EVIOCGKEY(len) _VKI_IOC(_VKI_IOC_READ, 'E', 0x18, len) /* get global keystate */ +#define VKI_EVIOCGLED(len) _VKI_IOC(_VKI_IOC_READ, 'E', 0x19, len) /* get all LEDs */ +#define VKI_EVIOCGSND(len) _VKI_IOC(_VKI_IOC_READ, 'E', 0x1a, len) /* get all sounds status */ +#define VKI_EVIOCGSW(len) _VKI_IOC(_VKI_IOC_READ, 'E', 0x1b, len) /* get all switch states */ + +#define VKI_EVIOCGBIT(ev,len) _VKI_IOC(_VKI_IOC_READ, 'E', 0x20 + ev, len) /* get event bits */ + +/* + * Event types + */ + +#define VKI_EV_SYN 0x00 +#define VKI_EV_KEY 0x01 +#define VKI_EV_REL 0x02 +#define VKI_EV_ABS 0x03 +#define VKI_EV_MSC 0x04 +#define VKI_EV_SW 0x05 +#define VKI_EV_LED 0x11 +#define VKI_EV_SND 0x12 +#define VKI_EV_REP 0x14 +#define VKI_EV_FF 0x15 +#define VKI_EV_PWR 0x16 +#define VKI_EV_FF_STATUS 0x17 +#define VKI_EV_MAX 0x1f +#define VKI_EV_CNT (VKI_EV_MAX+1) #endif // __VKI_LINUX_H diff --git a/include/vki/vki-posixtypes-amd64-linux.h b/include/vki/vki-posixtypes-amd64-linux.h index f3f9bb0..1862410 100644 --- a/include/vki/vki-posixtypes-amd64-linux.h +++ b/include/vki/vki-posixtypes-amd64-linux.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/vki/vki-posixtypes-arm-linux.h b/include/vki/vki-posixtypes-arm-linux.h new file mode 100644 index 0000000..043dbad --- /dev/null +++ b/include/vki/vki-posixtypes-arm-linux.h @@ -0,0 +1,68 @@ + +/*--------------------------------------------------------------------*/ +/*--- arm/Linux-specific kernel interface: posix types. ---*/ +/*--- vki-posixtypes-arm-linux.h ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2000-2010 Julian Seward + jseward@acm.org + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#ifndef __VKI_POSIXTYPES_ARM_LINUX_H +#define __VKI_POSIXTYPES_ARM_LINUX_H + +//---------------------------------------------------------------------- +// From linux-2.6.8.1/include/asm-i386/posix_types.h +//---------------------------------------------------------------------- + +typedef unsigned short __vki_kernel_mode_t; +typedef long __vki_kernel_off_t; +typedef int __vki_kernel_pid_t; +typedef unsigned short __vki_kernel_ipc_pid_t; +typedef unsigned short __vki_kernel_uid_t; +typedef unsigned short __vki_kernel_gid_t; +typedef unsigned int __vki_kernel_size_t; +typedef long __vki_kernel_time_t; +typedef long __vki_kernel_suseconds_t; +typedef long __vki_kernel_clock_t; +typedef int __vki_kernel_timer_t; +typedef int __vki_kernel_clockid_t; +typedef char * __vki_kernel_caddr_t; +typedef unsigned int __vki_kernel_uid32_t; +typedef unsigned int __vki_kernel_gid32_t; + +typedef unsigned short __vki_kernel_old_uid_t; +typedef unsigned short __vki_kernel_old_gid_t; + +typedef long long __vki_kernel_loff_t; + +typedef struct { + int val[2]; +} __vki_kernel_fsid_t; + +#endif // __VKI_POSIXTYPES_ARM_LINUX_H + +/*--------------------------------------------------------------------*/ +/*--- end vki-posixtypes-arm-linux.h ---*/ +/*--------------------------------------------------------------------*/ diff --git a/include/vki/vki-posixtypes-ppc32-linux.h b/include/vki/vki-posixtypes-ppc32-linux.h index 5cf1b2c..6ab8e6e 100644 --- a/include/vki/vki-posixtypes-ppc32-linux.h +++ b/include/vki/vki-posixtypes-ppc32-linux.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Julian Seward + Copyright (C) 2005-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/vki/vki-posixtypes-ppc64-linux.h b/include/vki/vki-posixtypes-ppc64-linux.h index 28cf4c7..3b0a91d 100644 --- a/include/vki/vki-posixtypes-ppc64-linux.h +++ b/include/vki/vki-posixtypes-ppc64-linux.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Julian Seward + Copyright (C) 2005-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/vki/vki-posixtypes-x86-linux.h b/include/vki/vki-posixtypes-x86-linux.h index 39fc88d..42b2bf0 100644 --- a/include/vki/vki-posixtypes-x86-linux.h +++ b/include/vki/vki-posixtypes-x86-linux.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or diff --git a/include/vki/vki-ppc32-aix5.h b/include/vki/vki-ppc32-aix5.h index 0780d27..71ca550 100644 --- a/include/vki/vki-ppc32-aix5.h +++ b/include/vki/vki-ppc32-aix5.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/include/vki/vki-ppc32-linux.h b/include/vki/vki-ppc32-linux.h index 69932c0..6b44386 100644 --- a/include/vki/vki-ppc32-linux.h +++ b/include/vki/vki-ppc32-linux.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Julian Seward + Copyright (C) 2005-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -68,6 +68,12 @@ extern unsigned long VKI_PAGE_SIZE; #define VKI_MAX_PAGE_SHIFT 16 #define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) +//---------------------------------------------------------------------- +// From linux-2.6.35.4/arch/powerpc/include/asm/shmparam.h +//---------------------------------------------------------------------- + +#define VKI_SHMLBA VKI_PAGE_SIZE + //---------------------------------------------------------------------- // From linux-2.6.9/include/asm-ppc/signal.h //---------------------------------------------------------------------- @@ -515,13 +521,6 @@ struct vki_termios { ((nr) << _VKI_IOC_NRSHIFT) | \ ((size) << _VKI_IOC_SIZESHIFT)) -/* provoke compile error for invalid uses of size argument */ -extern unsigned int __VKI_invalid_size_argument_for_IOC; -#define _VKI_IOC_TYPECHECK(t) \ - ((sizeof(t) == sizeof(t[1]) && \ - sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) ? \ - sizeof(t) : __VKI_invalid_size_argument_for_IOC) - /* used to create numbers */ #define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0) #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size))) diff --git a/include/vki/vki-ppc64-aix5.h b/include/vki/vki-ppc64-aix5.h index 0e3e73f..092d92c 100644 --- a/include/vki/vki-ppc64-aix5.h +++ b/include/vki/vki-ppc64-aix5.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/include/vki/vki-ppc64-linux.h b/include/vki/vki-ppc64-linux.h index 610a163..5af8470 100644 --- a/include/vki/vki-ppc64-linux.h +++ b/include/vki/vki-ppc64-linux.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Julian Seward + Copyright (C) 2005-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -69,6 +69,12 @@ extern unsigned long VKI_PAGE_SIZE; #define VKI_MAX_PAGE_SHIFT 16 #define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) +//---------------------------------------------------------------------- +// From linux-2.6.35.4/arch/powerpc/include/asm/shmparam.h +//---------------------------------------------------------------------- + +#define VKI_SHMLBA VKI_PAGE_SIZE + //---------------------------------------------------------------------- // From linux-2.6.13/include/asm-ppc64/signal.h //---------------------------------------------------------------------- @@ -558,13 +564,6 @@ struct vki_termios { ((nr) << _VKI_IOC_NRSHIFT) | \ ((size) << _VKI_IOC_SIZESHIFT)) -/* provoke compile error for invalid uses of size argument */ -extern unsigned int __invalid_size_argument_for_IOC; -#define _VKI_IOC_TYPECHECK(t) \ - ((sizeof(t) == sizeof(t[1]) && \ - sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) ? \ - sizeof(t) : __invalid_size_argument_for_IOC) - /* used to create numbers */ #define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0) #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr), \ diff --git a/include/vki/vki-scnums-aix5.h b/include/vki/vki-scnums-aix5.h index 11397ff..3ca8ebf 100644 --- a/include/vki/vki-scnums-aix5.h +++ b/include/vki/vki-scnums-aix5.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP + Copyright (C) 2006-2010 OpenWorks LLP info@open-works.co.uk This program is free software; you can redistribute it and/or diff --git a/include/vki/vki-scnums-amd64-linux.h b/include/vki/vki-scnums-amd64-linux.h index d4b3fd7..f891f94 100644 --- a/include/vki/vki-scnums-amd64-linux.h +++ b/include/vki/vki-scnums-amd64-linux.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -369,13 +369,17 @@ #define __NR_fallocate 285 #define __NR_timerfd_settime 286 #define __NR_timerfd_gettime 287 -#define __NR_paccept 288 +#define __NR_accept4 288 #define __NR_signalfd4 289 #define __NR_eventfd2 290 #define __NR_epoll_create1 291 #define __NR_dup3 292 #define __NR_pipe2 293 #define __NR_inotify_init1 294 +#define __NR_preadv 295 +#define __NR_pwritev 296 +#define __NR_rt_tgsigqueueinfo 297 +#define __NR_perf_counter_open 298 #endif /* __VKI_SCNUMS_AMD64_LINUX_H */ diff --git a/include/vki/vki-scnums-arm-linux.h b/include/vki/vki-scnums-arm-linux.h new file mode 100644 index 0000000..6300897 --- /dev/null +++ b/include/vki/vki-scnums-arm-linux.h @@ -0,0 +1,415 @@ + +/*--------------------------------------------------------------------*/ +/*--- System call numbers for arm-linux. ---*/ +/*--- vki-scnums-arm-linux.h ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2008-2010 Evan Geller + gaze@bea.ms + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#ifndef __VKI_SCNUMS_ARM_LINUX_H +#define __VKI_SCNUMS_ARM_LINUX_H + +// From linux-2.6.26.2/include/asm-arm/unistd.h + +#define __NR_restart_syscall 0 +#define __NR_exit 1 +#define __NR_fork 2 +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 + /* 7 was sys_waitpid */ +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_lchown 16 + /* 17 was sys_break */ + /* 18 was sys_stat */ +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 +#define __NR_umount 22 +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 + /* 28 was sys_fstat */ +#define __NR_pause 29 +#define __NR_utime 30 + /* 31 was sys_stty */ + /* 32 was sys_gtty */ +#define __NR_access 33 +#define __NR_nice 34 + /* 35 was sys_ftime */ +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 + /* 44 was sys_prof */ +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 + /* 48 was sys_signal */ +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 + /* 53 was sys_lock */ +#define __NR_ioctl 54 +#define __NR_fcntl 55 + /* 56 was sys_mpx */ +#define __NR_setpgid 57 + /* 58 was sys_ulimit */ + /* 59 was sys_olduname */ +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 +#define __NR_sigaction 67 + /* 68 was sys_sgetmask */ + /* 69 was sys_ssetmask */ +#define __NR_setreuid 70 +#define __NR_setregid 71 +#define __NR_sigsuspend 72 +#define __NR_sigpending 73 +#define __NR_sethostname 74 +#define __NR_setrlimit 75 +#define __NR_getrlimit 76 /* Back compat 2GB limited rlimit */ +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 +#define __NR_select 82 +#define __NR_symlink 83 + /* 84 was sys_lstat */ +#define __NR_readlink 85 +#define __NR_uselib 86 +#define __NR_swapon 87 +#define __NR_reboot 88 +#define __NR_readdir 89 +#define __NR_mmap 90 +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 + /* 98 was sys_profil */ +#define __NR_statfs 99 +#define __NR_fstatfs 100 + /* 101 was sys_ioperm */ +#define __NR_socketcall 102 +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 + /* 109 was sys_uname */ + /* 110 was sys_iopl */ +#define __NR_vhangup 111 + /* 112 was sys_idle */ +#define __NR_syscall 113 /* syscall to call a syscall! */ +#define __NR_wait4 114 +#define __NR_swapoff 115 +#define __NR_sysinfo 116 +#define __NR_ipc 117 +#define __NR_fsync 118 +#define __NR_sigreturn 119 +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 + /* 123 was sys_modify_ldt */ +#define __NR_adjtimex 124 +#define __NR_mprotect 125 +#define __NR_sigprocmask 126 + /* 127 was sys_create_module */ +#define __NR_init_module 128 +#define __NR_delete_module 129 + /* 130 was sys_get_kernel_syms */ +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 +#define __NR_sysfs 135 +#define __NR_personality 136 + /* 137 was sys_afs_syscall */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 +#define __NR__newselect 142 +#define __NR_flock 143 +#define __NR_msync 144 +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 +#define __NR_mlock 150 +#define __NR_munlock 151 +#define __NR_mlockall 152 +#define __NR_munlockall 153 +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 + /* 166 was sys_vm86 */ + /* 167 was sys_query_module */ +#define __NR_poll 168 +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread64 180 +#define __NR_pwrite64 181 +#define __NR_chown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 + /* 188 reserved */ + /* 189 reserved */ +#define __NR_vfork 190 +#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_lchown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_chown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_getdents64 217 +#define __NR_pivot_root 218 +#define __NR_mincore 219 +#define __NR_madvise 220 +#define __NR_fcntl64 221 + /* 222 for tux */ + /* 223 is unused */ +#define __NR_gettid 224 +#define __NR_readahead 225 +#define __NR_setxattr 226 +#define __NR_lsetxattr 227 +#define __NR_fsetxattr 228 +#define __NR_getxattr 229 +#define __NR_lgetxattr 230 +#define __NR_fgetxattr 231 +#define __NR_listxattr 232 +#define __NR_llistxattr 233 +#define __NR_flistxattr 234 +#define __NR_removexattr 235 +#define __NR_lremovexattr 236 +#define __NR_fremovexattr 237 +#define __NR_tkill 238 +#define __NR_sendfile64 239 +#define __NR_futex 240 +#define __NR_sched_setaffinity 241 +#define __NR_sched_getaffinity 242 +#define __NR_io_setup 243 +#define __NR_io_destroy 244 +#define __NR_io_getevents 245 +#define __NR_io_submit 246 +#define __NR_io_cancel 247 +#define __NR_exit_group 248 +#define __NR_lookup_dcookie 249 +#define __NR_epoll_create 250 +#define __NR_epoll_ctl 251 +#define __NR_epoll_wait 252 +#define __NR_remap_file_pages 253 + /* 254 for set_thread_area */ + /* 255 for get_thread_area */ +#define __NR_set_tid_address 256 +#define __NR_timer_create 257 +#define __NR_timer_settime 258 +#define __NR_timer_gettime 259 +#define __NR_timer_getoverrun 260 +#define __NR_timer_delete 261 +#define __NR_clock_settime 262 +#define __NR_clock_gettime 263 +#define __NR_clock_getres 264 +#define __NR_clock_nanosleep 265 +#define __NR_statfs64 266 +#define __NR_fstatfs64 267 +#define __NR_tgkill 268 +#define __NR_utimes 269 +#define __NR_arm_fadvise64_64 270 +#define __NR_fadvise64 270 //Added by Johan, 2008-10-11, not sure why it's called _arm_.. otherwise. +#define __NR_pciconfig_iobase 271 +#define __NR_pciconfig_read 272 +#define __NR_pciconfig_write 273 +#define __NR_mq_open 274 +#define __NR_mq_unlink 275 +#define __NR_mq_timedsend 276 +#define __NR_mq_timedreceive 277 +#define __NR_mq_notify 278 +#define __NR_mq_getsetattr 279 +#define __NR_waitid 280 +#define __NR_socket 281 +#define __NR_bind 282 +#define __NR_connect 283 +#define __NR_listen 284 +#define __NR_accept 285 +#define __NR_getsockname 286 +#define __NR_getpeername 287 +#define __NR_socketpair 288 +#define __NR_send 289 +#define __NR_sendto 290 +#define __NR_recv 291 +#define __NR_recvfrom 292 +#define __NR_shutdown 293 +#define __NR_setsockopt 294 +#define __NR_getsockopt 295 +#define __NR_sendmsg 296 +#define __NR_recvmsg 297 +#define __NR_semop 298 +#define __NR_semget 299 +#define __NR_semctl 300 +#define __NR_msgsnd 301 +#define __NR_msgrcv 302 +#define __NR_msgget 303 +#define __NR_msgctl 304 +#define __NR_shmat 305 +#define __NR_shmdt 306 +#define __NR_shmget 307 +#define __NR_shmctl 308 +#define __NR_add_key 309 +#define __NR_request_key 310 +#define __NR_keyctl 311 +#define __NR_semtimedop 312 +#define __NR_vserver 313 +#define __NR_ioprio_set 314 +#define __NR_ioprio_get 315 +#define __NR_inotify_init 316 +#define __NR_inotify_add_watch 317 +#define __NR_inotify_rm_watch 318 +#define __NR_mbind 319 +#define __NR_get_mempolicy 320 +#define __NR_set_mempolicy 321 +#define __NR_openat 322 +#define __NR_mkdirat 323 +#define __NR_mknodat 324 +#define __NR_fchownat 325 +#define __NR_futimesat 326 +#define __NR_fstatat64 327 +#define __NR_unlinkat 328 +#define __NR_renameat 329 +#define __NR_linkat 330 +#define __NR_symlinkat 331 +#define __NR_readlinkat 332 +#define __NR_fchmodat 333 +#define __NR_faccessat 334 +#define __NR_pselect6 335 /* JRS 20100812: is this correct? */ +#define __NR_ppoll 336 +#define __NR_unshare 337 +#define __NR_set_robust_list 338 +#define __NR_get_robust_list 339 +#define __NR_splice 340 +#define __NR_arm_sync_file_range 341 +#define __NR_sync_file_range2 __NR_arm_sync_file_range +#define __NR_tee 342 +#define __NR_vmsplice 343 +#define __NR_move_pages 344 +#define __NR_getcpu 345 + /* 346 for epoll_pwait */ +#define __NR_kexec_load 347 +#define __NR_utimensat 348 +#define __NR_signalfd 349 +#define __NR_timerfd_create 350 +#define __NR_eventfd 351 +#define __NR_fallocate 352 +#define __NR_timerfd_settime 353 +#define __NR_timerfd_gettime 354 +#define __NR_signalfd4 355 +#define __NR_eventfd2 356 +#define __NR_epoll_create1 357 +#define __NR_dup3 358 +#define __NR_pipe2 359 +#define __NR_inotify_init1 360 + + + +#define __NR_ARM_BASE (0x0f0000) +#define __NR_ARM_breakpoint (__NR_ARM_BASE+1) +#define __NR_ARM_cacheflush (__NR_ARM_BASE+2) +#define __NR_ARM_usr26 (__NR_ARM_BASE+3) +#define __NR_ARM_usr32 (__NR_ARM_BASE+4) +#define __NR_ARM_set_tls (__NR_ARM_BASE+5) + + +#endif /* __VKI_SCNUMS_ARM_LINUX_H */ + +/*--------------------------------------------------------------------*/ +/*--- end vki-scnums-arm-linux.h ---*/ +/*--------------------------------------------------------------------*/ diff --git a/include/vki/vki-scnums-darwin.h b/include/vki/vki-scnums-darwin.h index 2af0f30..f39f28e 100644 --- a/include/vki/vki-scnums-darwin.h +++ b/include/vki/vki-scnums-darwin.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2007-2009 Apple Inc. + Copyright (C) 2007-2010 Apple Inc. Greg Parker gparker@apple.com This program is free software; you can redistribute it and/or @@ -32,6 +32,9 @@ #define __VKI_SCNUMS_DARWIN_H +// need DARWIN_10_x definitions +#include "config.h" + // osfmk/mach/i386/syscall_sw.h // There are two syscall number encodings in Darwin. @@ -376,7 +379,11 @@ #define __NR_sigreturn VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(184) #define __NR_chud VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(185) /* 186 */ +#if DARWIN_VERS >= DARWIN_10_6 +#define __NR_fdatasync VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(187) +#else /* 187 */ +#endif #define __NR_stat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(188) #define __NR_fstat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(189) #define __NR_lstat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(190) @@ -403,8 +410,13 @@ #define __NR_ATPgetreq VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(211) #define __NR_ATPgetrsp VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(212) /* 213 Reserved for AppleTalk */ -#define __NR_kqueue_from_portset_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(214) -#define __NR_kqueue_portset_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(215) +#if DARWIN_VERS >= DARWIN_10_6 + /* 214 old kqueue_from_portset_np*/ + /* 215 old kqueue_portset_np*/ +#else +#define __NR_kqueue_from_portset_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(214) +#define __NR_kqueue_portset_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(215) +#endif #define __NR_mkcomplex VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(216) #define __NR_statv VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(217) #define __NR_lstatv VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(218) @@ -413,12 +425,17 @@ #define __NR_setattrlist VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(221) #define __NR_getdirentriesattr VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(222) #define __NR_exchangedata VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(223) - /* 224 checkuseraccess */ + /* 224 old checkuseraccess */ #define __NR_searchfs VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(225) #define __NR_delete VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(226) #define __NR_copyfile VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(227) +#if DARWIN_VERS >= DARWIN_10_6 +#define __NR_fgetattrlist VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(228) +#define __NR_fsetattrlist VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(229) +#else /* 228 */ /* 229 */ +#endif #define __NR_poll VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(230) #define __NR_watchevent VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(231) #define __NR_waitevent VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(232) @@ -434,7 +451,11 @@ #define __NR_fsctl VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(242) #define __NR_initgroups VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(243) #define __NR_posix_spawn VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(244) +#if DARWIN_VERS >= DARWIN_10_6 +#define __NR_ffsctl VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(245) +#else /* 245 */ +#endif /* 246 */ #define __NR_nfsclnt VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(247) #define __NR_fhopen VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(248) @@ -485,23 +506,27 @@ #define __NR_identitysvc VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(293) #define __NR_shared_region_check_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(294) #define __NR_shared_region_map_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(295) +#if DARWIN_VERS >= DARWIN_10_6 +#define __NR_vm_pressure_monitor VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(296) +#else /* 296 old load_shared_file */ +#endif /* 297 old reset_shared_file */ /* 298 old new_system_shared_regions */ /* 299 old shared_region_map_file_np */ /* 300 old shared_region_make_private_np */ -#define __NR___pthread_mutex_destroy VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(301) -#define __NR___pthread_mutex_init VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(302) -#define __NR___pthread_mutex_lock VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(303) -#define __NR___pthread_mutex_trylock VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(304) -#define __NR___pthread_mutex_unlock VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(305) -#define __NR___pthread_cond_init VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(306) -#define __NR___pthread_cond_destroy VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(307) -#define __NR___pthread_cond_broadcast VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(308) -#define __NR___pthread_cond_signal VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(309) + /* 301 */ + /* 302 */ + /* 303 */ + /* 304 */ + /* 305 */ + /* 306 */ + /* 307 */ + /* 308 */ + /* 309 */ #define __NR_getsid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(310) #define __NR_settid_with_pid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(311) -#define __NR___pthread_cond_timedwait VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(312) + /* 312 */ #define __NR_aio_fsync VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(313) #define __NR_aio_return VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(314) #define __NR_aio_suspend VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(315) @@ -510,7 +535,7 @@ #define __NR_aio_read VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(318) #define __NR_aio_write VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(319) #define __NR_lio_listio VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(320) -#define __NR___pthread_cond_wait VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(321) + /* 321 */ #define __NR_iopolicysys VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(322) /* 323 */ #define __NR_mlockall VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(324) @@ -559,10 +584,18 @@ #define __NR_bsdthread_register VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(366) #define __NR_workq_open VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(367) #define __NR_workq_ops VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(368) +#if DARWIN_VERS >= DARWIN_10_6 +#define __NR_kevent64 VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(369) +#else /* 369 */ +#endif /* 370 */ /* 371 */ +#if DARWIN_VERS >= DARWIN_10_6 +#define __NR___thread_selfid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(372) // was UX64 +#else /* 372 */ +#endif /* 373 */ /* 374 */ /* 375 */ @@ -617,7 +650,19 @@ #define __NR___mac_mount VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(424) #define __NR___mac_get_mount VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(425) #define __NR___mac_getfsstat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(426) +#if DARWIN_VERS >= DARWIN_10_6 +#define __NR_fsgetpath VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(427) +#define __NR_audit_session_self VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(428) +#define __NR_audit_session_join VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(429) +#endif + +#if DARWIN_VERS < DARWIN_10_6 #define __NR_MAXSYSCALL VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(427) +#elif DARWIN_VERSION < DARWIN_10_7 +#define __NR_MAXSYSCALL VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(430) +#else +#error unknown darwin version +#endif #define __NR_DARWIN_FAKE_SIGRETURN (1 + __NR_MAXSYSCALL) diff --git a/include/vki/vki-scnums-ppc32-linux.h b/include/vki/vki-scnums-ppc32-linux.h index 7ae5b23..2235653 100644 --- a/include/vki/vki-scnums-ppc32-linux.h +++ b/include/vki/vki-scnums-ppc32-linux.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Julian Seward + Copyright (C) 2005-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -361,6 +361,10 @@ #define __NR_dup3 316 #define __NR_pipe2 317 #define __NR_inotify_init1 318 +#define __NR_perf_counter_open 319 +#define __NR_preadv 320 +#define __NR_pwritev 321 +#define __NR_rt_tgsigqueueinfo 322 #endif /* __VKI_SCNUMS_PPC32_LINUX_H */ diff --git a/include/vki/vki-scnums-ppc64-linux.h b/include/vki/vki-scnums-ppc64-linux.h index 1123a4e..e019e6f 100644 --- a/include/vki/vki-scnums-ppc64-linux.h +++ b/include/vki/vki-scnums-ppc64-linux.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2005-2009 Julian Seward + Copyright (C) 2005-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -353,6 +353,10 @@ #define __NR_dup3 316 #define __NR_pipe2 317 #define __NR_inotify_init1 318 +#define __NR_perf_counter_open 319 +#define __NR_preadv 320 +#define __NR_pwritev 321 +#define __NR_rt_tgsigqueueinfo 322 #endif /* __VKI_SCNUMS_PPC64_LINUX_H */ diff --git a/include/vki/vki-scnums-x86-linux.h b/include/vki/vki-scnums-x86-linux.h index 165b07e..f194277 100644 --- a/include/vki/vki-scnums-x86-linux.h +++ b/include/vki/vki-scnums-x86-linux.h @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -367,6 +367,10 @@ #define __NR_dup3 330 #define __NR_pipe2 331 #define __NR_inotify_init1 332 +#define __NR_preadv 333 +#define __NR_pwritev 334 +#define __NR_rt_tgsigqueueinfo 335 +#define __NR_perf_counter_open 336 #endif /* __VKI_SCNUMS_X86_LINUX_H */ diff --git a/include/vki/vki-x86-linux.h b/include/vki/vki-x86-linux.h index 08aed50..8f8aec8 100644 --- a/include/vki/vki-x86-linux.h +++ b/include/vki/vki-x86-linux.h @@ -7,7 +7,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -63,6 +63,12 @@ typedef unsigned int vki_u32; #define VKI_MAX_PAGE_SHIFT VKI_PAGE_SHIFT #define VKI_MAX_PAGE_SIZE VKI_PAGE_SIZE +//---------------------------------------------------------------------- +// From linux-2.6.35.4/arch/x86/include/asm/shmparam.h +//---------------------------------------------------------------------- + +#define VKI_SHMLBA VKI_PAGE_SIZE + //---------------------------------------------------------------------- // From linux-2.6.8.1/include/asm-i386/signal.h //---------------------------------------------------------------------- @@ -479,13 +485,6 @@ struct vki_termios { ((nr) << _VKI_IOC_NRSHIFT) | \ ((size) << _VKI_IOC_SIZESHIFT)) -/* provoke compile error for invalid uses of size argument */ -extern unsigned int __vki_invalid_size_argument_for_IOC; -#define _VKI_IOC_TYPECHECK(t) \ - ((sizeof(t) == sizeof(t[1]) && \ - sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) ? \ - sizeof(t) : __vki_invalid_size_argument_for_IOC) - /* used to create numbers */ #define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0) #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size))) diff --git a/lackey/Makefile.am b/lackey/Makefile.am index ef89d73..20b3467 100644 --- a/lackey/Makefile.am +++ b/lackey/Makefile.am @@ -13,7 +13,8 @@ endif LACKEY_SOURCES_COMMON = lk_main.c -lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(LACKEY_SOURCES_COMMON) +lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ + $(LACKEY_SOURCES_COMMON) lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \ @@ -24,8 +25,16 @@ lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC -lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(LACKEY_SOURCES_COMMON) +lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ + $(LACKEY_SOURCES_COMMON) lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \ @@ -36,4 +45,10 @@ lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif diff --git a/lackey/lk_main.c b/lackey/lk_main.c index d2110b6..35e3599 100644 --- a/lackey/lk_main.c +++ b/lackey/lk_main.c @@ -7,7 +7,7 @@ This file is part of Lackey, an example Valgrind tool that does some simple program measurement and tracing. - Copyright (C) 2002-2009 Nicholas Nethercote + Copyright (C) 2002-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -790,17 +790,50 @@ IRSB* lk_instrument ( VgCallbackClosure* closure, was introduced, since prior to that point, the Vex front ends would translate a lock-prefixed instruction into a (normal) read followed by a (normal) write. */ + Int dataSize; + IRType dataTy; + IRCAS* cas = st->Ist.CAS.details; + tl_assert(cas->addr != NULL); + tl_assert(cas->dataLo != NULL); + dataTy = typeOfIRExpr(tyenv, cas->dataLo); + dataSize = sizeofIRType(dataTy); + if (cas->dataHi != NULL) + dataSize *= 2; /* since it's a doubleword-CAS */ if (clo_trace_mem) { - Int dataSize; - IRCAS* cas = st->Ist.CAS.details; - tl_assert(cas->addr != NULL); - tl_assert(cas->dataLo != NULL); - dataSize = sizeofIRType(typeOfIRExpr(tyenv, cas->dataLo)); - if (cas->dataHi != NULL) - dataSize *= 2; /* since it's a doubleword-CAS */ addEvent_Dr( sbOut, cas->addr, dataSize ); addEvent_Dw( sbOut, cas->addr, dataSize ); } + if (clo_detailed_counts) { + instrument_detail( sbOut, OpLoad, dataTy ); + if (cas->dataHi != NULL) /* dcas */ + instrument_detail( sbOut, OpLoad, dataTy ); + instrument_detail( sbOut, OpStore, dataTy ); + if (cas->dataHi != NULL) /* dcas */ + instrument_detail( sbOut, OpStore, dataTy ); + } + addStmtToIRSB( sbOut, st ); + break; + } + + case Ist_LLSC: { + IRType dataTy; + if (st->Ist.LLSC.storedata == NULL) { + /* LL */ + dataTy = typeOfIRTemp(tyenv, st->Ist.LLSC.result); + if (clo_trace_mem) + addEvent_Dr( sbOut, st->Ist.LLSC.addr, + sizeofIRType(dataTy) ); + if (clo_detailed_counts) + instrument_detail( sbOut, OpLoad, dataTy ); + } else { + /* SC */ + dataTy = typeOfIRExpr(tyenv, st->Ist.LLSC.storedata); + if (clo_trace_mem) + addEvent_Dw( sbOut, st->Ist.LLSC.addr, + sizeofIRType(dataTy) ); + if (clo_detailed_counts) + instrument_detail( sbOut, OpStore, dataTy ); + } addStmtToIRSB( sbOut, st ); break; } @@ -821,7 +854,8 @@ IRSB* lk_instrument ( VgCallbackClosure* closure, mkIRExprVec_0() ); else di = unsafeIRDirty_0_N( 0, "add_one_inverted_Jcc", - VG_(fnptr_to_fnentry)( &add_one_inverted_Jcc ), + VG_(fnptr_to_fnentry)( + &add_one_inverted_Jcc ), mkIRExprVec_0() ); addStmtToIRSB( sbOut, IRStmt_Dirty(di) ); @@ -931,7 +965,7 @@ static void lk_pre_clo_init(void) VG_(details_version) (NULL); VG_(details_description) ("an example Valgrind tool"); VG_(details_copyright_author)( - "Copyright (C) 2002-2009, and GNU GPL'd, by Nicholas Nethercote."); + "Copyright (C) 2002-2010, and GNU GPL'd, by Nicholas Nethercote."); VG_(details_bug_reports_to) (VG_BUGS_TO); VG_(details_avg_translation_sizeB) ( 200 ); diff --git a/massif/Makefile.am b/massif/Makefile.am index 32c54dd..94bcd68 100644 --- a/massif/Makefile.am +++ b/massif/Makefile.am @@ -23,7 +23,8 @@ endif MASSIF_SOURCES_COMMON = ms_main.c -massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(MASSIF_SOURCES_COMMON) +massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ + $(MASSIF_SOURCES_COMMON) massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \ @@ -34,8 +35,16 @@ massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC -massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(MASSIF_SOURCES_COMMON) +massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ + $(MASSIF_SOURCES_COMMON) massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \ @@ -46,6 +55,12 @@ massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif #---------------------------------------------------------------------------- @@ -71,6 +86,7 @@ vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \ vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) + if VGCONF_HAVE_PLATFORM_SEC vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS = \ diff --git a/massif/docs/ms-manual.xml b/massif/docs/ms-manual.xml index b31435e..51f872b 100644 --- a/massif/docs/ms-manual.xml +++ b/massif/docs/ms-manual.xml @@ -545,11 +545,11 @@ file, which will almost certainly make it unreadable by ms_print. -Memory Allocations Not Measured by Massif + xreflabel="Measuring All Memory in a Process"> +Measuring All Memory in a Process -It is worth emphasising that Massif measures only heap memory, i.e. memory -allocated with +It is worth emphasising that by default Massif measures only heap memory, i.e. +memory allocated with malloc, calloc, realloc, @@ -576,13 +576,49 @@ not the lower-level system calls. Furthermore, a client program may use these lower-level system calls -directly to allocate memory. Massif does not measure these. Nor does it -measure the size of code, data and BSS segments. Therefore, the numbers -reported by Massif may be significantly smaller than those reported by tools -such as top that measure a program's total size in +directly to allocate memory. By default, Massif does not measure these. Nor +does it measure the size of code, data and BSS segments. Therefore, the +numbers reported by Massif may be significantly smaller than those reported by +tools such as top that measure a program's total size in memory. + +However, if you wish to measure all the memory used by +your program, you can use the . When this +option is enabled, Massif's normal heap block profiling is replaced by +lower-level page profiling. Every page allocated via +mmap and similar system calls is treated as a distinct +block. This means that code, data and BSS segments are all measured, as they +are just memory pages. Even the stack is measured, since it is ultimately +allocated (and extended when necessary) via mmap; for +this reason is not allowed in conjunction with +. + + + +After is used, ms_print's output is +mostly unchanged. One difference is that the start of each detailed snapshot +says: + + + + +instead of the usual: + + + + +The stack traces in the output may be more difficult to read, and interpreting +them may require some detailed understanding of the lower levels of a program +like the memory allocators. But for some programs having the full information +about memory usage can be very useful. + + @@ -640,7 +676,7 @@ in a particular column, which makes following the allocation chains easier. - + Specifies whether stack profiling should be done. This option @@ -652,6 +688,17 @@ in a particular column, which makes following the allocation chains easier. + + + + + + Tells Massif to profile memory at the page level rather + than at the malloc'd block level. See above for details. + + + + diff --git a/massif/ms_main.c b/massif/ms_main.c index ecfb31c..c34d27b 100644 --- a/massif/ms_main.c +++ b/massif/ms_main.c @@ -6,7 +6,7 @@ This file is part of Massif, a Valgrind tool for profiling memory usage of programs. - Copyright (C) 2003-2009 Nicholas Nethercote + Copyright (C) 2003-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -176,6 +176,7 @@ Number of snapshots: 50 #include "pub_tool_options.h" #include "pub_tool_replacemalloc.h" #include "pub_tool_stacktrace.h" +#include "pub_tool_threadstate.h" #include "pub_tool_tooliface.h" #include "pub_tool_xarray.h" #include "pub_tool_clientstate.h" @@ -190,6 +191,10 @@ Number of snapshots: 50 // of detail, enough to tell how many bytes each line of code is responsible // for, more or less. The main data structure is a tree representing the // call tree beneath all the allocation functions like malloc(). +// (Alternatively, if --pages-as-heap=yes is specified, memory is tracked at +// the page level, and each page is treated much like a heap block. We use +// "heap" throughout below to cover this case because the concepts are all the +// same.) // // "Snapshots" are recordings of the memory usage. There are two basic // kinds: @@ -280,14 +285,17 @@ static SizeT peak_snapshot_total_szB = 0; // memory. An alternative to milliseconds as a unit of program "time". static ULong total_allocs_deallocs_szB = 0; -// We don't start taking snapshots until the first basic block is executed, -// rather than doing it in ms_post_clo_init (which is the obvious spot), for -// two reasons. +// When running with --heap=yes --pages-as-heap=no, we don't start taking +// snapshots until the first basic block is executed, rather than doing it in +// ms_post_clo_init (which is the obvious spot), for two reasons. // - It lets us ignore stack events prior to that, because they're not // really proper ones and just would screw things up. // - Because there's still some core initialisation to do, and so there // would be an artificial time gap between the first and second snapshots. // +// When running with --heap=yes --pages-as-heap=yes, snapshots start much +// earlier due to new_mem_startup so this isn't relevant. +// static Bool have_started_executing_code = False; //------------------------------------------------------------// @@ -393,12 +401,13 @@ static Char* TimeUnit_to_string(TimeUnit time_unit) } } -static Bool clo_heap = True; +static Bool clo_heap = True; // clo_heap_admin is deliberately a word-sized type. At one point it was // a UInt, but this caused problems on 64-bit machines when it was // multiplied by a small negative number and then promoted to a // word-sized type -- it ended up with a value of 4.2 billion. Sigh. static SSizeT clo_heap_admin = 8; +static Bool clo_pages_as_heap = False; static Bool clo_stacks = False; static Int clo_depth = 30; static double clo_threshold = 1.0; // percentage @@ -417,29 +426,39 @@ static Bool ms_process_cmd_line_option(Char* arg) // Remember the arg for later use. VG_(addToXA)(args_for_massif, &arg); - if VG_BOOL_CLO(arg, "--heap", clo_heap) {} - else if VG_BOOL_CLO(arg, "--stacks", clo_stacks) {} - - else if VG_BINT_CLO(arg, "--heap-admin", clo_heap_admin, 0, 1024) {} - else if VG_BINT_CLO(arg, "--depth", clo_depth, 1, MAX_DEPTH) {} + if VG_BOOL_CLO(arg, "--heap", clo_heap) {} + else if VG_BINT_CLO(arg, "--heap-admin", clo_heap_admin, 0, 1024) {} - else if VG_DBL_CLO(arg, "--threshold", clo_threshold) {} - - else if VG_DBL_CLO(arg, "--peak-inaccuracy", clo_peak_inaccuracy) {} + else if VG_BOOL_CLO(arg, "--stacks", clo_stacks) {} - else if VG_BINT_CLO(arg, "--detailed-freq", clo_detailed_freq, 1, 10000) {} - else if VG_BINT_CLO(arg, "--max-snapshots", clo_max_snapshots, 10, 1000) {} + else if VG_BOOL_CLO(arg, "--pages-as-heap", clo_pages_as_heap) {} - else if VG_XACT_CLO(arg, "--time-unit=i", clo_time_unit, TimeI) {} - else if VG_XACT_CLO(arg, "--time-unit=ms", clo_time_unit, TimeMS) {} - else if VG_XACT_CLO(arg, "--time-unit=B", clo_time_unit, TimeB) {} + else if VG_BINT_CLO(arg, "--depth", clo_depth, 1, MAX_DEPTH) {} - else if VG_STR_CLO(arg, "--alloc-fn", tmp_str) { + else if VG_STR_CLO(arg, "--alloc-fn", tmp_str) { VG_(addToXA)(alloc_fns, &tmp_str); } - else if VG_STR_CLO(arg, "--ignore-fn", tmp_str) { + else if VG_STR_CLO(arg, "--ignore-fn", tmp_str) { VG_(addToXA)(ignore_fns, &tmp_str); } + + else if VG_DBL_CLO(arg, "--threshold", clo_threshold) { + if (clo_threshold < 0 || clo_threshold > 100) { + VG_(fmsg_bad_option)(arg, + "--threshold must be between 0.0 and 100.0\n"); + } + } + + else if VG_DBL_CLO(arg, "--peak-inaccuracy", clo_peak_inaccuracy) {} + + else if VG_XACT_CLO(arg, "--time-unit=i", clo_time_unit, TimeI) {} + else if VG_XACT_CLO(arg, "--time-unit=ms", clo_time_unit, TimeMS) {} + else if VG_XACT_CLO(arg, "--time-unit=B", clo_time_unit, TimeB) {} + + else if VG_BINT_CLO(arg, "--detailed-freq", clo_detailed_freq, 1, 10000) {} + + else if VG_BINT_CLO(arg, "--max-snapshots", clo_max_snapshots, 10, 1000) {} + else if VG_STR_CLO(arg, "--massif-out-file", clo_massif_out_file) {} else @@ -455,6 +474,7 @@ static void ms_print_usage(void) " --heap-admin= average admin bytes per heap block;\n" " ignored if --heap=no [8]\n" " --stacks=no|yes profile stack(s) [no]\n" +" --pages-as-heap=no|yes profile memory at the page level [no]\n" " --depth= depth of contexts [30]\n" " --alloc-fn= specify as an alloc function [empty]\n" " --ignore-fn= ignore heap allocations within [empty]\n" @@ -842,7 +862,7 @@ static Bool fn_should_be_ignored(Addr ip) // Nb: it's possible to end up with an empty trace, eg. if 'main' is marked // as an alloc-fn. This is ok. static -Int get_IPs( ThreadId tid, Bool is_custom_alloc, Addr ips[]) +Int get_IPs( ThreadId tid, Bool exclude_first_entry, Addr ips[]) { static Char buf[BUF_LEN]; Int n_ips, i, n_alloc_fns_removed; @@ -877,11 +897,11 @@ Int get_IPs( ThreadId tid, Bool is_custom_alloc, Addr ips[]) // If the original stack trace is smaller than asked-for, redo=False. if (n_ips < clo_depth + overestimate) { redo = False; } - // Filter out alloc fns. If it's a non-custom block, we remove the - // first entry (which will be one of malloc, __builtin_new, etc) - // without looking at it, because VG_(get_fnname) is expensive (it - // involves calls to VG_(malloc)/VG_(free)). - n_alloc_fns_removed = ( is_custom_alloc ? 0 : 1 ); + // Filter out alloc fns. If requested, we automatically remove the + // first entry (which presumably will be something like malloc or + // __builtin_new that we're sure to filter out) without looking at it, + // because VG_(get_fnname) is expensive. + n_alloc_fns_removed = ( exclude_first_entry ? 1 : 0 ); for (i = n_alloc_fns_removed; i < n_ips; i++) { if (VG_(get_fnname)(ips[i], buf, BUF_LEN)) { if (is_member_fn(alloc_fns, buf)) { @@ -912,14 +932,14 @@ Int get_IPs( ThreadId tid, Bool is_custom_alloc, Addr ips[]) // Gets an XCon and puts it in the tree. Returns the XCon's bottom-XPt. // Unless the allocation should be ignored, in which case we return NULL. -static XPt* get_XCon( ThreadId tid, Bool is_custom_alloc ) +static XPt* get_XCon( ThreadId tid, Bool exclude_first_entry ) { static Addr ips[MAX_IPS]; Int i; XPt* xpt = alloc_xpt; // After this call, the IPs we want are in ips[0]..ips[n_ips-1]. - Int n_ips = get_IPs(tid, is_custom_alloc, ips); + Int n_ips = get_IPs(tid, exclude_first_entry, ips); // Should we ignore this allocation? (Nb: n_ips can be zero, eg. if // 'main' is marked as an alloc-fn.) @@ -996,7 +1016,7 @@ static XPt* get_XCon( ThreadId tid, Bool is_custom_alloc ) // Update 'szB' of every XPt in the XCon, by percolating upwards. static void update_XCon(XPt* xpt, SSizeT space_delta) { - tl_assert(True == clo_heap); + tl_assert(clo_heap); tl_assert(NULL != xpt); if (0 == space_delta) @@ -1323,7 +1343,9 @@ take_snapshot(Snapshot* snapshot, SnapshotKind kind, Time my_time, Bool is_detailed) { tl_assert(!is_snapshot_in_use(snapshot)); - tl_assert(have_started_executing_code); + if (!clo_pages_as_heap) { + tl_assert(have_started_executing_code); + } // Heap and heap admin. if (clo_heap) { @@ -1518,31 +1540,11 @@ static void update_heap_stats(SSizeT heap_szB_delta, Int heap_extra_szB_delta) } static -void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB, - Bool is_zeroed ) +void* record_block( ThreadId tid, void* p, SizeT req_szB, SizeT slop_szB, + Bool exclude_first_entry, Bool maybe_snapshot ) { - HP_Chunk* hc; - Bool is_custom_alloc = (NULL != p); - SizeT actual_szB, slop_szB; - - if ((SSizeT)req_szB < 0) return NULL; - - // Allocate and zero if necessary - if (!p) { - p = VG_(cli_malloc)( req_alignB, req_szB ); - if (!p) { - return NULL; - } - if (is_zeroed) VG_(memset)(p, 0, req_szB); - actual_szB = VG_(malloc_usable_size)(p); - tl_assert(actual_szB >= req_szB); - slop_szB = actual_szB - req_szB; - } else { - slop_szB = 0; - } - // Make new HP_Chunk node, add to malloc_list - hc = VG_(malloc)("ms.main.nb.1", sizeof(HP_Chunk)); + HP_Chunk* hc = VG_(malloc)("ms.main.rb.1", sizeof(HP_Chunk)); hc->req_szB = req_szB; hc->slop_szB = slop_szB; hc->data = (Addr)p; @@ -1550,9 +1552,9 @@ void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB, VG_(HT_add_node)(malloc_list, hc); if (clo_heap) { - VERB(3, "<<< new_mem_heap (%lu, %lu)\n", req_szB, slop_szB); + VERB(3, "<<< record_block (%lu, %lu)\n", req_szB, slop_szB); - hc->where = get_XCon( tid, is_custom_alloc ); + hc->where = get_XCon( tid, exclude_first_entry ); if (hc->where) { // Update statistics. @@ -1565,7 +1567,9 @@ void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB, update_XCon(hc->where, req_szB); // Maybe take a snapshot. - maybe_take_snapshot(Normal, " alloc"); + if (maybe_snapshot) { + maybe_take_snapshot(Normal, " alloc"); + } } else { // Ignored allocation. @@ -1581,7 +1585,33 @@ void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB, } static __inline__ -void die_block ( void* p, Bool custom_free ) +void* alloc_and_record_block ( ThreadId tid, SizeT req_szB, SizeT req_alignB, + Bool is_zeroed ) +{ + SizeT actual_szB, slop_szB; + void* p; + + if ((SSizeT)req_szB < 0) return NULL; + + // Allocate and zero if necessary. + p = VG_(cli_malloc)( req_alignB, req_szB ); + if (!p) { + return NULL; + } + if (is_zeroed) VG_(memset)(p, 0, req_szB); + actual_szB = VG_(malloc_usable_size)(p); + tl_assert(actual_szB >= req_szB); + slop_szB = actual_szB - req_szB; + + // Record block. + record_block(tid, p, req_szB, slop_szB, /*exclude_first_entry*/True, + /*maybe_snapshot*/True); + + return p; +} + +static __inline__ +void unrecord_block ( void* p, Bool maybe_snapshot ) { // Remove HP_Chunk from malloc_list HP_Chunk* hc = VG_(HT_remove)(malloc_list, (UWord)p); @@ -1590,14 +1620,16 @@ void die_block ( void* p, Bool custom_free ) } if (clo_heap) { - VERB(3, "<<< die_mem_heap\n"); + VERB(3, "<<< unrecord_block\n"); if (hc->where) { // Update statistics. n_heap_frees++; // Maybe take a peak snapshot, since it's a deallocation. - maybe_take_snapshot(Peak, "de-PEAK"); + if (maybe_snapshot) { + maybe_take_snapshot(Peak, "de-PEAK"); + } // Update heap stats. update_heap_stats(-hc->req_szB, -clo_heap_admin - hc->slop_szB); @@ -1606,7 +1638,9 @@ void die_block ( void* p, Bool custom_free ) update_XCon(hc->where, -hc->req_szB); // Maybe take a snapshot. - maybe_take_snapshot(Normal, "dealloc"); + if (maybe_snapshot) { + maybe_take_snapshot(Normal, "dealloc"); + } } else { n_ignored_heap_frees++; @@ -1619,8 +1653,6 @@ void die_block ( void* p, Bool custom_free ) // Actually free the chunk, and the heap block (if necessary) VG_(free)( hc ); hc = NULL; - if (!custom_free) - VG_(cli_free)( p ); } // Nb: --ignore-fn is tricky for realloc. If the block's original alloc was @@ -1630,7 +1662,7 @@ void die_block ( void* p, Bool custom_free ) // growing such a block, but for consistency (it also simplifies things) we // ignore such reallocs as well. static __inline__ -void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB ) +void* realloc_block ( ThreadId tid, void* p_old, SizeT new_req_szB ) { HP_Chunk* hc; void* p_new; @@ -1647,8 +1679,9 @@ void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB ) old_req_szB = hc->req_szB; old_slop_szB = hc->slop_szB; + tl_assert(!clo_pages_as_heap); // Shouldn't be here if --pages-as-heap=yes. if (clo_heap) { - VERB(3, "<<< renew_mem_heap (%lu)\n", new_req_szB); + VERB(3, "<<< realloc_block (%lu)\n", new_req_szB); if (hc->where) { // Update statistics. @@ -1696,7 +1729,7 @@ void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB ) // Update XTree. if (clo_heap) { - new_where = get_XCon( tid, /*custom_malloc*/False); + new_where = get_XCon( tid, /*exclude_first_entry*/True); if (!is_ignored && new_where) { hc->where = new_where; update_XCon(old_where, -old_req_szB); @@ -1745,47 +1778,50 @@ void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB ) static void* ms_malloc ( ThreadId tid, SizeT szB ) { - return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False ); + return alloc_and_record_block( tid, szB, VG_(clo_alignment), /*is_zeroed*/False ); } static void* ms___builtin_new ( ThreadId tid, SizeT szB ) { - return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False ); + return alloc_and_record_block( tid, szB, VG_(clo_alignment), /*is_zeroed*/False ); } static void* ms___builtin_vec_new ( ThreadId tid, SizeT szB ) { - return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False ); + return alloc_and_record_block( tid, szB, VG_(clo_alignment), /*is_zeroed*/False ); } static void* ms_calloc ( ThreadId tid, SizeT m, SizeT szB ) { - return new_block( tid, NULL, m*szB, VG_(clo_alignment), /*is_zeroed*/True ); + return alloc_and_record_block( tid, m*szB, VG_(clo_alignment), /*is_zeroed*/True ); } static void *ms_memalign ( ThreadId tid, SizeT alignB, SizeT szB ) { - return new_block( tid, NULL, szB, alignB, False ); + return alloc_and_record_block( tid, szB, alignB, False ); } static void ms_free ( ThreadId tid __attribute__((unused)), void* p ) { - die_block( p, /*custom_free*/False ); + unrecord_block(p, /*maybe_snapshot*/True); + VG_(cli_free)(p); } static void ms___builtin_delete ( ThreadId tid, void* p ) { - die_block( p, /*custom_free*/False); + unrecord_block(p, /*maybe_snapshot*/True); + VG_(cli_free)(p); } static void ms___builtin_vec_delete ( ThreadId tid, void* p ) { - die_block( p, /*custom_free*/False ); + unrecord_block(p, /*maybe_snapshot*/True); + VG_(cli_free)(p); } static void* ms_realloc ( ThreadId tid, void* p_old, SizeT new_szB ) { - return renew_block(tid, p_old, new_szB); + return realloc_block(tid, p_old, new_szB); } static SizeT ms_malloc_usable_size ( ThreadId tid, void* p ) @@ -1795,6 +1831,89 @@ static SizeT ms_malloc_usable_size ( ThreadId tid, void* p ) return ( hc ? hc->req_szB + hc->slop_szB : 0 ); } +//------------------------------------------------------------// +//--- Page handling ---// +//------------------------------------------------------------// + +static +void ms_record_page_mem ( Addr a, SizeT len ) +{ + ThreadId tid = VG_(get_running_tid)(); + Addr end; + tl_assert(VG_IS_PAGE_ALIGNED(len)); + tl_assert(len >= VKI_PAGE_SIZE); + // Record the first N-1 pages as blocks, but don't do any snapshots. + for (end = a + len - VKI_PAGE_SIZE; a < end; a += VKI_PAGE_SIZE) { + record_block( tid, (void*)a, VKI_PAGE_SIZE, /*slop_szB*/0, + /*exclude_first_entry*/False, /*maybe_snapshot*/False ); + } + // Record the last page as a block, and maybe do a snapshot afterwards. + record_block( tid, (void*)a, VKI_PAGE_SIZE, /*slop_szB*/0, + /*exclude_first_entry*/False, /*maybe_snapshot*/True ); +} + +static +void ms_unrecord_page_mem( Addr a, SizeT len ) +{ + Addr end; + tl_assert(VG_IS_PAGE_ALIGNED(len)); + tl_assert(len >= VKI_PAGE_SIZE); + for (end = a + len - VKI_PAGE_SIZE; a < end; a += VKI_PAGE_SIZE) { + unrecord_block((void*)a, /*maybe_snapshot*/False); + } + unrecord_block((void*)a, /*maybe_snapshot*/True); +} + +//------------------------------------------------------------// + +static +void ms_new_mem_mmap ( Addr a, SizeT len, + Bool rr, Bool ww, Bool xx, ULong di_handle ) +{ + tl_assert(VG_IS_PAGE_ALIGNED(len)); + ms_record_page_mem(a, len); +} + +static +void ms_new_mem_startup( Addr a, SizeT len, + Bool rr, Bool ww, Bool xx, ULong di_handle ) +{ + // startup maps are always be page-sized, except the trampoline page is + // marked by the core as only being the size of the trampoline itself, + // which is something like 57 bytes. Round it up to page size. + len = VG_PGROUNDUP(len); + ms_record_page_mem(a, len); +} + +static +void ms_new_mem_brk ( Addr a, SizeT len, ThreadId tid ) +{ + tl_assert(VG_IS_PAGE_ALIGNED(len)); + ms_record_page_mem(a, len); +} + +static +void ms_copy_mem_remap( Addr from, Addr to, SizeT len) +{ + tl_assert(VG_IS_PAGE_ALIGNED(len)); + ms_unrecord_page_mem(from, len); + ms_record_page_mem(to, len); +} + +static +void ms_die_mem_munmap( Addr a, SizeT len ) +{ + tl_assert(VG_IS_PAGE_ALIGNED(len)); + ms_unrecord_page_mem(a, len); +} + +static +void ms_die_mem_brk( Addr a, SizeT len ) +{ + tl_assert(VG_IS_PAGE_ALIGNED(len)); + ms_unrecord_page_mem(a, len); +} + //------------------------------------------------------------// //--- Stacks ---// //------------------------------------------------------------// @@ -1862,17 +1981,16 @@ static Bool ms_handle_client_request ( ThreadId tid, UWord* argv, UWord* ret ) { switch (argv[0]) { case VG_USERREQ__MALLOCLIKE_BLOCK: { - void* res; void* p = (void*)argv[1]; SizeT szB = argv[2]; - res = new_block( tid, p, szB, /*alignB--ignored*/0, /*is_zeroed*/False ); - tl_assert(res == p); + record_block( tid, p, szB, /*slop_szB*/0, /*exclude_first_entry*/False, + /*maybe_snapshot*/True ); *ret = 0; return True; } case VG_USERREQ__FREELIKE_BLOCK: { void* p = (void*)argv[1]; - die_block( p, /*custom_free*/True ); + unrecord_block(p, /*maybe_snapshot*/True); *ret = 0; return True; } @@ -1903,14 +2021,12 @@ static void add_counter_update(IRSB* sbOut, Int n) IRTemp t2 = newIRTemp(sbOut->tyenv, Ity_I64); IRExpr* counter_addr = mkIRExpr_HWord( (HWord)&guest_instrs_executed ); - IRStmt* st1 = IRStmt_WrTmp(t1, IRExpr_Load(False/*!isLL*/, - END, Ity_I64, counter_addr)); + IRStmt* st1 = IRStmt_WrTmp(t1, IRExpr_Load(END, Ity_I64, counter_addr)); IRStmt* st2 = IRStmt_WrTmp(t2, IRExpr_Binop(Iop_Add64, IRExpr_RdTmp(t1), IRExpr_Const(IRConst_U64(n)))); - IRStmt* st3 = IRStmt_Store(END, IRTemp_INVALID/*"not store-conditional"*/, - counter_addr, IRExpr_RdTmp(t2)); + IRStmt* st3 = IRStmt_Store(END, counter_addr, IRExpr_RdTmp(t2)); addStmtToIRSB( sbOut, st1 ); addStmtToIRSB( sbOut, st2 ); @@ -2021,8 +2137,15 @@ static void pp_snapshot_SXPt(Int fd, SXPt* sxpt, Int depth, Char* depth_str, case SigSXPt: // Print the SXPt itself. if (0 == depth) { - ip_desc = - "(heap allocation functions) malloc/new/new[], --alloc-fns, etc."; + if (clo_heap) { + ip_desc = + ( clo_pages_as_heap + ? "(page allocation syscalls) mmap/mremap/brk, --alloc-fns, etc." + : "(heap allocation functions) malloc/new/new[], --alloc-fns, etc." + ); + } else { + // XXX: --alloc-fns? + } } else { // If it's main-or-below-main, we (if appropriate) ignore everything // below it by pretending it has no children. @@ -2263,17 +2386,52 @@ static void ms_fini(Int exit_status) static void ms_post_clo_init(void) { Int i; + Char* LD_PRELOAD_val; + Char* s; + Char* s2; // Check options. - if (clo_threshold < 0 || clo_threshold > 100) { - VG_(umsg)("--threshold must be between 0.0 and 100.0\n"); - VG_(err_bad_option)("--threshold"); + if (clo_pages_as_heap) { + if (clo_stacks) { + VG_(fmsg_bad_option)( + "--pages-as-heap=yes together with --stacks=yes", ""); + } } - - // If we have --heap=no, set --heap-admin to zero, just to make sure we - // don't accidentally use a non-zero heap-admin size somewhere. if (!clo_heap) { - clo_heap_admin = 0; + clo_pages_as_heap = False; + } + + // If --pages-as-heap=yes we don't want malloc replacement to occur. So we + // disable vgpreload_massif-$PLATFORM.so by removing it from LD_PRELOAD (or + // platform-equivalent). We replace it entirely with spaces because then + // the linker doesn't complain (it does complain if we just change the name + // to a bogus file). This is a bit of a hack, but LD_PRELOAD is setup well + // before tool initialisation, so this seems the best way to do it. + if (clo_pages_as_heap) { + clo_heap_admin = 0; // No heap admin on pages. + + LD_PRELOAD_val = VG_(getenv)( (Char*)VG_(LD_PRELOAD_var_name) ); + tl_assert(LD_PRELOAD_val); + + // Make sure the vgpreload_core-$PLATFORM entry is there, for sanity. + s2 = VG_(strstr)(LD_PRELOAD_val, "vgpreload_core"); + tl_assert(s2); + + // Now find the vgpreload_massif-$PLATFORM entry. + s2 = VG_(strstr)(LD_PRELOAD_val, "vgpreload_massif"); + tl_assert(s2); + + // Blank out everything to the previous ':', which must be there because + // of the preceding vgpreload_core-$PLATFORM entry. + for (s = s2; *s != ':'; s--) { + *s = ' '; + } + + // Blank out everything to the end of the entry, which will be '\0' if + // LD_PRELOAD was empty before Valgrind started, or ':' otherwise. + for (s = s2; *s != ':' && *s != '\0'; s++) { + *s = ' '; + } } // Print alloc-fns and ignore-fns, if necessary. @@ -2302,6 +2460,17 @@ static void ms_post_clo_init(void) VG_(track_die_mem_stack_signal) ( die_mem_stack_signal ); } + if (clo_pages_as_heap) { + VG_(track_new_mem_startup) ( ms_new_mem_startup ); + VG_(track_new_mem_brk) ( ms_new_mem_brk ); + VG_(track_new_mem_mmap) ( ms_new_mem_mmap ); + + VG_(track_copy_mem_remap) ( ms_copy_mem_remap ); + + VG_(track_die_mem_brk) ( ms_die_mem_brk ); + VG_(track_die_mem_munmap) ( ms_die_mem_munmap ); + } + // Initialise snapshot array, and sanity-check it. snapshots = VG_(malloc)("ms.main.mpoci.1", sizeof(Snapshot) * clo_max_snapshots); @@ -2319,7 +2488,7 @@ static void ms_pre_clo_init(void) VG_(details_version) (NULL); VG_(details_description) ("a heap profiler"); VG_(details_copyright_author)( - "Copyright (C) 2003-2009, and GNU GPL'd, by Nicholas Nethercote"); + "Copyright (C) 2003-2010, and GNU GPL'd, by Nicholas Nethercote"); VG_(details_bug_reports_to) (VG_BUGS_TO); // Basic functions. diff --git a/massif/ms_print.in b/massif/ms_print.in old mode 100644 new mode 100755 diff --git a/memcheck/Makefile.am b/memcheck/Makefile.am index 50849c5..5f8fd2e 100644 --- a/memcheck/Makefile.am +++ b/memcheck/Makefile.am @@ -31,7 +31,8 @@ MEMCHECK_SOURCES_COMMON = \ mc_machine.c \ mc_errors.c -memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(MEMCHECK_SOURCES_COMMON) +memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ + $(MEMCHECK_SOURCES_COMMON) memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \ @@ -42,8 +43,16 @@ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC -memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(MEMCHECK_SOURCES_COMMON) +memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ + $(MEMCHECK_SOURCES_COMMON) memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \ @@ -54,6 +63,12 @@ memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif mc_main.o: CFLAGS += -fomit-frame-pointer @@ -84,6 +99,7 @@ vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \ vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) + if VGCONF_HAVE_PLATFORM_SEC vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = \ $(VGPRELOAD_MEMCHECK_SOURCES_COMMON) diff --git a/memcheck/docs/mc-manual.xml b/memcheck/docs/mc-manual.xml index 3ee00f2..c380fce 100644 --- a/memcheck/docs/mc-manual.xml +++ b/memcheck/docs/mc-manual.xml @@ -620,6 +620,16 @@ criteria: + + + + + + When disabled, the memory leak detector will not show "possibly lost" blocks. + + + + @@ -753,7 +763,7 @@ criteria: - + When the client program releases memory using @@ -769,7 +779,7 @@ criteria: have been freed. This option specifies the maximum total size, in bytes, of the - blocks in the queue. The default value is ten million bytes. + blocks in the queue. The default value is twenty million bytes. Increasing this increases the total amount of memory used by Memcheck but may detect invalid uses of freed blocks which would otherwise go undetected. @@ -1143,8 +1153,8 @@ follows: Each byte in memory has 8 associated V (valid-value) bits, saying whether or not the byte has a defined value, and a single A (valid-address) bit, saying whether or not the program currently has - the right to read/write that address. (But, as mentioned above, heavy - use of compression means the overhead is typically less than 25%.) + the right to read/write that address. As mentioned above, heavy + use of compression means the overhead is typically around 25%. diff --git a/memcheck/mc_errors.c b/memcheck/mc_errors.c index 5ee1055..00f09fc 100644 --- a/memcheck/mc_errors.c +++ b/memcheck/mc_errors.c @@ -8,7 +8,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -768,6 +768,7 @@ void MC_(pp_Error) ( Error* err ) for the --workaround-gcc296-bugs kludge. */ static Bool is_just_below_ESP( Addr esp, Addr aa ) { + esp -= VG_STACK_REDZONE_SZB; if (esp > aa && (esp - aa) <= VG_GCC296_BUG_STACK_SLOP) return True; else diff --git a/memcheck/mc_include.h b/memcheck/mc_include.h index 1032cf5..c2ef03e 100644 --- a/memcheck/mc_include.h +++ b/memcheck/mc_include.h @@ -8,7 +8,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -395,6 +395,9 @@ extern VgRes MC_(clo_leak_resolution); /* In leak check, show reachable-but-not-freed blocks? default: NO */ extern Bool MC_(clo_show_reachable); +/* In leak check, show possibly-lost blocks? default: YES */ +extern Bool MC_(clo_show_possibly_lost); + /* Assume accesses immediately below %esp are due to gcc-2.96 bugs. * default: NO */ extern Bool MC_(clo_workaround_gcc296_bugs); diff --git a/memcheck/mc_leakcheck.c b/memcheck/mc_leakcheck.c index 3893f27..13b8de3 100644 --- a/memcheck/mc_leakcheck.c +++ b/memcheck/mc_leakcheck.c @@ -7,7 +7,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -425,7 +425,8 @@ find_active_chunks(UInt* pn_chunks) typedef struct { UInt state:2; // Reachedness. - SizeT indirect_szB : (sizeof(SizeT)*8)-2; // If Unreached, how many bytes + UInt pending:1; // Scan pending. + SizeT indirect_szB : (sizeof(SizeT)*8)-3; // If Unreached, how many bytes // are unreachable from here. } LC_Extra; @@ -510,12 +511,16 @@ lc_is_a_chunk_ptr(Addr ptr, Int* pch_no, MC_Chunk** pch, LC_Extra** pex) // Push a chunk (well, just its index) onto the mark stack. static void lc_push(Int ch_no, MC_Chunk* ch) { - if (0) { - VG_(printf)("pushing %#lx-%#lx\n", ch->data, ch->data + ch->szB); + if (!lc_extras[ch_no].pending) { + if (0) { + VG_(printf)("pushing %#lx-%#lx\n", ch->data, ch->data + ch->szB); + } + lc_markstack_top++; + tl_assert(lc_markstack_top < lc_n_chunks); + lc_markstack[lc_markstack_top] = ch_no; + tl_assert(!lc_extras[ch_no].pending); + lc_extras[ch_no].pending = True; } - lc_markstack_top++; - tl_assert(lc_markstack_top < lc_n_chunks); - lc_markstack[lc_markstack_top] = ch_no; } // Return the index of the chunk on the top of the mark stack, or -1 if @@ -528,6 +533,8 @@ static Bool lc_pop(Int* ret) tl_assert(0 <= lc_markstack_top && lc_markstack_top < lc_n_chunks); *ret = lc_markstack[lc_markstack_top]; lc_markstack_top--; + tl_assert(lc_extras[*ret].pending); + lc_extras[*ret].pending = False; return True; } } @@ -544,25 +551,28 @@ lc_push_without_clique_if_a_chunk_ptr(Addr ptr, Bool is_prior_definite) if ( ! lc_is_a_chunk_ptr(ptr, &ch_no, &ch, &ex) ) return; - - // Only push it if it hasn't been seen previously. - if (ex->state == Unreached) { - lc_push(ch_no, ch); - } - + // Possibly upgrade the state, ie. one of: // - Unreached --> Possible // - Unreached --> Reachable // - Possible --> Reachable - if (ptr == ch->data && is_prior_definite) { + if (ptr == ch->data && is_prior_definite && ex->state != Reachable) { // 'ptr' points to the start of the block, and the prior node is // definite, which means that this block is definitely reachable. ex->state = Reachable; + // State has changed to Reachable so (re)scan the block to make + // sure any blocks it points to are correctly marked. + lc_push(ch_no, ch); + } else if (ex->state == Unreached) { // Either 'ptr' is a interior-pointer, or the prior node isn't definite, // which means that we can only mark this block as possibly reachable. ex->state = Possible; + + // State has changed to Possible so (re)scan the block to make + // sure any blocks it points to are correctly marked. + lc_push(ch_no, ch); } } @@ -708,7 +718,7 @@ static void lc_process_markstack(Int clique) Bool is_prior_definite; while (lc_pop(&top)) { - tl_assert(top >= 0 && top < lc_n_chunks); + tl_assert(top >= 0 && top < lc_n_chunks); // See comment about 'is_prior_definite' at the top to understand this. is_prior_definite = ( Possible != lc_extras[top].state ); @@ -845,7 +855,8 @@ static void print_results(ThreadId tid, Bool is_full_check) print_record = is_full_check && ( MC_(clo_show_reachable) || Unreached == lr->key.state || - Possible == lr->key.state ); + ( MC_(clo_show_possibly_lost) && + Possible == lr->key.state ) ); // We don't count a leaks as errors with --leak-check=summary. // Otherwise you can get high error counts with few or no error // messages, which can be confusing. Also, you could argue that @@ -1006,6 +1017,7 @@ void MC_(detect_memory_leaks) ( ThreadId tid, LeakCheckMode mode ) lc_extras = VG_(malloc)( "mc.dml.2", lc_n_chunks * sizeof(LC_Extra) ); for (i = 0; i < lc_n_chunks; i++) { lc_extras[i].state = Unreached; + lc_extras[i].pending = False; lc_extras[i].indirect_szB = 0; } diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c index 752f1a4..3cc665e 100644 --- a/memcheck/mc_machine.c +++ b/memcheck/mc_machine.c @@ -9,7 +9,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2008-2009 OpenWorks Ltd + Copyright (C) 2008-2010 OpenWorks Ltd info@open-works.co.uk This program is free software; you can redistribute it and/or @@ -65,6 +65,11 @@ # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC64State) #endif +#if defined(VGA_arm) +# include "libvex_guest_arm.h" +# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestARMState) +#endif + static inline Bool host_is_big_endian ( void ) { UInt x = 0x11223344; return 0x1122 == *(UShort*)(&x); @@ -488,6 +493,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) if (o == GOF(RIP) && sz == 8) return -1; /* slot unused */ if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1; /* slot unused */ if (o == GOF(IDFLAG) && sz == 8) return -1; /* slot used for %DH */ + if (o == GOF(ACFLAG) && sz == 8) return -1; /* slot unused */ if (o == GOF(FS_ZERO) && sz == 8) return -1; /* slot unused */ if (o == GOF(GS_0x60) && sz == 8) return -1; /* slot unused */ if (o == GOF(TISTART) && sz == 8) return -1; /* slot unused */ @@ -531,6 +537,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) if (o >= GOF(XMM13) && o+sz <= GOF(XMM13)+SZB(XMM13)) return GOF(XMM13); if (o >= GOF(XMM14) && o+sz <= GOF(XMM14)+SZB(XMM14)) return GOF(XMM14); if (o >= GOF(XMM15) && o+sz <= GOF(XMM15)+SZB(XMM15)) return GOF(XMM15); + if (o >= GOF(XMM16) && o+sz <= GOF(XMM16)+SZB(XMM16)) return GOF(XMM16); /* MMX accesses to FP regs. Need to allow for 32-bit references due to dirty helpers for frstor etc, which reference the entire @@ -672,6 +679,124 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) offset,szB); tl_assert(0); # undef GOF +# undef SZB + + /* --------------------- arm --------------------- */ + +# elif defined(VGA_arm) + +# define GOF(_fieldname) \ + (offsetof(VexGuestARMState,guest_##_fieldname)) +# define SZB(_fieldname) \ + (sizeof(((VexGuestARMState*)0)->guest_##_fieldname)) + + Int o = offset; + Int sz = szB; + tl_assert(sz > 0); + tl_assert(host_is_little_endian()); + + if (o == GOF(R0) && sz == 4) return o; + if (o == GOF(R1) && sz == 4) return o; + if (o == GOF(R2) && sz == 4) return o; + if (o == GOF(R3) && sz == 4) return o; + if (o == GOF(R4) && sz == 4) return o; + if (o == GOF(R5) && sz == 4) return o; + if (o == GOF(R6) && sz == 4) return o; + if (o == GOF(R7) && sz == 4) return o; + if (o == GOF(R8) && sz == 4) return o; + if (o == GOF(R9) && sz == 4) return o; + if (o == GOF(R10) && sz == 4) return o; + if (o == GOF(R11) && sz == 4) return o; + if (o == GOF(R12) && sz == 4) return o; + if (o == GOF(R13) && sz == 4) return o; + if (o == GOF(R14) && sz == 4) return o; + + /* EAZG: These may be completely wrong. */ + if (o == GOF(R15T) && sz == 4) return -1; /* slot unused */ + if (o == GOF(CC_OP) && sz == 4) return -1; /* slot unused */ + + if (o == GOF(CC_DEP1) && sz == 4) return o; + if (o == GOF(CC_DEP2) && sz == 4) return o; + + if (o == GOF(CC_NDEP) && sz == 4) return -1; /* slot unused */ + + if (o == GOF(QFLAG32) && sz == 4) return o; + + if (o == GOF(GEFLAG0) && sz == 4) return o; + if (o == GOF(GEFLAG1) && sz == 4) return o; + if (o == GOF(GEFLAG2) && sz == 4) return o; + if (o == GOF(GEFLAG3) && sz == 4) return o; + + //if (o == GOF(SYSCALLNO) && sz == 4) return -1; /* slot unused */ + //if (o == GOF(CC) && sz == 4) return -1; /* slot unused */ + //if (o == GOF(EMWARN) && sz == 4) return -1; /* slot unused */ + //if (o == GOF(TISTART) && sz == 4) return -1; /* slot unused */ + //if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */ + + if (o == GOF(FPSCR) && sz == 4) return -1; + if (o == GOF(TPIDRURO) && sz == 4) return -1; + if (o == GOF(ITSTATE) && sz == 4) return -1; + + /* Accesses to F or D registers */ + if (sz == 4 || sz == 8) { + if (o >= GOF(D0) && o+sz <= GOF(D0) +SZB(D0)) return GOF(D0); + if (o >= GOF(D1) && o+sz <= GOF(D1) +SZB(D1)) return GOF(D1); + if (o >= GOF(D2) && o+sz <= GOF(D2) +SZB(D2)) return GOF(D2); + if (o >= GOF(D3) && o+sz <= GOF(D3) +SZB(D3)) return GOF(D3); + if (o >= GOF(D4) && o+sz <= GOF(D4) +SZB(D4)) return GOF(D4); + if (o >= GOF(D5) && o+sz <= GOF(D5) +SZB(D5)) return GOF(D5); + if (o >= GOF(D6) && o+sz <= GOF(D6) +SZB(D6)) return GOF(D6); + if (o >= GOF(D7) && o+sz <= GOF(D7) +SZB(D7)) return GOF(D7); + if (o >= GOF(D8) && o+sz <= GOF(D8) +SZB(D8)) return GOF(D8); + if (o >= GOF(D9) && o+sz <= GOF(D9) +SZB(D9)) return GOF(D9); + if (o >= GOF(D10) && o+sz <= GOF(D10)+SZB(D10)) return GOF(D10); + if (o >= GOF(D11) && o+sz <= GOF(D11)+SZB(D11)) return GOF(D11); + if (o >= GOF(D12) && o+sz <= GOF(D12)+SZB(D12)) return GOF(D12); + if (o >= GOF(D13) && o+sz <= GOF(D13)+SZB(D13)) return GOF(D13); + if (o >= GOF(D14) && o+sz <= GOF(D14)+SZB(D14)) return GOF(D14); + if (o >= GOF(D15) && o+sz <= GOF(D15)+SZB(D15)) return GOF(D15); + if (o >= GOF(D16) && o+sz <= GOF(D16)+SZB(D16)) return GOF(D16); + if (o >= GOF(D17) && o+sz <= GOF(D17)+SZB(D17)) return GOF(D17); + if (o >= GOF(D18) && o+sz <= GOF(D18)+SZB(D18)) return GOF(D18); + if (o >= GOF(D19) && o+sz <= GOF(D19)+SZB(D19)) return GOF(D19); + if (o >= GOF(D20) && o+sz <= GOF(D20)+SZB(D20)) return GOF(D20); + if (o >= GOF(D21) && o+sz <= GOF(D21)+SZB(D21)) return GOF(D21); + if (o >= GOF(D22) && o+sz <= GOF(D22)+SZB(D22)) return GOF(D22); + if (o >= GOF(D23) && o+sz <= GOF(D23)+SZB(D23)) return GOF(D23); + if (o >= GOF(D24) && o+sz <= GOF(D24)+SZB(D24)) return GOF(D24); + if (o >= GOF(D25) && o+sz <= GOF(D25)+SZB(D25)) return GOF(D25); + if (o >= GOF(D26) && o+sz <= GOF(D26)+SZB(D26)) return GOF(D26); + if (o >= GOF(D27) && o+sz <= GOF(D27)+SZB(D27)) return GOF(D27); + if (o >= GOF(D28) && o+sz <= GOF(D28)+SZB(D28)) return GOF(D28); + if (o >= GOF(D29) && o+sz <= GOF(D29)+SZB(D29)) return GOF(D29); + if (o >= GOF(D30) && o+sz <= GOF(D30)+SZB(D30)) return GOF(D30); + if (o >= GOF(D31) && o+sz <= GOF(D31)+SZB(D31)) return GOF(D31); + } + + /* Accesses to Q registers */ + if (sz == 16) { + if (o >= GOF(D0) && o+sz <= GOF(D0) +2*SZB(D0)) return GOF(D0); // Q0 + if (o >= GOF(D2) && o+sz <= GOF(D2) +2*SZB(D2)) return GOF(D2); // Q1 + if (o >= GOF(D4) && o+sz <= GOF(D4) +2*SZB(D4)) return GOF(D4); // Q2 + if (o >= GOF(D6) && o+sz <= GOF(D6) +2*SZB(D6)) return GOF(D6); // Q3 + if (o >= GOF(D8) && o+sz <= GOF(D8) +2*SZB(D8)) return GOF(D8); // Q4 + if (o >= GOF(D10) && o+sz <= GOF(D10)+2*SZB(D10)) return GOF(D10); // Q5 + if (o >= GOF(D12) && o+sz <= GOF(D12)+2*SZB(D12)) return GOF(D12); // Q6 + if (o >= GOF(D14) && o+sz <= GOF(D14)+2*SZB(D14)) return GOF(D14); // Q7 + if (o >= GOF(D16) && o+sz <= GOF(D16)+2*SZB(D16)) return GOF(D16); // Q8 + if (o >= GOF(D18) && o+sz <= GOF(D18)+2*SZB(D18)) return GOF(D18); // Q9 + if (o >= GOF(D20) && o+sz <= GOF(D20)+2*SZB(D20)) return GOF(D20); // Q10 + if (o >= GOF(D22) && o+sz <= GOF(D22)+2*SZB(D22)) return GOF(D22); // Q11 + if (o >= GOF(D24) && o+sz <= GOF(D24)+2*SZB(D24)) return GOF(D24); // Q12 + if (o >= GOF(D26) && o+sz <= GOF(D26)+2*SZB(D26)) return GOF(D26); // Q13 + if (o >= GOF(D28) && o+sz <= GOF(D28)+2*SZB(D28)) return GOF(D28); // Q14 + if (o >= GOF(D30) && o+sz <= GOF(D30)+2*SZB(D30)) return GOF(D30); // Q15 + } + + VG_(printf)("MC_(get_otrack_shadow_offset)(arm)(off=%d,sz=%d)\n", + offset,szB); + tl_assert(0); +# undef GOF # undef SZB # else @@ -755,6 +880,14 @@ IRType MC_(get_otrack_reg_array_equiv_int_type) ( IRRegArray* arr ) VG_(printf)("\n"); tl_assert(0); + /* --------------------- arm --------------------- */ +# elif defined(VGA_arm) + + VG_(printf)("get_reg_array_equiv_int_type(arm): unhandled: "); + ppIRRegArray(arr); + VG_(printf)("\n"); + tl_assert(0); + # else # error "FIXME: not implemented for this architecture" # endif diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c index be0f3fd..cf7a021 100644 --- a/memcheck/mc_main.c +++ b/memcheck/mc_main.c @@ -9,7 +9,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -1606,6 +1606,7 @@ void make_mem_undefined_w_tid ( Addr a, SizeT len, ThreadId tid ) { make_mem_undefined_w_tid_and_okind ( a, len, tid, MC_OKIND_UNKNOWN ); } + void MC_(make_mem_defined) ( Addr a, SizeT len ) { PROF_EVENT(42, "MC_(make_mem_defined)"); @@ -1635,14 +1636,15 @@ static void make_mem_defined_if_addressable ( Addr a, SizeT len ) } } -static void make_mem_defined_if_unaddressable ( Addr a, SizeT len ) +/* Similarly (needed for mprotect handling ..) */ +static void make_mem_defined_if_noaccess ( Addr a, SizeT len ) { SizeT i; UChar vabits2; - DEBUG("make_mem_defined_if_unaddressable(%p, %llu)\n", a, (ULong)len); + DEBUG("make_mem_defined_if_noaccess(%p, %llu)\n", a, (ULong)len); for (i = 0; i < len; i++) { vabits2 = get_vabits2( a+i ); - if (vabits2 == VA_BITS2_NOACCESS) { + if (LIKELY(VA_BITS2_NOACCESS == vabits2)) { set_vabits2(a+i, VA_BITS2_DEFINED); if (UNLIKELY(MC_(clo_mc_level) >= 3)) { MC_(helperc_b_store1)( a+i, 0 ); /* clear the origin tag */ @@ -1651,26 +1653,6 @@ static void make_mem_defined_if_unaddressable ( Addr a, SizeT len ) } } -/* Track changes in the virtual memory space. */ -static void track_perms_change( Addr a, SizeT len, - Bool rr, Bool ww, Bool xx ) -{ -/* - if (!(rr || ww)) - MC_(make_mem_noaccess) ( a, len ); -*/ - /* - * Valgrind's memory management implementation is brain-damaged - * so we can't mark memory as unaccessible but defined :-( - * Thus we don't alter it if the new bits indicate the range - * as unaccessible and only change access bits for unaccessible - * bytes if permissions were given - */ - if (rr || ww) - make_mem_defined_if_unaddressable ( a, len ); -} - - /* --- Block-copy permissions (needed for implementing realloc() and sys_mremap). --- */ @@ -3735,16 +3717,86 @@ void check_mem_is_defined_asciiz ( CorePart part, ThreadId tid, } } +/* Handling of mmap and mprotect is not as simple as it seems. + + The underlying semantics are that memory obtained from mmap is + always initialised, but may be inaccessible. And changes to the + protection of memory do not change its contents and hence not its + definedness state. Problem is we can't model + inaccessible-but-with-some-definedness state; once we mark memory + as inaccessible we lose all info about definedness, and so can't + restore that if it is later made accessible again. + + One obvious thing to do is this: + + mmap/mprotect NONE -> noaccess + mmap/mprotect other -> defined + + The problem case here is: taking accessible memory, writing + uninitialised data to it, mprotecting it NONE and later mprotecting + it back to some accessible state causes the undefinedness to be + lost. + + A better proposal is: + + (1) mmap NONE -> make noaccess + (2) mmap other -> make defined + + (3) mprotect NONE -> # no change + (4) mprotect other -> change any "noaccess" to "defined" + + (2) is OK because memory newly obtained from mmap really is defined + (zeroed out by the kernel -- doing anything else would + constitute a massive security hole.) + + (1) is OK because the only way to make the memory usable is via + (4), in which case we also wind up correctly marking it all as + defined. + + (3) is the weak case. We choose not to change memory state. + (presumably the range is in some mixture of "defined" and + "undefined", viz, accessible but with arbitrary V bits). Doing + nothing means we retain the V bits, so that if the memory is + later mprotected "other", the V bits remain unchanged, so there + can be no false negatives. The bad effect is that if there's + an access in the area, then MC cannot warn; but at least we'll + get a SEGV to show, so it's better than nothing. + + Consider the sequence (3) followed by (4). Any memory that was + "defined" or "undefined" previously retains its state (as + required). Any memory that was "noaccess" before can only have + been made that way by (1), and so it's OK to change it to + "defined". + + See https://bugs.kde.org/show_bug.cgi?id=205541 + and https://bugs.kde.org/show_bug.cgi?id=210268 +*/ static void mc_new_mem_mmap ( Addr a, SizeT len, Bool rr, Bool ww, Bool xx, ULong di_handle ) { - if (rr || ww || xx) + if (rr || ww || xx) { + /* (2) mmap/mprotect other -> defined */ MC_(make_mem_defined)(a, len); - else + } else { + /* (1) mmap/mprotect NONE -> noaccess */ MC_(make_mem_noaccess)(a, len); + } +} + +static +void mc_new_mem_mprotect ( Addr a, SizeT len, Bool rr, Bool ww, Bool xx ) +{ + if (rr || ww || xx) { + /* (4) mprotect other -> change any "noaccess" to "defined" */ + make_mem_defined_if_noaccess(a, len); + } else { + /* (3) mprotect NONE -> # no change */ + /* do nothing */ + } } + static void mc_new_mem_startup( Addr a, SizeT len, Bool rr, Bool ww, Bool xx, ULong di_handle ) @@ -4688,10 +4740,11 @@ static Bool mc_expensive_sanity_check ( void ) /*------------------------------------------------------------*/ Bool MC_(clo_partial_loads_ok) = False; -Long MC_(clo_freelist_vol) = 10*1000*1000LL; +Long MC_(clo_freelist_vol) = 20*1000*1000LL; LeakCheckMode MC_(clo_leak_check) = LC_Summary; VgRes MC_(clo_leak_resolution) = Vg_HighRes; Bool MC_(clo_show_reachable) = False; +Bool MC_(clo_show_possibly_lost) = True; Bool MC_(clo_workaround_gcc296_bugs) = False; Int MC_(clo_malloc_fill) = -1; Int MC_(clo_free_fill) = -1; @@ -4700,8 +4753,6 @@ Int MC_(clo_mc_level) = 2; static Bool mc_process_cmd_line_options(Char* arg) { Char* tmp_str; - Char* bad_level_msg = - "ERROR: --track-origins=yes has no effect when --undef-value-errors=no"; tl_assert( MC_(clo_mc_level) >= 1 && MC_(clo_mc_level) <= 3 ); @@ -4716,8 +4767,7 @@ static Bool mc_process_cmd_line_options(Char* arg) */ if (0 == VG_(strcmp)(arg, "--undef-value-errors=no")) { if (MC_(clo_mc_level) == 3) { - VG_(message)(Vg_DebugMsg, "%s\n", bad_level_msg); - return False; + goto bad_level; } else { MC_(clo_mc_level) = 1; return True; @@ -4735,8 +4785,7 @@ static Bool mc_process_cmd_line_options(Char* arg) } if (0 == VG_(strcmp)(arg, "--track-origins=yes")) { if (MC_(clo_mc_level) == 1) { - VG_(message)(Vg_DebugMsg, "%s\n", bad_level_msg); - return False; + goto bad_level; } else { MC_(clo_mc_level) = 3; return True; @@ -4745,6 +4794,8 @@ static Bool mc_process_cmd_line_options(Char* arg) if VG_BOOL_CLO(arg, "--partial-loads-ok", MC_(clo_partial_loads_ok)) {} else if VG_BOOL_CLO(arg, "--show-reachable", MC_(clo_show_reachable)) {} + else if VG_BOOL_CLO(arg, "--show-possibly-lost", + MC_(clo_show_possibly_lost)) {} else if VG_BOOL_CLO(arg, "--workaround-gcc296-bugs", MC_(clo_workaround_gcc296_bugs)) {} @@ -4802,6 +4853,11 @@ static Bool mc_process_cmd_line_options(Char* arg) return VG_(replacement_malloc_process_cmd_line_option)(arg); return True; + + + bad_level: + VG_(fmsg_bad_option)(arg, + "--track-origins=yes has no effect when --undef-value-errors=no.\n"); } static void mc_print_usage(void) @@ -4810,10 +4866,12 @@ static void mc_print_usage(void) " --leak-check=no|summary|full search for memory leaks at exit? [summary]\n" " --leak-resolution=low|med|high differentiation of leak stack traces [high]\n" " --show-reachable=no|yes show reachable blocks in leak check? [no]\n" +" --show-possibly-lost=no|yes show possibly lost blocks in leak check?\n" +" [yes]\n" " --undef-value-errors=no|yes check for undefined value errors [yes]\n" " --track-origins=no|yes show origins of undefined values? [no]\n" " --partial-loads-ok=no|yes too hard to explain here; see manual [no]\n" -" --freelist-vol= volume of freed blocks queue [10000000]\n" +" --freelist-vol= volume of freed blocks queue [20000000]\n" " --workaround-gcc296-bugs=no|yes self explanatory [no]\n" " --ignore-ranges=0xPP-0xQQ[,0xRR-0xSS] assume given addresses are OK\n" " --malloc-fill= fill malloc'd areas with given value\n" @@ -5728,7 +5786,7 @@ static void mc_pre_clo_init(void) VG_(details_version) (NULL); VG_(details_description) ("a memory error detector"); VG_(details_copyright_author)( - "Copyright (C) 2002-2009, and GNU GPL'd, by Julian Seward et al."); + "Copyright (C) 2002-2010, and GNU GPL'd, by Julian Seward et al."); VG_(details_bug_reports_to) (VG_BUGS_TO); VG_(details_avg_translation_sizeB) ( 556 ); @@ -5814,7 +5872,7 @@ static void mc_pre_clo_init(void) // // So we should arguably observe all this. However: // - The current inaccuracy has caused maybe one complaint in seven years(?) - // - Telying on the zeroed-ness of whole brk'd pages is pretty grotty... I + // - Relying on the zeroed-ness of whole brk'd pages is pretty grotty... I // doubt most programmers know the above information. // So I'm not terribly unhappy with marking it as undefined. --njn. // @@ -5824,21 +5882,15 @@ static void mc_pre_clo_init(void) // just mark all memory it allocates as defined.] // VG_(track_new_mem_brk) ( make_mem_undefined_w_tid ); + + // Handling of mmap and mprotect isn't simple (well, it is simple, + // but the justification isn't.) See comments above, just prior to + // mc_new_mem_mmap. VG_(track_new_mem_mmap) ( mc_new_mem_mmap ); + VG_(track_change_mem_mprotect) ( mc_new_mem_mprotect ); VG_(track_copy_mem_remap) ( MC_(copy_address_range_state) ); - // Nb: we don't do anything with mprotect. This means that V bits are - // preserved if a program, for example, marks some memory as inaccessible - // and then later marks it as accessible again. - // - // If an access violation occurs (eg. writing to read-only memory) we let - // it fault and print an informative termination message. This doesn't - // happen if the program catches the signal, though, which is bad. If we - // had two A bits (for readability and writability) that were completely - // distinct from V bits, then we could handle all this properly. - VG_(track_change_mem_mprotect) ( track_perms_change ); - VG_(track_die_mem_stack_signal)( MC_(make_mem_noaccess) ); VG_(track_die_mem_brk) ( MC_(make_mem_noaccess) ); VG_(track_die_mem_munmap) ( MC_(make_mem_noaccess) ); diff --git a/memcheck/mc_malloc_wrappers.c b/memcheck/mc_malloc_wrappers.c index 5d16323..8b0ced6 100644 --- a/memcheck/mc_malloc_wrappers.c +++ b/memcheck/mc_malloc_wrappers.c @@ -8,7 +8,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -120,7 +120,8 @@ static void add_to_freed_queue ( MC_Chunk* mc ) mc1->next = NULL; /* just paranoia */ /* free MC_Chunk */ - VG_(cli_free) ( (void*)(mc1->data) ); + if (MC_AllocCustom != mc1->allockind) + VG_(cli_free) ( (void*)(mc1->data) ); VG_(free) ( mc1 ); } } @@ -290,14 +291,10 @@ void die_and_free_mem ( ThreadId tid, MC_Chunk* mc, SizeT rzB ) accessible with a client request... */ MC_(make_mem_noaccess)( mc->data-rzB, mc->szB + 2*rzB ); - /* Put it out of harm's way for a while, if not from a client request */ - if (MC_AllocCustom != mc->allockind) { - /* Record where freed */ - mc->where = VG_(record_ExeContext) ( tid, 0/*first_ip_delta*/ ); - add_to_freed_queue ( mc ); - } else { - VG_(free) ( mc ); - } + /* Record where freed */ + mc->where = VG_(record_ExeContext) ( tid, 0/*first_ip_delta*/ ); + /* Put it out of harm's way for a while */ + add_to_freed_queue ( mc ); } void MC_(handle_free) ( ThreadId tid, Addr p, UInt rzB, MC_AllocKind kind ) diff --git a/memcheck/mc_replace_strmem.c b/memcheck/mc_replace_strmem.c index 6744b6f..3370888 100644 --- a/memcheck/mc_replace_strmem.c +++ b/memcheck/mc_replace_strmem.c @@ -9,7 +9,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -115,6 +115,7 @@ Bool is_overlap ( void* dst, const void* src, SizeT dstlen, SizeT srclen ) STRRCHR(VG_Z_LIBC_SONAME, strrchr) STRRCHR(VG_Z_LIBC_SONAME, rindex) #if defined(VGO_linux) +STRRCHR(VG_Z_LIBC_SONAME, __GI_strrchr) STRRCHR(VG_Z_LD_LINUX_SO_2, rindex) #elif defined(VGO_freebsd) STRRCHR(VG_Z_LD_ELF_SO_1, strrchr) @@ -142,6 +143,7 @@ STRRCHR(VG_Z_DYLD, rindex) STRCHR(VG_Z_LIBC_SONAME, strchr) STRCHR(VG_Z_LIBC_SONAME, index) #if defined(VGO_linux) +STRCHR(VG_Z_LIBC_SONAME, __GI_strchr) STRCHR(VG_Z_LD_LINUX_SO_2, strchr) STRCHR(VG_Z_LD_LINUX_SO_2, index) STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, strchr) @@ -181,7 +183,9 @@ STRCAT(VG_Z_LIBC_SONAME, strcat) STRCAT(VG_Z_LD_ELF_SO_1, strcat) STRCAT(VG_Z_LD_ELF32_SO_1, strcat) #endif - +#if defined(VGO_linux) +STRCAT(VG_Z_LIBC_SONAME, __GI_strcat) +#endif #define STRNCAT(soname, fnname) \ char* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ @@ -269,6 +273,9 @@ STRLCAT(VG_Z_LD_ELF32_SO_1, strlcat) } STRNLEN(VG_Z_LIBC_SONAME, strnlen) +#if defined(VGO_linux) +STRNLEN(VG_Z_LIBC_SONAME, __GI_strnlen) +#endif // Note that this replacement often doesn't get used because gcc inlines @@ -286,6 +293,7 @@ STRNLEN(VG_Z_LIBC_SONAME, strnlen) STRLEN(VG_Z_LIBC_SONAME, strlen) #if defined(VGO_linux) +STRLEN(VG_Z_LIBC_SONAME, __GI_strlen) STRLEN(VG_Z_LD_LINUX_SO_2, strlen) STRLEN(VG_Z_LD_LINUX_X86_64_SO_2, strlen) #elif defined(VGO_freebsd) @@ -316,7 +324,9 @@ STRLEN(VG_Z_LD_ELF32_SO_1, strlen) } STRCPY(VG_Z_LIBC_SONAME, strcpy) -#if defined(VGO_darwin) +#if defined(VGO_linux) +STRCPY(VG_Z_LIBC_SONAME, __GI_strcpy) +#elif defined(VGO_darwin) STRCPY(VG_Z_DYLD, strcpy) #elif defined(VGO_freebsd) STRCPY(VG_Z_LD_ELF_SO_1, strcpy) @@ -345,7 +355,9 @@ STRCPY(VG_Z_LD_ELF32_SO_1, strcpy) } STRNCPY(VG_Z_LIBC_SONAME, strncpy) -#if defined(VGO_darwin) +#if defined(VGO_linux) +STRNCPY(VG_Z_LIBC_SONAME, __GI_strncpy) +#elif defined(VGO_darwin) STRNCPY(VG_Z_DYLD, strncpy) #elif defined(VGO_freebsd) STRNCPY(VG_Z_LD_ELF_SO_1, strncpy) @@ -408,7 +420,9 @@ STRLCPY(VG_Z_LD_ELF32_SO_1, strlcpy) } STRNCMP(VG_Z_LIBC_SONAME, strncmp) -#if defined(VGO_darwin) +#if defined(VGO_linux) +STRNCMP(VG_Z_LIBC_SONAME, __GI_strncmp) +#elif defined(VGO_darwin) STRNCMP(VG_Z_DYLD, strncmp) #elif defined(VGO_freebsd) STRNCMP(VG_Z_LD_ELF_SO_1, strncmp) @@ -438,6 +452,7 @@ STRNCMP(VG_Z_LD_ELF32_SO_1, strncmp) STRCMP(VG_Z_LIBC_SONAME, strcmp) #if defined(VGO_linux) +STRCMP(VG_Z_LIBC_SONAME, __GI_strcmp) STRCMP(VG_Z_LD_LINUX_X86_64_SO_2, strcmp) STRCMP(VG_Z_LD64_SO_1, strcmp) #elif defined(VGO_freebsd) @@ -473,42 +488,68 @@ MEMCHR(VG_Z_LD_ELF32_SO_1, memchr) void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ ( void *dst, const void *src, SizeT len ) \ { \ - register char *d; \ - register char *s; \ - \ - if (len == 0) \ - return dst; \ - \ if (is_overlap(dst, src, len, len)) \ RECORD_OVERLAP_ERROR("memcpy", dst, src, len); \ \ - if ( dst > src ) { \ - d = (char *)dst + len - 1; \ - s = (char *)src + len - 1; \ - while ( len >= 4 ) { \ - *d-- = *s--; \ - *d-- = *s--; \ - *d-- = *s--; \ - *d-- = *s--; \ - len -= 4; \ + const Addr WS = sizeof(UWord); /* 8 or 4 */ \ + const Addr WM = WS - 1; /* 7 or 3 */ \ + \ + if (dst < src) { \ + \ + /* Copying backwards. */ \ + SizeT n = len; \ + Addr d = (Addr)dst; \ + Addr s = (Addr)src; \ + \ + if (((s^d) & WM) == 0) { \ + /* s and d have same UWord alignment. */ \ + /* Pull up to a UWord boundary. */ \ + while ((s & WM) != 0 && n >= 1) \ + { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \ + /* Copy UWords. */ \ + while (n >= WS) \ + { *(UWord*)d = *(UWord*)s; s += WS; d += WS; n -= WS; } \ + if (n == 0) \ + return dst; \ } \ - while ( len-- ) { \ - *d-- = *s--; \ + if (((s|d) & 1) == 0) { \ + /* Both are 16-aligned; copy what we can thusly. */ \ + while (n >= 2) \ + { *(UShort*)d = *(UShort*)s; s += 2; d += 2; n -= 2; } \ } \ - } else if ( dst < src ) { \ - d = (char *)dst; \ - s = (char *)src; \ - while ( len >= 4 ) { \ - *d++ = *s++; \ - *d++ = *s++; \ - *d++ = *s++; \ - *d++ = *s++; \ - len -= 4; \ + /* Copy leftovers, or everything if misaligned. */ \ + while (n >= 1) \ + { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \ + \ + } else if (dst > src) { \ + \ + SizeT n = len; \ + Addr d = ((Addr)dst) + n; \ + Addr s = ((Addr)src) + n; \ + \ + /* Copying forwards. */ \ + if (((s^d) & WM) == 0) { \ + /* s and d have same UWord alignment. */ \ + /* Back down to a UWord boundary. */ \ + while ((s & WM) != 0 && n >= 1) \ + { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \ + /* Copy UWords. */ \ + while (n >= WS) \ + { s -= WS; d -= WS; *(UWord*)d = *(UWord*)s; n -= WS; } \ + if (n == 0) \ + return dst; \ } \ - while ( len-- ) { \ - *d++ = *s++; \ + if (((s|d) & 1) == 0) { \ + /* Both are 16-aligned; copy what we can thusly. */ \ + while (n >= 2) \ + { s -= 2; d -= 2; *(UShort*)d = *(UShort*)s; n -= 2; } \ } \ + /* Copy leftovers, or everything if misaligned. */ \ + while (n >= 1) \ + { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \ + \ } \ + \ return dst; \ } @@ -593,6 +634,7 @@ MEMCMP(VG_Z_DYLD, bcmp) STPCPY(VG_Z_LIBC_SONAME, stpcpy) #if defined(VGO_linux) +STPCPY(VG_Z_LIBC_SONAME, __GI_stpcpy) STPCPY(VG_Z_LD_LINUX_SO_2, stpcpy) STPCPY(VG_Z_LD_LINUX_X86_64_SO_2, stpcpy) #elif defined(VGO_freebsd) @@ -607,18 +649,16 @@ STPCPY(VG_Z_DYLD, stpcpy) void* VG_REPLACE_FUNCTION_ZU(soname,fnname)(void *s, Int c, SizeT n); \ void* VG_REPLACE_FUNCTION_ZU(soname,fnname)(void *s, Int c, SizeT n) \ { \ - unsigned char *cp = s; \ - while (n >= 4) { \ - cp[0] = c; \ - cp[1] = c; \ - cp[2] = c; \ - cp[3] = c; \ - cp += 4; \ - n -= 4; \ - } \ - while (n--) { \ - *cp++ = c; \ - } \ + Addr a = (Addr)s; \ + UInt c4 = (c & 0xFF); \ + c4 = (c4 << 8) | c4; \ + c4 = (c4 << 16) | c4; \ + while ((a & 3) != 0 && n >= 1) \ + { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ + while (n >= 4) \ + { *(UInt*)a = c4; a += 4; n -= 4; } \ + while (n >= 1) \ + { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ return s; \ } @@ -757,7 +797,9 @@ GLIBC232_STRCHRNUL(VG_Z_LIBC_SONAME, strchrnul) } GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, rawmemchr) - +#if defined (VGO_linux) +GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, __GI___rawmemchr) +#endif /* glibc variant of strcpy that checks the dest is big enough. Copied from glibc-2.5/debug/test-strcpy_chk.c. */ @@ -897,6 +939,153 @@ GLIBC25_MEMPCPY(VG_Z_LD_SO_1, mempcpy) /* ld.so.1 */ GLIBC26___MEMCPY_CHK(VG_Z_LIBC_SONAME, __memcpy_chk) +#define STRSTR(soname, fnname) \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* haystack, void* needle); \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* haystack, void* needle) \ + { \ + UChar* h = (UChar*)haystack; \ + UChar* n = (UChar*)needle; \ + \ + /* find the length of n, not including terminating zero */ \ + UWord nlen = 0; \ + while (n[nlen]) nlen++; \ + \ + /* if n is the empty string, match immediately. */ \ + if (nlen == 0) return h; \ + \ + /* assert(nlen >= 1); */ \ + UChar n0 = n[0]; \ + \ + while (1) { \ + UChar hh = *h; \ + if (hh == 0) return NULL; \ + if (hh != n0) { h++; continue; } \ + \ + UWord i; \ + for (i = 0; i < nlen; i++) { \ + if (n[i] != h[i]) \ + break; \ + } \ + /* assert(i >= 0 && i <= nlen); */ \ + if (i == nlen) \ + return h; \ + \ + h++; \ + } \ + } + +#if defined(VGO_linux) +STRSTR(VG_Z_LIBC_SONAME, strstr) +#endif + + +#define STRPBRK(soname, fnname) \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* sV, void* acceptV); \ + void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* sV, void* acceptV) \ + { \ + UChar* s = (UChar*)sV; \ + UChar* accept = (UChar*)acceptV; \ + \ + /* find the length of 'accept', not including terminating zero */ \ + UWord nacc = 0; \ + while (accept[nacc]) nacc++; \ + \ + /* if n is the empty string, fail immediately. */ \ + if (nacc == 0) return NULL; \ + \ + /* assert(nacc >= 1); */ \ + while (1) { \ + UWord i; \ + UChar sc = *s; \ + if (sc == 0) \ + break; \ + for (i = 0; i < nacc; i++) { \ + if (sc == accept[i]) \ + return s; \ + } \ + s++; \ + } \ + \ + return NULL; \ + } + +#if defined(VGO_linux) +STRPBRK(VG_Z_LIBC_SONAME, strpbrk) +#endif + + +#define STRCSPN(soname, fnname) \ + SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* sV, void* rejectV); \ + SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname) \ + (void* sV, void* rejectV) \ + { \ + UChar* s = (UChar*)sV; \ + UChar* reject = (UChar*)rejectV; \ + \ + /* find the length of 'reject', not including terminating zero */ \ + UWord nrej = 0; \ + while (reject[nrej]) nrej++; \ + \ + UWord len = 0; \ + while (1) { \ + UWord i; \ + UChar sc = *s; \ + if (sc == 0) \ + break; \ + for (i = 0; i < nrej; i++) { \ + if (sc == reject[i]) \ + break; \ + } \ + /* assert(i >= 0 && i <= nrej); */ \ + if (i < nrej) \ + break; \ + s++; \ + len++; \ + } \ + \ + return len; \ + } + +#if defined(VGO_linux) +STRCSPN(VG_Z_LIBC_SONAME, strcspn) +#endif + + +// And here's a validated strspn replacement, should it +// become necessary. +//UWord mystrspn( UChar* s, UChar* accept ) +//{ +// /* find the length of 'accept', not including terminating zero */ +// UWord nacc = 0; +// while (accept[nacc]) nacc++; +// if (nacc == 0) return 0; +// +// UWord len = 0; +// while (1) { +// UWord i; +// UChar sc = *s; +// if (sc == 0) +// break; +// for (i = 0; i < nacc; i++) { +// if (sc == accept[i]) +// break; +// } +// assert(i >= 0 && i <= nacc); +// if (i == nacc) +// break; +// s++; +// len++; +// } +// +// return len; +//} + + /*------------------------------------------------------------*/ /*--- Improve definedness checking of process environment ---*/ /*------------------------------------------------------------*/ diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index de570ab..50f2d49 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -8,7 +8,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward + Copyright (C) 2000-2010 Julian Seward jseward@acm.org This program is free software; you can redistribute it and/or @@ -398,6 +398,8 @@ void assign ( HChar cat, MCEnv* mce, IRTemp tmp, IRExpr* expr ) { } /* build various kinds of expressions */ +#define triop(_op, _arg1, _arg2, _arg3) \ + IRExpr_Triop((_op),(_arg1),(_arg2),(_arg3)) #define binop(_op, _arg1, _arg2) IRExpr_Binop((_op),(_arg1),(_arg2)) #define unop(_op, _arg) IRExpr_Unop((_op),(_arg)) #define mkU8(_n) IRExpr_Const(IRConst_U8(_n)) @@ -1392,7 +1394,7 @@ IRAtom* mkLazy3 ( MCEnv* mce, IRType finalVty, /* I32 x I64 x I64 -> I32 */ if (t1 == Ity_I32 && t2 == Ity_I64 && t3 == Ity_I64 && finalVty == Ity_I32) { - if (0) VG_(printf)("mkLazy3: I32 x I64 x I64 -> I64\n"); + if (0) VG_(printf)("mkLazy3: I32 x I64 x I64 -> I32\n"); at = mkPCastTo(mce, Ity_I64, va1); at = mkUifU(mce, Ity_I64, at, va2); at = mkUifU(mce, Ity_I64, at, va3); @@ -1400,6 +1402,18 @@ IRAtom* mkLazy3 ( MCEnv* mce, IRType finalVty, return at; } + /* I32 x I32 x I32 -> I32 */ + /* 32-bit FP idiom, as (eg) happens on ARM */ + if (t1 == Ity_I32 && t2 == Ity_I32 && t3 == Ity_I32 + && finalVty == Ity_I32) { + if (0) VG_(printf)("mkLazy3: I32 x I32 x I32 -> I32\n"); + at = va1; + at = mkUifU(mce, Ity_I32, at, va2); + at = mkUifU(mce, Ity_I32, at, va3); + at = mkPCastTo(mce, Ity_I32, at); + return at; + } + if (1) { VG_(printf)("mkLazy3: "); ppIRType(t1); @@ -1710,6 +1724,16 @@ static IRAtom* mkPCast8x8 ( MCEnv* mce, IRAtom* at ) return assignNew('V', mce, Ity_I64, unop(Iop_CmpNEZ8x8, at)); } +static IRAtom* mkPCast16x2 ( MCEnv* mce, IRAtom* at ) +{ + return assignNew('V', mce, Ity_I32, unop(Iop_CmpNEZ16x2, at)); +} + +static IRAtom* mkPCast8x4 ( MCEnv* mce, IRAtom* at ) +{ + return assignNew('V', mce, Ity_I32, unop(Iop_CmpNEZ8x4, at)); +} + /* Here's a simple scheme capable of handling ops derived from SSE1 code and while only generating ops that can be efficiently @@ -1837,6 +1861,28 @@ IRAtom* unary64F0x2 ( MCEnv* mce, IRAtom* vatomX ) return at; } +/* --- --- ... and ... 32Fx2 versions of the same --- --- */ + +static +IRAtom* binary32Fx2 ( MCEnv* mce, IRAtom* vatomX, IRAtom* vatomY ) +{ + IRAtom* at; + tl_assert(isShadowAtom(mce, vatomX)); + tl_assert(isShadowAtom(mce, vatomY)); + at = mkUifU64(mce, vatomX, vatomY); + at = assignNew('V', mce, Ity_I64, mkPCast32x2(mce, at)); + return at; +} + +static +IRAtom* unary32Fx2 ( MCEnv* mce, IRAtom* vatomX ) +{ + IRAtom* at; + tl_assert(isShadowAtom(mce, vatomX)); + at = assignNew('V', mce, Ity_I64, mkPCast32x2(mce, vatomX)); + return at; +} + /* --- --- Vector saturated narrowing --- --- */ /* This is quite subtle. What to do is simple: @@ -1906,6 +1952,54 @@ IRAtom* vectorNarrow64 ( MCEnv* mce, IROp narrow_op, return at3; } +static +IRAtom* vectorShortenV128 ( MCEnv* mce, IROp shorten_op, + IRAtom* vatom1) +{ + IRAtom *at1, *at2; + IRAtom* (*pcast)( MCEnv*, IRAtom* ); + switch (shorten_op) { + case Iop_Shorten16x8: pcast = mkPCast16x8; break; + case Iop_Shorten32x4: pcast = mkPCast32x4; break; + case Iop_Shorten64x2: pcast = mkPCast64x2; break; + case Iop_QShortenS16Sx8: pcast = mkPCast16x8; break; + case Iop_QShortenU16Sx8: pcast = mkPCast16x8; break; + case Iop_QShortenU16Ux8: pcast = mkPCast16x8; break; + case Iop_QShortenS32Sx4: pcast = mkPCast32x4; break; + case Iop_QShortenU32Sx4: pcast = mkPCast32x4; break; + case Iop_QShortenU32Ux4: pcast = mkPCast32x4; break; + case Iop_QShortenS64Sx2: pcast = mkPCast64x2; break; + case Iop_QShortenU64Sx2: pcast = mkPCast64x2; break; + case Iop_QShortenU64Ux2: pcast = mkPCast64x2; break; + default: VG_(tool_panic)("vectorShortenV128"); + } + tl_assert(isShadowAtom(mce,vatom1)); + at1 = assignNew('V', mce, Ity_V128, pcast(mce, vatom1)); + at2 = assignNew('V', mce, Ity_I64, unop(shorten_op, at1)); + return at2; +} + +static +IRAtom* vectorLongenI64 ( MCEnv* mce, IROp longen_op, + IRAtom* vatom1) +{ + IRAtom *at1, *at2; + IRAtom* (*pcast)( MCEnv*, IRAtom* ); + switch (longen_op) { + case Iop_Longen8Ux8: pcast = mkPCast16x8; break; + case Iop_Longen8Sx8: pcast = mkPCast16x8; break; + case Iop_Longen16Ux4: pcast = mkPCast32x4; break; + case Iop_Longen16Sx4: pcast = mkPCast32x4; break; + case Iop_Longen32Ux2: pcast = mkPCast64x2; break; + case Iop_Longen32Sx2: pcast = mkPCast64x2; break; + default: VG_(tool_panic)("vectorLongenI64"); + } + tl_assert(isShadowAtom(mce,vatom1)); + at1 = assignNew('V', mce, Ity_V128, unop(longen_op, vatom1)); + at2 = assignNew('V', mce, Ity_V128, pcast(mce, at1)); + return at2; +} + /* --- --- Vector integer arithmetic --- --- */ @@ -1978,6 +2072,35 @@ IRAtom* binary32Ix2 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 ) return at; } +static +IRAtom* binary64Ix1 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 ) +{ + IRAtom* at; + at = mkUifU64(mce, vatom1, vatom2); + at = mkPCastTo(mce, Ity_I64, at); + return at; +} + +/* --- 32-bit versions --- */ + +static +IRAtom* binary8Ix4 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 ) +{ + IRAtom* at; + at = mkUifU32(mce, vatom1, vatom2); + at = mkPCast8x4(mce, at); + return at; +} + +static +IRAtom* binary16Ix2 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 ) +{ + IRAtom* at; + at = mkUifU32(mce, vatom1, vatom2); + at = mkPCast16x2(mce, at); + return at; +} + /*------------------------------------------------------------*/ /*--- Generate shadow values from all kinds of IRExprs. ---*/ @@ -2059,6 +2182,23 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, case Iop_PRem1C3210F64: /* I32(rm) x F64 x F64 -> I32 */ return mkLazy3(mce, Ity_I32, vatom1, vatom2, vatom3); + case Iop_AddF32: + case Iop_SubF32: + case Iop_MulF32: + case Iop_DivF32: + /* I32(rm) x F32 x F32 -> I32 */ + return mkLazy3(mce, Ity_I32, vatom1, vatom2, vatom3); + case Iop_ExtractV128: + complainIfUndefined(mce, atom3); + return assignNew('V', mce, Ity_V128, triop(op, vatom1, vatom2, atom3)); + case Iop_Extract64: + complainIfUndefined(mce, atom3); + return assignNew('V', mce, Ity_I64, triop(op, vatom1, vatom2, atom3)); + case Iop_SetElem8x8: + case Iop_SetElem16x4: + case Iop_SetElem32x2: + complainIfUndefined(mce, atom2); + return assignNew('V', mce, Ity_I64, triop(op, vatom1, atom2, vatom3)); default: ppIROp(op); VG_(tool_panic)("memcheck:expr2vbits_Triop"); @@ -2087,8 +2227,33 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, tl_assert(sameKindedAtoms(atom2,vatom2)); switch (op) { + /* 32-bit SIMD */ + + case Iop_Add16x2: + case Iop_HAdd16Ux2: + case Iop_HAdd16Sx2: + case Iop_Sub16x2: + case Iop_HSub16Ux2: + case Iop_HSub16Sx2: + case Iop_QAdd16Sx2: + case Iop_QSub16Sx2: + return binary16Ix2(mce, vatom1, vatom2); + + case Iop_Add8x4: + case Iop_HAdd8Ux4: + case Iop_HAdd8Sx4: + case Iop_Sub8x4: + case Iop_HSub8Ux4: + case Iop_HSub8Sx4: + case Iop_QSub8Ux4: + case Iop_QAdd8Ux4: + case Iop_QSub8Sx4: + case Iop_QAdd8Sx4: + return binary8Ix4(mce, vatom1, vatom2); + /* 64-bit SIMD */ + case Iop_ShrN8x8: case Iop_ShrN16x4: case Iop_ShrN32x2: case Iop_SarN8x8: @@ -2107,20 +2272,29 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, return vectorNarrow64(mce, op, vatom1, vatom2); case Iop_Min8Ux8: + case Iop_Min8Sx8: case Iop_Max8Ux8: + case Iop_Max8Sx8: case Iop_Avg8Ux8: case Iop_QSub8Sx8: case Iop_QSub8Ux8: case Iop_Sub8x8: case Iop_CmpGT8Sx8: + case Iop_CmpGT8Ux8: case Iop_CmpEQ8x8: case Iop_QAdd8Sx8: case Iop_QAdd8Ux8: + case Iop_QSal8x8: + case Iop_QShl8x8: case Iop_Add8x8: + case Iop_Mul8x8: + case Iop_PolynomialMul8x8: return binary8Ix8(mce, vatom1, vatom2); case Iop_Min16Sx4: + case Iop_Min16Ux4: case Iop_Max16Sx4: + case Iop_Max16Ux4: case Iop_Avg16Ux4: case Iop_QSub16Ux4: case Iop_QSub16Sx4: @@ -2129,19 +2303,136 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_MulHi16Sx4: case Iop_MulHi16Ux4: case Iop_CmpGT16Sx4: + case Iop_CmpGT16Ux4: case Iop_CmpEQ16x4: case Iop_QAdd16Sx4: case Iop_QAdd16Ux4: + case Iop_QSal16x4: + case Iop_QShl16x4: case Iop_Add16x4: + case Iop_QDMulHi16Sx4: + case Iop_QRDMulHi16Sx4: return binary16Ix4(mce, vatom1, vatom2); case Iop_Sub32x2: case Iop_Mul32x2: + case Iop_Max32Sx2: + case Iop_Max32Ux2: + case Iop_Min32Sx2: + case Iop_Min32Ux2: case Iop_CmpGT32Sx2: + case Iop_CmpGT32Ux2: case Iop_CmpEQ32x2: case Iop_Add32x2: + case Iop_QAdd32Ux2: + case Iop_QAdd32Sx2: + case Iop_QSub32Ux2: + case Iop_QSub32Sx2: + case Iop_QSal32x2: + case Iop_QShl32x2: + case Iop_QDMulHi32Sx2: + case Iop_QRDMulHi32Sx2: return binary32Ix2(mce, vatom1, vatom2); + case Iop_QSub64Ux1: + case Iop_QSub64Sx1: + case Iop_QAdd64Ux1: + case Iop_QAdd64Sx1: + case Iop_QSal64x1: + case Iop_QShl64x1: + case Iop_Sal64x1: + return binary64Ix1(mce, vatom1, vatom2); + + case Iop_QShlN8Sx8: + case Iop_QShlN8x8: + case Iop_QSalN8x8: + complainIfUndefined(mce, atom2); + return mkPCast8x8(mce, vatom1); + + case Iop_QShlN16Sx4: + case Iop_QShlN16x4: + case Iop_QSalN16x4: + complainIfUndefined(mce, atom2); + return mkPCast16x4(mce, vatom1); + + case Iop_QShlN32Sx2: + case Iop_QShlN32x2: + case Iop_QSalN32x2: + complainIfUndefined(mce, atom2); + return mkPCast32x2(mce, vatom1); + + case Iop_QShlN64Sx1: + case Iop_QShlN64x1: + case Iop_QSalN64x1: + complainIfUndefined(mce, atom2); + return mkPCast32x2(mce, vatom1); + + case Iop_PwMax32Sx2: + case Iop_PwMax32Ux2: + case Iop_PwMin32Sx2: + case Iop_PwMin32Ux2: + case Iop_PwMax32Fx2: + case Iop_PwMin32Fx2: + return assignNew('V', mce, Ity_I64, binop(Iop_PwMax32Ux2, mkPCast32x2(mce, vatom1), + mkPCast32x2(mce, vatom2))); + + case Iop_PwMax16Sx4: + case Iop_PwMax16Ux4: + case Iop_PwMin16Sx4: + case Iop_PwMin16Ux4: + return assignNew('V', mce, Ity_I64, binop(Iop_PwMax16Ux4, mkPCast16x4(mce, vatom1), + mkPCast16x4(mce, vatom2))); + + case Iop_PwMax8Sx8: + case Iop_PwMax8Ux8: + case Iop_PwMin8Sx8: + case Iop_PwMin8Ux8: + return assignNew('V', mce, Ity_I64, binop(Iop_PwMax8Ux8, mkPCast8x8(mce, vatom1), + mkPCast8x8(mce, vatom2))); + + case Iop_PwAdd32x2: + case Iop_PwAdd32Fx2: + return mkPCast32x2(mce, + assignNew('V', mce, Ity_I64, binop(Iop_PwAdd32x2, mkPCast32x2(mce, vatom1), + mkPCast32x2(mce, vatom2)))); + + case Iop_PwAdd16x4: + return mkPCast16x4(mce, + assignNew('V', mce, Ity_I64, binop(op, mkPCast16x4(mce, vatom1), + mkPCast16x4(mce, vatom2)))); + + case Iop_PwAdd8x8: + return mkPCast8x8(mce, + assignNew('V', mce, Ity_I64, binop(op, mkPCast8x8(mce, vatom1), + mkPCast8x8(mce, vatom2)))); + + case Iop_Shl8x8: + case Iop_Shr8x8: + case Iop_Sar8x8: + case Iop_Sal8x8: + return mkUifU64(mce, + assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2)), + mkPCast8x8(mce,vatom2) + ); + + case Iop_Shl16x4: + case Iop_Shr16x4: + case Iop_Sar16x4: + case Iop_Sal16x4: + return mkUifU64(mce, + assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2)), + mkPCast16x4(mce,vatom2) + ); + + case Iop_Shl32x2: + case Iop_Shr32x2: + case Iop_Sar32x2: + case Iop_Sal32x2: + return mkUifU64(mce, + assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2)), + mkPCast32x2(mce,vatom2) + ); + /* 64-bit data-steering */ case Iop_InterleaveLO32x2: case Iop_InterleaveLO16x4: @@ -2149,10 +2440,26 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_InterleaveHI32x2: case Iop_InterleaveHI16x4: case Iop_InterleaveHI8x8: + case Iop_CatOddLanes8x8: + case Iop_CatEvenLanes8x8: case Iop_CatOddLanes16x4: case Iop_CatEvenLanes16x4: + case Iop_InterleaveOddLanes8x8: + case Iop_InterleaveEvenLanes8x8: + case Iop_InterleaveOddLanes16x4: + case Iop_InterleaveEvenLanes16x4: return assignNew('V', mce, Ity_I64, binop(op, vatom1, vatom2)); + case Iop_GetElem8x8: + complainIfUndefined(mce, atom2); + return assignNew('V', mce, Ity_I8, binop(op, vatom1, atom2)); + case Iop_GetElem16x4: + complainIfUndefined(mce, atom2); + return assignNew('V', mce, Ity_I16, binop(op, vatom1, atom2)); + case Iop_GetElem32x2: + complainIfUndefined(mce, atom2); + return assignNew('V', mce, Ity_I32, binop(op, vatom1, atom2)); + /* Perm8x8: rearrange values in left arg using steering values from right arg. So rearrange the vbits in the same way but pessimise wrt steering values. */ @@ -2165,16 +2472,18 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, /* V128-bit SIMD */ + case Iop_ShrN8x16: case Iop_ShrN16x8: case Iop_ShrN32x4: case Iop_ShrN64x2: + case Iop_SarN8x16: case Iop_SarN16x8: case Iop_SarN32x4: + case Iop_SarN64x2: + case Iop_ShlN8x16: case Iop_ShlN16x8: case Iop_ShlN32x4: case Iop_ShlN64x2: - case Iop_ShlN8x16: - case Iop_SarN8x16: /* Same scheme as with all other shifts. Note: 22 Oct 05: this is wrong now, scalar shifts are done properly lazily. Vector shifts should be fixed too. */ @@ -2185,6 +2494,7 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_Shl8x16: case Iop_Shr8x16: case Iop_Sar8x16: + case Iop_Sal8x16: case Iop_Rol8x16: return mkUifUV128(mce, assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)), @@ -2194,6 +2504,7 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_Shl16x8: case Iop_Shr16x8: case Iop_Sar16x8: + case Iop_Sal16x8: case Iop_Rol16x8: return mkUifUV128(mce, assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)), @@ -2203,12 +2514,36 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_Shl32x4: case Iop_Shr32x4: case Iop_Sar32x4: + case Iop_Sal32x4: case Iop_Rol32x4: return mkUifUV128(mce, assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)), mkPCast32x4(mce,vatom2) ); + case Iop_Shl64x2: + case Iop_Shr64x2: + case Iop_Sar64x2: + case Iop_Sal64x2: + return mkUifUV128(mce, + assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)), + mkPCast64x2(mce,vatom2) + ); + + case Iop_F32ToFixed32Ux4_RZ: + case Iop_F32ToFixed32Sx4_RZ: + case Iop_Fixed32UToF32x4_RN: + case Iop_Fixed32SToF32x4_RN: + complainIfUndefined(mce, atom2); + return mkPCast32x4(mce, vatom1); + + case Iop_F32ToFixed32Ux2_RZ: + case Iop_F32ToFixed32Sx2_RZ: + case Iop_Fixed32UToF32x2_RN: + case Iop_Fixed32SToF32x2_RN: + complainIfUndefined(mce, atom2); + return mkPCast32x2(mce, vatom1); + case Iop_QSub8Ux16: case Iop_QSub8Sx16: case Iop_Sub8x16: @@ -2223,7 +2558,11 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_Avg8Sx16: case Iop_QAdd8Ux16: case Iop_QAdd8Sx16: + case Iop_QSal8x16: + case Iop_QShl8x16: case Iop_Add8x16: + case Iop_Mul8x16: + case Iop_PolynomialMul8x16: return binary8Ix16(mce, vatom1, vatom2); case Iop_QSub16Ux8: @@ -2243,7 +2582,11 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_Avg16Sx8: case Iop_QAdd16Ux8: case Iop_QAdd16Sx8: + case Iop_QSal16x8: + case Iop_QShl16x8: case Iop_Add16x8: + case Iop_QDMulHi16Sx8: + case Iop_QRDMulHi16Sx8: return binary16Ix8(mce, vatom1, vatom2); case Iop_Sub32x4: @@ -2254,6 +2597,8 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_QAdd32Ux4: case Iop_QSub32Sx4: case Iop_QSub32Ux4: + case Iop_QSal32x4: + case Iop_QShl32x4: case Iop_Avg32Ux4: case Iop_Avg32Sx4: case Iop_Add32x4: @@ -2261,10 +2606,20 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_Max32Sx4: case Iop_Min32Ux4: case Iop_Min32Sx4: + case Iop_Mul32x4: + case Iop_QDMulHi32Sx4: + case Iop_QRDMulHi32Sx4: return binary32Ix4(mce, vatom1, vatom2); case Iop_Sub64x2: case Iop_Add64x2: + case Iop_CmpGT64Sx2: + case Iop_QSal64x2: + case Iop_QShl64x2: + case Iop_QAdd64Ux2: + case Iop_QAdd64Sx2: + case Iop_QSub64Ux2: + case Iop_QSub64Sx2: return binary64Ix2(mce, vatom1, vatom2); case Iop_QNarrow32Sx4: @@ -2309,8 +2664,22 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_CmpGT32Fx4: case Iop_CmpGE32Fx4: case Iop_Add32Fx4: + case Iop_Recps32Fx4: + case Iop_Rsqrts32Fx4: return binary32Fx4(mce, vatom1, vatom2); + case Iop_Sub32Fx2: + case Iop_Mul32Fx2: + case Iop_Min32Fx2: + case Iop_Max32Fx2: + case Iop_CmpEQ32Fx2: + case Iop_CmpGT32Fx2: + case Iop_CmpGE32Fx2: + case Iop_Add32Fx2: + case Iop_Recps32Fx2: + case Iop_Rsqrts32Fx2: + return binary32Fx2(mce, vatom1, vatom2); + case Iop_Sub32F0x4: case Iop_Mul32F0x4: case Iop_Min32F0x4: @@ -2323,6 +2692,63 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_Add32F0x4: return binary32F0x4(mce, vatom1, vatom2); + case Iop_QShlN8Sx16: + case Iop_QShlN8x16: + case Iop_QSalN8x16: + complainIfUndefined(mce, atom2); + return mkPCast8x16(mce, vatom1); + + case Iop_QShlN16Sx8: + case Iop_QShlN16x8: + case Iop_QSalN16x8: + complainIfUndefined(mce, atom2); + return mkPCast16x8(mce, vatom1); + + case Iop_QShlN32Sx4: + case Iop_QShlN32x4: + case Iop_QSalN32x4: + complainIfUndefined(mce, atom2); + return mkPCast32x4(mce, vatom1); + + case Iop_QShlN64Sx2: + case Iop_QShlN64x2: + case Iop_QSalN64x2: + complainIfUndefined(mce, atom2); + return mkPCast32x4(mce, vatom1); + + case Iop_Mull32Sx2: + case Iop_Mull32Ux2: + case Iop_QDMulLong32Sx2: + return vectorLongenI64(mce, Iop_Longen32Sx2, + mkUifU64(mce, vatom1, vatom2)); + + case Iop_Mull16Sx4: + case Iop_Mull16Ux4: + case Iop_QDMulLong16Sx4: + return vectorLongenI64(mce, Iop_Longen16Sx4, + mkUifU64(mce, vatom1, vatom2)); + + case Iop_Mull8Sx8: + case Iop_Mull8Ux8: + case Iop_PolynomialMull8x8: + return vectorLongenI64(mce, Iop_Longen8Sx8, + mkUifU64(mce, vatom1, vatom2)); + + case Iop_PwAdd32x4: + return mkPCast32x4(mce, + assignNew('V', mce, Ity_V128, binop(op, mkPCast32x4(mce, vatom1), + mkPCast32x4(mce, vatom2)))); + + case Iop_PwAdd16x8: + return mkPCast16x8(mce, + assignNew('V', mce, Ity_V128, binop(op, mkPCast16x8(mce, vatom1), + mkPCast16x8(mce, vatom2)))); + + case Iop_PwAdd8x16: + return mkPCast8x16(mce, + assignNew('V', mce, Ity_V128, binop(op, mkPCast8x16(mce, vatom1), + mkPCast8x16(mce, vatom2)))); + /* V128-bit data-steering */ case Iop_SetV128lo32: case Iop_SetV128lo64: @@ -2335,8 +2761,33 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_InterleaveHI32x4: case Iop_InterleaveHI16x8: case Iop_InterleaveHI8x16: + case Iop_CatOddLanes8x16: + case Iop_CatOddLanes16x8: + case Iop_CatOddLanes32x4: + case Iop_CatEvenLanes8x16: + case Iop_CatEvenLanes16x8: + case Iop_CatEvenLanes32x4: + case Iop_InterleaveOddLanes8x16: + case Iop_InterleaveOddLanes16x8: + case Iop_InterleaveOddLanes32x4: + case Iop_InterleaveEvenLanes8x16: + case Iop_InterleaveEvenLanes16x8: + case Iop_InterleaveEvenLanes32x4: return assignNew('V', mce, Ity_V128, binop(op, vatom1, vatom2)); - + + case Iop_GetElem8x16: + complainIfUndefined(mce, atom2); + return assignNew('V', mce, Ity_I8, binop(op, vatom1, atom2)); + case Iop_GetElem16x8: + complainIfUndefined(mce, atom2); + return assignNew('V', mce, Ity_I16, binop(op, vatom1, atom2)); + case Iop_GetElem32x4: + complainIfUndefined(mce, atom2); + return assignNew('V', mce, Ity_I32, binop(op, vatom1, atom2)); + case Iop_GetElem64x2: + complainIfUndefined(mce, atom2); + return assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2)); + /* Perm8x16: rearrange values in left arg using steering values from right arg. So rearrange the vbits in the same way but pessimise wrt steering values. */ @@ -2398,8 +2849,8 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_RoundF64toInt: case Iop_RoundF64toF32: - case Iop_F64toI64: - case Iop_I64toF64: + case Iop_F64toI64S: + case Iop_I64StoF64: case Iop_SinF64: case Iop_CosF64: case Iop_TanF64: @@ -2408,12 +2859,18 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, /* I32(rm) x I64/F64 -> I64/F64 */ return mkLazy2(mce, Ity_I64, vatom1, vatom2); - case Iop_F64toI32: + case Iop_RoundF32toInt: + case Iop_SqrtF32: + /* I32(rm) x I32/F32 -> I32/F32 */ + return mkLazy2(mce, Ity_I32, vatom1, vatom2); + + case Iop_F64toI32U: + case Iop_F64toI32S: case Iop_F64toF32: /* First arg is I32 (rounding mode), second is F64 (data). */ return mkLazy2(mce, Ity_I32, vatom1, vatom2); - case Iop_F64toI16: + case Iop_F64toI16S: /* First arg is I32 (rounding mode), second is F64 (data). */ return mkLazy2(mce, Ity_I16, vatom1, vatom2); @@ -2463,6 +2920,7 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, return assignNew('V', mce, Ity_I16, binop(Iop_8HLto16, vHi8, vLo8)); } + case Iop_Sad8Ux4: /* maybe we could do better? ftm, do mkLazy2. */ case Iop_DivS32: case Iop_DivU32: return mkLazy2(mce, Ity_I32, vatom1, vatom2); @@ -2651,8 +3109,21 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_RoundF32x4_RP: case Iop_RoundF32x4_RN: case Iop_RoundF32x4_RZ: + case Iop_Recip32x4: + case Iop_Abs32Fx4: + case Iop_Neg32Fx4: + case Iop_Rsqrte32Fx4: return unary32Fx4(mce, vatom); + case Iop_I32UtoFx2: + case Iop_I32StoFx2: + case Iop_Recip32Fx2: + case Iop_Recip32x2: + case Iop_Abs32Fx2: + case Iop_Neg32Fx2: + case Iop_Rsqrte32Fx2: + return unary32Fx2(mce, vatom); + case Iop_Sqrt32F0x4: case Iop_RSqrt32F0x4: case Iop_Recip32F0x4: @@ -2663,10 +3134,17 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Dup8x16: case Iop_Dup16x8: case Iop_Dup32x4: + case Iop_Reverse16_8x16: + case Iop_Reverse32_8x16: + case Iop_Reverse32_16x8: + case Iop_Reverse64_8x16: + case Iop_Reverse64_16x8: + case Iop_Reverse64_32x4: return assignNew('V', mce, Ity_V128, unop(op, vatom)); case Iop_F32toF64: - case Iop_I32toF64: + case Iop_I32StoF64: + case Iop_I32UtoF64: case Iop_NegF64: case Iop_AbsF64: case Iop_Est5FRSqrt: @@ -2681,6 +3159,8 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Clz32: case Iop_Ctz32: case Iop_TruncF64asF32: + case Iop_NegF32: + case Iop_AbsF32: return mkPCastTo(mce, Ity_I32, vatom); case Iop_1Uto64: @@ -2694,6 +3174,15 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_V128HIto64: case Iop_128HIto64: case Iop_128to64: + case Iop_Dup8x8: + case Iop_Dup16x4: + case Iop_Dup32x2: + case Iop_Reverse16_8x8: + case Iop_Reverse32_8x8: + case Iop_Reverse32_16x4: + case Iop_Reverse64_8x8: + case Iop_Reverse64_16x4: + case Iop_Reverse64_32x2: return assignNew('V', mce, Ity_I64, unop(op, vatom)); case Iop_64to32: @@ -2730,6 +3219,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_ReinterpF64asI64: case Iop_ReinterpI64asF64: case Iop_ReinterpI32asF32: + case Iop_ReinterpF32asI32: case Iop_NotV128: case Iop_Not64: case Iop_Not32: @@ -2738,6 +3228,106 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Not1: return vatom; + case Iop_CmpNEZ8x8: + case Iop_Cnt8x8: + case Iop_Clz8Sx8: + case Iop_Cls8Sx8: + case Iop_Abs8x8: + return mkPCast8x8(mce, vatom); + + case Iop_CmpNEZ8x16: + case Iop_Cnt8x16: + case Iop_Clz8Sx16: + case Iop_Cls8Sx16: + case Iop_Abs8x16: + return mkPCast8x16(mce, vatom); + + case Iop_CmpNEZ16x4: + case Iop_Clz16Sx4: + case Iop_Cls16Sx4: + case Iop_Abs16x4: + return mkPCast16x4(mce, vatom); + + case Iop_CmpNEZ16x8: + case Iop_Clz16Sx8: + case Iop_Cls16Sx8: + case Iop_Abs16x8: + return mkPCast16x8(mce, vatom); + + case Iop_CmpNEZ32x2: + case Iop_Clz32Sx2: + case Iop_Cls32Sx2: + case Iop_FtoI32Ux2_RZ: + case Iop_FtoI32Sx2_RZ: + case Iop_Abs32x2: + return mkPCast32x2(mce, vatom); + + case Iop_CmpNEZ32x4: + case Iop_Clz32Sx4: + case Iop_Cls32Sx4: + case Iop_FtoI32Ux4_RZ: + case Iop_FtoI32Sx4_RZ: + case Iop_Abs32x4: + return mkPCast32x4(mce, vatom); + + case Iop_CmpwNEZ64: + return mkPCastTo(mce, Ity_I64, vatom); + + case Iop_CmpNEZ64x2: + return mkPCast64x2(mce, vatom); + + case Iop_Shorten16x8: + case Iop_Shorten32x4: + case Iop_Shorten64x2: + case Iop_QShortenS16Sx8: + case Iop_QShortenU16Sx8: + case Iop_QShortenU16Ux8: + case Iop_QShortenS32Sx4: + case Iop_QShortenU32Sx4: + case Iop_QShortenU32Ux4: + case Iop_QShortenS64Sx2: + case Iop_QShortenU64Sx2: + case Iop_QShortenU64Ux2: + return vectorShortenV128(mce, op, vatom); + + case Iop_Longen8Sx8: + case Iop_Longen8Ux8: + case Iop_Longen16Sx4: + case Iop_Longen16Ux4: + case Iop_Longen32Sx2: + case Iop_Longen32Ux2: + return vectorLongenI64(mce, op, vatom); + + case Iop_PwAddL32Ux2: + case Iop_PwAddL32Sx2: + return mkPCastTo(mce, Ity_I64, + assignNew('V', mce, Ity_I64, unop(op, mkPCast32x2(mce, vatom)))); + + case Iop_PwAddL16Ux4: + case Iop_PwAddL16Sx4: + return mkPCast32x2(mce, + assignNew('V', mce, Ity_I64, unop(op, mkPCast16x4(mce, vatom)))); + + case Iop_PwAddL8Ux8: + case Iop_PwAddL8Sx8: + return mkPCast16x4(mce, + assignNew('V', mce, Ity_I64, unop(op, mkPCast8x8(mce, vatom)))); + + case Iop_PwAddL32Ux4: + case Iop_PwAddL32Sx4: + return mkPCast64x2(mce, + assignNew('V', mce, Ity_V128, unop(op, mkPCast32x4(mce, vatom)))); + + case Iop_PwAddL16Ux8: + case Iop_PwAddL16Sx8: + return mkPCast32x4(mce, + assignNew('V', mce, Ity_V128, unop(op, mkPCast16x8(mce, vatom)))); + + case Iop_PwAddL8Ux16: + case Iop_PwAddL8Sx16: + return mkPCast16x8(mce, + assignNew('V', mce, Ity_V128, unop(op, mkPCast8x16(mce, vatom)))); + default: ppIROp(op); VG_(tool_panic)("memcheck:expr2vbits_Unop"); @@ -3862,6 +4452,68 @@ static void do_shadow_CAS_double ( MCEnv* mce, IRCAS* cas ) } +/* ------ Dealing with LL/SC (not difficult) ------ */ + +static void do_shadow_LLSC ( MCEnv* mce, + IREndness stEnd, + IRTemp stResult, + IRExpr* stAddr, + IRExpr* stStoredata ) +{ + /* In short: treat a load-linked like a normal load followed by an + assignment of the loaded (shadow) data to the result temporary. + Treat a store-conditional like a normal store, and mark the + result temporary as defined. */ + IRType resTy = typeOfIRTemp(mce->sb->tyenv, stResult); + IRTemp resTmp = findShadowTmpV(mce, stResult); + + tl_assert(isIRAtom(stAddr)); + if (stStoredata) + tl_assert(isIRAtom(stStoredata)); + + if (stStoredata == NULL) { + /* Load Linked */ + /* Just treat this as a normal load, followed by an assignment of + the value to .result. */ + /* Stay sane */ + tl_assert(resTy == Ity_I64 || resTy == Ity_I32 + || resTy == Ity_I16 || resTy == Ity_I8); + assign( 'V', mce, resTmp, + expr2vbits_Load( + mce, stEnd, resTy, stAddr, 0/*addr bias*/)); + } else { + /* Store Conditional */ + /* Stay sane */ + IRType dataTy = typeOfIRExpr(mce->sb->tyenv, + stStoredata); + tl_assert(dataTy == Ity_I64 || dataTy == Ity_I32 + || dataTy == Ity_I16 || dataTy == Ity_I8); + do_shadow_Store( mce, stEnd, + stAddr, 0/* addr bias */, + stStoredata, + NULL /* shadow data */, + NULL/*guard*/ ); + /* This is a store conditional, so it writes to .result a value + indicating whether or not the store succeeded. Just claim + this value is always defined. In the PowerPC interpretation + of store-conditional, definedness of the success indication + depends on whether the address of the store matches the + reservation address. But we can't tell that here (and + anyway, we're not being PowerPC-specific). At least we are + guaranteed that the definedness of the store address, and its + addressibility, will be checked as per normal. So it seems + pretty safe to just say that the success indication is always + defined. + + In schemeS, for origin tracking, we must correspondingly set + a no-origin value for the origin shadow of .result. + */ + tl_assert(resTy == Ity_I1); + assign( 'V', mce, resTmp, definedOfType(resTy) ); + } +} + + /*------------------------------------------------------------*/ /*--- Memcheck main ---*/ /*------------------------------------------------------------*/ @@ -3979,6 +4631,11 @@ static Bool checkForBogusLiterals ( /*FLAT*/ IRStmt* st ) || isBogusAtom(cas->expdLo) || (cas->dataHi ? isBogusAtom(cas->dataHi) : False) || isBogusAtom(cas->dataLo); + case Ist_LLSC: + return isBogusAtom(st->Ist.LLSC.addr) + || (st->Ist.LLSC.storedata + ? isBogusAtom(st->Ist.LLSC.storedata) + : False); default: unhandled: ppIRStmt(st); @@ -4182,32 +4839,6 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, st->Ist.Store.data, NULL /* shadow data */, NULL/*guard*/ ); - /* If this is a store conditional, it writes to .resSC a - value indicating whether or not the store succeeded. - Just claim this value is always defined. In the - PowerPC interpretation of store-conditional, - definedness of the success indication depends on - whether the address of the store matches the - reservation address. But we can't tell that here (and - anyway, we're not being PowerPC-specific). At least we - are guarantted that the definedness of the store - address, and its addressibility, will be checked as per - normal. So it seems pretty safe to just say that the - success indication is always defined. - - In schemeS, for origin tracking, we must - correspondingly set a no-origin value for the origin - shadow of resSC. - */ - if (st->Ist.Store.resSC != IRTemp_INVALID) { - assign( 'V', &mce, - findShadowTmpV(&mce, st->Ist.Store.resSC), - definedOfType( - shadowTypeV( - typeOfIRTemp(mce.sb->tyenv, - st->Ist.Store.resSC) - ))); - } break; case Ist_Exit: @@ -4241,6 +4872,14 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, does it all. */ break; + case Ist_LLSC: + do_shadow_LLSC( &mce, + st->Ist.LLSC.end, + st->Ist.LLSC.result, + st->Ist.LLSC.addr, + st->Ist.LLSC.storedata ); + break; + default: VG_(printf)("\n"); ppIRStmt(st); @@ -4597,6 +5236,7 @@ static IRAtom* zWidenFrom32 ( MCEnv* mce, IRType dstTy, IRAtom* e ) { tl_assert(0); } + static IRAtom* schemeE ( MCEnv* mce, IRExpr* e ) { tl_assert(MC_(clo_mc_level) == 3); @@ -4732,6 +5372,7 @@ static IRAtom* schemeE ( MCEnv* mce, IRExpr* e ) } } + static void do_origins_Dirty ( MCEnv* mce, IRDirty* d ) { // This is a hacked version of do_shadow_Dirty @@ -4888,6 +5529,26 @@ static void do_origins_Dirty ( MCEnv* mce, IRDirty* d ) } } + +static void do_origins_Store ( MCEnv* mce, + IREndness stEnd, + IRExpr* stAddr, + IRExpr* stData ) +{ + Int dszB; + IRAtom* dataB; + /* assert that the B value for the address is already available + (somewhere), since the call to schemeE will want to see it. + XXXX how does this actually ensure that?? */ + tl_assert(isIRAtom(stAddr)); + tl_assert(isIRAtom(stData)); + dszB = sizeofIRType( typeOfIRExpr(mce->sb->tyenv, stData ) ); + dataB = schemeE( mce, stData ); + gen_store_b( mce, dszB, stAddr, 0/*offset*/, dataB, + NULL/*guard*/ ); +} + + static void schemeS ( MCEnv* mce, IRStmt* st ) { tl_assert(MC_(clo_mc_level) == 3); @@ -4928,30 +5589,47 @@ static void schemeS ( MCEnv* mce, IRStmt* st ) st->Ist.PutI.bias, t4 )); break; } + case Ist_Dirty: do_origins_Dirty( mce, st->Ist.Dirty.details ); break; - case Ist_Store: { - Int dszB; - IRAtom* dataB; - /* assert that the B value for the address is already - available (somewhere) */ - tl_assert(isIRAtom(st->Ist.Store.addr)); - dszB = sizeofIRType( - typeOfIRExpr(mce->sb->tyenv, st->Ist.Store.data )); - dataB = schemeE( mce, st->Ist.Store.data ); - gen_store_b( mce, dszB, st->Ist.Store.addr, 0/*offset*/, dataB, - NULL/*guard*/ ); - /* For the rationale behind this, see comments at the place - where the V-shadow for .resSC is constructed, in the main - loop in MC_(instrument). In short, wee regard .resSc as - always-defined. */ - if (st->Ist.Store.resSC != IRTemp_INVALID) { - assign( 'B', mce, findShadowTmpB(mce, st->Ist.Store.resSC), - mkU32(0) ); + + case Ist_Store: + do_origins_Store( mce, st->Ist.Store.end, + st->Ist.Store.addr, + st->Ist.Store.data ); + break; + + case Ist_LLSC: { + /* In short: treat a load-linked like a normal load followed + by an assignment of the loaded (shadow) data the result + temporary. Treat a store-conditional like a normal store, + and mark the result temporary as defined. */ + if (st->Ist.LLSC.storedata == NULL) { + /* Load Linked */ + IRType resTy + = typeOfIRTemp(mce->sb->tyenv, st->Ist.LLSC.result); + IRExpr* vanillaLoad + = IRExpr_Load(st->Ist.LLSC.end, resTy, st->Ist.LLSC.addr); + tl_assert(resTy == Ity_I64 || resTy == Ity_I32 + || resTy == Ity_I16 || resTy == Ity_I8); + assign( 'B', mce, findShadowTmpB(mce, st->Ist.LLSC.result), + schemeE(mce, vanillaLoad)); + } else { + /* Store conditional */ + do_origins_Store( mce, st->Ist.LLSC.end, + st->Ist.LLSC.addr, + st->Ist.LLSC.storedata ); + /* For the rationale behind this, see comments at the + place where the V-shadow for .result is constructed, in + do_shadow_LLSC. In short, we regard .result as + always-defined. */ + assign( 'B', mce, findShadowTmpB(mce, st->Ist.LLSC.result), + mkU32(0) ); } break; } + case Ist_Put: { Int b_offset = MC_(get_otrack_shadow_offset)( @@ -4965,15 +5643,18 @@ static void schemeS ( MCEnv* mce, IRStmt* st ) } break; } + case Ist_WrTmp: assign( 'B', mce, findShadowTmpB(mce, st->Ist.WrTmp.tmp), schemeE(mce, st->Ist.WrTmp.data) ); break; + case Ist_MBE: case Ist_NoOp: case Ist_Exit: case Ist_IMark: break; + default: VG_(printf)("mc_translate.c: schemeS: unhandled: "); ppIRStmt(st); diff --git a/memcheck/memcheck.h b/memcheck/memcheck.h index fc50dab..bf95491 100644 --- a/memcheck/memcheck.h +++ b/memcheck/memcheck.h @@ -13,7 +13,7 @@ This file is part of MemCheck, a heavyweight Valgrind tool for detecting memory errors. - Copyright (C) 2000-2009 Julian Seward. All rights reserved. + Copyright (C) 2000-2010 Julian Seward. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions @@ -107,66 +107,48 @@ typedef /* Mark memory at _qzz_addr as unaddressable for _qzz_len bytes. */ #define VALGRIND_MAKE_MEM_NOACCESS(_qzz_addr,_qzz_len) \ - (__extension__({unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* default return */, \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \ VG_USERREQ__MAKE_MEM_NOACCESS, \ - _qzz_addr, _qzz_len, 0, 0, 0); \ - _qzz_res; \ - })) + (_qzz_addr), (_qzz_len), 0, 0, 0) /* Similarly, mark memory at _qzz_addr as addressable but undefined for _qzz_len bytes. */ #define VALGRIND_MAKE_MEM_UNDEFINED(_qzz_addr,_qzz_len) \ - (__extension__({unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* default return */, \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \ VG_USERREQ__MAKE_MEM_UNDEFINED, \ - _qzz_addr, _qzz_len, 0, 0, 0); \ - _qzz_res; \ - })) + (_qzz_addr), (_qzz_len), 0, 0, 0) /* Similarly, mark memory at _qzz_addr as addressable and defined for _qzz_len bytes. */ #define VALGRIND_MAKE_MEM_DEFINED(_qzz_addr,_qzz_len) \ - (__extension__({unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* default return */, \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \ VG_USERREQ__MAKE_MEM_DEFINED, \ - _qzz_addr, _qzz_len, 0, 0, 0); \ - _qzz_res; \ - })) + (_qzz_addr), (_qzz_len), 0, 0, 0) /* Similar to VALGRIND_MAKE_MEM_DEFINED except that addressability is not altered: bytes which are addressable are marked as defined, but those which are not addressable are left unchanged. */ -#define VALGRIND_MAKE_MEM_DEFINED_IF_ADDRESSABLE(_qzz_addr,_qzz_len) \ - (__extension__({unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* default return */, \ +#define VALGRIND_MAKE_MEM_DEFINED_IF_ADDRESSABLE(_qzz_addr,_qzz_len) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \ VG_USERREQ__MAKE_MEM_DEFINED_IF_ADDRESSABLE, \ - _qzz_addr, _qzz_len, 0, 0, 0); \ - _qzz_res; \ - })) + (_qzz_addr), (_qzz_len), 0, 0, 0) /* Create a block-description handle. The description is an ascii string which is included in any messages pertaining to addresses within the specified memory range. Has no other effect on the properties of the memory range. */ -#define VALGRIND_CREATE_BLOCK(_qzz_addr,_qzz_len, _qzz_desc) \ - (__extension__({unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* default return */, \ - VG_USERREQ__CREATE_BLOCK, \ - _qzz_addr, _qzz_len, _qzz_desc, \ - 0, 0); \ - _qzz_res; \ - })) +#define VALGRIND_CREATE_BLOCK(_qzz_addr,_qzz_len, _qzz_desc) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \ + VG_USERREQ__CREATE_BLOCK, \ + (_qzz_addr), (_qzz_len), (_qzz_desc), \ + 0, 0) /* Discard a block-description-handle. Returns 1 for an invalid handle, 0 for a valid handle. */ #define VALGRIND_DISCARD(_qzz_blkindex) \ - (__extension__ ({unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* default return */, \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \ VG_USERREQ__DISCARD, \ - 0, _qzz_blkindex, 0, 0, 0); \ - _qzz_res; \ - })) + 0, (_qzz_blkindex), 0, 0, 0) /* Client-code macros to check the state of memory. */ @@ -175,25 +157,19 @@ typedef If suitable addressibility is not established, Valgrind prints an error message and returns the address of the first offending byte. Otherwise it returns zero. */ -#define VALGRIND_CHECK_MEM_IS_ADDRESSABLE(_qzz_addr,_qzz_len) \ - (__extension__({unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, \ - VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE,\ - _qzz_addr, _qzz_len, 0, 0, 0); \ - _qzz_res; \ - })) +#define VALGRIND_CHECK_MEM_IS_ADDRESSABLE(_qzz_addr,_qzz_len) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \ + VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE, \ + (_qzz_addr), (_qzz_len), 0, 0, 0) /* Check that memory at _qzz_addr is addressable and defined for _qzz_len bytes. If suitable addressibility and definedness are not established, Valgrind prints an error message and returns the address of the first offending byte. Otherwise it returns zero. */ #define VALGRIND_CHECK_MEM_IS_DEFINED(_qzz_addr,_qzz_len) \ - (__extension__({unsigned long _qzz_res; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \ VG_USERREQ__CHECK_MEM_IS_DEFINED, \ - _qzz_addr, _qzz_len, 0, 0, 0); \ - _qzz_res; \ - })) + (_qzz_addr), (_qzz_len), 0, 0, 0); /* Use this macro to force the definedness and addressibility of an lvalue to be checked. If suitable addressibility and definedness @@ -276,15 +252,11 @@ typedef The metadata is not copied in cases 0, 2 or 3 so it should be impossible to segfault your system by using this call. */ -#define VALGRIND_GET_VBITS(zza,zzvbits,zznbytes) \ - (__extension__({unsigned long _qzz_res; \ - char* czza = (char*)zza; \ - char* czzvbits = (char*)zzvbits; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, \ - VG_USERREQ__GET_VBITS, \ - czza, czzvbits, zznbytes, 0, 0 ); \ - _qzz_res; \ - })) +#define VALGRIND_GET_VBITS(zza,zzvbits,zznbytes) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \ + VG_USERREQ__GET_VBITS, \ + (char*)(zza), (char*)(zzvbits), \ + (zznbytes), 0, 0) /* Set the validity data for addresses [zza..zza+zznbytes-1], copying it from the provided zzvbits array. Return values: @@ -295,15 +267,11 @@ typedef The metadata is not copied in cases 0, 2 or 3 so it should be impossible to segfault your system by using this call. */ -#define VALGRIND_SET_VBITS(zza,zzvbits,zznbytes) \ - (__extension__({unsigned int _qzz_res; \ - char* czza = (char*)zza; \ - char* czzvbits = (char*)zzvbits; \ - VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0, \ - VG_USERREQ__SET_VBITS, \ - czza, czzvbits, zznbytes, 0, 0 ); \ - _qzz_res; \ - })) +#define VALGRIND_SET_VBITS(zza,zzvbits,zznbytes) \ + VALGRIND_DO_CLIENT_REQUEST_EXPR(0, \ + VG_USERREQ__SET_VBITS, \ + (char*)(zza), (char*)(zzvbits), \ + (zznbytes), 0, 0 ) #endif diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am index be6f165..53eb6ed 100644 --- a/memcheck/tests/Makefile.am +++ b/memcheck/tests/Makefile.am @@ -11,6 +11,13 @@ if VGCONF_ARCHS_INCLUDE_AMD64 SUBDIRS += amd64 endif +if VGCONF_ARCHS_INCLUDE_PPC32 +SUBDIRS += ppc32 +endif +if VGCONF_ARCHS_INCLUDE_PPC64 +SUBDIRS += ppc64 +endif + # OS-specific tests if VGCONF_OS_IS_LINUX SUBDIRS += linux @@ -23,12 +30,16 @@ endif if VGCONF_PLATFORMS_INCLUDE_X86_LINUX SUBDIRS += x86-linux endif +if VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX +SUBDIRS += amd64-linux +endif -DIST_SUBDIRS = x86 amd64 linux darwin x86-linux . +DIST_SUBDIRS = x86 amd64 ppc32 ppc64 linux darwin x86-linux amd64-linux . dist_noinst_SCRIPTS = \ filter_addressable \ filter_allocs \ + filter_leak_cases_possible \ filter_stderr filter_xml \ filter_varinfo3 @@ -42,6 +53,7 @@ EXTRA_DIST = \ badaddrvalue.stdout.exp badaddrvalue.vgtest \ badfree-2trace.stderr.exp badfree-2trace.vgtest \ badfree.stderr.exp badfree.vgtest \ + badfree3.stderr.exp badfree3.vgtest \ badjump.stderr.exp badjump.vgtest \ badjump2.stderr.exp badjump2.vgtest \ badloop.stderr.exp badloop.vgtest \ @@ -71,6 +83,7 @@ EXTRA_DIST = \ inline.stderr.exp inline.stdout.exp inline.vgtest \ leak-0.vgtest leak-0.stderr.exp \ leak-cases-full.vgtest leak-cases-full.stderr.exp \ + leak-cases-possible.vgtest leak-cases-possible.stderr.exp \ leak-cases-summary.vgtest leak-cases-summary.stderr.exp \ leak-cycle.vgtest leak-cycle.stderr.exp \ leak-pool-0.vgtest leak-pool-0.stderr.exp \ @@ -159,12 +172,12 @@ EXTRA_DIST = \ trivialleak.stderr.exp trivialleak.vgtest \ unit_libcbase.stderr.exp unit_libcbase.vgtest \ unit_oset.stderr.exp unit_oset.stdout.exp unit_oset.vgtest \ - varinfo1.vgtest varinfo1.stdout.exp varinfo1.stderr.exp \ - varinfo2.vgtest varinfo2.stdout.exp varinfo2.stderr.exp \ - varinfo3.vgtest varinfo3.stdout.exp varinfo3.stderr.exp \ - varinfo4.vgtest varinfo4.stdout.exp varinfo4.stderr.exp \ - varinfo5.vgtest varinfo5.stdout.exp varinfo5.stderr.exp \ - varinfo6.vgtest varinfo6.stdout.exp varinfo6.stderr.exp \ + varinfo1.vgtest varinfo1.stdout.exp varinfo1.stderr.exp varinfo1.stderr.exp-ppc64\ + varinfo2.vgtest varinfo2.stdout.exp varinfo2.stderr.exp varinfo2.stderr.exp-ppc64\ + varinfo3.vgtest varinfo3.stdout.exp varinfo3.stderr.exp varinfo3.stderr.exp-ppc64\ + varinfo4.vgtest varinfo4.stdout.exp varinfo4.stderr.exp varinfo4.stderr.exp-ppc64\ + varinfo5.vgtest varinfo5.stdout.exp varinfo5.stderr.exp varinfo5.stderr.exp-ppc64\ + varinfo6.vgtest varinfo6.stdout.exp varinfo6.stderr.exp varinfo6.stderr.exp-ppc64\ vcpu_bz2.stdout.exp vcpu_bz2.stderr.exp vcpu_bz2.vgtest \ vcpu_fbench.stdout.exp vcpu_fbench.stderr.exp vcpu_fbench.vgtest \ vcpu_fnfns.stdout.exp vcpu_fnfns.stdout.exp-glibc28-amd64 \ @@ -243,6 +256,11 @@ check_PROGRAMS = \ AM_CFLAGS += $(AM_FLAG_M3264_PRI) AM_CXXFLAGS += $(AM_FLAG_M3264_PRI) +if VGCONF_PLATFORMS_INCLUDE_ARM_LINUX +AM_CFLAGS += -mfloat-abi=softfp +AM_CXXFLAGS += -mfloat-abi=softfp +endif + if VGCONF_OS_IS_DARWIN atomic_incs_CFLAGS = $(AM_CFLAGS) -mdynamic-no-pic else diff --git a/memcheck/tests/amd64-linux/Makefile.am b/memcheck/tests/amd64-linux/Makefile.am new file mode 100644 index 0000000..9b31b80 --- /dev/null +++ b/memcheck/tests/amd64-linux/Makefile.am @@ -0,0 +1,21 @@ + +include $(top_srcdir)/Makefile.tool-tests.am + +dist_noinst_SCRIPTS = \ + filter_stderr filter_defcfaexpr + +EXTRA_DIST = \ + defcfaexpr.vgtest defcfaexpr.stderr.exp \ + int3-amd64.vgtest int3-amd64.stderr.exp int3-amd64.stdout.exp + +check_PROGRAMS = \ + defcfaexpr \ + int3-amd64 + + +AM_CFLAGS += @FLAG_M64@ +AM_CXXFLAGS += @FLAG_M64@ +AM_CCASFLAGS += @FLAG_M64@ + +defcfaexpr_SOURCES = defcfaexpr.S + diff --git a/memcheck/tests/amd64/defcfaexpr.S b/memcheck/tests/amd64-linux/defcfaexpr.S similarity index 100% rename from memcheck/tests/amd64/defcfaexpr.S rename to memcheck/tests/amd64-linux/defcfaexpr.S diff --git a/memcheck/tests/amd64/defcfaexpr.stderr.exp b/memcheck/tests/amd64-linux/defcfaexpr.stderr.exp similarity index 100% rename from memcheck/tests/amd64/defcfaexpr.stderr.exp rename to memcheck/tests/amd64-linux/defcfaexpr.stderr.exp diff --git a/memcheck/tests/amd64/defcfaexpr.vgtest b/memcheck/tests/amd64-linux/defcfaexpr.vgtest similarity index 100% rename from memcheck/tests/amd64/defcfaexpr.vgtest rename to memcheck/tests/amd64-linux/defcfaexpr.vgtest diff --git a/memcheck/tests/amd64/filter_defcfaexpr b/memcheck/tests/amd64-linux/filter_defcfaexpr similarity index 91% rename from memcheck/tests/amd64/filter_defcfaexpr rename to memcheck/tests/amd64-linux/filter_defcfaexpr index 7fa1afe..5f4af58 100755 --- a/memcheck/tests/amd64/filter_defcfaexpr +++ b/memcheck/tests/amd64-linux/filter_defcfaexpr @@ -23,6 +23,6 @@ # stack given the unusual CFAs describing it. -sed "s/\/.*\/tests\/amd64\/defcfaexpr/bogus.S:0/" | \ +sed "s/\/.*\/tests\/amd64-linux\/defcfaexpr/bogus.S:0/" | \ sed "s/(in /(/" | \ ./filter_stderr diff --git a/memcheck/tests/amd64-linux/filter_stderr b/memcheck/tests/amd64-linux/filter_stderr new file mode 100755 index 0000000..0ae9313 --- /dev/null +++ b/memcheck/tests/amd64-linux/filter_stderr @@ -0,0 +1,3 @@ +#! /bin/sh + +../filter_stderr diff --git a/memcheck/tests/amd64/int3-amd64.c b/memcheck/tests/amd64-linux/int3-amd64.c similarity index 94% rename from memcheck/tests/amd64/int3-amd64.c rename to memcheck/tests/amd64-linux/int3-amd64.c index 8f3c803..3a0fb0c 100644 --- a/memcheck/tests/amd64/int3-amd64.c +++ b/memcheck/tests/amd64-linux/int3-amd64.c @@ -8,17 +8,12 @@ static char* rip_at_sig = NULL; - static void int_handler(int signum, siginfo_t *si, void *uc_arg) { ucontext_t *uc = (ucontext_t *)uc_arg; /* Note that uc->uc_mcontext is an embedded struct, not a pointer */ mcontext_t *mc = &(uc->uc_mcontext); -#if defined(__FreeBSD__) - void *pc = (void*)mc->mc_rip; -#else void *pc = (void*)mc->gregs[REG_RIP]; -#endif printf("in int_handler, RIP is ...\n"); rip_at_sig = pc; } diff --git a/memcheck/tests/amd64/int3-amd64.stderr.exp b/memcheck/tests/amd64-linux/int3-amd64.stderr.exp similarity index 100% rename from memcheck/tests/amd64/int3-amd64.stderr.exp rename to memcheck/tests/amd64-linux/int3-amd64.stderr.exp diff --git a/memcheck/tests/amd64/int3-amd64.stdout.exp b/memcheck/tests/amd64-linux/int3-amd64.stdout.exp similarity index 100% rename from memcheck/tests/amd64/int3-amd64.stdout.exp rename to memcheck/tests/amd64-linux/int3-amd64.stdout.exp diff --git a/memcheck/tests/amd64/int3-amd64.vgtest b/memcheck/tests/amd64-linux/int3-amd64.vgtest similarity index 100% rename from memcheck/tests/amd64/int3-amd64.vgtest rename to memcheck/tests/amd64-linux/int3-amd64.vgtest diff --git a/memcheck/tests/amd64/Makefile.am b/memcheck/tests/amd64/Makefile.am index 2cca6b2..56494e6 100644 --- a/memcheck/tests/amd64/Makefile.am +++ b/memcheck/tests/amd64/Makefile.am @@ -12,26 +12,19 @@ EXTRA_DIST = \ bt_everything.stderr.exp bt_everything.stdout.exp \ bt_everything.vgtest \ bug132146.vgtest bug132146.stderr.exp bug132146.stdout.exp \ - defcfaexpr.vgtest defcfaexpr.stderr.exp filter_defcfaexpr \ fxsave-amd64.vgtest fxsave-amd64.stdout.exp fxsave-amd64.stderr.exp \ - int3-amd64.vgtest int3-amd64.stdout.exp int3-amd64.stderr.exp \ more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \ sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \ xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \ xor-undef-amd64.stderr.exp-freebsd xor-undef-amd64.vgtest -check_PROGRAMS = bt_everything bug132146 fxsave-amd64 \ - xor-undef-amd64 - -# DDD: not sure if these ones should work on Darwin or not... if not, should -# be moved into amd64-linux/. -if ! VGCONF_OS_IS_DARWIN - check_PROGRAMS += \ - defcfaexpr \ - int3-amd64 \ +check_PROGRAMS = \ + bt_everything \ + bug132146 \ + fxsave-amd64 \ more_x87_fp \ - sse_memory -endif + sse_memory \ + xor-undef-amd64 AM_CFLAGS += @FLAG_M64@ AM_CXXFLAGS += @FLAG_M64@ @@ -41,4 +34,3 @@ more_x87_fp_CFLAGS = $(AM_CFLAGS) -O -ffast-math -mfpmath=387 \ -mfancy-math-387 more_x87_fp_LDADD = -lm -defcfaexpr_SOURCES = defcfaexpr.S diff --git a/memcheck/tests/amd64/insn_fpu.stdout.exp b/memcheck/tests/amd64/insn_fpu.stdout.exp index c790618..2dbaa07 100644 --- a/memcheck/tests/amd64/insn_fpu.stdout.exp +++ b/memcheck/tests/amd64/insn_fpu.stdout.exp @@ -210,6 +210,14 @@ fildq_1 ... ok fildq_2 ... ok fildq_3 ... ok fildq_4 ... ok +fists_1 ... ok +fists_2 ... ok +fists_3 ... ok +fists_4 ... ok +fists_5 ... ok +fists_6 ... ok +fists_7 ... ok +fists_8 ... ok fistl_1 ... ok fistl_2 ... ok fistl_3 ... ok @@ -218,6 +226,14 @@ fistl_5 ... ok fistl_6 ... ok fistl_7 ... ok fistl_8 ... ok +fistps_1 ... ok +fistps_2 ... ok +fistps_3 ... ok +fistps_4 ... ok +fistps_5 ... ok +fistps_6 ... ok +fistps_7 ... ok +fistps_8 ... ok fistpl_1 ... ok fistpl_2 ... ok fistpl_3 ... ok diff --git a/memcheck/tests/amd64/xor-undef-amd64.stderr.exp b/memcheck/tests/amd64/xor-undef-amd64.stderr.exp index be1f9ed..ab36895 100644 --- a/memcheck/tests/amd64/xor-undef-amd64.stderr.exp +++ b/memcheck/tests/amd64/xor-undef-amd64.stderr.exp @@ -1,4 +1,3 @@ - Conditional jump or move depends on uninitialised value(s) at 0x........: main (xor-undef-amd64.c:17) @@ -14,13 +13,3 @@ Conditional jump or move depends on uninitialised value(s) Conditional jump or move depends on uninitialised value(s) at 0x........: main (xor-undef-amd64.c:117) - -HEAP SUMMARY: - in use at exit: 0 bytes in 0 blocks - total heap usage: 1 allocs, 1 frees, 48 bytes allocated - -For a detailed leak analysis, rerun with: --leak-check=full - -For counts of detected and suppressed errors, rerun with: -v -Use --track-origins=yes to see where uninitialised values come from -ERROR SUMMARY: 5 errors from 5 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/amd64/xor-undef-amd64.vgtest b/memcheck/tests/amd64/xor-undef-amd64.vgtest index b0a9be1..6d75090 100644 --- a/memcheck/tests/amd64/xor-undef-amd64.vgtest +++ b/memcheck/tests/amd64/xor-undef-amd64.vgtest @@ -1 +1,2 @@ prog: xor-undef-amd64 +vgopts: -q diff --git a/memcheck/tests/atomic_incs.c b/memcheck/tests/atomic_incs.c index 94af434..197902c 100644 --- a/memcheck/tests/atomic_incs.c +++ b/memcheck/tests/atomic_incs.c @@ -42,7 +42,7 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n ) ); #elif defined(VGA_ppc32) /* Nasty hack. Does correctly atomically do *p += n, but only if p - is 8-aligned -- guaranteed by caller. */ + is 4-aligned -- guaranteed by caller. */ unsigned long success; do { __asm__ __volatile__( @@ -74,6 +74,8 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n ) : /*trash*/ "memory", "cc", "r15" ); } while (success != 1); +#elif defined(VGA_arm) + *p += n; #else # error "Unsupported arch" #endif @@ -136,6 +138,8 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n ) : /*trash*/ "memory", "cc", "r15" ); } while (success != 1); +#elif defined(VGA_arm) + *p += n; #else # error "Unsupported arch" #endif @@ -195,6 +199,23 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n ) : /*trash*/ "memory", "cc", "r15" ); } while (success != 1); +#elif defined(VGA_arm) + unsigned int block[3] + = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF }; + do { + __asm__ __volatile__( + "mov r5, %0" "\n\t" + "ldr r9, [r5, #0]" "\n\t" // p + "ldr r10, [r5, #4]" "\n\t" // n + "ldrex r8, [r9]" "\n\t" + "add r8, r8, r10" "\n\t" + "strex r11, r8, [r9]" "\n\t" + "str r11, [r5, #8]" "\n\t" + : /*out*/ + : /*in*/ "r"(&block[0]) + : /*trash*/ "memory", "cc", "r5", "r8", "r9", "r10" + ); + } while (block[2] != 0); #else # error "Unsupported arch" #endif @@ -202,7 +223,7 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n ) __attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n ) { -#if defined(VGA_x86) || defined(VGA_ppc32) +#if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_arm) /* do nothing; is not supported */ #elif defined(VGA_amd64) // this is a bit subtle. It relies on the fact that, on a 64-bit platform, diff --git a/memcheck/tests/badfree3.stderr.exp b/memcheck/tests/badfree3.stderr.exp new file mode 100644 index 0000000..ca3ecf5 --- /dev/null +++ b/memcheck/tests/badfree3.stderr.exp @@ -0,0 +1,10 @@ +Invalid free() / delete / delete[] + at 0x........: free (coregrind/vg_replace_malloc.c:...) + by 0x........: main (memcheck/tests/badfree.c:12) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Invalid free() / delete / delete[] + at 0x........: free (coregrind/vg_replace_malloc.c:...) + by 0x........: main (memcheck/tests/badfree.c:15) + Address 0x........ is on thread 1's stack + diff --git a/memcheck/tests/badfree3.vgtest b/memcheck/tests/badfree3.vgtest new file mode 100644 index 0000000..876cced --- /dev/null +++ b/memcheck/tests/badfree3.vgtest @@ -0,0 +1,2 @@ +prog: badfree +vgopts: -q --fullpath-after=${PWD}/ diff --git a/memcheck/tests/custom_alloc.stderr.exp b/memcheck/tests/custom_alloc.stderr.exp index 140f56e..b3c2b09 100644 --- a/memcheck/tests/custom_alloc.stderr.exp +++ b/memcheck/tests/custom_alloc.stderr.exp @@ -18,5 +18,7 @@ Mismatched free() / delete / delete [] Invalid read of size 4 at 0x........: main (custom_alloc.c:89) - Address 0x........ is not stack'd, malloc'd or (recently) free'd + Address 0x........ is 0 bytes inside a block of size 40 free'd + at 0x........: custom_free (custom_alloc.c:54) + by 0x........: main (custom_alloc.c:81) diff --git a/memcheck/tests/filter_leak_cases_possible b/memcheck/tests/filter_leak_cases_possible new file mode 100755 index 0000000..1b50c53 --- /dev/null +++ b/memcheck/tests/filter_leak_cases_possible @@ -0,0 +1,4 @@ +#! /bin/sh + +./filter_stderr | +sed -e 's/^leaked.*$//' -e 's/^dubious.*$//' -e 's/^reachable.*$//' -e 's/^suppressed:.*$//' diff --git a/memcheck/tests/leak-cases-possible.stderr.exp b/memcheck/tests/leak-cases-possible.stderr.exp new file mode 100644 index 0000000..78ad60f --- /dev/null +++ b/memcheck/tests/leak-cases-possible.stderr.exp @@ -0,0 +1,22 @@ + + + + +16 bytes in 1 blocks are definitely lost in loss record ... of ... + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-cases.c:52) + by 0x........: f (leak-cases.c:74) + by 0x........: main (leak-cases.c:107) + +32 (16 direct, 16 indirect) bytes in 1 blocks are definitely lost in loss record ... of ... + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-cases.c:52) + by 0x........: f (leak-cases.c:76) + by 0x........: main (leak-cases.c:107) + +32 (16 direct, 16 indirect) bytes in 1 blocks are definitely lost in loss record ... of ... + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: mk (leak-cases.c:52) + by 0x........: f (leak-cases.c:91) + by 0x........: main (leak-cases.c:107) + diff --git a/memcheck/tests/leak-cases-possible.vgtest b/memcheck/tests/leak-cases-possible.vgtest new file mode 100644 index 0000000..146e1b9 --- /dev/null +++ b/memcheck/tests/leak-cases-possible.vgtest @@ -0,0 +1,3 @@ +prog: leak-cases +vgopts: -q --leak-check=full --leak-resolution=high --show-possibly-lost=no +stderr_filter: filter_leak_cases_possible diff --git a/memcheck/tests/leak-cases.c b/memcheck/tests/leak-cases.c index e6a010a..026e7d2 100644 --- a/memcheck/tests/leak-cases.c +++ b/memcheck/tests/leak-cases.c @@ -106,6 +106,7 @@ int main(void) // counting in main() avoids the problem. f(); + CLEAR_CALLER_SAVED_REGS; GET_FINAL_LEAK_COUNTS; PRINT_LEAK_COUNTS(stderr); diff --git a/memcheck/tests/leak-cycle.c b/memcheck/tests/leak-cycle.c index 76dae77..cee967b 100644 --- a/memcheck/tests/leak-cycle.c +++ b/memcheck/tests/leak-cycle.c @@ -68,6 +68,8 @@ int main() c1 = c2 = 0; + CLEAR_CALLER_SAVED_REGS; + GET_FINAL_LEAK_COUNTS; PRINT_LEAK_COUNTS(stderr); diff --git a/memcheck/tests/leak.h b/memcheck/tests/leak.h index ec94fe0..ac8a64c 100644 --- a/memcheck/tests/leak.h +++ b/memcheck/tests/leak.h @@ -41,3 +41,27 @@ S_bytes,S_blocks); \ } while (0) +/* Upon a call to a function, some architectures store pointers into + * into registers. Valgrind may consider these registers when determining + * whether an address is reachable, so we need to zero-out these registers + * as needed. + */ +#if defined __powerpc__ +#define CLEAR_CALLER_SAVED_REGS \ + do { \ + __asm__ __volatile__( "li 3, 0" : : :/*trash*/"r3" ); \ + __asm__ __volatile__( "li 4, 0" : : :/*trash*/"r4" ); \ + __asm__ __volatile__( "li 5, 0" : : :/*trash*/"r5" ); \ + __asm__ __volatile__( "li 6, 0" : : :/*trash*/"r6" ); \ + __asm__ __volatile__( "li 7, 0" : : :/*trash*/"r7" ); \ + __asm__ __volatile__( "li 8, 0" : : :/*trash*/"r8" ); \ + __asm__ __volatile__( "li 9, 0" : : :/*trash*/"r9" ); \ + __asm__ __volatile__( "li 10, 0" : : :/*trash*/"r10" ); \ + __asm__ __volatile__( "li 11, 0" : : :/*trash*/"r11" ); \ + __asm__ __volatile__( "li 12, 0" : : :/*trash*/"r12" ); \ + } while (0) +#else +#define CLEAR_CALLER_SAVED_REGS /*nothing*/ +#endif + + diff --git a/memcheck/tests/linux/Makefile.am b/memcheck/tests/linux/Makefile.am index a7a2d02..4bd7751 100644 --- a/memcheck/tests/linux/Makefile.am +++ b/memcheck/tests/linux/Makefile.am @@ -8,6 +8,7 @@ EXTRA_DIST = \ capget capget.stderr.exp \ lsframe1.vgtest lsframe1.stdout.exp lsframe1.stderr.exp \ lsframe2.vgtest lsframe2.stdout.exp lsframe2.stderr.exp \ + sigqueue.vgtest sigqueue.stderr.exp \ stack_changes.stderr.exp stack_changes.stdout.exp \ stack_changes.stdout.exp2 stack_changes.vgtest \ stack_switch.stderr.exp stack_switch.vgtest \ @@ -19,6 +20,7 @@ check_PROGRAMS = \ capget \ lsframe1 \ lsframe2 \ + sigqueue \ stack_changes \ stack_switch \ timerfd-syscall diff --git a/memcheck/tests/linux/sigqueue.c b/memcheck/tests/linux/sigqueue.c new file mode 100644 index 0000000..d18bd72 --- /dev/null +++ b/memcheck/tests/linux/sigqueue.c @@ -0,0 +1,36 @@ +/* Test program that invokes the Linux system call rt_sigqueueinfo(). */ + +#include +#include +#include +#include +#include +#include +#include + +int main(int argc, char **argv) +{ + siginfo_t *si; + const size_t sz = sizeof(*si); + + if (argc == 1) { + fprintf(stderr, "sizeof(*si) = %zu\n", sz); + fprintf(stdout, "offsetof(siginfo_t, si_signo) = %zd\n", + offsetof(siginfo_t, si_signo)); + fprintf(stdout, "offsetof(siginfo_t, si_errno) = %zd\n", + offsetof(siginfo_t, si_errno)); + fprintf(stdout, "offsetof(siginfo_t, si_code) = %zd\n", + offsetof(siginfo_t, si_code)); + fprintf(stdout, "offsetof(siginfo_t, _sifields) = %zd\n", + offsetof(siginfo_t, _sifields)); + } + si = calloc(1, sz); + si->si_signo = SIGWINCH; + si->si_code = SI_QUEUE; + si->si_pid = getpid(); + si->si_uid = getuid(); + syscall(__NR_rt_sigqueueinfo, getpid(), SIGWINCH, si); + free(si); + fprintf(stderr, "Done.\n"); + return 0; +} diff --git a/memcheck/tests/linux/sigqueue.stderr.exp b/memcheck/tests/linux/sigqueue.stderr.exp new file mode 100644 index 0000000..324c857 --- /dev/null +++ b/memcheck/tests/linux/sigqueue.stderr.exp @@ -0,0 +1,11 @@ + +Done. + +HEAP SUMMARY: + in use at exit: 0 bytes in 0 blocks + total heap usage: 1 allocs, 1 frees, 128 bytes allocated + +For a detailed leak analysis, rerun with: --leak-check=full + +For counts of detected and suppressed errors, rerun with: -v +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/linux/sigqueue.vgtest b/memcheck/tests/linux/sigqueue.vgtest new file mode 100644 index 0000000..1c2ac61 --- /dev/null +++ b/memcheck/tests/linux/sigqueue.vgtest @@ -0,0 +1,2 @@ +prog: sigqueue +args: -q diff --git a/memcheck/tests/linux/timerfd-syscall.c b/memcheck/tests/linux/timerfd-syscall.c index 1e5ba53..3a7862f 100644 --- a/memcheck/tests/linux/timerfd-syscall.c +++ b/memcheck/tests/linux/timerfd-syscall.c @@ -5,7 +5,7 @@ * timerfd-test2 by Davide Libenzi (test app for timerfd) * Copyright (C) 2007 Davide Libenzi * Modified for inclusion in Valgrind. - * Copyright (C) 2008 Bart Van Assche + * Copyright (C) 2008 Bart Van Assche * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -153,7 +153,7 @@ long waittmr(int tfd, int timeo) } if ((pfd.revents & POLLIN) == 0) { - fprintf(stdout, "no ticks happened\n"); + fprintf(stderr, "no ticks happened\n"); return -1; } if (read(tfd, &ticks, sizeof(ticks)) != sizeof(ticks)) @@ -182,11 +182,11 @@ int main(int ac, char **av) for (i = 0; i < sizeof(clks) / sizeof(clks[0]); i++) { - fprintf(stdout, "\n\n---------------------------------------\n"); - fprintf(stdout, "| testing %s\n", clks[i].name); - fprintf(stdout, "---------------------------------------\n\n"); + fprintf(stderr, "\n\n---------------------------------------\n"); + fprintf(stderr, "| testing %s\n", clks[i].name); + fprintf(stderr, "---------------------------------------\n\n"); - fprintf(stdout, "relative timer test (at 500 ms) ...\n"); + fprintf(stderr, "relative timer test (at 500 ms) ...\n"); set_timespec(&tmr.it_value, 500 * 1000); set_timespec(&tmr.it_interval, 0); tnow = getustime(clks[i].id); @@ -202,17 +202,17 @@ int main(int ac, char **av) return 1; } - fprintf(stdout, "wating timer ...\n"); + fprintf(stderr, "waiting timer ...\n"); ticks = waittmr(tfd, -1); ttmr = getustime(clks[i].id); if (ticks <= 0) - fprintf(stdout, "whooops! no timer showed up!\n"); + fprintf(stderr, "whooops! no timer showed up!\n"); else - fprintf(stdout, "got timer ticks (%ld) after %.1f s\n", + fprintf(stderr, "got timer ticks (%ld) after %.1f s\n", ticks, (ttmr - tnow) * 1e-6); - fprintf(stdout, "absolute timer test (at 500 ms) ...\n"); + fprintf(stderr, "absolute timer test (at 500 ms) ...\n"); tnow = getustime(clks[i].id); set_timespec(&tmr.it_value, tnow + 500 * 1000); set_timespec(&tmr.it_interval, 0); @@ -222,16 +222,16 @@ int main(int ac, char **av) return 1; } - fprintf(stdout, "wating timer ...\n"); + fprintf(stderr, "waiting timer ...\n"); ticks = waittmr(tfd, -1); ttmr = getustime(clks[i].id); if (ticks <= 0) - fprintf(stdout, "whooops! no timer showed up!\n"); + fprintf(stderr, "whooops! no timer showed up!\n"); else - fprintf(stdout, "got timer ticks (%ld) after %.1f s\n", + fprintf(stderr, "got timer ticks (%ld) after %.1f s\n", ticks, (ttmr - tnow) * 1e-6); - fprintf(stdout, "sequential timer test (100 ms clock) ...\n"); + fprintf(stderr, "sequential timer test (100 ms clock) ...\n"); tnow = getustime(clks[i].id); set_timespec(&tmr.it_value, tnow + 100 * 1000); set_timespec(&tmr.it_interval, 100 * 1000); @@ -241,31 +241,36 @@ int main(int ac, char **av) return 1; } - fprintf(stdout, "sleeping one second ...\n"); + fprintf(stderr, "sleeping one second ...\n"); sleep(1); if (timerfd_gettime(tfd, &tmr)) { perror("timerfd_gettime"); return 1; } - fprintf(stdout, "timerfd_gettime returned:\n" + fprintf(stderr, "timerfd_gettime returned:\n" "\tit_value = %.1f it_interval = %.1f\n", tmr.it_value.tv_sec + 1e-9 * tmr.it_value.tv_nsec, tmr.it_interval.tv_sec + 1e-9 * tmr.it_interval.tv_nsec); - fprintf(stdout, "sleeping 1 second ...\n"); + fprintf(stderr, "sleeping 1 second ...\n"); sleep(1); - fprintf(stdout, "wating timer ...\n"); + fprintf(stderr, "waiting timer ...\n"); ticks = waittmr(tfd, -1); ttmr = getustime(clks[i].id); if (ticks <= 0) - fprintf(stdout, "whooops! no timer showed up!\n"); + fprintf(stderr, "whooops! no timer showed up!\n"); else - fprintf(stdout, "got timer ticks (%ld) after %.1f s\n", - ticks, (ttmr - tnow) * 1e-6); + { + const double delta = (ttmr - tnow) * 1e-6; + if (1.9 < delta && delta < 2.1) + fprintf(stderr, "got timer ticks (%ld) after about 2s\n", ticks); + else + fprintf(stderr, "got timer ticks (%ld) after %.1f s\n", ticks, delta); + } - fprintf(stdout, "O_NONBLOCK test ...\n"); + fprintf(stderr, "O_NONBLOCK test ...\n"); tnow = getustime(clks[i].id); set_timespec(&tmr.it_value, 100 * 1000); set_timespec(&tmr.it_interval, 0); @@ -275,27 +280,27 @@ int main(int ac, char **av) return 1; } #if 0 - fprintf(stdout, "timerfd = %d\n", tfd); + fprintf(stderr, "timerfd = %d\n", tfd); #endif - fprintf(stdout, "wating timer (flush the single tick) ...\n"); + fprintf(stderr, "waiting timer (flush the single tick) ...\n"); ticks = waittmr(tfd, -1); ttmr = getustime(clks[i].id); if (ticks <= 0) - fprintf(stdout, "whooops! no timer showed up!\n"); + fprintf(stderr, "whooops! no timer showed up!\n"); else - fprintf(stdout, "got timer ticks (%ld) after %.1f s\n", + fprintf(stderr, "got timer ticks (%ld) after %.1f s\n", ticks, (ttmr - tnow) * 1e-6); fcntl(tfd, F_SETFL, fcntl(tfd, F_GETFL, 0) | O_NONBLOCK); if (read(tfd, &uticks, sizeof(uticks)) > 0) - fprintf(stdout, "whooops! timer ticks not zero when should have been\n"); + fprintf(stderr, "whooops! timer ticks not zero when should have been\n"); else if (errno != EAGAIN) - fprintf(stdout, "whooops! bad errno value (%d = '%s')!\n", + fprintf(stderr, "whooops! bad errno value (%d = '%s')!\n", errno, strerror(errno)); else - fprintf(stdout, "success\n"); + fprintf(stderr, "success\n"); fcntl(tfd, F_SETFL, fcntl(tfd, F_GETFL, 0) & ~O_NONBLOCK); diff --git a/memcheck/tests/linux/timerfd-syscall.stderr.exp b/memcheck/tests/linux/timerfd-syscall.stderr.exp index c22dd7f..247ce1f 100644 --- a/memcheck/tests/linux/timerfd-syscall.stderr.exp +++ b/memcheck/tests/linux/timerfd-syscall.stderr.exp @@ -1,5 +1,51 @@ + +--------------------------------------- +| testing CLOCK MONOTONIC +--------------------------------------- + +relative timer test (at 500 ms) ... +waiting timer ... +got timer ticks (1) after 0.5 s +absolute timer test (at 500 ms) ... +waiting timer ... +got timer ticks (1) after 0.5 s +sequential timer test (100 ms clock) ... +sleeping one second ... +timerfd_gettime returned: + it_value = 0.1 it_interval = 0.1 +sleeping 1 second ... +waiting timer ... +got timer ticks (20) after about 2s +O_NONBLOCK test ... +waiting timer (flush the single tick) ... +got timer ticks (1) after 0.1 s +success + + +--------------------------------------- +| testing CLOCK REALTIME +--------------------------------------- + +relative timer test (at 500 ms) ... +waiting timer ... +got timer ticks (1) after 0.5 s +absolute timer test (at 500 ms) ... +waiting timer ... +got timer ticks (1) after 0.5 s +sequential timer test (100 ms clock) ... +sleeping one second ... +timerfd_gettime returned: + it_value = 0.1 it_interval = 0.1 +sleeping 1 second ... +waiting timer ... +got timer ticks (20) after about 2s +O_NONBLOCK test ... +waiting timer (flush the single tick) ... +got timer ticks (1) after 0.1 s +success + HEAP SUMMARY: in use at exit: 0 bytes in 0 blocks total heap usage: 0 allocs, 0 frees, 0 bytes allocated diff --git a/memcheck/tests/linux/timerfd-syscall.stdout.exp b/memcheck/tests/linux/timerfd-syscall.stdout.exp deleted file mode 100644 index 651d6f3..0000000 --- a/memcheck/tests/linux/timerfd-syscall.stdout.exp +++ /dev/null @@ -1,46 +0,0 @@ - - ---------------------------------------- -| testing CLOCK MONOTONIC ---------------------------------------- - -relative timer test (at 500 ms) ... -wating timer ... -got timer ticks (1) after 0.5 s -absolute timer test (at 500 ms) ... -wating timer ... -got timer ticks (1) after 0.5 s -sequential timer test (100 ms clock) ... -sleeping one second ... -timerfd_gettime returned: - it_value = 0.1 it_interval = 0.1 -sleeping 1 second ... -wating timer ... -got timer ticks (20) after 2.0 s -O_NONBLOCK test ... -wating timer (flush the single tick) ... -got timer ticks (1) after 0.1 s -success - - ---------------------------------------- -| testing CLOCK REALTIME ---------------------------------------- - -relative timer test (at 500 ms) ... -wating timer ... -got timer ticks (1) after 0.5 s -absolute timer test (at 500 ms) ... -wating timer ... -got timer ticks (1) after 0.5 s -sequential timer test (100 ms clock) ... -sleeping one second ... -timerfd_gettime returned: - it_value = 0.1 it_interval = 0.1 -sleeping 1 second ... -wating timer ... -got timer ticks (20) after 2.0 s -O_NONBLOCK test ... -wating timer (flush the single tick) ... -got timer ticks (1) after 0.1 s -success diff --git a/memcheck/tests/long_namespace_xml.cpp b/memcheck/tests/long_namespace_xml.cpp index 0275a57..cd34d06 100644 --- a/memcheck/tests/long_namespace_xml.cpp +++ b/memcheck/tests/long_namespace_xml.cpp @@ -14,23 +14,34 @@ int main () { #else +#define N1 abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefgh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+ +#define N2 ABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZ + #include #include +#include + using namespace std; -namespace abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefgh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{ - namespace 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{ +// A function that returns p in such a way that gcc 4.5.x does not recognize +// that it returns p. Prevents that the optimizer throws the assignment away +// that occurs just before the free() call. +static char* idem(char* p) { return (char*)((uintptr_t)p * 2 / 2); } + +namespace N1 { + namespace N2 { void f() { cout << "I'm in an asininely long namespace!" << endl; char *ptr = (char *)malloc (4); - ptr[5] = 0; + idem(ptr)[5] = 0; free(ptr); } } } int main() { - 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+ N1::N2::f(); return 0; } diff --git a/memcheck/tests/origin5-bz2.stderr.exp-glibc27-ppc64 b/memcheck/tests/origin5-bz2.stderr.exp-glibc27-ppc64 index 6dfe8df..e0958e4 100644 --- a/memcheck/tests/origin5-bz2.stderr.exp-glibc27-ppc64 +++ b/memcheck/tests/origin5-bz2.stderr.exp-glibc27-ppc64 @@ -28,7 +28,8 @@ Use of uninitialised value of size 8 at 0x........: main (origin5-bz2.c:6481) Use of uninitialised value of size 8 - at 0x........: BZ2_blockSort (origin5-bz2.c:2820) + at 0x........: mainSort (origin5-bz2.c:2820) + by 0x........: BZ2_blockSort (origin5-bz2.c:3105) by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) by 0x........: handle_compress (origin5-bz2.c:4753) by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) @@ -38,7 +39,8 @@ Use of uninitialised value of size 8 at 0x........: main (origin5-bz2.c:6481) Use of uninitialised value of size 8 - at 0x........: BZ2_blockSort (origin5-bz2.c:2823) + at 0x........: mainSort (origin5-bz2.c:2823) + by 0x........: BZ2_blockSort (origin5-bz2.c:3105) by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) by 0x........: handle_compress (origin5-bz2.c:4753) by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) @@ -48,7 +50,8 @@ Use of uninitialised value of size 8 at 0x........: main (origin5-bz2.c:6481) Use of uninitialised value of size 8 - at 0x........: BZ2_blockSort (origin5-bz2.c:2854) + at 0x........: mainSort (origin5-bz2.c:2854) + by 0x........: BZ2_blockSort (origin5-bz2.c:3105) by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) by 0x........: handle_compress (origin5-bz2.c:4753) by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) @@ -58,7 +61,8 @@ Use of uninitialised value of size 8 at 0x........: main (origin5-bz2.c:6481) Use of uninitialised value of size 8 - at 0x........: BZ2_blockSort (origin5-bz2.c:2858) + at 0x........: mainSort (origin5-bz2.c:2858) + by 0x........: BZ2_blockSort (origin5-bz2.c:3105) by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) by 0x........: handle_compress (origin5-bz2.c:4753) by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) @@ -68,7 +72,8 @@ Use of uninitialised value of size 8 at 0x........: main (origin5-bz2.c:6481) Use of uninitialised value of size 8 - at 0x........: BZ2_blockSort (origin5-bz2.c:2963) + at 0x........: mainSort (origin5-bz2.c:2963) + by 0x........: BZ2_blockSort (origin5-bz2.c:3105) by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) by 0x........: handle_compress (origin5-bz2.c:4753) by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) @@ -78,7 +83,8 @@ Use of uninitialised value of size 8 at 0x........: main (origin5-bz2.c:6481) Use of uninitialised value of size 8 - at 0x........: BZ2_blockSort (origin5-bz2.c:2964) + at 0x........: mainSort (origin5-bz2.c:2964) + by 0x........: BZ2_blockSort (origin5-bz2.c:3105) by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) by 0x........: handle_compress (origin5-bz2.c:4753) by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) diff --git a/memcheck/tests/partiallydefinedeq.c b/memcheck/tests/partiallydefinedeq.c index 888240e..7d63126 100644 --- a/memcheck/tests/partiallydefinedeq.c +++ b/memcheck/tests/partiallydefinedeq.c @@ -57,9 +57,16 @@ int main ( void ) // Note: on ppc32/64 the second call to foo() does give an error, // since the expensive EQ/NE scheme does not apply to the CmpORD // primops used by ppc. -static void bar ( void ) +// +// On arm, the "normal" (x86-like) comparison primops are used, so +// the expensive EQ/NE scheme could apply. However, it doesn't, +// because the constant 0x80808080 is placed in a constant pool +// and so never appears as a literal, and so the instrumenter +// never spots it and so doesn't use the expensive scheme (for foo). +// Hence also on ARM we get 3 errors, not 2. +static __attribute__((noinline)) void bar ( void ) { -#if defined(__powerpc__) || defined(__powerpc64__) - fprintf(stderr, "Currently running on ppc32/64: this test should give 3 errors, not 2.\n"); +#if defined(__powerpc__) || defined(__powerpc64__) || defined(__arm__) + fprintf(stderr, "Currently running on ppc32/64/arm: this test should give 3 errors, not 2.\n"); #endif } diff --git a/memcheck/tests/partiallydefinedeq.stderr.exp2 b/memcheck/tests/partiallydefinedeq.stderr.exp2 index 3b81c25..19b46ae 100644 --- a/memcheck/tests/partiallydefinedeq.stderr.exp2 +++ b/memcheck/tests/partiallydefinedeq.stderr.exp2 @@ -1,5 +1,5 @@ -Currently running on ppc32/64: this test should give 3 errors, not 2. +Currently running on ppc32/64/arm: this test should give 3 errors, not 2. Conditional jump or move depends on uninitialised value(s) at 0x........: foo (partiallydefinedeq.c:15) by 0x........: main (partiallydefinedeq.c:37) @@ -22,4 +22,3 @@ For a detailed leak analysis, rerun with: --leak-check=full For counts of detected and suppressed errors, rerun with: -v Use --track-origins=yes to see where uninitialised values come from ERROR SUMMARY: 3 errors from 3 contexts (suppressed: 0 from 0) - diff --git a/memcheck/tests/ppc32/Makefile.am b/memcheck/tests/ppc32/Makefile.am new file mode 100644 index 0000000..40033fc --- /dev/null +++ b/memcheck/tests/ppc32/Makefile.am @@ -0,0 +1,13 @@ + +include $(top_srcdir)/Makefile.tool-tests.am + +dist_noinst_SCRIPTS = filter_stderr + +EXTRA_DIST = $(noinst_SCRIPTS) \ + power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest + +check_PROGRAMS = \ + power_ISA2_05 + +power_ISA2_05_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \ + -I$(top_srcdir)/include @FLAG_M32@ diff --git a/memcheck/tests/ppc32/filter_stderr b/memcheck/tests/ppc32/filter_stderr new file mode 100755 index 0000000..0ae9313 --- /dev/null +++ b/memcheck/tests/ppc32/filter_stderr @@ -0,0 +1,3 @@ +#! /bin/sh + +../filter_stderr diff --git a/memcheck/tests/ppc32/power_ISA2_05.c b/memcheck/tests/ppc32/power_ISA2_05.c new file mode 100644 index 0000000..82893a2 --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.c @@ -0,0 +1,207 @@ +#include + +double foo = -1.0; +double FRT1; +double FRT2; +int base256(int val) +{ +/* interpret the bitstream representing val as a base 256 number for testing + * the parity instrs + */ + int sum = 0; + int scale = 1; + int i; + + for (i = 0; i < 8; i++) { + int bit = val & 1; + sum = sum + bit * scale; + val <<= 1; + scale *= 256; + } + return sum; +} + +void test_parity_instrs() +{ + unsigned long long_word; + unsigned int word; + int i, parity; + + for (i = 0; i < 50; i++) { + word = base256(i); + long_word = word; + __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word)); + printf("prtyd (%x) => parity=%x\n", i, parity); + __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word)); + printf("prtyw (%x) => parity=%x\n", i, parity); + } +} + +void test_lfiwax() +{ + unsigned long base; + unsigned long offset; + + typedef struct { + unsigned int hi; + unsigned int lo; + } int_pair_t; + + int_pair_t *ip; + foo = -1024.0; + base = (unsigned long) &foo; + offset = 0; + __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base), + "r"(offset)); + ip = (int_pair_t *) & FRT1; + printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo); + + +} + + + +/* lfdp FPp, DS(RA) : load float double pair +** FPp = leftmost 64 bits stored at DS(RA) +** FPp+1= rightmost 64 bits stored at DS(RA) +** FPp must be an even float register +*/ +int test_double_pair_instrs() +{ + typedef struct { + double hi; + double lo; + } dbl_pair_t; + + /* the following decls are for alignment */ + int i; + int j; + int k; + int l; +#ifdef __powerpc64__ + int m; + int n; + int o; +#endif + dbl_pair_t dbl_pair[3]; /* must be quad word aligned */ + unsigned long base; + unsigned long offset; + + for (i = 0; i < 3; i++) { + dbl_pair[i].hi = -1024.0 + i; + dbl_pair[i].lo = 1024.0 + i + 1; + } + + __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0])); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n", + dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2); + + + FRT1 = 2.2048; + FRT2 = -4.1024; + __asm__ volatile ("fmr 10, %0"::"f" (FRT1)); + __asm__ volatile ("fmr 11, %0"::"f" (FRT2)); + __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1])); + printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n", + FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo); + + FRT1 = 0.0; + FRT2 = -1.0; + base = (unsigned long) &dbl_pair; + offset = (unsigned long) &dbl_pair[1] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("lfdpx 10, 20, 21"); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", + dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2); + + FRT1 = 8.2048; + FRT2 = -16.1024; + base = (unsigned long) &dbl_pair; + offset = (unsigned long) &dbl_pair[2] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + __asm__ volatile ("stfdpx 10, 20, 21"); + printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", + FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo); +#ifdef __powerpc64__ + return i + j + k + l + m + n + o; +#else + return i + j + k + l; +#endif +} + + +/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */ +void test_fcpsgn() +{ + double A[] = { + 10.101010, + -0.0, + 0.0, + -10.101010 + }; + + double B[] = { + 11.111111, + -0.0, + 0.0, + -11.111111 + }; + + double FRT, FRA, FRB; + int i, j; + + for (i = 0; i < 4; i++) { + FRA = A[i]; + for (j = 0; j < 4; j++) { + FRB = B[j]; + __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), + "f"(FRB)); + printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); + } + } +} + +/* b0 may be non-zero in lwarx/ldarx Power6 instrs */ +int test_reservation() +{ + + int RT; + int i, j; + unsigned long base; + unsigned long offset; + long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad }; + + + base = (unsigned long) &arr; + offset = (unsigned long) &arr[1] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT)); + printf("lwarx => %x\n", RT); + +#ifdef __powerpc64__ + offset = (unsigned long) &arr[1] - base; + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT)); + printf("ldarx => %x\n", RT); +#endif + return i + j; +} + +int main(void) +{ + (void) test_reservation(); + test_fcpsgn(); + (void) test_double_pair_instrs(); + test_lfiwax(); + test_parity_instrs(); + return 0; +} diff --git a/memcheck/tests/ppc32/power_ISA2_05.stderr.exp b/memcheck/tests/ppc32/power_ISA2_05.stderr.exp new file mode 100644 index 0000000..c22dd7f --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.stderr.exp @@ -0,0 +1,10 @@ + + +HEAP SUMMARY: + in use at exit: 0 bytes in 0 blocks + total heap usage: 0 allocs, 0 frees, 0 bytes allocated + +For a detailed leak analysis, rerun with: --leak-check=full + +For counts of detected and suppressed errors, rerun with: -v +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/ppc32/power_ISA2_05.stdout.exp b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp new file mode 100644 index 0000000..5513960 --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp @@ -0,0 +1,122 @@ +lwarx => bad0beef +fcpsgn sign=10.101010, base=11.111111 => 11.111111 +fcpsgn sign=10.101010, base=-0.000000 => 0.000000 +fcpsgn sign=10.101010, base=0.000000 => 0.000000 +fcpsgn sign=10.101010, base=-11.111111 => 11.111111 +fcpsgn sign=-0.000000, base=11.111111 => -11.111111 +fcpsgn sign=-0.000000, base=-0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=-11.111111 => -11.111111 +fcpsgn sign=0.000000, base=11.111111 => 11.111111 +fcpsgn sign=0.000000, base=-0.000000 => 0.000000 +fcpsgn sign=0.000000, base=0.000000 => 0.000000 +fcpsgn sign=0.000000, base=-11.111111 => 11.111111 +fcpsgn sign=-10.101010, base=11.111111 => -11.111111 +fcpsgn sign=-10.101010, base=-0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=-11.111111 => -11.111111 +lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000 +stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800 +lfiwax (-1024.000000) => FRT=(ffffffff, c0900000) +prtyd (0) => parity=0 +prtyw (0) => parity=0 +prtyd (1) => parity=1 +prtyw (1) => parity=1 +prtyd (2) => parity=0 +prtyw (2) => parity=0 +prtyd (3) => parity=1 +prtyw (3) => parity=1 +prtyd (4) => parity=0 +prtyw (4) => parity=0 +prtyd (5) => parity=1 +prtyw (5) => parity=1 +prtyd (6) => parity=0 +prtyw (6) => parity=0 +prtyd (7) => parity=1 +prtyw (7) => parity=1 +prtyd (8) => parity=0 +prtyw (8) => parity=0 +prtyd (9) => parity=1 +prtyw (9) => parity=1 +prtyd (a) => parity=0 +prtyw (a) => parity=0 +prtyd (b) => parity=1 +prtyw (b) => parity=1 +prtyd (c) => parity=0 +prtyw (c) => parity=0 +prtyd (d) => parity=1 +prtyw (d) => parity=1 +prtyd (e) => parity=0 +prtyw (e) => parity=0 +prtyd (f) => parity=1 +prtyw (f) => parity=1 +prtyd (10) => parity=0 +prtyw (10) => parity=0 +prtyd (11) => parity=1 +prtyw (11) => parity=1 +prtyd (12) => parity=0 +prtyw (12) => parity=0 +prtyd (13) => parity=1 +prtyw (13) => parity=1 +prtyd (14) => parity=0 +prtyw (14) => parity=0 +prtyd (15) => parity=1 +prtyw (15) => parity=1 +prtyd (16) => parity=0 +prtyw (16) => parity=0 +prtyd (17) => parity=1 +prtyw (17) => parity=1 +prtyd (18) => parity=0 +prtyw (18) => parity=0 +prtyd (19) => parity=1 +prtyw (19) => parity=1 +prtyd (1a) => parity=0 +prtyw (1a) => parity=0 +prtyd (1b) => parity=1 +prtyw (1b) => parity=1 +prtyd (1c) => parity=0 +prtyw (1c) => parity=0 +prtyd (1d) => parity=1 +prtyw (1d) => parity=1 +prtyd (1e) => parity=0 +prtyw (1e) => parity=0 +prtyd (1f) => parity=1 +prtyw (1f) => parity=1 +prtyd (20) => parity=0 +prtyw (20) => parity=0 +prtyd (21) => parity=1 +prtyw (21) => parity=1 +prtyd (22) => parity=0 +prtyw (22) => parity=0 +prtyd (23) => parity=1 +prtyw (23) => parity=1 +prtyd (24) => parity=0 +prtyw (24) => parity=0 +prtyd (25) => parity=1 +prtyw (25) => parity=1 +prtyd (26) => parity=0 +prtyw (26) => parity=0 +prtyd (27) => parity=1 +prtyw (27) => parity=1 +prtyd (28) => parity=0 +prtyw (28) => parity=0 +prtyd (29) => parity=1 +prtyw (29) => parity=1 +prtyd (2a) => parity=0 +prtyw (2a) => parity=0 +prtyd (2b) => parity=1 +prtyw (2b) => parity=1 +prtyd (2c) => parity=0 +prtyw (2c) => parity=0 +prtyd (2d) => parity=1 +prtyw (2d) => parity=1 +prtyd (2e) => parity=0 +prtyw (2e) => parity=0 +prtyd (2f) => parity=1 +prtyw (2f) => parity=1 +prtyd (30) => parity=0 +prtyw (30) => parity=0 +prtyd (31) => parity=1 +prtyw (31) => parity=1 diff --git a/memcheck/tests/ppc32/power_ISA2_05.vgtest b/memcheck/tests/ppc32/power_ISA2_05.vgtest new file mode 100644 index 0000000..712ec3b --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.vgtest @@ -0,0 +1 @@ +prog: power_ISA2_05 diff --git a/memcheck/tests/ppc64/Makefile.am b/memcheck/tests/ppc64/Makefile.am new file mode 100644 index 0000000..a18afd7 --- /dev/null +++ b/memcheck/tests/ppc64/Makefile.am @@ -0,0 +1,13 @@ + +include $(top_srcdir)/Makefile.tool-tests.am + +dist_noinst_SCRIPTS = filter_stderr + +EXTRA_DIST = $(noinst_SCRIPTS) \ + power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest + +check_PROGRAMS = \ + power_ISA2_05 + +power_ISA2_05_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \ + -I$(top_srcdir)/include @FLAG_M64@ diff --git a/memcheck/tests/ppc64/filter_stderr b/memcheck/tests/ppc64/filter_stderr new file mode 100755 index 0000000..0ae9313 --- /dev/null +++ b/memcheck/tests/ppc64/filter_stderr @@ -0,0 +1,3 @@ +#! /bin/sh + +../filter_stderr diff --git a/memcheck/tests/ppc64/power_ISA2_05.c b/memcheck/tests/ppc64/power_ISA2_05.c new file mode 100644 index 0000000..82893a2 --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.c @@ -0,0 +1,207 @@ +#include + +double foo = -1.0; +double FRT1; +double FRT2; +int base256(int val) +{ +/* interpret the bitstream representing val as a base 256 number for testing + * the parity instrs + */ + int sum = 0; + int scale = 1; + int i; + + for (i = 0; i < 8; i++) { + int bit = val & 1; + sum = sum + bit * scale; + val <<= 1; + scale *= 256; + } + return sum; +} + +void test_parity_instrs() +{ + unsigned long long_word; + unsigned int word; + int i, parity; + + for (i = 0; i < 50; i++) { + word = base256(i); + long_word = word; + __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word)); + printf("prtyd (%x) => parity=%x\n", i, parity); + __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word)); + printf("prtyw (%x) => parity=%x\n", i, parity); + } +} + +void test_lfiwax() +{ + unsigned long base; + unsigned long offset; + + typedef struct { + unsigned int hi; + unsigned int lo; + } int_pair_t; + + int_pair_t *ip; + foo = -1024.0; + base = (unsigned long) &foo; + offset = 0; + __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base), + "r"(offset)); + ip = (int_pair_t *) & FRT1; + printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo); + + +} + + + +/* lfdp FPp, DS(RA) : load float double pair +** FPp = leftmost 64 bits stored at DS(RA) +** FPp+1= rightmost 64 bits stored at DS(RA) +** FPp must be an even float register +*/ +int test_double_pair_instrs() +{ + typedef struct { + double hi; + double lo; + } dbl_pair_t; + + /* the following decls are for alignment */ + int i; + int j; + int k; + int l; +#ifdef __powerpc64__ + int m; + int n; + int o; +#endif + dbl_pair_t dbl_pair[3]; /* must be quad word aligned */ + unsigned long base; + unsigned long offset; + + for (i = 0; i < 3; i++) { + dbl_pair[i].hi = -1024.0 + i; + dbl_pair[i].lo = 1024.0 + i + 1; + } + + __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0])); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n", + dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2); + + + FRT1 = 2.2048; + FRT2 = -4.1024; + __asm__ volatile ("fmr 10, %0"::"f" (FRT1)); + __asm__ volatile ("fmr 11, %0"::"f" (FRT2)); + __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1])); + printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n", + FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo); + + FRT1 = 0.0; + FRT2 = -1.0; + base = (unsigned long) &dbl_pair; + offset = (unsigned long) &dbl_pair[1] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("lfdpx 10, 20, 21"); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", + dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2); + + FRT1 = 8.2048; + FRT2 = -16.1024; + base = (unsigned long) &dbl_pair; + offset = (unsigned long) &dbl_pair[2] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); + __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); + __asm__ volatile ("stfdpx 10, 20, 21"); + printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", + FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo); +#ifdef __powerpc64__ + return i + j + k + l + m + n + o; +#else + return i + j + k + l; +#endif +} + + +/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */ +void test_fcpsgn() +{ + double A[] = { + 10.101010, + -0.0, + 0.0, + -10.101010 + }; + + double B[] = { + 11.111111, + -0.0, + 0.0, + -11.111111 + }; + + double FRT, FRA, FRB; + int i, j; + + for (i = 0; i < 4; i++) { + FRA = A[i]; + for (j = 0; j < 4; j++) { + FRB = B[j]; + __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), + "f"(FRB)); + printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); + } + } +} + +/* b0 may be non-zero in lwarx/ldarx Power6 instrs */ +int test_reservation() +{ + + int RT; + int i, j; + unsigned long base; + unsigned long offset; + long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad }; + + + base = (unsigned long) &arr; + offset = (unsigned long) &arr[1] - base; + __asm__ volatile ("or 20, 0, %0"::"r" (base)); + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT)); + printf("lwarx => %x\n", RT); + +#ifdef __powerpc64__ + offset = (unsigned long) &arr[1] - base; + __asm__ volatile ("or 21, 0, %0"::"r" (offset)); + __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT)); + printf("ldarx => %x\n", RT); +#endif + return i + j; +} + +int main(void) +{ + (void) test_reservation(); + test_fcpsgn(); + (void) test_double_pair_instrs(); + test_lfiwax(); + test_parity_instrs(); + return 0; +} diff --git a/memcheck/tests/ppc64/power_ISA2_05.stderr.exp b/memcheck/tests/ppc64/power_ISA2_05.stderr.exp new file mode 100644 index 0000000..c22dd7f --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.stderr.exp @@ -0,0 +1,10 @@ + + +HEAP SUMMARY: + in use at exit: 0 bytes in 0 blocks + total heap usage: 0 allocs, 0 frees, 0 bytes allocated + +For a detailed leak analysis, rerun with: --leak-check=full + +For counts of detected and suppressed errors, rerun with: -v +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/ppc64/power_ISA2_05.stdout.exp b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp new file mode 100644 index 0000000..b5a7458 --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp @@ -0,0 +1,123 @@ +lwarx => 0 +ldarx => bad0beef +fcpsgn sign=10.101010, base=11.111111 => 11.111111 +fcpsgn sign=10.101010, base=-0.000000 => 0.000000 +fcpsgn sign=10.101010, base=0.000000 => 0.000000 +fcpsgn sign=10.101010, base=-11.111111 => 11.111111 +fcpsgn sign=-0.000000, base=11.111111 => -11.111111 +fcpsgn sign=-0.000000, base=-0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=-11.111111 => -11.111111 +fcpsgn sign=0.000000, base=11.111111 => 11.111111 +fcpsgn sign=0.000000, base=-0.000000 => 0.000000 +fcpsgn sign=0.000000, base=0.000000 => 0.000000 +fcpsgn sign=0.000000, base=-11.111111 => 11.111111 +fcpsgn sign=-10.101010, base=11.111111 => -11.111111 +fcpsgn sign=-10.101010, base=-0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=-11.111111 => -11.111111 +lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000 +stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +stfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 +lfiwax (-1024.000000) => FRT=(ffffffff, c0900000) +prtyd (0) => parity=0 +prtyw (0) => parity=0 +prtyd (1) => parity=1 +prtyw (1) => parity=1 +prtyd (2) => parity=0 +prtyw (2) => parity=0 +prtyd (3) => parity=1 +prtyw (3) => parity=1 +prtyd (4) => parity=0 +prtyw (4) => parity=0 +prtyd (5) => parity=1 +prtyw (5) => parity=1 +prtyd (6) => parity=0 +prtyw (6) => parity=0 +prtyd (7) => parity=1 +prtyw (7) => parity=1 +prtyd (8) => parity=0 +prtyw (8) => parity=0 +prtyd (9) => parity=1 +prtyw (9) => parity=1 +prtyd (a) => parity=0 +prtyw (a) => parity=0 +prtyd (b) => parity=1 +prtyw (b) => parity=1 +prtyd (c) => parity=0 +prtyw (c) => parity=0 +prtyd (d) => parity=1 +prtyw (d) => parity=1 +prtyd (e) => parity=0 +prtyw (e) => parity=0 +prtyd (f) => parity=1 +prtyw (f) => parity=1 +prtyd (10) => parity=0 +prtyw (10) => parity=0 +prtyd (11) => parity=1 +prtyw (11) => parity=1 +prtyd (12) => parity=0 +prtyw (12) => parity=0 +prtyd (13) => parity=1 +prtyw (13) => parity=1 +prtyd (14) => parity=0 +prtyw (14) => parity=0 +prtyd (15) => parity=1 +prtyw (15) => parity=1 +prtyd (16) => parity=0 +prtyw (16) => parity=0 +prtyd (17) => parity=1 +prtyw (17) => parity=1 +prtyd (18) => parity=0 +prtyw (18) => parity=0 +prtyd (19) => parity=1 +prtyw (19) => parity=1 +prtyd (1a) => parity=0 +prtyw (1a) => parity=0 +prtyd (1b) => parity=1 +prtyw (1b) => parity=1 +prtyd (1c) => parity=0 +prtyw (1c) => parity=0 +prtyd (1d) => parity=1 +prtyw (1d) => parity=1 +prtyd (1e) => parity=0 +prtyw (1e) => parity=0 +prtyd (1f) => parity=1 +prtyw (1f) => parity=1 +prtyd (20) => parity=0 +prtyw (20) => parity=0 +prtyd (21) => parity=1 +prtyw (21) => parity=1 +prtyd (22) => parity=0 +prtyw (22) => parity=0 +prtyd (23) => parity=1 +prtyw (23) => parity=1 +prtyd (24) => parity=0 +prtyw (24) => parity=0 +prtyd (25) => parity=1 +prtyw (25) => parity=1 +prtyd (26) => parity=0 +prtyw (26) => parity=0 +prtyd (27) => parity=1 +prtyw (27) => parity=1 +prtyd (28) => parity=0 +prtyw (28) => parity=0 +prtyd (29) => parity=1 +prtyw (29) => parity=1 +prtyd (2a) => parity=0 +prtyw (2a) => parity=0 +prtyd (2b) => parity=1 +prtyw (2b) => parity=1 +prtyd (2c) => parity=0 +prtyw (2c) => parity=0 +prtyd (2d) => parity=1 +prtyw (2d) => parity=1 +prtyd (2e) => parity=0 +prtyw (2e) => parity=0 +prtyd (2f) => parity=1 +prtyw (2f) => parity=1 +prtyd (30) => parity=0 +prtyw (30) => parity=0 +prtyd (31) => parity=1 +prtyw (31) => parity=1 diff --git a/memcheck/tests/ppc64/power_ISA2_05.vgtest b/memcheck/tests/ppc64/power_ISA2_05.vgtest new file mode 100644 index 0000000..7f0006a --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.vgtest @@ -0,0 +1,2 @@ +prog: power_ISA2_05 +vgopts: --workaround-gcc296-bugs=yes diff --git a/memcheck/tests/sigprocmask.c b/memcheck/tests/sigprocmask.c index d2911aa..05eb87a 100644 --- a/memcheck/tests/sigprocmask.c +++ b/memcheck/tests/sigprocmask.c @@ -11,7 +11,12 @@ int main(void) { -#if defined(__NR_sigprocmask) && !defined(__powerpc64__) && !defined(_AIX) +#if defined(__NR_sigprocmask) \ + && !defined(__powerpc64__) \ + && !defined(_AIX) \ + && !defined(__arm__) + + // arm-linux uses rt_sigprocmask, so no sigset mangling takes place int x[6], *s, *os, i; diff --git a/memcheck/tests/varinfo1.stderr.exp-ppc64 b/memcheck/tests/varinfo1.stderr.exp-ppc64 new file mode 100644 index 0000000..c339195 --- /dev/null +++ b/memcheck/tests/varinfo1.stderr.exp-ppc64 @@ -0,0 +1,37 @@ +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo1.c:29) + by 0x........: main (varinfo1.c:49) + Address 0x........ is 1 bytes inside a block of size 3 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (varinfo1.c:47) + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo1.c:29) + by 0x........: main (varinfo1.c:52) + Location 0x........ is 0 bytes inside global var "global_u1" + declared at varinfo1.c:35 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo1.c:29) + by 0x........: main (varinfo1.c:53) + Location 0x........ is 0 bytes inside global var "global_i1" + declared at varinfo1.c:37 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo1.c:29) + by 0x........: main (varinfo1.c:54) + Location 0x........ is 0 bytes inside global_u2[3], + a global variable declared at varinfo1.c:39 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo1.c:29) + by 0x........: main (varinfo1.c:55) + Location 0x........ is 0 bytes inside global_i2[7], + a global variable declared at varinfo1.c:41 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo1.c:29) + by 0x........: main (varinfo1.c:56) + Location 0x........ is 0 bytes inside local var "local" + declared at varinfo1.c:46, in frame #1 of thread 1 + diff --git a/memcheck/tests/varinfo2.stderr.exp-ppc64 b/memcheck/tests/varinfo2.stderr.exp-ppc64 new file mode 100644 index 0000000..81d1179 --- /dev/null +++ b/memcheck/tests/varinfo2.stderr.exp-ppc64 @@ -0,0 +1,21 @@ +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo2.c:29) + by 0x........: foo (varinfo2.c:41) + by 0x........: main (varinfo2.c:51) + Location 0x........ is 0 bytes inside var[7], + declared at varinfo2.c:39, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo2.c:29) + by 0x........: foo (varinfo2.c:43) + by 0x........: main (varinfo2.c:51) + Location 0x........ is 2 bytes inside var.bar, + declared at varinfo2.c:42, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo2.c:29) + by 0x........: foo (varinfo2.c:46) + by 0x........: main (varinfo2.c:51) + Location 0x........ is 1 byte inside local var "var" + declared at varinfo2.c:37, in frame #1 of thread 1 + diff --git a/memcheck/tests/varinfo3.stderr.exp-ppc64 b/memcheck/tests/varinfo3.stderr.exp-ppc64 new file mode 100644 index 0000000..e02a3c8 --- /dev/null +++ b/memcheck/tests/varinfo3.stderr.exp-ppc64 @@ -0,0 +1,58 @@ +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo3.c:29) + by 0x........: foo (varinfo3.c:54) + by 0x........: main (varinfo3.c:66) + Location 0x........ is 0 bytes inside static_global_def[1], + declared at varinfo3.c:35, in frame #0 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo3.c:29) + by 0x........: foo (varinfo3.c:55) + by 0x........: main (varinfo3.c:66) + Location 0x........ is 0 bytes inside nonstatic_global_def[2], + a global variable declared at varinfo3.c:36 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo3.c:29) + by 0x........: foo (varinfo3.c:56) + by 0x........: main (varinfo3.c:66) + Location 0x........ is 0 bytes inside static_global_undef[3], + declared at varinfo3.c:37, in frame #0 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo3.c:29) + by 0x........: foo (varinfo3.c:57) + by 0x........: main (varinfo3.c:66) + Location 0x........ is 0 bytes inside nonstatic_global_undef[4], + a global variable declared at varinfo3.c:38 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo3.c:29) + by 0x........: bar (varinfo3.c:42) + by 0x........: foo (varinfo3.c:58) + by 0x........: main (varinfo3.c:66) + Address 0x........ is 5 bytes inside data symbol "static_local_def.XXXX" + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo3.c:29) + by 0x........: bar (varinfo3.c:43) + by 0x........: foo (varinfo3.c:58) + by 0x........: main (varinfo3.c:66) + Location 0x........ is 0 bytes inside nonstatic_local_def[6], + declared at varinfo3.c:51, in frame #2 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo3.c:29) + by 0x........: bar (varinfo3.c:44) + by 0x........: foo (varinfo3.c:58) + by 0x........: main (varinfo3.c:66) + Address 0x........ is 7 bytes inside data symbol "static_local_undef.XXXX" + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo3.c:29) + by 0x........: bar (varinfo3.c:45) + by 0x........: foo (varinfo3.c:58) + by 0x........: main (varinfo3.c:66) + Location 0x........ is 0 bytes inside nonstatic_local_undef[8], + declared at varinfo3.c:53, in frame #2 of thread 1 + diff --git a/memcheck/tests/varinfo4.stderr.exp-ppc64 b/memcheck/tests/varinfo4.stderr.exp-ppc64 new file mode 100644 index 0000000..a47db5f --- /dev/null +++ b/memcheck/tests/varinfo4.stderr.exp-ppc64 @@ -0,0 +1,21 @@ +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo4.c:29) + by 0x........: blah (varinfo4.c:47) + by 0x........: main (varinfo4.c:56) + Location 0x........ is 1 byte inside a[3].xyzzy[21].c1, + declared at varinfo4.c:45, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo4.c:29) + by 0x........: blah (varinfo4.c:48) + by 0x........: main (varinfo4.c:56) + Location 0x........ is 0 bytes inside a[5].bong, + declared at varinfo4.c:45, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo4.c:29) + by 0x........: blah (varinfo4.c:49) + by 0x........: main (varinfo4.c:56) + Location 0x........ is 1 byte inside a[3].xyzzy[21].c2[2], + declared at varinfo4.c:45, in frame #1 of thread 1 + diff --git a/memcheck/tests/varinfo5.stderr.exp-ppc64 b/memcheck/tests/varinfo5.stderr.exp-ppc64 new file mode 100644 index 0000000..db0c4fd --- /dev/null +++ b/memcheck/tests/varinfo5.stderr.exp-ppc64 @@ -0,0 +1,180 @@ +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: varinfo1_main (varinfo5so.c:52) + by 0x........: varinfo5_main (varinfo5so.c:154) + by 0x........: main (varinfo5.c:5) + Address 0x........ is 1 bytes inside a block of size 3 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: varinfo1_main (varinfo5so.c:50) + by 0x........: varinfo5_main (varinfo5so.c:154) + by 0x........: main (varinfo5.c:5) + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: varinfo1_main (varinfo5so.c:55) + by 0x........: varinfo5_main (varinfo5so.c:154) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside global var "global_u1" + declared at varinfo5so.c:38 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: varinfo1_main (varinfo5so.c:56) + by 0x........: varinfo5_main (varinfo5so.c:154) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside global var "global_i1" + declared at varinfo5so.c:40 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: varinfo1_main (varinfo5so.c:57) + by 0x........: varinfo5_main (varinfo5so.c:154) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside global_u2[3], + a global variable declared at varinfo5so.c:42 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: varinfo1_main (varinfo5so.c:58) + by 0x........: varinfo5_main (varinfo5so.c:154) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside global_i2[7], + a global variable declared at varinfo5so.c:44 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: varinfo1_main (varinfo5so.c:59) + by 0x........: varinfo5_main (varinfo5so.c:154) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside local var "local" + declared at varinfo5so.c:49, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: foo2 (varinfo5so.c:71) + by 0x........: varinfo2_main (varinfo5so.c:81) + by 0x........: varinfo5_main (varinfo5so.c:155) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside var[7], + declared at varinfo5so.c:69, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: foo2 (varinfo5so.c:73) + by 0x........: varinfo2_main (varinfo5so.c:81) + by 0x........: varinfo5_main (varinfo5so.c:155) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 2 bytes inside var.bar, + declared at varinfo5so.c:72, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: foo2 (varinfo5so.c:76) + by 0x........: varinfo2_main (varinfo5so.c:81) + by 0x........: varinfo5_main (varinfo5so.c:155) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 1 byte inside local var "var" + declared at varinfo5so.c:67, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: foo3 (varinfo5so.c:106) + by 0x........: varinfo3_main (varinfo5so.c:118) + by 0x........: varinfo5_main (varinfo5so.c:156) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside static_global_def[1], + declared at varinfo5so.c:87, in frame #0 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: foo3 (varinfo5so.c:107) + by 0x........: varinfo3_main (varinfo5so.c:118) + by 0x........: varinfo5_main (varinfo5so.c:156) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside nonstatic_global_def[2], + a global variable declared at varinfo5so.c:88 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: foo3 (varinfo5so.c:108) + by 0x........: varinfo3_main (varinfo5so.c:118) + by 0x........: varinfo5_main (varinfo5so.c:156) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside static_global_undef[3], + declared at varinfo5so.c:89, in frame #0 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: foo3 (varinfo5so.c:109) + by 0x........: varinfo3_main (varinfo5so.c:118) + by 0x........: varinfo5_main (varinfo5so.c:156) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside nonstatic_global_undef[4], + a global variable declared at varinfo5so.c:90 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: bar3 (varinfo5so.c:94) + by 0x........: foo3 (varinfo5so.c:110) + by 0x........: varinfo3_main (varinfo5so.c:118) + by 0x........: varinfo5_main (varinfo5so.c:156) + by 0x........: main (varinfo5.c:5) + Address 0x........ is 5 bytes inside data symbol "static_local_def.XXXX" + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: bar3 (varinfo5so.c:95) + by 0x........: foo3 (varinfo5so.c:110) + by 0x........: varinfo3_main (varinfo5so.c:118) + by 0x........: varinfo5_main (varinfo5so.c:156) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside nonstatic_local_def[6], + declared at varinfo5so.c:103, in frame #2 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: bar3 (varinfo5so.c:96) + by 0x........: foo3 (varinfo5so.c:110) + by 0x........: varinfo3_main (varinfo5so.c:118) + by 0x........: varinfo5_main (varinfo5so.c:156) + by 0x........: main (varinfo5.c:5) + Address 0x........ is 7 bytes inside data symbol "static_local_undef.XXXX" + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: bar3 (varinfo5so.c:97) + by 0x........: foo3 (varinfo5so.c:110) + by 0x........: varinfo3_main (varinfo5so.c:118) + by 0x........: varinfo5_main (varinfo5so.c:156) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside nonstatic_local_undef[8], + declared at varinfo5so.c:105, in frame #2 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: blah4 (varinfo5so.c:137) + by 0x........: varinfo4_main (varinfo5so.c:146) + by 0x........: varinfo5_main (varinfo5so.c:157) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 1 byte inside a[3].xyzzy[21].c1, + declared at varinfo5so.c:135, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: blah4 (varinfo5so.c:138) + by 0x........: varinfo4_main (varinfo5so.c:146) + by 0x........: varinfo5_main (varinfo5so.c:157) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 0 bytes inside a[5].bong, + declared at varinfo5so.c:135, in frame #1 of thread 1 + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo5so.c:30) + by 0x........: blah4 (varinfo5so.c:139) + by 0x........: varinfo4_main (varinfo5so.c:146) + by 0x........: varinfo5_main (varinfo5so.c:157) + by 0x........: main (varinfo5.c:5) + Location 0x........ is 1 byte inside a[3].xyzzy[21].c2[2], + declared at varinfo5so.c:135, in frame #1 of thread 1 + +answer is 0 diff --git a/memcheck/tests/varinfo6.stderr.exp-ppc64 b/memcheck/tests/varinfo6.stderr.exp-ppc64 new file mode 100644 index 0000000..f574c73 --- /dev/null +++ b/memcheck/tests/varinfo6.stderr.exp-ppc64 @@ -0,0 +1,20 @@ +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo6.c:35) + by 0x........: mainSort (varinfo6.c:2999) + by 0x........: BZ2_blockSort (varinfo6.c:3143) + by 0x........: BZ2_compressBlock (varinfo6.c:4072) + by 0x........: handle_compress (varinfo6.c:4790) + by 0x........: BZ2_bzCompress (varinfo6.c:4860) + by 0x........: BZ2_bzBuffToBuffCompress (varinfo6.c:5667) + by 0x........: main (varinfo6.c:6517) + Address 0x........ is on thread 1's stack + +Uninitialised byte(s) found during client check request + at 0x........: croak (varinfo6.c:35) + by 0x........: BZ2_decompress (varinfo6.c:1699) + by 0x........: BZ2_bzDecompress (varinfo6.c:5230) + by 0x........: BZ2_bzBuffToBuffDecompress (varinfo6.c:5715) + by 0x........: main (varinfo6.c:6532) + Location 0x........ is 2 bytes inside local var "i" + declared at varinfo6.c:1517, in frame #1 of thread 1 + diff --git a/memcheck/tests/x86-linux/scalar.stderr.exp b/memcheck/tests/x86-linux/scalar.stderr.exp index 88150d4..a09a6d6 100644 --- a/memcheck/tests/x86-linux/scalar.stderr.exp +++ b/memcheck/tests/x86-linux/scalar.stderr.exp @@ -230,10 +230,6 @@ Syscall param mount(flags) contains uninitialised byte(s) Syscall param mount(data) contains uninitialised byte(s) ... -Syscall param mount(source) points to unaddressable byte(s) - ... - Address 0x........ is not stack'd, malloc'd or (recently) free'd - Syscall param mount(target) points to unaddressable byte(s) ... Address 0x........ is not stack'd, malloc'd or (recently) free'd @@ -505,9 +501,6 @@ Syscall param fcntl(arg) contains uninitialised byte(s) ----------------------------------------------------- 55: __NR_fcntl (GETLK) 1s 0m ----------------------------------------------------- - -More than 100 errors detected. Subsequent errors -will still be recorded, but in less detail than before. Syscall param fcntl(lock) contains uninitialised byte(s) ... @@ -517,6 +510,9 @@ Syscall param fcntl(lock) contains uninitialised byte(s) ----------------------------------------------------- 57: __NR_setpgid 2s 0m ----------------------------------------------------- + +More than 100 errors detected. Subsequent errors +will still be recorded, but in less detail than before. Syscall param setpgid(pid) contains uninitialised byte(s) ... @@ -1863,10 +1859,10 @@ Syscall param pread64(buf) contains uninitialised byte(s) Syscall param pread64(count) contains uninitialised byte(s) ... -Syscall param pread64(offset_low32) contains uninitialised byte(s) +Syscall param pread64(offset_low) contains uninitialised byte(s) ... -Syscall param pread64(offset_high32) contains uninitialised byte(s) +Syscall param pread64(offset_high) contains uninitialised byte(s) ... Syscall param pread64(buf) points to unaddressable byte(s) @@ -1885,10 +1881,10 @@ Syscall param pwrite64(buf) contains uninitialised byte(s) Syscall param pwrite64(count) contains uninitialised byte(s) ... -Syscall param pwrite64(offset_low32) contains uninitialised byte(s) +Syscall param pwrite64(offset_low) contains uninitialised byte(s) ... -Syscall param pwrite64(offset_high32) contains uninitialised byte(s) +Syscall param pwrite64(offset_high) contains uninitialised byte(s) ... Syscall param pwrite64(buf) points to unaddressable byte(s) @@ -2073,10 +2069,10 @@ Syscall param mmap2(offset) contains uninitialised byte(s) Syscall param truncate64(path) contains uninitialised byte(s) ... -Syscall param truncate64(length_low32) contains uninitialised byte(s) +Syscall param truncate64(length_low) contains uninitialised byte(s) ... -Syscall param truncate64(length_high32) contains uninitialised byte(s) +Syscall param truncate64(length_high) contains uninitialised byte(s) ... Syscall param truncate64(path) points to unaddressable byte(s) @@ -2089,10 +2085,10 @@ Syscall param truncate64(path) points to unaddressable byte(s) Syscall param ftruncate64(fd) contains uninitialised byte(s) ... -Syscall param ftruncate64(length_low32) contains uninitialised byte(s) +Syscall param ftruncate64(length_low) contains uninitialised byte(s) ... -Syscall param ftruncate64(length_high32) contains uninitialised byte(s) +Syscall param ftruncate64(length_high) contains uninitialised byte(s) ... ----------------------------------------------------- @@ -2874,10 +2870,10 @@ Syscall param io_cancel(result) points to unaddressable byte(s) ----------------------------------------------------- 253: __NR_lookup_dcookie 4s 1m ----------------------------------------------------- -Syscall param lookup_dcookie(cookie_low32) contains uninitialised byte(s) +Syscall param lookup_dcookie(cookie_low) contains uninitialised byte(s) ... -Syscall param lookup_dcookie(cookie_high32) contains uninitialised byte(s) +Syscall param lookup_dcookie(cookie_high) contains uninitialised byte(s) ... Syscall param lookup_dcookie(buf) contains uninitialised byte(s) diff --git a/mpi/libmpiwrap.c b/mpi/libmpiwrap.c index c0f41b8..0e307b3 100644 --- a/mpi/libmpiwrap.c +++ b/mpi/libmpiwrap.c @@ -18,7 +18,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright (C) 2006-2009 OpenWorks LLP. All rights reserved. + Copyright (C) 2006-2010 OpenWorks LLP. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions @@ -57,6 +57,32 @@ without prior written permission. */ +/* Handling of MPI_STATUS{ES}_IGNORE for MPI_Status* arguments. + + The MPI-2 spec allows many functions which have MPI_Status* purely + as an out parameter, to accept the constants MPI_STATUS_IGNORE or + MPI_STATUSES_IGNORE there instead, if the caller does not care + about the status. See the MPI-2 spec sec 4.5.1 ("Passing + MPI_STATUS_IGNORE for Status"). (mpi2-report.pdf, 1615898 bytes, + md5=694a5efe2fd291eecf7e8c9875b5f43f). + + This library handles such cases by allocating a fake MPI_Status + object (on the stack) or an array thereof (on the heap), and + passing that onwards instead. From the outside the caller sees no + difference. Unfortunately the simpler approach of merely detecting + and handling these special cases at a lower level does not work, + because we need to use information returned in MPI_Status* + arguments to paint result buffers, even if the caller doesn't + supply a real MPI_Status object. + + Eg, MPI_Recv. We can't paint the result buffer without knowing how + many items arrived; but we can't find that out without passing a + real MPI_Status object to the (real) MPI_Recv call. Hence, if the + caller did not supply one, we have no option but to use a temporary + stack allocated one for the inner call. Ditto, more indirectly + (via maybe_complete) for nonblocking receives and the various + associated wait/test calls. */ + /*------------------------------------------------------------*/ /*--- includes ---*/ @@ -103,6 +129,17 @@ #endif +/* Define HAVE_MPI_STATUS_IGNORE iff we have to deal with + MPI_STATUS{ES}_IGNORE. */ +#if MPI_VERSION >= 2 \ + || (defined(MPI_STATUS_IGNORE) && defined(MPI_STATUSES_IGNORE)) +# undef HAVE_MPI_STATUS_IGNORE +# define HAVE_MPI_STATUS_IGNORE 1 +#else +# undef HAVE_MPI_STATUS_IGNORE +#endif + + /*------------------------------------------------------------*/ /*--- Decls ---*/ /*------------------------------------------------------------*/ @@ -401,6 +438,20 @@ Bool eq_MPI_Request ( MPI_Request r1, MPI_Request r2 ) return r1 == r2; } +/* Return True if status is MPI_STATUS_IGNORE or MPI_STATUSES_IGNORE. + On MPI-1.x platforms which don't have these symbols (and they would + only have them if they've been backported from 2.x) always return + False. */ +static __inline__ +Bool isMSI ( MPI_Status* status ) +{ +# if defined(HAVE_MPI_STATUS_IGNORE) + return status == MPI_STATUSES_IGNORE || status == MPI_STATUS_IGNORE; +# else + return False; +# endif +} + /* Get the 'extent' of a type. Note, as per the MPI spec this includes whatever padding would be required when using 'ty' in an array. */ @@ -1045,10 +1096,13 @@ int WRAPPER_FOR(PMPI_Recv)(void *buf, int count, MPI_Datatype datatype, int source, int tag, MPI_Comm comm, MPI_Status *status) { - OrigFn fn; - int err, recv_count = 0; + OrigFn fn; + int err, recv_count = 0; + MPI_Status fake_status; VALGRIND_GET_ORIG_FN(fn); before("Recv"); + if (isMSI(status)) + status = &fake_status; check_mem_is_addressable(buf, count, datatype); check_mem_is_addressable_untyped(status, sizeof(*status)); CALL_FN_W_7W(err, fn, buf,count,datatype,source,tag,comm,status); @@ -1386,10 +1440,13 @@ int WRAPPER_FOR(PMPI_Wait)( MPI_Request* request, MPI_Status* status ) { MPI_Request request_before; + MPI_Status fake_status; OrigFn fn; int err; VALGRIND_GET_ORIG_FN(fn); before("Wait"); + if (isMSI(status)) + status = &fake_status; check_mem_is_addressable_untyped(status, sizeof(MPI_Status)); check_mem_is_defined_untyped(request, sizeof(MPI_Request)); request_before = *request; @@ -1410,10 +1467,13 @@ int WRAPPER_FOR(PMPI_Waitany)( int count, MPI_Status* status ) { MPI_Request* requests_before = NULL; + MPI_Status fake_status; OrigFn fn; int err, i; VALGRIND_GET_ORIG_FN(fn); before("Waitany"); + if (isMSI(status)) + status = &fake_status; if (0) fprintf(stderr, "Waitany: %d\n", count); check_mem_is_addressable_untyped(index, sizeof(int)); check_mem_is_addressable_untyped(status, sizeof(MPI_Status)); @@ -1441,9 +1501,14 @@ int WRAPPER_FOR(PMPI_Waitall)( int count, MPI_Request* requests_before = NULL; OrigFn fn; int err, i; + Bool free_sta = False; VALGRIND_GET_ORIG_FN(fn); before("Waitall"); if (0) fprintf(stderr, "Waitall: %d\n", count); + if (isMSI(statuses)) { + free_sta = True; + statuses = malloc( (count < 0 ? 0 : count) * sizeof(MPI_Status) ); + } for (i = 0; i < count; i++) { check_mem_is_addressable_untyped(&statuses[i], sizeof(MPI_Status)); check_mem_is_defined_untyped(&requests[i], sizeof(MPI_Request)); @@ -1462,6 +1527,8 @@ int WRAPPER_FOR(PMPI_Waitall)( int count, } if (requests_before) free(requests_before); + if (free_sta) + free(statuses); after("Waitall", err); return err; } @@ -1472,10 +1539,13 @@ int WRAPPER_FOR(PMPI_Test)( MPI_Request* request, int* flag, MPI_Status* status ) { MPI_Request request_before; + MPI_Status fake_status; OrigFn fn; int err; VALGRIND_GET_ORIG_FN(fn); before("Test"); + if (isMSI(status)) + status = &fake_status; check_mem_is_addressable_untyped(status, sizeof(MPI_Status)); check_mem_is_addressable_untyped(flag, sizeof(int)); check_mem_is_defined_untyped(request, sizeof(MPI_Request)); @@ -1498,9 +1568,14 @@ int WRAPPER_FOR(PMPI_Testall)( int count, MPI_Request* requests, MPI_Request* requests_before = NULL; OrigFn fn; int err, i; + Bool free_sta = False; VALGRIND_GET_ORIG_FN(fn); before("Testall"); if (0) fprintf(stderr, "Testall: %d\n", count); + if (isMSI(statuses)) { + free_sta = True; + statuses = malloc( (count < 0 ? 0 : count) * sizeof(MPI_Status) ); + } check_mem_is_addressable_untyped(flag, sizeof(int)); for (i = 0; i < count; i++) { check_mem_is_addressable_untyped(&statuses[i], sizeof(MPI_Status)); @@ -1516,11 +1591,14 @@ int WRAPPER_FOR(PMPI_Testall)( int count, MPI_Request* requests, for (i = 0; i < count; i++) { maybe_complete(e_i_s, requests_before[i], requests[i], &statuses[i]); - make_mem_defined_if_addressable_untyped(&statuses[i], sizeof(MPI_Status)); + make_mem_defined_if_addressable_untyped(&statuses[i], + sizeof(MPI_Status)); } } if (requests_before) free(requests_before); + if (free_sta) + free(statuses); after("Testall", err); return err; } @@ -1533,10 +1611,13 @@ int WRAPPER_FOR(PMPI_Iprobe)(int source, int tag, MPI_Comm comm, int* flag, MPI_Status* status) { - OrigFn fn; - int err; + MPI_Status fake_status; + OrigFn fn; + int err; VALGRIND_GET_ORIG_FN(fn); before("Iprobe"); + if (isMSI(status)) + status = &fake_status; check_mem_is_addressable_untyped(flag, sizeof(*flag)); check_mem_is_addressable_untyped(status, sizeof(*status)); CALL_FN_W_5W(err, fn, source,tag,comm,flag,status); @@ -1555,10 +1636,13 @@ int WRAPPER_FOR(PMPI_Iprobe)(int source, int tag, int WRAPPER_FOR(PMPI_Probe)(int source, int tag, MPI_Comm comm, MPI_Status* status) { - OrigFn fn; - int err; + MPI_Status fake_status; + OrigFn fn; + int err; VALGRIND_GET_ORIG_FN(fn); before("Probe"); + if (isMSI(status)) + status = &fake_status; check_mem_is_addressable_untyped(status, sizeof(*status)); CALL_FN_W_WWWW(err, fn, source,tag,comm,status); make_mem_defined_if_addressable_if_success_untyped(err, status, sizeof(*status)); @@ -1606,12 +1690,16 @@ int WRAPPER_FOR(PMPI_Sendrecv)( int source, int recvtag, MPI_Comm comm, MPI_Status *status) { - OrigFn fn; - int err, recvcount_actual = 0; + MPI_Status fake_status; + OrigFn fn; + int err, recvcount_actual = 0; VALGRIND_GET_ORIG_FN(fn); before("Sendrecv"); + if (isMSI(status)) + status = &fake_status; check_mem_is_defined(sendbuf, sendcount, sendtype); check_mem_is_addressable(recvbuf, recvcount, recvtype); + check_mem_is_addressable_untyped(status, sizeof(*status)); CALL_FN_W_12W(err, fn, sendbuf,sendcount,sendtype,dest,sendtag, recvbuf,recvcount,recvtype,source,recvtag, comm,status); diff --git a/nightly/conf/georgia-tech-cellbuzz-cross.conf b/nightly/conf/cellbuzz-cross.conf similarity index 100% rename from nightly/conf/georgia-tech-cellbuzz-cross.conf rename to nightly/conf/cellbuzz-cross.conf diff --git a/nightly/conf/georgia-tech-cellbuzz-cross.sendmail b/nightly/conf/cellbuzz-cross.sendmail old mode 100644 new mode 100755 similarity index 83% rename from nightly/conf/georgia-tech-cellbuzz-cross.sendmail rename to nightly/conf/cellbuzz-cross.sendmail index 3720e0e..ec079a5 --- a/nightly/conf/georgia-tech-cellbuzz-cross.sendmail +++ b/nightly/conf/cellbuzz-cross.sendmail @@ -3,9 +3,9 @@ # use: georgia-tech-cellbuzz.sendmail subject file-to-mail [file-to-attach] # Don't forget to set the variables 'from' and 'realname' in ~/.muttrc ! -sender="bart.vanassche@gmail.com" +sender="bvanassche@acm.org" recipients="valgrind-developers@lists.sourceforge.net" -#recipients="bart.vanassche@gmail.com" +#recipients="bvanassche@acm.org" if [ $# -ge 3 ]; then gzip -9 <"$3" >"$3.gz" mutt -s "$1" -a "$3.gz" ${recipients} < "$2" diff --git a/nightly/conf/georgia-tech-cellbuzz-native.conf b/nightly/conf/cellbuzz-native.conf similarity index 95% rename from nightly/conf/georgia-tech-cellbuzz-native.conf rename to nightly/conf/cellbuzz-native.conf index 7aff560..8b219da 100644 --- a/nightly/conf/georgia-tech-cellbuzz-native.conf +++ b/nightly/conf/cellbuzz-native.conf @@ -13,12 +13,12 @@ ABT_JOBS=2 cellbuzz_eval() { rm -f cmd-output.txt done - jobid=`echo "{ cd $PWD && eval \"$*\"; } >& $PWD/cmd-output.txt" \ - | qsub -m n -q sdk3.0` + jobid=`echo "{ cd $PWD && eval \"$*\"; } >& $PWD/cmd-output.txt" | qsub -m n` echo "Job ID = ${jobid}" while [ `qstat "${jobid}" 2>/dev/null | wc --lines` -gt 0 ] do sleep 10 done cat cmd-output.txt + rm -f STDIN.* } diff --git a/nightly/conf/georgia-tech-cellbuzz-native.sendmail b/nightly/conf/cellbuzz-native.sendmail old mode 100644 new mode 100755 similarity index 83% rename from nightly/conf/georgia-tech-cellbuzz-native.sendmail rename to nightly/conf/cellbuzz-native.sendmail index 3720e0e..ec079a5 --- a/nightly/conf/georgia-tech-cellbuzz-native.sendmail +++ b/nightly/conf/cellbuzz-native.sendmail @@ -3,9 +3,9 @@ # use: georgia-tech-cellbuzz.sendmail subject file-to-mail [file-to-attach] # Don't forget to set the variables 'from' and 'realname' in ~/.muttrc ! -sender="bart.vanassche@gmail.com" +sender="bvanassche@acm.org" recipients="valgrind-developers@lists.sourceforge.net" -#recipients="bart.vanassche@gmail.com" +#recipients="bvanassche@acm.org" if [ $# -ge 3 ]; then gzip -9 <"$3" >"$3.gz" mutt -s "$1" -a "$3.gz" ${recipients} < "$2" diff --git a/none/Makefile.am b/none/Makefile.am index a1affd3..753687e 100644 --- a/none/Makefile.am +++ b/none/Makefile.am @@ -13,7 +13,8 @@ endif NONE_SOURCES_COMMON = nl_main.c -none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(NONE_SOURCES_COMMON) +none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \ + $(NONE_SOURCES_COMMON) none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \ @@ -24,8 +25,16 @@ none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@) none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) +none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_PRI@ \ + $(LINK) \ + $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \ + $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) + if VGCONF_HAVE_PLATFORM_SEC -none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(NONE_SOURCES_COMMON) +none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \ + $(NONE_SOURCES_COMMON) none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \ @@ -36,6 +45,12 @@ none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@) none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) +none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \ + $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \ + @VALT_LOAD_ADDRESS_SEC@ \ + $(LINK) \ + $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \ + $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) endif diff --git a/none/nl_main.c b/none/nl_main.c index cb029bb..ab6c6e8 100644 --- a/none/nl_main.c +++ b/none/nl_main.c @@ -7,7 +7,7 @@ This file is part of Nulgrind, the minimal Valgrind tool, which does no instrumentation or analysis. - Copyright (C) 2002-2009 Nicholas Nethercote + Copyright (C) 2002-2010 Nicholas Nethercote njn@valgrind.org This program is free software; you can redistribute it and/or @@ -55,7 +55,7 @@ static void nl_pre_clo_init(void) VG_(details_version) (NULL); VG_(details_description) ("the minimal Valgrind tool"); VG_(details_copyright_author)( - "Copyright (C) 2002-2009, and GNU GPL'd, by Nicholas Nethercote."); + "Copyright (C) 2002-2010, and GNU GPL'd, by Nicholas Nethercote."); VG_(details_bug_reports_to) (VG_BUGS_TO); VG_(basic_tool_funcs) (nl_post_clo_init, diff --git a/none/tests/Makefile.am b/none/tests/Makefile.am index b281071..8bcd67e 100644 --- a/none/tests/Makefile.am +++ b/none/tests/Makefile.am @@ -16,6 +16,9 @@ endif if VGCONF_ARCHS_INCLUDE_PPC64 SUBDIRS += ppc64 endif +if VGCONF_ARCHS_INCLUDE_ARM +SUBDIRS += arm +endif # OS-specific tests if VGCONF_OS_IS_LINUX @@ -30,7 +33,7 @@ if VGCONF_PLATFORMS_INCLUDE_X86_LINUX SUBDIRS += x86-linux endif -DIST_SUBDIRS = x86 amd64 ppc32 ppc64 linux darwin x86-linux . +DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm linux darwin x86-linux . dist_noinst_SCRIPTS = \ filter_cmdline0 \ @@ -88,6 +91,10 @@ EXTRA_DIST = \ munmap_exe.stderr.exp munmap_exe.vgtest \ nestedfns.stderr.exp nestedfns.stdout.exp nestedfns.vgtest \ pending.stdout.exp pending.stderr.exp pending.vgtest \ + procfs-linux.stderr.exp-with-readlinkat \ + procfs-linux.stderr.exp-without-readlinkat \ + procfs-linux.vgtest \ + procfs-non-linux.stderr.exp procfs-non-linux.vgtest \ pth_atfork1.stderr.exp pth_atfork1.stdout.exp pth_atfork1.vgtest \ pth_blockedsig.stderr.exp \ pth_blockedsig.stdout.exp pth_blockedsig.vgtest \ @@ -106,6 +113,10 @@ EXTRA_DIST = \ rcrl.stderr.exp rcrl.stdout.exp rcrl.vgtest \ readline1.stderr.exp readline1.stdout.exp \ readline1.vgtest \ + require-text-symbol-1.vgtest \ + require-text-symbol-1.stderr.exp \ + require-text-symbol-2.vgtest \ + require-text-symbol-2.stderr.exp-libcso6 \ res_search.stderr.exp res_search.stdout.exp res_search.vgtest \ resolv.stderr.exp resolv.stdout.exp resolv.vgtest \ rlimit_nofile.stderr.exp rlimit_nofile.stdout.exp rlimit_nofile.vgtest \ @@ -155,10 +166,13 @@ check_PROGRAMS = \ munmap_exe map_unaligned map_unmap mq \ nestedfns \ pending \ + procfs-cmdline-exe \ pth_atfork1 pth_blockedsig pth_cancel1 pth_cancel2 pth_cvsimple \ pth_empty pth_exit pth_exit2 pth_mutexspeed pth_once pth_rwlock \ pth_stackalign \ - rcrl readline1 res_search resolv \ + rcrl readline1 \ + require-text-symbol \ + res_search resolv \ rlimit_nofile selfrun sem semlimit sha1_test \ shortpush shorts stackgrowth sigstackgrowth \ syscall-restart1 syscall-restart2 \ @@ -170,6 +184,7 @@ check_PROGRAMS = \ tls \ tls.so \ tls2.so \ + valgrind_cpp_test \ vgprintf \ coolo_sigaction \ gxx304 @@ -232,13 +247,13 @@ thread_exits_LDADD = -lpthread threaded_fork_LDADD = -lpthread threadederrno_LDADD = -lpthread tls_SOURCES = tls.c tls2.c -tls_DEPENDENCIES = tls.so +tls_DEPENDENCIES = tls.so tls2.so if VGCONF_OS_IS_AIX5 tls_LDFLAGS = else tls_LDFLAGS = -Wl,-rpath,$(top_builddir)/none/tests endif -tls_LDADD = tls.so -lpthread +tls_LDADD = tls.so tls2.so -lpthread tls_so_SOURCES = tls_so.c tls_so_DEPENDENCIES = tls2.so if VGCONF_OS_IS_AIX5 @@ -261,6 +276,9 @@ else tls2_so_LDFLAGS = -shared endif +valgrind_cpp_test_SOURCES = valgrind_cpp_test.cpp +valgrind_cpp_test_LDADD = -lstdc++ + # C++ tests coolo_sigaction_SOURCES = coolo_sigaction.cpp gxx304_SOURCES = gxx304.cpp diff --git a/none/tests/amd64/Makefile.am b/none/tests/amd64/Makefile.am index 51ec345..4c61832 100644 --- a/none/tests/amd64/Makefile.am +++ b/none/tests/amd64/Makefile.am @@ -12,10 +12,16 @@ endif if BUILD_SSSE3_TESTS INSN_TESTS += insn_ssse3 endif +if BUILD_PCLMULQDQ_TESTS +INSN_TESTS += insn_pclmulqdq +endif # Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS, # to avoid packaging screwups if 'make dist' is run on a machine # which failed the BUILD_SSE3_TESTS test in configure.in. + +## FIXME: move lzcnt64 to SSE4 conditionalisation, when that happens. + EXTRA_DIST = \ amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \ bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \ @@ -27,6 +33,7 @@ EXTRA_DIST = \ bug156404-amd64.vgtest bug156404-amd64.stdout.exp \ bug156404-amd64.stderr.exp \ clc.vgtest clc.stdout.exp clc.stderr.exp \ + cmpxchg.vgtest cmpxchg.stdout.exp cmpxchg.stderr.exp \ faultstatus.disabled faultstatus.stderr.exp \ fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \ fxtract.vgtest fxtract.stderr.exp fxtract.stdout.exp \ @@ -37,31 +44,40 @@ EXTRA_DIST = \ insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \ jrcxz.stderr.exp jrcxz.stdout.exp jrcxz.vgtest \ looper.stderr.exp looper.stdout.exp looper.vgtest \ + lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \ nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \ nibz_bennee_mmap.vgtest \ rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \ redundantRexW.vgtest redundantRexW.stdout.exp \ redundantRexW.stderr.exp \ smc1.stderr.exp smc1.stdout.exp smc1.vgtest \ + sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \ shrld.stderr.exp shrld.stdout.exp shrld.vgtest \ ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \ ssse3_misaligned.vgtest \ ssse3_misaligned.c \ slahf-amd64.stderr.exp slahf-amd64.stdout.exp \ - slahf-amd64.vgtest + slahf-amd64.vgtest \ + xadd.stderr.exp xadd.stdout.exp xadd.vgtest check_PROGRAMS = \ amd64locked \ bug127521-64 bug132813-amd64 bug132918 \ clc \ + cmpxchg \ $(INSN_TESTS) \ rcl-amd64 \ redundantRexW \ smc1 \ - nibz_bennee_mmap + sbbmisc \ + nibz_bennee_mmap \ + xadd if BUILD_SSSE3_TESTS check_PROGRAMS += ssse3_misaligned endif +if BUILD_LZCNT_TESTS + check_PROGRAMS += lzcnt64 +endif # DDD: these need to be made to work on Darwin like the x86/ ones were. if ! VGCONF_OS_IS_DARWIN diff --git a/none/tests/amd64/bug132918.stdout.exp b/none/tests/amd64/bug132918.stdout.exp index 9427c84..f12f46d 100644 --- a/none/tests/amd64/bug132918.stdout.exp +++ b/none/tests/amd64/bug132918.stdout.exp @@ -1,6 +1,6 @@ xx1 -> 0x4200 8.300000 xx2 -> 0x0000 1.440000 -xx -> 0x0000 nan +xx -> 0x0000 -nan xx -> 0x0000 0.809017 xx -> 0x0000 0.309018 xx -> 0x0000 -0.309015 diff --git a/none/tests/amd64/cmpxchg.c b/none/tests/amd64/cmpxchg.c new file mode 100644 index 0000000..62f1462 --- /dev/null +++ b/none/tests/amd64/cmpxchg.c @@ -0,0 +1,273 @@ +#include "tests/asm.h" +#include + +/* This test only checks register/register cmpxchg */ + +typedef unsigned long long int ULong; +typedef unsigned int UInt; + +ULong m64; + +ULong rax; +ULong rbx; +ULong rcx; +ULong rdx; +ULong rax_out; +ULong rbx_out; +ULong rcx_out; + +int main ( void ) +{ + + /* 8-bit */ + + rdx = 0x11111111; rax = 0x22222222; + rcx = 0x33333333; rbx = 0x44444444; + + printf("cmpxchg %%bl,%%cl (al=%llx bl=%llx cl=%llx)\n", + rax&0xff,rbx&0xff,rcx&0xff); + + asm("\n" + "\tpush %rax\n" + "\tpush %rbx\n" + "\tpush %rcx\n" + "\tpush %rdx\n" + "\txor %rax, %rax\n" // get eflags in a known state + "\tmov " VG_SYM(rax) ",%rax\n" + "\tmov " VG_SYM(rbx) ",%rbx\n" + "\tmov " VG_SYM(rcx) ",%rcx\n" + "\tmov " VG_SYM(rdx) ",%rdx\n" + "\tcmpxchg %bl,%cl \n" + "\tmov %rax," VG_SYM(rax_out) "\n" + "\tmov %rbx," VG_SYM(rbx_out) "\n" + "\tmov %rcx," VG_SYM(rcx_out) "\n" + "\tpop %rdx\n" + "\tpop %rcx\n" + "\tpop %rbx\n" + "\tpop %rax\n" + ); + + printf(" al!=cl so al should equal cl (Result al=%llx bl=%llx cl=%llx)\n", + rax_out&0xff,rbx_out&0xff,rcx_out&0xff); + + + + rdx = 0x99999999; rax = 0x77777777; + rcx = 0x55555555; rbx = 0x55555555; + + printf("cmpxchg %%bl,%%cl (al=%llx bl=%llx cl=%llx)\n", + rax&0xff,rbx&0xff,rcx&0xff); + + asm("\n" + "\tpush %rax\n" + "\tpush %rbx\n" + "\tpush %rcx\n" + "\tpush %rdx\n" + "\txor %rax, %rax\n" // get eflags in a known state + "\tmov " VG_SYM(rax) ",%rax\n" + "\tmov " VG_SYM(rbx) ",%rbx\n" + "\tmov " VG_SYM(rcx) ",%rcx\n" + "\tmov " VG_SYM(rdx) ",%rdx\n" + "\tcmpxchg %bl,%cl \n" + "\tmov %rax," VG_SYM(rax_out) "\n" + "\tmov %rbx," VG_SYM(rbx_out) "\n" + "\tmov %rcx," VG_SYM(rcx_out) "\n" + "\tpop %rdx\n" + "\tpop %rcx\n" + "\tpop %rbx\n" + "\tpop %rax\n" + ); + + printf(" al==cl so cl should equal bl (Result al=%llx bl=%llx cl=%llx)\n", + rax_out&0xff,rbx_out&0xff,rcx_out&0xff); + + /* 16-bit */ + + rdx = 0x11111111; rax = 0x22222222; + rcx = 0x33333333; rbx = 0x44444444; + + printf("cmpxchg %%bx,%%cx (ax=%llx bx=%llx cx=%llx)\n", + rax&0xffff,rbx&0xffff,rcx&0xffff); + + asm("\n" + "\tpush %rax\n" + "\tpush %rbx\n" + "\tpush %rcx\n" + "\tpush %rdx\n" + "\txor %rax, %rax\n" // get eflags in a known state + "\tmov " VG_SYM(rax) ",%rax\n" + "\tmov " VG_SYM(rbx) ",%rbx\n" + "\tmov " VG_SYM(rcx) ",%rcx\n" + "\tmov " VG_SYM(rdx) ",%rdx\n" + "\tcmpxchg %bx,%cx \n" + "\tmov %rax," VG_SYM(rax_out) "\n" + "\tmov %rbx," VG_SYM(rbx_out) "\n" + "\tmov %rcx," VG_SYM(rcx_out) "\n" + "\tpop %rdx\n" + "\tpop %rcx\n" + "\tpop %rbx\n" + "\tpop %rax\n" + ); + + printf(" ax!=cx so ax should equal cx (Result ax=%llx bx=%llx cx=%llx)\n", + rax_out&0xffff,rbx_out&0xffff,rcx_out&0xffff); + + + + rdx = 0x99999999; rax = 0x77777777; + rcx = 0x55555555; rbx = 0x55555555; + + printf("cmpxchg %%bx,%%cx (ax=%llx bx=%llx cx=%llx)\n", + rax&0xffff,rbx&0xffff,rcx&0xffff); + + asm("\n" + "\tpush %rax\n" + "\tpush %rbx\n" + "\tpush %rcx\n" + "\tpush %rdx\n" + "\txor %rax, %rax\n" // get eflags in a known state + "\tmov " VG_SYM(rax) ",%rax\n" + "\tmov " VG_SYM(rbx) ",%rbx\n" + "\tmov " VG_SYM(rcx) ",%rcx\n" + "\tmov " VG_SYM(rdx) ",%rdx\n" + "\tcmpxchg %bx,%cx \n" + "\tmov %rax," VG_SYM(rax_out) "\n" + "\tmov %rbx," VG_SYM(rbx_out) "\n" + "\tmov %rcx," VG_SYM(rcx_out) "\n" + "\tpop %rdx\n" + "\tpop %rcx\n" + "\tpop %rbx\n" + "\tpop %rax\n" + ); + + printf(" ax==cx so cx should equal bx (Result ax=%llx bx=%llx cx=%llx)\n", + rax_out&0xffff,rbx_out&0xffff,rcx_out&0xffff); + + + /* 32-bit */ + + rdx = 0x11111111; rax = 0x22222222; + rcx = 0x33333333; rbx = 0x44444444; + + printf("cmpxchg %%ebx,%%ecx (eax=%llx ebx=%llx ecx=%llx)\n", + rax&0xffffffff,rbx&0xffffffff,rcx&0xffffffff); + + asm("\n" + "\tpush %rax\n" + "\tpush %rbx\n" + "\tpush %rcx\n" + "\tpush %rdx\n" + "\txor %rax, %rax\n" // get eflags in a known state + "\tmov " VG_SYM(rax) ",%rax\n" + "\tmov " VG_SYM(rbx) ",%rbx\n" + "\tmov " VG_SYM(rcx) ",%rcx\n" + "\tmov " VG_SYM(rdx) ",%rdx\n" + "\tcmpxchg %ebx,%ecx \n" + "\tmov %rax," VG_SYM(rax_out) "\n" + "\tmov %rbx," VG_SYM(rbx_out) "\n" + "\tmov %rcx," VG_SYM(rcx_out) "\n" + "\tpop %rdx\n" + "\tpop %rcx\n" + "\tpop %rbx\n" + "\tpop %rax\n" + ); + + printf(" eax!=ecx so eax should equal ecx (Result eax=%llx ebx=%llx ecx=%llx)\n", + rax_out&0xffffffff,rbx_out&0xffffffff,rcx_out&0xffffffff); + + + + rdx = 0x99999999; rax = 0x77777777; + rcx = 0x55555555; rbx = 0x55555555; + + printf("cmpxchg %%ebx,%%ecx (eax=%llx ebx=%llx ecx=%llx)\n", + rax&0xffffffff,rbx&0xffffffff,rcx&0xffffffff); + + asm("\n" + "\tpush %rax\n" + "\tpush %rbx\n" + "\tpush %rcx\n" + "\tpush %rdx\n" + "\txor %rax, %rax\n" // get eflags in a known state + "\tmov " VG_SYM(rax) ",%rax\n" + "\tmov " VG_SYM(rbx) ",%rbx\n" + "\tmov " VG_SYM(rcx) ",%rcx\n" + "\tmov " VG_SYM(rdx) ",%rdx\n" + "\tcmpxchg %ebx,%ecx \n" + "\tmov %rax," VG_SYM(rax_out) "\n" + "\tmov %rbx," VG_SYM(rbx_out) "\n" + "\tmov %rcx," VG_SYM(rcx_out) "\n" + "\tpop %rdx\n" + "\tpop %rcx\n" + "\tpop %rbx\n" + "\tpop %rax\n" + ); + + printf(" eax==ecx so ecx should equal ebx (Result eax=%llx ebx=%llx ecx=%llx)\n", + rax_out&0xffffffff,rbx_out&0xffffffff,rcx_out&0xffffffff); + + + /* 64-bit */ + + rdx = 0x111111111; rax = 0x222222222; + rcx = 0x333333333; rbx = 0x444444444; + + printf("cmpxchg %%rbx,%%rcx (rax=%llx rbx=%llx rcx=%llx)\n", + rax,rbx,rcx); + + asm("\n" + "\tpush %rax\n" + "\tpush %rbx\n" + "\tpush %rcx\n" + "\tpush %rdx\n" + "\txor %rax, %rax\n" // get eflags in a known state + "\tmov " VG_SYM(rax) ",%rax\n" + "\tmov " VG_SYM(rbx) ",%rbx\n" + "\tmov " VG_SYM(rcx) ",%rcx\n" + "\tmov " VG_SYM(rdx) ",%rdx\n" + "\tcmpxchg %rbx,%rcx \n" + "\tmov %rax," VG_SYM(rax_out) "\n" + "\tmov %rbx," VG_SYM(rbx_out) "\n" + "\tmov %rcx," VG_SYM(rcx_out) "\n" + "\tpop %rdx\n" + "\tpop %rcx\n" + "\tpop %rbx\n" + "\tpop %rax\n" + ); + + printf(" rax!=rcx so rax should equal rcx (Result rax=%llx rbx=%llx rcx=%llx)\n", + rax_out,rbx_out,rcx_out); + + + + rdx = 0x999999999; rax = 0x777777777; + rcx = 0x555555555; rbx = 0x555555555; + + printf("cmpxchg %%rbx,%%rcx (rax=%llx rbx=%llx rcx=%llx)\n", + rax,rbx,rcx); + + asm("\n" + "\tpush %rax\n" + "\tpush %rbx\n" + "\tpush %rcx\n" + "\tpush %rdx\n" + "\txor %rax, %rax\n" // get eflags in a known state + "\tmov " VG_SYM(rax) ",%rax\n" + "\tmov " VG_SYM(rbx) ",%rbx\n" + "\tmov " VG_SYM(rcx) ",%rcx\n" + "\tmov " VG_SYM(rdx) ",%rdx\n" + "\tcmpxchg %rbx,%rcx \n" + "\tmov %rax," VG_SYM(rax_out) "\n" + "\tmov %rbx," VG_SYM(rbx_out) "\n" + "\tmov %rcx," VG_SYM(rcx_out) "\n" + "\tpop %rdx\n" + "\tpop %rcx\n" + "\tpop %rbx\n" + "\tpop %rax\n" + ); + + printf(" rax==rcx so ecx should equal rbx (Result rax=%llx rbx=%llx rcx=%llx)\n", + rax_out,rbx_out,rcx_out); + + return 0; +} diff --git a/none/tests/amd64/cmpxchg.stderr.exp b/none/tests/amd64/cmpxchg.stderr.exp new file mode 100644 index 0000000..139597f --- /dev/null +++ b/none/tests/amd64/cmpxchg.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/amd64/cmpxchg.stdout.exp b/none/tests/amd64/cmpxchg.stdout.exp new file mode 100644 index 0000000..75a54b4 --- /dev/null +++ b/none/tests/amd64/cmpxchg.stdout.exp @@ -0,0 +1,16 @@ +cmpxchg %bl,%cl (al=22 bl=44 cl=33) + al!=cl so al should equal cl (Result al=33 bl=44 cl=33) +cmpxchg %bl,%cl (al=77 bl=55 cl=55) + al==cl so cl should equal bl (Result al=55 bl=55 cl=55) +cmpxchg %bx,%cx (ax=2222 bx=4444 cx=3333) + ax!=cx so ax should equal cx (Result ax=3333 bx=4444 cx=3333) +cmpxchg %bx,%cx (ax=7777 bx=5555 cx=5555) + ax==cx so cx should equal bx (Result ax=5555 bx=5555 cx=5555) +cmpxchg %ebx,%ecx (eax=22222222 ebx=44444444 ecx=33333333) + eax!=ecx so eax should equal ecx (Result eax=33333333 ebx=44444444 ecx=33333333) +cmpxchg %ebx,%ecx (eax=77777777 ebx=55555555 ecx=55555555) + eax==ecx so ecx should equal ebx (Result eax=55555555 ebx=55555555 ecx=55555555) +cmpxchg %rbx,%rcx (rax=222222222 rbx=444444444 rcx=333333333) + rax!=rcx so rax should equal rcx (Result rax=333333333 rbx=444444444 rcx=333333333) +cmpxchg %rbx,%rcx (rax=777777777 rbx=555555555 rcx=555555555) + rax==rcx so ecx should equal rbx (Result rax=555555555 rbx=555555555 rcx=555555555) diff --git a/none/tests/amd64/cmpxchg.vgtest b/none/tests/amd64/cmpxchg.vgtest new file mode 100644 index 0000000..a6d32f3 --- /dev/null +++ b/none/tests/amd64/cmpxchg.vgtest @@ -0,0 +1 @@ +prog: cmpxchg diff --git a/none/tests/amd64/fxtract.stdout.exp b/none/tests/amd64/fxtract.stdout.exp index 4508fd6..b82f306 100644 --- a/none/tests/amd64/fxtract.stdout.exp +++ b/none/tests/amd64/fxtract.stdout.exp @@ -40,7 +40,7 @@ 2.7049662808e+02 -> 1.0566274534 8.0000000000 0.0000000000e+00 -> 0.0000000000 -inf inf -> inf inf - nan -> nan nan + -nan -> -nan -nan 7.2124891681e-308 -> 1.6207302828 -1021.0000000000 5.7982756057e-308 -> 1.3029400313 -1021.0000000000 4.3840620434e-308 -> 1.9702995595 -1022.0000000000 diff --git a/none/tests/amd64/insn_fpu.def b/none/tests/amd64/insn_fpu.def index 2393d9a..c99815e 100644 --- a/none/tests/amd64/insn_fpu.def +++ b/none/tests/amd64/insn_fpu.def @@ -210,14 +210,14 @@ fildq m64.sq[123456787654321] => st0.ps[123456787654321.0] fildq m64.sq[-123456787654321] => st0.ps[-123456787654321.0] fildq m64.sq[123456787654321] => st0.pd[123456787654321.0] fildq m64.sq[-123456787654321] => st0.pd[-123456787654321.0] -#fists fpucw[0xc00,0x000] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1235] st0.ps[1234.5678] -#fists fpucw[0xc00,0x000] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1235] st0.ps[-1234.5678] -#fists fpucw[0xc00,0x400] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1234] st0.ps[1234.5678] -#fists fpucw[0xc00,0x400] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1235] st0.ps[-1234.5678] -#fists fpucw[0xc00,0x800] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1235] st0.ps[1234.5678] -#fists fpucw[0xc00,0x800] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1234] st0.ps[-1234.5678] -#fists fpucw[0xc00,0xc00] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1234] st0.ps[1234.5678] -#fists fpucw[0xc00,0xc00] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1234] st0.ps[-1234.5678] +fists fpucw[0xc00,0x000] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1235] st0.ps[1234.5678] +fists fpucw[0xc00,0x000] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1235] st0.ps[-1234.5678] +fists fpucw[0xc00,0x400] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1234] st0.ps[1234.5678] +fists fpucw[0xc00,0x400] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1235] st0.ps[-1234.5678] +fists fpucw[0xc00,0x800] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1235] st0.ps[1234.5678] +fists fpucw[0xc00,0x800] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1234] st0.ps[-1234.5678] +fists fpucw[0xc00,0xc00] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1234] st0.ps[1234.5678] +fists fpucw[0xc00,0xc00] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1234] st0.ps[-1234.5678] fistl fpucw[0xc00,0x000] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234568] st0.pd[1234567.7654321] fistl fpucw[0xc00,0x000] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234568] st0.pd[-1234567.7654321] fistl fpucw[0xc00,0x400] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234567] st0.pd[1234567.7654321] @@ -226,14 +226,14 @@ fistl fpucw[0xc00,0x800] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234568] st fistl fpucw[0xc00,0x800] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234567] st0.pd[-1234567.7654321] fistl fpucw[0xc00,0xc00] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234567] st0.pd[1234567.7654321] fistl fpucw[0xc00,0xc00] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234567] st0.pd[-1234567.7654321] -#fistps fpucw[0xc00,0x000] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1235] st0.ps[1111.1111] -#fistps fpucw[0xc00,0x000] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1235] st0.ps[1111.1111] -#fistps fpucw[0xc00,0x400] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1234] st0.ps[1111.1111] -#fistps fpucw[0xc00,0x400] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1235] st0.ps[1111.1111] -#fistps fpucw[0xc00,0x800] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1235] st0.ps[1111.1111] -#fistps fpucw[0xc00,0x800] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1234] st0.ps[1111.1111] -#fistps fpucw[0xc00,0xc00] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1234] st0.ps[1111.1111] -#fistps fpucw[0xc00,0xc00] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1234] st0.ps[1111.1111] +fistps fpucw[0xc00,0x000] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1235] st0.ps[1111.1111] +fistps fpucw[0xc00,0x000] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1235] st0.ps[1111.1111] +fistps fpucw[0xc00,0x400] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1234] st0.ps[1111.1111] +fistps fpucw[0xc00,0x400] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1235] st0.ps[1111.1111] +fistps fpucw[0xc00,0x800] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1235] st0.ps[1111.1111] +fistps fpucw[0xc00,0x800] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1234] st0.ps[1111.1111] +fistps fpucw[0xc00,0xc00] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1234] st0.ps[1111.1111] +fistps fpucw[0xc00,0xc00] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1234] st0.ps[1111.1111] fistpl fpucw[0xc00,0x000] st0.pd[1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[1234568] st0.ps[1111.1111] fistpl fpucw[0xc00,0x000] st0.pd[-1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[-1234568] st0.ps[1111.1111] fistpl fpucw[0xc00,0x400] st0.pd[1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[1234567] st0.ps[1111.1111] diff --git a/none/tests/amd64/insn_fpu.stdout.exp b/none/tests/amd64/insn_fpu.stdout.exp index c790618..2dbaa07 100644 --- a/none/tests/amd64/insn_fpu.stdout.exp +++ b/none/tests/amd64/insn_fpu.stdout.exp @@ -210,6 +210,14 @@ fildq_1 ... ok fildq_2 ... ok fildq_3 ... ok fildq_4 ... ok +fists_1 ... ok +fists_2 ... ok +fists_3 ... ok +fists_4 ... ok +fists_5 ... ok +fists_6 ... ok +fists_7 ... ok +fists_8 ... ok fistl_1 ... ok fistl_2 ... ok fistl_3 ... ok @@ -218,6 +226,14 @@ fistl_5 ... ok fistl_6 ... ok fistl_7 ... ok fistl_8 ... ok +fistps_1 ... ok +fistps_2 ... ok +fistps_3 ... ok +fistps_4 ... ok +fistps_5 ... ok +fistps_6 ... ok +fistps_7 ... ok +fistps_8 ... ok fistpl_1 ... ok fistpl_2 ... ok fistpl_3 ... ok diff --git a/none/tests/amd64/insn_pclmulqdq.def b/none/tests/amd64/insn_pclmulqdq.def new file mode 100644 index 0000000..9593424 --- /dev/null +++ b/none/tests/amd64/insn_pclmulqdq.def @@ -0,0 +1,160 @@ +pclmulqdq imm8[0] xmm.uq[0x00017004200ab0cd,0xc000b802f6b31753] xmm.uq[0xa0005c0252074a9a,0x50002e0207b1643c] => 2.uq[0x5ff61cc8b1043fa2,0x00009602d147dc12] +pclmulqdq imm8[1] xmm.uq[0x28001701e286710d,0xd4000b81d7f0f773] xmm.uq[0xaa0005c1c2a63aaa,0x550002e1c000dc44] => 2.uq[0xd33d2883021ccb74,0x080804b056c3c3bd] +pclmulqdq imm8[16] xmm.uq[0x2a800171beae2d11,0xd54000b9b604d579] xmm.uq[0xaaa0005db1b029ad,0x9550002faf85d3c3] => 2.uq[0x5bd93710a920a9f5,0x777888724b473f64] +pclmulqdq imm8[17] xmm.uq[0x8aa80018be70a8d2,0x4554000d3de61358] xmm.uq[0x22aa00077da0c89b,0xd1550004957e233e] => 2.uq[0xd222922d28094790,0x37fb44403e2d3407] +pclmulqdq imm8[0] m128.uq[0x68aa8003296cd08e,0x3455400273642736] xmm.uq[0x1a2aa002185fd28a,0x0d155001eadda834] => 2.uq[0x6f56f9abeba01e6c,0x05101111e9709d8f] +pclmulqdq imm8[1] m128.uq[0x068aa801d41c9309,0xc3455401c0bc0875] xmm.uq[0xa1a2aa01c70bc327,0x90d15501ca33a080] => 2.uq[0x0c18b0e8ab072480,0x032f76887b10d528] +pclmulqdq imm8[16] m128.uq[0x4868aa81c3c78f2f,0xe4345541c8918684] xmm.uq[0x721a2aa1c2f68231,0xf90d1551c8290009] => 2.uq[0x11d8b7b8f72e3644,0x2a080288f207712b] +pclmulqdq imm8[17] m128.uq[0xbc868aa9cac23ef5,0x9e434555cc0ede67] xmm.uq[0x8f21a2abccb52e20,0x4790d156c50855ff] => 2.uq[0xd2e5bdd1665023dd,0x240dbdff7a0eb888] +pclmulqdq imm8[0] xmm.uq[0xe3c868ac4931e9ec,0x71e434570346b3e5] xmm.uq[0xf8f21a2c685118df,0xbc790d171ad64b5c] => 2.uq[0x0eebfc038c776124,0x5c177a6fb4d9adf2] +pclmulqdq imm8[1] xmm.uq[0x5e3c868c6c18e49d,0xef1e43471cba313b] xmm.uq[0xb78f21a4650ad78e,0x5bc790d311332ab6] => 2.uq[0x01f223ce761bbdbe,0x1046696140e99a8d] +pclmulqdq imm8[16] xmm.uq[0x2de3c86a6747544a,0x16f1e43612516914] xmm.uq[0x0b78f21be7d67379,0xc5bc790eda98f8ad] => 2.uq[0xf1b07b5d2dce2b74,0x008a2a80a6dea4c8] +pclmulqdq imm8[17] xmm.uq[0xa2de3c8843fa3b43,0x916f1e4508aadc92] xmm.uq[0x48b78f2363032d38,0x245bc792902f558b] => 2.uq[0xf8b35e3453aab226,0x10404514973eeacd] +pclmulqdq imm8[0] m128.uq[0xd22de3ca1ec569b6,0x6916f1e5ee1073ca] xmm.uq[0x348b78f3d5b5f8d4,0x1a45bc7ac988bb59] => 2.uq[0x6e44f4974d351b38,0x14410114bf2270ea] +pclmulqdq imm8[1] m128.uq[0xcd22de3e4b721c9d,0xa6916f200c66cd3b] xmm.uq[0x9348b790ece1258e,0x49a45bc9551e51b6] => 2.uq[0xd9ebb20510c452be,0x3590bae854a1ffd5] +pclmulqdq imm8[16] m128.uq[0x24d22de5893ce7ca,0x126916f3a34c32d4] xmm.uq[0x09348b7ab053d859,0xc49a45be2ed7ab1d] => 2.uq[0xeb5e5f29e6badc34,0x00820a20b0fa8ced] +pclmulqdq imm8[17] m128.uq[0xa24d22dffe19947b,0x91269170d5ba892e] xmm.uq[0x489348b9498b0386,0x2449a45d837340b2] => 2.uq[0x1934a4ec2d51b27c,0x10404105d1aac198] +pclmulqdq imm8[0] xmm.uq[0x1224d22fa0675f48,0x09126918aee16e93] xmm.uq[0xc489348d3e1e763a,0x62449a477dbcfa0c] => 2.uq[0x1411baeeee166950,0x0dda5c984c642a65] +pclmulqdq imm8[1] xmm.uq[0x31224d249d8c3bf5,0xd89126932573dce7] xmm.uq[0xac48934a7967ad60,0x562449a61b61959f] => 2.uq[0xf21b031e1f9fc8b3,0x0ffa971b97fa8b81] +pclmulqdq imm8[16] xmm.uq[0xeb1224d3e45e89bc,0x7589126ad0dd03cd] xmm.uq[0xfac489363f1c40d3,0xbd62449bf63bdf5a] => 2.uq[0x751e203b33096d47,0x2d2e6d8fd926d075] +pclmulqdq imm8[17] xmm.uq[0x5eb1224ed9cbae9c,0x2f5891284b93963d] xmm.uq[0xd7ac48950c778a0b,0xabd6244b6ce983f6] => 2.uq[0x6c7f0f43ad1d863e,0x13521ee11ef3275e] +pclmulqdq imm8[0] m128.uq[0x55eb1226952280ea,0x2af58914293eff64] xmm.uq[0x157ac48af34d3ea1,0xcabd624650545e41] => 2.uq[0x249f99dae3b624aa,0x04445511afa5163b] +pclmulqdq imm8[1] m128.uq[0xa55eb123fed7ee11,0x92af5892d619b5f9] xmm.uq[0x8957ac4a41ba99ed,0x84abd626078b0be3] => 2.uq[0x98f8fc12fdf0c7d3,0x507891a8303b6e0d] +pclmulqdq imm8[16] m128.uq[0x8255eb13ea7344e2,0x412af58ad3e76160] xmm.uq[0x20957ac648a16f9f,0xd04abd640afe76bc] => 2.uq[0x5d4e25af2f70ab20,0x08008222e18727b6] +pclmulqdq imm8[17] m128.uq[0x68255eb2e42cfa4d,0xf412af5a58c43c13] xmm.uq[0xba0957ae030fdcfa,0x5d04abd7e035ad6c] => 2.uq[0xa2f470774f11b174,0x36c2fe7c16d26dab] +pclmulqdq imm8[0] xmm.uq[0x2e8255eccec895a5,0xd7412af74e1209bf] xmm.uq[0xaba0957c8db6c3cc,0x55d04abf258920d5] => 2.uq[0xc3db9ad675a26f7c,0x1384704a229c5d7f] +pclmulqdq imm8[1] xmm.uq[0xeae8256079724f57,0xb57412b11366e698] xmm.uq[0x5aba09596861323b,0xed5d04ad9ade580e] => 2.uq[0x631d20044d9fd14a,0x56b5179ab8f1355f] +pclmulqdq imm8[16] xmm.uq[0x76ae8257ac1ceaf6,0x3b57412cb4bc346a] xmm.uq[0x1daba097390bd924,0x0ed5d04c7b33ab81] => 2.uq[0x43140ac0e96646e8,0x02a2888abaa8a737] +pclmulqdq imm8[17] xmm.uq[0xc76ae827144794b1,0xa3b5741460d18949] xmm.uq[0x91daba0b17168395,0x88ed5d06623900b7] => 2.uq[0x84dbc63cd168a7cf,0x54ad45cd2f140103] +pclmulqdq imm8[0] m128.uq[0x8476ae8417ca3f48,0x423b5742ea92de93] xmm.uq[0xe11daba25bf72e3a,0x708ed5d20ca9560c] => 2.uq[0x2f6fd6d371c96950,0x7322f9a7bdfbf7ce] +pclmulqdq imm8[1] m128.uq[0x38476ae9e50269f5,0xdc23b575d92ef3e7] xmm.uq[0xae11dabbc34538e0,0x5708ed5ec0505b5f] => 2.uq[0x36ab4b9f08a71773,0x0d3dae161adae679] +pclmulqdq imm8[16] m128.uq[0xeb8476b046d5ec9c,0x75c23b590218b53d] xmm.uq[0xfae11dad67ba198b,0xbd708ed79a8acbb6] => 2.uq[0x90ab3040b69bed2f,0x2d193b789ecdb8bf] +pclmulqdq imm8[17] m128.uq[0x5eb8476cabf324ca,0x2f5c23b734a75154] xmm.uq[0x17ae11dc79016799,0xcbd708ef132e72bd] => 2.uq[0x58394f2a30276364,0x1d6c5d6217d64627] +pclmulqdq imm8[0] xmm.uq[0xa5eb84786044f84b,0x92f5c23d16d03b16] xmm.uq[0x497ae11f6a15dc7a,0x24bd709093b8ad2c] => 2.uq[0xa19f5f3d150729de,0x2cc3c480d7262702] +pclmulqdq imm8[1] xmm.uq[0x125eb849288a1585,0xc92f5c257af2c9af] xmm.uq[0xa497ae13942723c4,0x524bd70aa8c150d1] => 2.uq[0xd86609565dd8fe15,0x0592c7bc6f0bff4b] +pclmulqdq imm8[16] xmm.uq[0xe925eb863b0e6759,0xb492f5c3f434f29d] xmm.uq[0x9a497ae2d0c8383b,0x8d24bd723f11db0e] => 2.uq[0x5a7c0b0663ed613f,0x55e5e712e20a7f3d] +pclmulqdq imm8[17] xmm.uq[0x46925eb9fe36ac76,0x23492f5dddc9152a] xmm.uq[0x11a497afcd924984,0x08d24bd8c576e3b1] => 2.uq[0x64d528322b29c9ca,0x01014411a41cd8f9] +pclmulqdq imm8[0] m128.uq[0xc46925ed496930c9,0xa23492f78b625755] xmm.uq[0x911a497cac5eea97,0x888d24bf3cdd3438] => 2.uq[0x9ee57eac6392c06f,0x6ebdb35952de298b] +pclmulqdq imm8[1] m128.uq[0x444692607d1c590b,0xe2234931153beb76] xmm.uq[0x7111a499694bb4aa,0x3888d24d93539944] => 2.uq[0xe76d06e2b08e45ec,0x0eceb968e17faa1f] +pclmulqdq imm8[16] m128.uq[0x1c446927a8578b91,0xce223494bad984b9] xmm.uq[0xa7111a4b341a814d,0x93888d2670baff93] => 2.uq[0x351bc2f119e0a4d5,0x7cb3956d93a777bb] +pclmulqdq imm8[17] m128.uq[0x89c446940f0b3eba,0x44e2234ae6335e4c] xmm.uq[0x227111a651c76e15,0xd13888d3ff9175f7] => 2.uq[0x52b883d7adab3fa4,0x374d8c769fd3cfd2] +pclmulqdq imm8[0] xmm.uq[0xa89c446ad67679e8,0x544e223649e8fbe3] xmm.uq[0xea27111c0ba23ce2,0x7513888ee47edd60] => 2.uq[0x71258e2844da20d0,0x6f79237864913e89] +pclmulqdq imm8[1] xmm.uq[0x3a89c44850ed2d9f,0xdd44e224ff2455bc] xmm.uq[0x6ea271135e3fe9cd,0xf751388a85cdb3d3] => 2.uq[0x0dce470a58b03611,0x17b7bff3cae3b878] +pclmulqdq imm8[16] xmm.uq[0xbba89c46299498da,0x5dd44e23f3780b5c] xmm.uq[0x2eea2712d869c49d,0xd775138a42e2a13b] => 2.uq[0x8e66578f04b5170c,0x08a8a888e58cdcd5] +pclmulqdq imm8[17] xmm.uq[0xabba89c6081f0f8e,0x55dd44e3e2bd46b6] xmm.uq[0x2aeea272d00c624a,0x1577513a46b3f014] => 2.uq[0x00039e62361051b8,0x04445454c9e2e3b4] +pclmulqdq imm8[0] m128.uq[0x0abba89e0207b6f9,0xc55dd44fe7b19a6d] xmm.uq[0xa2aeea28da868c23,0x9157751543f10502] => 2.uq[0xec91a12c1e78a82b,0x041bb00df2e9eeb3] +pclmulqdq imm8[1] m128.uq[0x48abba8b80a64170,0x2455dd469f00dfa7] xmm.uq[0xd22aeea4262e2ec0,0x69157752f1c4d64f] => 2.uq[0x4570a9283f65b1d0,0x1937917bc5469bf6] +pclmulqdq imm8[16] m128.uq[0xf48abbaa4f902a14,0x7a455dd60675d3f9] xmm.uq[0xfd22aeebe9e8a8ed,0xbe915776dba21363] => 2.uq[0x9708dd208b1f1635,0x2911f19625f63a33] +pclmulqdq imm8[17] m128.uq[0x9f48abbc447ec8a2,0x4fa455df00ed2340] xmm.uq[0x27d22af05f24508f,0xd3e91579063fe734] => 2.uq[0x9e438129c0f21100,0x302e6e9fad692a63] +pclmulqdq imm8[0] xmm.uq[0x69f48abd61cdb289,0xf4fa455f97949835] xmm.uq[0xba7d22b0a2780b07,0x9d3e915937e9c470] => 2.uq[0x77453ab2e39bcebf,0x3cd48149e75425dc] +pclmulqdq imm8[1] xmm.uq[0x4e9f48ad7aa2a127,0xe74fa45793ff0f80] xmm.uq[0x73a7d22ca8ad46af,0xf9d3e9173b046244] => 2.uq[0x6e590e31be91a35c,0x3bd8e3c886ba7063] +pclmulqdq imm8[16] xmm.uq[0x7ce9f48c7c2ff011,0xfe74fa4714c5b6f9] xmm.uq[0xbf3a7d2461109a6d,0x9f9d3e9317360c23] => 2.uq[0xd73226ad987c91b5,0x6a0d4938c709c850] +pclmulqdq imm8[17] xmm.uq[0x8fce9f4a6248c502,0x47e74fa60fd22170] xmm.uq[0x23f3a7d3e696cfa7,0xd1f9d3ead9f926c0] => 2.uq[0x098aae5ab281c400,0x360f213f1f15053e] +pclmulqdq imm8[0] m128.uq[0x68fce9f64baa524f,0xf47e74fc0c82e814] xmm.uq[0x7a3f3a7ee4ef32f9,0xfd1f9d405925586d] => 2.uq[0xc7150c4a11569767,0x1230b217e7562125] +pclmulqdq imm8[1] m128.uq[0xbe8fcea103406b23,0x9f47e751684df482] xmm.uq[0x4fa3f3a992d4b930,0x27d1f9d5a8181b87] => 2.uq[0x7ec8d0bb7e8acd69,0x14938d347e59462d] +pclmulqdq imm8[16] m128.uq[0xd3e8fcebbab9ccb0,0x69f47e76bc0aa547] xmm.uq[0xf4fa3f3c34b31190,0x7a7d1f9ef90747b7] => 2.uq[0x4d62ab2759d0c0f0,0x24a78a2ff2816467] +pclmulqdq imm8[17] m128.uq[0xfd3e8fd0533162c8,0x7e9f47e908467053] xmm.uq[0xff4fa3f56ad0f71a,0x7fa7d1fb94163a7c] => 2.uq[0xb7fc82a330a83644,0x152129527f84cd53] +pclmulqdq imm8[0] xmm.uq[0x3fd3e8fea8b8dc2d,0xdfe9f4803b0a2d03] xmm.uq[0xaff4fa40f432d572,0x57fa7d2158c729a8] => 2.uq[0xad24061697897d6a,0x1946dd2b6b334aa6] +pclmulqdq imm8[1] xmm.uq[0x2bfd3e918b1153c3,0xd5fe9f49ac3668d2] xmm.uq[0x6aff4fa5b4c8f358,0x357fa7d3b912389b] => 2.uq[0x01e66902d969ffed,0x0748de913628c280] +pclmulqdq imm8[16] xmm.uq[0xdabfd3eab336db3e,0x6d5fe9f638492c8e] xmm.uq[0x36aff4fbfad25536,0x1b57fa7edc16e98a] => 2.uq[0x9a16d14091086404,0x0a2888aa8b3b5dd4] +pclmulqdq imm8[17] xmm.uq[0x0dabfd404cb933b4,0x06d5fea1050a58c9] xmm.uq[0xc36aff516932eb55,0xa1b57fa99b473497] => 2.uq[0x3f904f57b277f66f,0x03b554c0f32d4dfa] +pclmulqdq imm8[0] m128.uq[0x90dabfd5a4515938,0x486d5febb0d66b8b] xmm.uq[0xe436aff6af18f4b6,0x721b57fc363a394a] => 2.uq[0x8c5f6ad18d379e10,0x7c1be44f7439dfec] +pclmulqdq imm8[1] m128.uq[0x390dabfef9cadb94,0x1c86d6005b932cb9] xmm.uq[0xce436b010477554d,0xa721b58168e96993] => 2.uq[0x5cfbe32f78bbabfc,0x1b0f409db94d30ce] +pclmulqdq imm8[16] m128.uq[0x9390dac19b2273ba,0x49c86d61ac3ef8cc] xmm.uq[0x24e436b1b4cd3b55,0xd2721b59b1145c97] => 2.uq[0x6a2bef2bac52d03c,0x0820a820580aebf6] +pclmulqdq imm8[17] m128.uq[0xa9390dadaf37ed38,0x549c86d7b649b58b] xmm.uq[0xea4e436cb1d299b6,0x752721b737970bca] => 2.uq[0xe374fdf10b9aa50e,0x1bf0a13b9a4b2d32] +pclmulqdq imm8[0] xmm.uq[0x3a9390dc7a7944d4,0x1d49c86f1bea6159] xmm.uq[0xcea4e43864a2ef9d,0xa752721d18ff36bb] => 2.uq[0xd6c456490d755a64,0x12bc3c19097f5a00] +pclmulqdq imm8[1] xmm.uq[0x93a9390f632d5a4e,0x49d49c8890446c16] xmm.uq[0x24ea4e4526cff4fa,0x127527237215b96c] => 2.uq[0x8d19b35c04f67f08,0x0820a88940df4faa] +pclmulqdq imm8[16] xmm.uq[0x093a939297b89ba5,0xc49d49ca228a0cbf] xmm.uq[0xa24ea4e5f7f2c54c,0x51275273daa72195] => 2.uq[0xa98a2c26439b7bc4,0x7b61d63f58d2a46a] +pclmulqdq imm8[17] xmm.uq[0xe893a93ac4014fb7,0xb449d49e48ae66c8] xmm.uq[0x5a24ea500304f253,0xed127528e830381a] => 2.uq[0xcd6a96a3f2ca5750,0x66729b7e79914803] +pclmulqdq imm8[0] m128.uq[0x76893a9552c5dafc,0x3b449d4b8810ac6d] xmm.uq[0xdda24ea6aab61523,0xaed127543c08c982] => 2.uq[0x71e1947ce8a3fc84,0x23a3c3ff0ac48e0c] +pclmulqdq imm8[1] m128.uq[0x576893aafcb223b0,0x2bb449d65d06d0c7] xmm.uq[0xd5da24ec05312750,0x6aed1276e1465297] => 2.uq[0x83bc107e3e1d6910,0x1d159417367f29d6] +pclmulqdq imm8[16] m128.uq[0xf576893c5750e838,0x7abb449f0a56330b] xmm.uq[0xfd5da2506bd8d876,0x7eaed129149a2b2a] => 2.uq[0x162d65810a9a912a,0x295151cffabdfebc] +pclmulqdq imm8[17] m128.uq[0x3f57689568fad484,0x1fabb44b932b2931] xmm.uq[0xcfd5da26a0435389,0xa7eaed1436cf68b5] => 2.uq[0xd2b7ff103f384845,0x0c75fdbda2b7fa1d] +pclmulqdq imm8[0] xmm.uq[0x93f5768af2157347,0x89fabb464fb87890] xmm.uq[0x44fd5da40689fb37,0xe27eaed2e9f2bc88] => 2.uq[0x1efac67fed4d2545,0x26c2a63498b85e4e] +pclmulqdq imm8[1] xmm.uq[0x713f576a53a71d33,0xf89fabb600814d8a] xmm.uq[0x7c4fd5dbdeee65b4,0x3e27eaeece24f1c9] => 2.uq[0x25ac28bd28c702eb,0x0b943f31e76dc46a] +pclmulqdq imm8[16] xmm.uq[0xdf13f5784dc037d5,0xaf89fabd0d8ddad7] xmm.uq[0x97c4fd5f6d74ac58,0x4be27eb09568151b] => 2.uq[0x88ede6d4e2454a08,0x5e0c23d1ad9c93aa] +pclmulqdq imm8[17] xmm.uq[0xe5f13f592161c97e,0x72f89fad6f5ea3ae] xmm.uq[0x397c4fd7965d10c6,0x1cbe27eca9dc4752] => 2.uq[0x5dd6030446d65c3c,0x0541155160eaa5f3] +pclmulqdq imm8[0] m128.uq[0x0e5f13f7339be298,0x072f89fc787bb03b] xmm.uq[0xc397c4ff12eb970e,0x61cbe28068238a76] => 2.uq[0x9d37888783271390,0x04ad49530ddeba57] +pclmulqdq imm8[1] m128.uq[0x30e5f14112bf842a,0x1872f8a1680d8104] xmm.uq[0x0c397c5192b47f71,0xc61cbe29a007fea9] => 2.uq[0xda22a0000546f93a,0x14eb8e72cfa9f51d] +pclmulqdq imm8[16] m128.uq[0xa30e5f15b6b1be45,0x91872f8bb2069e0f] xmm.uq[0x88c397c6afb10df4,0x4461cbe4368645e9] => 2.uq[0x0afb9d418fc1966c,0x4c22fc2c395f9b0a] +pclmulqdq imm8[17] m128.uq[0xe230e5f2f1f0e1e5,0xb11872fa4fa62fdf] xmm.uq[0x988c397e0e80d6dc,0x4c461cbfe5ee2a5d] => 2.uq[0x4a4c895ad9a6426b,0x2b2552b15c95b45a] +pclmulqdq imm8[0] xmm.uq[0xe6230e60d9a4d41b,0xb3118731438028fe] xmm.uq[0x5988c399806dd36e,0x2cc461cd9ee4a8a6] => 2.uq[0xb4bce4629b6a0022,0x3049a355e88b747d] +pclmulqdq imm8[1] xmm.uq[0x166230e7ae201342,0x0b311874b5bdc890] xmm.uq[0x05988c3b398ca337,0xc2cc461e73741088] => 2.uq[0x1443368a87d51b10,0x0e8b16ca9bb0a8d6] +pclmulqdq imm8[16] xmm.uq[0x616623101867c733,0xf0b31188e2e1a28a] xmm.uq[0x785988c5501e9034,0x3c2cc46386bd0709] => 2.uq[0x505b0a15e10953c8,0x2a8022826ef2c0ed] +pclmulqdq imm8[17] xmm.uq[0xde166232aa0c4275,0xaf0b311a3bb3e027] xmm.uq[0x9785988df487af00,0x4bc2cc47d8f1966f] => 2.uq[0x73b0bf7077a68eed,0x2f36ea74050c13fe] +pclmulqdq imm8[0] m128.uq[0xe5e16624c3268a24,0x72f0b31340410401] xmm.uq[0xf978598a86ce40f1,0xbcbc2cc62a14df69] => 2.uq[0xbd20232a4309f7e4,0x5e8cbf9a58306d67] +pclmulqdq imm8[1] m128.uq[0x9e5e1663fbb82ea5,0x8f2f0b32d489d63f] xmm.uq[0x8797859a40f2aa0c,0x43cbc2cdff2713f5] => 2.uq[0x6e66a095df81ee01,0x2658e6d490286e46] +pclmulqdq imm8[16] m128.uq[0xe1e5e167d64148e7,0xb0f2f0b4c1ce6360] xmm.uq[0x5879785b3f94f09f,0xec3cbc2e7678373c] => 2.uq[0xa1411d12187db520,0x22802a82bbe48273] +pclmulqdq imm8[17] m128.uq[0x761e5e1819e9da8d,0xfb0f2f0ce3a2ac33] xmm.uq[0xbd879787587f150a,0x5ec3cbc48aed4974] => 2.uq[0x98102e76a4d8925c,0x34f36e356807a7b8] +pclmulqdq imm8[0] xmm.uq[0x2f61e5e3242463a9,0xd7b0f2f278bff0c5] xmm.uq[0xabd8797a130db74f,0x95ec3cbde0349a94] => 2.uq[0xa9db52b34932b257,0x13498b4de2ead42b] +pclmulqdq imm8[1] xmm.uq[0x4af61e5fcec80c39,0xe57b0f30ce11c50d] xmm.uq[0xb2bd87994db6a173,0x995ec3cd8d890faa] => 2.uq[0x02bdfd5b8ae3851a,0x23dce4693be7adf0] +pclmulqdq imm8[16] xmm.uq[0x4caf61e7a57246c4,0x2657b0f4b166e251] xmm.uq[0xd32bd87b2f613019,0xa995ec3e7e5e56fd] => 2.uq[0x65396ddebd61e5c9,0x18b43ccdffec0aab] +pclmulqdq imm8[17] xmm.uq[0x94caf62015dcea6b,0x8a657b10e19c3426] xmm.uq[0x4532bd894f7bd902,0x22995ec5866bab70] => 2.uq[0xe5df1fa230385520,0x101105049484270b] +pclmulqdq imm8[0] m128.uq[0x114caf63a1e394a7,0xc8a657b2b79f8940] xmm.uq[0x64532bda3a7d838f,0xf22995edf3ec80b4] => 2.uq[0x14b59c3f07c170cd,0x063afa20a20bf1d3] +pclmulqdq imm8[1] m128.uq[0x7914caf7d8a3ff49,0xfc8a657cc2ffbe95] xmm.uq[0xbe4532bf482d9e37,0x9f2299608ac48e08] => 2.uq[0xd1b3a3b63ca68448,0x39b309fce070d54f] +pclmulqdq imm8[16] m128.uq[0x4f914cb1241005f3,0xe7c8a65978b5c1ea] xmm.uq[0x73e4532d9b089fe4,0x39f22997ac320ee1] => 2.uq[0xfe28658d590ed368,0x2a0aa820dbbaae83] +pclmulqdq imm8[17] m128.uq[0xdcf914ccbcc6c661,0xae7c8a6735112221] xmm.uq[0x973e453471365001,0x8b9f229b0f48e6f1] => 2.uq[0x12081cb0e7a6fad1,0x53e4d12a4d38b461] +pclmulqdq imm8[0] xmm.uq[0x85cf914e6e523269,0x82e7c8a81dd6d825] xmm.uq[0x8173e454e5992aff,0x80b9f22b597a546c] => 2.uq[0x747ebfee06547327,0x425a6e980d6f32f8] +pclmulqdq imm8[1] xmm.uq[0x405cf9168b6ae925,0xe02e7c8c2c63337f] xmm.uq[0xb0173e46fcdf58ac,0x580b9f245d1d6b45] => 2.uq[0x10d3ee4c6cada3f1,0x1612f3ff623fded0] +pclmulqdq imm8[16] xmm.uq[0xec05cf93053c748f,0xb602e7ca694bf934] xmm.uq[0x5b0173e61353bb89,0xed80b9f3e0579cb5] => 2.uq[0x465f8b79f0199694,0x228a0003e5a76b0c] +pclmulqdq imm8[17] xmm.uq[0xb6c05cfad6d98d47,0x9b602e7e421a8590] xmm.uq[0x4db0173fffbb01b7,0xe6d80ba0d68b3fc8] => 2.uq[0xf7caf3aef858f080,0x7b3959bd543d5319] +pclmulqdq imm8[0] m128.uq[0x736c05d149f35ed3,0xf9b602e98ba76e5a] xmm.uq[0x7cdb0175a481761c,0x3e6d80bbb0ee79fd] => 2.uq[0x4d7e2029ce741ae4,0x17f7c4da2519e2fb] +pclmulqdq imm8[1] m128.uq[0xdf36c05eaf24fbeb,0xaf9b60303e403ce6] xmm.uq[0x57cdb018fdcddd62,0x2be6d80d5d94ada0] => 2.uq[0x0b6d29afcf3d77e0,0x1c3f14ae1ee34afc] +pclmulqdq imm8[16] m128.uq[0x15f36c078d7815bf,0xcaf9b604ad69c9cc] xmm.uq[0x657cdb033562a3d5,0xf2be6d82715f10d7] => 2.uq[0x45492b482259333c,0x28222aa042940471] +pclmulqdq imm8[17] m128.uq[0xb95f36c20f5d4758,0x5caf9b61e65c629b] xmm.uq[0xee57cdb1d9dbf03e,0x772be6d9cb9bb70e] => 2.uq[0xa564c7636b75ca82,0x18ea04a16910639d] +pclmulqdq imm8[0] xmm.uq[0x3b95f36dc47b9a76,0x1dcaf9b7c0eb8c2a] xmm.uq[0x0ee57cdcbf238504,0x0772be6f3e3f8171] => 2.uq[0x93da7ceefb7cc7d8,0x01515044e5c70080] +pclmulqdq imm8[1] xmm.uq[0xc3b95f3875cd7fa9,0xa1dcaf9d11947ec5] xmm.uq[0x90ee57cf5f77fe4f,0x88772be88669be14] => 2.uq[0x1ff2cadc63448a34,0x67e792c3afe8cc55] +pclmulqdq imm8[16] xmm.uq[0x443b95f521e29df9,0xe21dcafb779f0ded] xmm.uq[0xb10ee57e927d45e3,0x988772c01fec61e2] => 2.uq[0x0fa35a87a4453f57,0x638b976af3ff9af9] +pclmulqdq imm8[17] xmm.uq[0x4c43b960eea3efe0,0x2621dcb155ffb6df] xmm.uq[0xd310ee5981ad9a5c,0x6988772d9f848c1d] => 2.uq[0x51c023c60bf9b2ab,0x0c494dba164d6a1a] +pclmulqdq imm8[0] m128.uq[0xf4c43b97a67004fb,0xba621dccb9e5c16e] xmm.uq[0x5d310ee73ba09fa6,0x2e9887747c7e0ec2] => 2.uq[0x031c347016c9f1fa,0x36ed9d92bc682f1e] +pclmulqdq imm8[1] m128.uq[0x174c43bb1cecc650,0x0ba621de6d242217] xmm.uq[0xc5d310f01d3fcff8,0x62e98878ed4da6eb] => 2.uq[0xacf5238d6a7eee70,0x07183a9373413ee5] +pclmulqdq imm8[16] m128.uq[0xf174c43d5d549266,0x78ba621f8d580822] xmm.uq[0x3c5d3110a559c300,0x1e2e9889315aa06f] => 2.uq[0xf27d9c6ac793e600,0x0aa022a73ecb539d] +pclmulqdq imm8[17] m128.uq[0xcf174c456f5b0f24,0x678ba623965b4681] xmm.uq[0xf3c5d312a1db6231,0xb9e2e98a379b7009] => 2.uq[0xd950b5c449820289,0x3a31f7c40b66ebf6] +pclmulqdq imm8[0] xmm.uq[0x9cf174c5f27b76f5,0x8e78ba63cfeb7a67] xmm.uq[0x873c5d32cea37c20,0x439e2e9a45ff7cff] => 2.uq[0xd8c13a16143112a0,0x4db281bbf229390c] +pclmulqdq imm8[1] xmm.uq[0xe1cf174e09ad7d6c,0x70e78ba7e3847da5] xmm.uq[0xf873c5d4d86ffdbf,0xbc39e2eb42e5bdcc] => 2.uq[0x71ad667673cd0fd0,0x665e4345d7dcc057] +pclmulqdq imm8[16] xmm.uq[0x5e1cf17680209dd5,0xef0e78bc26be0dd7] xmm.uq[0xb7873c5efa0cc5d8,0x5bc39e305bb421db] => 2.uq[0x4b74700bf2d5e688,0x666e225b4656f8e1] +pclmulqdq imm8[17] xmm.uq[0xede1cf190487cfde,0x76f0e78d60f1a6de] xmm.uq[0x3b7873c78f26925e,0x1dbc39e4a641081e] => 2.uq[0x17a07657d2da7dd4,0x0545154178351fca] +pclmulqdq imm8[0] m128.uq[0x0ede1cf331ce42fe,0x076f0e7a7794e06e] xmm.uq[0x03b7873e1a782f26,0x01dbc39febe9d682] => 2.uq[0x964b33c978b91bc4,0x0015145519fbe3f5] +pclmulqdq imm8[1] m128.uq[0x00ede1d0d4a2aa30,0x0076f0e948ff1407] xmm.uq[0xc03b78758b2d48f0,0x601dbc3ba4446367] => 2.uq[0x55314fda6f66cc90,0x0026cec405b1e6f8] +pclmulqdq imm8[16] m128.uq[0xf00ede1eb8cff0a0,0x78076f103b15b73f] xmm.uq[0xfc03b788f4389a8c,0x7e01dbc558ca0c35] => 2.uq[0x6a82fe6939f30c84,0x28a26c46b7ebe635] +pclmulqdq imm8[17] m128.uq[0xff00ede38312c507,0xbf8076f2a8372170] xmm.uq[0x5fc03b7a32c94fa7,0xefe01dbdf01266c0] => 2.uq[0xdcc216f4dd0dc400,0x617576c564455645] +pclmulqdq imm8[0] xmm.uq[0x77f00edfd6b6f24f,0xfbf80770c2093814] xmm.uq[0x7dfc03b93fb25af9,0xfefe01dd7686ec6d] => 2.uq[0x8bf569c40aba6f67,0x1647572ea59fec88] +pclmulqdq imm8[1] xmm.uq[0xbf7f00ef91f13523,0x9fbf80789fa65982] xmm.uq[0x4fdfc03d2e80ebb0,0x27efe01f75ee34c7] => 2.uq[0x1884b704d5d08ea9,0x14b2b2b889275ed6] +pclmulqdq imm8[16] xmm.uq[0xd3f7f01091a4d950,0x69fbf80927802b97] xmm.uq[0xf4fdfc057a6dd4b8,0x7a7efe039be4a94b] => 2.uq[0x2fa301cae17930a8,0x24a3a8a439dad38b] +pclmulqdq imm8[17] xmm.uq[0xfd3f7f02a4a01396,0x7e9fbf8230fdc8ba] xmm.uq[0x3f4fdfc1f72ca34c,0x1fa7efe1da441095] => 2.uq[0x5cff626dd6d19cf2,0x0555105536974019] +pclmulqdq imm8[0] m128.uq[0xcfd3f7f1c3cfc737,0xa7e9fbf9c895a288] xmm.uq[0x53f4fdfdc2f89033,0xe9fa7effc82a070a] => 2.uq[0xf6af04decad42cc9,0x3e1bd743a16ab263] +pclmulqdq imm8[1] m128.uq[0x74fd3f80c2c2c274,0x3a7e9fc1400f2029] xmm.uq[0xdd3f4fe186b54f05,0xae9fa7f1aa08666f] => 2.uq[0x663f048b0f4c376c,0x3643329a1e33c49c] +pclmulqdq imm8[16] m128.uq[0x974fd3f9bbb1f224,0x4ba7e9fdbc86b801] xmm.uq[0xe5d3f4ffb4f11af1,0xb2e9fa80b1264c69] => 2.uq[0x2db9e522590922f1,0x3f18ac8b499a5fdb] +pclmulqdq imm8[17] m128.uq[0x9974fd412f40e525,0x8cba7ea17e4e317f] xmm.uq[0x865d3f5195d4d7ac,0x432e9fa9a9982ac5] => 2.uq[0x10a01544dcacf2c3,0x22adc12d86b454a7] +pclmulqdq imm8[0] xmm.uq[0xe1974fd5bb79d44f,0xb0cba7ebb46aa914] xmm.uq[0x5865d3f6b8e31379,0xec32e9fc331f48ad] => 2.uq[0x39f8c415582c89e7,0x31576a4bfbf9de3f] +pclmulqdq imm8[1] xmm.uq[0xb61974fef03d6343,0x9b0cba804ecc7092] xmm.uq[0x4d865d410613f738,0x26c32ea161b7ba8b] => 2.uq[0xfe6e5df6e325505d,0x150039e3f5d91dc7] +pclmulqdq imm8[16] xmm.uq[0xd361975197899c36,0x69b0cba9aa728d0a] xmm.uq[0x34d865d5b3e70574,0x1a6c32ebb8a141a9] => 2.uq[0x51a65ce85f5f2548,0x0a20a2805797ed23] +pclmulqdq imm8[17] xmm.uq[0xcd361976b2fe5fc5,0xa69b0cbc302ceecf] xmm.uq[0x934d865eeec43654,0x49a6c330560fda19] => 2.uq[0x743fc6e863032247,0x2c70b2e5c1075701] +pclmulqdq imm8[0] m128.uq[0xe4d3619901b5abfd,0xb269b0cd678894eb] xmm.uq[0x9934d8679a720966,0x4c9a6c34abe6c3a2] => 2.uq[0xe48d608e6c5c6dee,0x7bf7c8be42cbc359] +pclmulqdq imm8[1] m128.uq[0x264d361b34a120c0,0x13269b0e78fe4f4f] xmm.uq[0xc9934d88132ce694,0x64c9a6c4e8443239] => 2.uq[0x4e519b2288cbb2c0,0x0dd8694f6a24e1f8] +pclmulqdq imm8[16] m128.uq[0xf264d3635acfd80d,0xb93269b28415aaf3] xmm.uq[0x9c9934da28b8946a,0x4e4c9a6df30a0924] => 2.uq[0xe72a61cb516c9cde,0x50752c361fe9f790] +pclmulqdq imm8[17] m128.uq[0x27264d37d832c381,0xd393269cc2c720b1] xmm.uq[0xa9c9934f48114f49,0x94e4c9a88ab66695] => 2.uq[0x086a7585d4d637e5,0x67faa7d867e596e8] +pclmulqdq imm8[0] xmm.uq[0x8a7264d52c08f237,0x8539326b7cb23808] xmm.uq[0x429c99369d06daf3,0xe14e4c9c25312c6a] => 2.uq[0x4100ed2820bf0389,0x23c3d0ef192c679b] +pclmulqdq imm8[1] xmm.uq[0x70a7264ef1465524,0x385393285750e981] xmm.uq[0xdc29c995025633b1,0xae14e4cb67d8d8c9] => 2.uq[0x8f6981733d8b4704,0x34e77f6cd5d2d608] +pclmulqdq imm8[16] xmm.uq[0x970a72669a9a2b55,0x8b85393423fad497] xmm.uq[0x85c29c9af8ab2938,0x42e14e4e5b03538b] => 2.uq[0x334171ba41a2b028,0x470172dfe90ec7a3] +pclmulqdq imm8[17] xmm.uq[0xe170a728042f68b6,0x70b85394e0c5734a] xmm.uq[0x385c29cb4f107894,0x1c2e14e68635fb39] => 2.uq[0x464de85ad5b05afa,0x05401150a66ea4dd] +pclmulqdq imm8[0] m128.uq[0xce170a7429c8bc8d,0xa70b853afb921d33] xmm.uq[0x9385c29e5476cd8a,0x49c2e15008e925b4] => 2.uq[0x6f7ef804725bcaf2,0x6adc6430b8465eaf] +pclmulqdq imm8[1] m128.uq[0x24e170a8e32251c9,0xd270b855583ee7d5] xmm.uq[0xa9385c2b82cd32d7,0x949c2e16a8145858] => 2.uq[0x1be3bccbf3f77898,0x10bca5dea41e786f] +pclmulqdq imm8[16] m128.uq[0x4a4e170c32b7eb1b,0xe5270b86f009b47e] xmm.uq[0x729385c456b2992e,0x3949c2e30a070b86] => 2.uq[0x2b68e2765ffdfb34,0x2a08820822669a21] +pclmulqdq imm8[17] m128.uq[0x1ca4e17263b144b2,0x0e5270ba10866148] xmm.uq[0x0729385de6f0ef93,0xc3949c2fda2636ba] => 2.uq[0x27bb3d7f7f6f6150,0x04a8a03284562190] +pclmulqdq imm8[0] xmm.uq[0x61ca4e18cbc0da4c,0x30e5270d448e2c15] xmm.uq[0xd872938788f4d4f7,0xac3949c4ab282968] => 2.uq[0x45795f55a307afa4,0x2d97e09b0bc3ba6e] +pclmulqdq imm8[1] xmm.uq[0x561ca4e33441d3a3,0xeb0e527270cea8c2] xmm.uq[0x7587293a17151350,0x3ac3949dea384897] => 2.uq[0x8952066b3e0c09d9,0x0d80def82390fa59] +pclmulqdq imm8[16] xmm.uq[0xdd61ca4fdbc9e338,0x6eb0e528cc92b08b] xmm.uq[0xf75872954cf71736,0x7bac394b85294a8a] => 2.uq[0x07e8e44eff28bbea,0x26de695e1f9507ac] +pclmulqdq imm8[17] xmm.uq[0x3dd61ca6a1426434,0x1eeb0e542f4ef109] xmm.uq[0xcf75872afe553775,0xa7bac39655d85aa7] => 2.uq[0x8fad3e20986ef89f,0x0cfdf3f1f7833e00] +pclmulqdq imm8[0] m128.uq[0x93dd61cc0199ec40,0x49eeb0e6df7ab50f] xmm.uq[0xe4f75874466b1974,0x727bac3b01e34ba9] => 2.uq[0xc93a243ecc35ad00,0x7d58bcc299211eab] +pclmulqdq imm8[1] m128.uq[0xf93dd61e679f64c5,0xbc9eeb101a7d714f] xmm.uq[0x9e4f7588e3ec7794,0x4f27bac550a3fab9] => 2.uq[0x96014936edcb669d,0x3b74884e3421a5a6] +pclmulqdq imm8[16] m128.uq[0xe793dd637effbc4d,0xb3c9eeb2962d9d13] xmm.uq[0x99e4f75a21c48d7a,0x4cf27badef9005ac] => 2.uq[0xe083eb2842bea22e,0x579424d4aee04284] +pclmulqdq imm8[17] m128.uq[0x26793dd7d675c1c5,0xd33c9eecc1e89fcf] xmm.uq[0xa99e4f7747a20ed4,0x54cf27bc827ec659] => 2.uq[0xbbe2a4fae75c8c87,0x3ae9f530feca9e83] +pclmulqdq imm8[0] xmm.uq[0xea6793df27ed221d,0xb533c9f07aa44ffb] xmm.uq[0x9a99e4f913ffe6ee,0x4d4cf27d68adb266] => 2.uq[0x2ecb87e2ee7738c6,0x7d6e3e944eaff450] +pclmulqdq imm8[1] xmm.uq[0x26a6793f93049822,0x13533ca0a8300b00] xmm.uq[0x09a99e5132c5c46f,0xc4d4cf297010a124] => 2.uq[0xae7428c8952c06c8,0x1a782a535e1cf462] +pclmulqdq imm8[16] xmm.uq[0x626a679596b60f81,0xf13533cba208c6b1] xmm.uq[0xb89a99e6b7b22249,0x9c4d4cf43286d015] => 2.uq[0x4a8f4c6ff6f61d79,0x6e57579e887d4fc8] +pclmulqdq imm8[17] xmm.uq[0x8e26a67aeff126f7,0x8713533e5ea65268] xmm.uq[0x4389a9a00e00e823,0xe1c4d4d0edae3302] => 2.uq[0x7752ad4e77e19cd0,0x72483d1e1c0e1d3a] +pclmulqdq imm8[0] m128.uq[0x70e26a695584d870,0x3871353589702b27] xmm.uq[0xdc389a9bab65d480,0x6e1c4d4eb460a92f] => 2.uq[0xd8c101b07d1ef800,0x2109baafa5af4636] +pclmulqdq imm8[1] m128.uq[0xf70e26a830de1384,0x7b871354f71cc8b1] xmm.uq[0xfdc389ab523c2349,0xbee1c4d67fcbd095] => 2.uq[0x2e0ab5ce0af9e7d4,0x6fc4778aacb0c279] +pclmulqdq imm8[16] m128.uq[0x9f70e26c1693a737,0x8fb87136e1f79288] xmm.uq[0x47dc389c4fa98833,0xe3ee1c4f0e82830a] => 2.uq[0x5e76a6469d8b8e18,0x202aa2a3ba5c9f52] +pclmulqdq imm8[17] m128.uq[0x71f70e2865ef0074,0x38fb871511a53f29] xmm.uq[0xdc7dc38b5f805e85,0xae3ee1c6866dee2f] => 2.uq[0xe9f524d62e90ffb7,0x1a32a63921dddcea] diff --git a/none/tests/amd64/insn_pclmulqdq.stderr.exp b/none/tests/amd64/insn_pclmulqdq.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/amd64/insn_pclmulqdq.stdout.exp b/none/tests/amd64/insn_pclmulqdq.stdout.exp new file mode 100644 index 0000000..7bfc790 --- /dev/null +++ b/none/tests/amd64/insn_pclmulqdq.stdout.exp @@ -0,0 +1,160 @@ +pclmulqdq_1 ... ok +pclmulqdq_2 ... ok +pclmulqdq_3 ... ok +pclmulqdq_4 ... ok +pclmulqdq_5 ... ok +pclmulqdq_6 ... ok +pclmulqdq_7 ... ok +pclmulqdq_8 ... ok +pclmulqdq_9 ... ok +pclmulqdq_10 ... ok +pclmulqdq_11 ... ok +pclmulqdq_12 ... ok +pclmulqdq_13 ... ok +pclmulqdq_14 ... ok +pclmulqdq_15 ... ok +pclmulqdq_16 ... ok +pclmulqdq_17 ... ok +pclmulqdq_18 ... ok +pclmulqdq_19 ... ok +pclmulqdq_20 ... ok +pclmulqdq_21 ... ok +pclmulqdq_22 ... ok +pclmulqdq_23 ... ok +pclmulqdq_24 ... ok +pclmulqdq_25 ... ok +pclmulqdq_26 ... ok +pclmulqdq_27 ... ok +pclmulqdq_28 ... ok +pclmulqdq_29 ... ok +pclmulqdq_30 ... ok +pclmulqdq_31 ... ok +pclmulqdq_32 ... ok +pclmulqdq_33 ... ok +pclmulqdq_34 ... ok +pclmulqdq_35 ... ok +pclmulqdq_36 ... ok +pclmulqdq_37 ... ok +pclmulqdq_38 ... ok +pclmulqdq_39 ... ok +pclmulqdq_40 ... ok +pclmulqdq_41 ... ok +pclmulqdq_42 ... ok +pclmulqdq_43 ... ok +pclmulqdq_44 ... ok +pclmulqdq_45 ... ok +pclmulqdq_46 ... ok +pclmulqdq_47 ... ok +pclmulqdq_48 ... ok +pclmulqdq_49 ... ok +pclmulqdq_50 ... ok +pclmulqdq_51 ... ok +pclmulqdq_52 ... ok +pclmulqdq_53 ... ok +pclmulqdq_54 ... ok +pclmulqdq_55 ... ok +pclmulqdq_56 ... ok +pclmulqdq_57 ... ok +pclmulqdq_58 ... ok +pclmulqdq_59 ... ok +pclmulqdq_60 ... ok +pclmulqdq_61 ... ok +pclmulqdq_62 ... ok +pclmulqdq_63 ... ok +pclmulqdq_64 ... ok +pclmulqdq_65 ... ok +pclmulqdq_66 ... ok +pclmulqdq_67 ... ok +pclmulqdq_68 ... ok +pclmulqdq_69 ... ok +pclmulqdq_70 ... ok +pclmulqdq_71 ... ok +pclmulqdq_72 ... ok +pclmulqdq_73 ... ok +pclmulqdq_74 ... ok +pclmulqdq_75 ... ok +pclmulqdq_76 ... ok +pclmulqdq_77 ... ok +pclmulqdq_78 ... ok +pclmulqdq_79 ... ok +pclmulqdq_80 ... ok +pclmulqdq_81 ... ok +pclmulqdq_82 ... ok +pclmulqdq_83 ... ok +pclmulqdq_84 ... ok +pclmulqdq_85 ... ok +pclmulqdq_86 ... ok +pclmulqdq_87 ... ok +pclmulqdq_88 ... ok +pclmulqdq_89 ... ok +pclmulqdq_90 ... ok +pclmulqdq_91 ... ok +pclmulqdq_92 ... ok +pclmulqdq_93 ... ok +pclmulqdq_94 ... ok +pclmulqdq_95 ... ok +pclmulqdq_96 ... ok +pclmulqdq_97 ... ok +pclmulqdq_98 ... ok +pclmulqdq_99 ... ok +pclmulqdq_100 ... ok +pclmulqdq_101 ... ok +pclmulqdq_102 ... ok +pclmulqdq_103 ... ok +pclmulqdq_104 ... ok +pclmulqdq_105 ... ok +pclmulqdq_106 ... ok +pclmulqdq_107 ... ok +pclmulqdq_108 ... ok +pclmulqdq_109 ... ok +pclmulqdq_110 ... ok +pclmulqdq_111 ... ok +pclmulqdq_112 ... ok +pclmulqdq_113 ... ok +pclmulqdq_114 ... ok +pclmulqdq_115 ... ok +pclmulqdq_116 ... ok +pclmulqdq_117 ... ok +pclmulqdq_118 ... ok +pclmulqdq_119 ... ok +pclmulqdq_120 ... ok +pclmulqdq_121 ... ok +pclmulqdq_122 ... ok +pclmulqdq_123 ... ok +pclmulqdq_124 ... ok +pclmulqdq_125 ... ok +pclmulqdq_126 ... ok +pclmulqdq_127 ... ok +pclmulqdq_128 ... ok +pclmulqdq_129 ... ok +pclmulqdq_130 ... ok +pclmulqdq_131 ... ok +pclmulqdq_132 ... ok +pclmulqdq_133 ... ok +pclmulqdq_134 ... ok +pclmulqdq_135 ... ok +pclmulqdq_136 ... ok +pclmulqdq_137 ... ok +pclmulqdq_138 ... ok +pclmulqdq_139 ... ok +pclmulqdq_140 ... ok +pclmulqdq_141 ... ok +pclmulqdq_142 ... ok +pclmulqdq_143 ... ok +pclmulqdq_144 ... ok +pclmulqdq_145 ... ok +pclmulqdq_146 ... ok +pclmulqdq_147 ... ok +pclmulqdq_148 ... ok +pclmulqdq_149 ... ok +pclmulqdq_150 ... ok +pclmulqdq_151 ... ok +pclmulqdq_152 ... ok +pclmulqdq_153 ... ok +pclmulqdq_154 ... ok +pclmulqdq_155 ... ok +pclmulqdq_156 ... ok +pclmulqdq_157 ... ok +pclmulqdq_158 ... ok +pclmulqdq_159 ... ok +pclmulqdq_160 ... ok diff --git a/none/tests/amd64/insn_pclmulqdq.vgtest b/none/tests/amd64/insn_pclmulqdq.vgtest new file mode 100644 index 0000000..d40ded1 --- /dev/null +++ b/none/tests/amd64/insn_pclmulqdq.vgtest @@ -0,0 +1,3 @@ +prog: ../../../none/tests/amd64/insn_pclmulqdq +prereq: ../../../tests/x86_amd64_features amd64-pclmulqdq +vgopts: -q diff --git a/none/tests/amd64/lzcnt64.c b/none/tests/amd64/lzcnt64.c new file mode 100644 index 0000000..22fa353 --- /dev/null +++ b/none/tests/amd64/lzcnt64.c @@ -0,0 +1,93 @@ + +#include + +typedef unsigned long long int ULong; +typedef unsigned int UInt; + +__attribute__((noinline)) +void do_lzcnt64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg ) +{ + ULong block[3] = { arg, 0ULL, 0ULL }; + __asm__ __volatile__( + "movabsq $0x5555555555555555, %%r11" "\n\t" + "lzcntq 0(%0), %%r11" "\n\t" + "movq %%r11, 8(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r11" "\n\t" + "movq %%r11, 16(%0)" "\n" + : : "r"(&block[0]) : "r11","cc","memory" + ); + *res = block[1]; + *flags = block[2] & 0x8d5; +} + +__attribute__((noinline)) +void do_lzcnt32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg ) +{ + ULong block[3] = { arg, 0ULL, 0ULL }; + __asm__ __volatile__( + "movabsq $0x5555555555555555, %%r11" "\n\t" + "lzcntl 0(%0), %%r11d" "\n\t" + "movq %%r11, 8(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r11" "\n\t" + "movq %%r11, 16(%0)" "\n" + : : "r"(&block[0]) : "r11","cc","memory" + ); + *res = block[1]; + *flags = block[2] & 0x8d5; +} + +__attribute__((noinline)) +void do_lzcnt16 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg ) +{ + ULong block[3] = { arg, 0ULL, 0ULL }; + __asm__ __volatile__( + "movabsq $0x5555555555555555, %%r11" "\n\t" + "lzcntw 0(%0), %%r11w" "\n\t" + "movq %%r11, 8(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r11" "\n\t" + "movq %%r11, 16(%0)" "\n" + : : "r"(&block[0]) : "r11","cc","memory" + ); + *res = block[1]; + *flags = block[2] & 0x8d5; +} + +int main ( void ) +{ + ULong w; + + w = 0xFEDC192837475675ULL; + while (1) { + ULong res; + UInt flags; + do_lzcnt64(&flags, &res, w); + printf("lzcntq %016llx -> %016llx %04x\n", w, res, flags); + if (w == 0) break; + w = ((w >> 2) | (w >> 1)) + (w / 17ULL); + } + + w = 0xFEDC192837475675ULL; + while (1) { + ULong res; + UInt flags; + do_lzcnt32(&flags, &res, w); + printf("lzcntl %016llx -> %016llx %04x\n", w, res, flags); + if (w == 0) break; + w = ((w >> 2) | (w >> 1)) + (w / 17ULL); + } + + w = 0xFEDC192837475675ULL; + while (1) { + ULong res; + UInt flags; + do_lzcnt16(&flags, &res, w); + printf("lzcntw %016llx -> %016llx %04x\n", w, res, flags); + if (w == 0) break; + w = ((w >> 2) | (w >> 1)) + (w / 17ULL); + } + + return 0; +} diff --git a/none/tests/amd64/lzcnt64.stderr.exp b/none/tests/amd64/lzcnt64.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/amd64/lzcnt64.stdout.exp b/none/tests/amd64/lzcnt64.stdout.exp new file mode 100644 index 0000000..fd73687 --- /dev/null +++ b/none/tests/amd64/lzcnt64.stdout.exp @@ -0,0 +1,375 @@ +lzcntq fedc192837475675 -> 0000000000000000 0040 +lzcntq 8efcf23ad7e922f3 -> 0000000000000000 0040 +lzcntq 7068b90cdf850938 -> 0000000000000001 0000 +lzcntq 42db3e5ed85503a5 -> 0000000000000001 0000 +lzcntq 35eea72efbea67d7 -> 0000000000000002 0000 +lzcntq 232c23d3b476ef47 -> 0000000000000002 0000 +lzcntq 1bf0c1bf27fbb3ab -> 0000000000000003 0000 +lzcntq 11a1311a29a562ea -> 0000000000000003 0000 +lzcntq 0e02582b8350ffd0 -> 0000000000000004 0000 +lzcntq 0854b4408f5b9e17 -> 0000000000000004 0000 +lzcntq 06bcf33434328063 -> 0000000000000005 0000 +lzcntq 0464f596e5f3ab8a -> 0000000000000005 0000 +lzcntq 037dac8063df281c -> 0000000000000006 0000 +lzcntq 0234910d6d0cfe89 -> 0000000000000006 0000 +lzcntq 01c0a27d7eaa2575 -> 0000000000000007 0000 +lzcntq 010adda943af43d8 -> 0000000000000007 0000 +lzcntq 00d7b2ae8c91c8ce -> 0000000000000008 0000 +lzcntq 008cae284a0c2065 -> 0000000000000008 0000 +lzcntq 006fc6190eb4fc04 -> 0000000000000009 0000 +lzcntq 004686bd6e829ce5 -> 0000000000000009 0000 +lzcntq 00380a0b248034f1 -> 000000000000000a 0000 +lzcntq 0021536a650d4fc6 -> 000000000000000a 0000 +lzcntq 001af3d8d0c8c068 -> 000000000000000b 0000 +lzcntq 001193de10460316 -> 000000000000000b 0000 +lzcntq 000df6b241dd45c1 -> 000000000000000c 0000 +lzcntq 0008d24469947f91 -> 000000000000000c 0000 +lzcntq 0007028a17f7fc21 -> 000000000000000d 0000 +lzcntq 00042b77370e9574 -> 000000000000000d 0000 +lzcntq 00035ecaa6c8cb9c -> 000000000000000e 0000 +lzcntq 000232b89c5ca207 -> 000000000000000e 0000 +lzcntq 0001bf185a53fb83 -> 000000000000000f 0000 +lzcntq 00011a1af9c2f08e -> 000000000000000f 0000 +lzcntq 0000e0282bc137ba -> 0000000000000010 0000 +lzcntq 0000854daa0b4caf -> 0000000000000010 0000 +lzcntq 00006bcf63e2fc01 -> 0000000000000011 0000 +lzcntq 0000464f7852a469 -> 0000000000000011 0000 +lzcntq 000037dac915aa8f -> 0000000000000012 0000 +lzcntq 0000234911b3280d -> 0000000000000012 0000 +lzcntq 00001c0a2862c244 -> 0000000000000013 0000 +lzcntq 000010addcd6577a -> 0000000000000013 0000 +lzcntq 00000d7b2a9b6ac9 -> 0000000000000014 0000 +lzcntq 000008cae2719cd4 -> 0000000000000014 0000 +lzcntq 000006fc61694403 -> 0000000000000015 0000 +lzcntq 000004686be70610 -> 0000000000000015 0000 +lzcntq 00000380a0af0023 -> 0000000000000016 0000 +lzcntq 0000021536a82984 -> 0000000000000016 0000 +lzcntq 000001af3d8f8abd -> 0000000000000017 0000 +lzcntq 000001193de14a82 -> 0000000000000017 0000 +lzcntq 000000df6b24569d -> 0000000000000018 0000 +lzcntq 0000008d2446cc8e -> 0000000000000018 0000 +lzcntq 0000007028a18af6 -> 0000000000000019 0000 +lzcntq 00000042b7735995 -> 0000000000000019 0000 +lzcntq 00000035ecaa6d9d -> 000000000000001a 0000 +lzcntq 000000232b89c661 -> 000000000000001a 0000 +lzcntq 0000001bf185a509 -> 000000000000001b 0000 +lzcntq 00000011a1af9c11 -> 000000000000001b 0000 +lzcntq 0000000e0282bbfd -> 000000000000001c 0000 +lzcntq 0000000854daa1a4 -> 000000000000001c 0000 +lzcntq 00000006bcf63eb9 -> 000000000000001d 0000 +lzcntq 0000000464f78590 -> 000000000000001d 0000 +lzcntq 000000037dac916c -> 000000000000001e 0000 +lzcntq 0000000234911b32 -> 000000000000001e 0000 +lzcntq 00000001c0a2862b -> 000000000000001f 0000 +lzcntq 000000010addcd65 -> 000000000000001f 0000 +lzcntq 00000000d7b2a9b5 -> 0000000000000020 0000 +lzcntq 000000008cae2718 -> 0000000000000020 0000 +lzcntq 000000006fc61693 -> 0000000000000021 0000 +lzcntq 000000004686be6e -> 0000000000000021 0000 +lzcntq 00000000380a0af2 -> 0000000000000022 0000 +lzcntq 0000000021536a83 -> 0000000000000022 0000 +lzcntq 000000001af3d8f7 -> 0000000000000023 0000 +lzcntq 000000001193de15 -> 0000000000000023 0000 +lzcntq 000000000df6b244 -> 0000000000000024 0000 +lzcntq 0000000008d2446b -> 0000000000000024 0000 +lzcntq 0000000007028a18 -> 0000000000000025 0000 +lzcntq 00000000042b7735 -> 0000000000000025 0000 +lzcntq 00000000035ecaa5 -> 0000000000000026 0000 +lzcntq 000000000232b89b -> 0000000000000026 0000 +lzcntq 0000000001bf185a -> 0000000000000027 0000 +lzcntq 00000000011a1af9 -> 0000000000000027 0000 +lzcntq 0000000000e0282a -> 0000000000000028 0000 +lzcntq 0000000000854da9 -> 0000000000000028 0000 +lzcntq 00000000006bcf62 -> 0000000000000029 0000 +lzcntq 0000000000464f77 -> 0000000000000029 0000 +lzcntq 000000000037dac9 -> 000000000000002a 0000 +lzcntq 0000000000234910 -> 000000000000002a 0000 +lzcntq 00000000001c0a27 -> 000000000000002b 0000 +lzcntq 000000000010add9 -> 000000000000002b 0000 +lzcntq 00000000000d7b28 -> 000000000000002c 0000 +lzcntq 000000000008cae0 -> 000000000000002c 0000 +lzcntq 000000000006fc5f -> 000000000000002d 0000 +lzcntq 0000000000046871 -> 000000000000002d 0000 +lzcntq 000000000003809d -> 000000000000002e 0000 +lzcntq 000000000002152c -> 000000000000002e 0000 +lzcntq 000000000001af3b -> 000000000000002f 0000 +lzcntq 000000000001193c -> 000000000000002f 0000 +lzcntq 000000000000df6a -> 0000000000000030 0000 +lzcntq 0000000000008d23 -> 0000000000000030 0000 +lzcntq 0000000000007026 -> 0000000000000031 0000 +lzcntq 00000000000042b3 -> 0000000000000031 0000 +lzcntq 00000000000035e9 -> 0000000000000032 0000 +lzcntq 0000000000002329 -> 0000000000000032 0000 +lzcntq 0000000000001bef -> 0000000000000033 0000 +lzcntq 00000000000011a3 -> 0000000000000033 0000 +lzcntq 0000000000000e02 -> 0000000000000034 0000 +lzcntq 0000000000000853 -> 0000000000000034 0000 +lzcntq 00000000000006ba -> 0000000000000035 0000 +lzcntq 0000000000000464 -> 0000000000000035 0000 +lzcntq 000000000000037d -> 0000000000000036 0000 +lzcntq 0000000000000233 -> 0000000000000036 0000 +lzcntq 00000000000001be -> 0000000000000037 0000 +lzcntq 0000000000000119 -> 0000000000000037 0000 +lzcntq 00000000000000de -> 0000000000000038 0000 +lzcntq 000000000000008c -> 0000000000000038 0000 +lzcntq 000000000000006f -> 0000000000000039 0000 +lzcntq 0000000000000045 -> 0000000000000039 0000 +lzcntq 0000000000000037 -> 000000000000003a 0000 +lzcntq 0000000000000022 -> 000000000000003a 0000 +lzcntq 000000000000001b -> 000000000000003b 0000 +lzcntq 0000000000000010 -> 000000000000003b 0000 +lzcntq 000000000000000c -> 000000000000003c 0000 +lzcntq 0000000000000007 -> 000000000000003d 0000 +lzcntq 0000000000000003 -> 000000000000003e 0000 +lzcntq 0000000000000001 -> 000000000000003f 0000 +lzcntq 0000000000000000 -> 0000000000000040 0001 +lzcntl fedc192837475675 -> 0000000000000002 0000 +lzcntl 8efcf23ad7e922f3 -> 0000000000000000 0040 +lzcntl 7068b90cdf850938 -> 0000000000000000 0040 +lzcntl 42db3e5ed85503a5 -> 0000000000000000 0040 +lzcntl 35eea72efbea67d7 -> 0000000000000000 0040 +lzcntl 232c23d3b476ef47 -> 0000000000000000 0040 +lzcntl 1bf0c1bf27fbb3ab -> 0000000000000002 0000 +lzcntl 11a1311a29a562ea -> 0000000000000002 0000 +lzcntl 0e02582b8350ffd0 -> 0000000000000000 0040 +lzcntl 0854b4408f5b9e17 -> 0000000000000000 0040 +lzcntl 06bcf33434328063 -> 0000000000000002 0000 +lzcntl 0464f596e5f3ab8a -> 0000000000000000 0040 +lzcntl 037dac8063df281c -> 0000000000000001 0000 +lzcntl 0234910d6d0cfe89 -> 0000000000000001 0000 +lzcntl 01c0a27d7eaa2575 -> 0000000000000001 0000 +lzcntl 010adda943af43d8 -> 0000000000000001 0000 +lzcntl 00d7b2ae8c91c8ce -> 0000000000000000 0040 +lzcntl 008cae284a0c2065 -> 0000000000000001 0000 +lzcntl 006fc6190eb4fc04 -> 0000000000000004 0000 +lzcntl 004686bd6e829ce5 -> 0000000000000001 0000 +lzcntl 00380a0b248034f1 -> 0000000000000002 0000 +lzcntl 0021536a650d4fc6 -> 0000000000000001 0000 +lzcntl 001af3d8d0c8c068 -> 0000000000000000 0040 +lzcntl 001193de10460316 -> 0000000000000003 0000 +lzcntl 000df6b241dd45c1 -> 0000000000000001 0000 +lzcntl 0008d24469947f91 -> 0000000000000001 0000 +lzcntl 0007028a17f7fc21 -> 0000000000000003 0000 +lzcntl 00042b77370e9574 -> 0000000000000002 0000 +lzcntl 00035ecaa6c8cb9c -> 0000000000000000 0040 +lzcntl 000232b89c5ca207 -> 0000000000000000 0040 +lzcntl 0001bf185a53fb83 -> 0000000000000001 0000 +lzcntl 00011a1af9c2f08e -> 0000000000000000 0040 +lzcntl 0000e0282bc137ba -> 0000000000000002 0000 +lzcntl 0000854daa0b4caf -> 0000000000000000 0040 +lzcntl 00006bcf63e2fc01 -> 0000000000000001 0000 +lzcntl 0000464f7852a469 -> 0000000000000001 0000 +lzcntl 000037dac915aa8f -> 0000000000000000 0040 +lzcntl 0000234911b3280d -> 0000000000000003 0000 +lzcntl 00001c0a2862c244 -> 0000000000000002 0000 +lzcntl 000010addcd6577a -> 0000000000000000 0040 +lzcntl 00000d7b2a9b6ac9 -> 0000000000000002 0000 +lzcntl 000008cae2719cd4 -> 0000000000000000 0040 +lzcntl 000006fc61694403 -> 0000000000000001 0000 +lzcntl 000004686be70610 -> 0000000000000001 0000 +lzcntl 00000380a0af0023 -> 0000000000000000 0040 +lzcntl 0000021536a82984 -> 0000000000000002 0000 +lzcntl 000001af3d8f8abd -> 0000000000000002 0000 +lzcntl 000001193de14a82 -> 0000000000000002 0000 +lzcntl 000000df6b24569d -> 0000000000000001 0000 +lzcntl 0000008d2446cc8e -> 0000000000000002 0000 +lzcntl 0000007028a18af6 -> 0000000000000002 0000 +lzcntl 00000042b7735995 -> 0000000000000000 0040 +lzcntl 00000035ecaa6d9d -> 0000000000000000 0040 +lzcntl 000000232b89c661 -> 0000000000000002 0000 +lzcntl 0000001bf185a509 -> 0000000000000000 0040 +lzcntl 00000011a1af9c11 -> 0000000000000000 0040 +lzcntl 0000000e0282bbfd -> 0000000000000006 0000 +lzcntl 0000000854daa1a4 -> 0000000000000001 0000 +lzcntl 00000006bcf63eb9 -> 0000000000000000 0040 +lzcntl 0000000464f78590 -> 0000000000000001 0000 +lzcntl 000000037dac916c -> 0000000000000001 0000 +lzcntl 0000000234911b32 -> 0000000000000002 0000 +lzcntl 00000001c0a2862b -> 0000000000000000 0040 +lzcntl 000000010addcd65 -> 0000000000000004 0000 +lzcntl 00000000d7b2a9b5 -> 0000000000000000 0040 +lzcntl 000000008cae2718 -> 0000000000000000 0040 +lzcntl 000000006fc61693 -> 0000000000000001 0000 +lzcntl 000000004686be6e -> 0000000000000001 0000 +lzcntl 00000000380a0af2 -> 0000000000000002 0000 +lzcntl 0000000021536a83 -> 0000000000000002 0000 +lzcntl 000000001af3d8f7 -> 0000000000000003 0000 +lzcntl 000000001193de15 -> 0000000000000003 0000 +lzcntl 000000000df6b244 -> 0000000000000004 0000 +lzcntl 0000000008d2446b -> 0000000000000004 0000 +lzcntl 0000000007028a18 -> 0000000000000005 0000 +lzcntl 00000000042b7735 -> 0000000000000005 0000 +lzcntl 00000000035ecaa5 -> 0000000000000006 0000 +lzcntl 000000000232b89b -> 0000000000000006 0000 +lzcntl 0000000001bf185a -> 0000000000000007 0000 +lzcntl 00000000011a1af9 -> 0000000000000007 0000 +lzcntl 0000000000e0282a -> 0000000000000008 0000 +lzcntl 0000000000854da9 -> 0000000000000008 0000 +lzcntl 00000000006bcf62 -> 0000000000000009 0000 +lzcntl 0000000000464f77 -> 0000000000000009 0000 +lzcntl 000000000037dac9 -> 000000000000000a 0000 +lzcntl 0000000000234910 -> 000000000000000a 0000 +lzcntl 00000000001c0a27 -> 000000000000000b 0000 +lzcntl 000000000010add9 -> 000000000000000b 0000 +lzcntl 00000000000d7b28 -> 000000000000000c 0000 +lzcntl 000000000008cae0 -> 000000000000000c 0000 +lzcntl 000000000006fc5f -> 000000000000000d 0000 +lzcntl 0000000000046871 -> 000000000000000d 0000 +lzcntl 000000000003809d -> 000000000000000e 0000 +lzcntl 000000000002152c -> 000000000000000e 0000 +lzcntl 000000000001af3b -> 000000000000000f 0000 +lzcntl 000000000001193c -> 000000000000000f 0000 +lzcntl 000000000000df6a -> 0000000000000010 0000 +lzcntl 0000000000008d23 -> 0000000000000010 0000 +lzcntl 0000000000007026 -> 0000000000000011 0000 +lzcntl 00000000000042b3 -> 0000000000000011 0000 +lzcntl 00000000000035e9 -> 0000000000000012 0000 +lzcntl 0000000000002329 -> 0000000000000012 0000 +lzcntl 0000000000001bef -> 0000000000000013 0000 +lzcntl 00000000000011a3 -> 0000000000000013 0000 +lzcntl 0000000000000e02 -> 0000000000000014 0000 +lzcntl 0000000000000853 -> 0000000000000014 0000 +lzcntl 00000000000006ba -> 0000000000000015 0000 +lzcntl 0000000000000464 -> 0000000000000015 0000 +lzcntl 000000000000037d -> 0000000000000016 0000 +lzcntl 0000000000000233 -> 0000000000000016 0000 +lzcntl 00000000000001be -> 0000000000000017 0000 +lzcntl 0000000000000119 -> 0000000000000017 0000 +lzcntl 00000000000000de -> 0000000000000018 0000 +lzcntl 000000000000008c -> 0000000000000018 0000 +lzcntl 000000000000006f -> 0000000000000019 0000 +lzcntl 0000000000000045 -> 0000000000000019 0000 +lzcntl 0000000000000037 -> 000000000000001a 0000 +lzcntl 0000000000000022 -> 000000000000001a 0000 +lzcntl 000000000000001b -> 000000000000001b 0000 +lzcntl 0000000000000010 -> 000000000000001b 0000 +lzcntl 000000000000000c -> 000000000000001c 0000 +lzcntl 0000000000000007 -> 000000000000001d 0000 +lzcntl 0000000000000003 -> 000000000000001e 0000 +lzcntl 0000000000000001 -> 000000000000001f 0000 +lzcntl 0000000000000000 -> 0000000000000020 0001 +lzcntw fedc192837475675 -> 5555555555550001 0000 +lzcntw 8efcf23ad7e922f3 -> 5555555555550002 0000 +lzcntw 7068b90cdf850938 -> 5555555555550004 0000 +lzcntw 42db3e5ed85503a5 -> 5555555555550006 0000 +lzcntw 35eea72efbea67d7 -> 5555555555550001 0000 +lzcntw 232c23d3b476ef47 -> 5555555555550000 0040 +lzcntw 1bf0c1bf27fbb3ab -> 5555555555550000 0040 +lzcntw 11a1311a29a562ea -> 5555555555550001 0000 +lzcntw 0e02582b8350ffd0 -> 5555555555550000 0040 +lzcntw 0854b4408f5b9e17 -> 5555555555550000 0040 +lzcntw 06bcf33434328063 -> 5555555555550000 0040 +lzcntw 0464f596e5f3ab8a -> 5555555555550000 0040 +lzcntw 037dac8063df281c -> 5555555555550002 0000 +lzcntw 0234910d6d0cfe89 -> 5555555555550000 0040 +lzcntw 01c0a27d7eaa2575 -> 5555555555550002 0000 +lzcntw 010adda943af43d8 -> 5555555555550001 0000 +lzcntw 00d7b2ae8c91c8ce -> 5555555555550000 0040 +lzcntw 008cae284a0c2065 -> 5555555555550002 0000 +lzcntw 006fc6190eb4fc04 -> 5555555555550000 0040 +lzcntw 004686bd6e829ce5 -> 5555555555550000 0040 +lzcntw 00380a0b248034f1 -> 5555555555550002 0000 +lzcntw 0021536a650d4fc6 -> 5555555555550001 0000 +lzcntw 001af3d8d0c8c068 -> 5555555555550000 0040 +lzcntw 001193de10460316 -> 5555555555550006 0000 +lzcntw 000df6b241dd45c1 -> 5555555555550001 0000 +lzcntw 0008d24469947f91 -> 5555555555550001 0000 +lzcntw 0007028a17f7fc21 -> 5555555555550000 0040 +lzcntw 00042b77370e9574 -> 5555555555550000 0040 +lzcntw 00035ecaa6c8cb9c -> 5555555555550000 0040 +lzcntw 000232b89c5ca207 -> 5555555555550000 0040 +lzcntw 0001bf185a53fb83 -> 5555555555550000 0040 +lzcntw 00011a1af9c2f08e -> 5555555555550000 0040 +lzcntw 0000e0282bc137ba -> 5555555555550002 0000 +lzcntw 0000854daa0b4caf -> 5555555555550001 0000 +lzcntw 00006bcf63e2fc01 -> 5555555555550000 0040 +lzcntw 0000464f7852a469 -> 5555555555550000 0040 +lzcntw 000037dac915aa8f -> 5555555555550000 0040 +lzcntw 0000234911b3280d -> 5555555555550002 0000 +lzcntw 00001c0a2862c244 -> 5555555555550000 0040 +lzcntw 000010addcd6577a -> 5555555555550001 0000 +lzcntw 00000d7b2a9b6ac9 -> 5555555555550001 0000 +lzcntw 000008cae2719cd4 -> 5555555555550000 0040 +lzcntw 000006fc61694403 -> 5555555555550001 0000 +lzcntw 000004686be70610 -> 5555555555550005 0000 +lzcntw 00000380a0af0023 -> 555555555555000a 0000 +lzcntw 0000021536a82984 -> 5555555555550002 0000 +lzcntw 000001af3d8f8abd -> 5555555555550000 0040 +lzcntw 000001193de14a82 -> 5555555555550001 0000 +lzcntw 000000df6b24569d -> 5555555555550001 0000 +lzcntw 0000008d2446cc8e -> 5555555555550000 0040 +lzcntw 0000007028a18af6 -> 5555555555550000 0040 +lzcntw 00000042b7735995 -> 5555555555550001 0000 +lzcntw 00000035ecaa6d9d -> 5555555555550001 0000 +lzcntw 000000232b89c661 -> 5555555555550000 0040 +lzcntw 0000001bf185a509 -> 5555555555550000 0040 +lzcntw 00000011a1af9c11 -> 5555555555550000 0040 +lzcntw 0000000e0282bbfd -> 5555555555550000 0040 +lzcntw 0000000854daa1a4 -> 5555555555550000 0040 +lzcntw 00000006bcf63eb9 -> 5555555555550002 0000 +lzcntw 0000000464f78590 -> 5555555555550000 0040 +lzcntw 000000037dac916c -> 5555555555550000 0040 +lzcntw 0000000234911b32 -> 5555555555550003 0000 +lzcntw 00000001c0a2862b -> 5555555555550000 0040 +lzcntw 000000010addcd65 -> 5555555555550000 0040 +lzcntw 00000000d7b2a9b5 -> 5555555555550000 0040 +lzcntw 000000008cae2718 -> 5555555555550002 0000 +lzcntw 000000006fc61693 -> 5555555555550003 0000 +lzcntw 000000004686be6e -> 5555555555550000 0040 +lzcntw 00000000380a0af2 -> 5555555555550004 0000 +lzcntw 0000000021536a83 -> 5555555555550001 0000 +lzcntw 000000001af3d8f7 -> 5555555555550000 0040 +lzcntw 000000001193de15 -> 5555555555550000 0040 +lzcntw 000000000df6b244 -> 5555555555550000 0040 +lzcntw 0000000008d2446b -> 5555555555550001 0000 +lzcntw 0000000007028a18 -> 5555555555550000 0040 +lzcntw 00000000042b7735 -> 5555555555550001 0000 +lzcntw 00000000035ecaa5 -> 5555555555550000 0040 +lzcntw 000000000232b89b -> 5555555555550000 0040 +lzcntw 0000000001bf185a -> 5555555555550003 0000 +lzcntw 00000000011a1af9 -> 5555555555550003 0000 +lzcntw 0000000000e0282a -> 5555555555550002 0000 +lzcntw 0000000000854da9 -> 5555555555550001 0000 +lzcntw 00000000006bcf62 -> 5555555555550000 0040 +lzcntw 0000000000464f77 -> 5555555555550001 0000 +lzcntw 000000000037dac9 -> 5555555555550000 0040 +lzcntw 0000000000234910 -> 5555555555550001 0000 +lzcntw 00000000001c0a27 -> 5555555555550004 0000 +lzcntw 000000000010add9 -> 5555555555550000 0040 +lzcntw 00000000000d7b28 -> 5555555555550001 0000 +lzcntw 000000000008cae0 -> 5555555555550000 0040 +lzcntw 000000000006fc5f -> 5555555555550000 0040 +lzcntw 0000000000046871 -> 5555555555550001 0000 +lzcntw 000000000003809d -> 5555555555550000 0040 +lzcntw 000000000002152c -> 5555555555550003 0000 +lzcntw 000000000001af3b -> 5555555555550000 0040 +lzcntw 000000000001193c -> 5555555555550003 0000 +lzcntw 000000000000df6a -> 5555555555550000 0040 +lzcntw 0000000000008d23 -> 5555555555550000 0040 +lzcntw 0000000000007026 -> 5555555555550001 0000 +lzcntw 00000000000042b3 -> 5555555555550001 0000 +lzcntw 00000000000035e9 -> 5555555555550002 0000 +lzcntw 0000000000002329 -> 5555555555550002 0000 +lzcntw 0000000000001bef -> 5555555555550003 0000 +lzcntw 00000000000011a3 -> 5555555555550003 0000 +lzcntw 0000000000000e02 -> 5555555555550004 0000 +lzcntw 0000000000000853 -> 5555555555550004 0000 +lzcntw 00000000000006ba -> 5555555555550005 0000 +lzcntw 0000000000000464 -> 5555555555550005 0000 +lzcntw 000000000000037d -> 5555555555550006 0000 +lzcntw 0000000000000233 -> 5555555555550006 0000 +lzcntw 00000000000001be -> 5555555555550007 0000 +lzcntw 0000000000000119 -> 5555555555550007 0000 +lzcntw 00000000000000de -> 5555555555550008 0000 +lzcntw 000000000000008c -> 5555555555550008 0000 +lzcntw 000000000000006f -> 5555555555550009 0000 +lzcntw 0000000000000045 -> 5555555555550009 0000 +lzcntw 0000000000000037 -> 555555555555000a 0000 +lzcntw 0000000000000022 -> 555555555555000a 0000 +lzcntw 000000000000001b -> 555555555555000b 0000 +lzcntw 0000000000000010 -> 555555555555000b 0000 +lzcntw 000000000000000c -> 555555555555000c 0000 +lzcntw 0000000000000007 -> 555555555555000d 0000 +lzcntw 0000000000000003 -> 555555555555000e 0000 +lzcntw 0000000000000001 -> 555555555555000f 0000 +lzcntw 0000000000000000 -> 5555555555550010 0001 diff --git a/none/tests/amd64/lzcnt64.vgtest b/none/tests/amd64/lzcnt64.vgtest new file mode 100644 index 0000000..74d82b5 --- /dev/null +++ b/none/tests/amd64/lzcnt64.vgtest @@ -0,0 +1,3 @@ +prog: lzcnt64 +prereq: ../../../tests/x86_amd64_features amd64-lzcnt +vgopts: -q diff --git a/none/tests/amd64/pcmpstr64.c b/none/tests/amd64/pcmpstr64.c new file mode 100644 index 0000000..c655ffb --- /dev/null +++ b/none/tests/amd64/pcmpstr64.c @@ -0,0 +1,1095 @@ + +/* Tests in detail the core arithmetic for pcmp{e,i}str{i,m} using + pcmpistri to drive it. Does not check the e-vs-i or i-vs-m + aspect. */ + +#include +#include +#include + +typedef unsigned int UInt; +typedef signed int Int; +typedef unsigned char UChar; +typedef unsigned long long int ULong; +typedef UChar Bool; +#define False ((Bool)0) +#define True ((Bool)1) + +//typedef unsigned char V128[16]; +typedef + union { + UChar uChar[16]; + UInt uInt[4]; + } + V128; + +#define SHIFT_O 11 +#define SHIFT_S 7 +#define SHIFT_Z 6 +#define SHIFT_A 4 +#define SHIFT_C 0 +#define SHIFT_P 2 + +#define MASK_O (1ULL << SHIFT_O) +#define MASK_S (1ULL << SHIFT_S) +#define MASK_Z (1ULL << SHIFT_Z) +#define MASK_A (1ULL << SHIFT_A) +#define MASK_C (1ULL << SHIFT_C) +#define MASK_P (1ULL << SHIFT_P) + + +UInt clz32 ( UInt x ) +{ + Int y, m, n; + y = -(x >> 16); + m = (y >> 16) & 16; + n = 16 - m; + x = x >> m; + y = x - 0x100; + m = (y >> 16) & 8; + n = n + m; + x = x << m; + y = x - 0x1000; + m = (y >> 16) & 4; + n = n + m; + x = x << m; + y = x - 0x4000; + m = (y >> 16) & 2; + n = n + m; + x = x << m; + y = x >> 14; + m = y & ~(y >> 1); + return n + 2 - m; +} + +UInt ctz32 ( UInt x ) +{ + return 32 - clz32((~x) & (x-1)); +} + +void expand ( V128* dst, char* summary ) +{ + Int i; + assert( strlen(summary) == 16 ); + for (i = 0; i < 16; i++) { + UChar xx = 0; + UChar x = summary[15-i]; + if (x >= '0' && x <= '9') { xx = x - '0'; } + else if (x >= 'A' && x <= 'F') { xx = x - 'A' + 10; } + else if (x >= 'a' && x <= 'f') { xx = x - 'a' + 10; } + else assert(0); + + assert(xx < 16); + xx = (xx << 4) | xx; + assert(xx < 256); + dst->uChar[i] = xx; + } +} + +void try_istri ( char* which, + UInt(*h_fn)(V128*,V128*), + UInt(*s_fn)(V128*,V128*), + char* summL, char* summR ) +{ + assert(strlen(which) == 2); + V128 argL, argR; + expand(&argL, summL); + expand(&argR, summR); + UInt h_res = h_fn(&argL, &argR); + UInt s_res = s_fn(&argL, &argR); + printf("istri %s %s %s -> %08x %08x %s\n", + which, summL, summR, h_res, s_res, h_res == s_res ? "" : "!!!!"); +} + +UInt zmask_from_V128 ( V128* arg ) +{ + UInt i, res = 0; + for (i = 0; i < 16; i++) { + res |= ((arg->uChar[i] == 0) ? 1 : 0) << i; + } + return res; +} + +////////////////////////////////////////////////////////// +// // +// GENERAL // +// // +////////////////////////////////////////////////////////// + + +/* Given partial results from a pcmpXstrX operation (intRes1, + basically), generate an I format (index value for ECX) output, and + also the new OSZACP flags. +*/ +static +void pcmpXstrX_WRK_gen_output_fmt_I(/*OUT*/V128* resV, + /*OUT*/UInt* resOSZACP, + UInt intRes1, + UInt zmaskL, UInt zmaskR, + UInt validL, + UInt pol, UInt idx ) +{ + assert((pol >> 2) == 0); + assert((idx >> 1) == 0); + + UInt intRes2 = 0; + switch (pol) { + case 0: intRes2 = intRes1; break; // pol + + case 1: intRes2 = ~intRes1; break; // pol - + case 2: intRes2 = intRes1; break; // pol m+ + case 3: intRes2 = intRes1 ^ validL; break; // pol m- + } + intRes2 &= 0xFFFF; + + // generate ecx value + UInt newECX = 0; + if (idx) { + // index of ms-1-bit + newECX = intRes2 == 0 ? 16 : (31 - clz32(intRes2)); + } else { + // index of ls-1-bit + newECX = intRes2 == 0 ? 16 : ctz32(intRes2); + } + + *(UInt*)(&resV[0]) = newECX; + + // generate new flags, common to all ISTRI and ISTRM cases + *resOSZACP // A, P are zero + = ((intRes2 == 0) ? 0 : MASK_C) // C == 0 iff intRes2 == 0 + | ((zmaskL == 0) ? 0 : MASK_Z) // Z == 1 iff any in argL is 0 + | ((zmaskR == 0) ? 0 : MASK_S) // S == 1 iff any in argR is 0 + | ((intRes2 & 1) << SHIFT_O); // O == IntRes2[0] +} + + +/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M} + variants. + + For xSTRI variants, the new ECX value is placed in the 32 bits + pointed to by *resV. For xSTRM variants, the result is a 128 bit + value and is placed at *resV in the obvious way. + + For all variants, the new OSZACP value is placed at *resOSZACP. + + argLV and argRV are the vector args. The caller must prepare a + 16-bit mask for each, zmaskL and zmaskR. For ISTRx variants this + must be 1 for each zero byte of of the respective arg. For ESTRx + variants this is derived from the explicit length indication, and + must be 0 in all places except at the bit index corresponding to + the valid length (0 .. 16). If the valid length is 16 then the + mask must be all zeroes. In all cases, bits 31:16 must be zero. + + imm8 is the original immediate from the instruction. isSTRM + indicates whether this is a xSTRM or xSTRI variant, which controls + how much of *res is written. + + If the given imm8 case can be handled, the return value is True. + If not, False is returned, and neither *res not *resOSZACP are + altered. +*/ + +Bool pcmpXstrX_WRK ( /*OUT*/V128* resV, + /*OUT*/UInt* resOSZACP, + V128* argLV, V128* argRV, + UInt zmaskL, UInt zmaskR, + UInt imm8, Bool isSTRM ) +{ + assert(imm8 < 0x80); + assert((zmaskL >> 16) == 0); + assert((zmaskR >> 16) == 0); + + /* Explicitly reject any imm8 values that haven't been validated, + even if they would probably work. Life is too short to have + unvalidated cases in the code base. */ + switch (imm8) { + case 0x02: case 0x08: case 0x0C: case 0x12: case 0x1A: + case 0x3A: case 0x44: case 0x4A: + break; + default: + return False; + } + + UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format + UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation fn + UInt pol = (imm8 >> 4) & 3; // imm8[5:4] polarity + UInt idx = (imm8 >> 6) & 1; // imm8[6] 1==msb/bytemask + + /*----------------------------------------*/ + /*-- strcmp on byte data --*/ + /*----------------------------------------*/ + + if (agg == 2/*equal each, aka strcmp*/ + && (fmt == 0/*ub*/ || fmt == 2/*sb*/) + && !isSTRM) { + Int i; + UChar* argL = (UChar*)argLV; + UChar* argR = (UChar*)argRV; + UInt boolResII = 0; + for (i = 15; i >= 0; i--) { + UChar cL = argL[i]; + UChar cR = argR[i]; + boolResII = (boolResII << 1) | (cL == cR ? 1 : 0); + } + UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL)) + UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR)) + + // do invalidation, common to all equal-each cases + UInt intRes1 + = (boolResII & validL & validR) // if both valid, use cmpres + | (~ (validL | validR)); // if both invalid, force 1 + // else force 0 + intRes1 &= 0xFFFF; + + // generate I-format output + pcmpXstrX_WRK_gen_output_fmt_I( + resV, resOSZACP, + intRes1, zmaskL, zmaskR, validL, pol, idx + ); + + return True; + } + + /*----------------------------------------*/ + /*-- set membership on byte data --*/ + /*----------------------------------------*/ + + if (agg == 0/*equal any, aka find chars in a set*/ + && (fmt == 0/*ub*/ || fmt == 2/*sb*/) + && !isSTRM) { + /* argL: the string, argR: charset */ + UInt si, ci; + UChar* argL = (UChar*)argLV; + UChar* argR = (UChar*)argRV; + UInt boolRes = 0; + UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL)) + UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR)) + + for (si = 0; si < 16; si++) { + if ((validL & (1 << si)) == 0) + // run off the end of the string. + break; + UInt m = 0; + for (ci = 0; ci < 16; ci++) { + if ((validR & (1 << ci)) == 0) break; + if (argR[ci] == argL[si]) { m = 1; break; } + } + boolRes |= (m << si); + } + + // boolRes is "pre-invalidated" + UInt intRes1 = boolRes & 0xFFFF; + + // generate I-format output + pcmpXstrX_WRK_gen_output_fmt_I( + resV, resOSZACP, + intRes1, zmaskL, zmaskR, validL, pol, idx + ); + + return True; + } + + /*----------------------------------------*/ + /*-- substring search on byte data --*/ + /*----------------------------------------*/ + + if (agg == 3/*equal ordered, aka substring search*/ + && (fmt == 0/*ub*/ || fmt == 2/*sb*/) + && !isSTRM) { + + /* argL: haystack, argR: needle */ + UInt ni, hi; + UChar* argL = (UChar*)argLV; + UChar* argR = (UChar*)argRV; + UInt boolRes = 0; + UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL)) + UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR)) + for (hi = 0; hi < 16; hi++) { + if ((validL & (1 << hi)) == 0) + // run off the end of the haystack + break; + UInt m = 1; + for (ni = 0; ni < 16; ni++) { + if ((validR & (1 << ni)) == 0) break; + UInt i = ni + hi; + if (i >= 16) break; + if (argL[i] != argR[ni]) { m = 0; break; } + } + boolRes |= (m << hi); + } + + // boolRes is "pre-invalidated" + UInt intRes1 = boolRes & 0xFFFF; + + // generate I-format output + pcmpXstrX_WRK_gen_output_fmt_I( + resV, resOSZACP, + intRes1, zmaskL, zmaskR, validL, pol, idx + ); + + return True; + } + + /*----------------------------------------*/ + /*-- ranges, unsigned byte data --*/ + /*----------------------------------------*/ + + if (agg == 1/*ranges*/ + && fmt == 0/*ub*/ + && !isSTRM) { + + /* argL: string, argR: range-pairs */ + UInt ri, si; + UChar* argL = (UChar*)argLV; + UChar* argR = (UChar*)argRV; + UInt boolRes = 0; + UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL)) + UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR)) + for (si = 0; si < 16; si++) { + if ((validL & (1 << si)) == 0) + // run off the end of the string + break; + UInt m = 0; + for (ri = 0; ri < 16; ri += 2) { + if ((validR & (3 << ri)) != (3 << ri)) break; + if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) { + m = 1; break; + } + } + boolRes |= (m << si); + } + + // boolRes is "pre-invalidated" + UInt intRes1 = boolRes & 0xFFFF; + + // generate I-format output + pcmpXstrX_WRK_gen_output_fmt_I( + resV, resOSZACP, + intRes1, zmaskL, zmaskR, validL, pol, idx + ); + + return True; + } + + return False; +} + + +////////////////////////////////////////////////////////// +// // +// ISTRI_4A // +// // +////////////////////////////////////////////////////////// + +UInt h_pcmpistri_4A ( V128* argL, V128* argR ) +{ + V128 block[2]; + memcpy(&block[0], argL, sizeof(V128)); + memcpy(&block[1], argR, sizeof(V128)); + ULong res, flags; + __asm__ __volatile__( + "subq $1024, %%rsp" "\n\t" + "movdqu 0(%2), %%xmm2" "\n\t" + "movdqu 16(%2), %%xmm11" "\n\t" + "pcmpistri $0x4A, %%xmm2, %%xmm11" "\n\t" + "pushfq" "\n\t" + "popq %%rdx" "\n\t" + "movq %%rcx, %0" "\n\t" + "movq %%rdx, %1" "\n\t" + "addq $1024, %%rsp" "\n\t" + : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0]) + : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory" + ); + return ((flags & 0x8D5) << 16) | (res & 0xFFFF); +} + +UInt s_pcmpistri_4A ( V128* argLU, V128* argRU ) +{ + V128 resV; + UInt resOSZACP, resECX; + Bool ok + = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU, + zmask_from_V128(argLU), + zmask_from_V128(argRU), + 0x4A, False/*!isSTRM*/ + ); + assert(ok); + resECX = resV.uInt[0]; + return (resOSZACP << 16) | resECX; +} + +void istri_4A ( void ) +{ + char* wot = "4A"; + UInt(*h)(V128*,V128*) = h_pcmpistri_4A; + UInt(*s)(V128*,V128*) = s_pcmpistri_4A; + + try_istri(wot,h,s, "0000000000000000", "0000000000000000"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa"); + + try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); + try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa"); + + try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa"); + + try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000"); +} + +////////////////////////////////////////////////////////// +// // +// ISTRI_3A // +// // +////////////////////////////////////////////////////////// + +UInt h_pcmpistri_3A ( V128* argL, V128* argR ) +{ + V128 block[2]; + memcpy(&block[0], argL, sizeof(V128)); + memcpy(&block[1], argR, sizeof(V128)); + ULong res, flags; + __asm__ __volatile__( + "subq $1024, %%rsp" "\n\t" + "movdqu 0(%2), %%xmm2" "\n\t" + "movdqu 16(%2), %%xmm11" "\n\t" + "pcmpistri $0x3A, %%xmm2, %%xmm11" "\n\t" + "pushfq" "\n\t" + "popq %%rdx" "\n\t" + "movq %%rcx, %0" "\n\t" + "movq %%rdx, %1" "\n\t" + "addq $1024, %%rsp" "\n\t" + : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0]) + : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory" + ); + return ((flags & 0x8D5) << 16) | (res & 0xFFFF); +} + +UInt s_pcmpistri_3A ( V128* argLU, V128* argRU ) +{ + V128 resV; + UInt resOSZACP, resECX; + Bool ok + = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU, + zmask_from_V128(argLU), + zmask_from_V128(argRU), + 0x3A, False/*!isSTRM*/ + ); + assert(ok); + resECX = resV.uInt[0]; + return (resOSZACP << 16) | resECX; +} + +void istri_3A ( void ) +{ + char* wot = "3A"; + UInt(*h)(V128*,V128*) = h_pcmpistri_3A; + UInt(*s)(V128*,V128*) = s_pcmpistri_3A; + + try_istri(wot,h,s, "0000000000000000", "0000000000000000"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa"); + + try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); + try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa"); + + try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa"); + + try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000"); +} + + + +////////////////////////////////////////////////////////// +// // +// ISTRI_0C // +// // +////////////////////////////////////////////////////////// + +__attribute__((noinline)) +UInt h_pcmpistri_0C ( V128* argL, V128* argR ) +{ + V128 block[2]; + memcpy(&block[0], argL, sizeof(V128)); + memcpy(&block[1], argR, sizeof(V128)); + ULong res = 0, flags = 0; + __asm__ __volatile__( + "movdqa 0(%2), %%xmm2" "\n\t" + "movdqa 16(%2), %%xmm11" "\n\t" + "pcmpistri $0x0C, %%xmm2, %%xmm11" "\n\t" + //"pcmpistrm $0x0C, %%xmm2, %%xmm11" "\n\t" + //"movd %%xmm0, %%ecx" "\n\t" + "pushfq" "\n\t" + "popq %%rdx" "\n\t" + "movq %%rcx, %0" "\n\t" + "movq %%rdx, %1" "\n\t" + : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0]) + : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory" + ); + return ((flags & 0x8D5) << 16) | (res & 0xFFFF); +} + +UInt s_pcmpistri_0C ( V128* argLU, V128* argRU ) +{ + V128 resV; + UInt resOSZACP, resECX; + Bool ok + = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU, + zmask_from_V128(argLU), + zmask_from_V128(argRU), + 0x0C, False/*!isSTRM*/ + ); + assert(ok); + resECX = resV.uInt[0]; + return (resOSZACP << 16) | resECX; +} + +void istri_0C ( void ) +{ + char* wot = "0C"; + UInt(*h)(V128*,V128*) = h_pcmpistri_0C; + UInt(*s)(V128*,V128*) = s_pcmpistri_0C; + + try_istri(wot,h,s, "111111111abcde11", "00000000000abcde"); + + try_istri(wot,h,s, "111111111abcde11", "0000abcde00abcde"); + + try_istri(wot,h,s, "1111111111abcde1", "00000000000abcde"); + try_istri(wot,h,s, "11111111111abcde", "00000000000abcde"); + try_istri(wot,h,s, "111111111111abcd", "00000000000abcde"); + + try_istri(wot,h,s, "111abcde1abcde11", "00000000000abcde"); + + try_istri(wot,h,s, "11abcde11abcde11", "00000000000abcde"); + try_istri(wot,h,s, "1abcde111abcde11", "00000000000abcde"); + try_istri(wot,h,s, "abcde1111abcde11", "00000000000abcde"); + try_istri(wot,h,s, "bcde11111abcde11", "00000000000abcde"); + try_istri(wot,h,s, "cde111111abcde11", "00000000000abcde"); + + try_istri(wot,h,s, "01abcde11abcde11", "00000000000abcde"); + try_istri(wot,h,s, "00abcde11abcde11", "00000000000abcde"); + try_istri(wot,h,s, "000bcde11abcde11", "00000000000abcde"); + + try_istri(wot,h,s, "00abcde10abcde11", "00000000000abcde"); + try_istri(wot,h,s, "00abcde100bcde11", "00000000000abcde"); + + try_istri(wot,h,s, "1111111111111234", "0000000000000000"); + try_istri(wot,h,s, "1111111111111234", "0000000000000001"); + try_istri(wot,h,s, "1111111111111234", "0000000000000011"); + + try_istri(wot,h,s, "1111111111111234", "1111111111111234"); + try_istri(wot,h,s, "a111111111111111", "000000000000000a"); + try_istri(wot,h,s, "b111111111111111", "000000000000000a"); +} + + +////////////////////////////////////////////////////////// +// // +// ISTRI_08 // +// // +////////////////////////////////////////////////////////// + +UInt h_pcmpistri_08 ( V128* argL, V128* argR ) +{ + V128 block[2]; + memcpy(&block[0], argL, sizeof(V128)); + memcpy(&block[1], argR, sizeof(V128)); + ULong res, flags; + __asm__ __volatile__( + "subq $1024, %%rsp" "\n\t" + "movdqu 0(%2), %%xmm2" "\n\t" + "movdqu 16(%2), %%xmm11" "\n\t" + "pcmpistri $0x08, %%xmm2, %%xmm11" "\n\t" + "pushfq" "\n\t" + "popq %%rdx" "\n\t" + "movq %%rcx, %0" "\n\t" + "movq %%rdx, %1" "\n\t" + "addq $1024, %%rsp" "\n\t" + : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0]) + : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory" + ); + return ((flags & 0x8D5) << 16) | (res & 0xFFFF); +} + +UInt s_pcmpistri_08 ( V128* argLU, V128* argRU ) +{ + V128 resV; + UInt resOSZACP, resECX; + Bool ok + = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU, + zmask_from_V128(argLU), + zmask_from_V128(argRU), + 0x08, False/*!isSTRM*/ + ); + assert(ok); + resECX = resV.uInt[0]; + return (resOSZACP << 16) | resECX; +} + +void istri_08 ( void ) +{ + char* wot = "08"; + UInt(*h)(V128*,V128*) = h_pcmpistri_08; + UInt(*s)(V128*,V128*) = s_pcmpistri_08; + + try_istri(wot,h,s, "0000000000000000", "0000000000000000"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa"); + + try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); + try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa"); + + try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa"); + + try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000"); +} + + + +////////////////////////////////////////////////////////// +// // +// ISTRI_1A // +// // +////////////////////////////////////////////////////////// + +UInt h_pcmpistri_1A ( V128* argL, V128* argR ) +{ + V128 block[2]; + memcpy(&block[0], argL, sizeof(V128)); + memcpy(&block[1], argR, sizeof(V128)); + ULong res, flags; + __asm__ __volatile__( + "subq $1024, %%rsp" "\n\t" + "movdqu 0(%2), %%xmm2" "\n\t" + "movdqu 16(%2), %%xmm11" "\n\t" + "pcmpistri $0x1A, %%xmm2, %%xmm11" "\n\t" + "pushfq" "\n\t" + "popq %%rdx" "\n\t" + "movq %%rcx, %0" "\n\t" + "movq %%rdx, %1" "\n\t" + "addq $1024, %%rsp" "\n\t" + : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0]) + : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory" + ); + return ((flags & 0x8D5) << 16) | (res & 0xFFFF); +} + +UInt s_pcmpistri_1A ( V128* argLU, V128* argRU ) +{ + V128 resV; + UInt resOSZACP, resECX; + Bool ok + = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU, + zmask_from_V128(argLU), + zmask_from_V128(argRU), + 0x1A, False/*!isSTRM*/ + ); + assert(ok); + resECX = resV.uInt[0]; + return (resOSZACP << 16) | resECX; +} + +void istri_1A ( void ) +{ + char* wot = "1A"; + UInt(*h)(V128*,V128*) = h_pcmpistri_1A; + UInt(*s)(V128*,V128*) = s_pcmpistri_1A; + + try_istri(wot,h,s, "0000000000000000", "0000000000000000"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa"); + try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa"); + + try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); + try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa"); + + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa"); + + try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa"); + try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa"); + + try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000"); +} + + + +////////////////////////////////////////////////////////// +// // +// ISTRI_02 // +// // +////////////////////////////////////////////////////////// + +UInt h_pcmpistri_02 ( V128* argL, V128* argR ) +{ + V128 block[2]; + memcpy(&block[0], argL, sizeof(V128)); + memcpy(&block[1], argR, sizeof(V128)); + ULong res, flags; + __asm__ __volatile__( + "subq $1024, %%rsp" "\n\t" + "movdqu 0(%2), %%xmm2" "\n\t" + "movdqu 16(%2), %%xmm11" "\n\t" + "pcmpistri $0x02, %%xmm2, %%xmm11" "\n\t" +//"pcmpistrm $0x02, %%xmm2, %%xmm11" "\n\t" +//"movd %%xmm0, %%ecx" "\n\t" + "pushfq" "\n\t" + "popq %%rdx" "\n\t" + "movq %%rcx, %0" "\n\t" + "movq %%rdx, %1" "\n\t" + "addq $1024, %%rsp" "\n\t" + : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0]) + : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory" + ); + return ((flags & 0x8D5) << 16) | (res & 0xFFFF); +} + +UInt s_pcmpistri_02 ( V128* argLU, V128* argRU ) +{ + V128 resV; + UInt resOSZACP, resECX; + Bool ok + = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU, + zmask_from_V128(argLU), + zmask_from_V128(argRU), + 0x02, False/*!isSTRM*/ + ); + assert(ok); + resECX = resV.uInt[0]; + return (resOSZACP << 16) | resECX; +} + +void istri_02 ( void ) +{ + char* wot = "02"; + UInt(*h)(V128*,V128*) = h_pcmpistri_02; + UInt(*s)(V128*,V128*) = s_pcmpistri_02; + + try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab"); + try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd"); + + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd"); + try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd"); + try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd"); + try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd"); + try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd"); + + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0"); + + try_istri(wot,h,s, "0000000000000000", "0000000000000000"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd"); + try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba"); + try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb"); + try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba"); + + try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0"); + + try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe"); + try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe"); +} + + +////////////////////////////////////////////////////////// +// // +// ISTRI_12 // +// // +////////////////////////////////////////////////////////// + +UInt h_pcmpistri_12 ( V128* argL, V128* argR ) +{ + V128 block[2]; + memcpy(&block[0], argL, sizeof(V128)); + memcpy(&block[1], argR, sizeof(V128)); + ULong res, flags; + __asm__ __volatile__( + "subq $1024, %%rsp" "\n\t" + "movdqu 0(%2), %%xmm2" "\n\t" + "movdqu 16(%2), %%xmm11" "\n\t" + "pcmpistri $0x12, %%xmm2, %%xmm11" "\n\t" +//"pcmpistrm $0x12, %%xmm2, %%xmm11" "\n\t" +//"movd %%xmm0, %%ecx" "\n\t" + "pushfq" "\n\t" + "popq %%rdx" "\n\t" + "movq %%rcx, %0" "\n\t" + "movq %%rdx, %1" "\n\t" + "addq $1024, %%rsp" "\n\t" + : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0]) + : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory" + ); + return ((flags & 0x8D5) << 16) | (res & 0xFFFF); +} + +UInt s_pcmpistri_12 ( V128* argLU, V128* argRU ) +{ + V128 resV; + UInt resOSZACP, resECX; + Bool ok + = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU, + zmask_from_V128(argLU), + zmask_from_V128(argRU), + 0x12, False/*!isSTRM*/ + ); + assert(ok); + resECX = resV.uInt[0]; + return (resOSZACP << 16) | resECX; +} + +void istri_12 ( void ) +{ + char* wot = "12"; + UInt(*h)(V128*,V128*) = h_pcmpistri_12; + UInt(*s)(V128*,V128*) = s_pcmpistri_12; + + try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab"); + try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd"); + + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd"); + try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd"); + try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd"); + try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd"); + try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd"); + + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d"); + try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0"); + + try_istri(wot,h,s, "0000000000000000", "0000000000000000"); + try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); + + try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd"); + try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba"); + try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb"); + try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba"); + + try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0"); + + try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe"); + try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe"); +} + + + +////////////////////////////////////////////////////////// +// // +// ISTRI_44 // +// // +////////////////////////////////////////////////////////// + +UInt h_pcmpistri_44 ( V128* argL, V128* argR ) +{ + V128 block[2]; + memcpy(&block[0], argL, sizeof(V128)); + memcpy(&block[1], argR, sizeof(V128)); + ULong res, flags; + __asm__ __volatile__( + "subq $1024, %%rsp" "\n\t" + "movdqu 0(%2), %%xmm2" "\n\t" + "movdqu 16(%2), %%xmm11" "\n\t" + "pcmpistri $0x44, %%xmm2, %%xmm11" "\n\t" +//"pcmpistrm $0x04, %%xmm2, %%xmm11" "\n\t" +//"movd %%xmm0, %%ecx" "\n\t" + "pushfq" "\n\t" + "popq %%rdx" "\n\t" + "movq %%rcx, %0" "\n\t" + "movq %%rdx, %1" "\n\t" + "addq $1024, %%rsp" "\n\t" + : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0]) + : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory" + ); + return ((flags & 0x8D5) << 16) | (res & 0xFFFF); +} + +UInt s_pcmpistri_44 ( V128* argLU, V128* argRU ) +{ + V128 resV; + UInt resOSZACP, resECX; + Bool ok + = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU, + zmask_from_V128(argLU), + zmask_from_V128(argRU), + 0x44, False/*!isSTRM*/ + ); + assert(ok); + resECX = resV.uInt[0]; + return (resOSZACP << 16) | resECX; +} + +void istri_44 ( void ) +{ + char* wot = "44"; + UInt(*h)(V128*,V128*) = h_pcmpistri_44; + UInt(*s)(V128*,V128*) = s_pcmpistri_44; + + try_istri(wot,h,s, "aaaabbbbccccdddd", "00000000000000bc"); + try_istri(wot,h,s, "aaaabbbbccccdddd", "00000000000000cb"); + try_istri(wot,h,s, "baaabbbbccccdddd", "00000000000000cb"); + try_istri(wot,h,s, "baaabbbbccccdddc", "00000000000000cb"); + + try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000cb"); + try_istri(wot,h,s, "bbbbbbbb0bbbbbbb", "00000000000000cb"); + try_istri(wot,h,s, "bbbbbbbbbbbbbb0b", "00000000000000cb"); + try_istri(wot,h,s, "bbbbbbbbbbbbbbb0", "00000000000000cb"); + try_istri(wot,h,s, "0000000000000000", "00000000000000cb"); + + try_istri(wot,h,s, "0000000000000000", "0000000000000000"); + + try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000cb"); + try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "000000000000000b"); + try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000062cb"); + + try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000002cb"); + try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000000cb"); + try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "000000000000000b"); + + try_istri(wot,h,s, "0123456789abcdef", "000000fecb975421"); + try_istri(wot,h,s, "123456789abcdef1", "000000fecb975421"); + + try_istri(wot,h,s, "0123456789abcdef", "00000000dca86532"); + try_istri(wot,h,s, "123456789abcdef1", "00000000dca86532"); +} + + + + + +////////////////////////////////////////////////////////// +// // +// main // +// // +////////////////////////////////////////////////////////// + +int main ( void ) +{ + istri_4A(); + istri_3A(); + istri_08(); + istri_1A(); + istri_02(); + istri_0C(); + istri_12(); + istri_44(); + return 0; +} diff --git a/none/tests/amd64/pcmpxstrx64.c b/none/tests/amd64/pcmpxstrx64.c new file mode 100644 index 0000000..6d67aa7 --- /dev/null +++ b/none/tests/amd64/pcmpxstrx64.c @@ -0,0 +1,334 @@ + +/* Tests e-vs-i or i-vs-m aspects for pcmp{e,i}str{i,m}. Does not + check the core arithmetic in any detail. */ + +#include +#include +#include + +typedef unsigned char V128[16]; +typedef unsigned int UInt; +typedef signed int Int; +typedef unsigned char UChar; +typedef unsigned long long int ULong; +typedef UChar Bool; +#define False ((Bool)0) +#define True ((Bool)1) + +void show_V128 ( V128* vec ) +{ + Int i; + for (i = 15; i >= 0; i--) + printf("%02x", (UInt)( (*vec)[i] )); +} + +void expand ( V128* dst, char* summary ) +{ + Int i; + assert( strlen(summary) == 16 ); + for (i = 0; i < 16; i++) { + UChar xx = 0; + UChar x = summary[15-i]; + if (x >= '0' && x <= '9') { xx = x - '0'; } + else if (x >= 'A' && x <= 'F') { xx = x - 'A' + 10; } + else if (x >= 'a' && x <= 'f') { xx = x - 'a' + 10; } + else assert(0); + + assert(xx < 16); + xx = (xx << 4) | xx; + assert(xx < 256); + (*dst)[i] = xx; + } +} + +void one_test ( char* summL, ULong rdxIN, char* summR, ULong raxIN ) +{ + V128 argL, argR; + expand( &argL, summL ); + expand( &argR, summR ); + printf("\n"); + printf("rdx %016llx argL ", rdxIN); + show_V128(&argL); + printf(" rax %016llx argR ", raxIN); + show_V128(&argR); + printf("\n"); + + ULong block[ 2/*in:argL*/ // 0 0 + + 2/*in:argR*/ // 2 16 + + 1/*in:rdx*/ // 4 32 + + 1/*in:rax*/ // 5 40 + + 2/*inout:xmm0*/ // 6 48 + + 1/*inout:rcx*/ // 8 64 + + 1/*out:rflags*/ ]; // 9 72 + assert(sizeof(block) == 80); + + UChar* blockC = (UChar*)&block[0]; + + /* ---------------- ISTRI_4A ---------------- */ + memset(blockC, 0x55, 80); + memcpy(blockC + 0, &argL, 16); + memcpy(blockC + 16, &argR, 16); + memcpy(blockC + 24, &rdxIN, 8); + memcpy(blockC + 32, &raxIN, 8); + memcpy(blockC + 40, &rdxIN, 8); + __asm__ __volatile__( + "movupd 0(%0), %%xmm2" "\n\t" + "movupd 16(%0), %%xmm13" "\n\t" + "movq 32(%0), %%rdx" "\n\t" + "movq 40(%0), %%rax" "\n\t" + "movupd 48(%0), %%xmm0" "\n\t" + "movw 64(%0), %%rcx" "\n\t" + "pcmpistri $0x4A, %%xmm2, %%xmm13" "\n\t" + "movupd %%xmm0, 48(%0)" "\n\t" + "movw %%rcx, 64(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r15" "\n\t" + "movq %%r15, 72(%0)" "\n\t" + : /*out*/ + : /*in*/"r"(blockC) + : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15" + ); + printf(" istri $0x4A: "); + printf(" xmm0 "); + show_V128( (V128*)(blockC+48) ); + printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5); + + /* ---------------- ISTRI_0A ---------------- */ + memset(blockC, 0x55, 80); + memcpy(blockC + 0, &argL, 16); + memcpy(blockC + 16, &argR, 16); + memcpy(blockC + 24, &rdxIN, 8); + memcpy(blockC + 32, &raxIN, 8); + memcpy(blockC + 40, &rdxIN, 8); + __asm__ __volatile__( + "movupd 0(%0), %%xmm2" "\n\t" + "movupd 16(%0), %%xmm13" "\n\t" + "movq 32(%0), %%rdx" "\n\t" + "movq 40(%0), %%rax" "\n\t" + "movupd 48(%0), %%xmm0" "\n\t" + "movw 64(%0), %%rcx" "\n\t" + "pcmpistri $0x0A, %%xmm2, %%xmm13" "\n\t" + "movupd %%xmm0, 48(%0)" "\n\t" + "movw %%rcx, 64(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r15" "\n\t" + "movq %%r15, 72(%0)" "\n\t" + : /*out*/ + : /*in*/"r"(blockC) + : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15" + ); + printf(" istri $0x0A: "); + printf(" xmm0 "); + show_V128( (V128*)(blockC+48) ); + printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5); + + /* ---------------- ISTRM_4A ---------------- */ + memset(blockC, 0x55, 80); + memcpy(blockC + 0, &argL, 16); + memcpy(blockC + 16, &argR, 16); + memcpy(blockC + 24, &rdxIN, 8); + memcpy(blockC + 32, &raxIN, 8); + memcpy(blockC + 40, &rdxIN, 8); + __asm__ __volatile__( + "movupd 0(%0), %%xmm2" "\n\t" + "movupd 16(%0), %%xmm13" "\n\t" + "movq 32(%0), %%rdx" "\n\t" + "movq 40(%0), %%rax" "\n\t" + "movupd 48(%0), %%xmm0" "\n\t" + "movw 64(%0), %%rcx" "\n\t" + "pcmpistrm $0x4A, %%xmm2, %%xmm13" "\n\t" + "movupd %%xmm0, 48(%0)" "\n\t" + "movw %%rcx, 64(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r15" "\n\t" + "movq %%r15, 72(%0)" "\n\t" + : /*out*/ + : /*in*/"r"(blockC) + : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15" + ); + printf(" istrm $0x4A: "); + printf(" xmm0 "); + show_V128( (V128*)(blockC+48) ); + printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5); + + /* ---------------- ISTRM_0A ---------------- */ + memset(blockC, 0x55, 80); + memcpy(blockC + 0, &argL, 16); + memcpy(blockC + 16, &argR, 16); + memcpy(blockC + 24, &rdxIN, 8); + memcpy(blockC + 32, &raxIN, 8); + memcpy(blockC + 40, &rdxIN, 8); + __asm__ __volatile__( + "movupd 0(%0), %%xmm2" "\n\t" + "movupd 16(%0), %%xmm13" "\n\t" + "movq 32(%0), %%rdx" "\n\t" + "movq 40(%0), %%rax" "\n\t" + "movupd 48(%0), %%xmm0" "\n\t" + "movw 64(%0), %%rcx" "\n\t" + "pcmpistrm $0x0A, %%xmm2, %%xmm13" "\n\t" + "movupd %%xmm0, 48(%0)" "\n\t" + "movw %%rcx, 64(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r15" "\n\t" + "movq %%r15, 72(%0)" "\n\t" + : /*out*/ + : /*in*/"r"(blockC) + : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15" + ); + printf(" istrm $0x0A: "); + printf(" xmm0 "); + show_V128( (V128*)(blockC+48) ); + printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5); + + /* ---------------- ESTRI_4A ---------------- */ + memset(blockC, 0x55, 80); + memcpy(blockC + 0, &argL, 16); + memcpy(blockC + 16, &argR, 16); + memcpy(blockC + 24, &rdxIN, 8); + memcpy(blockC + 32, &raxIN, 8); + memcpy(blockC + 40, &rdxIN, 8); + __asm__ __volatile__( + "movupd 0(%0), %%xmm2" "\n\t" + "movupd 16(%0), %%xmm13" "\n\t" + "movq 32(%0), %%rdx" "\n\t" + "movq 40(%0), %%rax" "\n\t" + "movupd 48(%0), %%xmm0" "\n\t" + "movw 64(%0), %%rcx" "\n\t" + "pcmpestri $0x4A, %%xmm2, %%xmm13" "\n\t" + "movupd %%xmm0, 48(%0)" "\n\t" + "movw %%rcx, 64(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r15" "\n\t" + "movq %%r15, 72(%0)" "\n\t" + : /*out*/ + : /*in*/"r"(blockC) + : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15" + ); + printf(" estri $0x4A: "); + printf(" xmm0 "); + show_V128( (V128*)(blockC+48) ); + printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5); + + /* ---------------- ESTRI_0A ---------------- */ + memset(blockC, 0x55, 80); + memcpy(blockC + 0, &argL, 16); + memcpy(blockC + 16, &argR, 16); + memcpy(blockC + 24, &rdxIN, 8); + memcpy(blockC + 32, &raxIN, 8); + memcpy(blockC + 40, &rdxIN, 8); + __asm__ __volatile__( + "movupd 0(%0), %%xmm2" "\n\t" + "movupd 16(%0), %%xmm13" "\n\t" + "movq 32(%0), %%rdx" "\n\t" + "movq 40(%0), %%rax" "\n\t" + "movupd 48(%0), %%xmm0" "\n\t" + "movw 64(%0), %%rcx" "\n\t" + "pcmpestri $0x0A, %%xmm2, %%xmm13" "\n\t" + "movupd %%xmm0, 48(%0)" "\n\t" + "movw %%rcx, 64(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r15" "\n\t" + "movq %%r15, 72(%0)" "\n\t" + : /*out*/ + : /*in*/"r"(blockC) + : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15" + ); + printf(" estri $0x0A: "); + printf(" xmm0 "); + show_V128( (V128*)(blockC+48) ); + printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5); + + /* ---------------- ESTRM_4A ---------------- */ + memset(blockC, 0x55, 80); + memcpy(blockC + 0, &argL, 16); + memcpy(blockC + 16, &argR, 16); + memcpy(blockC + 24, &rdxIN, 8); + memcpy(blockC + 32, &raxIN, 8); + memcpy(blockC + 40, &rdxIN, 8); + __asm__ __volatile__( + "movupd 0(%0), %%xmm2" "\n\t" + "movupd 16(%0), %%xmm13" "\n\t" + "movq 32(%0), %%rdx" "\n\t" + "movq 40(%0), %%rax" "\n\t" + "movupd 48(%0), %%xmm0" "\n\t" + "movw 64(%0), %%rcx" "\n\t" + "pcmpestrm $0x4A, %%xmm2, %%xmm13" "\n\t" + "movupd %%xmm0, 48(%0)" "\n\t" + "movw %%rcx, 64(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r15" "\n\t" + "movq %%r15, 72(%0)" "\n\t" + : /*out*/ + : /*in*/"r"(blockC) + : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15" + ); + printf(" estrm $0x4A: "); + printf(" xmm0 "); + show_V128( (V128*)(blockC+48) ); + printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5); + + /* ---------------- ESTRM_0A ---------------- */ + memset(blockC, 0x55, 80); + memcpy(blockC + 0, &argL, 16); + memcpy(blockC + 16, &argR, 16); + memcpy(blockC + 24, &rdxIN, 8); + memcpy(blockC + 32, &raxIN, 8); + memcpy(blockC + 40, &rdxIN, 8); + __asm__ __volatile__( + "movupd 0(%0), %%xmm2" "\n\t" + "movupd 16(%0), %%xmm13" "\n\t" + "movq 32(%0), %%rdx" "\n\t" + "movq 40(%0), %%rax" "\n\t" + "movupd 48(%0), %%xmm0" "\n\t" + "movw 64(%0), %%rcx" "\n\t" + "pcmpestrm $0x0A, %%xmm2, %%xmm13" "\n\t" + "movupd %%xmm0, 48(%0)" "\n\t" + "movw %%rcx, 64(%0)" "\n\t" + "pushfq" "\n\t" + "popq %%r15" "\n\t" + "movq %%r15, 72(%0)" "\n\t" + : /*out*/ + : /*in*/"r"(blockC) + : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15" + ); + printf(" estrm $0x0A: "); + printf(" xmm0 "); + show_V128( (V128*)(blockC+48) ); + printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5); + + + + +} + +int main ( void ) +{ + one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaa0aaaaaaa", 0 ); + one_test("0000000000000000", 0, "aaaaaaaa0aaaaaaa", 0 ); + + one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaaaaaaaaaa", 0 ); + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 0 ); + one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaaaaaaaaaa", 6 ); + + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 6 ); + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 15 ); + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 16 ); + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 17 ); + + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -6 ); + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -15 ); + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -16 ); + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -17 ); + + one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 6 ); + one_test("aaaaaaaaaaaaaaaa", 15, "aaaaaaaaaaaaaaaa", 6 ); + one_test("aaaaaaaaaaaaaaaa", 16, "aaaaaaaaaaaaaaaa", 6 ); + one_test("aaaaaaaaaaaaaaaa", 17, "aaaaaaaaaaaaaaaa", 6 ); + + one_test("aaaaaaaaaaaaaaaa", -5, "aaaaaaaaaaaaaaaa", 6 ); + one_test("aaaaaaaaaaaaaaaa", -15, "aaaaaaaaaaaaaaaa", 6 ); + one_test("aaaaaaaaaaaaaaaa", -16, "aaaaaaaaaaaaaaaa", 6 ); + one_test("aaaaaaaaaaaaaaaa", -17, "aaaaaaaaaaaaaaaa", 6 ); + + return 0; +} diff --git a/none/tests/amd64/sbbmisc.c b/none/tests/amd64/sbbmisc.c new file mode 100644 index 0000000..ef542fa --- /dev/null +++ b/none/tests/amd64/sbbmisc.c @@ -0,0 +1,244 @@ +#include "tests/asm.h" +#include + +char in_b, out_b1, out_b2, in_b2; + +short in_w, out_w1, out_w2; + +int in_l, out_l1, out_l2; + +extern void sbb_ib_al ( void ); +asm("\n" +VG_SYM(sbb_ib_al) ":\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tclc\n" +"\tsbbb $5, %al\n" +"\tmovb %al, " VG_SYM(out_b1) "\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tstc\n" +"\tsbbb $5, %al\n" +"\tmovb %al, " VG_SYM(out_b2) "\n" + +"\tretq\n" +); + + +extern void sbb_iw_ax ( void ); +asm("\n" +VG_SYM(sbb_iw_ax) ":\n" + +"\tmovw " VG_SYM(in_w) ", %ax\n" +"\tclc\n" +"\tsbbw $555, %ax\n" +"\tmovw %ax, " VG_SYM(out_w1) "\n" + +"\tmovw " VG_SYM(in_w) ", %ax\n" +"\tstc\n" +"\tsbbw $555, %ax\n" +"\tmovw %ax, " VG_SYM(out_w2) "\n" + +"\tretq\n" +); + + +extern void sbb_il_eax ( void ); +asm("\n" +VG_SYM(sbb_il_eax) ":\n" + +"\tmovl " VG_SYM(in_l) ", %eax\n" +"\tclc\n" +"\tsbbl $555666, %eax\n" +"\tmovl %eax, " VG_SYM(out_l1) "\n" + +"\tmovl " VG_SYM(in_l) ", %eax\n" +"\tstc\n" +"\tsbbl $555666, %eax\n" +"\tmovl %eax, " VG_SYM(out_l2) "\n" + +"\tretq\n" +); + + +extern void sbb_eb_gb ( void ); +asm("\n" +VG_SYM(sbb_eb_gb) ":\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tclc\n" +"\tsbbb " VG_SYM(in_b2) ", %al\n" +"\tmovb %al, " VG_SYM(out_b1) "\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tstc\n" +"\tsbbb " VG_SYM(in_b2) ", %al\n" +"\tmovb %al, " VG_SYM(out_b2) "\n" + +"\tretq\n" +); + + +extern void sbb_eb_gb_2 ( void ); +asm("\n" +VG_SYM(sbb_eb_gb_2) ":\n" +"\tpushq %rcx\n" + +"\tmovb " VG_SYM(in_b) ", %cl\n" +"\tmovb " VG_SYM(in_b2) ", %dh\n" +"\tclc\n" +"\tsbbb %dh,%cl\n" +"\tmovb %cl, " VG_SYM(out_b1) "\n" + +"\tmovb " VG_SYM(in_b) ", %cl\n" +"\tmovb " VG_SYM(in_b2) ", %dh\n" +"\tstc\n" +"\tsbbb %dh,%cl\n" +"\tmovb %cl, " VG_SYM(out_b2) "\n" + +"\tpopq %rcx\n" +"\tretq\n" +); + + +extern void adc_eb_gb ( void ); +asm("\n" +VG_SYM(adc_eb_gb) ":\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tclc\n" +"\tadcb " VG_SYM(in_b2) ", %al\n" +"\tmovb %al, " VG_SYM(out_b1) "\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tstc\n" +"\tadcb " VG_SYM(in_b2) ", %al\n" +"\tmovb %al, " VG_SYM(out_b2) "\n" + +"\tretq\n" +); + + +extern void adc_eb_gb_2 ( void ); +asm("\n" +VG_SYM(adc_eb_gb_2) ":\n" +"\tpushq %rcx\n" + +"\tmovb " VG_SYM(in_b) ", %cl\n" +"\tmovb " VG_SYM(in_b2) ", %dh\n" +"\tclc\n" +"\tadcb %dh,%cl\n" +"\tmovb %cl, " VG_SYM(out_b1) "\n" + +"\tmovb " VG_SYM(in_b) ", %cl\n" +"\tmovb " VG_SYM(in_b2) ", %dh\n" +"\tstc\n" +"\tadcb %dh,%cl\n" +"\tmovb %cl, " VG_SYM(out_b2) "\n" + +"\tpopq %rcx\n" +"\tretq\n" +); + +extern void adc_ib_al ( void ); +asm("\n" +VG_SYM(adc_ib_al) ":\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tclc\n" +"\tadcb $5, %al\n" +"\tmovb %al, " VG_SYM(out_b1) "\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tstc\n" +"\tadcb $5, %al\n" +"\tmovb %al, " VG_SYM(out_b2) "\n" + +"\tretq\n" +); + + +extern void adc_iw_ax ( void ); +asm("\n" +VG_SYM(adc_iw_ax) ":\n" + +"\tmovw " VG_SYM(in_w) ", %ax\n" +"\tclc\n" +"\tadcw $555, %ax\n" +"\tmovw %ax, " VG_SYM(out_w1) "\n" + +"\tmovw " VG_SYM(in_w) ", %ax\n" +"\tstc\n" +"\tadcw $555, %ax\n" +"\tmovw %ax, " VG_SYM(out_w2) "\n" + +"\tretq\n" +); + + +extern void adc_il_eax ( void ); +asm("\n" +VG_SYM(adc_il_eax) ":\n" + +"\tmovl " VG_SYM(in_l) ", %eax\n" +"\tclc\n" +"\tadcl $555666, %eax\n" +"\tmovl %eax, " VG_SYM(out_l1) "\n" + +"\tmovl " VG_SYM(in_l) ", %eax\n" +"\tstc\n" +"\tadcl $555666, %eax\n" +"\tmovl %eax, " VG_SYM(out_l2) "\n" + +"\tretq\n" +); + + +int main ( void ) +{ + in_b = 99; + sbb_ib_al(); + printf("r1 = %d %d\n", (int)out_b1, (int)out_b2); + + in_w = 49999; + sbb_iw_ax(); + printf("r2 = %d %d\n", (int)out_w1, (int)out_w2); + + in_l = 0xF0000000; + sbb_il_eax(); + printf("r3 = %d %d\n", (int)out_l1, (int)out_l2); + + in_b = 99; + in_b2 = 88; + sbb_eb_gb(); + printf("r4 = %d %d\n", (int)out_b1, (int)out_b2); + + in_b = 66; + in_b2 = 77; + sbb_eb_gb_2(); + printf("r5 = %d %d\n", (int)out_b1, (int)out_b2); + + in_b = 99; + in_b2 = 88; + adc_eb_gb(); + printf("r6 = %d %d\n", (int)out_b1, (int)out_b2); + + in_b = 66; + in_b2 = 77; + adc_eb_gb_2(); + printf("r7 = %d %d\n", (int)out_b1, (int)out_b2); + + in_b = 99; + adc_ib_al(); + printf("r8 = %d %d\n", (int)out_b1, (int)out_b2); + + in_w = 49999; + adc_iw_ax(); + printf("r9 = %d %d\n", (int)out_w1, (int)out_w2); + + in_l = 0xF0000000; + adc_il_eax(); + printf("r10 = %d %d\n", (int)out_l1, (int)out_l2); + + return 0; +} diff --git a/none/tests/amd64/sbbmisc.stderr.exp b/none/tests/amd64/sbbmisc.stderr.exp new file mode 100644 index 0000000..139597f --- /dev/null +++ b/none/tests/amd64/sbbmisc.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/amd64/sbbmisc.stdout.exp b/none/tests/amd64/sbbmisc.stdout.exp new file mode 100644 index 0000000..2945cc3 --- /dev/null +++ b/none/tests/amd64/sbbmisc.stdout.exp @@ -0,0 +1,10 @@ +r1 = 94 93 +r2 = -16092 -16093 +r3 = -268991122 -268991123 +r4 = 11 10 +r5 = -11 -12 +r6 = -69 -68 +r7 = -113 -112 +r8 = 104 105 +r9 = -14982 -14981 +r10 = -267879790 -267879789 diff --git a/none/tests/amd64/sbbmisc.vgtest b/none/tests/amd64/sbbmisc.vgtest new file mode 100644 index 0000000..b90ba2a --- /dev/null +++ b/none/tests/amd64/sbbmisc.vgtest @@ -0,0 +1 @@ +prog: sbbmisc diff --git a/none/tests/amd64/sse4-64.c b/none/tests/amd64/sse4-64.c new file mode 100644 index 0000000..467a03f --- /dev/null +++ b/none/tests/amd64/sse4-64.c @@ -0,0 +1,2681 @@ + +/* A program to test SSE4.1/SSE4.2 instructions. + Revisions: Nov.208 - wrote this file + Apr.10.2010 - added PEXTR* tests + Apr.16.2010 - added PINS* tests +*/ + +/* HOW TO COMPILE: + gcc -m64 -g -O -Wall -o sse4-64 sse4-64.c +*/ + +#include +#include +#include +//#include "tests/malloc.h" // reenable when reintegrated +#include + + + +// rmme when reintegrated +// Allocates a 16-aligned block. Asserts if the allocation fails. +#include +__attribute__((unused)) +static void* memalign16(size_t szB) +{ + void* x; +#if defined(VGO_darwin) + // Darwin lacks memalign, but its malloc is always 16-aligned anyway. + x = malloc(szB); +#else + x = memalign(16, szB); +#endif + assert(x); + assert(0 == ((16-1) & (unsigned long)x)); + return x; +} + + + +typedef unsigned char V128[16]; +typedef unsigned int UInt; +typedef signed int Int; +typedef unsigned char UChar; +typedef unsigned long long int ULong; + +typedef unsigned char Bool; +#define False ((Bool)0) +#define True ((Bool)1) + + +typedef + struct { + V128 arg1; + V128 arg2; + V128 res; + } + RRArgs; + +typedef + struct { + V128 arg1; + V128 res; + } + RMArgs; + +static void do64HLtoV128 ( /*OUT*/V128* res, ULong wHi, ULong wLo ) +{ + // try to sidestep strict-aliasing snafus by memcpying explicitly + UChar* p = (UChar*)res; + memcpy(&p[8], (UChar*)&wHi, 8); + memcpy(&p[0], (UChar*)&wLo, 8); +} + +static UChar randUChar ( void ) +{ + static UInt seed = 80021; + seed = 1103515245 * seed + 12345; + return (seed >> 17) & 0xFF; +} + +static ULong randULong ( void ) +{ + Int i; + ULong r = 0; + for (i = 0; i < 8; i++) { + r = (r << 8) | (ULong)(0xFF & randUChar()); + } + return r; +} + +static void randV128 ( V128* v ) +{ + Int i; + for (i = 0; i < 16; i++) + (*v)[i] = randUChar(); +} + +static void showV128 ( V128* v ) +{ + Int i; + for (i = 15; i >= 0; i--) + printf("%02x", (Int)(*v)[i]); +} + +static void showMaskedV128 ( V128* v, V128* mask ) +{ + Int i; + for (i = 15; i >= 0; i--) + printf("%02x", (Int)( ((*v)[i]) & ((*mask)[i]) )); +} + +static void showIGVV( char* rOrM, char* op, Int imm, + ULong src64, V128* dst, V128* res ) +{ + printf("%s %10s $%d ", rOrM, op, imm); + printf("%016llx", src64); + printf(" "); + showV128(dst); + printf(" "); + showV128(res); + printf("\n"); +} + +static void showIAG ( char* rOrM, char* op, Int imm, + V128* argL, ULong argR, ULong res ) +{ + printf("%s %10s $%d ", rOrM, op, imm); + showV128(argL); + printf(" "); + printf("%016llx", argR); + printf(" "); + printf("%016llx", res); + printf("\n"); +} + +static void showIAA ( char* rOrM, char* op, Int imm, RRArgs* rra, V128* rmask ) +{ + printf("%s %10s $%d ", rOrM, op, imm); + showV128(&rra->arg1); + printf(" "); + showV128(&rra->arg2); + printf(" "); + showMaskedV128(&rra->res, rmask); + printf("\n"); +} + +static void showAA ( char* rOrM, char* op, RRArgs* rra, V128* rmask ) +{ + printf("%s %10s ", rOrM, op); + showV128(&rra->arg1); + printf(" "); + showV128(&rra->arg2); + printf(" "); + showMaskedV128(&rra->res, rmask); + printf("\n"); +} + +/* Note: these are little endian. Hence first byte is the least + significant byte of lane zero. */ + +/* Mask for insns where all result bits are non-approximated. */ +static V128 AllMask = { 0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF }; + +/* Mark for insns which produce approximated vector short results. */ +static V128 ApproxPS = { 0x00,0x00,0x80,0xFF, 0x00,0x00,0x80,0xFF, + 0x00,0x00,0x80,0xFF, 0x00,0x00,0x80,0xFF }; + +/* Mark for insns which produce approximated scalar short results. */ +static V128 ApproxSS = { 0x00,0x00,0x80,0xFF, 0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF }; + +static V128 fives = { 0x55,0x55,0x55,0x55, 0x55,0x55,0x55,0x55, + 0x55,0x55,0x55,0x55, 0x55,0x55,0x55,0x55 }; + +static V128 zeroes = { 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00 }; + +double mkPosInf ( void ) { return 1.0 / 0.0; } +double mkNegInf ( void ) { return -mkPosInf(); } +double mkPosNan ( void ) { return 0.0 / 0.0; } +double mkNegNan ( void ) { return -mkPosNan(); } + + +#define DO_imm_r_r(_opname, _imm, _src, _dst) \ + { \ + V128 _tmp; \ + __asm__ __volatile__( \ + "movupd (%0), %%xmm2" "\n\t" \ + "movupd (%1), %%xmm11" "\n\t" \ + _opname " $" #_imm ", %%xmm2, %%xmm11" "\n\t" \ + "movupd %%xmm11, (%2)" "\n" \ + : /*out*/ : /*in*/ "r"(&(_src)), "r"(&(_dst)), "r"(&(_tmp)) \ + : "cc", "memory", "xmm2", "xmm11" \ + ); \ + RRArgs rra; \ + memcpy(&rra.arg1, &(_src), sizeof(V128)); \ + memcpy(&rra.arg2, &(_dst), sizeof(V128)); \ + memcpy(&rra.res, &(_tmp), sizeof(V128)); \ + showIAA("r", (_opname), (_imm), &rra, &AllMask); \ + } + +#define DO_imm_m_r(_opname, _imm, _src, _dst) \ + { \ + V128 _tmp; \ + V128* _srcM = memalign16(sizeof(V128)); \ + memcpy(_srcM, &(_src), sizeof(V128)); \ + __asm__ __volatile__( \ + "movupd (%1), %%xmm11" "\n\t" \ + _opname " $" #_imm ", (%0), %%xmm11" "\n\t" \ + "movupd %%xmm11, (%2)" "\n" \ + : /*out*/ : /*in*/ "r"(_srcM), "r"(&(_dst)), "r"(&(_tmp)) \ + : "cc", "memory", "xmm11" \ + ); \ + RRArgs rra; \ + memcpy(&rra.arg1, &(_src), sizeof(V128)); \ + memcpy(&rra.arg2, &(_dst), sizeof(V128)); \ + memcpy(&rra.res, &(_tmp), sizeof(V128)); \ + showIAA("m", (_opname), (_imm), &rra, &AllMask); \ + free(_srcM); \ + } + +#define DO_imm_mandr_r(_opname, _imm, _src, _dst) \ + DO_imm_r_r( _opname, _imm, _src, _dst ) \ + DO_imm_m_r( _opname, _imm, _src, _dst ) + + + + + +#define DO_r_r(_opname, _src, _dst) \ + { \ + V128 _tmp; \ + __asm__ __volatile__( \ + "movupd (%0), %%xmm2" "\n\t" \ + "movupd (%1), %%xmm11" "\n\t" \ + _opname " %%xmm2, %%xmm11" "\n\t" \ + "movupd %%xmm11, (%2)" "\n" \ + : /*out*/ : /*in*/ "r"(&(_src)), "r"(&(_dst)), "r"(&(_tmp)) \ + : "cc", "memory", "xmm2", "xmm11" \ + ); \ + RRArgs rra; \ + memcpy(&rra.arg1, &(_src), sizeof(V128)); \ + memcpy(&rra.arg2, &(_dst), sizeof(V128)); \ + memcpy(&rra.res, &(_tmp), sizeof(V128)); \ + showAA("r", (_opname), &rra, &AllMask); \ + } + +#define DO_m_r(_opname, _src, _dst) \ + { \ + V128 _tmp; \ + V128* _srcM = memalign16(sizeof(V128)); \ + memcpy(_srcM, &(_src), sizeof(V128)); \ + __asm__ __volatile__( \ + "movupd (%1), %%xmm11" "\n\t" \ + _opname " (%0), %%xmm11" "\n\t" \ + "movupd %%xmm11, (%2)" "\n" \ + : /*out*/ : /*in*/ "r"(_srcM), "r"(&(_dst)), "r"(&(_tmp)) \ + : "cc", "memory", "xmm11" \ + ); \ + RRArgs rra; \ + memcpy(&rra.arg1, &(_src), sizeof(V128)); \ + memcpy(&rra.arg2, &(_dst), sizeof(V128)); \ + memcpy(&rra.res, &(_tmp), sizeof(V128)); \ + showAA("m", (_opname), &rra, &AllMask); \ + free(_srcM); \ + } + +#define DO_mandr_r(_opname, _src, _dst) \ + DO_r_r(_opname, _src, _dst) \ + DO_m_r(_opname, _src, _dst) + + + + +#define DO_imm_r_to_rscalar(_opname, _imm, _src, _dstsuffix) \ + { \ + ULong _scbefore = 0x5555555555555555ULL; \ + ULong _scafter = 0xAAAAAAAAAAAAAAAAULL; \ + /* This assumes that gcc won't make any of %0, %1, %2 */ \ + /* be r11. That should be ensured (cough, cough) */ \ + /* by declaring r11 to be clobbered. */ \ + __asm__ __volatile__( \ + "movupd (%0), %%xmm2" "\n\t" \ + "movq (%1), %%r11" "\n\t" \ + _opname " $" #_imm ", %%xmm2, %%r11" _dstsuffix "\n\t" \ + "movq %%r11, (%2)" "\n" \ + : /*out*/ \ + : /*in*/ "r"(&(_src)), "r"(&(_scbefore)), "r"(&(_scafter)) \ + : "cc", "memory", "xmm2", "r11" \ + ); \ + showIAG("r", (_opname), (_imm), &(_src), (_scbefore), (_scafter)); \ + } + +#define DO_imm_r_to_mscalar(_opname, _imm, _src) \ + { \ + ULong _scbefore = 0x5555555555555555ULL; \ + ULong _scafter = _scbefore; \ + __asm__ __volatile__( \ + "movupd (%0), %%xmm2" "\n\t" \ + _opname " $" #_imm ", %%xmm2, (%1)" "\n\t" \ + : /*out*/ \ + : /*in*/ "r"(&(_src)), "r"(&(_scafter)) \ + : "cc", "memory", "xmm2" \ + ); \ + showIAG("m", (_opname), (_imm), &(_src), (_scbefore), (_scafter)); \ + } + +#define DO_imm_r_to_mandrscalar(_opname, _imm, _src, _dstsuffix) \ + DO_imm_r_to_rscalar( _opname, _imm, _src, _dstsuffix ) \ + DO_imm_r_to_mscalar( _opname, _imm, _src ) + + + + + + + + +#define DO_imm_rscalar_to_r(_opname, _imm, _src, _srcsuffix) \ + { \ + V128 dstv; \ + V128 res; \ + ULong src64 = (ULong)(_src); \ + memcpy(dstv, fives, sizeof(dstv)); \ + memcpy(res, zeroes, sizeof(res)); \ + /* This assumes that gcc won't make any of %0, %1, %2 */ \ + /* be r11. That should be ensured (cough, cough) */ \ + /* by declaring r11 to be clobbered. */ \ + __asm__ __volatile__( \ + "movupd (%0), %%xmm2" "\n\t" /*dstv*/ \ + "movq (%1), %%r11" "\n\t" /*src64*/ \ + _opname " $" #_imm ", %%r11" _srcsuffix ", %%xmm2" "\n\t" \ + "movupd %%xmm2, (%2)" "\n" /*res*/ \ + : /*out*/ \ + : /*in*/ "r"(&dstv), "r"(&src64), "r"(&res) \ + : "cc", "memory", "xmm2", "r11" \ + ); \ + showIGVV("r", (_opname), (_imm), src64, &dstv, &res); \ + } +#define DO_imm_mscalar_to_r(_opname, _imm, _src) \ + { \ + V128 dstv; \ + V128 res; \ + ULong src64 = (ULong)(_src); \ + memcpy(dstv, fives, sizeof(dstv)); \ + memcpy(res, zeroes, sizeof(res)); \ + __asm__ __volatile__( \ + "movupd (%0), %%xmm2" "\n\t" /*dstv*/ \ + _opname " $" #_imm ", (%1), %%xmm2" "\n\t" \ + "movupd %%xmm2, (%2)" "\n" /*res*/ \ + : /*out*/ \ + : /*in*/ "r"(&dstv), "r"(&src64), "r"(&res) \ + : "cc", "memory", "xmm2" \ + ); \ + showIGVV("m", (_opname), (_imm), src64, &dstv, &res); \ + } + +#define DO_imm_mandrscalar_to_r(_opname, _imm, _src, _dstsuffix) \ + DO_imm_rscalar_to_r( _opname, _imm, _src, _dstsuffix ) \ + DO_imm_mscalar_to_r( _opname, _imm, _src ) + + + + + +void test_BLENDPD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_imm_mandr_r("blendpd", 0, src, dst); + DO_imm_mandr_r("blendpd", 1, src, dst); + DO_imm_mandr_r("blendpd", 2, src, dst); + DO_imm_mandr_r("blendpd", 3, src, dst); + } +} + +void test_BLENDPS ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_imm_mandr_r("blendps", 0, src, dst); + DO_imm_mandr_r("blendps", 1, src, dst); + DO_imm_mandr_r("blendps", 2, src, dst); + DO_imm_mandr_r("blendps", 3, src, dst); + DO_imm_mandr_r("blendps", 4, src, dst); + DO_imm_mandr_r("blendps", 5, src, dst); + DO_imm_mandr_r("blendps", 6, src, dst); + DO_imm_mandr_r("blendps", 7, src, dst); + DO_imm_mandr_r("blendps", 8, src, dst); + DO_imm_mandr_r("blendps", 9, src, dst); + DO_imm_mandr_r("blendps", 10, src, dst); + DO_imm_mandr_r("blendps", 11, src, dst); + DO_imm_mandr_r("blendps", 12, src, dst); + DO_imm_mandr_r("blendps", 13, src, dst); + DO_imm_mandr_r("blendps", 14, src, dst); + DO_imm_mandr_r("blendps", 15, src, dst); + } +} + +void test_DPPD ( void ) +{ + V128 src, dst; + { + *(double*)(&src[0]) = 1.2345; + *(double*)(&src[8]) = -6.78910; + *(double*)(&dst[0]) = -11.121314; + *(double*)(&dst[8]) = 15.161718; + DO_imm_mandr_r("dppd", 0, src, dst); + DO_imm_mandr_r("dppd", 1, src, dst); + DO_imm_mandr_r("dppd", 2, src, dst); + DO_imm_mandr_r("dppd", 3, src, dst); + DO_imm_mandr_r("dppd", 4, src, dst); + DO_imm_mandr_r("dppd", 5, src, dst); + DO_imm_mandr_r("dppd", 6, src, dst); + DO_imm_mandr_r("dppd", 7, src, dst); + DO_imm_mandr_r("dppd", 8, src, dst); + DO_imm_mandr_r("dppd", 9, src, dst); + DO_imm_mandr_r("dppd", 10, src, dst); + DO_imm_mandr_r("dppd", 11, src, dst); + DO_imm_mandr_r("dppd", 12, src, dst); + DO_imm_mandr_r("dppd", 13, src, dst); + DO_imm_mandr_r("dppd", 14, src, dst); + DO_imm_mandr_r("dppd", 15, src, dst); + DO_imm_mandr_r("dppd", 16, src, dst); + DO_imm_mandr_r("dppd", 17, src, dst); + DO_imm_mandr_r("dppd", 18, src, dst); + DO_imm_mandr_r("dppd", 19, src, dst); + DO_imm_mandr_r("dppd", 20, src, dst); + DO_imm_mandr_r("dppd", 21, src, dst); + DO_imm_mandr_r("dppd", 22, src, dst); + DO_imm_mandr_r("dppd", 23, src, dst); + DO_imm_mandr_r("dppd", 24, src, dst); + DO_imm_mandr_r("dppd", 25, src, dst); + DO_imm_mandr_r("dppd", 26, src, dst); + DO_imm_mandr_r("dppd", 27, src, dst); + DO_imm_mandr_r("dppd", 28, src, dst); + DO_imm_mandr_r("dppd", 29, src, dst); + DO_imm_mandr_r("dppd", 30, src, dst); + DO_imm_mandr_r("dppd", 31, src, dst); + DO_imm_mandr_r("dppd", 32, src, dst); + DO_imm_mandr_r("dppd", 33, src, dst); + DO_imm_mandr_r("dppd", 34, src, dst); + DO_imm_mandr_r("dppd", 35, src, dst); + DO_imm_mandr_r("dppd", 36, src, dst); + DO_imm_mandr_r("dppd", 37, src, dst); + DO_imm_mandr_r("dppd", 38, src, dst); + DO_imm_mandr_r("dppd", 39, src, dst); + DO_imm_mandr_r("dppd", 40, src, dst); + DO_imm_mandr_r("dppd", 41, src, dst); + DO_imm_mandr_r("dppd", 42, src, dst); + DO_imm_mandr_r("dppd", 43, src, dst); + DO_imm_mandr_r("dppd", 44, src, dst); + DO_imm_mandr_r("dppd", 45, src, dst); + DO_imm_mandr_r("dppd", 46, src, dst); + DO_imm_mandr_r("dppd", 47, src, dst); + DO_imm_mandr_r("dppd", 48, src, dst); + DO_imm_mandr_r("dppd", 49, src, dst); + DO_imm_mandr_r("dppd", 50, src, dst); + DO_imm_mandr_r("dppd", 51, src, dst); + DO_imm_mandr_r("dppd", 52, src, dst); + DO_imm_mandr_r("dppd", 53, src, dst); + DO_imm_mandr_r("dppd", 54, src, dst); + DO_imm_mandr_r("dppd", 55, src, dst); + DO_imm_mandr_r("dppd", 56, src, dst); + DO_imm_mandr_r("dppd", 57, src, dst); + DO_imm_mandr_r("dppd", 58, src, dst); + DO_imm_mandr_r("dppd", 59, src, dst); + DO_imm_mandr_r("dppd", 60, src, dst); + DO_imm_mandr_r("dppd", 61, src, dst); + DO_imm_mandr_r("dppd", 62, src, dst); + DO_imm_mandr_r("dppd", 63, src, dst); + DO_imm_mandr_r("dppd", 64, src, dst); + DO_imm_mandr_r("dppd", 65, src, dst); + DO_imm_mandr_r("dppd", 66, src, dst); + DO_imm_mandr_r("dppd", 67, src, dst); + DO_imm_mandr_r("dppd", 68, src, dst); + DO_imm_mandr_r("dppd", 69, src, dst); + DO_imm_mandr_r("dppd", 70, src, dst); + DO_imm_mandr_r("dppd", 71, src, dst); + DO_imm_mandr_r("dppd", 72, src, dst); + DO_imm_mandr_r("dppd", 73, src, dst); + DO_imm_mandr_r("dppd", 74, src, dst); + DO_imm_mandr_r("dppd", 75, src, dst); + DO_imm_mandr_r("dppd", 76, src, dst); + DO_imm_mandr_r("dppd", 77, src, dst); + DO_imm_mandr_r("dppd", 78, src, dst); + DO_imm_mandr_r("dppd", 79, src, dst); + DO_imm_mandr_r("dppd", 80, src, dst); + DO_imm_mandr_r("dppd", 81, src, dst); + DO_imm_mandr_r("dppd", 82, src, dst); + DO_imm_mandr_r("dppd", 83, src, dst); + DO_imm_mandr_r("dppd", 84, src, dst); + DO_imm_mandr_r("dppd", 85, src, dst); + DO_imm_mandr_r("dppd", 86, src, dst); + DO_imm_mandr_r("dppd", 87, src, dst); + DO_imm_mandr_r("dppd", 88, src, dst); + DO_imm_mandr_r("dppd", 89, src, dst); + DO_imm_mandr_r("dppd", 90, src, dst); + DO_imm_mandr_r("dppd", 91, src, dst); + DO_imm_mandr_r("dppd", 92, src, dst); + DO_imm_mandr_r("dppd", 93, src, dst); + DO_imm_mandr_r("dppd", 94, src, dst); + DO_imm_mandr_r("dppd", 95, src, dst); + DO_imm_mandr_r("dppd", 96, src, dst); + DO_imm_mandr_r("dppd", 97, src, dst); + DO_imm_mandr_r("dppd", 98, src, dst); + DO_imm_mandr_r("dppd", 99, src, dst); + DO_imm_mandr_r("dppd", 100, src, dst); + DO_imm_mandr_r("dppd", 101, src, dst); + DO_imm_mandr_r("dppd", 102, src, dst); + DO_imm_mandr_r("dppd", 103, src, dst); + DO_imm_mandr_r("dppd", 104, src, dst); + DO_imm_mandr_r("dppd", 105, src, dst); + DO_imm_mandr_r("dppd", 106, src, dst); + DO_imm_mandr_r("dppd", 107, src, dst); + DO_imm_mandr_r("dppd", 108, src, dst); + DO_imm_mandr_r("dppd", 109, src, dst); + DO_imm_mandr_r("dppd", 110, src, dst); + DO_imm_mandr_r("dppd", 111, src, dst); + DO_imm_mandr_r("dppd", 112, src, dst); + DO_imm_mandr_r("dppd", 113, src, dst); + DO_imm_mandr_r("dppd", 114, src, dst); + DO_imm_mandr_r("dppd", 115, src, dst); + DO_imm_mandr_r("dppd", 116, src, dst); + DO_imm_mandr_r("dppd", 117, src, dst); + DO_imm_mandr_r("dppd", 118, src, dst); + DO_imm_mandr_r("dppd", 119, src, dst); + DO_imm_mandr_r("dppd", 120, src, dst); + DO_imm_mandr_r("dppd", 121, src, dst); + DO_imm_mandr_r("dppd", 122, src, dst); + DO_imm_mandr_r("dppd", 123, src, dst); + DO_imm_mandr_r("dppd", 124, src, dst); + DO_imm_mandr_r("dppd", 125, src, dst); + DO_imm_mandr_r("dppd", 126, src, dst); + DO_imm_mandr_r("dppd", 127, src, dst); + DO_imm_mandr_r("dppd", 128, src, dst); + DO_imm_mandr_r("dppd", 129, src, dst); + DO_imm_mandr_r("dppd", 130, src, dst); + DO_imm_mandr_r("dppd", 131, src, dst); + DO_imm_mandr_r("dppd", 132, src, dst); + DO_imm_mandr_r("dppd", 133, src, dst); + DO_imm_mandr_r("dppd", 134, src, dst); + DO_imm_mandr_r("dppd", 135, src, dst); + DO_imm_mandr_r("dppd", 136, src, dst); + DO_imm_mandr_r("dppd", 137, src, dst); + DO_imm_mandr_r("dppd", 138, src, dst); + DO_imm_mandr_r("dppd", 139, src, dst); + DO_imm_mandr_r("dppd", 140, src, dst); + DO_imm_mandr_r("dppd", 141, src, dst); + DO_imm_mandr_r("dppd", 142, src, dst); + DO_imm_mandr_r("dppd", 143, src, dst); + DO_imm_mandr_r("dppd", 144, src, dst); + DO_imm_mandr_r("dppd", 145, src, dst); + DO_imm_mandr_r("dppd", 146, src, dst); + DO_imm_mandr_r("dppd", 147, src, dst); + DO_imm_mandr_r("dppd", 148, src, dst); + DO_imm_mandr_r("dppd", 149, src, dst); + DO_imm_mandr_r("dppd", 150, src, dst); + DO_imm_mandr_r("dppd", 151, src, dst); + DO_imm_mandr_r("dppd", 152, src, dst); + DO_imm_mandr_r("dppd", 153, src, dst); + DO_imm_mandr_r("dppd", 154, src, dst); + DO_imm_mandr_r("dppd", 155, src, dst); + DO_imm_mandr_r("dppd", 156, src, dst); + DO_imm_mandr_r("dppd", 157, src, dst); + DO_imm_mandr_r("dppd", 158, src, dst); + DO_imm_mandr_r("dppd", 159, src, dst); + DO_imm_mandr_r("dppd", 160, src, dst); + DO_imm_mandr_r("dppd", 161, src, dst); + DO_imm_mandr_r("dppd", 162, src, dst); + DO_imm_mandr_r("dppd", 163, src, dst); + DO_imm_mandr_r("dppd", 164, src, dst); + DO_imm_mandr_r("dppd", 165, src, dst); + DO_imm_mandr_r("dppd", 166, src, dst); + DO_imm_mandr_r("dppd", 167, src, dst); + DO_imm_mandr_r("dppd", 168, src, dst); + DO_imm_mandr_r("dppd", 169, src, dst); + DO_imm_mandr_r("dppd", 170, src, dst); + DO_imm_mandr_r("dppd", 171, src, dst); + DO_imm_mandr_r("dppd", 172, src, dst); + DO_imm_mandr_r("dppd", 173, src, dst); + DO_imm_mandr_r("dppd", 174, src, dst); + DO_imm_mandr_r("dppd", 175, src, dst); + DO_imm_mandr_r("dppd", 176, src, dst); + DO_imm_mandr_r("dppd", 177, src, dst); + DO_imm_mandr_r("dppd", 178, src, dst); + DO_imm_mandr_r("dppd", 179, src, dst); + DO_imm_mandr_r("dppd", 180, src, dst); + DO_imm_mandr_r("dppd", 181, src, dst); + DO_imm_mandr_r("dppd", 182, src, dst); + DO_imm_mandr_r("dppd", 183, src, dst); + DO_imm_mandr_r("dppd", 184, src, dst); + DO_imm_mandr_r("dppd", 185, src, dst); + DO_imm_mandr_r("dppd", 186, src, dst); + DO_imm_mandr_r("dppd", 187, src, dst); + DO_imm_mandr_r("dppd", 188, src, dst); + DO_imm_mandr_r("dppd", 189, src, dst); + DO_imm_mandr_r("dppd", 190, src, dst); + DO_imm_mandr_r("dppd", 191, src, dst); + DO_imm_mandr_r("dppd", 192, src, dst); + DO_imm_mandr_r("dppd", 193, src, dst); + DO_imm_mandr_r("dppd", 194, src, dst); + DO_imm_mandr_r("dppd", 195, src, dst); + DO_imm_mandr_r("dppd", 196, src, dst); + DO_imm_mandr_r("dppd", 197, src, dst); + DO_imm_mandr_r("dppd", 198, src, dst); + DO_imm_mandr_r("dppd", 199, src, dst); + DO_imm_mandr_r("dppd", 200, src, dst); + DO_imm_mandr_r("dppd", 201, src, dst); + DO_imm_mandr_r("dppd", 202, src, dst); + DO_imm_mandr_r("dppd", 203, src, dst); + DO_imm_mandr_r("dppd", 204, src, dst); + DO_imm_mandr_r("dppd", 205, src, dst); + DO_imm_mandr_r("dppd", 206, src, dst); + DO_imm_mandr_r("dppd", 207, src, dst); + DO_imm_mandr_r("dppd", 208, src, dst); + DO_imm_mandr_r("dppd", 209, src, dst); + DO_imm_mandr_r("dppd", 210, src, dst); + DO_imm_mandr_r("dppd", 211, src, dst); + DO_imm_mandr_r("dppd", 212, src, dst); + DO_imm_mandr_r("dppd", 213, src, dst); + DO_imm_mandr_r("dppd", 214, src, dst); + DO_imm_mandr_r("dppd", 215, src, dst); + DO_imm_mandr_r("dppd", 216, src, dst); + DO_imm_mandr_r("dppd", 217, src, dst); + DO_imm_mandr_r("dppd", 218, src, dst); + DO_imm_mandr_r("dppd", 219, src, dst); + DO_imm_mandr_r("dppd", 220, src, dst); + DO_imm_mandr_r("dppd", 221, src, dst); + DO_imm_mandr_r("dppd", 222, src, dst); + DO_imm_mandr_r("dppd", 223, src, dst); + DO_imm_mandr_r("dppd", 224, src, dst); + DO_imm_mandr_r("dppd", 225, src, dst); + DO_imm_mandr_r("dppd", 226, src, dst); + DO_imm_mandr_r("dppd", 227, src, dst); + DO_imm_mandr_r("dppd", 228, src, dst); + DO_imm_mandr_r("dppd", 229, src, dst); + DO_imm_mandr_r("dppd", 230, src, dst); + DO_imm_mandr_r("dppd", 231, src, dst); + DO_imm_mandr_r("dppd", 232, src, dst); + DO_imm_mandr_r("dppd", 233, src, dst); + DO_imm_mandr_r("dppd", 234, src, dst); + DO_imm_mandr_r("dppd", 235, src, dst); + DO_imm_mandr_r("dppd", 236, src, dst); + DO_imm_mandr_r("dppd", 237, src, dst); + DO_imm_mandr_r("dppd", 238, src, dst); + DO_imm_mandr_r("dppd", 239, src, dst); + DO_imm_mandr_r("dppd", 240, src, dst); + DO_imm_mandr_r("dppd", 241, src, dst); + DO_imm_mandr_r("dppd", 242, src, dst); + DO_imm_mandr_r("dppd", 243, src, dst); + DO_imm_mandr_r("dppd", 244, src, dst); + DO_imm_mandr_r("dppd", 245, src, dst); + DO_imm_mandr_r("dppd", 246, src, dst); + DO_imm_mandr_r("dppd", 247, src, dst); + DO_imm_mandr_r("dppd", 248, src, dst); + DO_imm_mandr_r("dppd", 249, src, dst); + DO_imm_mandr_r("dppd", 250, src, dst); + DO_imm_mandr_r("dppd", 251, src, dst); + DO_imm_mandr_r("dppd", 252, src, dst); + DO_imm_mandr_r("dppd", 253, src, dst); + DO_imm_mandr_r("dppd", 254, src, dst); + DO_imm_mandr_r("dppd", 255, src, dst); + } +} + +void test_DPPS ( void ) +{ + V128 src, dst; + { + *(float*)(&src[0]) = 1.2; + *(float*)(&src[4]) = -3.4; + *(float*)(&src[8]) = -6.7; + *(float*)(&src[12]) = 8.9; + *(float*)(&dst[0]) = -10.11; + *(float*)(&dst[4]) = 12.13; + *(float*)(&dst[8]) = 14.15; + *(float*)(&dst[12]) = -16.17; + DO_imm_mandr_r("dpps", 0, src, dst); + DO_imm_mandr_r("dpps", 1, src, dst); + DO_imm_mandr_r("dpps", 2, src, dst); + DO_imm_mandr_r("dpps", 3, src, dst); + DO_imm_mandr_r("dpps", 4, src, dst); + DO_imm_mandr_r("dpps", 5, src, dst); + DO_imm_mandr_r("dpps", 6, src, dst); + DO_imm_mandr_r("dpps", 7, src, dst); + DO_imm_mandr_r("dpps", 8, src, dst); + DO_imm_mandr_r("dpps", 9, src, dst); + DO_imm_mandr_r("dpps", 10, src, dst); + DO_imm_mandr_r("dpps", 11, src, dst); + DO_imm_mandr_r("dpps", 12, src, dst); + DO_imm_mandr_r("dpps", 13, src, dst); + DO_imm_mandr_r("dpps", 14, src, dst); + DO_imm_mandr_r("dpps", 15, src, dst); + DO_imm_mandr_r("dpps", 16, src, dst); + DO_imm_mandr_r("dpps", 17, src, dst); + DO_imm_mandr_r("dpps", 18, src, dst); + DO_imm_mandr_r("dpps", 19, src, dst); + DO_imm_mandr_r("dpps", 20, src, dst); + DO_imm_mandr_r("dpps", 21, src, dst); + DO_imm_mandr_r("dpps", 22, src, dst); + DO_imm_mandr_r("dpps", 23, src, dst); + DO_imm_mandr_r("dpps", 24, src, dst); + DO_imm_mandr_r("dpps", 25, src, dst); + DO_imm_mandr_r("dpps", 26, src, dst); + DO_imm_mandr_r("dpps", 27, src, dst); + DO_imm_mandr_r("dpps", 28, src, dst); + DO_imm_mandr_r("dpps", 29, src, dst); + DO_imm_mandr_r("dpps", 30, src, dst); + DO_imm_mandr_r("dpps", 31, src, dst); + DO_imm_mandr_r("dpps", 32, src, dst); + DO_imm_mandr_r("dpps", 33, src, dst); + DO_imm_mandr_r("dpps", 34, src, dst); + DO_imm_mandr_r("dpps", 35, src, dst); + DO_imm_mandr_r("dpps", 36, src, dst); + DO_imm_mandr_r("dpps", 37, src, dst); + DO_imm_mandr_r("dpps", 38, src, dst); + DO_imm_mandr_r("dpps", 39, src, dst); + DO_imm_mandr_r("dpps", 40, src, dst); + DO_imm_mandr_r("dpps", 41, src, dst); + DO_imm_mandr_r("dpps", 42, src, dst); + DO_imm_mandr_r("dpps", 43, src, dst); + DO_imm_mandr_r("dpps", 44, src, dst); + DO_imm_mandr_r("dpps", 45, src, dst); + DO_imm_mandr_r("dpps", 46, src, dst); + DO_imm_mandr_r("dpps", 47, src, dst); + DO_imm_mandr_r("dpps", 48, src, dst); + DO_imm_mandr_r("dpps", 49, src, dst); + DO_imm_mandr_r("dpps", 50, src, dst); + DO_imm_mandr_r("dpps", 51, src, dst); + DO_imm_mandr_r("dpps", 52, src, dst); + DO_imm_mandr_r("dpps", 53, src, dst); + DO_imm_mandr_r("dpps", 54, src, dst); + DO_imm_mandr_r("dpps", 55, src, dst); + DO_imm_mandr_r("dpps", 56, src, dst); + DO_imm_mandr_r("dpps", 57, src, dst); + DO_imm_mandr_r("dpps", 58, src, dst); + DO_imm_mandr_r("dpps", 59, src, dst); + DO_imm_mandr_r("dpps", 60, src, dst); + DO_imm_mandr_r("dpps", 61, src, dst); + DO_imm_mandr_r("dpps", 62, src, dst); + DO_imm_mandr_r("dpps", 63, src, dst); + DO_imm_mandr_r("dpps", 64, src, dst); + DO_imm_mandr_r("dpps", 65, src, dst); + DO_imm_mandr_r("dpps", 66, src, dst); + DO_imm_mandr_r("dpps", 67, src, dst); + DO_imm_mandr_r("dpps", 68, src, dst); + DO_imm_mandr_r("dpps", 69, src, dst); + DO_imm_mandr_r("dpps", 70, src, dst); + DO_imm_mandr_r("dpps", 71, src, dst); + DO_imm_mandr_r("dpps", 72, src, dst); + DO_imm_mandr_r("dpps", 73, src, dst); + DO_imm_mandr_r("dpps", 74, src, dst); + DO_imm_mandr_r("dpps", 75, src, dst); + DO_imm_mandr_r("dpps", 76, src, dst); + DO_imm_mandr_r("dpps", 77, src, dst); + DO_imm_mandr_r("dpps", 78, src, dst); + DO_imm_mandr_r("dpps", 79, src, dst); + DO_imm_mandr_r("dpps", 80, src, dst); + DO_imm_mandr_r("dpps", 81, src, dst); + DO_imm_mandr_r("dpps", 82, src, dst); + DO_imm_mandr_r("dpps", 83, src, dst); + DO_imm_mandr_r("dpps", 84, src, dst); + DO_imm_mandr_r("dpps", 85, src, dst); + DO_imm_mandr_r("dpps", 86, src, dst); + DO_imm_mandr_r("dpps", 87, src, dst); + DO_imm_mandr_r("dpps", 88, src, dst); + DO_imm_mandr_r("dpps", 89, src, dst); + DO_imm_mandr_r("dpps", 90, src, dst); + DO_imm_mandr_r("dpps", 91, src, dst); + DO_imm_mandr_r("dpps", 92, src, dst); + DO_imm_mandr_r("dpps", 93, src, dst); + DO_imm_mandr_r("dpps", 94, src, dst); + DO_imm_mandr_r("dpps", 95, src, dst); + DO_imm_mandr_r("dpps", 96, src, dst); + DO_imm_mandr_r("dpps", 97, src, dst); + DO_imm_mandr_r("dpps", 98, src, dst); + DO_imm_mandr_r("dpps", 99, src, dst); + DO_imm_mandr_r("dpps", 100, src, dst); + DO_imm_mandr_r("dpps", 101, src, dst); + DO_imm_mandr_r("dpps", 102, src, dst); + DO_imm_mandr_r("dpps", 103, src, dst); + DO_imm_mandr_r("dpps", 104, src, dst); + DO_imm_mandr_r("dpps", 105, src, dst); + DO_imm_mandr_r("dpps", 106, src, dst); + DO_imm_mandr_r("dpps", 107, src, dst); + DO_imm_mandr_r("dpps", 108, src, dst); + DO_imm_mandr_r("dpps", 109, src, dst); + DO_imm_mandr_r("dpps", 110, src, dst); + DO_imm_mandr_r("dpps", 111, src, dst); + DO_imm_mandr_r("dpps", 112, src, dst); + DO_imm_mandr_r("dpps", 113, src, dst); + DO_imm_mandr_r("dpps", 114, src, dst); + DO_imm_mandr_r("dpps", 115, src, dst); + DO_imm_mandr_r("dpps", 116, src, dst); + DO_imm_mandr_r("dpps", 117, src, dst); + DO_imm_mandr_r("dpps", 118, src, dst); + DO_imm_mandr_r("dpps", 119, src, dst); + DO_imm_mandr_r("dpps", 120, src, dst); + DO_imm_mandr_r("dpps", 121, src, dst); + DO_imm_mandr_r("dpps", 122, src, dst); + DO_imm_mandr_r("dpps", 123, src, dst); + DO_imm_mandr_r("dpps", 124, src, dst); + DO_imm_mandr_r("dpps", 125, src, dst); + DO_imm_mandr_r("dpps", 126, src, dst); + DO_imm_mandr_r("dpps", 127, src, dst); + DO_imm_mandr_r("dpps", 128, src, dst); + DO_imm_mandr_r("dpps", 129, src, dst); + DO_imm_mandr_r("dpps", 130, src, dst); + DO_imm_mandr_r("dpps", 131, src, dst); + DO_imm_mandr_r("dpps", 132, src, dst); + DO_imm_mandr_r("dpps", 133, src, dst); + DO_imm_mandr_r("dpps", 134, src, dst); + DO_imm_mandr_r("dpps", 135, src, dst); + DO_imm_mandr_r("dpps", 136, src, dst); + DO_imm_mandr_r("dpps", 137, src, dst); + DO_imm_mandr_r("dpps", 138, src, dst); + DO_imm_mandr_r("dpps", 139, src, dst); + DO_imm_mandr_r("dpps", 140, src, dst); + DO_imm_mandr_r("dpps", 141, src, dst); + DO_imm_mandr_r("dpps", 142, src, dst); + DO_imm_mandr_r("dpps", 143, src, dst); + DO_imm_mandr_r("dpps", 144, src, dst); + DO_imm_mandr_r("dpps", 145, src, dst); + DO_imm_mandr_r("dpps", 146, src, dst); + DO_imm_mandr_r("dpps", 147, src, dst); + DO_imm_mandr_r("dpps", 148, src, dst); + DO_imm_mandr_r("dpps", 149, src, dst); + DO_imm_mandr_r("dpps", 150, src, dst); + DO_imm_mandr_r("dpps", 151, src, dst); + DO_imm_mandr_r("dpps", 152, src, dst); + DO_imm_mandr_r("dpps", 153, src, dst); + DO_imm_mandr_r("dpps", 154, src, dst); + DO_imm_mandr_r("dpps", 155, src, dst); + DO_imm_mandr_r("dpps", 156, src, dst); + DO_imm_mandr_r("dpps", 157, src, dst); + DO_imm_mandr_r("dpps", 158, src, dst); + DO_imm_mandr_r("dpps", 159, src, dst); + DO_imm_mandr_r("dpps", 160, src, dst); + DO_imm_mandr_r("dpps", 161, src, dst); + DO_imm_mandr_r("dpps", 162, src, dst); + DO_imm_mandr_r("dpps", 163, src, dst); + DO_imm_mandr_r("dpps", 164, src, dst); + DO_imm_mandr_r("dpps", 165, src, dst); + DO_imm_mandr_r("dpps", 166, src, dst); + DO_imm_mandr_r("dpps", 167, src, dst); + DO_imm_mandr_r("dpps", 168, src, dst); + DO_imm_mandr_r("dpps", 169, src, dst); + DO_imm_mandr_r("dpps", 170, src, dst); + DO_imm_mandr_r("dpps", 171, src, dst); + DO_imm_mandr_r("dpps", 172, src, dst); + DO_imm_mandr_r("dpps", 173, src, dst); + DO_imm_mandr_r("dpps", 174, src, dst); + DO_imm_mandr_r("dpps", 175, src, dst); + DO_imm_mandr_r("dpps", 176, src, dst); + DO_imm_mandr_r("dpps", 177, src, dst); + DO_imm_mandr_r("dpps", 178, src, dst); + DO_imm_mandr_r("dpps", 179, src, dst); + DO_imm_mandr_r("dpps", 180, src, dst); + DO_imm_mandr_r("dpps", 181, src, dst); + DO_imm_mandr_r("dpps", 182, src, dst); + DO_imm_mandr_r("dpps", 183, src, dst); + DO_imm_mandr_r("dpps", 184, src, dst); + DO_imm_mandr_r("dpps", 185, src, dst); + DO_imm_mandr_r("dpps", 186, src, dst); + DO_imm_mandr_r("dpps", 187, src, dst); + DO_imm_mandr_r("dpps", 188, src, dst); + DO_imm_mandr_r("dpps", 189, src, dst); + DO_imm_mandr_r("dpps", 190, src, dst); + DO_imm_mandr_r("dpps", 191, src, dst); + DO_imm_mandr_r("dpps", 192, src, dst); + DO_imm_mandr_r("dpps", 193, src, dst); + DO_imm_mandr_r("dpps", 194, src, dst); + DO_imm_mandr_r("dpps", 195, src, dst); + DO_imm_mandr_r("dpps", 196, src, dst); + DO_imm_mandr_r("dpps", 197, src, dst); + DO_imm_mandr_r("dpps", 198, src, dst); + DO_imm_mandr_r("dpps", 199, src, dst); + DO_imm_mandr_r("dpps", 200, src, dst); + DO_imm_mandr_r("dpps", 201, src, dst); + DO_imm_mandr_r("dpps", 202, src, dst); + DO_imm_mandr_r("dpps", 203, src, dst); + DO_imm_mandr_r("dpps", 204, src, dst); + DO_imm_mandr_r("dpps", 205, src, dst); + DO_imm_mandr_r("dpps", 206, src, dst); + DO_imm_mandr_r("dpps", 207, src, dst); + DO_imm_mandr_r("dpps", 208, src, dst); + DO_imm_mandr_r("dpps", 209, src, dst); + DO_imm_mandr_r("dpps", 210, src, dst); + DO_imm_mandr_r("dpps", 211, src, dst); + DO_imm_mandr_r("dpps", 212, src, dst); + DO_imm_mandr_r("dpps", 213, src, dst); + DO_imm_mandr_r("dpps", 214, src, dst); + DO_imm_mandr_r("dpps", 215, src, dst); + DO_imm_mandr_r("dpps", 216, src, dst); + DO_imm_mandr_r("dpps", 217, src, dst); + DO_imm_mandr_r("dpps", 218, src, dst); + DO_imm_mandr_r("dpps", 219, src, dst); + DO_imm_mandr_r("dpps", 220, src, dst); + DO_imm_mandr_r("dpps", 221, src, dst); + DO_imm_mandr_r("dpps", 222, src, dst); + DO_imm_mandr_r("dpps", 223, src, dst); + DO_imm_mandr_r("dpps", 224, src, dst); + DO_imm_mandr_r("dpps", 225, src, dst); + DO_imm_mandr_r("dpps", 226, src, dst); + DO_imm_mandr_r("dpps", 227, src, dst); + DO_imm_mandr_r("dpps", 228, src, dst); + DO_imm_mandr_r("dpps", 229, src, dst); + DO_imm_mandr_r("dpps", 230, src, dst); + DO_imm_mandr_r("dpps", 231, src, dst); + DO_imm_mandr_r("dpps", 232, src, dst); + DO_imm_mandr_r("dpps", 233, src, dst); + DO_imm_mandr_r("dpps", 234, src, dst); + DO_imm_mandr_r("dpps", 235, src, dst); + DO_imm_mandr_r("dpps", 236, src, dst); + DO_imm_mandr_r("dpps", 237, src, dst); + DO_imm_mandr_r("dpps", 238, src, dst); + DO_imm_mandr_r("dpps", 239, src, dst); + DO_imm_mandr_r("dpps", 240, src, dst); + DO_imm_mandr_r("dpps", 241, src, dst); + DO_imm_mandr_r("dpps", 242, src, dst); + DO_imm_mandr_r("dpps", 243, src, dst); + DO_imm_mandr_r("dpps", 244, src, dst); + DO_imm_mandr_r("dpps", 245, src, dst); + DO_imm_mandr_r("dpps", 246, src, dst); + DO_imm_mandr_r("dpps", 247, src, dst); + DO_imm_mandr_r("dpps", 248, src, dst); + DO_imm_mandr_r("dpps", 249, src, dst); + DO_imm_mandr_r("dpps", 250, src, dst); + DO_imm_mandr_r("dpps", 251, src, dst); + DO_imm_mandr_r("dpps", 252, src, dst); + DO_imm_mandr_r("dpps", 253, src, dst); + DO_imm_mandr_r("dpps", 254, src, dst); + DO_imm_mandr_r("dpps", 255, src, dst); + } +} + +void test_INSERTPS ( void ) +{ + V128 src, dst; + { + *(float*)(&src[0]) = 1.2; + *(float*)(&src[4]) = -3.4; + *(float*)(&src[8]) = -6.7; + *(float*)(&src[12]) = 8.9; + *(float*)(&dst[0]) = -10.11; + *(float*)(&dst[4]) = 12.13; + *(float*)(&dst[8]) = 14.15; + *(float*)(&dst[12]) = -16.17; + DO_imm_mandr_r("insertps", 0, src, dst); + DO_imm_mandr_r("insertps", 1, src, dst); + DO_imm_mandr_r("insertps", 2, src, dst); + DO_imm_mandr_r("insertps", 3, src, dst); + DO_imm_mandr_r("insertps", 4, src, dst); + DO_imm_mandr_r("insertps", 5, src, dst); + DO_imm_mandr_r("insertps", 6, src, dst); + DO_imm_mandr_r("insertps", 7, src, dst); + DO_imm_mandr_r("insertps", 8, src, dst); + DO_imm_mandr_r("insertps", 9, src, dst); + DO_imm_mandr_r("insertps", 10, src, dst); + DO_imm_mandr_r("insertps", 11, src, dst); + DO_imm_mandr_r("insertps", 12, src, dst); + DO_imm_mandr_r("insertps", 13, src, dst); + DO_imm_mandr_r("insertps", 14, src, dst); + DO_imm_mandr_r("insertps", 15, src, dst); + DO_imm_mandr_r("insertps", 16, src, dst); + DO_imm_mandr_r("insertps", 17, src, dst); + DO_imm_mandr_r("insertps", 18, src, dst); + DO_imm_mandr_r("insertps", 19, src, dst); + DO_imm_mandr_r("insertps", 20, src, dst); + DO_imm_mandr_r("insertps", 21, src, dst); + DO_imm_mandr_r("insertps", 22, src, dst); + DO_imm_mandr_r("insertps", 23, src, dst); + DO_imm_mandr_r("insertps", 24, src, dst); + DO_imm_mandr_r("insertps", 25, src, dst); + DO_imm_mandr_r("insertps", 26, src, dst); + DO_imm_mandr_r("insertps", 27, src, dst); + DO_imm_mandr_r("insertps", 28, src, dst); + DO_imm_mandr_r("insertps", 29, src, dst); + DO_imm_mandr_r("insertps", 30, src, dst); + DO_imm_mandr_r("insertps", 31, src, dst); + DO_imm_mandr_r("insertps", 32, src, dst); + DO_imm_mandr_r("insertps", 33, src, dst); + DO_imm_mandr_r("insertps", 34, src, dst); + DO_imm_mandr_r("insertps", 35, src, dst); + DO_imm_mandr_r("insertps", 36, src, dst); + DO_imm_mandr_r("insertps", 37, src, dst); + DO_imm_mandr_r("insertps", 38, src, dst); + DO_imm_mandr_r("insertps", 39, src, dst); + DO_imm_mandr_r("insertps", 40, src, dst); + DO_imm_mandr_r("insertps", 41, src, dst); + DO_imm_mandr_r("insertps", 42, src, dst); + DO_imm_mandr_r("insertps", 43, src, dst); + DO_imm_mandr_r("insertps", 44, src, dst); + DO_imm_mandr_r("insertps", 45, src, dst); + DO_imm_mandr_r("insertps", 46, src, dst); + DO_imm_mandr_r("insertps", 47, src, dst); + DO_imm_mandr_r("insertps", 48, src, dst); + DO_imm_mandr_r("insertps", 49, src, dst); + DO_imm_mandr_r("insertps", 50, src, dst); + DO_imm_mandr_r("insertps", 51, src, dst); + DO_imm_mandr_r("insertps", 52, src, dst); + DO_imm_mandr_r("insertps", 53, src, dst); + DO_imm_mandr_r("insertps", 54, src, dst); + DO_imm_mandr_r("insertps", 55, src, dst); + DO_imm_mandr_r("insertps", 56, src, dst); + DO_imm_mandr_r("insertps", 57, src, dst); + DO_imm_mandr_r("insertps", 58, src, dst); + DO_imm_mandr_r("insertps", 59, src, dst); + DO_imm_mandr_r("insertps", 60, src, dst); + DO_imm_mandr_r("insertps", 61, src, dst); + DO_imm_mandr_r("insertps", 62, src, dst); + DO_imm_mandr_r("insertps", 63, src, dst); + DO_imm_mandr_r("insertps", 64, src, dst); + DO_imm_mandr_r("insertps", 65, src, dst); + DO_imm_mandr_r("insertps", 66, src, dst); + DO_imm_mandr_r("insertps", 67, src, dst); + DO_imm_mandr_r("insertps", 68, src, dst); + DO_imm_mandr_r("insertps", 69, src, dst); + DO_imm_mandr_r("insertps", 70, src, dst); + DO_imm_mandr_r("insertps", 71, src, dst); + DO_imm_mandr_r("insertps", 72, src, dst); + DO_imm_mandr_r("insertps", 73, src, dst); + DO_imm_mandr_r("insertps", 74, src, dst); + DO_imm_mandr_r("insertps", 75, src, dst); + DO_imm_mandr_r("insertps", 76, src, dst); + DO_imm_mandr_r("insertps", 77, src, dst); + DO_imm_mandr_r("insertps", 78, src, dst); + DO_imm_mandr_r("insertps", 79, src, dst); + DO_imm_mandr_r("insertps", 80, src, dst); + DO_imm_mandr_r("insertps", 81, src, dst); + DO_imm_mandr_r("insertps", 82, src, dst); + DO_imm_mandr_r("insertps", 83, src, dst); + DO_imm_mandr_r("insertps", 84, src, dst); + DO_imm_mandr_r("insertps", 85, src, dst); + DO_imm_mandr_r("insertps", 86, src, dst); + DO_imm_mandr_r("insertps", 87, src, dst); + DO_imm_mandr_r("insertps", 88, src, dst); + DO_imm_mandr_r("insertps", 89, src, dst); + DO_imm_mandr_r("insertps", 90, src, dst); + DO_imm_mandr_r("insertps", 91, src, dst); + DO_imm_mandr_r("insertps", 92, src, dst); + DO_imm_mandr_r("insertps", 93, src, dst); + DO_imm_mandr_r("insertps", 94, src, dst); + DO_imm_mandr_r("insertps", 95, src, dst); + DO_imm_mandr_r("insertps", 96, src, dst); + DO_imm_mandr_r("insertps", 97, src, dst); + DO_imm_mandr_r("insertps", 98, src, dst); + DO_imm_mandr_r("insertps", 99, src, dst); + DO_imm_mandr_r("insertps", 100, src, dst); + DO_imm_mandr_r("insertps", 101, src, dst); + DO_imm_mandr_r("insertps", 102, src, dst); + DO_imm_mandr_r("insertps", 103, src, dst); + DO_imm_mandr_r("insertps", 104, src, dst); + DO_imm_mandr_r("insertps", 105, src, dst); + DO_imm_mandr_r("insertps", 106, src, dst); + DO_imm_mandr_r("insertps", 107, src, dst); + DO_imm_mandr_r("insertps", 108, src, dst); + DO_imm_mandr_r("insertps", 109, src, dst); + DO_imm_mandr_r("insertps", 110, src, dst); + DO_imm_mandr_r("insertps", 111, src, dst); + DO_imm_mandr_r("insertps", 112, src, dst); + DO_imm_mandr_r("insertps", 113, src, dst); + DO_imm_mandr_r("insertps", 114, src, dst); + DO_imm_mandr_r("insertps", 115, src, dst); + DO_imm_mandr_r("insertps", 116, src, dst); + DO_imm_mandr_r("insertps", 117, src, dst); + DO_imm_mandr_r("insertps", 118, src, dst); + DO_imm_mandr_r("insertps", 119, src, dst); + DO_imm_mandr_r("insertps", 120, src, dst); + DO_imm_mandr_r("insertps", 121, src, dst); + DO_imm_mandr_r("insertps", 122, src, dst); + DO_imm_mandr_r("insertps", 123, src, dst); + DO_imm_mandr_r("insertps", 124, src, dst); + DO_imm_mandr_r("insertps", 125, src, dst); + DO_imm_mandr_r("insertps", 126, src, dst); + DO_imm_mandr_r("insertps", 127, src, dst); + DO_imm_mandr_r("insertps", 128, src, dst); + DO_imm_mandr_r("insertps", 129, src, dst); + DO_imm_mandr_r("insertps", 130, src, dst); + DO_imm_mandr_r("insertps", 131, src, dst); + DO_imm_mandr_r("insertps", 132, src, dst); + DO_imm_mandr_r("insertps", 133, src, dst); + DO_imm_mandr_r("insertps", 134, src, dst); + DO_imm_mandr_r("insertps", 135, src, dst); + DO_imm_mandr_r("insertps", 136, src, dst); + DO_imm_mandr_r("insertps", 137, src, dst); + DO_imm_mandr_r("insertps", 138, src, dst); + DO_imm_mandr_r("insertps", 139, src, dst); + DO_imm_mandr_r("insertps", 140, src, dst); + DO_imm_mandr_r("insertps", 141, src, dst); + DO_imm_mandr_r("insertps", 142, src, dst); + DO_imm_mandr_r("insertps", 143, src, dst); + DO_imm_mandr_r("insertps", 144, src, dst); + DO_imm_mandr_r("insertps", 145, src, dst); + DO_imm_mandr_r("insertps", 146, src, dst); + DO_imm_mandr_r("insertps", 147, src, dst); + DO_imm_mandr_r("insertps", 148, src, dst); + DO_imm_mandr_r("insertps", 149, src, dst); + DO_imm_mandr_r("insertps", 150, src, dst); + DO_imm_mandr_r("insertps", 151, src, dst); + DO_imm_mandr_r("insertps", 152, src, dst); + DO_imm_mandr_r("insertps", 153, src, dst); + DO_imm_mandr_r("insertps", 154, src, dst); + DO_imm_mandr_r("insertps", 155, src, dst); + DO_imm_mandr_r("insertps", 156, src, dst); + DO_imm_mandr_r("insertps", 157, src, dst); + DO_imm_mandr_r("insertps", 158, src, dst); + DO_imm_mandr_r("insertps", 159, src, dst); + DO_imm_mandr_r("insertps", 160, src, dst); + DO_imm_mandr_r("insertps", 161, src, dst); + DO_imm_mandr_r("insertps", 162, src, dst); + DO_imm_mandr_r("insertps", 163, src, dst); + DO_imm_mandr_r("insertps", 164, src, dst); + DO_imm_mandr_r("insertps", 165, src, dst); + DO_imm_mandr_r("insertps", 166, src, dst); + DO_imm_mandr_r("insertps", 167, src, dst); + DO_imm_mandr_r("insertps", 168, src, dst); + DO_imm_mandr_r("insertps", 169, src, dst); + DO_imm_mandr_r("insertps", 170, src, dst); + DO_imm_mandr_r("insertps", 171, src, dst); + DO_imm_mandr_r("insertps", 172, src, dst); + DO_imm_mandr_r("insertps", 173, src, dst); + DO_imm_mandr_r("insertps", 174, src, dst); + DO_imm_mandr_r("insertps", 175, src, dst); + DO_imm_mandr_r("insertps", 176, src, dst); + DO_imm_mandr_r("insertps", 177, src, dst); + DO_imm_mandr_r("insertps", 178, src, dst); + DO_imm_mandr_r("insertps", 179, src, dst); + DO_imm_mandr_r("insertps", 180, src, dst); + DO_imm_mandr_r("insertps", 181, src, dst); + DO_imm_mandr_r("insertps", 182, src, dst); + DO_imm_mandr_r("insertps", 183, src, dst); + DO_imm_mandr_r("insertps", 184, src, dst); + DO_imm_mandr_r("insertps", 185, src, dst); + DO_imm_mandr_r("insertps", 186, src, dst); + DO_imm_mandr_r("insertps", 187, src, dst); + DO_imm_mandr_r("insertps", 188, src, dst); + DO_imm_mandr_r("insertps", 189, src, dst); + DO_imm_mandr_r("insertps", 190, src, dst); + DO_imm_mandr_r("insertps", 191, src, dst); + DO_imm_mandr_r("insertps", 192, src, dst); + DO_imm_mandr_r("insertps", 193, src, dst); + DO_imm_mandr_r("insertps", 194, src, dst); + DO_imm_mandr_r("insertps", 195, src, dst); + DO_imm_mandr_r("insertps", 196, src, dst); + DO_imm_mandr_r("insertps", 197, src, dst); + DO_imm_mandr_r("insertps", 198, src, dst); + DO_imm_mandr_r("insertps", 199, src, dst); + DO_imm_mandr_r("insertps", 200, src, dst); + DO_imm_mandr_r("insertps", 201, src, dst); + DO_imm_mandr_r("insertps", 202, src, dst); + DO_imm_mandr_r("insertps", 203, src, dst); + DO_imm_mandr_r("insertps", 204, src, dst); + DO_imm_mandr_r("insertps", 205, src, dst); + DO_imm_mandr_r("insertps", 206, src, dst); + DO_imm_mandr_r("insertps", 207, src, dst); + DO_imm_mandr_r("insertps", 208, src, dst); + DO_imm_mandr_r("insertps", 209, src, dst); + DO_imm_mandr_r("insertps", 210, src, dst); + DO_imm_mandr_r("insertps", 211, src, dst); + DO_imm_mandr_r("insertps", 212, src, dst); + DO_imm_mandr_r("insertps", 213, src, dst); + DO_imm_mandr_r("insertps", 214, src, dst); + DO_imm_mandr_r("insertps", 215, src, dst); + DO_imm_mandr_r("insertps", 216, src, dst); + DO_imm_mandr_r("insertps", 217, src, dst); + DO_imm_mandr_r("insertps", 218, src, dst); + DO_imm_mandr_r("insertps", 219, src, dst); + DO_imm_mandr_r("insertps", 220, src, dst); + DO_imm_mandr_r("insertps", 221, src, dst); + DO_imm_mandr_r("insertps", 222, src, dst); + DO_imm_mandr_r("insertps", 223, src, dst); + DO_imm_mandr_r("insertps", 224, src, dst); + DO_imm_mandr_r("insertps", 225, src, dst); + DO_imm_mandr_r("insertps", 226, src, dst); + DO_imm_mandr_r("insertps", 227, src, dst); + DO_imm_mandr_r("insertps", 228, src, dst); + DO_imm_mandr_r("insertps", 229, src, dst); + DO_imm_mandr_r("insertps", 230, src, dst); + DO_imm_mandr_r("insertps", 231, src, dst); + DO_imm_mandr_r("insertps", 232, src, dst); + DO_imm_mandr_r("insertps", 233, src, dst); + DO_imm_mandr_r("insertps", 234, src, dst); + DO_imm_mandr_r("insertps", 235, src, dst); + DO_imm_mandr_r("insertps", 236, src, dst); + DO_imm_mandr_r("insertps", 237, src, dst); + DO_imm_mandr_r("insertps", 238, src, dst); + DO_imm_mandr_r("insertps", 239, src, dst); + DO_imm_mandr_r("insertps", 240, src, dst); + DO_imm_mandr_r("insertps", 241, src, dst); + DO_imm_mandr_r("insertps", 242, src, dst); + DO_imm_mandr_r("insertps", 243, src, dst); + DO_imm_mandr_r("insertps", 244, src, dst); + DO_imm_mandr_r("insertps", 245, src, dst); + DO_imm_mandr_r("insertps", 246, src, dst); + DO_imm_mandr_r("insertps", 247, src, dst); + DO_imm_mandr_r("insertps", 248, src, dst); + DO_imm_mandr_r("insertps", 249, src, dst); + DO_imm_mandr_r("insertps", 250, src, dst); + DO_imm_mandr_r("insertps", 251, src, dst); + DO_imm_mandr_r("insertps", 252, src, dst); + DO_imm_mandr_r("insertps", 253, src, dst); + DO_imm_mandr_r("insertps", 254, src, dst); + DO_imm_mandr_r("insertps", 255, src, dst); + } +} + +void test_MPSADBW ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_imm_mandr_r("mpsadbw", 0, src, dst); + DO_imm_mandr_r("mpsadbw", 1, src, dst); + DO_imm_mandr_r("mpsadbw", 2, src, dst); + DO_imm_mandr_r("mpsadbw", 3, src, dst); + DO_imm_mandr_r("mpsadbw", 4, src, dst); + DO_imm_mandr_r("mpsadbw", 5, src, dst); + DO_imm_mandr_r("mpsadbw", 6, src, dst); + DO_imm_mandr_r("mpsadbw", 7, src, dst); + } +} + +void test_PACKUSDW ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + if (i < 9) { + randV128(&src); + randV128(&dst); + } else { + memset(&src, 0, sizeof(src)); + memset(&dst, 0, sizeof(src)); + src[0] = 0x11; src[1] = 0x22; + src[4] = 0x33; src[5] = 0x44; + src[8] = 0x55; src[9] = 0x66; + src[12] = 0x77; src[13] = 0x88; + dst[0] = 0xaa; dst[1] = 0xbb; + dst[4] = 0xcc; dst[5] = 0xdd; + dst[8] = 0xee; dst[9] = 0xff; + dst[12] = 0xa1; dst[13] = 0xb2; + } + DO_mandr_r("packusdw", src, dst); + } +} + +void test_PBLENDW ( void ) +{ + V128 src, dst; + randV128(&src); + randV128(&dst); + { + DO_imm_mandr_r("pblendw", 0, src, dst); + DO_imm_mandr_r("pblendw", 1, src, dst); + DO_imm_mandr_r("pblendw", 2, src, dst); + DO_imm_mandr_r("pblendw", 3, src, dst); + DO_imm_mandr_r("pblendw", 4, src, dst); + DO_imm_mandr_r("pblendw", 5, src, dst); + DO_imm_mandr_r("pblendw", 6, src, dst); + DO_imm_mandr_r("pblendw", 7, src, dst); + DO_imm_mandr_r("pblendw", 8, src, dst); + DO_imm_mandr_r("pblendw", 9, src, dst); + DO_imm_mandr_r("pblendw", 10, src, dst); + DO_imm_mandr_r("pblendw", 11, src, dst); + DO_imm_mandr_r("pblendw", 12, src, dst); + DO_imm_mandr_r("pblendw", 13, src, dst); + DO_imm_mandr_r("pblendw", 14, src, dst); + DO_imm_mandr_r("pblendw", 15, src, dst); + DO_imm_mandr_r("pblendw", 16, src, dst); + DO_imm_mandr_r("pblendw", 17, src, dst); + DO_imm_mandr_r("pblendw", 18, src, dst); + DO_imm_mandr_r("pblendw", 19, src, dst); + DO_imm_mandr_r("pblendw", 20, src, dst); + DO_imm_mandr_r("pblendw", 21, src, dst); + DO_imm_mandr_r("pblendw", 22, src, dst); + DO_imm_mandr_r("pblendw", 23, src, dst); + DO_imm_mandr_r("pblendw", 24, src, dst); + DO_imm_mandr_r("pblendw", 25, src, dst); + DO_imm_mandr_r("pblendw", 26, src, dst); + DO_imm_mandr_r("pblendw", 27, src, dst); + DO_imm_mandr_r("pblendw", 28, src, dst); + DO_imm_mandr_r("pblendw", 29, src, dst); + DO_imm_mandr_r("pblendw", 30, src, dst); + DO_imm_mandr_r("pblendw", 31, src, dst); + DO_imm_mandr_r("pblendw", 32, src, dst); + DO_imm_mandr_r("pblendw", 33, src, dst); + DO_imm_mandr_r("pblendw", 34, src, dst); + DO_imm_mandr_r("pblendw", 35, src, dst); + DO_imm_mandr_r("pblendw", 36, src, dst); + DO_imm_mandr_r("pblendw", 37, src, dst); + DO_imm_mandr_r("pblendw", 38, src, dst); + DO_imm_mandr_r("pblendw", 39, src, dst); + DO_imm_mandr_r("pblendw", 40, src, dst); + DO_imm_mandr_r("pblendw", 41, src, dst); + DO_imm_mandr_r("pblendw", 42, src, dst); + DO_imm_mandr_r("pblendw", 43, src, dst); + DO_imm_mandr_r("pblendw", 44, src, dst); + DO_imm_mandr_r("pblendw", 45, src, dst); + DO_imm_mandr_r("pblendw", 46, src, dst); + DO_imm_mandr_r("pblendw", 47, src, dst); + DO_imm_mandr_r("pblendw", 48, src, dst); + DO_imm_mandr_r("pblendw", 49, src, dst); + DO_imm_mandr_r("pblendw", 50, src, dst); + DO_imm_mandr_r("pblendw", 51, src, dst); + DO_imm_mandr_r("pblendw", 52, src, dst); + DO_imm_mandr_r("pblendw", 53, src, dst); + DO_imm_mandr_r("pblendw", 54, src, dst); + DO_imm_mandr_r("pblendw", 55, src, dst); + DO_imm_mandr_r("pblendw", 56, src, dst); + DO_imm_mandr_r("pblendw", 57, src, dst); + DO_imm_mandr_r("pblendw", 58, src, dst); + DO_imm_mandr_r("pblendw", 59, src, dst); + DO_imm_mandr_r("pblendw", 60, src, dst); + DO_imm_mandr_r("pblendw", 61, src, dst); + DO_imm_mandr_r("pblendw", 62, src, dst); + DO_imm_mandr_r("pblendw", 63, src, dst); + DO_imm_mandr_r("pblendw", 64, src, dst); + DO_imm_mandr_r("pblendw", 65, src, dst); + DO_imm_mandr_r("pblendw", 66, src, dst); + DO_imm_mandr_r("pblendw", 67, src, dst); + DO_imm_mandr_r("pblendw", 68, src, dst); + DO_imm_mandr_r("pblendw", 69, src, dst); + DO_imm_mandr_r("pblendw", 70, src, dst); + DO_imm_mandr_r("pblendw", 71, src, dst); + DO_imm_mandr_r("pblendw", 72, src, dst); + DO_imm_mandr_r("pblendw", 73, src, dst); + DO_imm_mandr_r("pblendw", 74, src, dst); + DO_imm_mandr_r("pblendw", 75, src, dst); + DO_imm_mandr_r("pblendw", 76, src, dst); + DO_imm_mandr_r("pblendw", 77, src, dst); + DO_imm_mandr_r("pblendw", 78, src, dst); + DO_imm_mandr_r("pblendw", 79, src, dst); + DO_imm_mandr_r("pblendw", 80, src, dst); + DO_imm_mandr_r("pblendw", 81, src, dst); + DO_imm_mandr_r("pblendw", 82, src, dst); + DO_imm_mandr_r("pblendw", 83, src, dst); + DO_imm_mandr_r("pblendw", 84, src, dst); + DO_imm_mandr_r("pblendw", 85, src, dst); + DO_imm_mandr_r("pblendw", 86, src, dst); + DO_imm_mandr_r("pblendw", 87, src, dst); + DO_imm_mandr_r("pblendw", 88, src, dst); + DO_imm_mandr_r("pblendw", 89, src, dst); + DO_imm_mandr_r("pblendw", 90, src, dst); + DO_imm_mandr_r("pblendw", 91, src, dst); + DO_imm_mandr_r("pblendw", 92, src, dst); + DO_imm_mandr_r("pblendw", 93, src, dst); + DO_imm_mandr_r("pblendw", 94, src, dst); + DO_imm_mandr_r("pblendw", 95, src, dst); + DO_imm_mandr_r("pblendw", 96, src, dst); + DO_imm_mandr_r("pblendw", 97, src, dst); + DO_imm_mandr_r("pblendw", 98, src, dst); + DO_imm_mandr_r("pblendw", 99, src, dst); + DO_imm_mandr_r("pblendw", 100, src, dst); + DO_imm_mandr_r("pblendw", 101, src, dst); + DO_imm_mandr_r("pblendw", 102, src, dst); + DO_imm_mandr_r("pblendw", 103, src, dst); + DO_imm_mandr_r("pblendw", 104, src, dst); + DO_imm_mandr_r("pblendw", 105, src, dst); + DO_imm_mandr_r("pblendw", 106, src, dst); + DO_imm_mandr_r("pblendw", 107, src, dst); + DO_imm_mandr_r("pblendw", 108, src, dst); + DO_imm_mandr_r("pblendw", 109, src, dst); + DO_imm_mandr_r("pblendw", 110, src, dst); + DO_imm_mandr_r("pblendw", 111, src, dst); + DO_imm_mandr_r("pblendw", 112, src, dst); + DO_imm_mandr_r("pblendw", 113, src, dst); + DO_imm_mandr_r("pblendw", 114, src, dst); + DO_imm_mandr_r("pblendw", 115, src, dst); + DO_imm_mandr_r("pblendw", 116, src, dst); + DO_imm_mandr_r("pblendw", 117, src, dst); + DO_imm_mandr_r("pblendw", 118, src, dst); + DO_imm_mandr_r("pblendw", 119, src, dst); + DO_imm_mandr_r("pblendw", 120, src, dst); + DO_imm_mandr_r("pblendw", 121, src, dst); + DO_imm_mandr_r("pblendw", 122, src, dst); + DO_imm_mandr_r("pblendw", 123, src, dst); + DO_imm_mandr_r("pblendw", 124, src, dst); + DO_imm_mandr_r("pblendw", 125, src, dst); + DO_imm_mandr_r("pblendw", 126, src, dst); + DO_imm_mandr_r("pblendw", 127, src, dst); + DO_imm_mandr_r("pblendw", 128, src, dst); + DO_imm_mandr_r("pblendw", 129, src, dst); + DO_imm_mandr_r("pblendw", 130, src, dst); + DO_imm_mandr_r("pblendw", 131, src, dst); + DO_imm_mandr_r("pblendw", 132, src, dst); + DO_imm_mandr_r("pblendw", 133, src, dst); + DO_imm_mandr_r("pblendw", 134, src, dst); + DO_imm_mandr_r("pblendw", 135, src, dst); + DO_imm_mandr_r("pblendw", 136, src, dst); + DO_imm_mandr_r("pblendw", 137, src, dst); + DO_imm_mandr_r("pblendw", 138, src, dst); + DO_imm_mandr_r("pblendw", 139, src, dst); + DO_imm_mandr_r("pblendw", 140, src, dst); + DO_imm_mandr_r("pblendw", 141, src, dst); + DO_imm_mandr_r("pblendw", 142, src, dst); + DO_imm_mandr_r("pblendw", 143, src, dst); + DO_imm_mandr_r("pblendw", 144, src, dst); + DO_imm_mandr_r("pblendw", 145, src, dst); + DO_imm_mandr_r("pblendw", 146, src, dst); + DO_imm_mandr_r("pblendw", 147, src, dst); + DO_imm_mandr_r("pblendw", 148, src, dst); + DO_imm_mandr_r("pblendw", 149, src, dst); + DO_imm_mandr_r("pblendw", 150, src, dst); + DO_imm_mandr_r("pblendw", 151, src, dst); + DO_imm_mandr_r("pblendw", 152, src, dst); + DO_imm_mandr_r("pblendw", 153, src, dst); + DO_imm_mandr_r("pblendw", 154, src, dst); + DO_imm_mandr_r("pblendw", 155, src, dst); + DO_imm_mandr_r("pblendw", 156, src, dst); + DO_imm_mandr_r("pblendw", 157, src, dst); + DO_imm_mandr_r("pblendw", 158, src, dst); + DO_imm_mandr_r("pblendw", 159, src, dst); + DO_imm_mandr_r("pblendw", 160, src, dst); + DO_imm_mandr_r("pblendw", 161, src, dst); + DO_imm_mandr_r("pblendw", 162, src, dst); + DO_imm_mandr_r("pblendw", 163, src, dst); + DO_imm_mandr_r("pblendw", 164, src, dst); + DO_imm_mandr_r("pblendw", 165, src, dst); + DO_imm_mandr_r("pblendw", 166, src, dst); + DO_imm_mandr_r("pblendw", 167, src, dst); + DO_imm_mandr_r("pblendw", 168, src, dst); + DO_imm_mandr_r("pblendw", 169, src, dst); + DO_imm_mandr_r("pblendw", 170, src, dst); + DO_imm_mandr_r("pblendw", 171, src, dst); + DO_imm_mandr_r("pblendw", 172, src, dst); + DO_imm_mandr_r("pblendw", 173, src, dst); + DO_imm_mandr_r("pblendw", 174, src, dst); + DO_imm_mandr_r("pblendw", 175, src, dst); + DO_imm_mandr_r("pblendw", 176, src, dst); + DO_imm_mandr_r("pblendw", 177, src, dst); + DO_imm_mandr_r("pblendw", 178, src, dst); + DO_imm_mandr_r("pblendw", 179, src, dst); + DO_imm_mandr_r("pblendw", 180, src, dst); + DO_imm_mandr_r("pblendw", 181, src, dst); + DO_imm_mandr_r("pblendw", 182, src, dst); + DO_imm_mandr_r("pblendw", 183, src, dst); + DO_imm_mandr_r("pblendw", 184, src, dst); + DO_imm_mandr_r("pblendw", 185, src, dst); + DO_imm_mandr_r("pblendw", 186, src, dst); + DO_imm_mandr_r("pblendw", 187, src, dst); + DO_imm_mandr_r("pblendw", 188, src, dst); + DO_imm_mandr_r("pblendw", 189, src, dst); + DO_imm_mandr_r("pblendw", 190, src, dst); + DO_imm_mandr_r("pblendw", 191, src, dst); + DO_imm_mandr_r("pblendw", 192, src, dst); + DO_imm_mandr_r("pblendw", 193, src, dst); + DO_imm_mandr_r("pblendw", 194, src, dst); + DO_imm_mandr_r("pblendw", 195, src, dst); + DO_imm_mandr_r("pblendw", 196, src, dst); + DO_imm_mandr_r("pblendw", 197, src, dst); + DO_imm_mandr_r("pblendw", 198, src, dst); + DO_imm_mandr_r("pblendw", 199, src, dst); + DO_imm_mandr_r("pblendw", 200, src, dst); + DO_imm_mandr_r("pblendw", 201, src, dst); + DO_imm_mandr_r("pblendw", 202, src, dst); + DO_imm_mandr_r("pblendw", 203, src, dst); + DO_imm_mandr_r("pblendw", 204, src, dst); + DO_imm_mandr_r("pblendw", 205, src, dst); + DO_imm_mandr_r("pblendw", 206, src, dst); + DO_imm_mandr_r("pblendw", 207, src, dst); + DO_imm_mandr_r("pblendw", 208, src, dst); + DO_imm_mandr_r("pblendw", 209, src, dst); + DO_imm_mandr_r("pblendw", 210, src, dst); + DO_imm_mandr_r("pblendw", 211, src, dst); + DO_imm_mandr_r("pblendw", 212, src, dst); + DO_imm_mandr_r("pblendw", 213, src, dst); + DO_imm_mandr_r("pblendw", 214, src, dst); + DO_imm_mandr_r("pblendw", 215, src, dst); + DO_imm_mandr_r("pblendw", 216, src, dst); + DO_imm_mandr_r("pblendw", 217, src, dst); + DO_imm_mandr_r("pblendw", 218, src, dst); + DO_imm_mandr_r("pblendw", 219, src, dst); + DO_imm_mandr_r("pblendw", 220, src, dst); + DO_imm_mandr_r("pblendw", 221, src, dst); + DO_imm_mandr_r("pblendw", 222, src, dst); + DO_imm_mandr_r("pblendw", 223, src, dst); + DO_imm_mandr_r("pblendw", 224, src, dst); + DO_imm_mandr_r("pblendw", 225, src, dst); + DO_imm_mandr_r("pblendw", 226, src, dst); + DO_imm_mandr_r("pblendw", 227, src, dst); + DO_imm_mandr_r("pblendw", 228, src, dst); + DO_imm_mandr_r("pblendw", 229, src, dst); + DO_imm_mandr_r("pblendw", 230, src, dst); + DO_imm_mandr_r("pblendw", 231, src, dst); + DO_imm_mandr_r("pblendw", 232, src, dst); + DO_imm_mandr_r("pblendw", 233, src, dst); + DO_imm_mandr_r("pblendw", 234, src, dst); + DO_imm_mandr_r("pblendw", 235, src, dst); + DO_imm_mandr_r("pblendw", 236, src, dst); + DO_imm_mandr_r("pblendw", 237, src, dst); + DO_imm_mandr_r("pblendw", 238, src, dst); + DO_imm_mandr_r("pblendw", 239, src, dst); + DO_imm_mandr_r("pblendw", 240, src, dst); + DO_imm_mandr_r("pblendw", 241, src, dst); + DO_imm_mandr_r("pblendw", 242, src, dst); + DO_imm_mandr_r("pblendw", 243, src, dst); + DO_imm_mandr_r("pblendw", 244, src, dst); + DO_imm_mandr_r("pblendw", 245, src, dst); + DO_imm_mandr_r("pblendw", 246, src, dst); + DO_imm_mandr_r("pblendw", 247, src, dst); + DO_imm_mandr_r("pblendw", 248, src, dst); + DO_imm_mandr_r("pblendw", 249, src, dst); + DO_imm_mandr_r("pblendw", 250, src, dst); + DO_imm_mandr_r("pblendw", 251, src, dst); + DO_imm_mandr_r("pblendw", 252, src, dst); + DO_imm_mandr_r("pblendw", 253, src, dst); + DO_imm_mandr_r("pblendw", 254, src, dst); + DO_imm_mandr_r("pblendw", 255, src, dst); + } +} + + +void test_PCMPEQQ ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + switch (i - 6) { + case 0: memset(&src[0], 0x55, 8); + memset(&dst[0], 0x55, 8); break; + case 1: memset(&src[8], 0x55, 8); + memset(&dst[8], 0x55, 8); break; + default: + break; + } + DO_mandr_r("pcmpeqq", src, dst); + } +} + + +void test_PEXTRB ( void ) +{ + V128 src; + randV128(&src); + DO_imm_r_to_mandrscalar("pextrb", 0, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 1, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 2, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 3, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 4, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 5, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 6, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 7, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 8, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 9, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 10, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 11, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 12, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 13, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 14, src, "d"); + DO_imm_r_to_mandrscalar("pextrb", 15, src, "d"); +} + +void test_PINSRB ( void ) +{ + ULong src; + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 0, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 1, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 2, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 3, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 4, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 5, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 6, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 7, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 8, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 9, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 10, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 11, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 12, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 13, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 14, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrb", 15, src, "d"); +} + + +void test_PEXTRW ( void ) +{ + V128 src; + randV128(&src); + DO_imm_r_to_mandrscalar("pextrw", 0, src, "d"); + DO_imm_r_to_mandrscalar("pextrw", 1, src, "d"); + DO_imm_r_to_mandrscalar("pextrw", 2, src, "d"); + DO_imm_r_to_mandrscalar("pextrw", 3, src, "d"); + DO_imm_r_to_mandrscalar("pextrw", 4, src, "d"); + DO_imm_r_to_mandrscalar("pextrw", 5, src, "d"); + DO_imm_r_to_mandrscalar("pextrw", 6, src, "d"); + DO_imm_r_to_mandrscalar("pextrw", 7, src, "d"); +} + +void test_PINSRW ( void ) +{ + ULong src; + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrw", 0, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrw", 1, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrw", 2, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrw", 3, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrw", 4, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrw", 5, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrw", 6, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrw", 7, src, "d"); +} + + +void test_PEXTRD ( void ) +{ + V128 src; + randV128(&src); + DO_imm_r_to_mandrscalar("pextrd", 0, src, "d"); + DO_imm_r_to_mandrscalar("pextrd", 1, src, "d"); + DO_imm_r_to_mandrscalar("pextrd", 2, src, "d"); + DO_imm_r_to_mandrscalar("pextrd", 3, src, "d"); +} + +void test_PINSRD ( void ) +{ + ULong src; + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrd", 0, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrd", 1, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrd", 2, src, "d"); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrd", 3, src, "d"); +} + + +void test_PEXTRQ ( void ) +{ + V128 src; + randV128(&src); + DO_imm_r_to_mandrscalar("pextrq", 0, src, ""); + DO_imm_r_to_mandrscalar("pextrq", 1, src, ""); +} + +void test_PINSRQ ( void ) +{ + ULong src; + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrq", 0, src, ""); + src = randULong(); + DO_imm_mandrscalar_to_r("pinsrq", 1, src, ""); +} + + +void test_PHMINPOSUW ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("phminposuw", src, dst); + } +} + +void test_PMAXSB ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmaxsb", src, dst); + } +} + +void test_PMAXSD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmaxsd", src, dst); + } +} + +void test_PMAXUD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmaxud", src, dst); + } +} + +void test_PMAXUW ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmaxuw", src, dst); + } +} + +void test_PMINSB ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pminsb", src, dst); + } +} + +void test_PMINSD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pminsd", src, dst); + } +} + +void test_PMINUD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pminud", src, dst); + } +} + +void test_PMINUW ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pminuw", src, dst); + } +} + +void test_PMOVSXBW ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovsxbw", src, dst); + } +} + +void test_PMOVSXBD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovsxbd", src, dst); + } +} + +void test_PMOVSXBQ ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovsxbq", src, dst); + } +} + +void test_PMOVSXWD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovsxwd", src, dst); + } +} + +void test_PMOVSXWQ ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovsxwq", src, dst); + } +} + +void test_PMOVSXDQ ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovsxdq", src, dst); + } +} + +void test_PMOVZXBW ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovzxbw", src, dst); + } +} + +void test_PMOVZXBD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovzxbd", src, dst); + } +} + +void test_PMOVZXBQ ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovzxbq", src, dst); + } +} + +void test_PMOVZXWD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovzxwd", src, dst); + } +} + +void test_PMOVZXWQ ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovzxwq", src, dst); + } +} + +void test_PMOVZXDQ ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmovzxdq", src, dst); + } +} + +void test_PMULDQ ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmuldq", src, dst); + } +} + + +void test_PMULLD ( void ) +{ + V128 src, dst; + Int i; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pmulld", src, dst); + } +} + + +void test_POPCNTQ ( void ) +{ + ULong block[4]; + Int i; + ULong oszacp_mask = 0x8D5; + for (i = 0; i < 10; i++) { + block[0] = i == 0 ? 0 : randULong(); + block[1] = randULong(); + block[2] = randULong(); + block[3] = randULong(); + __asm__ __volatile__( + "movq %0, %%rax" "\n\t" + "movq 0(%%rax), %%rdi" "\n\t" + "movq 8(%%rax), %%r11" "\n\t" + "popcntq %%rdi, %%r11" "\n\t" + "movq %%r11, 16(%%rax)" "\n\t" + "pushfq" "\n\t" + "popq %%r12" "\n\t" + "movq %%r12, 24(%%rax)" "\n" + : /*out*/ + : /*in*/"r"(&block[0]) + : /*trash*/ "cc", "memory", "rdi", "r11", "r12" + ); + printf("r popcntq %016llx %016llx %016llx %016llx\n", + block[0], block[1], block[2], block[3] & oszacp_mask); + + block[0] = i == 0 ? 0 : randULong(); + block[1] = randULong(); + block[2] = randULong(); + block[3] = randULong(); + __asm__ __volatile__( + "movq %0, %%rax" "\n\t" + "movq 8(%%rax), %%r11" "\n\t" + "popcntq 0(%%rax), %%r11" "\n\t" + "movq %%r11, 16(%%rax)" "\n\t" + "pushfq" "\n\t" + "popq %%r12" "\n\t" + "movq %%r12, 24(%%rax)" "\n" + : /*out*/ + : /*in*/"r"(&block[0]) + : /*trash*/ "cc", "memory", "r11", "r12" + ); + printf("m popcntq %016llx %016llx %016llx %016llx\n", + block[0], block[1], block[2], block[3] & oszacp_mask); + } +} + + +void test_POPCNTL ( void ) +{ + ULong block[4]; + Int i; + ULong oszacp_mask = 0x8D5; + for (i = 0; i < 10; i++) { + block[0] = i == 0 ? 0 : randULong(); + block[1] = randULong(); + block[2] = randULong(); + block[3] = randULong(); + __asm__ __volatile__( + "movq %0, %%rax" "\n\t" + "movq 0(%%rax), %%rdi" "\n\t" + "movq 8(%%rax), %%r11" "\n\t" + "popcntl %%edi, %%r11d" "\n\t" + "movq %%r11, 16(%%rax)" "\n\t" + "pushfq" "\n\t" + "popq %%r12" "\n\t" + "movq %%r12, 24(%%rax)" "\n" + : /*out*/ + : /*in*/"r"(&block[0]) + : /*trash*/ "cc", "memory", "rdi", "r11", "r12" + ); + printf("r popcntl %016llx %016llx %016llx %016llx\n", + block[0], block[1], block[2], block[3] & oszacp_mask); + + block[0] = i == 0 ? 0 : randULong(); + block[1] = randULong(); + block[2] = randULong(); + block[3] = randULong(); + __asm__ __volatile__( + "movq %0, %%rax" "\n\t" + "movq 8(%%rax), %%r11" "\n\t" + "popcntl 0(%%rax), %%r11d" "\n\t" + "movq %%r11, 16(%%rax)" "\n\t" + "pushfq" "\n\t" + "popq %%r12" "\n\t" + "movq %%r12, 24(%%rax)" "\n" + : /*out*/ + : /*in*/"r"(&block[0]) + : /*trash*/ "cc", "memory", "r11", "r12" + ); + printf("m popcntl %016llx %016llx %016llx %016llx\n", + block[0], block[1], block[2], block[3] & oszacp_mask); + } +} + + +void test_POPCNTW ( void ) +{ + ULong block[4]; + Int i; + ULong oszacp_mask = 0x8D5; + for (i = 0; i < 10; i++) { + block[0] = i == 0 ? 0 : randULong(); + block[1] = randULong(); + block[2] = randULong(); + block[3] = randULong(); + __asm__ __volatile__( + "movq %0, %%rax" "\n\t" + "movq 0(%%rax), %%rdi" "\n\t" + "movq 8(%%rax), %%r11" "\n\t" + "popcntw %%di, %%r11w" "\n\t" + "movq %%r11, 16(%%rax)" "\n\t" + "pushfq" "\n\t" + "popq %%r12" "\n\t" + "movq %%r12, 24(%%rax)" "\n" + : /*out*/ + : /*in*/"r"(&block[0]) + : /*trash*/ "cc", "memory", "rdi", "r11", "r12" + ); + printf("r popcntw %016llx %016llx %016llx %016llx\n", + block[0], block[1], block[2], block[3] & oszacp_mask); + + block[0] = i == 0 ? 0 : randULong(); + block[1] = randULong(); + block[2] = randULong(); + block[3] = randULong(); + __asm__ __volatile__( + "movq %0, %%rax" "\n\t" + "movq 8(%%rax), %%r11" "\n\t" + "popcntw 0(%%rax), %%r11w" "\n\t" + "movq %%r11, 16(%%rax)" "\n\t" + "pushfq" "\n\t" + "popq %%r12" "\n\t" + "movq %%r12, 24(%%rax)" "\n" + : /*out*/ + : /*in*/"r"(&block[0]) + : /*trash*/ "cc", "memory", "r11", "r12" + ); + printf("m popcntw %016llx %016llx %016llx %016llx\n", + block[0], block[1], block[2], block[3] & oszacp_mask); + } +} + + +void test_PCMPGTQ ( void ) +{ + V128 spec[7]; + do64HLtoV128( &spec[0], 0x0000000000000000ULL, 0xffffffffffffffffULL ); + do64HLtoV128( &spec[1], 0x0000000000000001ULL, 0xfffffffffffffffeULL ); + do64HLtoV128( &spec[2], 0x7fffffffffffffffULL, 0x8000000000000001ULL ); + do64HLtoV128( &spec[3], 0x8000000000000000ULL, 0x8000000000000000ULL ); + do64HLtoV128( &spec[4], 0x8000000000000001ULL, 0x7fffffffffffffffULL ); + do64HLtoV128( &spec[5], 0xfffffffffffffffeULL, 0x0000000000000001ULL ); + do64HLtoV128( &spec[6], 0xffffffffffffffffULL, 0x0000000000000000ULL ); + + V128 src, dst; + Int i, j; + for (i = 0; i < 10; i++) { + randV128(&src); + randV128(&dst); + DO_mandr_r("pcmpgtq", src, dst); + } + for (i = 0; i < 7; i++) { + for (j = 0; j < 7; j++) { + memcpy(&src, &spec[i], 16); + memcpy(&dst, &spec[j], 16); + DO_mandr_r("pcmpgtq", src, dst); + } + } +} + +/* ------------ ROUNDSD ------------ */ + +void do_ROUNDSD_000 ( Bool mem, V128* src, /*OUT*/V128* dst ) +{ + if (mem) { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "roundsd $0, (%0), %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11" + ); + } else { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "movupd (%0), %%xmm2" "\n\t" + "roundsd $0, %%xmm2, %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11","xmm2" + ); + } +} + +void do_ROUNDSD_001 ( Bool mem, V128* src, /*OUT*/V128* dst ) +{ + if (mem) { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "roundsd $1, (%0), %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11" + ); + } else { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "movupd (%0), %%xmm2" "\n\t" + "roundsd $1, %%xmm2, %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11","xmm2" + ); + } +} + +void do_ROUNDSD_010 ( Bool mem, V128* src, /*OUT*/V128* dst ) +{ + if (mem) { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "roundsd $2, (%0), %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11" + ); + } else { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "movupd (%0), %%xmm2" "\n\t" + "roundsd $2, %%xmm2, %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11","xmm2" + ); + } +} + +void do_ROUNDSD_011 ( Bool mem, V128* src, /*OUT*/V128* dst ) +{ + if (mem) { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "roundsd $3, (%0), %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11" + ); + } else { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "movupd (%0), %%xmm2" "\n\t" + "roundsd $3, %%xmm2, %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11","xmm2" + ); + } +} + + +void test_ROUNDSD_w_immediate_rounding ( void ) +{ + double vals[22]; + Int i = 0; + vals[i++] = 0.0; + vals[i++] = -0.0; + vals[i++] = mkPosInf(); + vals[i++] = mkNegInf(); + vals[i++] = mkPosNan(); + vals[i++] = mkNegNan(); + vals[i++] = -1.3; + vals[i++] = -1.1; + vals[i++] = -0.9; + vals[i++] = -0.7; + vals[i++] = -0.50001; + vals[i++] = -0.49999; + vals[i++] = -0.3; + vals[i++] = -0.1; + vals[i++] = 0.1; + vals[i++] = 0.3; + vals[i++] = 0.49999; + vals[i++] = 0.50001; + vals[i++] = 0.7; + vals[i++] = 0.9; + vals[i++] = 1.1; + vals[i++] = 1.3; + assert(i == 22); + + for (i = 0; i < sizeof(vals)/sizeof(vals[0]); i++) { + V128 src, dst; + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 8); + do_ROUNDSD_000(False/*reg*/, &src, &dst); + printf("r roundsd_000 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", vals[i], *(double*)(&dst[0])); + printf("\n"); + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 8); + do_ROUNDSD_000(True/*mem*/, &src, &dst); + printf("m roundsd_000 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", vals[i], *(double*)(&dst[0])); + printf("\n"); + + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 8); + do_ROUNDSD_001(False/*reg*/, &src, &dst); + printf("r roundsd_001 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", vals[i], *(double*)(&dst[0])); + printf("\n"); + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 8); + do_ROUNDSD_001(True/*mem*/, &src, &dst); + printf("m roundsd_001 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", vals[i], *(double*)(&dst[0])); + printf("\n"); + + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 8); + do_ROUNDSD_010(False/*reg*/, &src, &dst); + printf("r roundsd_010 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", vals[i], *(double*)(&dst[0])); + printf("\n"); + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 8); + do_ROUNDSD_010(True/*mem*/, &src, &dst); + printf("m roundsd_010 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", vals[i], *(double*)(&dst[0])); + printf("\n"); + + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 8); + do_ROUNDSD_011(False/*reg*/, &src, &dst); + printf("r roundsd_011 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", vals[i], *(double*)(&dst[0])); + printf("\n"); + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 8); + do_ROUNDSD_011(True/*mem*/, &src, &dst); + printf("m roundsd_011 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", vals[i], *(double*)(&dst[0])); + printf("\n"); + } +} + +/* ------------ ROUNDSS ------------ */ + +void do_ROUNDSS_000 ( Bool mem, V128* src, /*OUT*/V128* dst ) +{ + if (mem) { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "roundss $0, (%0), %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11" + ); + } else { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "movupd (%0), %%xmm2" "\n\t" + "roundss $0, %%xmm2, %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11","xmm2" + ); + } +} + +void do_ROUNDSS_001 ( Bool mem, V128* src, /*OUT*/V128* dst ) +{ + if (mem) { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "roundss $1, (%0), %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11" + ); + } else { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "movupd (%0), %%xmm2" "\n\t" + "roundss $1, %%xmm2, %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11","xmm2" + ); + } +} + +void do_ROUNDSS_010 ( Bool mem, V128* src, /*OUT*/V128* dst ) +{ + if (mem) { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "roundss $2, (%0), %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11" + ); + } else { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "movupd (%0), %%xmm2" "\n\t" + "roundss $2, %%xmm2, %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11","xmm2" + ); + } +} + +void do_ROUNDSS_011 ( Bool mem, V128* src, /*OUT*/V128* dst ) +{ + if (mem) { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "roundss $3, (%0), %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11" + ); + } else { + __asm__ __volatile__( + "movupd (%1), %%xmm11" "\n\t" + "movupd (%0), %%xmm2" "\n\t" + "roundss $3, %%xmm2, %%xmm11" "\n\t" + "movupd %%xmm11, (%1)" "\n" + : /*OUT*/ + : /*IN*/ "r"(src), "r"(dst) + : /*TRASH*/ "xmm11","xmm2" + ); + } +} + + +void test_ROUNDSS_w_immediate_rounding ( void ) +{ + float vals[22]; + Int i = 0; + vals[i++] = 0.0; + vals[i++] = -0.0; + vals[i++] = mkPosInf(); + vals[i++] = mkNegInf(); + vals[i++] = mkPosNan(); + vals[i++] = mkNegNan(); + vals[i++] = -1.3; + vals[i++] = -1.1; + vals[i++] = -0.9; + vals[i++] = -0.7; + vals[i++] = -0.50001; + vals[i++] = -0.49999; + vals[i++] = -0.3; + vals[i++] = -0.1; + vals[i++] = 0.1; + vals[i++] = 0.3; + vals[i++] = 0.49999; + vals[i++] = 0.50001; + vals[i++] = 0.7; + vals[i++] = 0.9; + vals[i++] = 1.1; + vals[i++] = 1.3; + assert(i == 22); + + for (i = 0; i < sizeof(vals)/sizeof(vals[0]); i++) { + V128 src, dst; + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 4); + do_ROUNDSS_000(False/*reg*/, &src, &dst); + printf("r roundss_000 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", (double)vals[i], (double)*(float*)(&dst[0])); + printf("\n"); + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 4); + do_ROUNDSS_000(True/*mem*/, &src, &dst); + printf("m roundss_000 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", (double)vals[i], (double)*(float*)(&dst[0])); + printf("\n"); + + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 4); + do_ROUNDSS_001(False/*reg*/, &src, &dst); + printf("r roundss_001 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", (double)vals[i], (double)*(float*)(&dst[0])); + printf("\n"); + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 4); + do_ROUNDSS_001(True/*mem*/, &src, &dst); + printf("m roundss_001 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", (double)vals[i], (double)*(float*)(&dst[0])); + printf("\n"); + + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 4); + do_ROUNDSS_010(False/*reg*/, &src, &dst); + printf("r roundss_010 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", (double)vals[i], (double)*(float*)(&dst[0])); + printf("\n"); + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 4); + do_ROUNDSS_010(True/*mem*/, &src, &dst); + printf("m roundss_010 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", (double)vals[i], (double)*(float*)(&dst[0])); + printf("\n"); + + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 4); + do_ROUNDSS_011(False/*reg*/, &src, &dst); + printf("r roundss_011 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", (double)vals[i], (double)*(float*)(&dst[0])); + printf("\n"); + + randV128(&src); + randV128(&dst); + memcpy(&src[0], &vals[i], 4); + do_ROUNDSS_011(True/*mem*/, &src, &dst); + printf("m roundss_011 "); + showV128(&src); + printf(" "); + showV128(&dst); + printf(" %10f %10f", (double)vals[i], (double)*(float*)(&dst[0])); + printf("\n"); + } +} + +void test_PTEST ( void ) +{ + const Int ntests = 8; + V128 spec[ntests]; + do64HLtoV128( &spec[0], 0x0000000000000000ULL, 0x0000000000000000ULL ); + do64HLtoV128( &spec[1], 0x0000000000000000ULL, 0x0000000000000001ULL ); + do64HLtoV128( &spec[2], 0x0000000000000001ULL, 0x0000000000000000ULL ); + do64HLtoV128( &spec[3], 0x0000000000000001ULL, 0x0000000000000001ULL ); + do64HLtoV128( &spec[4], 0xffffffffffffffffULL, 0xffffffffffffffffULL ); + do64HLtoV128( &spec[5], 0xffffffffffffffffULL, 0xfffffffffffffffeULL ); + do64HLtoV128( &spec[6], 0xfffffffffffffffeULL, 0xffffffffffffffffULL ); + do64HLtoV128( &spec[7], 0xfffffffffffffffeULL, 0xfffffffffffffffeULL ); + V128 block[2]; + Int i, j; + ULong flags; + for (i = 0; i < ntests; i++) { + for (j = 0; j < ntests; j++) { + memcpy(&block[0], &spec[i], 16); + memcpy(&block[1], &spec[j], 16); + __asm__ __volatile__( + "subq $256, %%rsp" "\n\t" + "movupd 0(%1), %%xmm2" "\n\t" + "ptest 16(%1), %%xmm2" "\n\t" + "pushfq" "\n\t" + "popq %0" "\n\t" + "addq $256, %%rsp" "\n\t" + : /*out*/"=r"(flags) : /*in*/ "r"(&block[0]) : + "xmm2", "memory", "cc" + ); + printf("r ptest "); + showV128(&block[0]); + printf(" "); + showV128(&block[1]); + printf(" -> eflags %04x\n", (UInt)flags & 0x8D5); + } + } +} + +int main ( int argc, char** argv ) +{ +#if 1 + // ------ SSE 4.1 ------ + test_BLENDPD(); // done Apr.01.2010 + test_BLENDPS(); // done Apr.02.2010 + //test_PBLENDW(); + // BLENDVPD + // BLENDVPS + test_DPPD(); // done Apr.08.2010 + test_DPPS(); // done Apr.09.2010 + // EXTRACTPS + test_INSERTPS(); // done Apr.01.2010 + // MOVNTDQA + //test_MPSADBW(); + //test_PACKUSDW(); + // PBLENDVB + //test_PCMPEQQ(); + test_PEXTRB(); // done Apr.15.2010 + test_PEXTRD(); // done Apr.14.2010 + test_PEXTRQ(); // done Apr.14.2010 + test_PEXTRW(); // done Apr.14.2010 + test_PINSRQ(); // done Apr.16.2010 + test_PINSRD(); // todo + //test_PINSRW(); // todo + test_PINSRB(); // todo + //test_PHMINPOSUW(); + test_PMAXSB(); + test_PMAXSD(); // done Apr.09.2010 + test_PMAXUD(); // done Apr.16.2010 + test_PMAXUW(); + test_PMINSB(); + test_PMINSD(); // done Apr.09.2010 + test_PMINUD(); + test_PMINUW(); + test_PMOVSXBW(); // done Apr.02.2010 + test_PMOVSXBD(); // done Mar.30.2010 + test_PMOVSXBQ(); // done Mar.30.2010 + test_PMOVSXWD(); // done Mar.31.2010 + test_PMOVSXWQ(); // done Mar.31.2010 + test_PMOVSXDQ(); // done Mar.31.2010 + test_PMOVZXBW(); // done Mar.28.2010 + test_PMOVZXBD(); // done Mar.29.2010 + test_PMOVZXBQ(); // done Mar.29.2010 + test_PMOVZXWD(); // done Mar.28.2010 + test_PMOVZXWQ(); // done Mar.29.2010 + test_PMOVZXDQ(); // done Mar.29.2010 + test_POPCNTW(); + test_POPCNTL(); + test_POPCNTQ(); + //test_PMULDQ(); + test_PMULLD(); + test_PTEST(); + // ROUNDPD + // ROUNDPS + // ROUNDSD + // ROUNDSS + test_ROUNDSD_w_immediate_rounding(); + test_ROUNDSS_w_immediate_rounding(); + // ------ SSE 4.2 ------ + test_PCMPGTQ(); +#else + test_PTEST(); +#endif + + return 0; + + ////////////////// + + Int sse1 = 0, sse2 = 0; + + if (argc == 2 && 0==strcmp(argv[1], "sse1")) { + sse1 = 1; + } + else + if (argc == 2 && 0==strcmp(argv[1], "sse2")) { + sse2 = 1; + } + else + if (argc == 2 && 0==strcmp(argv[1], "all")) { + sse1 = sse2 = 1; + } + else { + fprintf(stderr, "usage: sse_memory [sse1|sse2|all]\n"); + return 0; + } + + return 0; +} + diff --git a/none/tests/amd64/xadd.c b/none/tests/amd64/xadd.c new file mode 100644 index 0000000..38d4f20 --- /dev/null +++ b/none/tests/amd64/xadd.c @@ -0,0 +1,51 @@ + +#include "config.h" +#include +#include + +/* Simple test program, no race. + Tests the 'xadd' exchange-and-add instruction with {r,r} operands, which is rarely generated by compilers. */ + +#undef PLAT_x86_linux +#undef PLAT_amd64_linux +#undef PLAT_ppc32_linux +#undef PLAT_ppc64_linux +#undef PLAT_ppc32_aix5 +#undef PLAT_ppc64_aix5 + +#if !defined(_AIX) && defined(__i386__) +# define PLAT_x86_linux 1 +#elif !defined(_AIX) && defined(__x86_64__) +# define PLAT_amd64_linux 1 +#endif + + +#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) +# define XADD_R_R(_addr,_lval) \ + __asm__ __volatile__( \ + "xadd %1, %0" \ + : /*out*/ "=r"(_lval),"=r"(_addr) \ + : /*in*/ "0"(_lval),"1"(_addr) \ + : "flags" \ + ) +#else +# error "Unsupported architecture" +#endif + +int main ( void ) +{ + long d = 20, s = 2; + long xadd_r_r_res; +#define XADD_R_R_RES 42 + + XADD_R_R(s, d); + xadd_r_r_res = s + d; + assert(xadd_r_r_res == XADD_R_R_RES); + + if (xadd_r_r_res == XADD_R_R_RES) + printf("success\n"); + else + printf("failure\n"); + + return xadd_r_r_res; +} diff --git a/none/tests/amd64/xadd.stderr.exp b/none/tests/amd64/xadd.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/amd64/xadd.stdout.exp b/none/tests/amd64/xadd.stdout.exp new file mode 100644 index 0000000..2e9ba47 --- /dev/null +++ b/none/tests/amd64/xadd.stdout.exp @@ -0,0 +1 @@ +success diff --git a/none/tests/amd64/xadd.vgtest b/none/tests/amd64/xadd.vgtest new file mode 100644 index 0000000..2cb1bee --- /dev/null +++ b/none/tests/amd64/xadd.vgtest @@ -0,0 +1,2 @@ +prog: xadd +vgopts: -q diff --git a/none/tests/arm/Makefile.am b/none/tests/arm/Makefile.am new file mode 100644 index 0000000..ffa52bd --- /dev/null +++ b/none/tests/arm/Makefile.am @@ -0,0 +1,49 @@ + +include $(top_srcdir)/Makefile.tool-tests.am + +dist_noinst_SCRIPTS = filter_stderr + +EXTRA_DIST = \ + neon128.stdout.exp neon128.stderr.exp neon128.vgtest \ + neon64.stdout.exp neon64.stderr.exp neon64.vgtest \ + v6intARM.stdout.exp v6intARM.stderr.exp v6intARM.vgtest \ + v6intThumb.stdout.exp v6intThumb.stderr.exp v6intThumb.vgtest \ + v6media.stdout.exp v6media.stderr.exp v6media.vgtest \ + vfp.stdout.exp vfp.stderr.exp vfp.vgtest + +check_PROGRAMS = \ + neon128 \ + neon64 \ + v6intARM \ + v6intThumb \ + v6media \ + vfp + +AM_CFLAGS += @FLAG_M32@ +AM_CXXFLAGS += @FLAG_M32@ +AM_CCASFLAGS += @FLAG_M32@ + +# These two are specific to their ARM/Thumb respectively and so we +# hardwire -marm/-mthumb. neon64 and neon128 are compilable on both, +# however, ask for them to be compiled on thumb, as that looks +# like that's going to be the more common use case. They also +# need special helping w.r.t -mfpu and -mfloat-abi, though. +# Also force -O0 since -O takes hundreds of MB of memory +# for v6intThumb.c. +v6intARM_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -marm +v6intThumb_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb + +v6media_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb + +vfp_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \ + -mfpu=neon -mfloat-abi=softfp \ + -mthumb + + +neon128_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \ + -mfpu=neon -mfloat-abi=softfp \ + -mthumb + +neon64_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \ + -mfpu=neon -mfloat-abi=softfp \ + -mthumb diff --git a/none/tests/arm/filter_stderr b/none/tests/arm/filter_stderr new file mode 100755 index 0000000..616ce05 --- /dev/null +++ b/none/tests/arm/filter_stderr @@ -0,0 +1,4 @@ +#! /bin/sh + +../filter_stderr + diff --git a/none/tests/arm/neon128.c b/none/tests/arm/neon128.c new file mode 100644 index 0000000..9ca94fb --- /dev/null +++ b/none/tests/arm/neon128.c @@ -0,0 +1,3223 @@ + +/* How to compile: + + gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \ + -marm -o neon128-a neon128.c + + or + + gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \ + -mthumb -o neon128-t neon128.c + +*/ + +#include +#include + +#ifndef __thumb__ +// ARM +#define MOVE_to_FPSCR_from_R4 \ + ".word 0xEEE14A10 @ vmsr FPSCR, r4\n\t" +#define MOVE_to_R4_from_FPSCR \ + ".word 0xEEF14A10 @ vmrs r4, FPSCR\n\t" +#endif + +#ifdef __thumb__ +// Thumb +#define MOVE_to_FPSCR_from_R4 \ + ".word 0x4A10EEE1 @ vmsr FPSCR, r4\n\t" +#define MOVE_to_R4_from_FPSCR \ + ".word 0x4A10EEF1 @ vmrs r4, FPSCR\n\t" +#endif + +static inline unsigned int f2u(float x) { + union { + float f; + unsigned int u; + } cvt; + cvt.f = x; + return cvt.u; +} + +/* test macros to generate and output the result of a single instruction */ + +const unsigned int mem[] = { + 0x121f1e1f, 0x131b1a1b, 0x141c1f1c, 0x151d191d, + 0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a, + 0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a, + 0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c +}; + +#define TESTINSN_imm(instruction, QD, imm) \ +{ \ + unsigned int out[4]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + instruction ", #" #imm "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out) \ + : #QD, "memory" \ + ); \ + printf("%s, #" #imm " :: Qd 0x%08x 0x%08x 0x%08x 0x%08x\n", \ + instruction, out[3], out[2], out[1], out[0]); \ +}\ +{ \ + unsigned int out[4]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %1, %2\n\t" \ + "vldmia %1!, {" #QD "}\n\t" \ + instruction ", #" #imm "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (addr), "r" (mem) \ + : #QD, "%2", "memory" \ + ); \ + printf("%s, #" #imm " :: Qd 0x%08x 0x%08x 0x%08x 0x%08x\n", \ + instruction, out[3], out[2], out[1], out[0]); \ +} + +#define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \ +{ \ + unsigned int out[4]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval); \ +} \ +{ \ + unsigned int out[4]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %2, %3\n\t" \ + "vldmia %2!, {" #QD "}\n\t" \ + "vldmia %2!, {" #QM "}\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (addr), "r" (mem) \ + : #QD, #QM, "%2", "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval); \ +} + + +#define TESTINSN_un_q(instruction, QD, QM, QMtype, QMval) \ +{ \ + unsigned int out[4]; \ + unsigned int fpscr; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + "vdup." #QMtype " " #QM ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + MOVE_to_R4_from_FPSCR \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory", "r4" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " fpscr: %08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval, fpscr); \ +} \ +{ \ + unsigned int out[4]; \ + unsigned int fpscr; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + "mov %3, %4\n\t" \ + "vldmia %3!, {" #QM "}\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + MOVE_to_R4_from_FPSCR \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (QMval), "r" (addr), "r" (mem) \ + : #QD, #QM, "memory", "r4" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " fpscr: %08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval, fpscr); \ +} + +#define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out[4]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + "vdup." #QNtype " " #QN ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QNval) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval, QNval); \ +} \ +/*{ \ + unsigned int out[4]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %0, %4\n\t" \ + "vldmia %0!, {" #QM "}\n\t" \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + : "+r" (addr) \ + : "r" (out), "r" (QMval), "r" (QNval), "r" (mem) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval, QNval); \ +} */ + +#define TESTINSN_bin_f(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out[4]; \ +\ + __asm__ volatile( \ + "vdup.i32 " #QD ", %3\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + "vdup." #QNtype " " #QN ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QNval), "r" (0x3f800000) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval, QNval); \ +} \ +{ \ + unsigned int out[4]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "vdup.i32 " #QD ", %3\n\t" \ + "mov %4, %5\n\t" \ + "vldmia %4!, {" #QM "}\n\t" \ + "vdup." #QNtype " " #QN ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QNval), "r"(0x3f800000), "r" (addr), "r" (mem) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval, QNval); \ +} + +#define TESTINSN_bin_q(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out[4]; \ + unsigned int fpscr; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + "vdup." #QMtype " " #QM ", %2\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + MOVE_to_R4_from_FPSCR \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (QMval), "r" (QNval) \ + : #QD, #QM, #QN, "memory", "r4" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x fpscr: %08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval, QNval, fpscr); \ +} \ +{ \ + unsigned int out[4]; \ + unsigned int fpscr; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + "mov %4, %5\n\t" \ + "vldmia %4!, {" #QM "}\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + MOVE_to_R4_from_FPSCR \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (QMval), "r" (QNval), "r" (addr), "r" (mem) \ + : #QD, #QM, #QN, "memory", "r4" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x fpscr: %08x\n", \ + instruction, out[1], out[0], QMval, QNval, fpscr); \ + printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x fpscr: %08x\n", \ + instruction, out[3], out[2], out[1], out[0], QMval, QNval, fpscr); \ +} + +#define TESTINSN_dual(instruction, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out1[4]; \ + unsigned int out2[4]; \ +\ + __asm__ volatile( \ + "vdup." #QMtype " " #QM ", %2\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QM "}\n\t" \ + "vstmia %1, {" #QN "}\n\t" \ + : \ + : "r" (out1), "r" (out2), "r" (QMval), "r" (QNval) \ + : #QM, #QN, "memory" \ + ); \ + printf("%s :: Qm 0x%08x 0x%08x 0x%08x 0x%08x Qn 0x%08x 0x%08x 0x%08x 0x%08x" \ + " Qm (" #QMtype ")0x%08x Qn (" #QNtype ")0x%08x\n", \ + instruction, out1[3], out1[2], out1[1], out1[0], \ + out2[3], out2[2], out2[1], out2[0], QMval, QNval); \ +} \ +{ \ + unsigned int out1[4]; \ + unsigned int out2[4]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %4, %5\n\t" \ + "vldmia %4!, {" #QM "}\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QM "}\n\t" \ + "vstmia %1, {" #QN "}\n\t" \ + : \ + : "r" (out1), "r" (out2), "r" (QMval), "r" (QNval), "r" (addr), "r" (mem) \ + : #QM, #QN, "%4", "memory" \ + ); \ + printf("%s :: Qm 0x%08x 0x%08x 0x%08x 0x%08x Qn 0x%08x 0x%08x 0x%08x 0x%08x\nQm (" \ +#QMtype ")0x%08x" " Qn (" #QNtype ")0x%08x\n", \ + instruction, out1[3], out1[2], out1[1], out1[0],\ + out2[3], out2[2], out2[1], out2[0], QMval, QNval); \ +} + +#if 0 +#define TESTINSN_2reg_shift(instruction, QD, QM, QMtype, QMval, imm) \ +{ \ + unsigned int out[4]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + instruction ", #" #imm "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory" \ + ); \ + printf("%s, #" #imm " :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x", \ + instruction, out[3], out[2], out[1], out[0], QMval); \ +} +#endif + +int main(int argc, char **argv) +{ + printf("----- VMOV (immediate) -----\n"); + TESTINSN_imm("vmov.i32 q0", q0, 0x7); + TESTINSN_imm("vmov.i16 q1", q1, 0x7); + TESTINSN_imm("vmov.i8 q2", q2, 0x7); + TESTINSN_imm("vmov.i32 q5", q5, 0x700); + TESTINSN_imm("vmov.i16 q7", q7, 0x700); + TESTINSN_imm("vmov.i32 q10", q10, 0x70000); + TESTINSN_imm("vmov.i32 q12", q12, 0x7000000); + TESTINSN_imm("vmov.i32 q13", q13, 0x7FF); + TESTINSN_imm("vmov.i32 q14", q14, 0x7FFFF); + TESTINSN_imm("vmov.i64 q15", q15, 0xFF0000FF00FFFF00); + + printf("----- VMVN (immediate) -----\n"); + TESTINSN_imm("vmvn.i32 q0", q0, 0x7); + TESTINSN_imm("vmvn.i16 q1", q1, 0x7); + TESTINSN_imm("vmvn.i8 q2", q2, 0x7); + TESTINSN_imm("vmvn.i32 q5", q5, 0x700); + TESTINSN_imm("vmvn.i16 q7", q7, 0x700); + TESTINSN_imm("vmvn.i32 q10", q10, 0x70000); + TESTINSN_imm("vmvn.i32 q13", q13, 0x7000000); + TESTINSN_imm("vmvn.i32 q11", q11, 0x7FF); + TESTINSN_imm("vmvn.i32 q14", q14, 0x7FFFF); + TESTINSN_imm("vmvn.i64 q15", q15, 0xFF0000FF00FFFF00); + + printf("----- VORR (immediate) -----\n"); + TESTINSN_imm("vorr.i32 q0", q0, 0x7); + TESTINSN_imm("vorr.i16 q2", q2, 0x7); + TESTINSN_imm("vorr.i32 q8", q8, 0x700); + TESTINSN_imm("vorr.i16 q6", q6, 0x700); + TESTINSN_imm("vorr.i32 q14", q14, 0x70000); + TESTINSN_imm("vorr.i32 q15", q15, 0x7000000); + + printf("----- VBIC (immediate) -----\n"); + TESTINSN_imm("vbic.i32 q0", q0, 0x7); + TESTINSN_imm("vbic.i16 q3", q3, 0x7); + TESTINSN_imm("vbic.i32 q5", q5, 0x700); + TESTINSN_imm("vbic.i16 q8", q8, 0x700); + TESTINSN_imm("vbic.i32 q10", q10, 0x70000); + TESTINSN_imm("vbic.i32 q15", q15, 0x7000000); + + printf("---- VMVN (register) ----\n"); + TESTINSN_un("vmvn q0, q1", q0, q1, i32, 24); + TESTINSN_un("vmvn q10, q15", q10, q15, i32, 24); + TESTINSN_un("vmvn q0, q14", q0, q14, i32, 24); + + printf("---- VMOV (register) ----\n"); + TESTINSN_un("vmov q0, q1", q0, q1, i32, 24); + TESTINSN_un("vmov q10, q15", q10, q15, i32, 24); + TESTINSN_un("vmov q0, q14", q0, q14, i32, 24); + + printf("---- VDUP (ARM core register) (tested indirectly) ----\n"); + TESTINSN_un("vmov q0, q1", q0, q1, i8, 7); + TESTINSN_un("vmov q10, q11", q10, q11, i16, 7); + TESTINSN_un("vmov q0, q15", q0, q15, i32, 7); + + printf("---- VADD ----\n"); + TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vadd.i64 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vadd.i16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vadd.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vadd.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vadd.i16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vadd.i64 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vadd.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vadd.i64 q13, q14, q15", q13, q14, i32, 140, q15, i32, 120); + + printf("---- VSUB ----\n"); + TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vsub.i64 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vsub.i16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vsub.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vsub.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vsub.i16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vsub.i64 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vsub.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vsub.i64 q13, q14, q15", q13, q14, i32, 140, q15, i32, 120); + + printf("---- VAND ----\n"); + TESTINSN_bin("vand q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77); + TESTINSN_bin("vand q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57); + TESTINSN_bin("vand q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed); + TESTINSN_bin("vand q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff); + + printf("---- VBIC ----\n"); + TESTINSN_bin("vbic q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77); + TESTINSN_bin("vbic q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57); + TESTINSN_bin("vbic q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed); + TESTINSN_bin("vbic q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff); + + printf("---- VORR ----\n"); + TESTINSN_bin("vorr q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73); + TESTINSN_bin("vorr q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff); + TESTINSN_bin("vorr q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff); + TESTINSN_bin("vorr q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f); + + printf("---- VORN ----\n"); + TESTINSN_bin("vorn q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73); + TESTINSN_bin("vorn q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff); + TESTINSN_bin("vorn q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff); + TESTINSN_bin("vorn q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f); + + printf("---- VEOR ----\n"); + TESTINSN_bin("veor q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77); + TESTINSN_bin("veor q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57); + TESTINSN_bin("veor q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed); + TESTINSN_bin("veor q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff); + TESTINSN_bin("veor q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73); + TESTINSN_bin("veor q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff); + TESTINSN_bin("veor q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff); + TESTINSN_bin("veor q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f); + + printf("---- VBSL ----\n"); + TESTINSN_bin("vbsl q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77); + TESTINSN_bin("vbsl q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57); + TESTINSN_bin("vbsl q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed); + TESTINSN_bin("vbsl q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff); + TESTINSN_bin("vbsl q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73); + TESTINSN_bin("vbsl q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff); + TESTINSN_bin("vbsl q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff); + TESTINSN_bin("vbsl q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f); + + printf("---- VBIT ----\n"); + TESTINSN_bin("vbit q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77); + TESTINSN_bin("vbit q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57); + TESTINSN_bin("vbit q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed); + TESTINSN_bin("vbit q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff); + TESTINSN_bin("vbit q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73); + TESTINSN_bin("vbit q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff); + TESTINSN_bin("vbit q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff); + TESTINSN_bin("vbit q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f); + + printf("---- VBIF ----\n"); + TESTINSN_bin("vbif q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77); + TESTINSN_bin("vbif q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57); + TESTINSN_bin("vbif q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed); + TESTINSN_bin("vbif q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff); + TESTINSN_bin("vbif q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73); + TESTINSN_bin("vbif q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff); + TESTINSN_bin("vbif q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff); + TESTINSN_bin("vbif q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f); + + printf("---- VEXT ----\n"); + TESTINSN_bin("vext.8 q0, q1, q2, #0", q0, q1, i8, 0x77, q2, i8, 0xff); + TESTINSN_bin("vext.8 q0, q1, q2, #1", q0, q1, i8, 0x77, q2, i8, 0xff); + TESTINSN_bin("vext.8 q0, q1, q2, #9", q0, q1, i8, 0x77, q2, i8, 0xff); + TESTINSN_bin("vext.8 q0, q1, q2, #15", q0, q1, i8, 0x77, q2, i8, 0xff); + TESTINSN_bin("vext.8 q10, q11, q12, #4", q10, q11, i8, 0x77, q12, i8, 0xff); + TESTINSN_bin("vext.8 q0, q5, q15, #12", q0, q5, i8, 0x77, q15, i8, 0xff); + + printf("---- VHADD ----\n"); + TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i8, 141, q2, i8, 121); + TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i8, 141, q2, i8, 121); + TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VHSUB ----\n"); + TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhsub.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhsub.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhsub.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhsub.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhsub.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vhsub.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VQADD ----\n"); + TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqadd.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VQSUB ----\n"); + TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqsub.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqsub.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqsub.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqsub.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqsub.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin_q("vqsub.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VRHADD ----\n"); + TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121); + TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vrhadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VCGT ----\n"); + TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121); + TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140); + TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140); + TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140); + TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 3, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 2, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VCGE ----\n"); + TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121); + TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140); + TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140); + TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140); + TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 3, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 2, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VSHL (register) ----\n"); + TESTINSN_bin("vshl.s8 q0, q1, q2", q0, q1, i32, 24, q2, i32, 1); + TESTINSN_bin("vshl.s8 q8, q1, q12", q8, q1, i32, 24, q12, i32, 8); + TESTINSN_bin("vshl.s8 q10, q11, q7", q10, q11, i32, 24, q7, i32, 4); + TESTINSN_bin("vshl.s16 q3, q8, q11", q3, q8, i32, 14, q11, i32, 2); + TESTINSN_bin("vshl.s16 q5, q12, q14", q5, q12, i32, (1 << 30), q14, i32, 1); + TESTINSN_bin("vshl.s16 q15, q2, q1", q15, q2, i32, (1 << 30), q1, i32, 11); + TESTINSN_bin("vshl.s32 q9, q12, q15", q9, q12, i32, (1 << 31) + 2, q15, i32, 2); + TESTINSN_bin("vshl.s32 q11, q2, q0", q11, q2, i32, -1, q0, i32, 12); + TESTINSN_bin("vshl.s32 q5, q2, q3", q5, q2, i32, (1 << 30), q3, i32, 21); + TESTINSN_bin("vshl.s64 q15, q12, q4", q15, q12, i32, 5, q4, i32, 20); + TESTINSN_bin("vshl.s64 q8, q2, q4", q8, q2, i32, 15, q4, i32, 4); + TESTINSN_bin("vshl.s64 q5, q12, q4", q5, q12, i32, (1 << 31) + 1, q4, i32, 30); + TESTINSN_bin("vshl.u8 q0, q1, q2", q0, q1, i32, 24, q2, i32, 1); + TESTINSN_bin("vshl.u8 q8, q1, q12", q8, q1, i32, 24, q12, i32, 8); + TESTINSN_bin("vshl.u8 q10, q11, q7", q10, q11, i32, 24, q7, i32, 4); + TESTINSN_bin("vshl.u16 q3, q8, q11", q3, q8, i32, 14, q11, i32, 2); + TESTINSN_bin("vshl.u16 q5, q12, q14", q5, q12, i32, (1 << 30), q14, i32, 1); + TESTINSN_bin("vshl.u16 q15, q2, q1", q15, q2, i32, (1 << 30), q1, i32, 11); + TESTINSN_bin("vshl.u32 q9, q12, q15", q9, q12, i32, (1 << 31) + 2, q15, i32, 2); + TESTINSN_bin("vshl.u32 q11, q2, q0", q11, q2, i32, -1, q0, i32, 12); + TESTINSN_bin("vshl.u32 q5, q2, q3", q5, q2, i32, (1 << 30), q3, i32, 21); + TESTINSN_bin("vshl.u64 q15, q12, q4", q15, q12, i32, 5, q4, i32, 20); + TESTINSN_bin("vshl.u64 q8, q2, q4", q8, q2, i32, 15, q4, i32, 4); + TESTINSN_bin("vshl.u64 q5, q12, q4", q5, q12, i32, (1 << 31) + 1, q4, i32, 30); + + printf("---- VQSHL (register) ----\n"); + TESTINSN_bin_q("vqshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1); + TESTINSN_bin_q("vqshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1); + TESTINSN_bin_q("vqshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3); + TESTINSN_bin_q("vqshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14); + TESTINSN_bin_q("vqshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26); + TESTINSN_bin_q("vqshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60); + TESTINSN_bin_q("vqshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30); + TESTINSN_bin_q("vqshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4); + TESTINSN_bin_q("vqshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9); + TESTINSN_bin_q("vqshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7); + TESTINSN_bin_q("vqshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1); + TESTINSN_bin_q("vqshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3); + TESTINSN_bin_q("vqshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31); + TESTINSN_bin_q("vqshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3); + TESTINSN_bin_q("vqshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1); + TESTINSN_bin_q("vqshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31); + TESTINSN_bin_q("vqshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13); + TESTINSN_bin_q("vqshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30); + TESTINSN_bin_q("vqshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40); + TESTINSN_bin_q("vqshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30); + TESTINSN_bin_q("vqshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3); + TESTINSN_bin_q("vqshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16); + TESTINSN_bin_q("vqshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2); + TESTINSN_bin_q("vqshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin_q("vqshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1); + TESTINSN_bin_q("vqshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1); + TESTINSN_bin_q("vqshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3); + TESTINSN_bin_q("vqshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14); + TESTINSN_bin_q("vqshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26); + TESTINSN_bin_q("vqshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60); + TESTINSN_bin_q("vqshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30); + TESTINSN_bin_q("vqshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4); + TESTINSN_bin_q("vqshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9); + TESTINSN_bin_q("vqshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7); + TESTINSN_bin_q("vqshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1); + TESTINSN_bin_q("vqshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3); + TESTINSN_bin_q("vqshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31); + TESTINSN_bin_q("vqshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3); + TESTINSN_bin_q("vqshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1); + TESTINSN_bin_q("vqshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31); + TESTINSN_bin_q("vqshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13); + TESTINSN_bin_q("vqshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30); + TESTINSN_bin_q("vqshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40); + TESTINSN_bin_q("vqshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30); + TESTINSN_bin_q("vqshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3); + TESTINSN_bin_q("vqshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16); + TESTINSN_bin_q("vqshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2); + TESTINSN_bin_q("vqshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VQSHL / VQSHLU (immediate) ----\n"); + TESTINSN_un_q("vqshl.s64 q0, q1, #1", q0, q1, i32, 1); + TESTINSN_un_q("vqshl.s64 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshl.s64 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshl.s64 q5, q4, #63", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s64 q5, q4, #60", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s64 q5, q4, #59", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s64 q5, q4, #58", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s64 q5, q4, #17", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s64 q5, q4, #63", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.s64 q5, q4, #60", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.s64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.s32 q10, q11, #1", q10, q11, i32, 1); + TESTINSN_un_q("vqshl.s32 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshl.s32 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshl.s32 q5, q4, #31", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s32 q5, q4, #28", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s32 q5, q4, #27", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s32 q5, q4, #26", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s32 q5, q4, #17", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s32 q5, q4, #31", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.s32 q5, q4, #29", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.s32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.s16 q9, q8, #1", q9, q8, i32, 1); + TESTINSN_un_q("vqshl.s16 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshl.s16 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshl.s16 q9, q8, #15", q9, q8, i32, 16); + TESTINSN_un_q("vqshl.s16 q5, q4, #12", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s16 q5, q4, #11", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s16 q5, q4, #10", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s16 q5, q4, #4", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s16 q5, q4, #15", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.s16 q5, q4, #12", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.s16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.s8 q0, q1, #1", q0, q1, i32, 1); + TESTINSN_un_q("vqshl.s8 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshl.s8 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshl.s8 q5, q4, #7", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s8 q5, q4, #4", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s8 q5, q4, #3", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s8 q5, q4, #2", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s8 q5, q4, #1", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.s8 q5, q4, #7", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.s8 q5, q4, #5", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.s8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.u64 q0, q1, #1", q0, q1, i32, 1); + TESTINSN_un_q("vqshl.u64 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshl.u64 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshl.u64 q5, q4, #63", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u64 q5, q4, #60", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u64 q5, q4, #59", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u64 q5, q4, #58", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u64 q5, q4, #17", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u64 q5, q4, #63", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.u64 q5, q4, #60", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.u64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.u32 q10, q11, #1", q10, q11, i32, 1); + TESTINSN_un_q("vqshl.u32 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshl.u32 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshl.u32 q5, q4, #31", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u32 q5, q4, #28", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u32 q5, q4, #27", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u32 q5, q4, #26", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u32 q5, q4, #17", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u32 q5, q4, #31", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.u32 q5, q4, #29", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.u32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.u16 q9, q8, #1", q9, q8, i32, 1); + TESTINSN_un_q("vqshl.u16 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshl.u16 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshl.u16 q9, q8, #15", q9, q8, i32, 16); + TESTINSN_un_q("vqshl.u16 q5, q4, #12", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u16 q5, q4, #11", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u16 q5, q4, #10", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u16 q5, q4, #4", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u16 q5, q4, #15", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.u16 q5, q4, #12", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.u16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.u8 q0, q1, #1", q0, q1, i32, 1); + TESTINSN_un_q("vqshl.u8 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshl.u8 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshl.u8 q5, q4, #7", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u8 q5, q4, #4", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u8 q5, q4, #3", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u8 q5, q4, #2", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u8 q5, q4, #1", q5, q4, i32, 16); + TESTINSN_un_q("vqshl.u8 q5, q4, #7", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.u8 q5, q4, #5", q5, q4, i32, -1); + TESTINSN_un_q("vqshl.u8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshlu.s64 q0, q1, #1", q0, q1, i32, 1); + TESTINSN_un_q("vqshlu.s64 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshlu.s64 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshlu.s64 q5, q4, #63", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s64 q5, q4, #60", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s64 q5, q4, #59", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s64 q5, q4, #58", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s64 q5, q4, #17", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s64 q5, q4, #63", q5, q4, i32, -1); + TESTINSN_un_q("vqshlu.s64 q5, q4, #60", q5, q4, i32, -1); + TESTINSN_un_q("vqshlu.s64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshlu.s32 q10, q11, #1", q10, q11, i32, 1); + TESTINSN_un_q("vqshlu.s32 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshlu.s32 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshlu.s32 q5, q4, #31", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s32 q5, q4, #28", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s32 q5, q4, #27", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s32 q5, q4, #26", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s32 q5, q4, #17", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s32 q5, q4, #31", q5, q4, i32, -1); + TESTINSN_un_q("vqshlu.s32 q5, q4, #29", q5, q4, i32, -1); + TESTINSN_un_q("vqshlu.s32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshlu.s16 q9, q8, #1", q9, q8, i32, 1); + TESTINSN_un_q("vqshlu.s16 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshlu.s16 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshlu.s16 q9, q8, #15", q9, q8, i32, 16); + TESTINSN_un_q("vqshlu.s16 q5, q4, #12", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s16 q5, q4, #11", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s16 q5, q4, #10", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s16 q5, q4, #4", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s16 q5, q4, #15", q5, q4, i32, -1); + TESTINSN_un_q("vqshlu.s16 q5, q4, #12", q5, q4, i32, -1); + TESTINSN_un_q("vqshlu.s16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshlu.s8 q0, q1, #1", q0, q1, i32, 1); + TESTINSN_un_q("vqshlu.s8 q15, q14, #1", q15, q14, i32, -127); + TESTINSN_un_q("vqshlu.s8 q5, q4, #0", q5, q4, i32, -127); + TESTINSN_un_q("vqshlu.s8 q5, q4, #7", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s8 q5, q4, #4", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s8 q5, q4, #3", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s8 q5, q4, #2", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s8 q5, q4, #1", q5, q4, i32, 16); + TESTINSN_un_q("vqshlu.s8 q5, q4, #7", q5, q4, i32, -1); + TESTINSN_un_q("vqshlu.s8 q5, q4, #5", q5, q4, i32, -1); + TESTINSN_un_q("vqshlu.s8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2); + + printf("---- VQRSHL (register) ----\n"); + TESTINSN_bin_q("vqrshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1); + TESTINSN_bin_q("vqrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1); + TESTINSN_bin_q("vqrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3); + TESTINSN_bin_q("vqrshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14); + TESTINSN_bin_q("vqrshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26); + TESTINSN_bin_q("vqrshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60); + TESTINSN_bin_q("vqrshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30); + TESTINSN_bin_q("vqrshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4); + TESTINSN_bin_q("vqrshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9); + TESTINSN_bin_q("vqrshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7); + TESTINSN_bin_q("vqrshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3); + TESTINSN_bin_q("vqrshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31); + TESTINSN_bin_q("vqrshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3); + TESTINSN_bin_q("vqrshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1); + TESTINSN_bin_q("vqrshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31); + TESTINSN_bin_q("vqrshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13); + TESTINSN_bin_q("vqrshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30); + TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40); + TESTINSN_bin_q("vqrshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30); + TESTINSN_bin_q("vqrshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3); + TESTINSN_bin_q("vqrshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16); + TESTINSN_bin_q("vqrshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2); + TESTINSN_bin_q("vqrshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin_q("vqrshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1); + TESTINSN_bin_q("vqrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1); + TESTINSN_bin_q("vqrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3); + TESTINSN_bin_q("vqrshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14); + TESTINSN_bin_q("vqrshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26); + TESTINSN_bin_q("vqrshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60); + TESTINSN_bin_q("vqrshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30); + TESTINSN_bin_q("vqrshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4); + TESTINSN_bin_q("vqrshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9); + TESTINSN_bin_q("vqrshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7); + TESTINSN_bin_q("vqrshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1); + TESTINSN_bin_q("vqrshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3); + TESTINSN_bin_q("vqrshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31); + TESTINSN_bin_q("vqrshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3); + TESTINSN_bin_q("vqrshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1); + TESTINSN_bin_q("vqrshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31); + TESTINSN_bin_q("vqrshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13); + TESTINSN_bin_q("vqrshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30); + TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40); + TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin_q("vqrshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30); + TESTINSN_bin_q("vqrshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3); + TESTINSN_bin_q("vqrshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16); + TESTINSN_bin_q("vqrshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2); + TESTINSN_bin_q("vqrshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VRSHL (register) ----\n"); + TESTINSN_bin("vrshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1); + TESTINSN_bin("vrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1); + TESTINSN_bin("vrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3); + TESTINSN_bin("vrshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14); + TESTINSN_bin("vrshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26); + TESTINSN_bin("vrshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60); + TESTINSN_bin("vrshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30); + TESTINSN_bin("vrshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4); + TESTINSN_bin("vrshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9); + TESTINSN_bin("vrshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7); + TESTINSN_bin("vrshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1); + TESTINSN_bin("vrshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3); + TESTINSN_bin("vrshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31); + TESTINSN_bin("vrshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3); + TESTINSN_bin("vrshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1); + TESTINSN_bin("vrshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31); + TESTINSN_bin("vrshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13); + TESTINSN_bin("vrshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30); + TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0); + TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40); + TESTINSN_bin("vrshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30); + TESTINSN_bin("vrshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3); + TESTINSN_bin("vrshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16); + TESTINSN_bin("vrshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2); + TESTINSN_bin("vrshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vrshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1); + TESTINSN_bin("vrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1); + TESTINSN_bin("vrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3); + TESTINSN_bin("vrshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14); + TESTINSN_bin("vrshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26); + TESTINSN_bin("vrshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60); + TESTINSN_bin("vrshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30); + TESTINSN_bin("vrshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4); + TESTINSN_bin("vrshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9); + TESTINSN_bin("vrshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7); + TESTINSN_bin("vrshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1); + TESTINSN_bin("vrshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3); + TESTINSN_bin("vrshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31); + TESTINSN_bin("vrshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3); + TESTINSN_bin("vrshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1); + TESTINSN_bin("vrshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31); + TESTINSN_bin("vrshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13); + TESTINSN_bin("vrshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30); + TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40); + TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1); + TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1); + TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1); + TESTINSN_bin("vrshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30); + TESTINSN_bin("vrshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3); + TESTINSN_bin("vrshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16); + TESTINSN_bin("vrshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2); + TESTINSN_bin("vrshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VMAX (integer) ----\n"); + TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121); + TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 121); + TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vmax.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 120); + TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VMIN (integer) ----\n"); + TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121); + TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 121); + TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vmin.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 120); + TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120); + TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140); + TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VABD ----\n"); + TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121); + TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, -120); + TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vabd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200); + TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, -140, q2, i32, 120); + TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vabd.u8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200); + TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VABA ----\n"); + TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121); + TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vaba.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200); + TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120); + TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vaba.u8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200); + TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VABAL ----\n"); + TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabal.s8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200); + TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.s32 q10, d31, d12", q10, d31, i32, 24, d12, i32, 120); + TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabal.u8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.u8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200); + TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabal.u32 q10, d11, d12", q10, d11, i32, 24, d12, i32, 120); + + printf("---- VABDL ----\n"); + TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabdl.s8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200); + TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.s32 q10, d31, d12", q10, d31, i32, 24, d12, i32, 120); + TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabdl.u8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.u8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200); + TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabdl.u32 q10, d11, d12", q10, d11, i32, 24, d12, i32, 120); + + printf("---- VTST ----\n"); + TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vtst.32 q3, q4, q5", q3, q4, i32, 140, q5, i32, 120); + TESTINSN_bin("vtst.16 q6, q7, q8", q6, q7, i32, 120, q8, i32, 120); + TESTINSN_bin("vtst.8 q9, q10, q12", q9, q10, i32, 140, q12, i32, 120); + TESTINSN_bin("vtst.8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vtst.16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1); + TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vtst.8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, 2); + TESTINSN_bin("vtst.16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1); + TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vtst.32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VCEQ ----\n"); + TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vceq.i32 q3, q4, q5", q3, q4, i32, 140, q5, i32, 120); + TESTINSN_bin("vceq.i16 q6, q7, q8", q6, q7, i32, 120, q8, i32, 120); + TESTINSN_bin("vceq.i8 q9, q10, q12", q9, q10, i32, 140, q12, i32, 120); + TESTINSN_bin("vceq.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vceq.i16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1); + TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vceq.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, 2); + TESTINSN_bin("vceq.i16 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 14) + 1); + TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 31) + 2); + TESTINSN_bin("vceq.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120); + + printf("---- VMLA ----\n"); + TESTINSN_bin("vmla.i32 q0, q1, q2", q0, q1, i32, -24, q2, i32, 120); + TESTINSN_bin("vmla.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, 120); + TESTINSN_bin("vmla.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120); + TESTINSN_bin("vmla.i16 q7, q1, q2", q7, q1, i32, 0x140, q2, i32, 0x120); + TESTINSN_bin("vmla.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, -120); + TESTINSN_bin("vmla.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2); + TESTINSN_bin("vmla.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i16 q14, q5, q9", q14, q5, i32, (1 << 14) + 1, q9, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin("vmla.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2); + TESTINSN_bin("vmla.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin("vmla.i32 q10, q11, q15", q10, q11, i32, 24, q15, i32, -120); + + printf("---- VMLS ----\n"); + TESTINSN_bin("vmls.i32 q0, q1, q2", q0, q1, i32, -24, q2, i32, 120); + TESTINSN_bin("vmls.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120); + TESTINSN_bin("vmls.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120); + TESTINSN_bin("vmls.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vmls.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2); + TESTINSN_bin("vmls.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin("vmls.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2); + TESTINSN_bin("vmls.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin("vmls.i32 q10, q11, q15", q10, q11, i32, -24, q15, i32, 120); + + printf("---- VMUL ----\n"); + TESTINSN_bin("vmul.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin("vmul.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120); + TESTINSN_bin("vmul.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120); + TESTINSN_bin("vmul.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120); + TESTINSN_bin("vmul.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2); + TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin("vmul.i8 q10, q11, q12", q10, q11, i32, (1 << 25) + 0xfeb2, q12, i32, (1 << 13) + 0xdf); + TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12); + TESTINSN_bin("vmul.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2); + TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin("vmul.i32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120); + TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 3, q2, i32, 3); + TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 12, q2, i8, 0x0f); + + printf("---- VMUL (by scalar) ----\n"); + TESTINSN_bin("vmul.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmul.i32 q15, q8, d7[1]", q15, q8, i32, 140, d4, i32, -120); + TESTINSN_bin("vmul.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmul.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmul.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmul.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VMLA (by scalar) ----\n"); + TESTINSN_bin("vmla.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmla.i32 q15, q8, d7[1]", q15, q8, i32, 140, d7, i32, -120); + TESTINSN_bin("vmla.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmla.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmla.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmla.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VMLS (by scalar) ----\n"); + TESTINSN_bin("vmls.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmls.i32 q15, q8, d7[1]", q15, q8, i32, 140, d7, i32, -120); + TESTINSN_bin("vmls.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmls.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmls.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmls.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VMULL (by scalar) ----\n"); + TESTINSN_bin("vmull.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120); + TESTINSN_bin("vmull.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120); + TESTINSN_bin("vmull.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmull.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmull.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + TESTINSN_bin("vmull.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmull.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120); + TESTINSN_bin("vmull.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmull.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmull.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmull.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VMLAL (by scalar) ----\n"); + TESTINSN_bin("vmlal.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120); + TESTINSN_bin("vmlal.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120); + TESTINSN_bin("vmlal.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmlal.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmlal.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + TESTINSN_bin("vmlal.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmlal.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120); + TESTINSN_bin("vmlal.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmlal.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmlal.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmlal.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VMLSL (by scalar) ----\n"); + TESTINSN_bin("vmlsl.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120); + TESTINSN_bin("vmlsl.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120); + TESTINSN_bin("vmlsl.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmlsl.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmlsl.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + TESTINSN_bin("vmlsl.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmlsl.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120); + TESTINSN_bin("vmlsl.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmlsl.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmlsl.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmlsl.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VRSHR ----\n"); + TESTINSN_un("vrshr.s8 q0, q1, #0", q0, q1, i32, -1); + TESTINSN_un("vrshr.s8 q0, q1, #1", q0, q1, i32, -1); + TESTINSN_un("vrshr.s16 q3, q4, #2", q3, q4, i32, -0x7c); + TESTINSN_un("vrshr.s32 q2, q5, #31", q2, q5, i32, -1); + TESTINSN_un("vrshr.s8 q6, q7, #7", q6, q7, i32, 0xffff); + TESTINSN_un("vrshr.s16 q8, q9, #12", q8, q9, i32, -10); + TESTINSN_un("vrshr.s32 q10, q11, #5", q10, q11, i32, 10234); + TESTINSN_un("vrshr.u8 q12, q13, #1", q12, q13, i32, -1); + TESTINSN_un("vrshr.u16 q14, q15, #11", q14, q15, i32, -1); + TESTINSN_un("vrshr.u32 q10, q11, #9", q10, q11, i32, 1000); + TESTINSN_un("vrshr.u8 q7, q13, #7", q7, q13, i32, -1); + TESTINSN_un("vrshr.u16 q8, q1, #5", q8, q1, i32, 0xabcf); + TESTINSN_un("vrshr.u32 q12, q3, #15", q12, q3, i32, -0x1b0); + TESTINSN_un("vrshr.u64 q0, q1, #42", q0, q1, i32, -1); + TESTINSN_un("vrshr.s64 q6, q7, #12", q6, q7, i32, 0xfac); + TESTINSN_un("vrshr.u64 q8, q4, #9", q8, q4, i32, 13560); + TESTINSN_un("vrshr.s64 q9, q12, #11", q9, q12, i32, 98710); + + printf("---- VRSRA ----\n"); + TESTINSN_un("vrsra.s8 q0, q1, #1", q0, q1, i32, -1); + TESTINSN_un("vrsra.s16 q3, q4, #2", q3, q4, i32, -0x7c); + TESTINSN_un("vrsra.s32 q2, q5, #31", q2, q5, i32, -1); + TESTINSN_un("vrsra.s8 q6, q7, #7", q6, q7, i32, 0xffff); + TESTINSN_un("vrsra.s16 q8, q9, #12", q8, q9, i32, -10); + TESTINSN_un("vrsra.s32 q10, q11, #5", q10, q11, i32, 10234); + TESTINSN_un("vrsra.u8 q12, q13, #1", q12, q13, i32, -1); + TESTINSN_un("vrsra.u16 q14, q15, #11", q14, q15, i32, -1); + TESTINSN_un("vrsra.u32 q10, q11, #9", q10, q11, i32, 1000); + TESTINSN_un("vrsra.u8 q7, q13, #7", q7, q13, i32, -1); + TESTINSN_un("vrsra.u16 q8, q1, #5", q8, q1, i32, 0xabcf); + TESTINSN_un("vrsra.u32 q12, q3, #15", q12, q3, i32, -0x1b0); + TESTINSN_un("vrsra.u64 q0, q1, #42", q0, q1, i32, -1); + TESTINSN_un("vrsra.s64 q6, q7, #12", q6, q7, i32, 0xfac); + TESTINSN_un("vrsra.u64 q8, q4, #9", q8, q4, i32, 13560); + TESTINSN_un("vrsra.s64 q9, q12, #11", q9, q12, i32, 98710); + + printf("---- VSHR ----\n"); + TESTINSN_un("vshr.s8 q0, q1, #0", q0, q1, i32, -1); + TESTINSN_un("vshr.s8 q0, q1, #1", q0, q1, i32, -1); + TESTINSN_un("vshr.s16 q3, q4, #2", q3, q4, i32, -0x7c); + TESTINSN_un("vshr.s32 q2, q5, #31", q2, q5, i32, -1); + TESTINSN_un("vshr.s8 q6, q7, #7", q6, q7, i32, 0xffff); + TESTINSN_un("vshr.s16 q8, q9, #12", q8, q9, i32, -10); + TESTINSN_un("vshr.s32 q10, q11, #5", q10, q11, i32, 10234); + TESTINSN_un("vshr.u8 q12, q13, #1", q12, q13, i32, -1); + TESTINSN_un("vshr.u16 q14, q15, #11", q14, q15, i32, -1); + TESTINSN_un("vshr.u32 q10, q11, #9", q10, q11, i32, 1000); + TESTINSN_un("vshr.u8 q7, q13, #7", q7, q13, i32, -1); + TESTINSN_un("vshr.u16 q8, q1, #5", q8, q1, i32, 0xabcf); + TESTINSN_un("vshr.u32 q12, q3, #15", q12, q3, i32, -0x1b0); + TESTINSN_un("vshr.u64 q0, q1, #42", q0, q1, i32, -1); + TESTINSN_un("vshr.s64 q6, q7, #12", q6, q7, i32, 0xfac); + TESTINSN_un("vshr.u64 q8, q4, #9", q8, q4, i32, 13560); + TESTINSN_un("vshr.s64 q9, q12, #11", q9, q12, i32, 98710); + + printf("---- VSRA ----\n"); + TESTINSN_un("vsra.s8 q0, q1, #1", q0, q1, i32, -1); + TESTINSN_un("vsra.s16 q3, q4, #2", q3, q4, i32, -0x7c); + TESTINSN_un("vsra.s32 q2, q5, #31", q2, q5, i32, -1); + TESTINSN_un("vsra.s8 q6, q7, #7", q6, q7, i32, 0xffff); + TESTINSN_un("vsra.s16 q8, q9, #12", q8, q9, i32, -10); + TESTINSN_un("vsra.s32 q10, q11, #5", q10, q11, i32, 10234); + TESTINSN_un("vsra.u8 q12, q13, #1", q12, q13, i32, -1); + TESTINSN_un("vsra.u16 q14, q15, #11", q14, q15, i32, -1); + TESTINSN_un("vsra.u32 q10, q11, #9", q10, q11, i32, 1000); + TESTINSN_un("vsra.u8 q7, q13, #7", q7, q13, i32, -1); + TESTINSN_un("vsra.u16 q8, q1, #5", q8, q1, i32, 0xabcf); + TESTINSN_un("vsra.u32 q12, q3, #15", q12, q3, i32, -0x1b0); + TESTINSN_un("vsra.u64 q0, q1, #42", q0, q1, i32, -1); + TESTINSN_un("vsra.s64 q6, q7, #12", q6, q7, i32, 0xfac); + TESTINSN_un("vsra.u64 q8, q4, #9", q8, q4, i32, 13560); + TESTINSN_un("vsra.s64 q9, q12, #11", q9, q12, i32, 98710); + + printf("---- VSRI ----\n"); + TESTINSN_un("vsri.16 q0, q1, #1", q0, q1, i32, -1); + TESTINSN_un("vsri.16 q3, q4, #2", q3, q4, i32, -0x7c); + TESTINSN_un("vsri.32 q2, q5, #31", q2, q5, i32, -1); + TESTINSN_un("vsri.8 q6, q7, #7", q6, q7, i32, 0xffff); + TESTINSN_un("vsri.16 q8, q9, #12", q8, q9, i32, -10); + TESTINSN_un("vsri.32 q10, q11, #5", q10, q11, i32, 10234); + TESTINSN_un("vsri.8 q12, q13, #1", q12, q13, i32, -1); + TESTINSN_un("vsri.16 q14, q15, #11", q14, q15, i32, -1); + TESTINSN_un("vsri.32 q10, q11, #9", q10, q11, i32, 1000); + TESTINSN_un("vsri.8 q7, q13, #7", q7, q13, i32, -1); + TESTINSN_un("vsri.16 q8, q1, #5", q8, q1, i32, 0xabcf); + TESTINSN_un("vsri.32 q12, q3, #15", q12, q3, i32, -0x1b0); + TESTINSN_un("vsri.64 q0, q1, #42", q0, q1, i32, -1); + TESTINSN_un("vsri.64 q6, q7, #12", q6, q7, i32, 0xfac); + TESTINSN_un("vsri.64 q8, q4, #9", q8, q4, i32, 13560); + TESTINSN_un("vsri.64 q9, q12, #11", q9, q12, i32, 98710); + + printf("---- VMOVL ----\n"); + TESTINSN_un("vmovl.u32 q0, d2", q0, d2, i32, 0x42); + TESTINSN_un("vmovl.u16 q15, d2", q15, d2, i32, 0x42); + TESTINSN_un("vmovl.u8 q3, d31", q0, d31, i32, 0x42); + TESTINSN_un("vmovl.s32 q0, d2", q0, d2, i32, 0x42); + TESTINSN_un("vmovl.s16 q15, d2", q15, d2, i32, 0x42); + TESTINSN_un("vmovl.s8 q3, d31", q0, d31, i32, 0x42); + TESTINSN_un("vmovl.u32 q0, d2", q0, d2, i8, 0xed); + TESTINSN_un("vmovl.u16 q15, d2", q15, d2, i8, 0xed); + TESTINSN_un("vmovl.u8 q3, d31", q0, d31, i8, 0xed); + TESTINSN_un("vmovl.s32 q0, d2", q0, d2, i8, 0xed); + TESTINSN_un("vmovl.s16 q15, d2", q15, d2, i8, 0xed); + TESTINSN_un("vmovl.s8 q3, d31", q0, d31, i8, 0xed); + + printf("---- VABS ----\n"); + TESTINSN_un("vabs.s32 q0, q1", q0, q1, i32, 0x73); + TESTINSN_un("vabs.s16 q15, q4", q15, q4, i32, 0x73); + TESTINSN_un("vabs.s8 q8, q7", q8, q7, i32, 0x73); + TESTINSN_un("vabs.s32 q0, q1", q0, q1, i32, 0xfe); + TESTINSN_un("vabs.s16 q15, q4", q15, q4, i32, 0xef); + TESTINSN_un("vabs.s8 q8, q7", q8, q7, i32, 0xde); + TESTINSN_un("vabs.s32 q0, q1", q0, q1, i16, 0xfe0a); + TESTINSN_un("vabs.s16 q15, q4", q15, q4, i16, 0xef0b); + TESTINSN_un("vabs.s8 q8, q7", q8, q7, i16, 0xde0c); + + printf("---- VQABS ----\n"); + TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 0x73); + TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 1 << 31); + TESTINSN_un_q("vqabs.s16 q0, q1", q0, q1, i32, 1 << 31); + TESTINSN_un_q("vqabs.s8 q0, q1", q0, q1, i32, 1 << 31); + TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i32, 0x73); + TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i32, 0x73); + TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 0xfe); + TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i32, 0xef); + TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i32, 0xde); + TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i16, 0xfe0a); + TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i16, 0xef0b); + TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i16, 0xde0c); + + printf("---- VADDW ----\n"); + TESTINSN_bin("vaddw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0x12); + TESTINSN_bin("vaddw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0xe2); + TESTINSN_bin("vaddw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2); + + printf("---- VADDL ----\n"); + TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0x12); + TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0xe2); + TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i8, 0x99, d31, i8, 0x12); + TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2); + TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0xe2); + TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i8, 0x93, d31, i8, 0xe2); + TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2); + TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2); + TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2); + + printf("---- VSUBW ----\n"); + TESTINSN_bin("vsubw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0x12); + TESTINSN_bin("vsubw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0xe2); + TESTINSN_bin("vsubw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2); + + printf("---- VSUBL ----\n"); + TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0x12); + TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12); + TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0xe2); + TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2); + TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i8, 0x99, d31, i8, 0x12); + TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12); + TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2); + TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0xe2); + TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i8, 0x93, d31, i8, 0xe2); + TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2); + TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2); + TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2); + + printf("---- VCEQ #0 ----\n"); + TESTINSN_un("vceq.i32 q0, q1, #0", q0, q1, i32, 0x21); + TESTINSN_un("vceq.i16 q2, q1, #0", q2, q1, i32, 0x21); + TESTINSN_un("vceq.i8 q10, q11, #0", q10, q11, i32, 0x21); + TESTINSN_un("vceq.i32 q0, q1, #0", q0, q1, i32, 0x0); + TESTINSN_un("vceq.i16 q2, q1, #0", q2, q1, i32, 0x0); + TESTINSN_un("vceq.i8 q10, q11, #0", q10, q11, i32, 0x0); + + printf("---- VCGT #0 ----\n"); + TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i32, 0x21); + TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i32, 0x21); + TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i32, 0x21); + TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i32, 0x0); + TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i32, 0x0); + TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i32, 0x0); + TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i8, 0xef); + TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i8, 0xed); + TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i8, 0xae); + + printf("---- VCGE #0 ----\n"); + TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0x21); + TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0x21); + TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0x21); + TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0x0); + TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0x0); + TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0x0); + TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i8, 0xef); + TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i8, 0xed); + TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i8, 0xae); + TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0xef); + TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0xed); + TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0xae); + + printf("---- VCLE #0 ----\n"); + TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i32, 0x21); + TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i32, 0x21); + TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i32, 0x21); + TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i32, 0x0); + TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i32, 0x0); + TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i32, 0x0); + TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i8, 0xef); + TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i8, 0xed); + TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i8, 0xae); + + printf("---- VCLT #0 ----\n"); + TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0x21); + TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0x21); + TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0x21); + TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0x0); + TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0x0); + TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0x0); + TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i8, 0xef); + TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i8, 0xed); + TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i8, 0xae); + TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0xef); + TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0xed); + TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0xae); + + printf("---- VCNT ----\n"); + TESTINSN_un("vcnt.8 q0, q1", q0, q1, i32, 0xac3d25eb); + TESTINSN_un("vcnt.8 q11, q14", q11, q14, i32, 0xac3d25eb); + TESTINSN_un("vcnt.8 q6, q2", q6, q2, i32, 0xad0eb); + + printf("---- VCLS ----\n"); + TESTINSN_un("vcls.s8 q0, q1", q0, q1, i32, 0x21); + TESTINSN_un("vcls.s8 q10, q15", q10, q15, i8, 0x82); + TESTINSN_un("vcls.s16 q0, q1", q0, q1, i32, 0x21); + TESTINSN_un("vcls.s16 q15, q10", q15, q10, i8, 0x82); + TESTINSN_un("vcls.s32 q6, q1", q6, q1, i32, 0x21); + TESTINSN_un("vcls.s32 q10, q5", q10, q5, i8, 0x82); + TESTINSN_un("vcls.s8 q2, q4", q2, q4, i8, 0xff); + TESTINSN_un("vcls.s16 q2, q4", q2, q4, i8, 0xff); + TESTINSN_un("vcls.s32 q2, q4", q2, q4, i8, 0xff); + TESTINSN_un("vcls.s8 q2, q4", q2, q4, i16, 0xffef); + TESTINSN_un("vcls.s16 q2, q4", q2, q4, i16, 0xffef); + TESTINSN_un("vcls.s32 q2, q4", q2, q4, i16, 0xffef); + TESTINSN_un("vcls.s8 q2, q4", q2, q4, i8, 0x00); + TESTINSN_un("vcls.s16 q2, q4", q2, q4, i8, 0x00); + TESTINSN_un("vcls.s32 q2, q4", q2, q4, i8, 0x00); + TESTINSN_un("vcls.s8 q2, q4", q2, q4, i16, 0x00ef); + TESTINSN_un("vcls.s16 q2, q4", q2, q4, i16, 0x00ef); + TESTINSN_un("vcls.s32 q2, q4", q2, q4, i16, 0x00ef); + + printf("---- VCLZ ----\n"); + TESTINSN_un("vclz.i8 q0, q1", q0, q1, i32, 0x21); + TESTINSN_un("vclz.i8 q10, q15", q10, q15, i8, 0x82); + TESTINSN_un("vclz.i16 q0, q1", q0, q1, i32, 0x21); + TESTINSN_un("vclz.i16 q15, q10", q15, q10, i8, 0x82); + TESTINSN_un("vclz.i32 q6, q1", q6, q1, i32, 0x21); + TESTINSN_un("vclz.i32 q10, q5", q10, q5, i8, 0x82); + TESTINSN_un("vclz.i8 q2, q4", q2, q4, i8, 0xff); + TESTINSN_un("vclz.i16 q2, q4", q2, q4, i8, 0xff); + TESTINSN_un("vclz.i32 q2, q4", q2, q4, i8, 0xff); + TESTINSN_un("vclz.i8 q2, q4", q2, q4, i16, 0xffef); + TESTINSN_un("vclz.i16 q2, q4", q2, q4, i16, 0xffef); + TESTINSN_un("vclz.i32 q2, q4", q2, q4, i16, 0xffef); + TESTINSN_un("vclz.i8 q2, q4", q2, q4, i8, 0x00); + TESTINSN_un("vclz.i16 q2, q4", q2, q4, i8, 0x00); + TESTINSN_un("vclz.i32 q2, q4", q2, q4, i8, 0x00); + TESTINSN_un("vclz.i8 q2, q4", q2, q4, i16, 0x00ef); + TESTINSN_un("vclz.i16 q2, q4", q2, q4, i16, 0x00ef); + TESTINSN_un("vclz.i32 q2, q4", q2, q4, i16, 0x00ef); + + printf("---- VSLI ----\n"); + TESTINSN_un("vsli.16 q0, q1, #1", q0, q1, i32, -1); + TESTINSN_un("vsli.16 q3, q4, #2", q3, q4, i32, -0x7c); + TESTINSN_un("vsli.32 q2, q5, #31", q2, q5, i32, -1); + TESTINSN_un("vsli.8 q6, q7, #7", q6, q7, i32, 0xffff); + TESTINSN_un("vsli.16 q8, q9, #12", q8, q9, i32, -10); + TESTINSN_un("vsli.32 q10, q11, #5", q10, q11, i32, 10234); + TESTINSN_un("vsli.8 q12, q13, #1", q12, q13, i32, -1); + TESTINSN_un("vsli.16 q14, q15, #11", q14, q15, i32, -1); + TESTINSN_un("vsli.32 q10, q11, #9", q10, q11, i32, 1000); + TESTINSN_un("vsli.8 q7, q13, #7", q7, q13, i32, -1); + TESTINSN_un("vsli.16 q8, q1, #1", q8, q1, i32, 0xabcf); + TESTINSN_un("vsli.32 q12, q3, #15", q12, q3, i32, -0x1b0); + TESTINSN_un("vsli.64 q0, q1, #42", q0, q1, i32, -1); + TESTINSN_un("vsli.64 q6, q7, #12", q6, q7, i32, 0xfac); + TESTINSN_un("vsli.64 q8, q4, #9", q8, q4, i32, 13560); + TESTINSN_un("vsli.64 q9, q12, #11", q9, q12, i32, 98710); + + printf("---- VPADDL ----\n"); + TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, 24); + TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpaddl.u16 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpaddl.u8 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpaddl.u8 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.u16 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.u32 q10, q11", q10, q11, i32, 24); + TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, 24); + TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpaddl.s16 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpaddl.s8 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpaddl.s8 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.s16 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.s32 q10, q11", q10, q11, i32, 24); + + printf("---- VPADAL ----\n"); + TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, 24); + TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpadal.u16 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpadal.u8 q0, q1", q0, q1, i8, 140); + TESTINSN_un("vpadal.u8 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.u16 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.u32 q10, q11", q10, q11, i32, 24); + TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, 24); + TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpadal.s16 q0, q1", q0, q1, i32, 140); + TESTINSN_un("vpadal.s8 q0, q1", q0, q1, i8, 140); + TESTINSN_un("vpadal.s8 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.s16 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.s32 q10, q11", q10, q11, i32, 24); + + printf("---- VZIP ----\n"); + TESTINSN_dual("vzip.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34); + TESTINSN_dual("vzip.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34); + TESTINSN_dual("vzip.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34); + TESTINSN_dual("vzip.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d); + TESTINSN_dual("vzip.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d); + TESTINSN_dual("vzip.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d); + + printf("---- VUZP ----\n"); + TESTINSN_dual("vuzp.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34); + TESTINSN_dual("vuzp.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34); + TESTINSN_dual("vuzp.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34); + TESTINSN_dual("vuzp.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d); + TESTINSN_dual("vuzp.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d); + TESTINSN_dual("vuzp.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d); + + printf("---- VTRN ----\n"); + TESTINSN_dual("vtrn.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34); + TESTINSN_dual("vtrn.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34); + TESTINSN_dual("vtrn.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34); + TESTINSN_dual("vtrn.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d); + TESTINSN_dual("vtrn.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d); + TESTINSN_dual("vtrn.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d); + + printf("---- VSWP ----\n"); + TESTINSN_dual("vswp q0, q1", q0, i8, 0x12, q1, i8, 0x34); + TESTINSN_dual("vswp q1, q0", q0, i8, 0x12, q1, i8, 0x34); + TESTINSN_dual("vswp q10, q11", q10, i8, 0x12, q11, i8, 0x34); + TESTINSN_dual("vswp q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d); + TESTINSN_dual("vswp q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d); + TESTINSN_dual("vswp q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d); + + printf("---- VDUP ----\n"); + TESTINSN_un("vdup.8 q2, d2[0]", q2, d2, i32, 0xabc4657); + TESTINSN_un("vdup.8 q3, d3[2]", q3, d3, i32, 0x7a1b3); + TESTINSN_un("vdup.8 q1, d0[7]", q1, d0, i32, 0x713aaa); + TESTINSN_un("vdup.8 q0, d4[3]", q0, d4, i32, 0xaa713); + TESTINSN_un("vdup.8 q4, d28[4]", q4, d28, i32, 0x7b1c3); + TESTINSN_un("vdup.16 q7, d19[3]", q7, d19, i32, 0x713ffff); + TESTINSN_un("vdup.16 q15, d31[0]", q15, d31, i32, 0x7f00fa); + TESTINSN_un("vdup.16 q6, d2[0]", q6, d2, i32, 0xffabcde); + TESTINSN_un("vdup.16 q8, d22[3]", q8, d22, i32, 0x713); + TESTINSN_un("vdup.16 q9, d2[0]", q9, d2, i32, 0x713); + TESTINSN_un("vdup.32 q10, d17[1]", q10, d17, i32, 0x713); + TESTINSN_un("vdup.32 q15, d11[0]", q15, d11, i32, 0x3); + TESTINSN_un("vdup.32 q10, d29[1]", q10, d29, i32, 0xf00000aa); + TESTINSN_un("vdup.32 q12, d0[1]", q12, d0, i32, 0xf); + TESTINSN_un("vdup.32 q13, d13[0]", q13, d13, i32, -1); + + printf("---- VQDMULL ----\n"); + TESTINSN_bin_q("vqdmull.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqdmull.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin_q("vqdmull.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmull.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmull.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmull.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + + printf("---- VQDMULL (by scalar) ----\n"); + TESTINSN_bin_q("vqdmull.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120); + TESTINSN_bin_q("vqdmull.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120); + TESTINSN_bin_q("vqdmull.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2); + TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12); + TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmull.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmull.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmull.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmull.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmull.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30); + + printf("---- VQDMLSL ----\n"); + TESTINSN_bin_q("vqdmlsl.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqdmlsl.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin_q("vqdmlsl.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmlsl.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + + printf("---- VQDMLSL (by scalar) ----\n"); + TESTINSN_bin_q("vqdmlsl.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120); + TESTINSN_bin_q("vqdmlsl.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120); + TESTINSN_bin_q("vqdmlsl.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12); + TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmlsl.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30); + + printf("---- VQDMLAL ----\n"); + TESTINSN_bin_q("vqdmlal.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqdmlal.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin_q("vqdmlal.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmlal.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + + printf("---- VQDMLAL (by scalar) ----\n"); + TESTINSN_bin_q("vqdmlal.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120); + TESTINSN_bin_q("vqdmlal.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120); + TESTINSN_bin_q("vqdmlal.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12); + TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmlal.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmlal.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmlal.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmlal.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31); + TESTINSN_bin_q("vqdmlal.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30); + + printf("---- VQDMULH ----\n"); + TESTINSN_bin_q("vqdmulh.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin_q("vqdmulh.s32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120); + TESTINSN_bin_q("vqdmulh.s16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120); + TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12); + TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmulh.s32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120); + TESTINSN_bin_q("vqdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 30, q15, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 30); + + printf("---- VQDMULH (by scalar) ----\n"); + TESTINSN_bin_q("vqdmulh.s32 q0, q1, d6[0]", q0, q1, i32, 24, d6, i32, 120); + TESTINSN_bin_q("vqdmulh.s32 q6, q7, d1[1]", q6, q7, i32, 140, d1, i32, -120); + TESTINSN_bin_q("vqdmulh.s16 q9, q11, d7[0]", q9, q11, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[1]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[1]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[2]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmulh.s32 q10, q11, d15[0]", q10, q11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s16 q10, q14, d7[3]", q10, q14, i32, 1 << 31, q15, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 30, d15, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s16 q10, q14, d7[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 30); + + printf("---- VSHL (immediate) ----\n"); + TESTINSN_un("vshl.i64 q0, q1, #1", q0, q1, i32, 24); + TESTINSN_un("vshl.i64 q5, q2, #1", q5, q2, i32, (1 << 30)); + TESTINSN_un("vshl.i64 q9, q12, #2", q9, q12, i32, (1 << 31) + 2); + TESTINSN_un("vshl.i64 q11, q2, #12", q11, q2, i32, -1); + TESTINSN_un("vshl.i64 q15, q12, #63", q15, q12, i32, 5); + TESTINSN_un("vshl.i64 q5, q12, #62", q5, q12, i32, (1 << 31) + 1); + TESTINSN_un("vshl.i32 q0, q1, #1", q0, q1, i32, 24); + TESTINSN_un("vshl.i32 q5, q2, #1", q5, q2, i32, (1 << 30)); + TESTINSN_un("vshl.i32 q9, q12, #2", q9, q12, i32, (1 << 31) + 2); + TESTINSN_un("vshl.i32 q11, q2, #12", q11, q2, i32, -1); + TESTINSN_un("vshl.i32 q15, q12, #20", q15, q12, i32, 5); + TESTINSN_un("vshl.i32 q5, q12, #30", q5, q12, i32, (1 << 31) + 1); + TESTINSN_un("vshl.i16 q0, q1, #1", q0, q1, i16, 24); + TESTINSN_un("vshl.i16 q5, q2, #1", q5, q2, i32, (1 << 30)); + TESTINSN_un("vshl.i16 q9, q12, #2", q9, q12, i32, (1 << 31) + 2); + TESTINSN_un("vshl.i16 q11, q2, #12", q11, q2, i16, -1); + TESTINSN_un("vshl.i16 q15, q12, #3", q15, q12, i16, 5); + TESTINSN_un("vshl.i16 q5, q12, #14", q5, q12, i32, (1 << 31) + 1); + TESTINSN_un("vshl.i8 q0, q1, #1", q0, q1, i8, 24); + TESTINSN_un("vshl.i8 q5, q2, #1", q5, q2, i32, (1 << 30)); + TESTINSN_un("vshl.i8 q9, q12, #2", q9, q12, i32, (1 << 31) + 2); + TESTINSN_un("vshl.i8 q11, q2, #7", q11, q2, i8, -1); + TESTINSN_un("vshl.i8 q15, q12, #3", q15, q12, i8, 5); + TESTINSN_un("vshl.i8 q5, q12, #6", q5, q12, i32, (1 << 31) + 1); + + printf("---- VNEG ----\n"); + TESTINSN_un("vneg.s32 q0, q1", q0, q1, i32, 0x73); + TESTINSN_un("vneg.s16 q15, q4", q15, q4, i32, 0x73); + TESTINSN_un("vneg.s8 q8, q7", q8, q7, i32, 0x73); + TESTINSN_un("vneg.s32 q0, q1", q0, q1, i32, 0xfe); + TESTINSN_un("vneg.s16 q15, q4", q15, q4, i32, 0xef); + TESTINSN_un("vneg.s8 q8, q7", q8, q7, i32, 0xde); + TESTINSN_un("vneg.s32 q0, q1", q0, q1, i16, 0xfe0a); + TESTINSN_un("vneg.s16 q15, q4", q15, q4, i16, 0xef0b); + TESTINSN_un("vneg.s8 q8, q7", q8, q7, i16, 0xde0c); + + printf("---- VQNEG ----\n"); + TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 0x73); + TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 1 << 31); + TESTINSN_un_q("vqneg.s16 q0, q1", q0, q1, i32, 1 << 31); + TESTINSN_un_q("vqneg.s8 q0, q1", q0, q1, i32, 1 << 31); + TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i32, 0x73); + TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i32, 0x73); + TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 0xfe); + TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i32, 0xef); + TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i32, 0xde); + TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i16, 0xfe0a); + TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i16, 0xef0b); + TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i16, 0xde0c); + + printf("---- VREV ----\n"); + TESTINSN_un("vrev64.8 q0, q1", q0, q1, i32, 0xaabbccdd); + TESTINSN_un("vrev64.16 q10, q15", q10, q15, i32, 0xaabbccdd); + TESTINSN_un("vrev64.32 q1, q14", q1, q14, i32, 0xaabbccdd); + TESTINSN_un("vrev32.8 q0, q1", q0, q1, i32, 0xaabbccdd); + TESTINSN_un("vrev32.16 q10, q15", q10, q15, i32, 0xaabbccdd); + TESTINSN_un("vrev16.8 q0, q1", q0, q1, i32, 0xaabbccdd); + + printf("---- VSHLL ----\n"); + TESTINSN_un("vshll.s32 q0, d1, #1", q0, d1, i32, 24); + TESTINSN_un("vshll.s32 q5, d2, #1", q5, d2, i32, (1 << 30)); + TESTINSN_un("vshll.s32 q9, d12, #2", q9, d12, i32, (1 << 31) + 2); + TESTINSN_un("vshll.u32 q11, d2, #12", q11, d2, i32, -1); + TESTINSN_un("vshll.u32 q15, d12, #20", q15, d12, i32, 5); + TESTINSN_un("vshll.u32 q5, d22, #30", q5, d22, i32, (1 << 31) + 1); + TESTINSN_un("vshll.s16 q0, d1, #1", q0, d1, i16, 24); + TESTINSN_un("vshll.s16 q5, d2, #1", q5, d2, i32, (1 << 30)); + TESTINSN_un("vshll.s16 q9, d12, #2", q9, d12, i32, (1 << 31) + 2); + TESTINSN_un("vshll.u16 q11, d2, #12", q11, d2, i16, -1); + TESTINSN_un("vshll.u16 q15, d22, #3", q15, d22, i16, 5); + TESTINSN_un("vshll.u16 q5, d12, #14", q5, d12, i32, (1 << 31) + 1); + TESTINSN_un("vshll.s8 q0, d1, #1", q0, d1, i8, 24); + TESTINSN_un("vshll.s8 q5, d2, #1", q5, d2, i32, (1 << 30)); + TESTINSN_un("vshll.s8 q9, d12, #2", q9, d12, i32, (1 << 31) + 2); + TESTINSN_un("vshll.u8 q11, d2, #7", q11, d2, i8, -1); + TESTINSN_un("vshll.u8 q15, d19, #3", q15, d19, i8, 5); + TESTINSN_un("vshll.u8 q5, d12, #6", q5, d12, i32, (1 << 31) + 1); + + printf("---- VSHLL (max shift) ----\n"); + TESTINSN_un("vshll.i32 q0, d1, #32", q0, d1, i32, 24); + TESTINSN_un("vshll.i32 q5, d2, #32", q5, d2, i32, (1 << 30)); + TESTINSN_un("vshll.i32 q11, d2, #32", q11, d2, i32, -1); + TESTINSN_un("vshll.i32 q15, d12, #32", q15, d12, i32, 5); + TESTINSN_un("vshll.i16 q0, d1, #16", q0, d1, i16, 24); + TESTINSN_un("vshll.i16 q5, d2, #16", q5, d2, i32, (1 << 30)); + TESTINSN_un("vshll.i16 q11, d2, #16", q11, d2, i16, -1); + TESTINSN_un("vshll.i16 q15, d22, #16", q15, d22, i16, 5); + TESTINSN_un("vshll.i8 q0, d1, #8", q0, d1, i8, 24); + TESTINSN_un("vshll.i8 q5, d2, #8", q5, d2, i32, (1 << 30)); + TESTINSN_un("vshll.i8 q11, d2, #8", q11, d2, i8, -1); + TESTINSN_un("vshll.i8 q15, d19, #8", q15, d19, i8, 5); + + printf("---- VMULL ----\n"); + TESTINSN_bin("vmull.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmull.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmull.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmull.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmull.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmull.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmull.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmull.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmull.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmull.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmull.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmull.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmull.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmull.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmull.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a); + TESTINSN_bin("vmull.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmull.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin("vmull.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmull.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin("vmull.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a); + TESTINSN_bin("vmull.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmull.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin("vmull.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmull.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin("vmull.p8 q9, d11, d12", q9, d11, i32, 0x1a4b0c, d12, i32, 0xd1e2f0); + TESTINSN_bin("vmull.p8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmull.p8 q4, d15, d26", q4, d15, i32, (1 << 14) - 0xabcd, d26, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmull.p8 q14, d5, d6", q14, d5, i32, (1 << 28) + 0xefe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmull.p8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmull.p8 q10, d27, d31", q10, d27, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmull.p8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmull.p8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmull.p8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + + printf("---- VMLAL ----\n"); + TESTINSN_bin("vmlal.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmlal.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmlal.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlal.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmlal.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmlal.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmlal.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlal.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmlal.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmlal.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmlal.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmlal.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmlal.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlal.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmlal.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a); + TESTINSN_bin("vmlal.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmlal.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin("vmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin("vmlal.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a); + TESTINSN_bin("vmlal.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmlal.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin("vmlal.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlal.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + + printf("---- VMLSL ----\n"); + TESTINSN_bin("vmlsl.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmlsl.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmlsl.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlsl.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmlsl.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmlsl.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmlsl.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlsl.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmlsl.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmlsl.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmlsl.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1); + TESTINSN_bin("vmlsl.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2); + TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d); + TESTINSN_bin("vmlsl.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlsl.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30); + TESTINSN_bin("vmlsl.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a); + TESTINSN_bin("vmlsl.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmlsl.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin("vmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin("vmlsl.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a); + TESTINSN_bin("vmlsl.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmlsl.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin("vmlsl.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin("vmlsl.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31); + + printf("---- VQRDMULH ----\n"); + TESTINSN_bin_q("vqrdmulh.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120); + TESTINSN_bin_q("vqrdmulh.s32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120); + TESTINSN_bin_q("vqrdmulh.s16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120); + TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12); + TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqrdmulh.s32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120); + TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, (1 << 31) + 1); + TESTINSN_bin_q("vqrdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 30, q15, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 30); + + printf("---- VQRDMULH (by scalar) ----\n"); + TESTINSN_bin_q("vqrdmulh.s32 q0, q1, d6[0]", q0, q1, i32, 24, d6, i32, 120); + TESTINSN_bin_q("vqrdmulh.s32 q6, q7, d1[1]", q6, q7, i32, 140, d1, i32, -120); + TESTINSN_bin_q("vqrdmulh.s16 q9, q11, d7[0]", q9, q11, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[1]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[1]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[2]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqrdmulh.s32 q10, q11, d15[0]", q10, q11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqrdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s16 q10, q14, d7[3]", q10, q14, i32, 1 << 31, q15, i32, (1 << 31) + 1); + TESTINSN_bin_q("vqrdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 30, d15, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s16 q10, q14, d7[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 30); + + printf("---- VADD (fp) ----\n"); + TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vadd.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vadd.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vadd.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vadd.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vadd.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vadd.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VSUB (fp) ----\n"); + TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(24.89), q5, i32, f2u(1346)); + TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vsub.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vsub.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vsub.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vsub.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vsub.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vsub.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VABD (fp) ----\n"); + TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vabd.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vabd.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vabd.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vabd.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vabd.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vabd.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VMUL (fp) ----\n"); + TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vmul.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vmul.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vmul.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vmul.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vmul.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vmul.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VMLA (fp) ----\n"); + TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin_f("vmla.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin_f("vmla.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin_f("vmla.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin_f("vmla.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin_f("vmla.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin_f("vmla.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VMLA (fp by scalar) ----\n"); + TESTINSN_bin_f("vmla.f32 q0, q1, d4[0]", q0, q1, i32, f2u(24), d4, i32, f2u(120)); + TESTINSN_bin_f("vmla.f32 q15, q8, d7[1]", q15, q8, i32, f2u(140), d7, i32, f2u(-120)); + TESTINSN_bin_f("vmla.f32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin_f("vmla.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin_f("vmla.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + TESTINSN_bin_f("vmla.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e22), d1, i32, f2u(1e-19)); + TESTINSN_bin_f("vmla.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e12), d1, i32, f2u(1e11)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VMLS (fp) ----\n"); + TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin_f("vmls.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin_f("vmls.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin_f("vmls.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin_f("vmls.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin_f("vmls.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin_f("vmls.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VMLS (fp by scalar) ----\n"); + TESTINSN_bin_f("vmls.f32 q0, q1, d4[0]", q0, q1, i32, f2u(24), d4, i32, f2u(120)); + TESTINSN_bin_f("vmls.f32 q15, q8, d7[1]", q15, q8, i32, f2u(140), d7, i32, f2u(-120)); + TESTINSN_bin_f("vmls.f32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin_f("vmls.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin_f("vmls.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + TESTINSN_bin_f("vmls.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e22), d1, i32, f2u(1e-19)); + TESTINSN_bin_f("vmls.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e12), d1, i32, f2u(1e11)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VCVT (integer <-> fp) ----\n"); + TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vcvt.u32.f32 q10, q11", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vcvt.u32.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vcvt.u32.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vcvt.s32.f32 q10, q11", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vcvt.s32.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vcvt.s32.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, 7); + TESTINSN_un("vcvt.f32.u32 q10, q11", q10, q11, i32, 1 << 31); + TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vcvt.f32.u32 q0, q14", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, 7); + TESTINSN_un("vcvt.f32.s32 q10, q11", q10, q11, i32, 1 << 31); + TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vcvt.f32.s32 q0, q14", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(-INFINITY)); + TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VCVT (fixed <-> fp) ----\n"); + TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vcvt.u32.f32 q10, q11, #1", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vcvt.u32.f32 q15, q4, #32", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vcvt.u32.f32 q15, q4, #7", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vcvt.u32.f32 q15, q4, #4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vcvt.u32.f32 q12, q8, #3", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vcvt.u32.f32 q12, q8, #3", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vcvt.s32.f32 q0, q1, #5", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vcvt.s32.f32 q10, q11, #1", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vcvt.s32.f32 q15, q4, #8", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vcvt.s32.f32 q15, q4, #2", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vcvt.s32.f32 q15, q4, #1", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vcvt.s32.f32 q12, q8, #2", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vcvt.s32.f32 q12, q8, #2", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vcvt.f32.u32 q0, q1, #5", q0, q1, i32, 7); + TESTINSN_un("vcvt.f32.u32 q10, q11, #9", q10, q11, i32, 1 << 31); + TESTINSN_un("vcvt.f32.u32 q0, q1, #4", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vcvt.f32.u32 q0, q1, #6", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vcvt.f32.u32 q0, q14, #5", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vcvt.f32.s32 q0, q1, #12", q0, q1, i32, 7); + TESTINSN_un("vcvt.f32.s32 q10, q11, #8", q10, q11, i32, 1 << 31); + TESTINSN_un("vcvt.f32.s32 q0, q1, #2", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vcvt.f32.s32 q0, q1, #1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vcvt.f32.s32 q0, q14, #6", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(-INFINITY)); + TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VMAX (fp) ----\n"); + TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vmax.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vmax.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vmax.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vmax.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vmax.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vmax.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VMIN (fp) ----\n"); + TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vmin.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vmin.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vmin.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vmin.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vmin.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vmin.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VRECPE ----\n"); + TESTINSN_un("vrecpe.u32 q0, q1", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vrecpe.u32 q10, q11", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vrecpe.u32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vrecpe.u32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vrecpe.u32 q0, q1", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vrecpe.u32 q10, q11", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vrecpe.f32 q15, q4", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vrecpe.f32 q15, q4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vrecpe.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vrecpe.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, 7); + TESTINSN_un("vrecpe.f32 q10, q11", q10, q11, i32, 1 << 31); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vrecpe.f32 q0, q14", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, 7); + TESTINSN_un("vrecpe.f32 q10, q11", q10, q11, i32, 1 << 31); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vrecpe.f32 q0, q14", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(-INFINITY)); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VRECPS ----\n"); + TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vrecps.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vrecps.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vrecps.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vrecps.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vrecps.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vrecps.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VABS (fp) ----\n"); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, 7); + TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, 1 << 31); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vabs.f32 q0, q14", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, 7); + TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, 1 << 31); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vabs.f32 q0, q14", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(-INFINITY)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VCGT (fp) ----\n"); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5)); + TESTINSN_bin("vcgt.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52)); + TESTINSN_bin("vcgt.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45)); + TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vcgt.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vcgt.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vcgt.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vcgt.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vcgt.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vcgt.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VCGE (fp) ----\n"); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5)); + TESTINSN_bin("vcge.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52)); + TESTINSN_bin("vcge.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45)); + TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vcge.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vcge.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vcge.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vcge.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vcge.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vcge.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VACGT (fp) ----\n"); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5)); + TESTINSN_bin("vacgt.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52)); + TESTINSN_bin("vacgt.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45)); + TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vacgt.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vacgt.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vacgt.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vacgt.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vacgt.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vacgt.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VACGE (fp) ----\n"); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5)); + TESTINSN_bin("vacge.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52)); + TESTINSN_bin("vacge.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45)); + TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vacge.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vacge.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vacge.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vacge.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vacge.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vacge.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VCEQ (fp) ----\n"); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5)); + TESTINSN_bin("vceq.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52)); + TESTINSN_bin("vceq.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45)); + TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vceq.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vceq.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vceq.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vceq.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vceq.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vceq.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VCEQ (fp) #0 ----\n"); + TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, 0x01000000); + TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, 0x1); + TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, 1 << 31); + TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, f2u(23.04)); + TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04)); + TESTINSN_un("vceq.f32 q10, q15, #0", q10, q15, i32, 0x0); + TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VCGT (fp) #0 ----\n"); + TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, 0x01000000); + TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, 0x1); + TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, 1 << 31); + TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, f2u(23.04)); + TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04)); + TESTINSN_un("vcgt.f32 q10, q15, #0", q10, q15, i32, 0x0); + TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VCLT (fp) #0 ----\n"); + TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, 0x01000000); + TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, 0x1); + TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, 1 << 31); + TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, f2u(23.04)); + TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04)); + TESTINSN_un("vclt.f32 q10, q15, #0", q10, q15, i32, 0x0); + TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VCGE (fp) #0 ----\n"); + TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, 0x01000000); + TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, 0x1); + TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, 1 << 31); + TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, f2u(23.04)); + TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04)); + TESTINSN_un("vcge.f32 q10, q15, #0", q10, q15, i32, 0x0); + TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VCLE (fp) #0 ----\n"); + TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, 0x01000000); + TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, 0x1); + TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, 1 << 31); + TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, f2u(23.04)); + TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04)); + TESTINSN_un("vcle.f32 q10, q15, #0", q10, q15, i32, 0x0); + TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VNEG (fp) ----\n"); + TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, 0x01000000); + TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, 0x1); + TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, 1 << 31); + TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, f2u(23.04)); + TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, f2u(-23.04)); + TESTINSN_un("vneg.f32 q10, q15", q10, q15, i32, 0x0); + TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(-INFINITY)); + + printf("---- VRSQRTS ----\n"); + TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687)); + TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346)); + TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476)); + TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065)); + TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76)); + TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346)); + TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089)); + TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065)); + TESTINSN_bin("vrsqrts.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009)); + TESTINSN_bin("vrsqrts.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107)); + TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6)); + TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109)); + TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752)); + TESTINSN_bin("vrsqrts.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47)); + TESTINSN_bin("vrsqrts.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676)); + TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876)); + TESTINSN_bin("vrsqrts.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245)); + TESTINSN_bin("vrsqrts.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY)); + TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY)); + + printf("---- VRSQRTE (fp) ----\n"); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(3.2)); + TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, f2u(3e22)); + TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(3e9)); + TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-0.5)); + TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-7.1)); + TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, 7); + TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, 1 << 31); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vrsqrte.f32 q0, q14", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, 7); + TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, 1 << 31); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) + 1); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) - 1); + TESTINSN_un("vrsqrte.f32 q0, q14", q0, q14, i32, 0x30a0bcef); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(NAN)); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(0.0)); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(INFINITY)); + TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(-INFINITY)); + + return 0; +} diff --git a/none/tests/arm/neon128.stderr.exp b/none/tests/arm/neon128.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/arm/neon128.stdout.exp b/none/tests/arm/neon128.stdout.exp new file mode 100644 index 0000000..ff75a01 --- /dev/null +++ b/none/tests/arm/neon128.stdout.exp @@ -0,0 +1,4245 @@ +----- VMOV (immediate) ----- +vmov.i32 q0, #0x7 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 +vmov.i32 q0, #0x7 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 +vmov.i16 q1, #0x7 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007 +vmov.i16 q1, #0x7 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007 +vmov.i8 q2, #0x7 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 +vmov.i8 q2, #0x7 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 +vmov.i32 q5, #0x700 :: Qd 0x00000700 0x00000700 0x00000700 0x00000700 +vmov.i32 q5, #0x700 :: Qd 0x00000700 0x00000700 0x00000700 0x00000700 +vmov.i16 q7, #0x700 :: Qd 0x07000700 0x07000700 0x07000700 0x07000700 +vmov.i16 q7, #0x700 :: Qd 0x07000700 0x07000700 0x07000700 0x07000700 +vmov.i32 q10, #0x70000 :: Qd 0x00070000 0x00070000 0x00070000 0x00070000 +vmov.i32 q10, #0x70000 :: Qd 0x00070000 0x00070000 0x00070000 0x00070000 +vmov.i32 q12, #0x7000000 :: Qd 0x07000000 0x07000000 0x07000000 0x07000000 +vmov.i32 q12, #0x7000000 :: Qd 0x07000000 0x07000000 0x07000000 0x07000000 +vmov.i32 q13, #0x7FF :: Qd 0x000007ff 0x000007ff 0x000007ff 0x000007ff +vmov.i32 q13, #0x7FF :: Qd 0x000007ff 0x000007ff 0x000007ff 0x000007ff +vmov.i32 q14, #0x7FFFF :: Qd 0x0007ffff 0x0007ffff 0x0007ffff 0x0007ffff +vmov.i32 q14, #0x7FFFF :: Qd 0x0007ffff 0x0007ffff 0x0007ffff 0x0007ffff +vmov.i64 q15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00 0xff0000ff 0x00ffff00 +vmov.i64 q15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00 0xff0000ff 0x00ffff00 +----- VMVN (immediate) ----- +vmvn.i32 q0, #0x7 :: Qd 0xfffffff8 0xfffffff8 0xfffffff8 0xfffffff8 +vmvn.i32 q0, #0x7 :: Qd 0xfffffff8 0xfffffff8 0xfffffff8 0xfffffff8 +vmvn.i16 q1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8 0xfff8fff8 0xfff8fff8 +vmvn.i16 q1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8 0xfff8fff8 0xfff8fff8 +vmvn.i8 q2, #0x7 :: Qd 0xf8f8f8f8 0xf8f8f8f8 0xf8f8f8f8 0xf8f8f8f8 +vmvn.i8 q2, #0x7 :: Qd 0xf8f8f8f8 0xf8f8f8f8 0xf8f8f8f8 0xf8f8f8f8 +vmvn.i32 q5, #0x700 :: Qd 0xfffff8ff 0xfffff8ff 0xfffff8ff 0xfffff8ff +vmvn.i32 q5, #0x700 :: Qd 0xfffff8ff 0xfffff8ff 0xfffff8ff 0xfffff8ff +vmvn.i16 q7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff 0xf8fff8ff 0xf8fff8ff +vmvn.i16 q7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff 0xf8fff8ff 0xf8fff8ff +vmvn.i32 q10, #0x70000 :: Qd 0xfff8ffff 0xfff8ffff 0xfff8ffff 0xfff8ffff +vmvn.i32 q10, #0x70000 :: Qd 0xfff8ffff 0xfff8ffff 0xfff8ffff 0xfff8ffff +vmvn.i32 q13, #0x7000000 :: Qd 0xf8ffffff 0xf8ffffff 0xf8ffffff 0xf8ffffff +vmvn.i32 q13, #0x7000000 :: Qd 0xf8ffffff 0xf8ffffff 0xf8ffffff 0xf8ffffff +vmvn.i32 q11, #0x7FF :: Qd 0xfffff800 0xfffff800 0xfffff800 0xfffff800 +vmvn.i32 q11, #0x7FF :: Qd 0xfffff800 0xfffff800 0xfffff800 0xfffff800 +vmvn.i32 q14, #0x7FFFF :: Qd 0xfff80000 0xfff80000 0xfff80000 0xfff80000 +vmvn.i32 q14, #0x7FFFF :: Qd 0xfff80000 0xfff80000 0xfff80000 0xfff80000 +vmvn.i64 q15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff 0x00ffff00 0xff0000ff +vmvn.i64 q15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff 0x00ffff00 0xff0000ff +----- VORR (immediate) ----- +vorr.i32 q0, #0x7 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 +vorr.i32 q0, #0x7 :: Qd 0x151d191f 0x141c1f1f 0x131b1a1f 0x121f1e1f +vorr.i16 q2, #0x7 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557 +vorr.i16 q2, #0x7 :: Qd 0x151f191f 0x141f1f1f 0x131f1a1f 0x121f1e1f +vorr.i32 q8, #0x700 :: Qd 0x55555755 0x55555755 0x55555755 0x55555755 +vorr.i32 q8, #0x700 :: Qd 0x151d1f1d 0x141c1f1c 0x131b1f1b 0x121f1f1f +vorr.i16 q6, #0x700 :: Qd 0x57555755 0x57555755 0x57555755 0x57555755 +vorr.i16 q6, #0x700 :: Qd 0x171d1f1d 0x171c1f1c 0x171b1f1b 0x171f1f1f +vorr.i32 q14, #0x70000 :: Qd 0x55575555 0x55575555 0x55575555 0x55575555 +vorr.i32 q14, #0x70000 :: Qd 0x151f191d 0x141f1f1c 0x131f1a1b 0x121f1e1f +vorr.i32 q15, #0x7000000 :: Qd 0x57555555 0x57555555 0x57555555 0x57555555 +vorr.i32 q15, #0x7000000 :: Qd 0x171d191d 0x171c1f1c 0x171b1a1b 0x171f1e1f +----- VBIC (immediate) ----- +vbic.i32 q0, #0x7 :: Qd 0x55555550 0x55555550 0x55555550 0x55555550 +vbic.i32 q0, #0x7 :: Qd 0x151d1918 0x141c1f18 0x131b1a18 0x121f1e18 +vbic.i16 q3, #0x7 :: Qd 0x55505550 0x55505550 0x55505550 0x55505550 +vbic.i16 q3, #0x7 :: Qd 0x15181918 0x14181f18 0x13181a18 0x12181e18 +vbic.i32 q5, #0x700 :: Qd 0x55555055 0x55555055 0x55555055 0x55555055 +vbic.i32 q5, #0x700 :: Qd 0x151d181d 0x141c181c 0x131b181b 0x121f181f +vbic.i16 q8, #0x700 :: Qd 0x50555055 0x50555055 0x50555055 0x50555055 +vbic.i16 q8, #0x700 :: Qd 0x101d181d 0x101c181c 0x101b181b 0x101f181f +vbic.i32 q10, #0x70000 :: Qd 0x55505555 0x55505555 0x55505555 0x55505555 +vbic.i32 q10, #0x70000 :: Qd 0x1518191d 0x14181f1c 0x13181a1b 0x12181e1f +vbic.i32 q15, #0x7000000 :: Qd 0x50555555 0x50555555 0x50555555 0x50555555 +vbic.i32 q15, #0x7000000 :: Qd 0x101d191d 0x101c1f1c 0x101b1a1b 0x101f1e1f +---- VMVN (register) ---- +vmvn q0, q1 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7 Qm (i32)0x00000018 +vmvn q0, q1 :: Qd 0xd9d2d2d5 0xdad5d1d4 0xdbd3d4d4 0xdcd0d1d0 Qm (i32)0x00000018 +vmvn q10, q15 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7 Qm (i32)0x00000018 +vmvn q10, q15 :: Qd 0xd9d2d2d5 0xdad5d1d4 0xdbd3d4d4 0xdcd0d1d0 Qm (i32)0x00000018 +vmvn q0, q14 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7 Qm (i32)0x00000018 +vmvn q0, q14 :: Qd 0xd9d2d2d5 0xdad5d1d4 0xdbd3d4d4 0xdcd0d1d0 Qm (i32)0x00000018 +---- VMOV (register) ---- +vmov q0, q1 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018 +vmov q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000018 +vmov q10, q15 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018 +vmov q10, q15 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000018 +vmov q0, q14 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018 +vmov q0, q14 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000018 +---- VDUP (ARM core register) (tested indirectly) ---- +vmov q0, q1 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 Qm (i8)0x00000007 +vmov q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i8)0x00000007 +vmov q10, q11 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007 Qm (i16)0x00000007 +vmov q10, q11 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i16)0x00000007 +vmov q0, q15 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x00000007 +vmov q0, q15 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000007 +---- VADD ---- +vadd.i32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 +vadd.i64 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i8 q0, q1, q2 :: Qd 0x00000004 0x00000004 0x00000004 0x00000004 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i8 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i16 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i32 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i64 q0, q1, q2 :: Qd 0x00000004 0x00000003 0x00000004 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 +vadd.i64 q13, q14, q15 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 +---- VSUB ---- +vsub.i32 q0, q1, q2 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vsub.i64 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i64 q0, q1, q2 :: Qd 0xfffffffe 0xffffffff 0xfffffffe 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i32 q10, q11, q12 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vsub.i64 q13, q14, q15 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +---- VAND ---- +vand q0, q1, q2 :: Qd 0x00240024 0x00240024 0x00240024 0x00240024 Qm (i8)0x00000024 Qn (i16)0x00000077 +vand q4, q6, q5 :: Qd 0x00570057 0x00570057 0x00570057 0x00570057 Qm (i8)0x000000ff Qn (i16)0x00000057 +vand q10, q11, q12 :: Qd 0xecececec 0xecececec 0xecececec 0xecececec Qm (i8)0x000000fe Qn (i8)0x000000ed +vand q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +---- VBIC ---- +vbic q0, q1, q2 :: Qd 0x24002400 0x24002400 0x24002400 0x24002400 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbic q4, q6, q5 :: Qd 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbic q10, q11, q12 :: Qd 0x12121212 0x12121212 0x12121212 0x12121212 Qm (i8)0x000000fe Qn (i8)0x000000ed +vbic q15, q15, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff +---- VORR ---- +vorr q0, q1, q2 :: Qd 0x24772477 0x24772477 0x24772477 0x24772477 Qm (i8)0x00000024 Qn (i16)0x00000073 +vorr q7, q3, q0 :: Qd 0x24ff24ff 0x24ff24ff 0x24ff24ff 0x24ff24ff Qm (i8)0x00000024 Qn (i16)0x000000ff +vorr q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vorr q2, q3, q15 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VORN ---- +vorn q0, q1, q2 :: Qd 0xffacffac 0xffacffac 0xffacffac 0xffacffac Qm (i8)0x00000024 Qn (i16)0x00000073 +vorn q7, q3, q0 :: Qd 0xff24ff24 0xff24ff24 0xff24ff24 0xff24ff24 Qm (i8)0x00000024 Qn (i16)0x000000ff +vorn q4, q4, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i16)0x000000ff Qn (i16)0x000000ff +vorn q2, q3, q15 :: Qd 0xffffffe4 0xffffffe4 0xffffffe4 0xffffffe4 Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VEOR ---- +veor q0, q1, q2 :: Qd 0x24532453 0x24532453 0x24532453 0x24532453 Qm (i8)0x00000024 Qn (i16)0x00000077 +veor q4, q6, q5 :: Qd 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 Qm (i8)0x000000ff Qn (i16)0x00000057 +veor q10, q11, q12 :: Qd 0x13131313 0x13131313 0x13131313 0x13131313 Qm (i8)0x000000fe Qn (i8)0x000000ed +veor q15, q15, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff +veor q0, q1, q2 :: Qd 0x24572457 0x24572457 0x24572457 0x24572457 Qm (i8)0x00000024 Qn (i16)0x00000073 +veor q7, q3, q0 :: Qd 0x24db24db 0x24db24db 0x24db24db 0x24db24db Qm (i8)0x00000024 Qn (i16)0x000000ff +veor q4, q4, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i16)0x000000ff Qn (i16)0x000000ff +veor q2, q3, q15 :: Qd 0x0000003b 0x0000003b 0x0000003b 0x0000003b Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VBSL ---- +vbsl q0, q1, q2 :: Qd 0x04260426 0x04260426 0x04260426 0x04260426 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbsl q4, q6, q5 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbsl q10, q11, q12 :: Qd 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc Qm (i8)0x000000fe Qn (i8)0x000000ed +vbsl q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbsl q0, q1, q2 :: Qd 0x04260426 0x04260426 0x04260426 0x04260426 Qm (i8)0x00000024 Qn (i16)0x00000073 +vbsl q7, q3, q0 :: Qd 0x04ae04ae 0x04ae04ae 0x04ae04ae 0x04ae04ae Qm (i8)0x00000024 Qn (i16)0x000000ff +vbsl q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbsl q2, q3, q15 :: Qd 0x0000000e 0x0000000e 0x0000000e 0x0000000e Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VBIT ---- +vbit q0, q1, q2 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbit q4, q6, q5 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbit q10, q11, q12 :: Qd 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc Qm (i8)0x000000fe Qn (i8)0x000000ed +vbit q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbit q0, q1, q2 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x00000073 +vbit q7, q3, q0 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x000000ff +vbit q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbit q2, q3, q15 :: Qd 0x55555544 0x55555544 0x55555544 0x55555544 Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VBIF ---- +vbif q0, q1, q2 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbif q4, q6, q5 :: Qd 0xfffdfffd 0xfffdfffd 0xfffdfffd 0xfffdfffd Qm (i8)0x000000ff Qn (i16)0x00000057 +vbif q10, q11, q12 :: Qd 0x57575757 0x57575757 0x57575757 0x57575757 Qm (i8)0x000000fe Qn (i8)0x000000ed +vbif q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbif q0, q1, q2 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x00000073 +vbif q7, q3, q0 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x000000ff +vbif q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbif q2, q3, q15 :: Qd 0x00000035 0x00000035 0x00000035 0x00000035 Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VEXT ---- +vext.8 q0, q1, q2, #0 :: Qd 0x77777777 0x77777777 0x77777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 q0, q1, q2, #1 :: Qd 0xff777777 0x77777777 0x77777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 q0, q1, q2, #9 :: Qd 0xffffffff 0xffffffff 0xff777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 q0, q1, q2, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffff77 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 q10, q11, q12, #4 :: Qd 0xffffffff 0x77777777 0x77777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 q0, q5, q15, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +---- VHADD ---- +vhadd.s32 q0, q1, q2 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.s32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s8 q0, q1, q2 :: Qd 0x03030303 0x03030303 0x03030303 0x03030303 Qm (i8)0x0000008d Qn (i8)0x00000079 +vhadd.s8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.u32 q0, q1, q2 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.u32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u8 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u8 q0, q1, q2 :: Qd 0x83838383 0x83838383 0x83838383 0x83838383 Qm (i8)0x0000008d Qn (i8)0x00000079 +vhadd.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VHSUB ---- +vhsub.s32 q0, q1, q2 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.s32 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s16 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s8 q0, q1, q2 :: Qd 0x0000008a 0x0000008a 0x0000008a 0x0000008a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s32 q10, q11, q12 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.u32 q0, q1, q2 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.u32 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u16 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u8 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u32 q10, q11, q12 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VQADD ---- +vqadd.s32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 q0, q1, q2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 q0, q1, q2 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 q0, q1, q2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 q0, q1, q2 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s16 q0, q1, q2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s16 q0, q1, q2 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s8 q0, q1, q2 :: Qd 0x00000004 0x00000004 0x00000004 0x00000004 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s8 q0, q1, q2 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqadd.s8 q0, q1, q2 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqadd.s8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.s8 q0, q1, q2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s8 q0, q1, q2 :: Qd 0x951d191f 0x941c1f1e 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.s16 q0, q1, q2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s16 q0, q1, q2 :: Qd 0x951d191f 0x941c1f1e 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s32 q0, q1, q2 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.s32 q0, q1, q2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s32 q0, q1, q2 :: Qd 0x951d191f 0x941c1f1e 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 q10, q11, q12 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 q10, q11, q12 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 q0, q1, q2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 q0, q1, q2 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 q0, q1, q2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 q0, q1, q2 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u16 q0, q1, q2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u16 q0, q1, q2 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqadd.u8 q0, q1, q2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u8 q0, q1, q2 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u8 q0, q1, q2 :: Qd 0xff000003 0xff000003 0xff000003 0xff000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.u8 q0, q1, q2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u8 q0, q1, q2 :: Qd 0x951d191f 0x941c1f1e 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u16 q0, q1, q2 :: Qd 0xffff0003 0xffff0003 0xffff0003 0xffff0003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.u16 q0, q1, q2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u16 q0, q1, q2 :: Qd 0x951d191f 0x941c1f1e 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.u32 q0, q1, q2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u32 q0, q1, q2 :: Qd 0x951d191f 0x941c1f1e 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 q10, q11, q12 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 q10, q11, q12 :: Qd 0x151d1995 0x141c1f94 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +---- VQSUB ---- +vqsub.s32 q0, q1, q2 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s16 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s16 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s8 q0, q1, q2 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqsub.s8 q0, q1, q2 :: Qd 0x131b1aa3 0x121f1ea7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s8 q0, q1, q2 :: Qd 0x151d19a5 0x141c1fa4 0x131b1aa3 0x121f1ea7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqsub.s8 q0, q1, q2 :: Qd 0x7f1b1a19 0x7f1f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s8 q0, q1, q2 :: Qd 0x7f1d191b 0x7f1c1f1a 0x7f1b1a19 0x7f1f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqsub.s16 q0, q1, q2 :: Qd 0x7fff1a19 0x7fff1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s16 q0, q1, q2 :: Qd 0x7fff191b 0x7fff1f1a 0x7fff1a19 0x7fff1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqsub.s32 q0, q1, q2 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s32 q0, q1, q2 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s32 q10, q11, q12 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 q10, q11, q12 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 q10, q11, q12 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqsub.u32 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u16 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u16 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u8 q0, q1, q2 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqsub.u8 q0, q1, q2 :: Qd 0x151d1900 0x141c1f00 0x131b1a00 0x121f1e00 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqsub.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u8 q0, q1, q2 :: Qd 0x001b1a19 0x001f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u8 q0, q1, q2 :: Qd 0x001d191b 0x001c1f1a 0x001b1a19 0x001f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u16 q0, q1, q2 :: Qd 0x00001a19 0x00001e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u16 q0, q1, q2 :: Qd 0x0000191b 0x00001f1a 0x00001a19 0x00001e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqsub.u32 q10, q11, q12 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 q10, q11, q12 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +---- VRHADD ---- +vrhadd.s32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000078 +vrhadd.s32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000079 +vrhadd.s32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vrhadd.u32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000078 +vrhadd.u32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u8 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VCGT ---- +vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078 +vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000079 +vcgt.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s8 q5, q7, q5 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s8 q5, q7, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s8 q5, q7, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078 +vcgt.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VCGE ---- +vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078 +vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000079 +vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s8 q5, q7, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s8 q5, q7, q5 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s8 q5, q7, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vcge.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078 +vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VSHL (register) ---- +vshl.s8 q0, q1, q2 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i32)0x00000018 Qn (i32)0x00000001 +vshl.s8 q8, q1, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000008 +vshl.s8 q10, q11, q7 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x00000018 Qn (i32)0x00000004 +vshl.s16 q3, q8, q11 :: Qd 0x00000038 0x00000038 0x00000038 0x00000038 Qm (i32)0x0000000e Qn (i32)0x00000002 +vshl.s16 q5, q12, q14 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000001 +vshl.s16 q15, q2, q1 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x0000000b +vshl.s32 q9, q12, q15 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 Qn (i32)0x00000002 +vshl.s32 q11, q2, q0 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000 Qm (i32)0xffffffff Qn (i32)0x0000000c +vshl.s32 q5, q2, q3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x00000015 +vshl.s64 q15, q12, q4 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000 Qm (i32)0x00000005 Qn (i32)0x00000014 +vshl.s64 q8, q2, q4 :: Qd 0x000000f0 0x000000f0 0x000000f0 0x000000f0 Qm (i32)0x0000000f Qn (i32)0x00000004 +vshl.s64 q5, q12, q4 :: Qd 0x60000000 0x40000000 0x60000000 0x40000000 Qm (i32)0x80000001 Qn (i32)0x0000001e +vshl.u8 q0, q1, q2 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i32)0x00000018 Qn (i32)0x00000001 +vshl.u8 q8, q1, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000008 +vshl.u8 q10, q11, q7 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x00000018 Qn (i32)0x00000004 +vshl.u16 q3, q8, q11 :: Qd 0x00000038 0x00000038 0x00000038 0x00000038 Qm (i32)0x0000000e Qn (i32)0x00000002 +vshl.u16 q5, q12, q14 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000001 +vshl.u16 q15, q2, q1 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x0000000b +vshl.u32 q9, q12, q15 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 Qn (i32)0x00000002 +vshl.u32 q11, q2, q0 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000 Qm (i32)0xffffffff Qn (i32)0x0000000c +vshl.u32 q5, q2, q3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x00000015 +vshl.u64 q15, q12, q4 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000 Qm (i32)0x00000005 Qn (i32)0x00000014 +vshl.u64 q8, q2, q4 :: Qd 0x000000f0 0x000000f0 0x000000f0 0x000000f0 Qm (i32)0x0000000f Qn (i32)0x00000004 +vshl.u64 q5, q12, q4 :: Qd 0x60000000 0x40000000 0x60000000 0x40000000 Qm (i32)0x80000001 Qn (i32)0x0000001e +---- VQSHL (register) ---- +vqshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 q0, q1, q2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 q0, q1, q2 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 q3, q4, q5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 q3, q4, q5 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s64 q3, q4, q5 :: Qd 0x02636343 0x6243e3c3 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s64 q3, q4, q5 :: Qd 0x02a3a323 0xa28383e3 0x02636343 0x6243e3c3 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000 +vqshl.s64 q0, q1, q2 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqshl.s64 q0, q1, q2 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffbff 0xffffffff 0xfffffbff Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.s64 q13, q14, q15 :: Qd 0x00000004 0xc6c686c4 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.s64 q13, q14, q15 :: Qd 0x00000005 0x47464745 0x00000004 0xc6c686c4 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.s32 q2, q8, q4 :: Qd 0x0131b1a1 0x0121f1e1 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.s32 q2, q8, q4 :: Qd 0x0151d191 0x0141c1f1 0x0131b1a1 0x0121f1e1 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.s32 q12, q11, q13 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.s32 q12, q11, q13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.s32 q12, q11, q13 :: Qd 0x000a8e8c 0x000a0e0f 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.s32 q0, q1, q2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.s32 q0, q1, q2 :: Qd 0x002a3a32 0x0028383e 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s32 q9, q10, q11 :: Qd 0x098d8d0d 0x090f8f0f Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s32 q9, q10, q11 :: Qd 0x0a8e8c8e 0x0a0e0f8e 0x098d8d0d 0x090f8f0f Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqshl.s32 q13, q3, q5 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 08000000 +vqshl.s32 q13, q3, q5 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 08000000 +vqshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 q11, q10, q2 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 q11, q10, q2 :: Qd 0x0a8e0000 0x0a0e0000 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s16 q3, q14, q7 :: Qd 0x098d0343 0x090f03c3 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s16 q3, q14, q7 :: Qd 0x0a8e0323 0x0a0e03e3 0x098d0343 0x090f03c3 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s16 q0, q11, q2 :: Qd 0x098d0d0d 0x090f0f0f Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s16 q0, q11, q2 :: Qd 0x0a8e0c8e 0x0a0e0f8e 0x098d0d0d 0x090f0f0f Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 q1, q2, q3 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 q1, q2, q3 :: Qd 0x0a8e0000 0x0a0e0000 0x098d0000 0x090f0000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.s16 q3, q4, q5 :: Qd 0x098d0000 0x090f0000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.s16 q3, q4, q5 :: Qd 0x0a8e0000 0x0a0e0000 0x098d0000 0x090f0000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.s16 q0, q15, q2 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s16 q0, q15, q2 :: Qd 0x131b7fff 0x121f7fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s16 q0, q15, q2 :: Qd 0x151d7fff 0x141c7fff 0x131b7fff 0x121f7fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s8 q2, q7, q11 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80 Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.s8 q2, q7, q11 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.s8 q2, q7, q11 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.s8 q13, q1, q2 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80 Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s8 q13, q1, q2 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s8 q13, q1, q2 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqshl.s8 q3, q7, q5 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 08000000 +vqshl.s8 q3, q7, q5 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 08000000 +vqshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000 +vqshl.s8 q10, q11, q12 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqshl.s8 q10, q11, q12 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.s8 q6, q7, q8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.s8 q6, q7, q8 :: Qd 0x151d1974 0x141c1f70 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.s8 q10, q11, q12 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqshl.s8 q10, q11, q12 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqshl.s8 q10, q11, q12 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.u64 q0, q1, q2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.u64 q0, q1, q2 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.u64 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 08000000 +vqshl.u64 q3, q4, q5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.u64 q3, q4, q5 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u64 q3, q4, q5 :: Qd 0x02636343 0x6243e3c3 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u64 q3, q4, q5 :: Qd 0x02a3a323 0xa28383e3 0x02636343 0x6243e3c3 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000 +vqshl.u64 q0, q1, q2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqshl.u64 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffbff 0x0000003f 0xfffffbff Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.u64 q13, q14, q15 :: Qd 0x00000004 0xc6c686c4 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.u64 q13, q14, q15 :: Qd 0x00000005 0x47464745 0x00000004 0xc6c686c4 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.u32 q2, q8, q4 :: Qd 0x0131b1a1 0x0121f1e1 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.u32 q2, q8, q4 :: Qd 0x0151d191 0x0141c1f1 0x0131b1a1 0x0121f1e1 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.u32 q12, q11, q13 :: Qd 0x007fffff 0x007fffff 0x007fffff 0x007fffff Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.u32 q12, q11, q13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.u32 q12, q11, q13 :: Qd 0x000a8e8c 0x000a0e0f 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.u32 q0, q1, q2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.u32 q0, q1, q2 :: Qd 0x002a3a32 0x0028383e 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u32 q9, q10, q11 :: Qd 0x098d8d0d 0x090f8f0f Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u32 q9, q10, q11 :: Qd 0x0a8e8c8e 0x0a0e0f8e 0x098d8d0d 0x090f8f0f Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u32 q13, q3, q5 :: Qd 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u32 q13, q3, q5 :: Qd 0xa8e8c8e8 0xa0e0f8e0 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 q11, q10, q2 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 q11, q10, q2 :: Qd 0x0a8e0000 0x0a0e0000 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u16 q3, q14, q7 :: Qd 0x098d0343 0x090f03c3 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u16 q3, q14, q7 :: Qd 0x0a8e0323 0x0a0e03e3 0x098d0343 0x090f03c3 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u16 q0, q11, q2 :: Qd 0x098d0d0d 0x090f0f0f Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u16 q0, q11, q2 :: Qd 0x0a8e0c8e 0x0a0e0f8e 0x098d0d0d 0x090f0f0f Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 q1, q2, q3 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 q1, q2, q3 :: Qd 0x0a8e0000 0x0a0e0000 0x098d0000 0x090f0000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.u16 q3, q4, q5 :: Qd 0x098d0000 0x090f0000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.u16 q3, q4, q5 :: Qd 0x0a8e0000 0x0a0e0000 0x098d0000 0x090f0000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.u16 q0, q15, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u16 q0, q15, q2 :: Qd 0x131bffff 0x121fffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u16 q0, q15, q2 :: Qd 0x151dffff 0x141cffff 0x131bffff 0x121fffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.u8 q2, q7, q11 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.u8 q2, q7, q11 :: Qd 0x151d19ff 0x141c1fff 0x131b1aff 0x121f1eff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.u8 q13, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u8 q13, q1, q2 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u8 q13, q1, q2 :: Qd 0x151d19ff 0x141c1fff 0x131b1aff 0x121f1eff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u8 q3, q7, q5 :: Qd 0x131b1ad8 0x121f1ef8 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u8 q3, q7, q5 :: Qd 0x151d19e8 0x141c1fe0 0x131b1ad8 0x121f1ef8 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000 +vqshl.u8 q10, q11, q12 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqshl.u8 q10, q11, q12 :: Qd 0x151d19ff 0x141c1fff 0x131b1aff 0x121f1eff Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.u8 q6, q7, q8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.u8 q6, q7, q8 :: Qd 0x151d1974 0x141c1f70 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.u8 q10, q11, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqshl.u8 q10, q11, q12 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqshl.u8 q10, q11, q12 :: Qd 0x151d19ff 0x141c1fff 0x131b1aff 0x121f1eff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +---- VQSHL / VQSHLU (immediate) ---- +vqshl.s64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshl.s64 q0, q1, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshl.s64 q15, q14, #1 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s64 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s64 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s64 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s64 q5, q4, #63 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #63 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #60 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #60 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #59 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #59 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #58 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #58 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s64 q5, q4, #17 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s64 q5, q4, #63 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000 Qm (i32)0xffffffff fpscr: 00000000 +vqshl.s64 q5, q4, #63 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.s64 q5, q4, #60 :: Qd 0xf0000000 0x00000000 0xf0000000 0x00000000 Qm (i32)0xffffffff fpscr: 00000000 +vqshl.s64 q5, q4, #60 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.s64 q5, q4, #7 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000 Qm (i32)0x80000002 fpscr: 08000000 +vqshl.s64 q5, q4, #7 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshl.s32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshl.s32 q10, q11, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshl.s32 q15, q14, #1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s32 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s32 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s32 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s32 q5, q4, #31 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s32 q5, q4, #31 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s32 q5, q4, #28 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s32 q5, q4, #28 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s32 q5, q4, #27 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s32 q5, q4, #27 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s32 q5, q4, #26 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s32 q5, q4, #17 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s32 q5, q4, #31 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xffffffff fpscr: 00000000 +vqshl.s32 q5, q4, #31 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.s32 q5, q4, #29 :: Qd 0xe0000000 0xe0000000 0xe0000000 0xe0000000 Qm (i32)0xffffffff fpscr: 00000000 +vqshl.s32 q5, q4, #29 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.s32 q5, q4, #7 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x80000002 fpscr: 08000000 +vqshl.s32 q5, q4, #7 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshl.s16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshl.s16 q9, q8, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshl.s16 q15, q14, #1 :: Qd 0xfffeff02 0xfffeff02 0xfffeff02 0xfffeff02 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s16 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s16 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s16 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s16 q9, q8, #15 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s16 q9, q8, #15 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s16 q5, q4, #12 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s16 q5, q4, #12 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s16 q5, q4, #11 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s16 q5, q4, #11 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s16 q5, q4, #10 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s16 q5, q4, #4 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s16 q5, q4, #15 :: Qd 0x80008000 0x80008000 0x80008000 0x80008000 Qm (i32)0xffffffff fpscr: 00000000 +vqshl.s16 q5, q4, #15 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.s16 q5, q4, #12 :: Qd 0xf000f000 0xf000f000 0xf000f000 0xf000f000 Qm (i32)0xffffffff fpscr: 00000000 +vqshl.s16 q5, q4, #12 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.s16 q5, q4, #7 :: Qd 0x80000100 0x80000100 0x80000100 0x80000100 Qm (i32)0x80000002 fpscr: 08000000 +vqshl.s16 q5, q4, #7 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0x80000002 fpscr: 08000000 +vqshl.s8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshl.s8 q0, q1, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshl.s8 q15, q14, #1 :: Qd 0xfefefe80 0xfefefe80 0xfefefe80 0xfefefe80 Qm (i32)0xffffff81 fpscr: 08000000 +vqshl.s8 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s8 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s8 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.s8 q5, q4, #7 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s8 q5, q4, #7 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s8 q5, q4, #4 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s8 q5, q4, #4 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s8 q5, q4, #3 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s8 q5, q4, #3 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0x00000010 fpscr: 08000000 +vqshl.s8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s8 q5, q4, #2 :: Qd 0x54746474 0x50707c70 0x4c6c686c 0x487c787c Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s8 q5, q4, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000010 fpscr: 00000000 +vqshl.s8 q5, q4, #7 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff fpscr: 00000000 +vqshl.s8 q5, q4, #7 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff fpscr: 08000000 +vqshl.s8 q5, q4, #5 :: Qd 0xe0e0e0e0 0xe0e0e0e0 0xe0e0e0e0 0xe0e0e0e0 Qm (i32)0xffffffff fpscr: 00000000 +vqshl.s8 q5, q4, #5 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff fpscr: 08000000 +vqshl.s8 q5, q4, #2 :: Qd 0x80000008 0x80000008 0x80000008 0x80000008 Qm (i32)0x80000002 fpscr: 08000000 +vqshl.s8 q5, q4, #2 :: Qd 0x54746474 0x50707c70 0x4c6c686c 0x487c787c Qm (i32)0x80000002 fpscr: 00000000 +vqshl.u64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshl.u64 q0, q1, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshl.u64 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr: 08000000 +vqshl.u64 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u64 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u64 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #59 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #59 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #58 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #58 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u64 q5, q4, #17 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u64 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshl.u64 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshl.u32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshl.u32 q10, q11, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshl.u32 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr: 08000000 +vqshl.u32 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u32 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u32 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u32 q5, q4, #28 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u32 q5, q4, #28 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u32 q5, q4, #27 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u32 q5, q4, #27 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u32 q5, q4, #26 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u32 q5, q4, #17 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u32 q5, q4, #29 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u32 q5, q4, #29 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u32 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshl.u32 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshl.u16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshl.u16 q9, q8, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshl.u16 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr: 08000000 +vqshl.u16 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u16 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u16 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u16 q9, q8, #15 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u16 q9, q8, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u16 q5, q4, #12 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u16 q5, q4, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u16 q5, q4, #11 :: Qd 0x00008000 0x00008000 0x00008000 0x00008000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u16 q5, q4, #11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u16 q5, q4, #10 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u16 q5, q4, #4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u16 q5, q4, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u16 q5, q4, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u16 q5, q4, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u16 q5, q4, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u16 q5, q4, #7 :: Qd 0xffff0100 0xffff0100 0xffff0100 0xffff0100 Qm (i32)0x80000002 fpscr: 08000000 +vqshl.u16 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshl.u8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshl.u8 q0, q1, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshl.u8 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr: 08000000 +vqshl.u8 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u8 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u8 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshl.u8 q5, q4, #7 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u8 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u8 q5, q4, #4 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u8 q5, q4, #4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshl.u8 q5, q4, #3 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u8 q5, q4, #3 :: Qd 0xa8e8c8e8 0xa0e0f8e0 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u8 q5, q4, #2 :: Qd 0x54746474 0x50707c70 0x4c6c686c 0x487c787c Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u8 q5, q4, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000010 fpscr: 00000000 +vqshl.u8 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u8 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u8 q5, q4, #5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u8 q5, q4, #5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshl.u8 q5, q4, #2 :: Qd 0xff000008 0xff000008 0xff000008 0xff000008 Qm (i32)0x80000002 fpscr: 08000000 +vqshl.u8 q5, q4, #2 :: Qd 0x54746474 0x50707c70 0x4c6c686c 0x487c787c Qm (i32)0x80000002 fpscr: 00000000 +vqshlu.s64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshlu.s64 q0, q1, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshlu.s64 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000 +vqshlu.s64 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshlu.s64 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000 +vqshlu.s64 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshlu.s64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #59 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #59 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #58 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #58 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s64 q5, q4, #17 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s64 q5, q4, #63 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s64 q5, q4, #60 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s64 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 fpscr: 08000000 +vqshlu.s64 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshlu.s32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshlu.s32 q10, q11, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshlu.s32 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000 +vqshlu.s32 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshlu.s32 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000 +vqshlu.s32 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshlu.s32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s32 q5, q4, #28 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s32 q5, q4, #28 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s32 q5, q4, #27 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s32 q5, q4, #27 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s32 q5, q4, #26 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s32 q5, q4, #17 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s32 q5, q4, #31 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s32 q5, q4, #29 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s32 q5, q4, #29 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s32 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 fpscr: 08000000 +vqshlu.s32 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshlu.s16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshlu.s16 q9, q8, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshlu.s16 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000 +vqshlu.s16 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshlu.s16 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000 +vqshlu.s16 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshlu.s16 q9, q8, #15 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s16 q9, q8, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s16 q5, q4, #12 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s16 q5, q4, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s16 q5, q4, #11 :: Qd 0x00008000 0x00008000 0x00008000 0x00008000 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s16 q5, q4, #11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s16 q5, q4, #10 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s16 q5, q4, #4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s16 q5, q4, #15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s16 q5, q4, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s16 q5, q4, #12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s16 q5, q4, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s16 q5, q4, #7 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100 Qm (i32)0x80000002 fpscr: 08000000 +vqshlu.s16 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000 +vqshlu.s8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000 +vqshlu.s8 q0, q1, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000 +vqshlu.s8 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000 +vqshlu.s8 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000 +vqshlu.s8 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000 +vqshlu.s8 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000 +vqshlu.s8 q5, q4, #7 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s8 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s8 q5, q4, #4 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s8 q5, q4, #4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000 +vqshlu.s8 q5, q4, #3 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s8 q5, q4, #3 :: Qd 0xa8e8c8e8 0xa0e0f8e0 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s8 q5, q4, #2 :: Qd 0x54746474 0x50707c70 0x4c6c686c 0x487c787c Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s8 q5, q4, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000010 fpscr: 00000000 +vqshlu.s8 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s8 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s8 q5, q4, #5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s8 q5, q4, #5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000 +vqshlu.s8 q5, q4, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 fpscr: 08000000 +vqshlu.s8 q5, q4, #2 :: Qd 0x54746474 0x50707c70 0x4c6c686c 0x487c787c Qm (i32)0x80000002 fpscr: 00000000 +---- VQRSHL (register) ---- +vqrshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 q0, q1, q2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 q0, q1, q2 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 q3, q4, q5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 q3, q4, q5 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s64 q3, q4, q5 :: Qd 0x02636343 0x6243e3c4 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s64 q3, q4, q5 :: Qd 0x02a3a323 0xa28383e4 0x02636343 0x6243e3c4 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000 +vqrshl.s64 q0, q1, q2 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqrshl.s64 q0, q1, q2 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqrshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffc00 0xffffffff 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.s64 q13, q14, q15 :: Qd 0x00000004 0xc6c686c5 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.s64 q13, q14, q15 :: Qd 0x00000005 0x47464745 0x00000004 0xc6c686c5 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.s32 q2, q8, q4 :: Qd 0x0131b1a2 0x0121f1e2 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.s32 q2, q8, q4 :: Qd 0x0151d192 0x0141c1f2 0x0131b1a2 0x0121f1e2 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.s32 q12, q11, q13 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.s32 q12, q11, q13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.s32 q12, q11, q13 :: Qd 0x000a8e8d 0x000a0e10 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.s32 q0, q1, q2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.s32 q0, q1, q2 :: Qd 0x002a3a32 0x0028383e 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q9, q10, q11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q9, q10, q11 :: Qd 0x0a8e8c8f 0x0a0e0f8e 0x098d8d0e 0x090f8f10 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.s32 q13, q3, q5 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 08000000 +vqrshl.s32 q13, q3, q5 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 08000000 +vqrshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 q11, q10, q2 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 q11, q10, q2 :: Qd 0x0a8f0000 0x0a0e0000 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s16 q3, q14, q7 :: Qd 0x098e0343 0x091003c4 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s16 q3, q14, q7 :: Qd 0x0a8f0324 0x0a0e03e4 0x098e0343 0x091003c4 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q0, q11, q2 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q0, q11, q2 :: Qd 0x0a8f0c8f 0x0a0e0f8e 0x098e0d0e 0x09100f10 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 q1, q2, q3 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 q1, q2, q3 :: Qd 0x0a8f0000 0x0a0e0000 0x098e0000 0x09100000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.s16 q3, q4, q5 :: Qd 0x098e0001 0x09100001 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.s16 q3, q4, q5 :: Qd 0x0a8f0001 0x0a0e0001 0x098e0001 0x09100001 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.s16 q0, q15, q2 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s16 q0, q15, q2 :: Qd 0x131b7fff 0x121f7fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s16 q0, q15, q2 :: Qd 0x151d7fff 0x141c7fff 0x131b7fff 0x121f7fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x0b0f0d0f 0x0a0e100e 0x0a0e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x0a8f0c8f 0x0a0e0f8e 0x098e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x0a8e8c8f 0x0a0e0f8e 0x098d8d0e 0x090f8f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x0b0f0d0f 0x0a0e100e 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x0a8f0c8f 0x0a0e0f8e 0x098e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x0a8e8c8f 0x0a0e0f8e 0x098d8d0e 0x090f8f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x0b0f0d0f 0x0a0e100e 0x0a0e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x0a8f0c8f 0x0a0e0f8e 0x098e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x0a8e8c8f 0x0a0e0f8e 0x098d8d0e 0x090f8f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s16 q2, q7, q11 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s32 q2, q7, q11 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s8 q2, q7, q11 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80 Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.s8 q2, q7, q11 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.s8 q13, q1, q2 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80 Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s8 q13, q1, q2 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s8 q13, q1, q2 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.s8 q3, q7, q5 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 08000000 +vqrshl.s8 q3, q7, q5 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 08000000 +vqrshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000 +vqrshl.s8 q10, q11, q12 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqrshl.s8 q10, q11, q12 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqrshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.s8 q6, q7, q8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.s8 q6, q7, q8 :: Qd 0x151d1974 0x141c1f70 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.s8 q10, q11, q12 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqrshl.s8 q10, q11, q12 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqrshl.s8 q10, q11, q12 :: Qd 0x151d197f 0x141c1f7f 0x131b1a7f 0x121f1e7f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqrshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.u64 q0, q1, q2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.u64 q0, q1, q2 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.u64 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 08000000 +vqrshl.u64 q3, q4, q5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.u64 q3, q4, q5 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u64 q3, q4, q5 :: Qd 0x02636343 0x6243e3c4 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u64 q3, q4, q5 :: Qd 0x02a3a323 0xa28383e4 0x02636343 0x6243e3c4 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000 +vqrshl.u64 q0, q1, q2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqrshl.u64 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqrshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffc00 0x0000003f 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.u64 q13, q14, q15 :: Qd 0x00000004 0xc6c686c5 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.u64 q13, q14, q15 :: Qd 0x00000005 0x47464745 0x00000004 0xc6c686c5 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.u32 q2, q8, q4 :: Qd 0x0131b1a2 0x0121f1e2 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.u32 q2, q8, q4 :: Qd 0x0151d192 0x0141c1f2 0x0131b1a2 0x0121f1e2 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.u32 q12, q11, q13 :: Qd 0x00800000 0x00800000 0x00800000 0x00800000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.u32 q12, q11, q13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.u32 q12, q11, q13 :: Qd 0x000a8e8d 0x000a0e10 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.u32 q0, q1, q2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.u32 q0, q1, q2 :: Qd 0x002a3a32 0x0028383e 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q9, q10, q11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q9, q10, q11 :: Qd 0x0a8e8c8f 0x0a0e0f8e 0x098d8d0e 0x090f8f10 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u32 q13, q3, q5 :: Qd 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u32 q13, q3, q5 :: Qd 0xa8e8c8e8 0xa0e0f8e0 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 q11, q10, q2 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 q11, q10, q2 :: Qd 0x0a8f0000 0x0a0e0000 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u16 q3, q14, q7 :: Qd 0x098e0343 0x091003c4 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u16 q3, q14, q7 :: Qd 0x0a8f0324 0x0a0e03e4 0x098e0343 0x091003c4 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q0, q11, q2 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q0, q11, q2 :: Qd 0x0a8f0c8f 0x0a0e0f8e 0x098e0d0e 0x09100f10 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 q1, q2, q3 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 q1, q2, q3 :: Qd 0x0a8f0000 0x0a0e0000 0x098e0000 0x09100000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.u16 q3, q4, q5 :: Qd 0x098e0001 0x09100001 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.u16 q3, q4, q5 :: Qd 0x0a8f0001 0x0a0e0001 0x098e0001 0x09100001 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.u16 q0, q15, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u16 q0, q15, q2 :: Qd 0x131bffff 0x121fffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u16 q0, q15, q2 :: Qd 0x151dffff 0x141cffff 0x131bffff 0x121fffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x151d19ff 0x141c1fff 0x131b1aff 0x121f1eff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x0b0f0d0f 0x0a0e100e 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x0b0f0d0f 0x0a0e100e 0x0a0e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0x0a8f0c8f 0x0a0e0f8e 0x098e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0x0a8e8c8f 0x0a0e0f8e 0x098d8d0e 0x090f8f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x8080807f 0x8080807f 0x8080807f 0x8080807f Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x0b0f0d0f 0x0a0e100e 0x0a0e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0x80007fff 0x80007fff 0x80007fff 0x80007fff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0x0a8f0c8f 0x0a0e0f8e 0x098e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0x0a8e8c8f 0x0a0e0f8e 0x098d8d0e 0x090f8f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u8 q2, q7, q11 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u16 q2, q7, q11 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u32 q2, q7, q11 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u8 q13, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u8 q13, q1, q2 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u8 q13, q1, q2 :: Qd 0x151d19ff 0x141c1fff 0x131b1aff 0x121f1eff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u8 q3, q7, q5 :: Qd 0x131b1ad8 0x121f1ef8 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u8 q3, q7, q5 :: Qd 0x151d19e8 0x141c1fe0 0x131b1ad8 0x121f1ef8 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000 +vqrshl.u8 q10, q11, q12 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqrshl.u8 q10, q11, q12 :: Qd 0x151d19ff 0x141c1fff 0x131b1aff 0x121f1eff Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqrshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.u8 q6, q7, q8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.u8 q6, q7, q8 :: Qd 0x151d1974 0x141c1f70 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.u8 q10, q11, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqrshl.u8 q10, q11, q12 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqrshl.u8 q10, q11, q12 :: Qd 0x151d19ff 0x141c1fff 0x131b1aff 0x121f1eff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +---- VRSHL (register) ---- +vrshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 +vrshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 +vrshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd +vrshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e +vrshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffc00 0xffffffff 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 +vrshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 +vrshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 +vrshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc +vrshl.s32 q12, q11, q13 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 +vrshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 +vrshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff +vrshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 +vrshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 +vrshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd +vrshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff +vrshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 +vrshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 +vrshl.s16 q0, q15, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x0000001e +vrshl.s8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s8 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s16 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s32 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s8 q2, q7, q11 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s16 q2, q7, q11 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s8 q2, q7, q11 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0xffffffff Qn (i32)0x00000028 +vrshl.s8 q13, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0xfffffffc Qn (i32)0x0000001e +vrshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 +vrshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 +vrshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 +vrshl.s8 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vrshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 +vrshl.u64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 +vrshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd +vrshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e +vrshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffc00 0x0000003f 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 +vrshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 +vrshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 +vrshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc +vrshl.u32 q12, q11, q13 :: Qd 0x00800000 0x00800000 0x00800000 0x00800000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 +vrshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 +vrshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff +vrshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 +vrshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 +vrshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd +vrshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff +vrshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 +vrshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 +vrshl.u16 q0, q15, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x0000001e +vrshl.u8 q2, q7, q11 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0xffffffff Qn (i32)0x00000028 +vrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u16 q2, q7, q11 :: Qd 0x80008000 0x80008000 0x80008000 0x80008000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u32 q2, q7, q11 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u8 q2, q7, q11 :: Qd 0x8080807f 0x8080807f 0x8080807f 0x8080807f Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u16 q2, q7, q11 :: Qd 0x80007fff 0x80007fff 0x80007fff 0x80007fff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u32 q2, q7, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u8 q13, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0xfffffffc Qn (i32)0x0000001e +vrshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 +vrshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 +vrshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 +vrshl.u8 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VMAX (integer) ---- +vmax.s32 q0, q1, q2 :: Qd 0x00000079 0x00000079 0x00000079 0x00000079 Qm (i32)0x00000019 Qn (i32)0x00000079 +vmax.s32 q0, q1, q2 :: Qd 0x000000fa 0x000000fa 0x000000fa 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000079 +vmax.s32 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmax.s16 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x00000078 +vmax.s8 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmax.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s8 q5, q7, q5 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s16 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s32 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s32 q10, q11, q12 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmax.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000019 Qn (i32)0x00000078 +vmax.u32 q0, q1, q2 :: Qd 0x000000fa 0x000000fa 0x000000fa 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000078 +vmax.u32 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmax.u16 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x00000078 +vmax.u8 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmax.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u8 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u16 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u32 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u32 q10, q11, q12 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VMIN (integer) ---- +vmin.s32 q0, q1, q2 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000079 +vmin.s32 q0, q1, q2 :: Qd 0x00000079 0x00000079 0x00000079 0x00000079 Qm (i32)0x000000fa Qn (i32)0x00000079 +vmin.s32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmin.s16 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmin.s8 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmin.s8 q5, q7, q5 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s8 q5, q7, q5 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s32 q10, q11, q12 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmin.u32 q0, q1, q2 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000078 +vmin.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x000000fa Qn (i32)0x00000078 +vmin.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmin.u16 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmin.u8 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmin.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u32 q10, q11, q12 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VABD ---- +vabd.s32 q0, q1, q2 :: Qd 0x0000005f 0x0000005f 0x0000005f 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078 +vabd.s32 q0, q1, q2 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060 Qm (i32)0x00000019 Qn (i32)0x00000079 +vabd.s32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vabd.s16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.s8 q0, q1, q2 :: Qd 0x000000ec 0x000000ec 0x000000ec 0x000000ec Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.s8 q5, q7, q5 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s8 q5, q7, q5 :: Qd 0x7f010101 0x7f010101 0x7f010101 0x7f010101 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabd.s8 q5, q7, q5 :: Qd 0x7f010137 0x7f010137 0x7f010137 0x7f010137 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabd.s16 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s32 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s8 q5, q7, q5 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s8 q5, q7, q5 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s32 q10, q11, q12 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078 +vabd.u32 q0, q1, q2 :: Qd 0x0000005f 0x0000005f 0x0000005f 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078 +vabd.u32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.u16 q0, q1, q2 :: Qd 0xfffffefc 0xfffffefc 0xfffffefc 0xfffffefc Qm (i32)0xffffff74 Qn (i32)0x00000078 +vabd.u8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.u8 q5, q7, q5 :: Qd 0x7fffff01 0x7fffff01 0x7fffff01 0x7fffff01 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabd.u8 q5, q7, q5 :: Qd 0x7fffff37 0x7fffff37 0x7fffff37 0x7fffff37 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabd.u8 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u16 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u32 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u32 q10, q11, q12 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VABA ---- +vaba.s32 q0, q1, q2 :: Qd 0x555555b4 0x555555b4 0x555555b4 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078 +vaba.s32 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x00000019 Qn (i32)0x00000079 +vaba.s32 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s16 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s8 q0, q1, q2 :: Qd 0x55555541 0x55555541 0x55555541 0x55555541 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s8 q5, q7, q5 :: Qd 0xff010103 0xff010103 0xff010103 0xff010103 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vaba.s8 q5, q7, q5 :: Qd 0x7e00006f 0x7e00006f 0x7e00006f 0x7e00006f Qm (i32)0x80000001 Qn (i32)0xffffff38 +vaba.s16 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s32 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s8 q5, q7, q5 :: Qd 0x80000005 0x80000005 0x80000005 0x80000005 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s8 q5, q7, q5 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s32 q10, q11, q12 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078 +vaba.u32 q0, q1, q2 :: Qd 0x555555b4 0x555555b4 0x555555b4 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078 +vaba.u32 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u16 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u8 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u8 q5, q7, q5 :: Qd 0xffffff03 0xffffff03 0xffffff03 0xffffff03 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vaba.u8 q5, q7, q5 :: Qd 0x7efefe6f 0x7efefe6f 0x7efefe6f 0x7efefe6f Qm (i32)0x80000001 Qn (i32)0xffffff38 +vaba.u8 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u16 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u32 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u8 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u8 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u32 q10, q11, q12 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VABAL ---- +vabal.s32 q0, d1, d2 :: Qd 0x00000019 0x00000078 0x55555555 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078 +vabal.s32 q0, d1, d2 :: Qd 0x00000019 0x00000079 0x55555555 0x555555b5 Qm (i32)0x00000019 Qn (i32)0x00000079 +vabal.s32 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabal.s16 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabal.s8 q0, d1, d2 :: Qd 0x0000008c 0x00000178 0x55555555 0x55555641 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555556 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabal.s8 q5, d7, d5 :: Qd 0x55d45556 0x55565556 0x55d45556 0x55565556 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabal.s8 q5, d7, d5 :: Qd 0x55d45556 0x5556558c 0x55d45556 0x5556558c Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabal.s16 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabal.s32 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555557 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabal.s16 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabal.s32 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555557 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabal.s16 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabal.s32 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabal.s32 q10, d31, d12 :: Qd 0x55555555 0x555555b5 0x55555555 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078 +vabal.u32 q0, d1, d2 :: Qd 0x00000019 0x00000078 0x55555555 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078 +vabal.u32 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabal.u16 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabal.u8 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabal.u8 q5, d7, d5 :: Qd 0x55d45654 0x56545556 0x55d45654 0x56545556 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabal.u8 q5, d7, d5 :: Qd 0x55d45654 0x5654558c 0x55d45654 0x5654558c Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabal.u8 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabal.u16 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabal.u32 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabal.u8 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabal.u16 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabal.u32 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabal.u8 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabal.u16 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabal.u32 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabal.u32 q10, d11, d12 :: Qd 0x55555555 0x555555b5 0x55555555 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VABDL ---- +vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x0000005f 0x00000000 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078 +vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060 Qm (i32)0x00000019 Qn (i32)0x00000079 +vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabdl.s8 q0, d1, d2 :: Qd 0x00000000 0x000000ec 0x00000000 0x000000ec Qm (i32)0x0000008c Qn (i32)0x00000078 +vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabdl.s8 q5, d7, d5 :: Qd 0x007f0001 0x00010001 0x007f0001 0x00010001 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabdl.s8 q5, d7, d5 :: Qd 0x007f0001 0x00010037 0x007f0001 0x00010037 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabdl.s32 q10, d31, d12 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078 +vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x0000005f 0x00000000 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078 +vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabdl.u8 q5, d7, d5 :: Qd 0x007f00ff 0x00ff0001 0x007f00ff 0x00ff0001 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabdl.u8 q5, d7, d5 :: Qd 0x007f00ff 0x00ff0037 0x007f00ff 0x00ff0037 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabdl.u32 q10, d11, d12 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VTST ---- +vtst.32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +vtst.32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vtst.16 q6, q7, q8 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vtst.8 q9, q10, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078 +vtst.8 q0, q1, q2 :: Qd 0xff000000 0xff000000 0xff000000 0xff000000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vtst.16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00004001 Qn (i32)0x00004001 +vtst.32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vtst.8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x00000002 +vtst.16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00004001 Qn (i32)0x00004001 +vtst.32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x80000002 +vtst.32 q10, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VCEQ ---- +vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vceq.i32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078 +vceq.i16 q6, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vceq.i8 q9, q10, q12 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078 +vceq.i8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000002 +vceq.i16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00004001 Qn (i32)0x00004001 +vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vceq.i8 q0, q1, q2 :: Qd 0x00ffff00 0x00ffff00 0x00ffff00 0x00ffff00 Qm (i32)0x80000001 Qn (i32)0x00000002 +vceq.i16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000001 Qn (i32)0x00004001 +vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x80000002 +vceq.i32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VMLA ---- +vmla.i32 q0, q1, q2 :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15 Qm (i32)0xffffffe8 Qn (i32)0x00000078 +vmla.i32 q6, q7, q8 :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmla.i16 q9, q11, q12 :: Qd 0x5555bd55 0x5555bd55 0x5555bd55 0x5555bd55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmla.i16 q7, q1, q2 :: Qd 0x5555bd55 0x5555bd55 0x5555bd55 0x5555bd55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmla.i8 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmla.i8 q10, q11, q12 :: Qd 0x5555559f 0x5555559f 0x5555559f 0x5555559f Qm (i32)0x00000021 Qn (i32)0x0000000a +vmla.i16 q4, q5, q6 :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmla.i16 q14, q5, q9 :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmla.i32 q7, q8, q9 :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i8 q10, q13, q12 :: Qd 0x5555559f 0x5555559f 0x5555559f 0x5555559f Qm (i32)0x00000021 Qn (i32)0x0000000a +vmla.i16 q4, q5, q6 :: Qd 0x55551751 0x55551751 0x55551751 0x55551751 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmla.i32 q7, q8, q9 :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i32 q10, q11, q15 :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15 Qm (i32)0x00000018 Qn (i32)0xffffff88 +---- VMLS ---- +vmls.i32 q0, q1, q2 :: Qd 0x55556095 0x55556095 0x55556095 0x55556095 Qm (i32)0xffffffe8 Qn (i32)0x00000078 +vmls.i32 q6, q7, q8 :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmls.i16 q9, q11, q12 :: Qd 0x5555ed55 0x5555ed55 0x5555ed55 0x5555ed55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmls.i8 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmls.i8 q10, q11, q12 :: Qd 0x5555550b 0x5555550b 0x5555550b 0x5555550b Qm (i32)0x00000021 Qn (i32)0x0000000a +vmls.i16 q4, q5, q6 :: Qd 0x5555b553 0x5555b553 0x5555b553 0x5555b553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmls.i32 q7, q8, q9 :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i8 q10, q13, q12 :: Qd 0x5555550b 0x5555550b 0x5555550b 0x5555550b Qm (i32)0x00000021 Qn (i32)0x0000000a +vmls.i16 q4, q5, q6 :: Qd 0x55559359 0x55559359 0x55559359 0x55559359 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmls.i32 q7, q8, q9 :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i32 q10, q11, q15 :: Qd 0x55556095 0x55556095 0x55556095 0x55556095 Qm (i32)0xffffffe8 Qn (i32)0x00000078 +---- VMUL ---- +vmul.i32 q0, q1, q2 :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.i32 q6, q7, q8 :: Qd 0xffffbe60 0xffffbe60 0xffffbe60 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmul.i16 q9, q11, q12 :: Qd 0x00006800 0x00006800 0x00006800 0x00006800 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmul.i8 q0, q1, q2 :: Qd 0x000000a0 0x000000a0 0x000000a0 0x000000a0 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmul.i8 q10, q11, q12 :: Qd 0x0000004a 0x0000004a 0x0000004a 0x0000004a Qm (i32)0x00000021 Qn (i32)0x0000000a +vmul.i16 q4, q5, q6 :: Qd 0x0000a002 0x0000a002 0x0000a002 0x0000a002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmul.i32 q7, q8, q9 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i8 q10, q11, q12 :: Qd 0x0000c00e 0x0000c00e 0x0000c00e 0x0000c00e Qm (i32)0x0200feb2 Qn (i32)0x000020df +vmul.i16 q4, q5, q6 :: Qd 0x00008866 0x00008866 0x00008866 0x00008866 Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmul.i32 q7, q8, q9 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmul.i8 q10, q13, q12 :: Qd 0x0000004a 0x0000004a 0x0000004a 0x0000004a Qm (i32)0x00000021 Qn (i32)0x0000000a +vmul.i16 q4, q5, q6 :: Qd 0x0000c1fc 0x0000c1fc 0x0000c1fc 0x0000c1fc Qm (i32)0x100000fe Qn (i32)0x00002002 +vmul.i32 q7, q8, q9 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i32 q10, q11, q15 :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.p8 q0, q1, q2 :: Qd 0x00000005 0x00000005 0x00000005 0x00000005 Qm (i32)0x00000003 Qn (i32)0x00000003 +vmul.p8 q0, q1, q2 :: Qd 0x00000044 0x00000044 0x00000044 0x00000044 Qm (i32)0x0000000c Qn (i8)0x0000000f +---- VMUL (by scalar) ---- +vmul.i32 q0, q1, d4[0] :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.i32 q15, q8, d7[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmul.i16 q10, q9, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmul.i16 q4, q5, d6[2] :: Qd 0x0000a002 0x0000a002 0x0000a002 0x0000a002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmul.i32 q4, q8, d15[1] :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i16 q4, q5, d6[0] :: Qd 0xdffe8866 0xdffe8866 0xdffe8866 0xdffe8866 Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmul.i32 q7, q8, d1[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmul.i16 q4, q5, d6[0] :: Qd 0x2000c1fc 0x2000c1fc 0x2000c1fc 0x2000c1fc Qm (i32)0x100000fe Qn (i32)0x00002002 +vmul.i32 q7, q8, d1[1] :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VMLA (by scalar) ---- +vmla.i32 q0, q1, d4[0] :: Qd 0x55556095 0x55556095 0x55556095 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmla.i32 q15, q8, d7[1] :: Qd 0x555513b5 0x555513b5 0x555513b5 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmla.i16 q10, q9, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmla.i16 q4, q5, d6[2] :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmla.i32 q4, q8, d15[1] :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i16 q4, q5, d6[0] :: Qd 0x3553ddbb 0x3553ddbb 0x3553ddbb 0x3553ddbb Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmla.i32 q7, q8, d1[1] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmla.i16 q4, q5, d6[0] :: Qd 0x75551751 0x75551751 0x75551751 0x75551751 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmla.i32 q7, q8, d1[1] :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VMLS (by scalar) ---- +vmls.i32 q0, q1, d4[0] :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmls.i32 q15, q8, d7[1] :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmls.i16 q10, q9, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmls.i16 q4, q5, d6[2] :: Qd 0x5555b553 0x5555b553 0x5555b553 0x5555b553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmls.i32 q4, q8, d15[1] :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i16 q4, q5, d6[0] :: Qd 0x7557ccef 0x7557ccef 0x7557ccef 0x7557ccef Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmls.i32 q7, q8, d1[1] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmls.i16 q4, q5, d6[0] :: Qd 0x35559359 0x35559359 0x35559359 0x35559359 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmls.i32 q7, q8, d1[1] :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VMULL (by scalar) ---- +vmull.s32 q0, d2, d4[0] :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmull.s32 q15, d8, d7[1] :: Qd 0xffffffff 0xffffbe60 0xffffffff 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmull.s16 q10, d31, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmull.s16 q4, d5, d6[2] :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmull.s32 q4, d7, d15[1] :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmull.s16 q4, d5, d6[0] :: Qd 0xffffdffe 0xf2858866 0xffffdffe 0xf2858866 Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmull.s32 q7, d7, d1[1] :: Qd 0xfff9fffa 0x00000000 0xfff9fffa 0x00000000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmull.s16 q4, d5, d6[0] :: Qd 0x02002000 0x001fc1fc 0x02002000 0x001fc1fc Qm (i32)0x100000fe Qn (i32)0x00002002 +vmull.s32 q7, d7, d1[1] :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmull.u32 q0, d1, d4[0] :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmull.u32 q15, d8, d7[1] :: Qd 0x00000046 0x0000008c 0x00000046 0x0000008c Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmull.u16 q10, d31, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmull.u16 q4, d5, d6[2] :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmull.u32 q4, d7, d15[1] :: Qd 0x40000001 0x80000002 0x40000001 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmull.u16 q4, d5, d6[0] :: Qd 0x2001dffe 0x12878866 0x2001dffe 0x12878866 Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmull.u32 q7, d7, d1[1] :: Qd 0x00060006 0x00000000 0x00060006 0x00000000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmull.u16 q4, d5, d6[0] :: Qd 0x02002000 0x001fc1fc 0x02002000 0x001fc1fc Qm (i32)0x100000fe Qn (i32)0x00002002 +vmull.u32 q7, d7, d1[1] :: Qd 0x40000001 0x80000002 0x40000001 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VMLAL (by scalar) ---- +vmlal.s32 q0, d2, d4[0] :: Qd 0x55555555 0x55556095 0x55555555 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmlal.s32 q15, d8, d7[1] :: Qd 0x55555555 0x555513b5 0x55555555 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmlal.s16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlal.s16 q4, d5, d6[2] :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlal.s32 q4, d7, d15[1] :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlal.s16 q4, d5, d6[0] :: Qd 0x55553553 0x47daddbb 0x55553553 0x47daddbb Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmlal.s32 q7, d7, d1[1] :: Qd 0x554f554f 0x55555555 0x554f554f 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmlal.s16 q4, d5, d6[0] :: Qd 0x57557555 0x55751751 0x57557555 0x55751751 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmlal.s32 q7, d7, d1[1] :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlal.u32 q0, d1, d4[0] :: Qd 0x00000018 0x00000b58 0x55555555 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmlal.u32 q15, d8, d7[1] :: Qd 0x5555559b 0x555555e1 0x5555559b 0x555555e1 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmlal.u16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlal.u16 q4, d5, d6[2] :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlal.u32 q4, d7, d15[1] :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlal.u16 q4, d5, d6[0] :: Qd 0x75573553 0x67dcddbb 0x75573553 0x67dcddbb Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmlal.u32 q7, d7, d1[1] :: Qd 0x555b555b 0x55555555 0x555b555b 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmlal.u16 q4, d5, d6[0] :: Qd 0x57557555 0x55751751 0x57557555 0x55751751 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmlal.u32 q7, d7, d1[1] :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VMLSL (by scalar) ---- +vmlsl.s32 q0, d2, d4[0] :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmlsl.s32 q15, d8, d7[1] :: Qd 0x55555555 0x555596f5 0x55555555 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmlsl.s16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlsl.s16 q4, d5, d6[2] :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlsl.s32 q4, d7, d15[1] :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlsl.s16 q4, d5, d6[0] :: Qd 0x55557557 0x62cfccef 0x55557557 0x62cfccef Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmlsl.s32 q7, d7, d1[1] :: Qd 0x555b555b 0x55555555 0x555b555b 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmlsl.s16 q4, d5, d6[0] :: Qd 0x53553555 0x55359359 0x53553555 0x55359359 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmlsl.s32 q7, d7, d1[1] :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlsl.u32 q0, d1, d4[0] :: Qd 0x00000017 0xfffff4d8 0x55555555 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmlsl.u32 q15, d8, d7[1] :: Qd 0x5555550f 0x555554c9 0x5555550f 0x555554c9 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmlsl.u16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlsl.u16 q4, d5, d6[2] :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlsl.u32 q4, d7, d15[1] :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlsl.u16 q4, d5, d6[0] :: Qd 0x35537557 0x42cdccef 0x35537557 0x42cdccef Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmlsl.u32 q7, d7, d1[1] :: Qd 0x554f554f 0x55555555 0x554f554f 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmlsl.u16 q4, d5, d6[0] :: Qd 0x53553555 0x55359359 0x53553555 0x55359359 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmlsl.u32 q7, d7, d1[1] :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VRSHR ---- +vrshr.s8 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff +vrshr.s8 q0, q1, #0 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xffffffff +vrshr.s8 q0, q1, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshr.s8 q0, q1, #1 :: Qd 0x13171715 0x13151716 0x12161616 0x12181718 Qm (i32)0xffffffff +vrshr.s16 q3, q4, #2 :: Qd 0x0000ffe1 0x0000ffe1 0x0000ffe1 0x0000ffe1 Qm (i32)0xffffff84 +vrshr.s16 q3, q4, #2 :: Qd 0x098b0b4b 0x094b0b8b 0x090b0acb 0x08cc0b8c Qm (i32)0xffffff84 +vrshr.s32 q2, q5, #31 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshr.s32 q2, q5, #31 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshr.s8 q6, q7, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000ffff +vrshr.s8 q6, q7, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000ffff +vrshr.s16 q8, q9, #12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xfffffff6 +vrshr.s16 q8, q9, #12 :: Qd 0x00020003 0x00020003 0x00020003 0x00020003 Qm (i32)0xfffffff6 +vrshr.s32 q10, q11, #5 :: Qd 0x00000140 0x00000140 0x00000140 0x00000140 Qm (i32)0x000027fa +vrshr.s32 q10, q11, #5 :: Qd 0x01316969 0x01295171 0x01216159 0x01197971 Qm (i32)0x000027fa +vrshr.u8 q12, q13, #1 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff +vrshr.u8 q12, q13, #1 :: Qd 0x13171715 0x13151716 0x12161616 0x12181718 Qm (i32)0xffffffff +vrshr.u16 q14, q15, #11 :: Qd 0x00200020 0x00200020 0x00200020 0x00200020 Qm (i32)0xffffffff +vrshr.u16 q14, q15, #11 :: Qd 0x00050006 0x00050006 0x00050005 0x00040006 Qm (i32)0xffffffff +vrshr.u32 q10, q11, #9 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x000003e8 +vrshr.u32 q10, q11, #9 :: Qd 0x00131697 0x00129517 0x00121616 0x00119797 Qm (i32)0x000003e8 +vrshr.u8 q7, q13, #7 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i32)0xffffffff +vrshr.u8 q7, q13, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshr.u16 q8, q1, #5 :: Qd 0x0000055e 0x0000055e 0x0000055e 0x0000055e Qm (i32)0x0000abcf +vrshr.u16 q8, q1, #5 :: Qd 0x01310169 0x01290171 0x01210159 0x01190171 Qm (i32)0x0000abcf +vrshr.u32 q12, q3, #15 :: Qd 0x00020000 0x00020000 0x00020000 0x00020000 Qm (i32)0xfffffe50 +vrshr.u32 q12, q3, #15 :: Qd 0x00004c5a 0x00004a54 0x00004858 0x0000465e Qm (i32)0xfffffe50 +vrshr.u64 q0, q1, #42 :: Qd 0x00000000 0x00400000 0x00000000 0x00400000 Qm (i32)0xffffffff +vrshr.u64 q0, q1, #42 :: Qd 0x00000000 0x00098b4b 0x00000000 0x00090b0b Qm (i32)0xffffffff +vrshr.s64 q6, q7, #12 :: Qd 0x00000000 0xfac00001 0x00000000 0xfac00001 Qm (i32)0x00000fac +vrshr.s64 q6, q7, #12 :: Qd 0x000262d2 0xd2a252a3 0x000242c2 0xb2b232f3 Qm (i32)0x00000fac +vrshr.u64 q8, q4, #9 :: Qd 0x0000001a 0x7c00001a 0x0000001a 0x7c00001a Qm (i32)0x000034f8 +vrshr.u64 q8, q4, #9 :: Qd 0x00131696 0x95129517 0x00121615 0x95919797 Qm (i32)0x000034f8 +vrshr.s64 q9, q12, #11 :: Qd 0x00000030 0x32c00030 0x00000030 0x32c00030 Qm (i32)0x00018196 +vrshr.s64 q9, q12, #11 :: Qd 0x0004c5a5 0xa544a546 0x00048585 0x656465e6 Qm (i32)0x00018196 +---- VRSRA ---- +vrsra.s8 q0, q1, #1 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xffffffff +vrsra.s8 q0, q1, #1 :: Qd 0x28343032 0x27313632 0x25313031 0x24373537 Qm (i32)0xffffffff +vrsra.s16 q3, q4, #2 :: Qd 0x55555536 0x55555536 0x55555536 0x55555536 Qm (i32)0xffffff84 +vrsra.s16 q3, q4, #2 :: Qd 0x1ea82468 0x1d672aa7 0x1c2624e6 0x1aeb29ab Qm (i32)0xffffff84 +vrsra.s32 q2, q5, #31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xffffffff +vrsra.s32 q2, q5, #31 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff +vrsra.s8 q6, q7, #7 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x0000ffff +vrsra.s8 q6, q7, #7 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x0000ffff +vrsra.s16 q8, q9, #12 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xfffffff6 +vrsra.s16 q8, q9, #12 :: Qd 0x151f1920 0x141e1f1f 0x131d1a1e 0x12211e22 Qm (i32)0xfffffff6 +vrsra.s32 q10, q11, #5 :: Qd 0x55555695 0x55555695 0x55555695 0x55555695 Qm (i32)0x000027fa +vrsra.s32 q10, q11, #5 :: Qd 0x164e8286 0x1545708d 0x143c7b74 0x13389790 Qm (i32)0x000027fa +vrsra.u8 q12, q13, #1 :: Qd 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 Qm (i32)0xffffffff +vrsra.u8 q12, q13, #1 :: Qd 0x28343032 0x27313632 0x25313031 0x24373537 Qm (i32)0xffffffff +vrsra.u16 q14, q15, #11 :: Qd 0x55755575 0x55755575 0x55755575 0x55755575 Qm (i32)0xffffffff +vrsra.u16 q14, q15, #11 :: Qd 0x15221923 0x14211f22 0x13201a20 0x12231e25 Qm (i32)0xffffffff +vrsra.u32 q10, q11, #9 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x000003e8 +vrsra.u32 q10, q11, #9 :: Qd 0x15302fb4 0x142eb433 0x132d3031 0x1230b5b6 Qm (i32)0x000003e8 +vrsra.u8 q7, q13, #7 :: Qd 0x57575757 0x57575757 0x57575757 0x57575757 Qm (i32)0xffffffff +vrsra.u8 q7, q13, #7 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff +vrsra.u16 q8, q1, #5 :: Qd 0x55555ab3 0x55555ab3 0x55555ab3 0x55555ab3 Qm (i32)0x0000abcf +vrsra.u16 q8, q1, #5 :: Qd 0x164e1a86 0x1545208d 0x143c1b74 0x13381f90 Qm (i32)0x0000abcf +vrsra.u32 q12, q3, #15 :: Qd 0x55575555 0x55575555 0x55575555 0x55575555 Qm (i32)0xfffffe50 +vrsra.u32 q12, q3, #15 :: Qd 0x151d6577 0x141c6970 0x131b6273 0x121f647d Qm (i32)0xfffffe50 +vrsra.u64 q0, q1, #42 :: Qd 0x55555555 0x55955555 0x55555555 0x55955555 Qm (i32)0xffffffff +vrsra.u64 q0, q1, #42 :: Qd 0x151d191d 0x1425aa67 0x131b1a1b 0x1228292a Qm (i32)0xffffffff +vrsra.s64 q6, q7, #12 :: Qd 0x55555556 0x50155556 0x55555556 0x50155556 Qm (i32)0x00000fac +vrsra.s64 q6, q7, #12 :: Qd 0x151f7bef 0xe6be71bf 0x131d5cdd 0xc4d15112 Qm (i32)0x00000fac +vrsra.u64 q8, q4, #9 :: Qd 0x5555556f 0xd155556f 0x5555556f 0xd155556f Qm (i32)0x000034f8 +vrsra.u64 q8, q4, #9 :: Qd 0x15302fb3 0xa92eb433 0x132d3030 0xa7b0b5b6 Qm (i32)0x000034f8 +vrsra.s64 q9, q12, #11 :: Qd 0x55555585 0x88155585 0x55555585 0x88155585 Qm (i32)0x00018196 +vrsra.s64 q9, q12, #11 :: Qd 0x1521dec2 0xb960c462 0x131f9fa0 0x77838405 Qm (i32)0x00018196 +---- VSHR ---- +vshr.s8 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshr.s8 q0, q1, #0 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xffffffff +vshr.s8 q0, q1, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshr.s8 q0, q1, #1 :: Qd 0x13161615 0x12151715 0x12161515 0x11171717 Qm (i32)0xffffffff +vshr.s16 q3, q4, #2 :: Qd 0xffffffe1 0xffffffe1 0xffffffe1 0xffffffe1 Qm (i32)0xffffff84 +vshr.s16 q3, q4, #2 :: Qd 0x098b0b4a 0x094a0b8a 0x090b0aca 0x08cb0b8b Qm (i32)0xffffff84 +vshr.s32 q2, q5, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshr.s32 q2, q5, #31 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff +vshr.s8 q6, q7, #7 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x0000ffff +vshr.s8 q6, q7, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000ffff +vshr.s16 q8, q9, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffff6 +vshr.s16 q8, q9, #12 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i32)0xfffffff6 +vshr.s32 q10, q11, #5 :: Qd 0x0000013f 0x0000013f 0x0000013f 0x0000013f Qm (i32)0x000027fa +vshr.s32 q10, q11, #5 :: Qd 0x01316969 0x01295171 0x01216159 0x01197971 Qm (i32)0x000027fa +vshr.u8 q12, q13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff +vshr.u8 q12, q13, #1 :: Qd 0x13161615 0x12151715 0x12161515 0x11171717 Qm (i32)0xffffffff +vshr.u16 q14, q15, #11 :: Qd 0x001f001f 0x001f001f 0x001f001f 0x001f001f Qm (i32)0xffffffff +vshr.u16 q14, q15, #11 :: Qd 0x00040005 0x00040005 0x00040005 0x00040005 Qm (i32)0xffffffff +vshr.u32 q10, q11, #9 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x000003e8 +vshr.u32 q10, q11, #9 :: Qd 0x00131696 0x00129517 0x00121615 0x00119797 Qm (i32)0x000003e8 +vshr.u8 q7, q13, #7 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101 Qm (i32)0xffffffff +vshr.u8 q7, q13, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff +vshr.u16 q8, q1, #5 :: Qd 0x0000055e 0x0000055e 0x0000055e 0x0000055e Qm (i32)0x0000abcf +vshr.u16 q8, q1, #5 :: Qd 0x01310169 0x01290171 0x01210159 0x01190171 Qm (i32)0x0000abcf +vshr.u32 q12, q3, #15 :: Qd 0x0001ffff 0x0001ffff 0x0001ffff 0x0001ffff Qm (i32)0xfffffe50 +vshr.u32 q12, q3, #15 :: Qd 0x00004c5a 0x00004a54 0x00004858 0x0000465e Qm (i32)0xfffffe50 +vshr.u64 q0, q1, #42 :: Qd 0x00000000 0x003fffff 0x00000000 0x003fffff Qm (i32)0xffffffff +vshr.u64 q0, q1, #42 :: Qd 0x00000000 0x00098b4b 0x00000000 0x00090b0a Qm (i32)0xffffffff +vshr.s64 q6, q7, #12 :: Qd 0x00000000 0xfac00000 0x00000000 0xfac00000 Qm (i32)0x00000fac +vshr.s64 q6, q7, #12 :: Qd 0x000262d2 0xd2a252a2 0x000242c2 0xb2b232f2 Qm (i32)0x00000fac +vshr.u64 q8, q4, #9 :: Qd 0x0000001a 0x7c00001a 0x0000001a 0x7c00001a Qm (i32)0x000034f8 +vshr.u64 q8, q4, #9 :: Qd 0x00131696 0x95129517 0x00121615 0x95919797 Qm (i32)0x000034f8 +vshr.s64 q9, q12, #11 :: Qd 0x00000030 0x32c00030 0x00000030 0x32c00030 Qm (i32)0x00018196 +vshr.s64 q9, q12, #11 :: Qd 0x0004c5a5 0xa544a545 0x00048585 0x656465e5 Qm (i32)0x00018196 +---- VSRA ---- +vsra.s8 q0, q1, #1 :: Qd 0x54545454 0x54545454 0x54545454 0x54545454 Qm (i32)0xffffffff +vsra.s8 q0, q1, #1 :: Qd 0x28332f32 0x26313631 0x25312f30 0x23363536 Qm (i32)0xffffffff +vsra.s16 q3, q4, #2 :: Qd 0x55545536 0x55545536 0x55545536 0x55545536 Qm (i32)0xffffff84 +vsra.s16 q3, q4, #2 :: Qd 0x1ea82467 0x1d662aa6 0x1c2624e5 0x1aea29aa Qm (i32)0xffffff84 +vsra.s32 q2, q5, #31 :: Qd 0x55555554 0x55555554 0x55555554 0x55555554 Qm (i32)0xffffffff +vsra.s32 q2, q5, #31 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff +vsra.s8 q6, q7, #7 :: Qd 0x55555454 0x55555454 0x55555454 0x55555454 Qm (i32)0x0000ffff +vsra.s8 q6, q7, #7 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x0000ffff +vsra.s16 q8, q9, #12 :: Qd 0x55545554 0x55545554 0x55545554 0x55545554 Qm (i32)0xfffffff6 +vsra.s16 q8, q9, #12 :: Qd 0x151f191f 0x141e1f1e 0x131d1a1d 0x12211e21 Qm (i32)0xfffffff6 +vsra.s32 q10, q11, #5 :: Qd 0x55555694 0x55555694 0x55555694 0x55555694 Qm (i32)0x000027fa +vsra.s32 q10, q11, #5 :: Qd 0x164e8286 0x1545708d 0x143c7b74 0x13389790 Qm (i32)0x000027fa +vsra.u8 q12, q13, #1 :: Qd 0xd4d4d4d4 0xd4d4d4d4 0xd4d4d4d4 0xd4d4d4d4 Qm (i32)0xffffffff +vsra.u8 q12, q13, #1 :: Qd 0x28332f32 0x26313631 0x25312f30 0x23363536 Qm (i32)0xffffffff +vsra.u16 q14, q15, #11 :: Qd 0x55745574 0x55745574 0x55745574 0x55745574 Qm (i32)0xffffffff +vsra.u16 q14, q15, #11 :: Qd 0x15211922 0x14201f21 0x131f1a20 0x12231e24 Qm (i32)0xffffffff +vsra.u32 q10, q11, #9 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x000003e8 +vsra.u32 q10, q11, #9 :: Qd 0x15302fb3 0x142eb433 0x132d3030 0x1230b5b6 Qm (i32)0x000003e8 +vsra.u8 q7, q13, #7 :: Qd 0x56565656 0x56565656 0x56565656 0x56565656 Qm (i32)0xffffffff +vsra.u8 q7, q13, #7 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff +vsra.u16 q8, q1, #5 :: Qd 0x55555ab3 0x55555ab3 0x55555ab3 0x55555ab3 Qm (i32)0x0000abcf +vsra.u16 q8, q1, #5 :: Qd 0x164e1a86 0x1545208d 0x143c1b74 0x13381f90 Qm (i32)0x0000abcf +vsra.u32 q12, q3, #15 :: Qd 0x55575554 0x55575554 0x55575554 0x55575554 Qm (i32)0xfffffe50 +vsra.u32 q12, q3, #15 :: Qd 0x151d6577 0x141c6970 0x131b6273 0x121f647d Qm (i32)0xfffffe50 +vsra.u64 q0, q1, #42 :: Qd 0x55555555 0x55955554 0x55555555 0x55955554 Qm (i32)0xffffffff +vsra.u64 q0, q1, #42 :: Qd 0x151d191d 0x1425aa67 0x131b1a1b 0x12282929 Qm (i32)0xffffffff +vsra.s64 q6, q7, #12 :: Qd 0x55555556 0x50155555 0x55555556 0x50155555 Qm (i32)0x00000fac +vsra.s64 q6, q7, #12 :: Qd 0x151f7bef 0xe6be71be 0x131d5cdd 0xc4d15111 Qm (i32)0x00000fac +vsra.u64 q8, q4, #9 :: Qd 0x5555556f 0xd155556f 0x5555556f 0xd155556f Qm (i32)0x000034f8 +vsra.u64 q8, q4, #9 :: Qd 0x15302fb3 0xa92eb433 0x132d3030 0xa7b0b5b6 Qm (i32)0x000034f8 +vsra.s64 q9, q12, #11 :: Qd 0x55555585 0x88155585 0x55555585 0x88155585 Qm (i32)0x00018196 +vsra.s64 q9, q12, #11 :: Qd 0x1521dec2 0xb960c461 0x131f9fa0 0x77838404 Qm (i32)0x00018196 +---- VSRI ---- +vsri.16 q0, q1, #1 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff +vsri.16 q0, q1, #1 :: Qd 0x13161695 0x12951715 0x12161595 0x11971717 Qm (i32)0xffffffff +vsri.16 q3, q4, #2 :: Qd 0x7fff7fe1 0x7fff7fe1 0x7fff7fe1 0x7fff7fe1 Qm (i32)0xffffff84 +vsri.16 q3, q4, #2 :: Qd 0x098b0b4a 0x094a0b8a 0x090b0aca 0x08cb0b8b Qm (i32)0xffffff84 +vsri.32 q2, q5, #31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xffffffff +vsri.32 q2, q5, #31 :: Qd 0x151d191c 0x141c1f1c 0x131b1a1a 0x121f1e1e Qm (i32)0xffffffff +vsri.8 q6, q7, #7 :: Qd 0x54545555 0x54545555 0x54545555 0x54545555 Qm (i32)0x0000ffff +vsri.8 q6, q7, #7 :: Qd 0x141c181c 0x141c1e1c 0x121a1a1a 0x121e1e1e Qm (i32)0x0000ffff +vsri.16 q8, q9, #12 :: Qd 0x555f555f 0x555f555f 0x555f555f 0x555f555f Qm (i32)0xfffffff6 +vsri.16 q8, q9, #12 :: Qd 0x15121912 0x14121f12 0x13121a12 0x12121e12 Qm (i32)0xfffffff6 +vsri.32 q10, q11, #5 :: Qd 0x5000013f 0x5000013f 0x5000013f 0x5000013f Qm (i32)0x000027fa +vsri.32 q10, q11, #5 :: Qd 0x11316969 0x11295171 0x11216159 0x11197971 Qm (i32)0x000027fa +vsri.8 q12, q13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff +vsri.8 q12, q13, #1 :: Qd 0x13161615 0x12151715 0x12161515 0x11171717 Qm (i32)0xffffffff +vsri.16 q14, q15, #11 :: Qd 0x555f555f 0x555f555f 0x555f555f 0x555f555f Qm (i32)0xffffffff +vsri.16 q14, q15, #11 :: Qd 0x15041905 0x14041f05 0x13041a05 0x12041e05 Qm (i32)0xffffffff +vsri.32 q10, q11, #9 :: Qd 0x55000001 0x55000001 0x55000001 0x55000001 Qm (i32)0x000003e8 +vsri.32 q10, q11, #9 :: Qd 0x15131696 0x14129517 0x13121615 0x12119797 Qm (i32)0x000003e8 +vsri.8 q7, q13, #7 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xffffffff +vsri.8 q7, q13, #7 :: Qd 0x141c181c 0x141c1e1c 0x121a1a1a 0x121e1e1e Qm (i32)0xffffffff +vsri.16 q8, q1, #5 :: Qd 0x5000555e 0x5000555e 0x5000555e 0x5000555e Qm (i32)0x0000abcf +vsri.16 q8, q1, #5 :: Qd 0x11311969 0x11291971 0x11211959 0x11191971 Qm (i32)0x0000abcf +vsri.32 q12, q3, #15 :: Qd 0x5555ffff 0x5555ffff 0x5555ffff 0x5555ffff Qm (i32)0xfffffe50 +vsri.32 q12, q3, #15 :: Qd 0x151c4c5a 0x141c4a54 0x131a4858 0x121e465e Qm (i32)0xfffffe50 +vsri.64 q0, q1, #42 :: Qd 0x55555555 0x557fffff 0x55555555 0x557fffff Qm (i32)0xffffffff +vsri.64 q0, q1, #42 :: Qd 0x151d191d 0x14098b4b 0x131b1a1b 0x12090b0a Qm (i32)0xffffffff +vsri.64 q6, q7, #12 :: Qd 0x55500000 0xfac00000 0x55500000 0xfac00000 Qm (i32)0x00000fac +vsri.64 q6, q7, #12 :: Qd 0x151262d2 0xd2a252a2 0x131242c2 0xb2b232f2 Qm (i32)0x00000fac +vsri.64 q8, q4, #9 :: Qd 0x5500001a 0x7c00001a 0x5500001a 0x7c00001a Qm (i32)0x000034f8 +vsri.64 q8, q4, #9 :: Qd 0x15131696 0x95129517 0x13121615 0x95919797 Qm (i32)0x000034f8 +vsri.64 q9, q12, #11 :: Qd 0x55400030 0x32c00030 0x55400030 0x32c00030 Qm (i32)0x00018196 +vsri.64 q9, q12, #11 :: Qd 0x1504c5a5 0xa544a545 0x13048585 0x656465e5 Qm (i32)0x00018196 +---- VMOVL ---- +vmovl.u32 q0, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042 Qm (i32)0x00000042 +vmovl.u32 q0, d2 :: Qd 0x00000000 0x242c2b2b 0x00000000 0x232f2e2f Qm (i32)0x00000042 +vmovl.u16 q15, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042 Qm (i32)0x00000042 +vmovl.u16 q15, d2 :: Qd 0x0000242c 0x00002b2b 0x0000232f 0x00002e2f Qm (i32)0x00000042 +vmovl.u8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000042 +vmovl.u8 q3, d31 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x00000042 +vmovl.s32 q0, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042 Qm (i32)0x00000042 +vmovl.s32 q0, d2 :: Qd 0x00000000 0x242c2b2b 0x00000000 0x232f2e2f Qm (i32)0x00000042 +vmovl.s16 q15, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042 Qm (i32)0x00000042 +vmovl.s16 q15, d2 :: Qd 0x0000242c 0x00002b2b 0x0000232f 0x00002e2f Qm (i32)0x00000042 +vmovl.s8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000042 +vmovl.s8 q3, d31 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x00000042 +vmovl.u32 q0, d2 :: Qd 0x00000000 0xedededed 0x00000000 0xedededed Qm (i8)0x000000ed +vmovl.u32 q0, d2 :: Qd 0x00000000 0x242c2b2b 0x00000000 0x232f2e2f Qm (i8)0x000000ed +vmovl.u16 q15, d2 :: Qd 0x0000eded 0x0000eded 0x0000eded 0x0000eded Qm (i8)0x000000ed +vmovl.u16 q15, d2 :: Qd 0x0000242c 0x00002b2b 0x0000232f 0x00002e2f Qm (i8)0x000000ed +vmovl.u8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i8)0x000000ed +vmovl.u8 q3, d31 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i8)0x000000ed +vmovl.s32 q0, d2 :: Qd 0xffffffff 0xedededed 0xffffffff 0xedededed Qm (i8)0x000000ed +vmovl.s32 q0, d2 :: Qd 0x00000000 0x242c2b2b 0x00000000 0x232f2e2f Qm (i8)0x000000ed +vmovl.s16 q15, d2 :: Qd 0xffffeded 0xffffeded 0xffffeded 0xffffeded Qm (i8)0x000000ed +vmovl.s16 q15, d2 :: Qd 0x0000242c 0x00002b2b 0x0000232f 0x00002e2f Qm (i8)0x000000ed +vmovl.s8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i8)0x000000ed +vmovl.s8 q3, d31 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i8)0x000000ed +---- VABS ---- +vabs.s32 q0, q1 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 +vabs.s32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000073 +vabs.s16 q15, q4 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 +vabs.s16 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000073 +vabs.s8 q8, q7 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 +vabs.s8 q8, q7 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000073 +vabs.s32 q0, q1 :: Qd 0x000000fe 0x000000fe 0x000000fe 0x000000fe Qm (i32)0x000000fe +vabs.s32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x000000fe +vabs.s16 q15, q4 :: Qd 0x000000ef 0x000000ef 0x000000ef 0x000000ef Qm (i32)0x000000ef +vabs.s16 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x000000ef +vabs.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022 Qm (i32)0x000000de +vabs.s8 q8, q7 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x000000de +vabs.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a +vabs.s32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i16)0x0000fe0a +vabs.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b +vabs.s16 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i16)0x0000ef0b +vabs.s8 q8, q7 :: Qd 0x220c220c 0x220c220c 0x220c220c 0x220c220c Qm (i16)0x0000de0c +vabs.s8 q8, q7 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i16)0x0000de0c +---- VQABS ---- +vqabs.s32 q0, q1 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr: 00000000 +vqabs.s32 q0, q1 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x00000073 fpscr: 00000000 +vqabs.s32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 fpscr: 08000000 +vqabs.s32 q0, q1 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x80000000 fpscr: 00000000 +vqabs.s16 q0, q1 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 fpscr: 08000000 +vqabs.s16 q0, q1 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x80000000 fpscr: 00000000 +vqabs.s8 q0, q1 :: Qd 0x7f000000 0x7f000000 0x7f000000 0x7f000000 Qm (i32)0x80000000 fpscr: 08000000 +vqabs.s8 q0, q1 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x80000000 fpscr: 00000000 +vqabs.s16 q15, q4 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr: 00000000 +vqabs.s16 q15, q4 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x00000073 fpscr: 00000000 +vqabs.s8 q8, q7 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr: 00000000 +vqabs.s8 q8, q7 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x00000073 fpscr: 00000000 +vqabs.s32 q0, q1 :: Qd 0x000000fe 0x000000fe 0x000000fe 0x000000fe Qm (i32)0x000000fe fpscr: 00000000 +vqabs.s32 q0, q1 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x000000fe fpscr: 00000000 +vqabs.s16 q15, q4 :: Qd 0x000000ef 0x000000ef 0x000000ef 0x000000ef Qm (i32)0x000000ef fpscr: 00000000 +vqabs.s16 q15, q4 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x000000ef fpscr: 00000000 +vqabs.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022 Qm (i32)0x000000de fpscr: 00000000 +vqabs.s8 q8, q7 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0x000000de fpscr: 00000000 +vqabs.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a fpscr: 00000000 +vqabs.s32 q0, q1 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i16)0x0000fe0a fpscr: 00000000 +vqabs.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b fpscr: 00000000 +vqabs.s16 q15, q4 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i16)0x0000ef0b fpscr: 00000000 +vqabs.s8 q8, q7 :: Qd 0x220c220c 0x220c220c 0x220c220c 0x220c220c Qm (i16)0x0000de0c fpscr: 00000000 +vqabs.s8 q8, q7 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i16)0x0000de0c fpscr: 00000000 +---- VADDW ---- +vaddw.s32 q0, q1, d4 :: Qd 0x00000073 0x12121285 0x00000073 0x12121285 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddw.s16 q15, q14, d4 :: Qd 0x00001285 0x00001285 0x00001285 0x00001285 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddw.s8 q0, q1, d31 :: Qd 0x00120085 0x00120085 0x00120085 0x00120085 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddw.u32 q0, q1, d4 :: Qd 0x00000073 0x12121285 0x00000073 0x12121285 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddw.u16 q0, q1, d4 :: Qd 0x00001285 0x00001285 0x00001285 0x00001285 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddw.u8 q0, q1, d4 :: Qd 0x00120085 0x00120085 0x00120085 0x00120085 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddw.s32 q0, q1, d4 :: Qd 0x00000072 0xe2e2e355 0x00000072 0xe2e2e355 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddw.s16 q15, q14, d4 :: Qd 0xffffe355 0xffffe355 0xffffe355 0xffffe355 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddw.s8 q0, q1, d31 :: Qd 0xffe20055 0xffe20055 0xffe20055 0xffe20055 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddw.u32 q0, q1, d4 :: Qd 0x00000073 0xe2e2e355 0x00000073 0xe2e2e355 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddw.u16 q0, q1, d4 :: Qd 0x0000e355 0x0000e355 0x0000e355 0x0000e355 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddw.u8 q0, q1, d4 :: Qd 0x00e20155 0x00e20155 0x00e20155 0x00e20155 Qm (i32)0x00000073 Qn (i8)0x000000e2 +---- VADDL ---- +vaddl.s32 q0, d2, d4 :: Qd 0x00000000 0x12121285 0x00000000 0x12121285 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddl.s16 q15, d14, d4 :: Qd 0x00001212 0x00001285 0x00001212 0x00001285 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddl.s8 q0, d2, d31 :: Qd 0x00120012 0x00120085 0x00120012 0x00120085 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0x12121285 0x00000000 0x12121285 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddl.u16 q0, d2, d4 :: Qd 0x00001212 0x00001285 0x00001212 0x00001285 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddl.u8 q0, d2, d4 :: Qd 0x00120012 0x00120085 0x00120012 0x00120085 Qm (i32)0x00000073 Qn (i8)0x00000012 +vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0xe2e2e355 0xffffffff 0xe2e2e355 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddl.s16 q15, d14, d4 :: Qd 0xffffe2e2 0xffffe355 0xffffe2e2 0xffffe355 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddl.s8 q0, d2, d31 :: Qd 0xffe2ffe2 0xffe20055 0xffe2ffe2 0xffe20055 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0xe2e2e355 0x00000000 0xe2e2e355 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddl.u16 q0, d2, d4 :: Qd 0x0000e2e2 0x0000e355 0x0000e2e2 0x0000e355 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddl.u8 q0, d2, d4 :: Qd 0x00e200e2 0x00e20155 0x00e200e2 0x00e20155 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0xa5a5a5a5 0xffffffff 0xa5a5a5a5 Qm (i8)0x00000093 Qn (i8)0x00000012 +vaddl.s16 q15, d14, d4 :: Qd 0xffffa5a5 0xffffa5a5 0xffffa5a5 0xffffa5a5 Qm (i8)0x00000093 Qn (i8)0x00000012 +vaddl.s8 q0, d2, d31 :: Qd 0xffabffab 0xffabffab 0xffabffab 0xffabffab Qm (i8)0x00000099 Qn (i8)0x00000012 +vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0xa5a5a5a5 0x00000000 0xa5a5a5a5 Qm (i8)0x00000093 Qn (i8)0x00000012 +vaddl.u16 q0, d2, d4 :: Qd 0x0000a5a5 0x0000a5a5 0x0000a5a5 0x0000a5a5 Qm (i8)0x00000093 Qn (i8)0x00000012 +vaddl.u8 q0, d2, d4 :: Qd 0x00a500a5 0x00a500a5 0x00a500a5 0x00a500a5 Qm (i8)0x00000093 Qn (i8)0x00000012 +vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0x76767675 0xffffffff 0x76767675 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vaddl.s16 q15, d14, d4 :: Qd 0xffff7675 0xffff7675 0xffff7675 0xffff7675 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vaddl.s8 q0, d2, d31 :: Qd 0xff75ff75 0xff75ff75 0xff75ff75 0xff75ff75 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vaddl.u32 q0, d2, d4 :: Qd 0x00000001 0x76767675 0x00000001 0x76767675 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vaddl.u16 q0, d2, d4 :: Qd 0x00017675 0x00017675 0x00017675 0x00017675 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vaddl.u8 q0, d2, d4 :: Qd 0x01750175 0x01750175 0x01750175 0x01750175 Qm (i8)0x00000093 Qn (i8)0x000000e2 +---- VSUBW ---- +vsubw.s32 q0, q1, d4 :: Qd 0x00000072 0xededee61 0x00000072 0xededee61 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubw.s16 q15, q14, d4 :: Qd 0xffffee61 0xffffee61 0xffffee61 0xffffee61 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubw.s8 q0, q1, d31 :: Qd 0xffee0061 0xffee0061 0xffee0061 0xffee0061 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubw.u32 q0, q1, d4 :: Qd 0x00000072 0xededee61 0x00000072 0xededee61 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubw.u16 q0, q1, d4 :: Qd 0xffffee61 0xffffee61 0xffffee61 0xffffee61 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubw.u8 q0, q1, d4 :: Qd 0xffee0061 0xffee0061 0xffee0061 0xffee0061 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubw.s32 q0, q1, d4 :: Qd 0x00000073 0x1d1d1d91 0x00000073 0x1d1d1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubw.s16 q15, q14, d4 :: Qd 0x00001d91 0x00001d91 0x00001d91 0x00001d91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubw.s8 q0, q1, d31 :: Qd 0x001e0091 0x001e0091 0x001e0091 0x001e0091 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubw.u32 q0, q1, d4 :: Qd 0x00000072 0x1d1d1d91 0x00000072 0x1d1d1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubw.u16 q0, q1, d4 :: Qd 0xffff1d91 0xffff1d91 0xffff1d91 0xffff1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubw.u8 q0, q1, d4 :: Qd 0xff1eff91 0xff1eff91 0xff1eff91 0xff1eff91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +---- VSUBL ---- +vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0xededee61 0xffffffff 0xededee61 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubl.s16 q15, d14, d4 :: Qd 0xffffedee 0xffffee61 0xffffedee 0xffffee61 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubl.s8 q0, d2, d31 :: Qd 0xffeeffee 0xffee0061 0xffeeffee 0xffee0061 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0xededee61 0xffffffff 0xededee61 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubl.u16 q0, d2, d4 :: Qd 0xffffedee 0xffffee61 0xffffedee 0xffffee61 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubl.u8 q0, d2, d4 :: Qd 0xffeeffee 0xffee0061 0xffeeffee 0xffee0061 Qm (i32)0x00000073 Qn (i8)0x00000012 +vsubl.s32 q0, d2, d4 :: Qd 0x00000000 0x1d1d1d91 0x00000000 0x1d1d1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubl.s16 q15, d14, d4 :: Qd 0x00001d1e 0x00001d91 0x00001d1e 0x00001d91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubl.s8 q0, d2, d31 :: Qd 0x001e001e 0x001e0091 0x001e001e 0x001e0091 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0x1d1d1d91 0xffffffff 0x1d1d1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubl.u16 q0, d2, d4 :: Qd 0xffff1d1e 0xffff1d91 0xffff1d1e 0xffff1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubl.u8 q0, d2, d4 :: Qd 0xff1eff1e 0xff1eff91 0xff1eff1e 0xff1eff91 Qm (i32)0x00000073 Qn (i8)0x000000e2 +vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0x81818181 0xffffffff 0x81818181 Qm (i8)0x00000093 Qn (i8)0x00000012 +vsubl.s16 q15, d14, d4 :: Qd 0xffff8181 0xffff8181 0xffff8181 0xffff8181 Qm (i8)0x00000093 Qn (i8)0x00000012 +vsubl.s8 q0, d2, d31 :: Qd 0xff87ff87 0xff87ff87 0xff87ff87 0xff87ff87 Qm (i8)0x00000099 Qn (i8)0x00000012 +vsubl.u32 q0, d2, d4 :: Qd 0x00000000 0x81818181 0x00000000 0x81818181 Qm (i8)0x00000093 Qn (i8)0x00000012 +vsubl.u16 q0, d2, d4 :: Qd 0x00008181 0x00008181 0x00008181 0x00008181 Qm (i8)0x00000093 Qn (i8)0x00000012 +vsubl.u8 q0, d2, d4 :: Qd 0x00810081 0x00810081 0x00810081 0x00810081 Qm (i8)0x00000093 Qn (i8)0x00000012 +vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0xb0b0b0b1 0xffffffff 0xb0b0b0b1 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vsubl.s16 q15, d14, d4 :: Qd 0xffffb0b1 0xffffb0b1 0xffffb0b1 0xffffb0b1 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vsubl.s8 q0, d2, d31 :: Qd 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0xb0b0b0b1 0xffffffff 0xb0b0b0b1 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vsubl.u16 q0, d2, d4 :: Qd 0xffffb0b1 0xffffb0b1 0xffffb0b1 0xffffb0b1 Qm (i8)0x00000093 Qn (i8)0x000000e2 +vsubl.u8 q0, d2, d4 :: Qd 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 Qm (i8)0x00000093 Qn (i8)0x000000e2 +---- VCEQ #0 ---- +vceq.i32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vceq.i32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vceq.i16 q2, q1, #0 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000021 +vceq.i16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vceq.i8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x00000021 +vceq.i8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vceq.i32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.i32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vceq.i16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.i16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vceq.i8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.i8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +---- VCGT #0 ---- +vcgt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcgt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcgt.s16 q2, q1, #0 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000021 +vcgt.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcgt.s8 q10, q11, #0 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000021 +vcgt.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcgt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ef +vcgt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ef +vcgt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ed +vcgt.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ed +vcgt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ae +vcgt.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ae +---- VCGE #0 ---- +vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ef +vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ef +vcge.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ed +vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ed +vcge.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ae +vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ae +vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x000000ef +vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x000000ef +vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x000000ed +vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x000000ed +vcge.s8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x000000ae +vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x000000ae +---- VCLE #0 ---- +vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vcle.s16 q2, q1, #0 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000021 +vcle.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vcle.s8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x00000021 +vcle.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vcle.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ef +vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ef +vcle.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ed +vcle.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ed +vcle.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ae +vcle.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ae +---- VCLT #0 ---- +vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ef +vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ef +vclt.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ed +vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ed +vclt.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ae +vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ae +vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000000ef +vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000000ef +vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000000ed +vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000000ed +vclt.s8 q10, q11, #0 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x000000ae +vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000000ae +---- VCNT ---- +vcnt.8 q0, q1 :: Qd 0x04050306 0x04050306 0x04050306 0x04050306 Qm (i32)0xac3d25eb +vcnt.8 q0, q1 :: Qd 0x03040403 0x03030404 0x02030404 0x03050405 Qm (i32)0xac3d25eb +vcnt.8 q11, q14 :: Qd 0x04050306 0x04050306 0x04050306 0x04050306 Qm (i32)0xac3d25eb +vcnt.8 q11, q14 :: Qd 0x03040403 0x03030404 0x02030404 0x03050405 Qm (i32)0xac3d25eb +vcnt.8 q6, q2 :: Qd 0x00020306 0x00020306 0x00020306 0x00020306 Qm (i32)0x000ad0eb +vcnt.8 q6, q2 :: Qd 0x03040403 0x03030404 0x02030404 0x03050405 Qm (i32)0x000ad0eb +---- VCLS ---- +vcls.s8 q0, q1 :: Qd 0x07070701 0x07070701 0x07070701 0x07070701 Qm (i32)0x00000021 +vcls.s8 q0, q1 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101 Qm (i32)0x00000021 +vcls.s8 q10, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082 +vcls.s8 q10, q15 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101 Qm (i8)0x00000082 +vcls.s16 q0, q1 :: Qd 0x000f0009 0x000f0009 0x000f0009 0x000f0009 Qm (i32)0x00000021 +vcls.s16 q0, q1 :: Qd 0x00010001 0x00010001 0x00010001 0x00010001 Qm (i32)0x00000021 +vcls.s16 q15, q10 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082 +vcls.s16 q15, q10 :: Qd 0x00010001 0x00010001 0x00010001 0x00010001 Qm (i8)0x00000082 +vcls.s32 q6, q1 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019 Qm (i32)0x00000021 +vcls.s32 q6, q1 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x00000021 +vcls.s32 q10, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082 +vcls.s32 q10, q5 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i8)0x00000082 +vcls.s8 q2, q4 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 Qm (i8)0x000000ff +vcls.s8 q2, q4 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101 Qm (i8)0x000000ff +vcls.s16 q2, q4 :: Qd 0x000f000f 0x000f000f 0x000f000f 0x000f000f Qm (i8)0x000000ff +vcls.s16 q2, q4 :: Qd 0x00010001 0x00010001 0x00010001 0x00010001 Qm (i8)0x000000ff +vcls.s32 q2, q4 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f Qm (i8)0x000000ff +vcls.s32 q2, q4 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i8)0x000000ff +vcls.s8 q2, q4 :: Qd 0x07020702 0x07020702 0x07020702 0x07020702 Qm (i16)0x0000ffef +vcls.s8 q2, q4 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101 Qm (i16)0x0000ffef +vcls.s16 q2, q4 :: Qd 0x000a000a 0x000a000a 0x000a000a 0x000a000a Qm (i16)0x0000ffef +vcls.s16 q2, q4 :: Qd 0x00010001 0x00010001 0x00010001 0x00010001 Qm (i16)0x0000ffef +vcls.s32 q2, q4 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i16)0x0000ffef +vcls.s32 q2, q4 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i16)0x0000ffef +vcls.s8 q2, q4 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 Qm (i8)0x00000000 +vcls.s8 q2, q4 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101 Qm (i8)0x00000000 +vcls.s16 q2, q4 :: Qd 0x000f000f 0x000f000f 0x000f000f 0x000f000f Qm (i8)0x00000000 +vcls.s16 q2, q4 :: Qd 0x00010001 0x00010001 0x00010001 0x00010001 Qm (i8)0x00000000 +vcls.s32 q2, q4 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f Qm (i8)0x00000000 +vcls.s32 q2, q4 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i8)0x00000000 +vcls.s8 q2, q4 :: Qd 0x07020702 0x07020702 0x07020702 0x07020702 Qm (i16)0x000000ef +vcls.s8 q2, q4 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101 Qm (i16)0x000000ef +vcls.s16 q2, q4 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007 Qm (i16)0x000000ef +vcls.s16 q2, q4 :: Qd 0x00010001 0x00010001 0x00010001 0x00010001 Qm (i16)0x000000ef +vcls.s32 q2, q4 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i16)0x000000ef +vcls.s32 q2, q4 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i16)0x000000ef +---- VCLZ ---- +vclz.i8 q0, q1 :: Qd 0x08080802 0x08080802 0x08080802 0x08080802 Qm (i32)0x00000021 +vclz.i8 q0, q1 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i32)0x00000021 +vclz.i8 q10, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082 +vclz.i8 q10, q15 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i8)0x00000082 +vclz.i16 q0, q1 :: Qd 0x0010000a 0x0010000a 0x0010000a 0x0010000a Qm (i32)0x00000021 +vclz.i16 q0, q1 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i32)0x00000021 +vclz.i16 q15, q10 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082 +vclz.i16 q15, q10 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i8)0x00000082 +vclz.i32 q6, q1 :: Qd 0x0000001a 0x0000001a 0x0000001a 0x0000001a Qm (i32)0x00000021 +vclz.i32 q6, q1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000021 +vclz.i32 q10, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082 +vclz.i32 q10, q5 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i8)0x00000082 +vclz.i8 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff +vclz.i8 q2, q4 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i8)0x000000ff +vclz.i16 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff +vclz.i16 q2, q4 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i8)0x000000ff +vclz.i32 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff +vclz.i32 q2, q4 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i8)0x000000ff +vclz.i8 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i16)0x0000ffef +vclz.i8 q2, q4 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i16)0x0000ffef +vclz.i16 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i16)0x0000ffef +vclz.i16 q2, q4 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i16)0x0000ffef +vclz.i32 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i16)0x0000ffef +vclz.i32 q2, q4 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i16)0x0000ffef +vclz.i8 q2, q4 :: Qd 0x08080808 0x08080808 0x08080808 0x08080808 Qm (i8)0x00000000 +vclz.i8 q2, q4 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i8)0x00000000 +vclz.i16 q2, q4 :: Qd 0x00100010 0x00100010 0x00100010 0x00100010 Qm (i8)0x00000000 +vclz.i16 q2, q4 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i8)0x00000000 +vclz.i32 q2, q4 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020 Qm (i8)0x00000000 +vclz.i32 q2, q4 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i8)0x00000000 +vclz.i8 q2, q4 :: Qd 0x08000800 0x08000800 0x08000800 0x08000800 Qm (i16)0x000000ef +vclz.i8 q2, q4 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i16)0x000000ef +vclz.i16 q2, q4 :: Qd 0x00080008 0x00080008 0x00080008 0x00080008 Qm (i16)0x000000ef +vclz.i16 q2, q4 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i16)0x000000ef +vclz.i32 q2, q4 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i16)0x000000ef +vclz.i32 q2, q4 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i16)0x000000ef +---- VSLI ---- +vsli.16 q0, q1, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff +vsli.16 q0, q1, #1 :: Qd 0x4c5b5a55 0x4a545c56 0x48595657 0x465f5c5f Qm (i32)0xffffffff +vsli.16 q3, q4, #2 :: Qd 0xfffdfe11 0xfffdfe11 0xfffdfe11 0xfffdfe11 Qm (i32)0xffffff84 +vsli.16 q3, q4, #2 :: Qd 0x98b5b4a9 0x94a8b8ac 0x90b3acaf 0x8cbfb8bf Qm (i32)0xffffff84 +vsli.32 q2, q5, #31 :: Qd 0xd5555555 0xd5555555 0xd5555555 0xd5555555 Qm (i32)0xffffffff +vsli.32 q2, q5, #31 :: Qd 0x151d191d 0x941c1f1c 0x931b1a1b 0x921f1e1f Qm (i32)0xffffffff +vsli.8 q6, q7, #7 :: Qd 0x5555d5d5 0x5555d5d5 0x5555d5d5 0x5555d5d5 Qm (i32)0x0000ffff +vsli.8 q6, q7, #7 :: Qd 0x159d991d 0x941c1f9c 0x131b9a9b 0x929f1e9f Qm (i32)0x0000ffff +vsli.16 q8, q9, #12 :: Qd 0xf5556555 0xf5556555 0xf5556555 0xf5556555 Qm (i32)0xfffffff6 +vsli.16 q8, q9, #12 :: Qd 0xd51da91d 0xa41cbf1c 0xc31bba1b 0xf21ffe1f Qm (i32)0xfffffff6 +vsli.32 q10, q11, #5 :: Qd 0x0004ff55 0x0004ff55 0x0004ff55 0x0004ff55 Qm (i32)0x000027fa +vsli.32 q10, q11, #5 :: Qd 0xc5a5a55d 0xa545c57c 0x8585657b 0x65e5c5ff Qm (i32)0x000027fa +vsli.8 q12, q13, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff +vsli.8 q12, q13, #1 :: Qd 0x4d5b5b55 0x4a545d56 0x49595657 0x465f5c5f Qm (i32)0xffffffff +vsli.16 q14, q15, #11 :: Qd 0xfd55fd55 0xfd55fd55 0xfd55fd55 0xfd55fd55 Qm (i32)0xffffffff +vsli.16 q14, q15, #11 :: Qd 0x6d1d511d 0x541c5f1c 0x631b5a1b 0x7a1f7e1f Qm (i32)0xffffffff +vsli.32 q10, q11, #9 :: Qd 0x0007d155 0x0007d155 0x0007d155 0x0007d155 Qm (i32)0x000003e8 +vsli.32 q10, q11, #9 :: Qd 0x5a5a551d 0x545c571c 0x5856561b 0x5e5c5e1f Qm (i32)0x000003e8 +vsli.8 q7, q13, #7 :: Qd 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 Qm (i32)0xffffffff +vsli.8 q7, q13, #7 :: Qd 0x159d991d 0x941c1f9c 0x131b9a9b 0x929f1e9f Qm (i32)0xffffffff +vsli.16 q8, q1, #1 :: Qd 0x0001579f 0x0001579f 0x0001579f 0x0001579f Qm (i32)0x0000abcf +vsli.16 q8, q1, #1 :: Qd 0x4c5b5a55 0x4a545c56 0x48595657 0x465f5c5f Qm (i32)0x0000abcf +vsli.32 q12, q3, #15 :: Qd 0xff285555 0xff285555 0xff285555 0xff285555 Qm (i32)0xfffffe50 +vsli.32 q12, q3, #15 :: Qd 0x9695191d 0x17159f1c 0x15959a1b 0x97179e1f Qm (i32)0xfffffe50 +vsli.64 q0, q1, #42 :: Qd 0xfffffd55 0x55555555 0xfffffd55 0x55555555 Qm (i32)0xffffffff +vsli.64 q0, q1, #42 :: Qd 0xa8b8ad1d 0x141c1f1c 0xbcb8be1b 0x121f1e1f Qm (i32)0xffffffff +vsli.64 q6, q7, #12 :: Qd 0x00fac000 0x00fac555 0x00fac000 0x00fac555 Qm (i32)0x00000fac +vsli.64 q6, q7, #12 :: Qd 0xd2d2a252 0xa2e2bf1c 0xc2b2b232 0xf2e2fe1f Qm (i32)0x00000fac +vsli.64 q8, q4, #9 :: Qd 0x0069f000 0x0069f155 0x0069f000 0x0069f155 Qm (i32)0x000034f8 +vsli.64 q8, q4, #9 :: Qd 0x5a5a544a 0x545c571c 0x58565646 0x5e5c5e1f Qm (i32)0x000034f8 +vsli.64 q9, q12, #11 :: Qd 0x0c0cb000 0x0c0cb555 0x0c0cb000 0x0c0cb555 Qm (i32)0x00018196 +vsli.64 q9, q12, #11 :: Qd 0x69695129 0x51715f1c 0x61595919 0x79717e1f Qm (i32)0x00018196 +---- VPADDL ---- +vpaddl.u32 q0, q1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018 +vpaddl.u32 q0, q1 :: Qd 0x00000000 0x4b575b55 0x00000000 0x475b595a Qm (i32)0x00000018 +vpaddl.u32 q0, q1 :: Qd 0x00000000 0x00000118 0x00000000 0x00000118 Qm (i32)0x0000008c +vpaddl.u32 q0, q1 :: Qd 0x00000000 0x4b575b55 0x00000000 0x475b595a Qm (i32)0x0000008c +vpaddl.u16 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c +vpaddl.u16 q0, q1 :: Qd 0x00005357 0x00005355 0x00004f57 0x0000515e Qm (i32)0x0000008c +vpaddl.u8 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c +vpaddl.u8 q0, q1 :: Qd 0x00530057 0x004f0059 0x00500056 0x0052005d Qm (i32)0x0000008c +vpaddl.u8 q0, q1 :: Qd 0x00800001 0x00800001 0x00800001 0x00800001 Qm (i32)0x80000001 +vpaddl.u8 q0, q1 :: Qd 0x00530057 0x004f0059 0x00500056 0x0052005d Qm (i32)0x80000001 +vpaddl.u16 q0, q1 :: Qd 0x00008001 0x00008001 0x00008001 0x00008001 Qm (i32)0x80000001 +vpaddl.u16 q0, q1 :: Qd 0x00005357 0x00005355 0x00004f57 0x0000515e Qm (i32)0x80000001 +vpaddl.u32 q0, q1 :: Qd 0x00000001 0x00000002 0x00000001 0x00000002 Qm (i32)0x80000001 +vpaddl.u32 q0, q1 :: Qd 0x00000000 0x4b575b55 0x00000000 0x475b595a Qm (i32)0x80000001 +vpaddl.u32 q10, q11 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018 +vpaddl.u32 q10, q11 :: Qd 0x00000000 0x4b575b55 0x00000000 0x475b595a Qm (i32)0x00000018 +vpaddl.s32 q0, q1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018 +vpaddl.s32 q0, q1 :: Qd 0x00000000 0x4b575b55 0x00000000 0x475b595a Qm (i32)0x00000018 +vpaddl.s32 q0, q1 :: Qd 0x00000000 0x00000118 0x00000000 0x00000118 Qm (i32)0x0000008c +vpaddl.s32 q0, q1 :: Qd 0x00000000 0x4b575b55 0x00000000 0x475b595a Qm (i32)0x0000008c +vpaddl.s16 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c +vpaddl.s16 q0, q1 :: Qd 0x00005357 0x00005355 0x00004f57 0x0000515e Qm (i32)0x0000008c +vpaddl.s8 q0, q1 :: Qd 0x0000ff8c 0x0000ff8c 0x0000ff8c 0x0000ff8c Qm (i32)0x0000008c +vpaddl.s8 q0, q1 :: Qd 0x00530057 0x004f0059 0x00500056 0x0052005d Qm (i32)0x0000008c +vpaddl.s8 q0, q1 :: Qd 0xff800001 0xff800001 0xff800001 0xff800001 Qm (i32)0x80000001 +vpaddl.s8 q0, q1 :: Qd 0x00530057 0x004f0059 0x00500056 0x0052005d Qm (i32)0x80000001 +vpaddl.s16 q0, q1 :: Qd 0xffff8001 0xffff8001 0xffff8001 0xffff8001 Qm (i32)0x80000001 +vpaddl.s16 q0, q1 :: Qd 0x00005357 0x00005355 0x00004f57 0x0000515e Qm (i32)0x80000001 +vpaddl.s32 q0, q1 :: Qd 0xffffffff 0x00000002 0xffffffff 0x00000002 Qm (i32)0x80000001 +vpaddl.s32 q0, q1 :: Qd 0x00000000 0x4b575b55 0x00000000 0x475b595a Qm (i32)0x80000001 +vpaddl.s32 q10, q11 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018 +vpaddl.s32 q10, q11 :: Qd 0x00000000 0x4b575b55 0x00000000 0x475b595a Qm (i32)0x00000018 +---- VPADAL ---- +vpadal.u32 q0, q1 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585 Qm (i32)0x00000018 +vpadal.u32 q0, q1 :: Qd 0x151d191d 0x5f737a71 0x131b1a1b 0x597a7779 Qm (i32)0x00000018 +vpadal.u32 q0, q1 :: Qd 0x55555555 0x5555566d 0x55555555 0x5555566d Qm (i32)0x0000008c +vpadal.u32 q0, q1 :: Qd 0x151d191d 0x5f737a71 0x131b1a1b 0x597a7779 Qm (i32)0x0000008c +vpadal.u16 q0, q1 :: Qd 0x555555e1 0x555555e1 0x555555e1 0x555555e1 Qm (i32)0x0000008c +vpadal.u16 q0, q1 :: Qd 0x151d6c74 0x141c7271 0x131b6972 0x121f6f7d Qm (i32)0x0000008c +vpadal.u8 q0, q1 :: Qd 0x566d566d 0x566d566d 0x566d566d 0x566d566d Qm (i8)0x0000008c +vpadal.u8 q0, q1 :: Qd 0x15701974 0x146b1f75 0x136b1a71 0x12711e7c Qm (i8)0x0000008c +vpadal.u8 q0, q1 :: Qd 0x55d55556 0x55d55556 0x55d55556 0x55d55556 Qm (i32)0x80000001 +vpadal.u8 q0, q1 :: Qd 0x15701974 0x146b1f75 0x136b1a71 0x12711e7c Qm (i32)0x80000001 +vpadal.u16 q0, q1 :: Qd 0x5555d556 0x5555d556 0x5555d556 0x5555d556 Qm (i32)0x80000001 +vpadal.u16 q0, q1 :: Qd 0x151d6c74 0x141c7271 0x131b6972 0x121f6f7d Qm (i32)0x80000001 +vpadal.u32 q0, q1 :: Qd 0x55555556 0x55555557 0x55555556 0x55555557 Qm (i32)0x80000001 +vpadal.u32 q0, q1 :: Qd 0x151d191d 0x5f737a71 0x131b1a1b 0x597a7779 Qm (i32)0x80000001 +vpadal.u32 q10, q11 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585 Qm (i32)0x00000018 +vpadal.u32 q10, q11 :: Qd 0x151d191d 0x5f737a71 0x131b1a1b 0x597a7779 Qm (i32)0x00000018 +vpadal.s32 q0, q1 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585 Qm (i32)0x00000018 +vpadal.s32 q0, q1 :: Qd 0x151d191d 0x5f737a71 0x131b1a1b 0x597a7779 Qm (i32)0x00000018 +vpadal.s32 q0, q1 :: Qd 0x55555555 0x5555566d 0x55555555 0x5555566d Qm (i32)0x0000008c +vpadal.s32 q0, q1 :: Qd 0x151d191d 0x5f737a71 0x131b1a1b 0x597a7779 Qm (i32)0x0000008c +vpadal.s16 q0, q1 :: Qd 0x555555e1 0x555555e1 0x555555e1 0x555555e1 Qm (i32)0x0000008c +vpadal.s16 q0, q1 :: Qd 0x151d6c74 0x141c7271 0x131b6972 0x121f6f7d Qm (i32)0x0000008c +vpadal.s8 q0, q1 :: Qd 0x546d546d 0x546d546d 0x546d546d 0x546d546d Qm (i8)0x0000008c +vpadal.s8 q0, q1 :: Qd 0x15701974 0x146b1f75 0x136b1a71 0x12711e7c Qm (i8)0x0000008c +vpadal.s8 q0, q1 :: Qd 0x54d55556 0x54d55556 0x54d55556 0x54d55556 Qm (i32)0x80000001 +vpadal.s8 q0, q1 :: Qd 0x15701974 0x146b1f75 0x136b1a71 0x12711e7c Qm (i32)0x80000001 +vpadal.s16 q0, q1 :: Qd 0x5554d556 0x5554d556 0x5554d556 0x5554d556 Qm (i32)0x80000001 +vpadal.s16 q0, q1 :: Qd 0x151d6c74 0x141c7271 0x131b6972 0x121f6f7d Qm (i32)0x80000001 +vpadal.s32 q0, q1 :: Qd 0x55555554 0x55555557 0x55555554 0x55555557 Qm (i32)0x80000001 +vpadal.s32 q0, q1 :: Qd 0x151d191d 0x5f737a71 0x131b1a1b 0x597a7779 Qm (i32)0x80000001 +vpadal.s32 q10, q11 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585 Qm (i32)0x00000018 +vpadal.s32 q10, q11 :: Qd 0x151d191d 0x5f737a71 0x131b1a1b 0x597a7779 Qm (i32)0x00000018 +---- VZIP ---- +vzip.32 q0, q1 :: Qm 0x34343434 0x12121212 0x34343434 0x12121212 Qn 0x34343434 0x12121212 0x34343434 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.32 q0, q1 :: Qm 0x34343434 0x131b1a1b 0x34343434 0x121f1e1f Qn 0x34343434 0x151d191d 0x34343434 0x141c1f1c +Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.16 q1, q0 :: Qm 0x12123434 0x12123434 0x12123434 0x12123434 Qn 0x12123434 0x12123434 0x12123434 0x12123434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.16 q1, q0 :: Qm 0x151d3434 0x191d3434 0x141c3434 0x1f1c3434 Qn 0x131b3434 0x1a1b3434 0x121f3434 0x1e1f3434 +Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.8 q10, q11 :: Qm 0x34123412 0x34123412 0x34123412 0x34123412 Qn 0x34123412 0x34123412 0x34123412 0x34123412 Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.8 q10, q11 :: Qm 0x3413341b 0x341a341b 0x3412341f 0x341e341f Qn 0x3415341d 0x3419341d 0x3414341c 0x341f341c +Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.32 q0, q1 :: Qm 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678 Qn 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.32 q0, q1 :: Qm 0x0a0b0c0d 0x131b1a1b 0x0a0b0c0d 0x121f1e1f Qn 0x0a0b0c0d 0x151d191d 0x0a0b0c0d 0x141c1f1c +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.16 q1, q0 :: Qm 0x12340a0b 0x56780c0d 0x12340a0b 0x56780c0d Qn 0x12340a0b 0x56780c0d 0x12340a0b 0x56780c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.16 q1, q0 :: Qm 0x151d0a0b 0x191d0c0d 0x141c0a0b 0x1f1c0c0d Qn 0x131b0a0b 0x1a1b0c0d 0x121f0a0b 0x1e1f0c0d +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.8 q10, q11 :: Qm 0x0a120b34 0x0c560d78 0x0a120b34 0x0c560d78 Qn 0x0a120b34 0x0c560d78 0x0a120b34 0x0c560d78 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.8 q10, q11 :: Qm 0x0a130b1b 0x0c1a0d1b 0x0a120b1f 0x0c1e0d1f Qn 0x0a150b1d 0x0c190d1d 0x0a140b1c 0x0c1f0d1c +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +---- VUZP ---- +vuzp.32 q0, q1 :: Qm 0x34343434 0x34343434 0x12121212 0x12121212 Qn 0x34343434 0x34343434 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.32 q0, q1 :: Qm 0x34343434 0x34343434 0x141c1f1c 0x121f1e1f Qn 0x34343434 0x34343434 0x151d191d 0x131b1a1b +Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.16 q1, q0 :: Qm 0x12121212 0x12121212 0x34343434 0x34343434 Qn 0x12121212 0x12121212 0x34343434 0x34343434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.16 q1, q0 :: Qm 0x151d141c 0x131b121f 0x34343434 0x34343434 Qn 0x191d1f1c 0x1a1b1e1f 0x34343434 0x34343434 +Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.8 q10, q11 :: Qm 0x34343434 0x34343434 0x12121212 0x12121212 Qn 0x34343434 0x34343434 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.8 q10, q11 :: Qm 0x34343434 0x34343434 0x1d1d1c1c 0x1b1b1f1f Qn 0x34343434 0x34343434 0x1519141f 0x131a121e +Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.32 q0, q1 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x12345678 0x12345678 Qn 0x0a0b0c0d 0x0a0b0c0d 0x12345678 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.32 q0, q1 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x141c1f1c 0x121f1e1f Qn 0x0a0b0c0d 0x0a0b0c0d 0x151d191d 0x131b1a1b +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.16 q1, q0 :: Qm 0x12341234 0x12341234 0x0a0b0a0b 0x0a0b0a0b Qn 0x56785678 0x56785678 0x0c0d0c0d 0x0c0d0c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.16 q1, q0 :: Qm 0x151d141c 0x131b121f 0x0a0b0a0b 0x0a0b0a0b Qn 0x191d1f1c 0x1a1b1e1f 0x0c0d0c0d 0x0c0d0c0d +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.8 q10, q11 :: Qm 0x0b0d0b0d 0x0b0d0b0d 0x34783478 0x34783478 Qn 0x0a0c0a0c 0x0a0c0a0c 0x12561256 0x12561256 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.8 q10, q11 :: Qm 0x0b0d0b0d 0x0b0d0b0d 0x1d1d1c1c 0x1b1b1f1f Qn 0x0a0c0a0c 0x0a0c0a0c 0x1519141f 0x131a121e +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +---- VTRN ---- +vtrn.32 q0, q1 :: Qm 0x34343434 0x12121212 0x34343434 0x12121212 Qn 0x34343434 0x12121212 0x34343434 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.32 q0, q1 :: Qm 0x34343434 0x141c1f1c 0x34343434 0x121f1e1f Qn 0x34343434 0x151d191d 0x34343434 0x131b1a1b +Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.16 q1, q0 :: Qm 0x12123434 0x12123434 0x12123434 0x12123434 Qn 0x12123434 0x12123434 0x12123434 0x12123434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.16 q1, q0 :: Qm 0x151d3434 0x141c3434 0x131b3434 0x121f3434 Qn 0x191d3434 0x1f1c3434 0x1a1b3434 0x1e1f3434 +Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.8 q10, q11 :: Qm 0x34123412 0x34123412 0x34123412 0x34123412 Qn 0x34123412 0x34123412 0x34123412 0x34123412 Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.8 q10, q11 :: Qm 0x341d341d 0x341c341c 0x341b341b 0x341f341f Qn 0x34153419 0x3414341f 0x3413341a 0x3412341e +Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.32 q0, q1 :: Qm 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678 Qn 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.32 q0, q1 :: Qm 0x0a0b0c0d 0x141c1f1c 0x0a0b0c0d 0x121f1e1f Qn 0x0a0b0c0d 0x151d191d 0x0a0b0c0d 0x131b1a1b +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.16 q1, q0 :: Qm 0x12340a0b 0x12340a0b 0x12340a0b 0x12340a0b Qn 0x56780c0d 0x56780c0d 0x56780c0d 0x56780c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.16 q1, q0 :: Qm 0x151d0a0b 0x141c0a0b 0x131b0a0b 0x121f0a0b Qn 0x191d0c0d 0x1f1c0c0d 0x1a1b0c0d 0x1e1f0c0d +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.8 q10, q11 :: Qm 0x0b340d78 0x0b340d78 0x0b340d78 0x0b340d78 Qn 0x0a120c56 0x0a120c56 0x0a120c56 0x0a120c56 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.8 q10, q11 :: Qm 0x0b1d0d1d 0x0b1c0d1c 0x0b1b0d1b 0x0b1f0d1f Qn 0x0a150c19 0x0a140c1f 0x0a130c1a 0x0a120c1e +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +---- VSWP ---- +vswp q0, q1 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x12121212 0x12121212 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp q0, q1 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f +Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp q1, q0 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x12121212 0x12121212 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp q1, q0 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f +Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp q10, q11 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x12121212 0x12121212 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp q10, q11 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f +Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp q0, q1 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x12345678 0x12345678 0x12345678 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp q0, q1 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp q1, q0 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x12345678 0x12345678 0x12345678 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp q1, q0 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp q10, q11 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x12345678 0x12345678 0x12345678 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp q10, q11 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f +Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +---- VDUP ---- +vdup.8 q2, d2[0] :: Qd 0x57575757 0x57575757 0x57575757 0x57575757 Qm (i32)0x0abc4657 +vdup.8 q2, d2[0] :: Qd 0x2f2f2f2f 0x2f2f2f2f 0x2f2f2f2f 0x2f2f2f2f Qm (i32)0x0abc4657 +vdup.8 q3, d3[2] :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 Qm (i32)0x0007a1b3 +vdup.8 q3, d3[2] :: Qd 0x2f2f2f2f 0x2f2f2f2f 0x2f2f2f2f 0x2f2f2f2f Qm (i32)0x0007a1b3 +vdup.8 q1, d0[7] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00713aaa +vdup.8 q1, d0[7] :: Qd 0x24242424 0x24242424 0x24242424 0x24242424 Qm (i32)0x00713aaa +vdup.8 q0, d4[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000aa713 +vdup.8 q0, d4[3] :: Qd 0x23232323 0x23232323 0x23232323 0x23232323 Qm (i32)0x000aa713 +vdup.8 q4, d28[4] :: Qd 0xc3c3c3c3 0xc3c3c3c3 0xc3c3c3c3 0xc3c3c3c3 Qm (i32)0x0007b1c3 +vdup.8 q4, d28[4] :: Qd 0x2b2b2b2b 0x2b2b2b2b 0x2b2b2b2b 0x2b2b2b2b Qm (i32)0x0007b1c3 +vdup.16 q7, d19[3] :: Qd 0x07130713 0x07130713 0x07130713 0x07130713 Qm (i32)0x0713ffff +vdup.16 q7, d19[3] :: Qd 0x242c242c 0x242c242c 0x242c242c 0x242c242c Qm (i32)0x0713ffff +vdup.16 q15, d31[0] :: Qd 0x00fa00fa 0x00fa00fa 0x00fa00fa 0x00fa00fa Qm (i32)0x007f00fa +vdup.16 q15, d31[0] :: Qd 0x2e2f2e2f 0x2e2f2e2f 0x2e2f2e2f 0x2e2f2e2f Qm (i32)0x007f00fa +vdup.16 q6, d2[0] :: Qd 0xbcdebcde 0xbcdebcde 0xbcdebcde 0xbcdebcde Qm (i32)0x0ffabcde +vdup.16 q6, d2[0] :: Qd 0x2e2f2e2f 0x2e2f2e2f 0x2e2f2e2f 0x2e2f2e2f Qm (i32)0x0ffabcde +vdup.16 q8, d22[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000713 +vdup.16 q8, d22[3] :: Qd 0x242c242c 0x242c242c 0x242c242c 0x242c242c Qm (i32)0x00000713 +vdup.16 q9, d2[0] :: Qd 0x07130713 0x07130713 0x07130713 0x07130713 Qm (i32)0x00000713 +vdup.16 q9, d2[0] :: Qd 0x2e2f2e2f 0x2e2f2e2f 0x2e2f2e2f 0x2e2f2e2f Qm (i32)0x00000713 +vdup.32 q10, d17[1] :: Qd 0x00000713 0x00000713 0x00000713 0x00000713 Qm (i32)0x00000713 +vdup.32 q10, d17[1] :: Qd 0x242c2b2b 0x242c2b2b 0x242c2b2b 0x242c2b2b Qm (i32)0x00000713 +vdup.32 q15, d11[0] :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x00000003 +vdup.32 q15, d11[0] :: Qd 0x232f2e2f 0x232f2e2f 0x232f2e2f 0x232f2e2f Qm (i32)0x00000003 +vdup.32 q10, d29[1] :: Qd 0xf00000aa 0xf00000aa 0xf00000aa 0xf00000aa Qm (i32)0xf00000aa +vdup.32 q10, d29[1] :: Qd 0x242c2b2b 0x242c2b2b 0x242c2b2b 0x242c2b2b Qm (i32)0xf00000aa +vdup.32 q12, d0[1] :: Qd 0x0000000f 0x0000000f 0x0000000f 0x0000000f Qm (i32)0x0000000f +vdup.32 q12, d0[1] :: Qd 0x242c2b2b 0x242c2b2b 0x242c2b2b 0x242c2b2b Qm (i32)0x0000000f +vdup.32 q13, d13[0] :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff +vdup.32 q13, d13[0] :: Qd 0x232f2e2f 0x232f2e2f 0x232f2e2f 0x232f2e2f Qm (i32)0xffffffff +---- VQDMULL ---- +vqdmull.s32 q0, d1, d2 :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q0, d1, d2 :: Qd 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q0, d1, d2 :: Qd 0x00000011 0xe9687950 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q6, d7, d8 :: Qd 0xffffffff 0xffff7cc0 0xffffffff 0xffff7cc0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmull.s32 q6, d7, d8 :: Qd 0xffffffef 0x02d3c2f0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmull.s32 q6, d7, d8 :: Qd 0xffffffee 0x169786b0 0xffffffef 0x02d3c2f0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmull.s16 q9, d11, d12 :: Qd 0x00000000 0x0002d000 0x00000000 0x0002d000 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmull.s16 q9, d11, d12 :: Qd 0x00000000 0x0043c5c0 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmull.s16 q9, d11, d12 :: Qd 0x00000000 0x003abcc0 0x00000000 0x0043c5c0 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x10014004 0x00000000 0x10014004 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0788387c Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0687286c 0x00000000 0x0788387c Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0xede0e1e1 0x487c787c Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0xece4e5e5 0x4c6c686c 0xede0e1e1 0x487c787c Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0xe50b10cc 0x00000000 0xe50b10cc Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0788387c Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0687286c 0x00000000 0x0788387c Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0xfffffff4 0x00000000 0xfffffff4 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0x00000001 0xb2ead2e8 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0x00000001 0xca8a7288 0x00000001 0xb2ead2e8 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x003f83f8 0x00000000 0x003f83f8 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0788387c Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0687286c 0x00000000 0x0788387c Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0xede0e1e1 0x487c787c Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q7, d8, d9 :: Qd 0xece4e5e5 0x4c6c686c 0xede0e1e1 0x487c787c Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q10, d11, d15 :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q10, d11, d15 :: Qd 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q10, d11, d15 :: Qd 0x00000011 0xe9687950 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmull.s32 q10, d30, d31 :: Qd 0xede0e1e1 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s32 q10, d30, d31 :: Qd 0xece4e5e5 0x00000000 0xede0e1e1 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d31 :: Qd 0x7fffffff 0x00000000 0x7fffffff 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmull.s16 q10, d30, d31 :: Qd 0xede10000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d31 :: Qd 0xece50000 0x00000000 0xede10000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s32 q10, d30, d31 :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s32 q10, d30, d31 :: Qd 0xede0e1e1 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s32 q10, d30, d31 :: Qd 0xece4e5e5 0x00000000 0xede0e1e1 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d31 :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d31 :: Qd 0x090f8000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d31 :: Qd 0x098d8000 0x00000000 0x090f8000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQDMULL (by scalar) ---- +vqdmull.s32 q0, d1, d7[0] :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q0, d1, d7[0] :: Qd 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q0, d1, d7[0] :: Qd 0x00000011 0xe9687950 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q6, d7, d6[0] :: Qd 0xffffffff 0xffff7cc0 0xffffffff 0xffff7cc0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmull.s32 q6, d7, d6[0] :: Qd 0xffffffef 0x02d3c2f0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmull.s32 q6, d7, d6[0] :: Qd 0xffffffee 0x169786b0 0xffffffef 0x02d3c2f0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmull.s16 q9, d11, d7[2] :: Qd 0x00000000 0x0002d000 0x00000000 0x0002d000 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmull.s16 q9, d11, d7[2] :: Qd 0x0028c5c0 0x0043c5c0 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmull.s16 q9, d11, d7[2] :: Qd 0x002afcc0 0x003abcc0 0x0028c5c0 0x0043c5c0 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmull.s16 q4, d5, d6[2] :: Qd 0x00000000 0x10014004 0x00000000 0x10014004 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6[2] :: Qd 0x0488087c 0x0788387c Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6[2] :: Qd 0x04c70c6c 0x0687286c 0x0488087c 0x0788387c Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s32 q7, d8, d3[1] :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q7, d8, d3[1] :: Qd 0xede0e1e1 0x487c787c Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q7, d8, d3[1] :: Qd 0xece4e5e5 0x4c6c686c 0xede0e1e1 0x487c787c Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6[1] :: Qd 0xffffbffc 0xe50b10cc 0xffffbffc 0xe50b10cc Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6[1] :: Qd 0x0488087c 0x0788387c Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6[1] :: Qd 0x04c70c6c 0x0687286c 0x0488087c 0x0788387c Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmull.s32 q7, d8, d3[0] :: Qd 0xfffffff4 0x00000000 0xfffffff4 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmull.s32 q7, d8, d3[0] :: Qd 0x00000001 0xb2ead2e8 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmull.s32 q7, d8, d3[0] :: Qd 0x00000001 0xca8a7288 0x00000001 0xb2ead2e8 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmull.s16 q4, d5, d6[2] :: Qd 0x04004000 0x003f83f8 0x04004000 0x003f83f8 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6[2] :: Qd 0x0488087c 0x0788387c Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s16 q4, d5, d6[2] :: Qd 0x04c70c6c 0x0687286c 0x0488087c 0x0788387c Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmull.s32 q7, d8, d3[1] :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q7, d8, d3[1] :: Qd 0xede0e1e1 0x487c787c Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q7, d8, d3[1] :: Qd 0xece4e5e5 0x4c6c686c 0xede0e1e1 0x487c787c Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmull.s32 q10, d11, d15[1] :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q10, d11, d15[1] :: Qd 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q10, d11, d15[1] :: Qd 0x00000011 0xe9687950 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmull.s32 q10, d30, d1[0] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmull.s32 q10, d30, d1[0] :: Qd 0xede0e1e1 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s32 q10, d30, d1[0] :: Qd 0xece4e5e5 0x00000000 0xede0e1e1 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d1[1] :: Qd 0x7fffffff 0x00000000 0x7fffffff 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmull.s16 q10, d30, d1[1] :: Qd 0xede10000 0xe1e10000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d1[1] :: Qd 0xece50000 0xe5e50000 0xede10000 0xe1e10000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s32 q10, d30, d1[1] :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s32 q10, d30, d1[1] :: Qd 0xede0e1e1 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s32 q10, d30, d1[1] :: Qd 0xece4e5e5 0x00000000 0xede0e1e1 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d1[3] :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d1[3] :: Qd 0x090f8000 0x0f0f8000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmull.s16 q10, d30, d1[3] :: Qd 0x098d8000 0x0d0d8000 0x090f8000 0x0f0f8000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQDMLSL ---- +vqdmlsl.s32 q0, d1, d2 :: Qd 0x00000017 0xffffe998 0x55555555 0x55553ed5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q0, d1, d2 :: Qd 0x55555544 0x58291845 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q0, d1, d2 :: Qd 0x131b1a09 0x28b6a4cf 0x55555544 0x58291845 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q6, d7, d8 :: Qd 0x55555555 0x5555d895 0x55555555 0x5555d895 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlsl.s32 q6, d7, d8 :: Qd 0x55555566 0x52819265 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlsl.s32 q6, d7, d8 :: Qd 0x55555567 0x3ebdcea5 0x55555566 0x52819265 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlsl.s16 q9, d11, d12 :: Qd 0x55555555 0x55528555 0x55555555 0x55528555 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlsl.s16 q9, d11, d12 :: Qd 0x55555555 0x55118f95 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlsl.s16 q9, d11, d12 :: Qd 0x55555555 0x551a9895 0x55555555 0x55118f95 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x45541551 0x55555555 0x45541551 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4dcd1cd9 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4ece2ce9 0x55555555 0x4dcd1cd9 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0x67747374 0x0cd8dcd9 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0x68706f70 0x08e8ece9 0x67747374 0x0cd8dcd9 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x704a4489 0x55555555 0x704a4489 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4dcd1cd9 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4ece2ce9 0x55555555 0x4dcd1cd9 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0x55555561 0x55555555 0x55555561 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0x55555553 0xa26a826d Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0x55555553 0x8acae2cd 0x55555553 0xa26a826d Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x5515d15d 0x55555555 0x5515d15d Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4dcd1cd9 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4ece2ce9 0x55555555 0x4dcd1cd9 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0x67747374 0x0cd8dcd9 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d9 :: Qd 0x68706f70 0x08e8ece9 0x67747374 0x0cd8dcd9 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q10, d11, d15 :: Qd 0x55555555 0x55553ed5 0x55555555 0x55553ed5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q10, d11, d15 :: Qd 0x55555544 0x58291845 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q10, d11, d15 :: Qd 0x55555543 0x6becdc05 0x55555544 0x58291845 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q10, d30, d31 :: Qd 0xd5555555 0x55555556 0xd5555555 0x55555556 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlsl.s32 q10, d30, d31 :: Qd 0x67747374 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s32 q10, d30, d31 :: Qd 0x68706f70 0x55555555 0x67747374 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s16 q10, d30, d31 :: Qd 0xd5555556 0x55555555 0xd5555556 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlsl.s16 q10, d30, d31 :: Qd 0x67745555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s16 q10, d30, d31 :: Qd 0x68705555 0x55555555 0x67745555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlsl.s32 q10, d30, d31 :: Qd 0x67747374 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s32 q10, d30, d31 :: Qd 0x68706f70 0x55555555 0x67747374 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s16 q10, d30, d31 :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 08000000 +vqdmlsl.s16 q10, d30, d31 :: Qd 0x4c45d555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmlsl.s16 q10, d30, d31 :: Qd 0x4bc7d555 0x55555555 0x4c45d555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQDMLSL (by scalar) ---- +vqdmlsl.s32 q0, d1, d7[0] :: Qd 0x00000017 0xffffe998 0x55555555 0x55553ed5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q0, d1, d7[0] :: Qd 0x55555544 0x58291845 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q0, d1, d7[0] :: Qd 0x131b1a09 0x28b6a4cf 0x55555544 0x58291845 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q6, d7, d6[0] :: Qd 0x55555555 0x5555d895 0x55555555 0x5555d895 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlsl.s32 q6, d7, d6[0] :: Qd 0x55555566 0x52819265 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlsl.s32 q6, d7, d6[0] :: Qd 0x55555567 0x3ebdcea5 0x55555566 0x52819265 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlsl.s16 q9, d11, d7[2] :: Qd 0x55555555 0x55528555 0x55555555 0x55528555 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlsl.s16 q9, d11, d7[2] :: Qd 0x552c8f95 0x55118f95 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlsl.s16 q9, d11, d7[2] :: Qd 0x552a5895 0x551a9895 0x552c8f95 0x55118f95 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x55555555 0x45541551 0x55555555 0x45541551 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x50cd4cd9 0x4dcd1cd9 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x508e48e9 0x4ece2ce9 0x50cd4cd9 0x4dcd1cd9 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[1] :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[1] :: Qd 0x67747374 0x0cd8dcd9 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[1] :: Qd 0x68706f70 0x08e8ece9 0x67747374 0x0cd8dcd9 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[1] :: Qd 0x55559559 0x704a4489 0x55559559 0x704a4489 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[1] :: Qd 0x50cd4cd9 0x4dcd1cd9 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[1] :: Qd 0x508e48e9 0x4ece2ce9 0x50cd4cd9 0x4dcd1cd9 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[0] :: Qd 0x55555561 0x55555555 0x55555561 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[0] :: Qd 0x55555553 0xa26a826d Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[0] :: Qd 0x55555553 0x8acae2cd 0x55555553 0xa26a826d Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x51551555 0x5515d15d 0x51551555 0x5515d15d Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x50cd4cd9 0x4dcd1cd9 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x508e48e9 0x4ece2ce9 0x50cd4cd9 0x4dcd1cd9 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[1] :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[1] :: Qd 0x67747374 0x0cd8dcd9 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q7, d8, d3[1] :: Qd 0x68706f70 0x08e8ece9 0x67747374 0x0cd8dcd9 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlsl.s32 q10, d11, d15[1] :: Qd 0x55555555 0x55553ed5 0x55555555 0x55553ed5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q10, d11, d15[1] :: Qd 0x55555544 0x58291845 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q10, d11, d15[1] :: Qd 0x55555543 0x6becdc05 0x55555544 0x58291845 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlsl.s32 q10, d30, d1[0] :: Qd 0xd5555555 0x55555556 0xd5555555 0x55555556 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlsl.s32 q10, d30, d1[0] :: Qd 0x67747374 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s32 q10, d30, d1[0] :: Qd 0x68706f70 0x55555555 0x67747374 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s16 q10, d30, d1[1] :: Qd 0xd5555556 0x55555555 0xd5555556 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlsl.s16 q10, d30, d1[1] :: Qd 0x67745555 0x73745555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s16 q10, d30, d1[1] :: Qd 0x68705555 0x6f705555 0x67745555 0x73745555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s32 q10, d30, d1[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlsl.s32 q10, d30, d1[1] :: Qd 0x67747374 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s32 q10, d30, d1[1] :: Qd 0x68706f70 0x55555555 0x67747374 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlsl.s16 q10, d30, d1[3] :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 08000000 +vqdmlsl.s16 q10, d30, d1[3] :: Qd 0x4c45d555 0x4645d555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmlsl.s16 q10, d30, d1[3] :: Qd 0x4bc7d555 0x4847d555 0x4c45d555 0x4645d555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQDMLAL ---- +vqdmlal.s32 q0, d1, d2 :: Qd 0x00000018 0x00001698 0x55555555 0x55556bd5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q0, d1, d2 :: Qd 0x55555566 0x52819265 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q0, d1, d2 :: Qd 0x131b1a2c 0xfb87976f 0x55555566 0x52819265 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q6, d7, d8 :: Qd 0x55555555 0x5554d215 0x55555555 0x5554d215 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlal.s32 q6, d7, d8 :: Qd 0x55555544 0x58291845 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlal.s32 q6, d7, d8 :: Qd 0x55555543 0x6becdc05 0x55555544 0x58291845 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlal.s16 q9, d11, d12 :: Qd 0x55555555 0x55582555 0x55555555 0x55582555 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlal.s16 q9, d11, d12 :: Qd 0x55555555 0x55991b15 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlal.s16 q9, d11, d12 :: Qd 0x55555555 0x55901215 0x55555555 0x55991b15 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x65569559 0x55555555 0x65569559 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5cdd8dd1 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5bdc7dc1 0x55555555 0x5cdd8dd1 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x43363736 0x9dd1cdd1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x423a3b3a 0xa1c1bdc1 0x43363736 0x9dd1cdd1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x3a606621 0x55555555 0x3a606621 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5cdd8dd1 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5bdc7dc1 0x55555555 0x5cdd8dd1 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x55555549 0x55555555 0x55555549 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x55555557 0x0840283d Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x55555557 0x1fdfc7dd 0x55555557 0x0840283d Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5594d94d 0x55555555 0x5594d94d Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5cdd8dd1 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5bdc7dc1 0x55555555 0x5cdd8dd1 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x43363736 0x9dd1cdd1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d9 :: Qd 0x423a3b3a 0xa1c1bdc1 0x43363736 0x9dd1cdd1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlal.s32 q10, d11, d15 :: Qd 0x55555555 0x55556bd5 0x55555555 0x55556bd5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q10, d11, d15 :: Qd 0x55555566 0x52819265 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q10, d11, d15 :: Qd 0x55555567 0x3ebdcea5 0x55555566 0x52819265 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlal.s32 q10, d30, d31 :: Qd 0x43363736 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s32 q10, d30, d31 :: Qd 0x423a3b3a 0x55555555 0x43363736 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d31 :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlal.s16 q10, d30, d31 :: Qd 0x43365555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d31 :: Qd 0x423a5555 0x55555555 0x43365555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s32 q10, d30, d31 :: Qd 0x43363736 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s32 q10, d30, d31 :: Qd 0x423a3b3a 0x55555555 0x43363736 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d31 :: Qd 0x5e64d555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d31 :: Qd 0x5ee2d555 0x55555555 0x5e64d555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQDMLAL (by scalar) ---- +vqdmlal.s32 q0, d1, d7[0] :: Qd 0x00000018 0x00001698 0x55555555 0x55556bd5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q0, d1, d7[0] :: Qd 0x55555566 0x52819265 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q0, d1, d7[0] :: Qd 0x131b1a2c 0xfb87976f 0x55555566 0x52819265 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q6, d7, d6[0] :: Qd 0x55555555 0x5554d215 0x55555555 0x5554d215 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlal.s32 q6, d7, d6[0] :: Qd 0x55555544 0x58291845 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlal.s32 q6, d7, d6[0] :: Qd 0x55555543 0x6becdc05 0x55555544 0x58291845 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmlal.s16 q9, d11, d7[2] :: Qd 0x55555555 0x55582555 0x55555555 0x55582555 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlal.s16 q9, d11, d7[2] :: Qd 0x557e1b15 0x55991b15 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlal.s16 q9, d11, d7[2] :: Qd 0x55805215 0x55901215 0x557e1b15 0x55991b15 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[2] :: Qd 0x55555555 0x65569559 0x55555555 0x65569559 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[2] :: Qd 0x59dd5dd1 0x5cdd8dd1 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[2] :: Qd 0x5a1c61c1 0x5bdc7dc1 0x59dd5dd1 0x5cdd8dd1 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d3[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqdmlal.s32 q7, d8, d3[1] :: Qd 0x43363736 0x9dd1cdd1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d3[1] :: Qd 0x423a3b3a 0xa1c1bdc1 0x43363736 0x9dd1cdd1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[1] :: Qd 0x55551551 0x3a606621 0x55551551 0x3a606621 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[1] :: Qd 0x59dd5dd1 0x5cdd8dd1 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[1] :: Qd 0x5a1c61c1 0x5bdc7dc1 0x59dd5dd1 0x5cdd8dd1 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d3[0] :: Qd 0x55555549 0x55555555 0x55555549 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlal.s32 q7, d8, d3[0] :: Qd 0x55555557 0x0840283d Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlal.s32 q7, d8, d3[0] :: Qd 0x55555557 0x1fdfc7dd 0x55555557 0x0840283d Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[2] :: Qd 0x59559555 0x5594d94d 0x59559555 0x5594d94d Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[2] :: Qd 0x59dd5dd1 0x5cdd8dd1 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s16 q4, d5, d6[2] :: Qd 0x5a1c61c1 0x5bdc7dc1 0x59dd5dd1 0x5cdd8dd1 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d3[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqdmlal.s32 q7, d8, d3[1] :: Qd 0x43363736 0x9dd1cdd1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlal.s32 q7, d8, d3[1] :: Qd 0x423a3b3a 0xa1c1bdc1 0x43363736 0x9dd1cdd1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmlal.s32 q10, d11, d15[1] :: Qd 0x55555555 0x55556bd5 0x55555555 0x55556bd5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q10, d11, d15[1] :: Qd 0x55555566 0x52819265 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q10, d11, d15[1] :: Qd 0x55555567 0x3ebdcea5 0x55555566 0x52819265 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmlal.s32 q10, d30, d1[0] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlal.s32 q10, d30, d1[0] :: Qd 0x43363736 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s32 q10, d30, d1[0] :: Qd 0x423a3b3a 0x55555555 0x43363736 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d1[1] :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmlal.s16 q10, d30, d1[1] :: Qd 0x43365555 0x37365555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d1[1] :: Qd 0x423a5555 0x3b3a5555 0x43365555 0x37365555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s32 q10, d30, d1[1] :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s32 q10, d30, d1[1] :: Qd 0x43363736 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s32 q10, d30, d1[1] :: Qd 0x423a3b3a 0x55555555 0x43363736 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d1[3] :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d1[3] :: Qd 0x5e64d555 0x6464d555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmlal.s16 q10, d30, d1[3] :: Qd 0x5ee2d555 0x6262d555 0x5e64d555 0x6464d555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQDMULH ---- +vqdmulh.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q0, q1, q2 :: Qd 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q0, q1, q2 :: Qd 0x00000013 0x00000012 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q6, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s32 q6, q7, q8 :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s32 q6, q7, q8 :: Qd 0xffffffec 0xffffffed 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s16 q9, q11, q12 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 q9, q11, q12 :: Qd 0x0000003a 0x00000043 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 q9, q11, q12 :: Qd 0x00000038 0x00000045 0x0000003a 0x00000043 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x00001001 0x00001001 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x00000687 0x00000788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x00000647 0x000007c7 0x00000687 0x00000788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x00000687 0x00000788 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x00000647 0x000007c7 0x00000687 0x00000788 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x00000687 0x00000788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, q6 :: Qd 0x00000647 0x000007c7 0x00000687 0x00000788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q7, q8, q9 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q10, q11, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q10, q11, q15 :: Qd 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q10, q11, q15 :: Qd 0x00000013 0x00000012 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmulh.s32 q10, q14, q15 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, q15 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, q15 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmulh.s16 q10, q14, q15 :: Qd 0xece50000 0xede10000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, q15 :: Qd 0xeae30000 0xebe40000 0xece50000 0xede10000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, q15 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, q15 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, q15 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, q15 :: Qd 0x0a8e0000 0x0a0e0000 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQDMULH (by scalar) ---- +vqdmulh.s32 q0, q1, d6[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q0, q1, d6[0] :: Qd 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q0, q1, d6[0] :: Qd 0x00000013 0x00000012 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q6, q7, d1[1] :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s32 q6, q7, d1[1] :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s32 q6, q7, d1[1] :: Qd 0xffffffec 0xffffffed 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s16 q9, q11, d7[0] :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 q9, q11, d7[0] :: Qd 0x002a003a 0x00280043 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 q9, q11, d7[0] :: Qd 0x002f0038 0x002d0045 0x002a003a 0x00280043 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[0] :: Qd 0x00001001 0x00001001 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[0] :: Qd 0x04c70687 0x04880788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[0] :: Qd 0x05470647 0x050707c7 0x04c70687 0x04880788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[1] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[1] :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[1] :: Qd 0xffffe50b 0xffffe50b 0xffffe50b 0xffffe50b Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[1] :: Qd 0x04c70687 0x04880788 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[1] :: Qd 0x05470647 0x050707c7 0x04c70687 0x04880788 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[0] :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[0] :: Qd 0x00000001 0x00000001 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[0] :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[2] :: Qd 0x0400003f 0x0400003f 0x0400003f 0x0400003f Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[2] :: Qd 0x04c70687 0x04880788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 q4, q5, d6[2] :: Qd 0x05470647 0x050707c7 0x04c70687 0x04880788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[0] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q7, q8, d9[0] :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 q10, q11, d15[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q10, q11, d15[0] :: Qd 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q10, q11, d15[0] :: Qd 0x00000013 0x00000012 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 q10, q14, d15[1] :: Qd 0xffffff88 0xffffff88 0xffffff88 0xffffff88 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, d15[1] :: Qd 0x00000011 0x00000010 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, d15[1] :: Qd 0x00000013 0x00000012 0x00000011 0x00000010 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, d7[3] :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmulh.s16 q10, q14, d7[3] :: Qd 0xece5e5e5 0xede1e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, d7[3] :: Qd 0xeae3e6e3 0xebe4e0e4 0xece5e5e5 0xede1e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, d15[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, d15[1] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 q10, q14, d15[1] :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, d7[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, d7[1] :: Qd 0x098d0d0d 0x090f0f0f Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmulh.s16 q10, q14, d7[1] :: Qd 0x0a8e0c8e 0x0a0e0f8e 0x098d0d0d 0x090f0f0f Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VSHL (immediate) ---- +vshl.i64 q0, q1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i32)0x00000018 +vshl.i64 q0, q1, #1 :: Qd 0x4c5a5a54 0x4a545c56 0x48585656 0x465e5c5e Qm (i32)0x00000018 +vshl.i64 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x40000000 +vshl.i64 q5, q2, #1 :: Qd 0x4c5a5a54 0x4a545c56 0x48585656 0x465e5c5e Qm (i32)0x40000000 +vshl.i64 q9, q12, #2 :: Qd 0x0000000a 0x00000008 0x0000000a 0x00000008 Qm (i32)0x80000002 +vshl.i64 q9, q12, #2 :: Qd 0x98b4b4a8 0x94a8b8ac 0x90b0acac 0x8cbcb8bc Qm (i32)0x80000002 +vshl.i64 q11, q2, #12 :: Qd 0xffffffff 0xfffff000 0xffffffff 0xfffff000 Qm (i32)0xffffffff +vshl.i64 q11, q2, #12 :: Qd 0xd2d2a252 0xa2e2b000 0xc2b2b232 0xf2e2f000 Qm (i32)0xffffffff +vshl.i64 q15, q12, #63 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000 Qm (i32)0x00000005 +vshl.i64 q15, q12, #63 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000 Qm (i32)0x00000005 +vshl.i64 q5, q12, #62 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000001 +vshl.i64 q5, q12, #62 :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x80000001 +vshl.i32 q0, q1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i32)0x00000018 +vshl.i32 q0, q1, #1 :: Qd 0x4c5a5a54 0x4a545c56 0x48585656 0x465e5c5e Qm (i32)0x00000018 +vshl.i32 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x40000000 +vshl.i32 q5, q2, #1 :: Qd 0x4c5a5a54 0x4a545c56 0x48585656 0x465e5c5e Qm (i32)0x40000000 +vshl.i32 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 +vshl.i32 q9, q12, #2 :: Qd 0x98b4b4a8 0x94a8b8ac 0x90b0acac 0x8cbcb8bc Qm (i32)0x80000002 +vshl.i32 q11, q2, #12 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000 Qm (i32)0xffffffff +vshl.i32 q11, q2, #12 :: Qd 0xd2d2a000 0xa2e2b000 0xc2b2b000 0xf2e2f000 Qm (i32)0xffffffff +vshl.i32 q15, q12, #20 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000 Qm (i32)0x00000005 +vshl.i32 q15, q12, #20 :: Qd 0xd2a00000 0xe2b00000 0xb2b00000 0xe2f00000 Qm (i32)0x00000005 +vshl.i32 q5, q12, #30 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000001 +vshl.i32 q5, q12, #30 :: Qd 0x80000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000001 +vshl.i16 q0, q1, #1 :: Qd 0x00300030 0x00300030 0x00300030 0x00300030 Qm (i16)0x00000018 +vshl.i16 q0, q1, #1 :: Qd 0x4c5a5a54 0x4a545c56 0x48585656 0x465e5c5e Qm (i16)0x00000018 +vshl.i16 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x40000000 +vshl.i16 q5, q2, #1 :: Qd 0x4c5a5a54 0x4a545c56 0x48585656 0x465e5c5e Qm (i32)0x40000000 +vshl.i16 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 +vshl.i16 q9, q12, #2 :: Qd 0x98b4b4a8 0x94a8b8ac 0x90b0acac 0x8cbcb8bc Qm (i32)0x80000002 +vshl.i16 q11, q2, #12 :: Qd 0xf000f000 0xf000f000 0xf000f000 0xf000f000 Qm (i16)0xffffffff +vshl.i16 q11, q2, #12 :: Qd 0xd000a000 0xa000b000 0xc000b000 0xf000f000 Qm (i16)0xffffffff +vshl.i16 q15, q12, #3 :: Qd 0x00280028 0x00280028 0x00280028 0x00280028 Qm (i16)0x00000005 +vshl.i16 q15, q12, #3 :: Qd 0x31686950 0x29507158 0x21605958 0x19787178 Qm (i16)0x00000005 +vshl.i16 q5, q12, #14 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000 Qm (i32)0x80000001 +vshl.i16 q5, q12, #14 :: Qd 0x40008000 0x8000c000 0x0000c000 0xc000c000 Qm (i32)0x80000001 +vshl.i8 q0, q1, #1 :: Qd 0x30303030 0x30303030 0x30303030 0x30303030 Qm (i8)0x00000018 +vshl.i8 q0, q1, #1 :: Qd 0x4c5a5a54 0x4a545c56 0x48585656 0x465e5c5e Qm (i8)0x00000018 +vshl.i8 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x40000000 +vshl.i8 q5, q2, #1 :: Qd 0x4c5a5a54 0x4a545c56 0x48585656 0x465e5c5e Qm (i32)0x40000000 +vshl.i8 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 +vshl.i8 q9, q12, #2 :: Qd 0x98b4b4a8 0x94a8b8ac 0x90b0acac 0x8cbcb8bc Qm (i32)0x80000002 +vshl.i8 q11, q2, #7 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i8)0xffffffff +vshl.i8 q11, q2, #7 :: Qd 0x00808000 0x80000080 0x00008080 0x80800080 Qm (i8)0xffffffff +vshl.i8 q15, q12, #3 :: Qd 0x28282828 0x28282828 0x28282828 0x28282828 Qm (i8)0x00000005 +vshl.i8 q15, q12, #3 :: Qd 0x30686850 0x28507058 0x20605858 0x18787078 Qm (i8)0x00000005 +vshl.i8 q5, q12, #6 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x80000001 +vshl.i8 q5, q12, #6 :: Qd 0x80404080 0x408080c0 0x0000c0c0 0xc0c080c0 Qm (i32)0x80000001 +---- VNEG ---- +vneg.s32 q0, q1 :: Qd 0xffffff8d 0xffffff8d 0xffffff8d 0xffffff8d Qm (i32)0x00000073 +vneg.s32 q0, q1 :: Qd 0xd9d2d2d6 0xdad5d1d5 0xdbd3d4d5 0xdcd0d1d1 Qm (i32)0x00000073 +vneg.s16 q15, q4 :: Qd 0x0000ff8d 0x0000ff8d 0x0000ff8d 0x0000ff8d Qm (i32)0x00000073 +vneg.s16 q15, q4 :: Qd 0xd9d3d2d6 0xdad6d1d5 0xdbd4d4d5 0xdcd1d1d1 Qm (i32)0x00000073 +vneg.s8 q8, q7 :: Qd 0x0000008d 0x0000008d 0x0000008d 0x0000008d Qm (i32)0x00000073 +vneg.s8 q8, q7 :: Qd 0xdad3d3d6 0xdbd6d2d5 0xdcd4d5d5 0xddd1d2d1 Qm (i32)0x00000073 +vneg.s32 q0, q1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02 Qm (i32)0x000000fe +vneg.s32 q0, q1 :: Qd 0xd9d2d2d6 0xdad5d1d5 0xdbd3d4d5 0xdcd0d1d1 Qm (i32)0x000000fe +vneg.s16 q15, q4 :: Qd 0x0000ff11 0x0000ff11 0x0000ff11 0x0000ff11 Qm (i32)0x000000ef +vneg.s16 q15, q4 :: Qd 0xd9d3d2d6 0xdad6d1d5 0xdbd4d4d5 0xdcd1d1d1 Qm (i32)0x000000ef +vneg.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022 Qm (i32)0x000000de +vneg.s8 q8, q7 :: Qd 0xdad3d3d6 0xdbd6d2d5 0xdcd4d5d5 0xddd1d2d1 Qm (i32)0x000000de +vneg.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a +vneg.s32 q0, q1 :: Qd 0xd9d2d2d6 0xdad5d1d5 0xdbd3d4d5 0xdcd0d1d1 Qm (i16)0x0000fe0a +vneg.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b +vneg.s16 q15, q4 :: Qd 0xd9d3d2d6 0xdad6d1d5 0xdbd4d4d5 0xdcd1d1d1 Qm (i16)0x0000ef0b +vneg.s8 q8, q7 :: Qd 0x22f422f4 0x22f422f4 0x22f422f4 0x22f422f4 Qm (i16)0x0000de0c +vneg.s8 q8, q7 :: Qd 0xdad3d3d6 0xdbd6d2d5 0xdcd4d5d5 0xddd1d2d1 Qm (i16)0x0000de0c +---- VQNEG ---- +vqneg.s32 q0, q1 :: Qd 0xffffff8d 0xffffff8d 0xffffff8d 0xffffff8d Qm (i32)0x00000073 fpscr: 00000000 +vqneg.s32 q0, q1 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x00000073 fpscr: 00000000 +vqneg.s32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 fpscr: 08000000 +vqneg.s32 q0, q1 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 fpscr: 00000000 +vqneg.s16 q0, q1 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 fpscr: 08000000 +vqneg.s16 q0, q1 :: Qd 0xeae3e6e3 0xebe4e0e4 0xece5e5e5 0xede1e1e1 Qm (i32)0x80000000 fpscr: 00000000 +vqneg.s8 q0, q1 :: Qd 0x7f000000 0x7f000000 0x7f000000 0x7f000000 Qm (i32)0x80000000 fpscr: 08000000 +vqneg.s8 q0, q1 :: Qd 0xebe3e7e3 0xece4e1e4 0xede5e6e5 0xeee1e2e1 Qm (i32)0x80000000 fpscr: 00000000 +vqneg.s16 q15, q4 :: Qd 0x0000ff8d 0x0000ff8d 0x0000ff8d 0x0000ff8d Qm (i32)0x00000073 fpscr: 00000000 +vqneg.s16 q15, q4 :: Qd 0xeae3e6e3 0xebe4e0e4 0xece5e5e5 0xede1e1e1 Qm (i32)0x00000073 fpscr: 00000000 +vqneg.s8 q8, q7 :: Qd 0x0000008d 0x0000008d 0x0000008d 0x0000008d Qm (i32)0x00000073 fpscr: 00000000 +vqneg.s8 q8, q7 :: Qd 0xebe3e7e3 0xece4e1e4 0xede5e6e5 0xeee1e2e1 Qm (i32)0x00000073 fpscr: 00000000 +vqneg.s32 q0, q1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02 Qm (i32)0x000000fe fpscr: 00000000 +vqneg.s32 q0, q1 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x000000fe fpscr: 00000000 +vqneg.s16 q15, q4 :: Qd 0x0000ff11 0x0000ff11 0x0000ff11 0x0000ff11 Qm (i32)0x000000ef fpscr: 00000000 +vqneg.s16 q15, q4 :: Qd 0xeae3e6e3 0xebe4e0e4 0xece5e5e5 0xede1e1e1 Qm (i32)0x000000ef fpscr: 00000000 +vqneg.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022 Qm (i32)0x000000de fpscr: 00000000 +vqneg.s8 q8, q7 :: Qd 0xebe3e7e3 0xece4e1e4 0xede5e6e5 0xeee1e2e1 Qm (i32)0x000000de fpscr: 00000000 +vqneg.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a fpscr: 00000000 +vqneg.s32 q0, q1 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i16)0x0000fe0a fpscr: 00000000 +vqneg.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b fpscr: 00000000 +vqneg.s16 q15, q4 :: Qd 0xeae3e6e3 0xebe4e0e4 0xece5e5e5 0xede1e1e1 Qm (i16)0x0000ef0b fpscr: 00000000 +vqneg.s8 q8, q7 :: Qd 0x22f422f4 0x22f422f4 0x22f422f4 0x22f422f4 Qm (i16)0x0000de0c fpscr: 00000000 +vqneg.s8 q8, q7 :: Qd 0xebe3e7e3 0xece4e1e4 0xede5e6e5 0xeee1e2e1 Qm (i16)0x0000de0c fpscr: 00000000 +---- VREV ---- +vrev64.8 q0, q1 :: Qd 0xddccbbaa 0xddccbbaa 0xddccbbaa 0xddccbbaa Qm (i32)0xaabbccdd +vrev64.8 q0, q1 :: Qd 0x2b2e2a25 0x2a2d2d26 0x2f2e2f23 0x2b2b2c24 Qm (i32)0xaabbccdd +vrev64.16 q10, q15 :: Qd 0xccddaabb 0xccddaabb 0xccddaabb 0xccddaabb Qm (i32)0xaabbccdd +vrev64.16 q10, q15 :: Qd 0x2e2b252a 0x2d2a262d 0x2e2f232f 0x2b2b242c Qm (i32)0xaabbccdd +vrev64.32 q1, q14 :: Qd 0xaabbccdd 0xaabbccdd 0xaabbccdd 0xaabbccdd Qm (i32)0xaabbccdd +vrev64.32 q1, q14 :: Qd 0x252a2e2b 0x262d2d2a 0x232f2e2f 0x242c2b2b Qm (i32)0xaabbccdd +vrev32.8 q0, q1 :: Qd 0xddccbbaa 0xddccbbaa 0xddccbbaa 0xddccbbaa Qm (i32)0xaabbccdd +vrev32.8 q0, q1 :: Qd 0x2a2d2d26 0x2b2e2a25 0x2b2b2c24 0x2f2e2f23 Qm (i32)0xaabbccdd +vrev32.16 q10, q15 :: Qd 0xccddaabb 0xccddaabb 0xccddaabb 0xccddaabb Qm (i32)0xaabbccdd +vrev32.16 q10, q15 :: Qd 0x2d2a262d 0x2e2b252a 0x2b2b242c 0x2e2f232f Qm (i32)0xaabbccdd +vrev16.8 q0, q1 :: Qd 0xbbaaddcc 0xbbaaddcc 0xbbaaddcc 0xbbaaddcc Qm (i32)0xaabbccdd +vrev16.8 q0, q1 :: Qd 0x2d262a2d 0x2a252b2e 0x2c242b2b 0x2f232f2e Qm (i32)0xaabbccdd +---- VSHLL ---- +vshll.s32 q0, d1, #1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018 +vshll.s32 q0, d1, #1 :: Qd 0x00000000 0x48585656 0x00000000 0x465e5c5e Qm (i32)0x00000018 +vshll.s32 q5, d2, #1 :: Qd 0x00000000 0x80000000 0x00000000 0x80000000 Qm (i32)0x40000000 +vshll.s32 q5, d2, #1 :: Qd 0x00000000 0x48585656 0x00000000 0x465e5c5e Qm (i32)0x40000000 +vshll.s32 q9, d12, #2 :: Qd 0xfffffffe 0x00000008 0xfffffffe 0x00000008 Qm (i32)0x80000002 +vshll.s32 q9, d12, #2 :: Qd 0x00000000 0x90b0acac 0x00000000 0x8cbcb8bc Qm (i32)0x80000002 +vshll.u32 q11, d2, #12 :: Qd 0x00000fff 0xfffff000 0x00000fff 0xfffff000 Qm (i32)0xffffffff +vshll.u32 q11, d2, #12 :: Qd 0x00000242 0xc2b2b000 0x00000232 0xf2e2f000 Qm (i32)0xffffffff +vshll.u32 q15, d12, #20 :: Qd 0x00000000 0x00500000 0x00000000 0x00500000 Qm (i32)0x00000005 +vshll.u32 q15, d12, #20 :: Qd 0x000242c2 0xb2b00000 0x000232f2 0xe2f00000 Qm (i32)0x00000005 +vshll.u32 q5, d22, #30 :: Qd 0x20000000 0x40000000 0x20000000 0x40000000 Qm (i32)0x80000001 +vshll.u32 q5, d22, #30 :: Qd 0x090b0aca 0xc0000000 0x08cbcb8b 0xc0000000 Qm (i32)0x80000001 +vshll.s16 q0, d1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i16)0x00000018 +vshll.s16 q0, d1, #1 :: Qd 0x00004858 0x00005656 0x0000465e 0x00005c5e Qm (i16)0x00000018 +vshll.s16 q5, d2, #1 :: Qd 0x00008000 0x00000000 0x00008000 0x00000000 Qm (i32)0x40000000 +vshll.s16 q5, d2, #1 :: Qd 0x00004858 0x00005656 0x0000465e 0x00005c5e Qm (i32)0x40000000 +vshll.s16 q9, d12, #2 :: Qd 0xfffe0000 0x00000008 0xfffe0000 0x00000008 Qm (i32)0x80000002 +vshll.s16 q9, d12, #2 :: Qd 0x000090b0 0x0000acac 0x00008cbc 0x0000b8bc Qm (i32)0x80000002 +vshll.u16 q11, d2, #12 :: Qd 0x0ffff000 0x0ffff000 0x0ffff000 0x0ffff000 Qm (i16)0xffffffff +vshll.u16 q11, d2, #12 :: Qd 0x0242c000 0x02b2b000 0x0232f000 0x02e2f000 Qm (i16)0xffffffff +vshll.u16 q15, d22, #3 :: Qd 0x00000028 0x00000028 0x00000028 0x00000028 Qm (i16)0x00000005 +vshll.u16 q15, d22, #3 :: Qd 0x00012160 0x00015958 0x00011978 0x00017178 Qm (i16)0x00000005 +vshll.u16 q5, d12, #14 :: Qd 0x20000000 0x00004000 0x20000000 0x00004000 Qm (i32)0x80000001 +vshll.u16 q5, d12, #14 :: Qd 0x090b0000 0x0acac000 0x08cbc000 0x0b8bc000 Qm (i32)0x80000001 +vshll.s8 q0, d1, #1 :: Qd 0x00300030 0x00300030 0x00300030 0x00300030 Qm (i8)0x00000018 +vshll.s8 q0, d1, #1 :: Qd 0x00480058 0x00560056 0x0046005e 0x005c005e Qm (i8)0x00000018 +vshll.s8 q5, d2, #1 :: Qd 0x00800000 0x00000000 0x00800000 0x00000000 Qm (i32)0x40000000 +vshll.s8 q5, d2, #1 :: Qd 0x00480058 0x00560056 0x0046005e 0x005c005e Qm (i32)0x40000000 +vshll.s8 q9, d12, #2 :: Qd 0xfe000000 0x00000008 0xfe000000 0x00000008 Qm (i32)0x80000002 +vshll.s8 q9, d12, #2 :: Qd 0x009000b0 0x00ac00ac 0x008c00bc 0x00b800bc Qm (i32)0x80000002 +vshll.u8 q11, d2, #7 :: Qd 0x7f807f80 0x7f807f80 0x7f807f80 0x7f807f80 Qm (i8)0xffffffff +vshll.u8 q11, d2, #7 :: Qd 0x12001600 0x15801580 0x11801780 0x17001780 Qm (i8)0xffffffff +vshll.u8 q15, d19, #3 :: Qd 0x00280028 0x00280028 0x00280028 0x00280028 Qm (i8)0x00000005 +vshll.u8 q15, d19, #3 :: Qd 0x01200160 0x01580158 0x01180178 0x01700178 Qm (i8)0x00000005 +vshll.u8 q5, d12, #6 :: Qd 0x20000000 0x00000040 0x20000000 0x00000040 Qm (i32)0x80000001 +vshll.u8 q5, d12, #6 :: Qd 0x09000b00 0x0ac00ac0 0x08c00bc0 0x0b800bc0 Qm (i32)0x80000001 +---- VSHLL (max shift) ---- +vshll.i32 q0, d1, #32 :: Qd 0x00000018 0x00000000 0x00000018 0x00000000 Qm (i32)0x00000018 +vshll.i32 q0, d1, #32 :: Qd 0x242c2b2b 0x00000000 0x232f2e2f 0x00000000 Qm (i32)0x00000018 +vshll.i32 q5, d2, #32 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x40000000 +vshll.i32 q5, d2, #32 :: Qd 0x242c2b2b 0x00000000 0x232f2e2f 0x00000000 Qm (i32)0x40000000 +vshll.i32 q11, d2, #32 :: Qd 0xffffffff 0x00000000 0xffffffff 0x00000000 Qm (i32)0xffffffff +vshll.i32 q11, d2, #32 :: Qd 0x242c2b2b 0x00000000 0x232f2e2f 0x00000000 Qm (i32)0xffffffff +vshll.i32 q15, d12, #32 :: Qd 0x00000005 0x00000000 0x00000005 0x00000000 Qm (i32)0x00000005 +vshll.i32 q15, d12, #32 :: Qd 0x242c2b2b 0x00000000 0x232f2e2f 0x00000000 Qm (i32)0x00000005 +vshll.i16 q0, d1, #16 :: Qd 0x00180000 0x00180000 0x00180000 0x00180000 Qm (i16)0x00000018 +vshll.i16 q0, d1, #16 :: Qd 0x242c0000 0x2b2b0000 0x232f0000 0x2e2f0000 Qm (i16)0x00000018 +vshll.i16 q5, d2, #16 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x40000000 +vshll.i16 q5, d2, #16 :: Qd 0x242c0000 0x2b2b0000 0x232f0000 0x2e2f0000 Qm (i32)0x40000000 +vshll.i16 q11, d2, #16 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i16)0xffffffff +vshll.i16 q11, d2, #16 :: Qd 0x242c0000 0x2b2b0000 0x232f0000 0x2e2f0000 Qm (i16)0xffffffff +vshll.i16 q15, d22, #16 :: Qd 0x00050000 0x00050000 0x00050000 0x00050000 Qm (i16)0x00000005 +vshll.i16 q15, d22, #16 :: Qd 0x242c0000 0x2b2b0000 0x232f0000 0x2e2f0000 Qm (i16)0x00000005 +vshll.i8 q0, d1, #8 :: Qd 0x18001800 0x18001800 0x18001800 0x18001800 Qm (i8)0x00000018 +vshll.i8 q0, d1, #8 :: Qd 0x24002c00 0x2b002b00 0x23002f00 0x2e002f00 Qm (i8)0x00000018 +vshll.i8 q5, d2, #8 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x40000000 +vshll.i8 q5, d2, #8 :: Qd 0x24002c00 0x2b002b00 0x23002f00 0x2e002f00 Qm (i32)0x40000000 +vshll.i8 q11, d2, #8 :: Qd 0xff00ff00 0xff00ff00 0xff00ff00 0xff00ff00 Qm (i8)0xffffffff +vshll.i8 q11, d2, #8 :: Qd 0x24002c00 0x2b002b00 0x23002f00 0x2e002f00 Qm (i8)0xffffffff +vshll.i8 q15, d19, #8 :: Qd 0x05000500 0x05000500 0x05000500 0x05000500 Qm (i8)0x00000005 +vshll.i8 q15, d19, #8 :: Qd 0x24002c00 0x2b002b00 0x23002f00 0x2e002f00 Qm (i8)0x00000005 +---- VMULL ---- +vmull.s8 q0, d1, d12 :: Qd 0x0000fe0c 0x01980d94 0x0000fe0c 0x01980d94 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmull.s8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmull.s8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmull.s8 q4, d5, d6 :: Qd 0x00000000 0xee48ed46 0x00000000 0xee48ed46 Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmull.s8 q4, d5, d6 :: Qd 0x00000000 0x0000ffa6 0x00000000 0x0000ffa6 Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmull.s8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmull.s8 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmull.u8 q0, d1, d12 :: Qd 0x0000080c 0xb7989294 0x0000080c 0xb7989294 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmull.u8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x18482046 0x00000000 0x18482046 Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x00002ca6 0x00000000 0x00002ca6 Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmull.u8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmull.u8 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmull.s16 q0, d1, d12 :: Qd 0x0000080c 0x01649694 0x0000080c 0x01649694 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmull.s16 q9, d11, d12 :: Qd 0x00000000 0x00016800 0x00000000 0x00016800 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmull.s16 q4, d5, d6 :: Qd 0x00000000 0xee0c2646 0x00000000 0xee0c2646 Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmull.s16 q4, d5, d6 :: Qd 0x0002b000 0xffdc74a6 0x0002b000 0xffdc74a6 Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmull.s16 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmull.s16 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmull.u16 q0, d1, d12 :: Qd 0x0000080c 0xb8e99694 0x0000080c 0xb8e99694 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmull.u16 q9, d11, d12 :: Qd 0x00000000 0x00016800 0x00000000 0x00016800 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmull.u16 q4, d5, d6 :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmull.u16 q4, d5, d6 :: Qd 0x00000000 0x18ae2646 0x00000000 0x18ae2646 Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmull.u16 q4, d5, d6 :: Qd 0x0002b000 0x00da74a6 0x0002b000 0x00da74a6 Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmull.u16 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmull.u16 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmull.s32 q0, d1, d2 :: Qd 0x000121f2 0xd7d30fa8 0x000121f2 0xd7d30fa8 Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a +vmull.s32 q6, d7, d8 :: Qd 0xffffffff 0xffffbe60 0xffffffff 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmull.s32 q7, d8, d9 :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmull.s32 q7, d8, d9 :: Qd 0xfffffffa 0x00000000 0xfffffffa 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmull.s32 q7, d8, d9 :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmull.s32 q10, d11, d15 :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmull.s32 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmull.s32 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 +vmull.u32 q0, d1, d2 :: Qd 0x000121f2 0xd7d30fa8 0x000121f2 0xd7d30fa8 Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a +vmull.u32 q6, d7, d8 :: Qd 0x0000008b 0xffffbe60 0x0000008b 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmull.u32 q7, d8, d9 :: Qd 0x40000001 0x80000002 0x40000001 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmull.u32 q7, d8, d9 :: Qd 0x00000006 0x00000000 0x00000006 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmull.u32 q7, d8, d9 :: Qd 0x40000001 0x80000002 0x40000001 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmull.u32 q10, d11, d15 :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmull.u32 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmull.u32 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 +vmull.p8 q9, d11, d12 :: Qd 0x00000a3a 0x3eb60440 0x00000a3a 0x3eb60440 Qm (i32)0x001a4b0c Qn (i32)0x00d1e2f0 +vmull.p8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmull.p8 q4, d15, d26 :: Qd 0x00000000 0x17081f86 0x00000000 0x17081f86 Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmull.p8 q14, d5, d6 :: Qd 0x00000000 0x04281b36 0x00000000 0x04281b36 Qm (i32)0x10000efe Qn (i32)0x002bdc2d +vmull.p8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmull.p8 q10, d27, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmull.p8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmull.p8 q4, d5, d6 :: Qd 0x00000000 0x00001b36 0x00000000 0x00001b36 Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmull.p8 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 +---- VMLAL ---- +vmlal.s8 q0, d1, d12 :: Qd 0x000abae0 0x01a2ca68 0x55555361 0x56ed62e9 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmlal.s8 q9, d11, d12 :: Qd 0x55555555 0x55565d55 0x55555555 0x55565d55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x5d555557 0x55555555 0x5d555557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x439d429b 0x55555555 0x439d429b Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x555554fb 0x55555555 0x555554fb Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmlal.s8 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlal.s8 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmlal.u8 q0, d1, d12 :: Qd 0x000ac4e0 0xb7a24f68 0x55555d61 0x0cede7e9 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmlal.u8 q9, d11, d12 :: Qd 0x55555555 0x55565d55 0x55555555 0x55565d55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x5d555557 0x55555555 0x5d555557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x6d9d759b 0x55555555 0x6d9d759b Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x555581fb 0x55555555 0x555581fb Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmlal.u8 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlal.u8 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmlal.s16 q0, d1, d12 :: Qd 0x000ac4e0 0x016f5368 0x55555d61 0x56b9ebe9 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmlal.s16 q9, d11, d12 :: Qd 0x55555555 0x5556bd55 0x55555555 0x5556bd55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x43617b9b 0x55555555 0x43617b9b Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmlal.s16 q4, d5, d6 :: Qd 0x55580555 0x5531c9fb 0x55580555 0x5531c9fb Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmlal.s16 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlal.s16 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmlal.u16 q0, d1, d12 :: Qd 0x000ac4e0 0xb8f45368 0x55555d61 0x0e3eebe9 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmlal.u16 q9, d11, d12 :: Qd 0x55555555 0x5556bd55 0x55555555 0x5556bd55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlal.u16 q4, d5, d6 :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlal.u16 q4, d5, d6 :: Qd 0x55555555 0x6e037b9b 0x55555555 0x6e037b9b Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmlal.u16 q4, d5, d6 :: Qd 0x55580555 0x562fc9fb 0x55580555 0x562fc9fb Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmlal.u16 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlal.u16 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmlal.s32 q0, d1, d2 :: Qd 0x0aacdeb6 0xe27ecc6c 0x55567748 0x2d2864fd Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a +vmlal.s32 q6, d7, d8 :: Qd 0x55555555 0x555513b5 0x55555555 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmlal.s32 q7, d8, d9 :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlal.s32 q7, d8, d9 :: Qd 0x5555554f 0x55555555 0x5555554f 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmlal.s32 q7, d8, d9 :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlal.s32 q10, d11, d15 :: Qd 0x55555555 0x55556095 0x55555555 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmlal.s32 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlal.s32 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 +vmlal.u32 q0, d1, d2 :: Qd 0x0aacdeb6 0xe27ecc6c 0x55567748 0x2d2864fd Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a +vmlal.u32 q6, d7, d8 :: Qd 0x555555e1 0x555513b5 0x555555e1 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmlal.u32 q7, d8, d9 :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlal.u32 q7, d8, d9 :: Qd 0x5555555b 0x55555555 0x5555555b 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmlal.u32 q7, d8, d9 :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlal.u32 q10, d11, d15 :: Qd 0x55555555 0x55556095 0x55555555 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmlal.u32 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlal.u32 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 +---- VMLSL ---- +vmlsl.s8 q0, d1, d12 :: Qd 0x000abec8 0xfe72af40 0x55555749 0x53bd47c1 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmlsl.s8 q9, d11, d12 :: Qd 0x55555555 0x55544d55 0x55555555 0x55544d55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x4d555553 0x55555555 0x4d555553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x670d680f 0x55555555 0x670d680f Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x555555af 0x55555555 0x555555af Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmlsl.s8 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlsl.s8 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmlsl.u8 q0, d1, d12 :: Qd 0x000ab4c8 0x48722a40 0x55554d49 0x9dbdc2c1 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmlsl.u8 q9, d11, d12 :: Qd 0x55555555 0x55544d55 0x55555555 0x55544d55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x4d555553 0x55555555 0x4d555553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x3d0d350f 0x55555555 0x3d0d350f Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x555528af 0x55555555 0x555528af Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmlsl.u8 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlsl.u8 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmlsl.s16 q0, d1, d12 :: Qd 0x000ab4c8 0xfea62640 0x55554d49 0x53f0bec1 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmlsl.s16 q9, d11, d12 :: Qd 0x55555555 0x5553ed55 0x55555555 0x5553ed55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x67492f0f 0x55555555 0x67492f0f Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmlsl.s16 q4, d5, d6 :: Qd 0x5552a555 0x5578e0af 0x5552a555 0x5578e0af Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmlsl.s16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlsl.s16 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmlsl.u16 q0, d1, d12 :: Qd 0x000ab4c8 0x47212640 0x55554d49 0x9c6bbec1 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1 +vmlsl.u16 q9, d11, d12 :: Qd 0x55555555 0x5553ed55 0x55555555 0x5553ed55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmlsl.u16 q4, d5, d6 :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmlsl.u16 q4, d5, d6 :: Qd 0x55555555 0x3ca72f0f 0x55555555 0x3ca72f0f Qm (i32)0xffff9433 Qn (i32)0x00002aa2 +vmlsl.u16 q4, d5, d6 :: Qd 0x5552a555 0x547ae0af 0x5552a555 0x547ae0af Qm (i32)0x100000fe Qn (i32)0x002bdc2d +vmlsl.u16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlsl.u16 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 +vmlsl.s32 q0, d1, d2 :: Qd 0x0aaa9ad1 0x32d8ad1c 0x55543362 0x7d8245ad Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a +vmlsl.s32 q6, d7, d8 :: Qd 0x55555555 0x555596f5 0x55555555 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmlsl.s32 q7, d8, d9 :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlsl.s32 q7, d8, d9 :: Qd 0x5555555b 0x55555555 0x5555555b 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmlsl.s32 q7, d8, d9 :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlsl.s32 q10, d11, d15 :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmlsl.s32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlsl.s32 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 +vmlsl.u32 q0, d1, d2 :: Qd 0x0aaa9ad1 0x32d8ad1c 0x55543362 0x7d8245ad Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a +vmlsl.u32 q6, d7, d8 :: Qd 0x555554c9 0x555596f5 0x555554c9 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmlsl.u32 q7, d8, d9 :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlsl.u32 q7, d8, d9 :: Qd 0x5555554f 0x55555555 0x5555554f 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmlsl.u32 q7, d8, d9 :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmlsl.u32 q10, d11, d15 :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmlsl.u32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 +vmlsl.u32 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 +---- VQRDMULH ---- +vqrdmulh.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q0, q1, q2 :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q0, q1, q2 :: Qd 0x00000014 0x00000013 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q6, q7, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s32 q6, q7, q8 :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s32 q6, q7, q8 :: Qd 0xffffffec 0xffffffed 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s16 q9, q11, q12 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 q9, q11, q12 :: Qd 0x0000003b 0x00000044 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 q9, q11, q12 :: Qd 0x00000039 0x00000046 0x0000003b 0x00000044 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x00001001 0x00001001 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000687 0x00000788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000648 0x000007c7 0x00000687 0x00000788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000687 0x00000788 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000648 0x000007c7 0x00000687 0x00000788 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000687 0x00000788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000648 0x000007c7 0x00000687 0x00000788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, q9 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q10, q11, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q10, q11, q15 :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q10, q11, q15 :: Qd 0x00000014 0x00000013 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 00000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 00000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 00000000 +vqrdmulh.s16 q10, q14, q15 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqrdmulh.s16 q10, q14, q15 :: Qd 0xece50000 0xede10000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s16 q10, q14, q15 :: Qd 0xeae30000 0xebe40000 0xece50000 0xede10000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, q15 :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s16 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqrdmulh.s16 q10, q14, q15 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqrdmulh.s16 q10, q14, q15 :: Qd 0x0a8f0000 0x0a0e0000 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQRDMULH (by scalar) ---- +vqrdmulh.s32 q0, q1, d6[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q0, q1, d6[0] :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q0, q1, d6[0] :: Qd 0x00000014 0x00000013 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q6, q7, d1[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s32 q6, q7, d1[1] :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s32 q6, q7, d1[1] :: Qd 0xffffffec 0xffffffed 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s16 q9, q11, d7[0] :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 q9, q11, d7[0] :: Qd 0x002b003b 0x00290044 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 q9, q11, d7[0] :: Qd 0x00300039 0x002d0046 0x002b003b 0x00290044 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[0] :: Qd 0x00001001 0x00001001 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[0] :: Qd 0x04c70687 0x04880788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[0] :: Qd 0x05480648 0x050707c7 0x04c70687 0x04880788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[1] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[1] :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[1] :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[1] :: Qd 0x04c70687 0x04880788 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[1] :: Qd 0x05480648 0x050707c7 0x04c70687 0x04880788 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[0] :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[0] :: Qd 0x00000002 0x00000002 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[0] :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[2] :: Qd 0x04000040 0x04000040 0x04000040 0x04000040 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[2] :: Qd 0x04c70687 0x04880788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 q4, q5, d6[2] :: Qd 0x05480648 0x050707c7 0x04c70687 0x04880788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[0] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q7, q8, d9[0] :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 q10, q11, d15[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q10, q11, d15[0] :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q10, q11, d15[0] :: Qd 0x00000014 0x00000013 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 q10, q14, d15[1] :: Qd 0xffffff88 0xffffff88 0xffffff88 0xffffff88 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, d15[1] :: Qd 0x00000012 0x00000011 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, d15[1] :: Qd 0x00000014 0x00000013 0x00000012 0x00000011 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s16 q10, q14, d7[3] :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 08000000 +vqrdmulh.s16 q10, q14, d7[3] :: Qd 0xece5e5e5 0xede1e1e1 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 00000000 +vqrdmulh.s16 q10, q14, d7[3] :: Qd 0xeae3e6e3 0xebe4e0e4 0xece5e5e5 0xede1e1e1 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 00000000 +vqrdmulh.s32 q10, q14, d15[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, d15[1] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 q10, q14, d15[1] :: Qd 0xeae2e6e3 0xebe3e0e4 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s16 q10, q14, d7[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqrdmulh.s16 q10, q14, d7[1] :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqrdmulh.s16 q10, q14, d7[1] :: Qd 0x0a8f0c8f 0x0a0e0f8e 0x098e0d0e 0x09100f10 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VADD (fp) ---- +vadd.f32 q0, q5, q2 :: Qd 0xc1b43ac6 0xc1b43ac6 0xc1b43ac6 0xc1b43ac6 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vadd.f32 q3, q4, q5 :: Qd 0xc8a931cf 0xc8a931cf 0xc8a931cf 0xc8a931cf Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vadd.f32 q10, q11, q2 :: Qd 0x45398860 0x45398860 0x45398860 0x45398860 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vadd.f32 q9, q5, q7 :: Qd 0x47dc9261 0x47dc9261 0x47dc9261 0x47dc9261 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vadd.f32 q0, q5, q2 :: Qd 0xc88faac0 0xc88faac0 0xc88faac0 0xc88faac0 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vadd.f32 q3, q4, q5 :: Qd 0x44ab4000 0x44ab4000 0x44ab4000 0x44ab4000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vadd.f32 q10, q11, q2 :: Qd 0x4742b400 0x4742b400 0x4742b400 0x4742b400 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vadd.f32 q9, q5, q7 :: Qd 0x49d5e6b8 0x49d5e6b8 0x49d5e6b8 0x49d5e6b8 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vadd.f32 q0, q11, q12 :: Qd 0x48b0b752 0x48b0b752 0x48b0b752 0x48b0b752 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vadd.f32 q7, q1, q6 :: Qd 0x420802fd 0x420802fd 0x420802fd 0x420802fd Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vadd.f32 q0, q1, q2 :: Qd 0x4532d000 0x4532d000 0x4532d000 0x4532d000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vadd.f32 q3, q4, q5 :: Qd 0x450d299a 0x450d299a 0x450d299a 0x450d299a Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vadd.f32 q10, q11, q2 :: Qd 0x44152592 0x44152592 0x44152592 0x44152592 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vadd.f32 q9, q5, q7 :: Qd 0x4573a000 0x4573a000 0x4573a000 0x4573a000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vadd.f32 q0, q11, q12 :: Qd 0xc5b695c3 0xc5b695c3 0xc5b695c3 0xc5b695c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vadd.f32 q7, q1, q6 :: Qd 0x43e07a2a 0x43e07a2a 0x43e07a2a 0x43e07a2a Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vadd.f32 q0, q5, q2 :: Qd 0x44053ee0 0x44053ee0 0x44053ee0 0x44053ee0 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vadd.f32 q10, q13, q15 :: Qd 0xc4838fb4 0xc4838fb4 0xc4838fb4 0xc4838fb4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vadd.f32 q10, q13, q15 :: Qd 0x488c3d8e 0x488c3d8e 0x488c3d8e 0x488c3d8e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vadd.f32 q0, q1, q2 :: Qd 0x4efa8dc5 0x4efa8dc5 0x4efa8dc5 0x4efa8dc5 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vadd.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vadd.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VSUB (fp) ---- +vsub.f32 q0, q5, q2 :: Qd 0x428937a8 0x428937a8 0x428937a8 0x428937a8 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vsub.f32 q3, q4, q5 :: Qd 0xc8aa824f 0xc8aa824f 0xc8aa824f 0xc8aa824f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vsub.f32 q10, q11, q2 :: Qd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vsub.f32 q9, q5, q7 :: Qd 0x4799e961 0x4799e961 0x4799e961 0x4799e961 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vsub.f32 q0, q5, q2 :: Qd 0x484623e2 0x484623e2 0x484623e2 0x484623e2 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vsub.f32 q3, q4, q5 :: Qd 0xc4a52385 0xc4a52385 0xc4a52385 0xc4a52385 Qm (i32)0x41c71eb8 Qn (i32)0x44a84000 +vsub.f32 q10, q11, q2 :: Qd 0x473a3200 0x473a3200 0x473a3200 0x473a3200 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vsub.f32 q9, q5, q7 :: Qd 0xc9d5d958 0xc9d5d958 0xc9d5d958 0xc9d5d958 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vsub.f32 q0, q11, q12 :: Qd 0x48aafc92 0x48aafc92 0x48aafc92 0x48aafc92 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vsub.f32 q7, q1, q6 :: Qd 0x4207fdf5 0x4207fdf5 0x4207fdf5 0x4207fdf5 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vsub.f32 q0, q1, q2 :: Qd 0x45257000 0x45257000 0x45257000 0x45257000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vsub.f32 q3, q4, q5 :: Qd 0xc3ff4ccc 0xc3ff4ccc 0xc3ff4ccc 0xc3ff4ccc Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vsub.f32 q10, q11, q2 :: Qd 0x43bd4b23 0x43bd4b23 0x43bd4b23 0x43bd4b23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vsub.f32 q9, q5, q7 :: Qd 0x43c50000 0x43c50000 0x43c50000 0x43c50000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vsub.f32 q0, q11, q12 :: Qd 0x45b311c3 0x45b311c3 0x45b311c3 0x45b311c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vsub.f32 q7, q1, q6 :: Qd 0x43e7c592 0x43e7c592 0x43e7c592 0x43e7c592 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vsub.f32 q0, q5, q2 :: Qd 0x44053f76 0x44053f76 0x44053f76 0x44053f76 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vsub.f32 q10, q13, q15 :: Qd 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vsub.f32 q10, q13, q15 :: Qd 0x4883b08e 0x4883b08e 0x4883b08e 0x4883b08e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vsub.f32 q0, q1, q2 :: Qd 0xcda5da84 0xcda5da84 0xcda5da84 0xcda5da84 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vsub.f32 q0, q1, q2 :: Qd 0xbf800000 0xbf800000 0xbf800000 0xbf800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vsub.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VABD (fp) ---- +vabd.f32 q0, q5, q2 :: Qd 0x428937a8 0x428937a8 0x428937a8 0x428937a8 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vabd.f32 q3, q4, q5 :: Qd 0x48aa824f 0x48aa824f 0x48aa824f 0x48aa824f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vabd.f32 q10, q11, q2 :: Qd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vabd.f32 q9, q5, q7 :: Qd 0x4799e961 0x4799e961 0x4799e961 0x4799e961 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vabd.f32 q0, q5, q2 :: Qd 0x484623e2 0x484623e2 0x484623e2 0x484623e2 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vabd.f32 q3, q4, q5 :: Qd 0x44a54000 0x44a54000 0x44a54000 0x44a54000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vabd.f32 q10, q11, q2 :: Qd 0x473a3200 0x473a3200 0x473a3200 0x473a3200 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vabd.f32 q9, q5, q7 :: Qd 0x49d5d958 0x49d5d958 0x49d5d958 0x49d5d958 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vabd.f32 q0, q11, q12 :: Qd 0x48aafc92 0x48aafc92 0x48aafc92 0x48aafc92 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vabd.f32 q7, q1, q6 :: Qd 0x4207fdf5 0x4207fdf5 0x4207fdf5 0x4207fdf5 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vabd.f32 q0, q1, q2 :: Qd 0x45257000 0x45257000 0x45257000 0x45257000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vabd.f32 q3, q4, q5 :: Qd 0x43ff4ccc 0x43ff4ccc 0x43ff4ccc 0x43ff4ccc Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vabd.f32 q10, q11, q2 :: Qd 0x43bd4b23 0x43bd4b23 0x43bd4b23 0x43bd4b23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vabd.f32 q9, q5, q7 :: Qd 0x43c50000 0x43c50000 0x43c50000 0x43c50000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vabd.f32 q0, q11, q12 :: Qd 0x45b311c3 0x45b311c3 0x45b311c3 0x45b311c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vabd.f32 q7, q1, q6 :: Qd 0x43e7c592 0x43e7c592 0x43e7c592 0x43e7c592 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vabd.f32 q0, q5, q2 :: Qd 0x44053f76 0x44053f76 0x44053f76 0x44053f76 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vabd.f32 q10, q13, q15 :: Qd 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vabd.f32 q10, q13, q15 :: Qd 0x4883b08e 0x4883b08e 0x4883b08e 0x4883b08e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vabd.f32 q0, q1, q2 :: Qd 0x4da5da84 0x4da5da84 0x4da5da84 0x4da5da84 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vabd.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vabd.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMUL (fp) ---- +vmul.f32 q0, q5, q2 :: Qd 0xc4833ce4 0xc4833ce4 0xc4833ce4 0xc4833ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmul.f32 q3, q4, q5 :: Qd 0xcddf4321 0xcddf4321 0xcddf4321 0xcddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmul.f32 q10, q11, q2 :: Qd 0xcf050e7f 0xcf050e7f 0xcf050e7f 0xcf050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmul.f32 q9, q5, q7 :: Qd 0x4ec3063f 0x4ec3063f 0x4ec3063f 0x4ec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmul.f32 q0, q5, q2 :: Qd 0x5029254c 0x5029254c 0x5029254c 0x5029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmul.f32 q3, q4, q5 :: Qd 0x46fc6000 0x46fc6000 0x46fc6000 0x46fc6000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmul.f32 q10, q11, q2 :: Qd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmul.f32 q9, q5, q7 :: Qd 0x4db2c947 0x4db2c947 0x4db2c947 0x4db2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmul.f32 q0, q11, q12 :: Qd 0x4ef90536 0x4ef90536 0x4ef90536 0x4ef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmul.f32 q7, q1, q6 :: Qd 0x3dab1f7a 0x3dab1f7a 0x3dab1f7a 0x3dab1f7a Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmul.f32 q0, q1, q2 :: Qd 0x488fe2c0 0x488fe2c0 0x488fe2c0 0x488fe2c0 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmul.f32 q3, q4, q5 :: Qd 0x4993b8e3 0x4993b8e3 0x4993b8e3 0x4993b8e3 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmul.f32 q10, q11, q2 :: Qd 0x474f9afc 0x474f9afc 0x474f9afc 0x474f9afc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmul.f32 q9, q5, q7 :: Qd 0x4a657ac0 0x4a657ac0 0x4a657ac0 0x4a657ac0 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmul.f32 q0, q11, q12 :: Qd 0x489eee1e 0x489eee1e 0x489eee1e 0x489eee1e Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmul.f32 q7, q1, q6 :: Qd 0xc5500239 0xc5500239 0xc5500239 0xc5500239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmul.f32 q0, q5, q2 :: Qd 0xc01c7d07 0xc01c7d07 0xc01c7d07 0xc01c7d07 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmul.f32 q10, q13, q15 :: Qd 0x488666a6 0x488666a6 0x488666a6 0x488666a6 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmul.f32 q10, q13, q15 :: Qd 0x4f115379 0x4f115379 0x4f115379 0x4f115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmul.f32 q0, q1, q2 :: Qd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmul.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmul.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMLA (fp) ---- +vmla.f32 q0, q5, q2 :: Qd 0xc4831ce4 0xc4831ce4 0xc4831ce4 0xc4831ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmla.f32 q0, q5, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmla.f32 q3, q4, q5 :: Qd 0xcddf4321 0xcddf4321 0xcddf4321 0xcddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmla.f32 q3, q4, q5 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmla.f32 q10, q11, q2 :: Qd 0xcf050e7f 0xcf050e7f 0xcf050e7f 0xcf050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmla.f32 q10, q11, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmla.f32 q9, q5, q7 :: Qd 0x4ec3063f 0x4ec3063f 0x4ec3063f 0x4ec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmla.f32 q9, q5, q7 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmla.f32 q0, q5, q2 :: Qd 0x5029254c 0x5029254c 0x5029254c 0x5029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmla.f32 q0, q5, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmla.f32 q3, q4, q5 :: Qd 0x46fc6200 0x46fc6200 0x46fc6200 0x46fc6200 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmla.f32 q3, q4, q5 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmla.f32 q10, q11, q2 :: Qd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmla.f32 q10, q11, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmla.f32 q9, q5, q7 :: Qd 0x4db2c947 0x4db2c947 0x4db2c947 0x4db2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmla.f32 q9, q5, q7 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmla.f32 q0, q11, q12 :: Qd 0x4ef90536 0x4ef90536 0x4ef90536 0x4ef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmla.f32 q0, q11, q12 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmla.f32 q7, q1, q6 :: Qd 0x3f8ab1f8 0x3f8ab1f8 0x3f8ab1f8 0x3f8ab1f8 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmla.f32 q7, q1, q6 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmla.f32 q0, q1, q2 :: Qd 0x488fe2e0 0x488fe2e0 0x488fe2e0 0x488fe2e0 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmla.f32 q3, q4, q5 :: Qd 0x4993b8eb 0x4993b8eb 0x4993b8eb 0x4993b8eb Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmla.f32 q3, q4, q5 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmla.f32 q10, q11, q2 :: Qd 0x474f9bfc 0x474f9bfc 0x474f9bfc 0x474f9bfc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmla.f32 q10, q11, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmla.f32 q9, q5, q7 :: Qd 0x4a657ac4 0x4a657ac4 0x4a657ac4 0x4a657ac4 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmla.f32 q9, q5, q7 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmla.f32 q0, q11, q12 :: Qd 0x489eee3e 0x489eee3e 0x489eee3e 0x489eee3e Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmla.f32 q0, q11, q12 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmla.f32 q7, q1, q6 :: Qd 0xc54ff239 0xc54ff239 0xc54ff239 0xc54ff239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmla.f32 q7, q1, q6 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmla.f32 q0, q5, q2 :: Qd 0xbfb8fa0e 0xbfb8fa0e 0xbfb8fa0e 0xbfb8fa0e Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmla.f32 q0, q5, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmla.f32 q10, q13, q15 :: Qd 0x488666c6 0x488666c6 0x488666c6 0x488666c6 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmla.f32 q10, q13, q15 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmla.f32 q10, q13, q15 :: Qd 0x4f115379 0x4f115379 0x4f115379 0x4f115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmla.f32 q10, q13, q15 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmla.f32 q0, q1, q2 :: Qd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMLA (fp by scalar) ---- +vmla.f32 q0, q1, d4[0] :: Qd 0x45341000 0x45341000 0x45341000 0x45341000 Qm (i32)0x41c00000 Qn (i32)0x42f00000 +vmla.f32 q0, q1, d4[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x41c00000 Qn (i32)0x42f00000 +vmla.f32 q15, q8, d7[1] :: Qd 0xc6833e00 0xc6833e00 0xc6833e00 0xc6833e00 Qm (i32)0x430c0000 Qn (i32)0xc2f00000 +vmla.f32 q15, q8, d7[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x430c0000 Qn (i32)0xc2f00000 +vmla.f32 q4, q8, d15[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.f32 q4, q8, d15[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmla.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmla.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.f32 q7, q8, d1[0] :: Qd 0x447a3fff 0x447a3fff 0x447a3fff 0x447a3fff Qm (i32)0x64078678 Qn (i32)0x1fec1e4a +vmla.f32 q7, q8, d1[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x64078678 Qn (i32)0x1fec1e4a +vmla.f32 q7, q8, d1[0] :: Qd 0x65a96816 0x65a96816 0x65a96816 0x65a96816 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7 +vmla.f32 q7, q8, d1[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x40000000 0x40000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x40000000 0x40000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x40000000 0x40000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x40000000 0x40000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x40000000 0x40000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x40000000 0x40000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMLS (fp) ---- +vmls.f32 q0, q5, q2 :: Qd 0x44835ce4 0x44835ce4 0x44835ce4 0x44835ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmls.f32 q0, q5, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmls.f32 q3, q4, q5 :: Qd 0x4ddf4321 0x4ddf4321 0x4ddf4321 0x4ddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmls.f32 q3, q4, q5 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmls.f32 q10, q11, q2 :: Qd 0x4f050e7f 0x4f050e7f 0x4f050e7f 0x4f050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmls.f32 q10, q11, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmls.f32 q9, q5, q7 :: Qd 0xcec3063f 0xcec3063f 0xcec3063f 0xcec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmls.f32 q9, q5, q7 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmls.f32 q0, q5, q2 :: Qd 0xd029254c 0xd029254c 0xd029254c 0xd029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmls.f32 q0, q5, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmls.f32 q3, q4, q5 :: Qd 0xc6fc5e00 0xc6fc5e00 0xc6fc5e00 0xc6fc5e00 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmls.f32 q3, q4, q5 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmls.f32 q10, q11, q2 :: Qd 0xcc4a89cd 0xcc4a89cd 0xcc4a89cd 0xcc4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmls.f32 q10, q11, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmls.f32 q9, q5, q7 :: Qd 0xcdb2c947 0xcdb2c947 0xcdb2c947 0xcdb2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmls.f32 q9, q5, q7 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmls.f32 q0, q11, q12 :: Qd 0xcef90536 0xcef90536 0xcef90536 0xcef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmls.f32 q0, q11, q12 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmls.f32 q7, q1, q6 :: Qd 0x3f6a9c11 0x3f6a9c11 0x3f6a9c11 0x3f6a9c11 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmls.f32 q7, q1, q6 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmls.f32 q0, q1, q2 :: Qd 0xc88fe2a0 0xc88fe2a0 0xc88fe2a0 0xc88fe2a0 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmls.f32 q3, q4, q5 :: Qd 0xc993b8db 0xc993b8db 0xc993b8db 0xc993b8db Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmls.f32 q3, q4, q5 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmls.f32 q10, q11, q2 :: Qd 0xc74f99fc 0xc74f99fc 0xc74f99fc 0xc74f99fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmls.f32 q10, q11, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmls.f32 q9, q5, q7 :: Qd 0xca657abc 0xca657abc 0xca657abc 0xca657abc Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmls.f32 q9, q5, q7 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmls.f32 q0, q11, q12 :: Qd 0xc89eedfe 0xc89eedfe 0xc89eedfe 0xc89eedfe Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmls.f32 q0, q11, q12 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmls.f32 q7, q1, q6 :: Qd 0x45501239 0x45501239 0x45501239 0x45501239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmls.f32 q7, q1, q6 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmls.f32 q0, q5, q2 :: Qd 0x405c7d07 0x405c7d07 0x405c7d07 0x405c7d07 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmls.f32 q0, q5, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmls.f32 q10, q13, q15 :: Qd 0xc8866686 0xc8866686 0xc8866686 0xc8866686 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmls.f32 q10, q13, q15 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmls.f32 q10, q13, q15 :: Qd 0xcf115379 0xcf115379 0xcf115379 0xcf115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmls.f32 q10, q13, q15 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmls.f32 q0, q1, q2 :: Qd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMLS (fp by scalar) ---- +vmls.f32 q0, q1, d4[0] :: Qd 0xc533f000 0xc533f000 0xc533f000 0xc533f000 Qm (i32)0x41c00000 Qn (i32)0x42f00000 +vmls.f32 q0, q1, d4[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x41c00000 Qn (i32)0x42f00000 +vmls.f32 q15, q8, d7[1] :: Qd 0x46834200 0x46834200 0x46834200 0x46834200 Qm (i32)0x430c0000 Qn (i32)0xc2f00000 +vmls.f32 q15, q8, d7[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x430c0000 Qn (i32)0xc2f00000 +vmls.f32 q4, q8, d15[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.f32 q4, q8, d15[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmls.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmls.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.f32 q7, q8, d1[0] :: Qd 0xc479bfff 0xc479bfff 0xc479bfff 0xc479bfff Qm (i32)0x64078678 Qn (i32)0x1fec1e4a +vmls.f32 q7, q8, d1[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x64078678 Qn (i32)0x1fec1e4a +vmls.f32 q7, q8, d1[0] :: Qd 0xe5a96816 0xe5a96816 0xe5a96816 0xe5a96816 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7 +vmls.f32 q7, q8, d1[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VCVT (integer <-> fp) ---- +vcvt.u32.f32 q0, q1 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x404ccccd +vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x404ccccd +vcvt.u32.f32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vcvt.u32.f32 q10, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x64cb49b4 +vcvt.u32.f32 q15, q4 :: Qd 0xb2d05e00 0xb2d05e00 0xb2d05e00 0xb2d05e00 Qm (i32)0x4f32d05e +vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4f32d05e +vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.u32.f32 q12, q8 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x40fff800 +vcvt.u32.f32 q12, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x40fff800 +vcvt.u32.f32 q12, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.u32.f32 q12, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.s32.f32 q0, q1 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x404ccccd +vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x404ccccd +vcvt.s32.f32 q10, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x64cb49b4 +vcvt.s32.f32 q10, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x64cb49b4 +vcvt.s32.f32 q15, q4 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x4f32d05e +vcvt.s32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4f32d05e +vcvt.s32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.s32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.s32.f32 q15, q4 :: Qd 0xfffffff9 0xfffffff9 0xfffffff9 0xfffffff9 Qm (i32)0xc0e33333 +vcvt.s32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.s32.f32 q12, q8 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x40fff800 +vcvt.s32.f32 q12, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x40fff800 +vcvt.s32.f32 q12, q8 :: Qd 0xfffffff9 0xfffffff9 0xfffffff9 0xfffffff9 Qm (i32)0xc0fff800 +vcvt.s32.f32 q12, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.f32.u32 q0, q1 :: Qd 0x40e00000 0x40e00000 0x40e00000 0x40e00000 Qm (i32)0x00000007 +vcvt.f32.u32 q0, q1 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x00000007 +vcvt.f32.u32 q10, q11 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000 Qm (i32)0x80000000 +vcvt.f32.u32 q10, q11 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x80000000 +vcvt.f32.u32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000 Qm (i32)0x80000001 +vcvt.f32.u32 q0, q1 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x80000001 +vcvt.f32.u32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000 Qm (i32)0x7fffffff +vcvt.f32.u32 q0, q1 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x7fffffff +vcvt.f32.u32 q0, q14 :: Qd 0x4e4282f4 0x4e4282f4 0x4e4282f4 0x4e4282f4 Qm (i32)0x30a0bcef +vcvt.f32.u32 q0, q14 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x30a0bcef +vcvt.f32.s32 q0, q1 :: Qd 0x40e00000 0x40e00000 0x40e00000 0x40e00000 Qm (i32)0x00000007 +vcvt.f32.s32 q0, q1 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x00000007 +vcvt.f32.s32 q10, q11 :: Qd 0xcf000000 0xcf000000 0xcf000000 0xcf000000 Qm (i32)0x80000000 +vcvt.f32.s32 q10, q11 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x80000000 +vcvt.f32.s32 q0, q1 :: Qd 0xcf000000 0xcf000000 0xcf000000 0xcf000000 Qm (i32)0x80000001 +vcvt.f32.s32 q0, q1 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x80000001 +vcvt.f32.s32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000 Qm (i32)0x7fffffff +vcvt.f32.s32 q0, q1 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x7fffffff +vcvt.f32.s32 q0, q14 :: Qd 0x4e4282f4 0x4e4282f4 0x4e4282f4 0x4e4282f4 Qm (i32)0x30a0bcef +vcvt.f32.s32 q0, q14 :: Qd 0x4e18b4b5 0x4e14a8b9 0x4e10b0ad 0x4e0cbcb9 Qm (i32)0x30a0bcef +vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.u32.f32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.s32.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x7f800000 +vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcvt.s32.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xff800000 +vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VCVT (fixed <-> fp) ---- +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019 Qm (i32)0x404ccccd +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x404ccccd +vcvt.u32.f32 q10, q11, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vcvt.u32.f32 q10, q11, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x64cb49b4 +vcvt.u32.f32 q15, q4, #32 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vcvt.u32.f32 q15, q4, #32 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4f32d05e +vcvt.u32.f32 q15, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.u32.f32 q15, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.u32.f32 q15, q4, #4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.u32.f32 q15, q4, #4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.u32.f32 q12, q8, #3 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f Qm (i32)0x40fff800 +vcvt.u32.f32 q12, q8, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x40fff800 +vcvt.u32.f32 q12, q8, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.u32.f32 q12, q8, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.s32.f32 q0, q1, #5 :: Qd 0x00000066 0x00000066 0x00000066 0x00000066 Qm (i32)0x404ccccd +vcvt.s32.f32 q0, q1, #5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x404ccccd +vcvt.s32.f32 q10, q11, #1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x64cb49b4 +vcvt.s32.f32 q10, q11, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x64cb49b4 +vcvt.s32.f32 q15, q4, #8 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x4f32d05e +vcvt.s32.f32 q15, q4, #8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4f32d05e +vcvt.s32.f32 q15, q4, #2 :: Qd 0xfffffffe 0xfffffffe 0xfffffffe 0xfffffffe Qm (i32)0xbf000000 +vcvt.s32.f32 q15, q4, #2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.s32.f32 q15, q4, #1 :: Qd 0xfffffff2 0xfffffff2 0xfffffff2 0xfffffff2 Qm (i32)0xc0e33333 +vcvt.s32.f32 q15, q4, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.s32.f32 q12, q8, #2 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f Qm (i32)0x40fff800 +vcvt.s32.f32 q12, q8, #2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x40fff800 +vcvt.s32.f32 q12, q8, #2 :: Qd 0xffffffe1 0xffffffe1 0xffffffe1 0xffffffe1 Qm (i32)0xc0fff800 +vcvt.s32.f32 q12, q8, #2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.f32.u32 q0, q1, #5 :: Qd 0x3e600000 0x3e600000 0x3e600000 0x3e600000 Qm (i32)0x00000007 +vcvt.f32.u32 q0, q1, #5 :: Qd 0x4b98b4b5 0x4b94a8b9 0x4b90b0ad 0x4b8cbcb9 Qm (i32)0x00000007 +vcvt.f32.u32 q10, q11, #9 :: Qd 0x4a800000 0x4a800000 0x4a800000 0x4a800000 Qm (i32)0x80000000 +vcvt.f32.u32 q10, q11, #9 :: Qd 0x4998b4b5 0x4994a8b9 0x4990b0ad 0x498cbcb9 Qm (i32)0x80000000 +vcvt.f32.u32 q0, q1, #4 :: Qd 0x4d000000 0x4d000000 0x4d000000 0x4d000000 Qm (i32)0x80000001 +vcvt.f32.u32 q0, q1, #4 :: Qd 0x4c18b4b5 0x4c14a8b9 0x4c10b0ad 0x4c0cbcb9 Qm (i32)0x80000001 +vcvt.f32.u32 q0, q1, #6 :: Qd 0x4c000000 0x4c000000 0x4c000000 0x4c000000 Qm (i32)0x7fffffff +vcvt.f32.u32 q0, q1, #6 :: Qd 0x4b18b4b5 0x4b14a8b9 0x4b10b0ad 0x4b0cbcb9 Qm (i32)0x7fffffff +vcvt.f32.u32 q0, q14, #5 :: Qd 0x4bc282f4 0x4bc282f4 0x4bc282f4 0x4bc282f4 Qm (i32)0x30a0bcef +vcvt.f32.u32 q0, q14, #5 :: Qd 0x4b98b4b5 0x4b94a8b9 0x4b90b0ad 0x4b8cbcb9 Qm (i32)0x30a0bcef +vcvt.f32.s32 q0, q1, #12 :: Qd 0x3ae00000 0x3ae00000 0x3ae00000 0x3ae00000 Qm (i32)0x00000007 +vcvt.f32.s32 q0, q1, #12 :: Qd 0x4818b4b5 0x4814a8b9 0x4810b0ad 0x480cbcb9 Qm (i32)0x00000007 +vcvt.f32.s32 q10, q11, #8 :: Qd 0xcb000000 0xcb000000 0xcb000000 0xcb000000 Qm (i32)0x80000000 +vcvt.f32.s32 q10, q11, #8 :: Qd 0x4a18b4b5 0x4a14a8b9 0x4a10b0ad 0x4a0cbcb9 Qm (i32)0x80000000 +vcvt.f32.s32 q0, q1, #2 :: Qd 0xce000000 0xce000000 0xce000000 0xce000000 Qm (i32)0x80000001 +vcvt.f32.s32 q0, q1, #2 :: Qd 0x4d18b4b5 0x4d14a8b9 0x4d10b0ad 0x4d0cbcb9 Qm (i32)0x80000001 +vcvt.f32.s32 q0, q1, #1 :: Qd 0x4e800000 0x4e800000 0x4e800000 0x4e800000 Qm (i32)0x7fffffff +vcvt.f32.s32 q0, q1, #1 :: Qd 0x4d98b4b5 0x4d94a8b9 0x4d90b0ad 0x4d8cbcb9 Qm (i32)0x7fffffff +vcvt.f32.s32 q0, q14, #6 :: Qd 0x4b4282f4 0x4b4282f4 0x4b4282f4 0x4b4282f4 Qm (i32)0x30a0bcef +vcvt.f32.s32 q0, q14, #6 :: Qd 0x4b18b4b5 0x4b14a8b9 0x4b10b0ad 0x4b0cbcb9 Qm (i32)0x30a0bcef +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.u32.f32 q0, q1, #3 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.s32.f32 q0, q1, #3 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x7f800000 +vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcvt.s32.f32 q0, q1, #3 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xff800000 +vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VMAX (fp) ---- +vmax.f32 q0, q5, q2 :: Qd 0x41b851ec 0x41b851ec 0x41b851ec 0x41b851ec Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmax.f32 q3, q4, q5 :: Qd 0x44a84000 0x44a84000 0x44a84000 0x44a84000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmax.f32 q10, q11, q2 :: Qd 0x473e7300 0x473e7300 0x473e7300 0x473e7300 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmax.f32 q9, q5, q7 :: Qd 0x47bb3de1 0x47bb3de1 0x47bb3de1 0x47bb3de1 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmax.f32 q0, q5, q2 :: Qd 0xc732633d 0xc732633d 0xc732633d 0xc732633d Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmax.f32 q3, q4, q5 :: Qd 0x44a84000 0x44a84000 0x44a84000 0x44a84000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmax.f32 q10, q11, q2 :: Qd 0x473e7300 0x473e7300 0x473e7300 0x473e7300 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmax.f32 q9, q5, q7 :: Qd 0x49d5e008 0x49d5e008 0x49d5e008 0x49d5e008 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmax.f32 q0, q11, q12 :: Qd 0x48add9f2 0x48add9f2 0x48add9f2 0x48add9f2 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmax.f32 q7, q1, q6 :: Qd 0x42080079 0x42080079 0x42080079 0x42080079 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmax.f32 q0, q1, q2 :: Qd 0x452c2000 0x452c2000 0x452c2000 0x452c2000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmax.f32 q3, q4, q5 :: Qd 0x44ad1333 0x44ad1333 0x44ad1333 0x44ad1333 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmax.f32 q10, q11, q2 :: Qd 0x43f3cb23 0x43f3cb23 0x43f3cb23 0x43f3cb23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmax.f32 q9, q5, q7 :: Qd 0x45062000 0x45062000 0x45062000 0x45062000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmax.f32 q0, q11, q12 :: Qd 0xc2610000 0xc2610000 0xc2610000 0xc2610000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmax.f32 q7, q1, q6 :: Qd 0x43e41fde 0x43e41fde 0x43e41fde 0x43e41fde Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmax.f32 q0, q5, q2 :: Qd 0x44053f2b 0x44053f2b 0x44053f2b 0x44053f2b Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmax.f32 q10, q13, q15 :: Qd 0xc3f29f73 0xc3f29f73 0xc3f29f73 0xc3f29f73 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmax.f32 q10, q13, q15 :: Qd 0x4887f70e 0x4887f70e 0x4887f70e 0x4887f70e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmax.f32 q0, q1, q2 :: Qd 0x4e920233 0x4e920233 0x4e920233 0x4e920233 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmax.f32 q0, q1, q2 :: Qd 0x3a800000 0x3a800000 0x3a800000 0x3a800000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vmax.f32 q0, q1, q2 :: Qd 0x3a800000 0x3a800000 0x3a800000 0x3a800000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vmax.f32 q0, q1, q2 :: Qd 0x45126004 0x45126004 0x45126004 0x45126004 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vmax.f32 q0, q1, q2 :: Qd 0xc5125ffc 0xc5125ffc 0xc5125ffc 0xc5125ffc Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vmax.f32 q0, q1, q2 :: Qd 0x47ae5e00 0x47ae5e00 0x47ae5e00 0x47ae5e00 Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00 +vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmax.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmax.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmax.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMIN (fp) ---- +vmin.f32 q0, q5, q2 :: Qd 0xc2364659 0xc2364659 0xc2364659 0xc2364659 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmin.f32 q3, q4, q5 :: Qd 0xc8a9da0f 0xc8a9da0f 0xc8a9da0f 0xc8a9da0f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmin.f32 q10, q11, q2 :: Qd 0xc732da7a 0xc732da7a 0xc732da7a 0xc732da7a Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmin.f32 q9, q5, q7 :: Qd 0x46855200 0x46855200 0x46855200 0x46855200 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmin.f32 q0, q5, q2 :: Qd 0xc872bcb1 0xc872bcb1 0xc872bcb1 0xc872bcb1 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmin.f32 q3, q4, q5 :: Qd 0x41c00000 0x41c00000 0x41c00000 0x41c00000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmin.f32 q10, q11, q2 :: Qd 0x44882000 0x44882000 0x44882000 0x44882000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmin.f32 q9, q5, q7 :: Qd 0x43560000 0x43560000 0x43560000 0x43560000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmin.f32 q0, q11, q12 :: Qd 0x45b75812 0x45b75812 0x45b75812 0x45b75812 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmin.f32 q7, q1, q6 :: Qd 0x3b210e02 0x3b210e02 0x3b210e02 0x3b210e02 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmin.f32 q0, q1, q2 :: Qd 0x42d60000 0x42d60000 0x42d60000 0x42d60000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmin.f32 q3, q4, q5 :: Qd 0x445a8000 0x445a8000 0x445a8000 0x445a8000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmin.f32 q10, q11, q2 :: Qd 0x42da0000 0x42da0000 0x42da0000 0x42da0000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmin.f32 q9, q5, q7 :: Qd 0x44db0000 0x44db0000 0x44db0000 0x44db0000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmin.f32 q0, q11, q12 :: Qd 0xc5b4d3c3 0xc5b4d3c3 0xc5b4d3c3 0xc5b4d3c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmin.f32 q7, q1, q6 :: Qd 0xc0e96d19 0xc0e96d19 0xc0e96d19 0xc0e96d19 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmin.f32 q0, q5, q2 :: Qd 0xbb965394 0xbb965394 0xbb965394 0xbb965394 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmin.f32 q10, q13, q15 :: Qd 0xc40dcfae 0xc40dcfae 0xc40dcfae 0xc40dcfae Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmin.f32 q10, q13, q15 :: Qd 0x4608d008 0x4608d008 0x4608d008 0x4608d008 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmin.f32 q0, q1, q2 :: Qd 0x4e511724 0x4e511724 0x4e511724 0x4e511724 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmin.f32 q0, q1, q2 :: Qd 0xba800000 0xba800000 0xba800000 0xba800000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vmin.f32 q0, q1, q2 :: Qd 0xba800000 0xba800000 0xba800000 0xba800000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vmin.f32 q0, q1, q2 :: Qd 0x45125ffc 0x45125ffc 0x45125ffc 0x45125ffc Qm (i32)0x45126004 Qn (i32)0x45125ffc +vmin.f32 q0, q1, q2 :: Qd 0xc5126004 0xc5126004 0xc5126004 0xc5126004 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vmin.f32 q0, q1, q2 :: Qd 0x47ae5e00 0x47ae5e00 0x47ae5e00 0x47ae5e00 Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00 +vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmin.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmin.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VRECPE ---- +vrecpe.u32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x404ccccd +vrecpe.u32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x404ccccd +vrecpe.u32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vrecpe.u32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vrecpe.u32 q15, q4 :: Qd 0xab800000 0xab800000 0xab800000 0xab800000 Qm (i32)0xbf000000 +vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xbf000000 +vrecpe.u32 q15, q4 :: Qd 0xaa000000 0xaa000000 0xaa000000 0xaa000000 Qm (i32)0xc0e33333 +vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc0e33333 +vrecpe.u32 q12, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x40fff800 +vrecpe.u32 q12, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x40fff800 +vrecpe.u32 q12, q8 :: Qd 0xaa000000 0xaa000000 0xaa000000 0xaa000000 Qm (i32)0xc0fff800 +vrecpe.u32 q12, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc0fff800 +vrecpe.u32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x404ccccd +vrecpe.u32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x404ccccd +vrecpe.u32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vrecpe.u32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vrecpe.f32 q15, q4 :: Qd 0xbfff8000 0xbfff8000 0xbfff8000 0xbfff8000 Qm (i32)0xbf000000 +vrecpe.f32 q15, q4 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0xbf000000 +vrecpe.f32 q15, q4 :: Qd 0xbe100000 0xbe100000 0xbe100000 0xbe100000 Qm (i32)0xc0e33333 +vrecpe.f32 q15, q4 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0xc0e33333 +vrecpe.f32 q12, q8 :: Qd 0x3e000000 0x3e000000 0x3e000000 0x3e000000 Qm (i32)0x40fff800 +vrecpe.f32 q12, q8 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x40fff800 +vrecpe.f32 q12, q8 :: Qd 0xbe000000 0xbe000000 0xbe000000 0xbe000000 Qm (i32)0xc0fff800 +vrecpe.f32 q12, q8 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0xc0fff800 +vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000007 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x00000007 +vrecpe.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000000 +vrecpe.f32 q10, q11 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x80000000 +vrecpe.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000001 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x80000001 +vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x7fffffff +vrecpe.f32 q0, q14 :: Qd 0x4e4c0000 0x4e4c0000 0x4e4c0000 0x4e4c0000 Qm (i32)0x30a0bcef +vrecpe.f32 q0, q14 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x30a0bcef +vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000007 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x00000007 +vrecpe.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000000 +vrecpe.f32 q10, q11 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x80000000 +vrecpe.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000001 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x80000001 +vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x7fffffff +vrecpe.f32 q0, q14 :: Qd 0x4e4c0000 0x4e4c0000 0x4e4c0000 0x4e4c0000 Qm (i32)0x30a0bcef +vrecpe.f32 q0, q14 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x30a0bcef +vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x7fc00000 +vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x00000000 +vrecpe.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x7f800000 +vrecpe.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xff800000 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0xff800000 +vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x7fc00000 +vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x00000000 +vrecpe.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0x7f800000 +vrecpe.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xff800000 +vrecpe.f32 q0, q1 :: Qd 0x58bd0000 0x59c08000 0x5abe0000 0x5bbb0000 Qm (i32)0xff800000 +---- VRECPS ---- +vrecps.f32 q0, q5, q2 :: Qd 0x44837ce4 0x44837ce4 0x44837ce4 0x44837ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vrecps.f32 q3, q4, q5 :: Qd 0x4ddf4321 0x4ddf4321 0x4ddf4321 0x4ddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vrecps.f32 q10, q11, q2 :: Qd 0x4f050e7f 0x4f050e7f 0x4f050e7f 0x4f050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vrecps.f32 q9, q5, q7 :: Qd 0xcec3063f 0xcec3063f 0xcec3063f 0xcec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vrecps.f32 q0, q5, q2 :: Qd 0xd029254c 0xd029254c 0xd029254c 0xd029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vrecps.f32 q3, q4, q5 :: Qd 0xc6fc5c00 0xc6fc5c00 0xc6fc5c00 0xc6fc5c00 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vrecps.f32 q10, q11, q2 :: Qd 0xcc4a89cc 0xcc4a89cc 0xcc4a89cc 0xcc4a89cc Qm (i32)0x473e7300 Qn (i32)0x44882000 +vrecps.f32 q9, q5, q7 :: Qd 0xcdb2c947 0xcdb2c947 0xcdb2c947 0xcdb2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vrecps.f32 q0, q11, q12 :: Qd 0xcef90536 0xcef90536 0xcef90536 0xcef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vrecps.f32 q7, q1, q6 :: Qd 0x3ff54e08 0x3ff54e08 0x3ff54e08 0x3ff54e08 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vrecps.f32 q0, q1, q2 :: Qd 0xc88fe280 0xc88fe280 0xc88fe280 0xc88fe280 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vrecps.f32 q3, q4, q5 :: Qd 0xc993b8d3 0xc993b8d3 0xc993b8d3 0xc993b8d3 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vrecps.f32 q10, q11, q2 :: Qd 0xc74f98fc 0xc74f98fc 0xc74f98fc 0xc74f98fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vrecps.f32 q9, q5, q7 :: Qd 0xca657ab8 0xca657ab8 0xca657ab8 0xca657ab8 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vrecps.f32 q0, q11, q12 :: Qd 0xc89eedde 0xc89eedde 0xc89eedde 0xc89eedde Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vrecps.f32 q7, q1, q6 :: Qd 0x45502239 0x45502239 0x45502239 0x45502239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vrecps.f32 q0, q5, q2 :: Qd 0x408e3e84 0x408e3e84 0x408e3e84 0x408e3e84 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vrecps.f32 q10, q13, q15 :: Qd 0xc8866666 0xc8866666 0xc8866666 0xc8866666 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vrecps.f32 q10, q13, q15 :: Qd 0xcf115379 0xcf115379 0xcf115379 0xcf115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vrecps.f32 q0, q1, q2 :: Qd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VABS (fp) ---- +vabs.f32 q0, q1 :: Qd 0x404ccccd 0x404ccccd 0x404ccccd 0x404ccccd Qm (i32)0x404ccccd +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x404ccccd +vabs.f32 q10, q11 :: Qd 0x64cb49b4 0x64cb49b4 0x64cb49b4 0x64cb49b4 Qm (i32)0x64cb49b4 +vabs.f32 q10, q11 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x64cb49b4 +vabs.f32 q15, q4 :: Qd 0x4f32d05e 0x4f32d05e 0x4f32d05e 0x4f32d05e Qm (i32)0x4f32d05e +vabs.f32 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x4f32d05e +vabs.f32 q15, q4 :: Qd 0x3f000000 0x3f000000 0x3f000000 0x3f000000 Qm (i32)0xbf000000 +vabs.f32 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xbf000000 +vabs.f32 q15, q4 :: Qd 0x40e33333 0x40e33333 0x40e33333 0x40e33333 Qm (i32)0xc0e33333 +vabs.f32 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xc0e33333 +vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800 Qm (i32)0x40fff800 +vabs.f32 q12, q8 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x40fff800 +vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800 Qm (i32)0xc0fff800 +vabs.f32 q12, q8 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xc0fff800 +vabs.f32 q0, q1 :: Qd 0x404ccccd 0x404ccccd 0x404ccccd 0x404ccccd Qm (i32)0x404ccccd +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x404ccccd +vabs.f32 q10, q11 :: Qd 0x64cb49b4 0x64cb49b4 0x64cb49b4 0x64cb49b4 Qm (i32)0x64cb49b4 +vabs.f32 q10, q11 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x64cb49b4 +vabs.f32 q15, q4 :: Qd 0x4f32d05e 0x4f32d05e 0x4f32d05e 0x4f32d05e Qm (i32)0x4f32d05e +vabs.f32 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x4f32d05e +vabs.f32 q15, q4 :: Qd 0x3f000000 0x3f000000 0x3f000000 0x3f000000 Qm (i32)0xbf000000 +vabs.f32 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xbf000000 +vabs.f32 q15, q4 :: Qd 0x40e33333 0x40e33333 0x40e33333 0x40e33333 Qm (i32)0xc0e33333 +vabs.f32 q15, q4 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xc0e33333 +vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800 Qm (i32)0x40fff800 +vabs.f32 q12, q8 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x40fff800 +vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800 Qm (i32)0xc0fff800 +vabs.f32 q12, q8 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xc0fff800 +vabs.f32 q0, q1 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x00000007 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000007 +vabs.f32 q10, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 +vabs.f32 q10, q11 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x80000000 +vabs.f32 q0, q1 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x80000001 +vabs.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x7fffffff +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x7fffffff +vabs.f32 q0, q14 :: Qd 0x30a0bcef 0x30a0bcef 0x30a0bcef 0x30a0bcef Qm (i32)0x30a0bcef +vabs.f32 q0, q14 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x30a0bcef +vabs.f32 q0, q1 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x00000007 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000007 +vabs.f32 q10, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 +vabs.f32 q10, q11 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x80000000 +vabs.f32 q0, q1 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x80000001 +vabs.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x7fffffff +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x7fffffff +vabs.f32 q0, q14 :: Qd 0x30a0bcef 0x30a0bcef 0x30a0bcef 0x30a0bcef Qm (i32)0x30a0bcef +vabs.f32 q0, q14 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x30a0bcef +vabs.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x7fc00000 +vabs.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000000 +vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x7f800000 +vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xff800000 +vabs.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x7fc00000 +vabs.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x00000000 +vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0x7f800000 +vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 +vabs.f32 q0, q1 :: Qd 0x262d2d2a 0x252a2e2b 0x242c2b2b 0x232f2e2f Qm (i32)0xff800000 +---- VCGT (fp) ---- +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vcgt.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vcgt.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vcgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0x44882000 +vcgt.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vcgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vcgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vcgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000 +vcgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vcgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vcgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vcgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0xff800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VCGE (fp) ---- +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vcge.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vcge.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vcge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0x44882000 +vcge.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vcge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vcge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vcge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000 +vcge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vcge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vcge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vcge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0xff800000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VACGT (fp) ---- +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vacgt.f32 q2, q15, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vacgt.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vacgt.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vacgt.f32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vacgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vacgt.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vacgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0x44882000 +vacgt.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vacgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vacgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vacgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vacgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000 +vacgt.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vacgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vacgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vacgt.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vacgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x3f800000 +vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VACGE (fp) ---- +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vacge.f32 q2, q15, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vacge.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vacge.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vacge.f32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vacge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vacge.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vacge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0x44882000 +vacge.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vacge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vacge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vacge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vacge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000 +vacge.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vacge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vacge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vacge.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vacge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xba800000 Qn (i32)0x3a800000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000 +vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x3f800000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x7f800000 +vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VCEQ (fp) ---- +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vceq.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vceq.f32 q15, q7, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43677333 Qn (i32)0x43677333 +vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vceq.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vceq.f32 q7, q1, q6 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vceq.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vceq.f32 q7, q1, q6 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vceq.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vceq.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VCEQ (fp) #0 ---- +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000 +vceq.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000001 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 +vceq.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000000 +vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 +vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec +vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec +vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vceq.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vceq.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VCGT (fp) #0 ---- +vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x01000000 +vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x01000000 +vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 +vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000001 +vcgt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 +vcgt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000000 +vcgt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec +vcgt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec +vcgt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vcgt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc1b851ec +vcgt.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7fc00000 +vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 +---- VCLT (fp) #0 ---- +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 +vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 +vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 +vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec +vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec +vclt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc1b851ec +vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vclt.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vclt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 +vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VCGE (fp) #0 ---- +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x01000000 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x01000000 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000001 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000001 +vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000000 +vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000000 +vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec +vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec +vcge.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc1b851ec +vcge.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7fc00000 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcge.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 +---- VCLE (fp) #0 ---- +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000 +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000 +vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000001 +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 +vcle.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000000 +vcle.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 +vcle.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec +vcle.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec +vcle.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc1b851ec +vcle.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vcle.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 +vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VNEG (fp) ---- +vneg.f32 q0, q1 :: Qd 0x81000000 0x81000000 0x81000000 0x81000000 Qm (i32)0x01000000 +vneg.f32 q0, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0x01000000 +vneg.f32 q0, q1 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x00000001 +vneg.f32 q0, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0x00000001 +vneg.f32 q2, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 +vneg.f32 q2, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0x80000000 +vneg.f32 q2, q1 :: Qd 0xc1b851ec 0xc1b851ec 0xc1b851ec 0xc1b851ec Qm (i32)0x41b851ec +vneg.f32 q2, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0x41b851ec +vneg.f32 q2, q1 :: Qd 0x41b851ec 0x41b851ec 0x41b851ec 0x41b851ec Qm (i32)0xc1b851ec +vneg.f32 q2, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0xc1b851ec +vneg.f32 q10, q15 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x00000000 +vneg.f32 q10, q15 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0x00000000 +vneg.f32 q0, q1 :: Qd 0xffc00000 0xffc00000 0xffc00000 0xffc00000 Qm (i32)0x7fc00000 +vneg.f32 q0, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0x7fc00000 +vneg.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x00000000 +vneg.f32 q0, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0x00000000 +vneg.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 +vneg.f32 q0, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0x7f800000 +vneg.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 +vneg.f32 q0, q1 :: Qd 0xa62d2d2a 0xa52a2e2b 0xa42c2b2b 0xa32f2e2f Qm (i32)0xff800000 +---- VRSQRTS ---- +vrsqrts.f32 q0, q5, q2 :: Qd 0x44039ce4 0x44039ce4 0x44039ce4 0x44039ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vrsqrts.f32 q3, q4, q5 :: Qd 0x4d5f4321 0x4d5f4321 0x4d5f4321 0x4d5f4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vrsqrts.f32 q10, q11, q2 :: Qd 0x4e850e7f 0x4e850e7f 0x4e850e7f 0x4e850e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vrsqrts.f32 q9, q5, q7 :: Qd 0xce43063f 0xce43063f 0xce43063f 0xce43063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vrsqrts.f32 q0, q5, q2 :: Qd 0xcfa9254c 0xcfa9254c 0xcfa9254c 0xcfa9254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vrsqrts.f32 q3, q4, q5 :: Qd 0xc67c5a00 0xc67c5a00 0xc67c5a00 0xc67c5a00 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vrsqrts.f32 q10, q11, q2 :: Qd 0xcbca89cc 0xcbca89cc 0xcbca89cc 0xcbca89cc Qm (i32)0x473e7300 Qn (i32)0x44882000 +vrsqrts.f32 q9, q5, q7 :: Qd 0xcd32c947 0xcd32c947 0xcd32c947 0xcd32c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vrsqrts.f32 q0, q11, q12 :: Qd 0xce790536 0xce790536 0xce790536 0xce790536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vrsqrts.f32 q7, q1, q6 :: Qd 0x3fbaa704 0x3fbaa704 0x3fbaa704 0x3fbaa704 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vrsqrts.f32 q0, q1, q2 :: Qd 0xc80fe260 0xc80fe260 0xc80fe260 0xc80fe260 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vrsqrts.f32 q3, q4, q5 :: Qd 0xc913b8cb 0xc913b8cb 0xc913b8cb 0xc913b8cb Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vrsqrts.f32 q10, q11, q2 :: Qd 0xc6cf97fc 0xc6cf97fc 0xc6cf97fc 0xc6cf97fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vrsqrts.f32 q9, q5, q7 :: Qd 0xc9e57ab4 0xc9e57ab4 0xc9e57ab4 0xc9e57ab4 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vrsqrts.f32 q0, q11, q12 :: Qd 0xc81eedbe 0xc81eedbe 0xc81eedbe 0xc81eedbe Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vrsqrts.f32 q7, q1, q6 :: Qd 0x44d03239 0x44d03239 0x44d03239 0x44d03239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vrsqrts.f32 q0, q5, q2 :: Qd 0x402e3e84 0x402e3e84 0x402e3e84 0x402e3e84 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vrsqrts.f32 q10, q13, q15 :: Qd 0xc8066646 0xc8066646 0xc8066646 0xc8066646 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vrsqrts.f32 q10, q13, q15 :: Qd 0xce915379 0xce915379 0xce915379 0xce915379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vrsqrts.f32 q0, q1, q2 :: Qd 0xdcee81fd 0xdcee81fd 0xdcee81fd 0xdcee81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VRSQRTE (fp) ---- +vrsqrte.f32 q0, q1 :: Qd 0x3f0f0000 0x3f0f0000 0x3f0f0000 0x3f0f0000 Qm (i32)0x404ccccd +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x404ccccd +vrsqrte.f32 q10, q11 :: Qd 0x2ccb0000 0x2ccb0000 0x2ccb0000 0x2ccb0000 Qm (i32)0x64cb49b4 +vrsqrte.f32 q10, q11 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x64cb49b4 +vrsqrte.f32 q15, q4 :: Qd 0x37998000 0x37998000 0x37998000 0x37998000 Qm (i32)0x4f32d05e +vrsqrte.f32 q15, q4 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x4f32d05e +vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xbf000000 +vrsqrte.f32 q15, q4 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0xbf000000 +vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xc0e33333 +vrsqrte.f32 q15, q4 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0xc0e33333 +vrsqrte.f32 q12, q8 :: Qd 0x3eb50000 0x3eb50000 0x3eb50000 0x3eb50000 Qm (i32)0x40fff800 +vrsqrte.f32 q12, q8 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x40fff800 +vrsqrte.f32 q12, q8 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xc0fff800 +vrsqrte.f32 q12, q8 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0xc0fff800 +vrsqrte.f32 q0, q1 :: Qd 0x3f0f0000 0x3f0f0000 0x3f0f0000 0x3f0f0000 Qm (i32)0x404ccccd +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x404ccccd +vrsqrte.f32 q10, q11 :: Qd 0x2ccb0000 0x2ccb0000 0x2ccb0000 0x2ccb0000 Qm (i32)0x64cb49b4 +vrsqrte.f32 q10, q11 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x64cb49b4 +vrsqrte.f32 q15, q4 :: Qd 0x37998000 0x37998000 0x37998000 0x37998000 Qm (i32)0x4f32d05e +vrsqrte.f32 q15, q4 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x4f32d05e +vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xbf000000 +vrsqrte.f32 q15, q4 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0xbf000000 +vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xc0e33333 +vrsqrte.f32 q15, q4 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0xc0e33333 +vrsqrte.f32 q12, q8 :: Qd 0x3eb50000 0x3eb50000 0x3eb50000 0x3eb50000 Qm (i32)0x40fff800 +vrsqrte.f32 q12, q8 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x40fff800 +vrsqrte.f32 q12, q8 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xc0fff800 +vrsqrte.f32 q12, q8 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0xc0fff800 +vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000007 +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x00000007 +vrsqrte.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000000 +vrsqrte.f32 q10, q11 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x80000000 +vrsqrte.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000001 +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x80000001 +vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x7fffffff +vrsqrte.f32 q0, q14 :: Qd 0x46e48000 0x46e48000 0x46e48000 0x46e48000 Qm (i32)0x30a0bcef +vrsqrte.f32 q0, q14 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x30a0bcef +vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000007 +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x00000007 +vrsqrte.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000000 +vrsqrte.f32 q10, q11 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x80000000 +vrsqrte.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000001 +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x80000001 +vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x7fffffff +vrsqrte.f32 q0, q14 :: Qd 0x46e48000 0x46e48000 0x46e48000 0x46e48000 Qm (i32)0x30a0bcef +vrsqrte.f32 q0, q14 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x30a0bcef +vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x7fc00000 +vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x00000000 +vrsqrte.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x7f800000 +vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 +vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0xff800000 diff --git a/none/tests/arm/neon128.vgtest b/none/tests/arm/neon128.vgtest new file mode 100644 index 0000000..d73f24b --- /dev/null +++ b/none/tests/arm/neon128.vgtest @@ -0,0 +1,2 @@ +prog: neon128 +vgopts: -q diff --git a/none/tests/arm/neon64.c b/none/tests/arm/neon64.c new file mode 100644 index 0000000..a936302 --- /dev/null +++ b/none/tests/arm/neon64.c @@ -0,0 +1,4506 @@ + +/* How to compile: + + gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \ + -marm -o neon64-a neon64.c + + or + + gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \ + -mthumb -o neon64-t neon64.c + +*/ + +#include +#include +#include + +#ifndef __thumb__ +// ARM +#define MOVE_to_FPSCR_from_R4 \ + ".word 0xEEE14A10 @ vmsr FPSCR, r4\n\t" +#define MOVE_to_R4_from_FPSCR \ + ".word 0xEEF14A10 @ vmrs r4, FPSCR\n\t" +#endif + +#ifdef __thumb__ +// Thumb +#define MOVE_to_FPSCR_from_R4 \ + ".word 0x4A10EEE1 @ vmsr FPSCR, r4\n\t" +#define MOVE_to_R4_from_FPSCR \ + ".word 0x4A10EEF1 @ vmrs r4, FPSCR\n\t" +#endif + +static inline unsigned int f2u(float x) { + union { + float f; + unsigned int u; + } cvt; + cvt.f = x; + return cvt.u; +} + +/* test macros to generate and output the result of a single instruction */ + +const unsigned int mem[] = { + 0x121f1e1f, 0x131b1a1b, 0x141c1f1c, 0x151d191d, + 0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a, + 0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a, + 0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c +}; + +#define TESTINSN_imm(instruction, QD, imm) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + instruction ", #" #imm "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out) \ + : #QD, "memory" \ + ); \ + printf("%s, #" #imm " :: Qd 0x%08x 0x%08x\n", \ + instruction, out[1], out[0]); \ +} \ +{ \ + unsigned int out[2]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %1, %2\n\t" \ + "vldmia %1!, {" #QD "}\n\t" \ + instruction ", #" #imm "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (addr), "r" (mem) \ + : #QD, "%2", "memory" \ + ); \ + printf("%s, #" #imm " :: Qd 0x%08x 0x%08x\n", \ + instruction, out[1], out[0]); \ +} + +#define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x\n", \ + instruction, out[1], out[0], QMval); \ +} \ +{ \ + unsigned int out[2]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %2, %3\n\t" \ + "vldmia %2!, {" #QD "}\n\t" \ + "vldmia %2!, {" #QM "}\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (addr), "r" (mem) \ + : #QD, #QM, "%2", "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x\n", \ + instruction, out[1], out[0], QMval ); \ +} + +#define TESTINSN_un_q(instruction, QD, QM, QMtype, QMval) \ +{ \ + unsigned int out[2]; \ + unsigned int fpscr; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + "vdup." #QMtype " " #QM ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + MOVE_to_R4_from_FPSCR \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory", "r4" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x fpscr %08x\n", \ + instruction, out[1], out[0], QMval, fpscr); \ +} \ +{ \ + unsigned int out[2]; \ + unsigned int fpscr; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + "mov %3, %4\n\t" \ + "vldmia %3!, {" #QM "}\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + MOVE_to_R4_from_FPSCR \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (QMval), "r" (addr), "r" (mem) \ + : #QD, #QM, "memory", "r4" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x fpscr %08x\n", \ + instruction, out[1], out[0], QMval, fpscr); \ +} + +#define TESTINSN_core_to_scalar(instruction, QD, QM, QMval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov " #QM ", %1\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm 0x%08x\n", \ + instruction, out[1], out[0], QMval); \ +} + +#define TESTINSN_scalar_to_core(instruction, QD, QM, QMtype, QMval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "mov " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + instruction "\n\t" \ + "str " #QD ", [%0]\n\t" \ + : \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory" \ + ); \ + printf("%s :: Rd 0x%08x Qm (" #QMtype ")0x%08x\n", \ + instruction, out[0], QMval); \ +} + +#define TESTINSN_VLDn(instruction, QD1, QD2, QD3, QD4) \ +{ \ + unsigned int out[9]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD1 ", #0x55" "\n\t" \ + "vmov.i8 " #QD2 ", #0x55" "\n\t" \ + "vmov.i8 " #QD3 ", #0x55" "\n\t" \ + "vmov.i8 " #QD4 ", #0x55" "\n\t" \ + instruction ", [%1]\n\t" \ + "mov r4, %0\n\t" \ + "vstmia %0!, {" #QD1 "}\n\t" \ + "vstmia %0!, {" #QD2 "}\n\t" \ + "vstmia %0!, {" #QD3 "}\n\t" \ + "vstmia %0!, {" #QD4 "}\n\t" \ + "str %1, [%2]\n\t" \ + "mov %0, r4\n\t" \ + : \ + : "r" (out), "r" (mem), "r"(&out[8]) \ + : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\ + "0x%08x 0x%08x 0x%08x 0x%08x delta %d\n", \ + instruction, out[0], out[1], out[2], out[3], out[4],\ + out[5], out[6], out[7], (int)out[8]-(int)mem); \ +} + +#define TESTINSN_VSTn(instruction, QD1, QD2, QD3, QD4) \ +{ \ + unsigned int out[9]; \ +\ + memset(out, 0x55, 8 * (sizeof(unsigned int)));\ + __asm__ volatile( \ + "mov r4, %1\n\t" \ + "vldmia %1!, {" #QD1 "}\n\t" \ + "vldmia %1!, {" #QD2 "}\n\t" \ + "vldmia %1!, {" #QD3 "}\n\t" \ + "vldmia %1!, {" #QD4 "}\n\t" \ + "mov %1, r4\n\t" \ + instruction ", [%0]\n\t" \ + "str %0, [%2]\n\t" \ + : \ + : "r" (out), "r" (mem), "r"(&out[8]) \ + : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\ + "0x%08x 0x%08x 0x%08x 0x%08x delta %d\n", \ + instruction, out[0], out[1], out[2], out[3], out[4],\ + out[5], out[6], out[7], (int)out[8]-(int)out); \ +} + +#define TESTINSN_VLDn_WB(instruction, QD1, QD2, QD3, QD4) \ +{ \ + unsigned int out[9]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %0, %2\n\t" \ + "vmov.i8 " #QD1 ", #0x55" "\n\t" \ + "vmov.i8 " #QD2 ", #0x55" "\n\t" \ + "vmov.i8 " #QD3 ", #0x55" "\n\t" \ + "vmov.i8 " #QD4 ", #0x55" "\n\t" \ + instruction ", [%0]!\n\t" \ + "mov r4, %1\n\t" \ + "vstmia %1!, {" #QD1 "}\n\t" \ + "vstmia %1!, {" #QD2 "}\n\t" \ + "vstmia %1!, {" #QD3 "}\n\t" \ + "vstmia %1!, {" #QD4 "}\n\t" \ + "str %0, [%3]\n\t" \ + "mov %1, r4\n\t" \ + : "+r" (addr) \ + : "r" (out), "r" (mem), "r"(&out[8]) \ + : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\ + "0x%08x 0x%08x 0x%08x 0x%08x delta %d\n", \ + instruction, out[0], out[1], out[2], out[3], out[4],\ + out[5], out[6], out[7], (int)out[8]-(int)mem); \ +} + +#define TESTINSN_VSTn_WB(instruction, QD1, QD2, QD3, QD4) \ +{ \ + unsigned int out[9]; \ + unsigned int addr = 0; \ + \ + memset(out, 0x55, 8 * (sizeof(unsigned int)));\ + __asm__ volatile( \ + "mov %0, %1\n\t" \ + "mov r4, %2\n\t" \ + "vldmia r4!, {" #QD1 "}\n\t" \ + "vldmia r4!, {" #QD2 "}\n\t" \ + "vldmia r4!, {" #QD3 "}\n\t" \ + "vldmia r4!, {" #QD4 "}\n\t" \ + instruction ", [%0]!\n\t" \ + "str %0, [%3]\n\t" \ + : "+r" (addr) \ + : "r" (out), "r" (mem), "r"(&out[8]) \ + : #QD1, #QD2, #QD3, #QD4, "memory", "r4", "0" \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\ + "0x%08x 0x%08x 0x%08x 0x%08x delta %d\n", \ + instruction, out[0], out[1], out[2], out[3], out[4],\ + out[5], out[6], out[7], (int)out[8]-(int)out); \ +} + +#define TESTINSN_VLDn_RI(instruction, QD1, QD2, QD3, QD4, RM, RMval) \ +{ \ + unsigned int out[9]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %0, %2\n\t" \ + "vmov.i8 " #QD1 ", #0x55" "\n\t" \ + "vmov.i8 " #QD2 ", #0x55" "\n\t" \ + "vmov.i8 " #QD3 ", #0x55" "\n\t" \ + "vmov.i8 " #QD4 ", #0x55" "\n\t" \ + "mov " #RM ", %4\n\t" \ + instruction ", [%0], " #RM "\n\t" \ + "mov r4, %1\n\t" \ + "vstmia %1!, {" #QD1 "}\n\t" \ + "vstmia %1!, {" #QD2 "}\n\t" \ + "vstmia %1!, {" #QD3 "}\n\t" \ + "vstmia %1!, {" #QD4 "}\n\t" \ + "str %0, [%3]\n\t" \ + "mov %1, r4\n\t" \ + : "+r" (addr) \ + : "r" (out), "r" (mem), "r"(&out[8]), "r"(RMval) \ + : #QD1, #QD2, #QD3, #QD4, "memory", "r4", #RM \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\ + "0x%08x 0x%08x 0x%08x 0x%08x delta %d\n", \ + instruction, out[0], out[1], out[2], out[3], out[4],\ + out[5], out[6], out[7], (int)out[8]-(int)addr); \ +} + + +#define TESTINSN_VSTn_RI(instruction, QD1, QD2, QD3, QD4, RM, RMval) \ +{ \ + unsigned int out[9]; \ + unsigned int addr = 0; \ + \ + memset(out, 0x55, 8 * (sizeof(unsigned int)));\ + __asm__ volatile( \ + "mov %0, %1\n\t" \ + "mov r4, %2\n\t" \ + "vldmia r4!, {" #QD1 "}\n\t" \ + "vldmia r4!, {" #QD2 "}\n\t" \ + "vldmia r4!, {" #QD3 "}\n\t" \ + "vldmia r4!, {" #QD4 "}\n\t" \ + "mov " #RM ", %4\n\t" \ + instruction ", [%0], " #RM "\n\t" \ + "str %0, [%3]\n\t" \ + : "+r" (addr) \ + : "r" (out), "r" (mem), "r"(&out[8]), "r"(#RMval) \ + : #QD1, #QD2, #QD3, #QD4, "memory", "r4", #RM \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\ + "0x%08x 0x%08x 0x%08x 0x%08x delta %d\n", \ + instruction, out[0], out[1], out[2], out[3], out[4],\ + out[5], out[6], out[7], (int)out[8]-(int)out); \ +} + +#define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + "vdup." #QNtype " " #QN ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QNval) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[1], out[0], QMval, QNval); \ +} \ +{ \ + unsigned int out[2]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %0, %4\n\t" \ + "vldmia %0!, {" #QM "}\n\t" \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + : "+r" (addr) \ + : "r" (out), "r" (QMval), "r" (QNval), "r" (mem) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[1], out[0], QMval, QNval); \ +} + +#define TESTINSN_bin_f(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vdup.i32 " #QD ", %3\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + "vdup." #QNtype " " #QN ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QNval), "r"(0x3f800000) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[1], out[0], QMval, QNval); \ +} \ +{ \ + unsigned int out[2]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "vdup.i32 " #QD ", %3\n\t" \ + "mov %4, %5\n\t" \ + "vldmia %4!, {" #QM "}\n\t" \ + "vdup." #QNtype " " #QN ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QNval), "r"(0x3f800000), "r" (addr), "r" (mem) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[1], out[0], QMval, QNval); \ +} + +#define TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \ + QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + "vdup." #QN1type " " #QN1 ", %2\n\t" \ + "vdup." #QN2type " " #QN2 ", %3\n\t" \ + "vdup." #QN3type " " #QN3 ", %4\n\t" \ + "vdup." #QN4type " " #QN4 ", %5\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QN1val), "r" (QN2val), "r" (QN3val), \ + "r" (QN4val) \ + : #QD, #QM, #QN1, #QN2, #QN3, #QN4, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn1 (" #QN1type ")0x%08x" \ + " Qn2 (" #QN2type ")0x%08x" \ + " Qn3 (" #QN3type ")0x%08x" \ + " Qn4 (" #QN4type ")0x%08x\n", \ + instruction, out[1], out[0], QMval, QN1val, QN2val, QN3val, QN4val); \ +} \ +{ \ + unsigned int out[2]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %6, %7\n\t" \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + "vldmia %6!, {" #QN1 "}\n\t" \ + "vdup." #QN2type " " #QN2 ", %3\n\t" \ + "vldmia %6!, {" #QN3 "}\n\t" \ + "vdup." #QN4type " " #QN4 ", %5\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QN1val), "r" (QN2val), "r" (QN3val), \ + "r" (QN4val), "r" (addr), "r" (mem) \ + : #QD, #QM, #QN1, #QN2, #QN3, #QN4, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn1 (" #QN1type ")0x%08x" \ + " Qn2 (" #QN2type ")0x%08x" \ + " Qn3 (" #QN3type ")0x%08x" \ + " Qn4 (" #QN4type ")0x%08x\n", \ + instruction, out[1], out[0], QMval, QN1val, QN2val, QN3val, QN4val); \ +} + +#define TESTINSN_tbl_1(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val) \ + TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \ + QN1, QN1type, QN1val, QN1, QN1type, QN1val, QN1, QN1type, QN1val) +#define TESTINSN_tbl_2(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \ + QN2, QN2type, QN2val) \ + TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \ + QN2, QN2type, QN2val, QN1, QN1type, QN1val, QN2, QN2type, QN2val) +#define TESTINSN_tbl_3(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \ + QN2, QN2type, QN2val, QN3, QN3type, QN3val) \ + TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \ + QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN2, QN2type, QN2val) +#define TESTINSN_tbl_4(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \ + QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val) \ + TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \ + QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val) + +#define TESTINSN_bin_q(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out[2]; \ + unsigned int fpscr; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + "vdup." #QMtype " " #QM ", %2\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + MOVE_to_R4_from_FPSCR \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (QMval), "r" (QNval) \ + : #QD, #QM, #QN, "memory", "r4" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x fpscr: %08x\n", \ + instruction, out[1], out[0], QMval, QNval, fpscr); \ +} \ +{ \ + unsigned int out[2]; \ + unsigned int fpscr; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + "mov %4, %5\n\t" \ + "vldmia %4!, {" #QM "}\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #QD "}\n\t" \ + MOVE_to_R4_from_FPSCR \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (QMval), "r" (QNval), "r" (addr), "r" (mem) \ + : #QD, #QM, #QN, "memory", "r4" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x fpscr: %08x\n", \ + instruction, out[1], out[0], QMval, QNval, fpscr); \ +} + +#define TESTINSN_dual(instruction, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out1[2]; \ + unsigned int out2[2]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %4, %5\n\t" \ + "vldmia %4!, {" #QM "}\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QM "}\n\t" \ + "vstmia %1, {" #QN "}\n\t" \ + : \ + : "r" (out1), "r" (out2), "r" (QMval), "r" (QNval), "r" (addr), "r" (mem) \ + : #QM, #QN, "memory" \ + ); \ + printf("%s :: Qm 0x%08x 0x%08x Qn 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out1[1], out1[0], out2[1], out2[0], QMval, QNval); \ +} \ +{ \ + unsigned int out1[2]; \ + unsigned int out2[2]; \ + unsigned int addr = 0; \ + \ + __asm__ volatile( \ + "mov %4, %5\n\t" \ + "vldmia %4!, {" #QM "}\n\t" \ + "vdup." #QNtype " " #QN ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QM "}\n\t" \ + "vstmia %1, {" #QN "}\n\t" \ + : \ + : "r" (out1), "r" (out2), "r" (QMval), "r" (QNval), "r" (addr), "r" (mem) \ + : #QM, #QN, "%4", "memory" \ + ); \ + printf("%s :: Qm 0x%08x 0x%08x Qn 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out1[1], out1[0], out2[1], out2[0], QMval, QNval); \ +} + +#if 0 +#define TESTINSN_2reg_shift(instruction, QD, QM, QMtype, QMval, imm) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + instruction ", #" #imm "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory" \ + ); \ + printf("%s, #" #imm " :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x", \ + instruction, out[1], out[0], QMval); \ +} +#endif + +int main(int argc, char **argv) +{ + printf("----- VMOV (immediate) -----\n"); + TESTINSN_imm("vmov.i32 d0", d0, 0x7); + TESTINSN_imm("vmov.i16 d1", d1, 0x7); + TESTINSN_imm("vmov.i8 d2", d2, 0x7); + TESTINSN_imm("vmov.i32 d5", d5, 0x700); + TESTINSN_imm("vmov.i16 d7", d7, 0x700); + TESTINSN_imm("vmov.i32 d10", d10, 0x70000); + TESTINSN_imm("vmov.i32 d12", d12, 0x7000000); + TESTINSN_imm("vmov.i32 d13", d13, 0x7FF); + TESTINSN_imm("vmov.i32 d14", d14, 0x7FFFF); + TESTINSN_imm("vmov.i64 d15", d15, 0xFF0000FF00FFFF00); + + printf("----- VMVN (immediate) -----\n"); + TESTINSN_imm("vmvn.i32 d0", d0, 0x7); + TESTINSN_imm("vmvn.i16 d1", d1, 0x7); + TESTINSN_imm("vmvn.i8 d2", d2, 0x7); + TESTINSN_imm("vmvn.i32 d5", d5, 0x700); + TESTINSN_imm("vmvn.i16 d7", d7, 0x700); + TESTINSN_imm("vmvn.i32 d10", d10, 0x70000); + TESTINSN_imm("vmvn.i32 d13", d13, 0x7000000); + TESTINSN_imm("vmvn.i32 d11", d11, 0x7FF); + TESTINSN_imm("vmvn.i32 d14", d14, 0x7FFFF); + TESTINSN_imm("vmvn.i64 d15", d15, 0xFF0000FF00FFFF00); + + printf("----- VORR (immediate) -----\n"); + TESTINSN_imm("vorr.i32 d0", d0, 0x7); + TESTINSN_imm("vorr.i16 d2", d2, 0x7); + TESTINSN_imm("vorr.i32 d8", d8, 0x700); + TESTINSN_imm("vorr.i16 d6", d6, 0x700); + TESTINSN_imm("vorr.i32 d14", d14, 0x70000); + TESTINSN_imm("vorr.i32 d15", d15, 0x7000000); + + printf("----- VBIC (immediate) -----\n"); + TESTINSN_imm("vbic.i32 d0", d0, 0x7); + TESTINSN_imm("vbic.i16 d3", d3, 0x7); + TESTINSN_imm("vbic.i32 d5", d5, 0x700); + TESTINSN_imm("vbic.i16 d8", d8, 0x700); + TESTINSN_imm("vbic.i32 d10", d10, 0x70000); + TESTINSN_imm("vbic.i32 d15", d15, 0x7000000); + + printf("---- VMVN (register) ----\n"); + TESTINSN_un("vmvn d0, d1", d0, d1, i32, 24); + TESTINSN_un("vmvn d10, d15", d10, d15, i32, 24); + TESTINSN_un("vmvn d0, d14", d0, d14, i32, 24); + + printf("---- VMOV (register) ----\n"); + TESTINSN_un("vmov d0, d1", d0, d1, i32, 24); + TESTINSN_un("vmov d10, d15", d10, d15, i32, 24); + TESTINSN_un("vmov d0, d14", d0, d14, i32, 24); + + printf("---- VDUP (ARM core register) (tested indirectly) ----\n"); + TESTINSN_un("vmov d0, d1", d0, d1, i8, 7); + TESTINSN_un("vmov d10, d11", d10, d11, i16, 7); + TESTINSN_un("vmov d0, d15", d0, d15, i32, 7); + + printf("---- VADD ----\n"); + TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vadd.i64 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vadd.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vadd.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vadd.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vadd.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vadd.i64 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vadd.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vadd.i64 d13, d14, d15", d13, d14, i32, 140, d15, i32, 120); + + printf("---- VSUB ----\n"); + TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vsub.i64 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vsub.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vsub.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vsub.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vsub.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vsub.i64 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vsub.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vsub.i64 d13, d14, d15", d13, d14, i32, 140, d15, i32, 120); + + printf("---- VAND ----\n"); + TESTINSN_bin("vand d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77); + TESTINSN_bin("vand d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); + TESTINSN_bin("vand d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed); + TESTINSN_bin("vand d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff); + + printf("---- VBIC ----\n"); + TESTINSN_bin("vbic d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77); + TESTINSN_bin("vbic d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); + TESTINSN_bin("vbic d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed); + TESTINSN_bin("vbic d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff); + + printf("---- VORR ----\n"); + TESTINSN_bin("vorr d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73); + TESTINSN_bin("vorr d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); + TESTINSN_bin("vorr d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); + TESTINSN_bin("vorr d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f); + + printf("---- VORN ----\n"); + TESTINSN_bin("vorn d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73); + TESTINSN_bin("vorn d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); + TESTINSN_bin("vorn d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); + TESTINSN_bin("vorn d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f); + + printf("---- VEOR ----\n"); + TESTINSN_bin("veor d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77); + TESTINSN_bin("veor d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); + TESTINSN_bin("veor d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed); + TESTINSN_bin("veor d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff); + TESTINSN_bin("veor d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73); + TESTINSN_bin("veor d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); + TESTINSN_bin("veor d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); + TESTINSN_bin("veor d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f); + + printf("---- VBSL ----\n"); + TESTINSN_bin("vbsl d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77); + TESTINSN_bin("vbsl d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); + TESTINSN_bin("vbsl d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed); + TESTINSN_bin("vbsl d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff); + TESTINSN_bin("vbsl d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73); + TESTINSN_bin("vbsl d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); + TESTINSN_bin("vbsl d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); + TESTINSN_bin("vbsl d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f); + + printf("---- VBIT ----\n"); + TESTINSN_bin("vbit d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77); + TESTINSN_bin("vbit d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); + TESTINSN_bin("vbit d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed); + TESTINSN_bin("vbit d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff); + TESTINSN_bin("vbit d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73); + TESTINSN_bin("vbit d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); + TESTINSN_bin("vbit d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); + TESTINSN_bin("vbit d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f); + + printf("---- VBIF ----\n"); + TESTINSN_bin("vbif d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77); + TESTINSN_bin("vbif d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); + TESTINSN_bin("vbif d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed); + TESTINSN_bin("vbif d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff); + TESTINSN_bin("vbif d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73); + TESTINSN_bin("vbif d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); + TESTINSN_bin("vbif d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); + TESTINSN_bin("vbif d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f); + + printf("---- VEXT ----\n"); + TESTINSN_bin("vext.8 d0, d1, d2, #0", d0, d1, i8, 0x77, d2, i8, 0xff); + TESTINSN_bin("vext.8 d0, d1, d2, #1", d0, d1, i8, 0x77, d2, i8, 0xff); + TESTINSN_bin("vext.8 d0, d1, d2, #7", d0, d1, i8, 0x77, d2, i8, 0xff); + TESTINSN_bin("vext.8 d0, d1, d2, #6", d0, d1, i8, 0x77, d2, i8, 0xff); + TESTINSN_bin("vext.8 d10, d11, d12, #4", d10, d11, i8, 0x77, d12, i8, 0xff); + TESTINSN_bin("vext.8 d0, d5, d15, #5", d0, d5, i8, 0x77, d15, i8, 0xff); + + printf("---- VHADD ----\n"); + TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i8, 141, d2, i8, 121); + TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i8, 141, d2, i8, 121); + TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VHSUB ----\n"); + TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhsub.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhsub.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhsub.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhsub.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhsub.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vhsub.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vhsub.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VQADD ----\n"); + TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqadd.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VQSUB ----\n"); + TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqsub.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqsub.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqsub.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqsub.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqsub.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin_q("vqsub.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqsub.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VRHADD ----\n"); + TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vrhadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vrhadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VCGT ----\n"); + TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140); + TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140); + TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140); + TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 3, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 2, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcgt.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VCGE ----\n"); + TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140); + TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140); + TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140); + TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 3, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 2, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vcge.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VSHL (register) ----\n"); + TESTINSN_bin("vshl.s8 d0, d1, d2", d0, d1, i32, 24, d2, i32, 1); + TESTINSN_bin("vshl.s8 d8, d1, d12", d8, d1, i32, 24, d12, i32, 8); + TESTINSN_bin("vshl.s8 d10, d31, d7", d10, d31, i32, 24, d7, i32, 4); + TESTINSN_bin("vshl.s16 d3, d8, d11", d3, d8, i32, 14, d11, i32, 2); + TESTINSN_bin("vshl.s16 d5, d12, d14", d5, d12, i32, (1 << 30), d14, i32, 1); + TESTINSN_bin("vshl.s16 d15, d2, d1", d15, d2, i32, (1 << 30), d1, i32, 11); + TESTINSN_bin("vshl.s32 d9, d12, d19", d9, d12, i32, (1 << 31) + 2, d19, i32, 2); + TESTINSN_bin("vshl.s32 d11, d22, d0", d11, d22, i32, -1, d0, i32, 12); + TESTINSN_bin("vshl.s32 d5, d2, d3", d5, d2, i32, (1 << 30), d3, i32, 21); + TESTINSN_bin("vshl.s64 d15, d12, d4", d15, d12, i32, 5, d4, i32, 20); + TESTINSN_bin("vshl.s64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 4); + TESTINSN_bin("vshl.s64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 30); + TESTINSN_bin("vshl.s64 d15, d2, d4", d15, d2, i32, 0xffabcd59, d4, i32, 0xabcdefab); + TESTINSN_bin("vshl.s64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 0x400bb5); + TESTINSN_bin("vshl.s64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 0x30abcff); + TESTINSN_bin("vshl.u8 d0, d1, d2", d0, d1, i32, 24, d2, i32, 1); + TESTINSN_bin("vshl.u8 d8, d1, d12", d8, d1, i32, 24, d12, i32, 8); + TESTINSN_bin("vshl.u8 d10, d11, d7", d10, d11, i32, 24, d7, i32, 4); + TESTINSN_bin("vshl.u16 d3, d8, d11", d3, d8, i32, 14, d11, i32, 2); + TESTINSN_bin("vshl.u16 d5, d12, d14", d5, d12, i32, (1 << 30), d14, i32, 1); + TESTINSN_bin("vshl.u16 d15, d2, d1", d15, d2, i32, (1 << 30), d1, i32, 11); + TESTINSN_bin("vshl.u32 d9, d12, d15", d9, d12, i32, (1 << 31) + 2, d15, i32, 2); + TESTINSN_bin("vshl.u32 d11, d2, d0", d11, d2, i32, -1, d0, i32, 12); + TESTINSN_bin("vshl.u32 d5, d2, d3", d5, d2, i32, (1 << 30), d3, i32, 21); + TESTINSN_bin("vshl.u64 d15, d12, d4", d15, d12, i32, 5, d4, i32, 20); + TESTINSN_bin("vshl.u64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 4); + TESTINSN_bin("vshl.u64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 30); + TESTINSN_bin("vshl.u64 d15, d2, d4", d15, d2, i32, 0xffabcd59, d4, i32, 0xabcdefab); + TESTINSN_bin("vshl.u64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 0x400bb5); + TESTINSN_bin("vshl.u64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 0x30abcff); + + printf("---- VQSHL (register) ----\n"); + TESTINSN_bin_q("vqshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1); + TESTINSN_bin_q("vqshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1); + TESTINSN_bin_q("vqshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3); + TESTINSN_bin_q("vqshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14); + TESTINSN_bin_q("vqshl.s64 d13, d14, d31", d13, d14, i32, -17, d31, i32, -26); + TESTINSN_bin_q("vqshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60); + TESTINSN_bin_q("vqshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30); + TESTINSN_bin_q("vqshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4); + TESTINSN_bin_q("vqshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9); + TESTINSN_bin_q("vqshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7); + TESTINSN_bin_q("vqshl.s32 d9, d30, d11", d9, d30, i32, (1 << 31) + 8, d11, i32, -1); + TESTINSN_bin_q("vqshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3); + TESTINSN_bin_q("vqshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31); + TESTINSN_bin_q("vqshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3); + TESTINSN_bin_q("vqshl.s16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1); + TESTINSN_bin_q("vqshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31); + TESTINSN_bin_q("vqshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13); + TESTINSN_bin_q("vqshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30); + TESTINSN_bin_q("vqshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40); + TESTINSN_bin_q("vqshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30); + TESTINSN_bin_q("vqshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3); + TESTINSN_bin_q("vqshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16); + TESTINSN_bin_q("vqshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2); + TESTINSN_bin_q("vqshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin_q("vqshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1); + TESTINSN_bin_q("vqshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1); + TESTINSN_bin_q("vqshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3); + TESTINSN_bin_q("vqshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14); + TESTINSN_bin_q("vqshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26); + TESTINSN_bin_q("vqshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60); + TESTINSN_bin_q("vqshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30); + TESTINSN_bin_q("vqshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4); + TESTINSN_bin_q("vqshl.u32 d12, d31, d13", d12, d31, i32, -120, d13, i32, -9); + TESTINSN_bin_q("vqshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7); + TESTINSN_bin_q("vqshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1); + TESTINSN_bin_q("vqshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3); + TESTINSN_bin_q("vqshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31); + TESTINSN_bin_q("vqshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3); + TESTINSN_bin_q("vqshl.u16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1); + TESTINSN_bin_q("vqshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31); + TESTINSN_bin_q("vqshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13); + TESTINSN_bin_q("vqshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30); + TESTINSN_bin_q("vqshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40); + TESTINSN_bin_q("vqshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30); + TESTINSN_bin_q("vqshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3); + TESTINSN_bin_q("vqshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16); + TESTINSN_bin_q("vqshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2); + TESTINSN_bin_q("vqshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VQSHL / VQSHLU (immediate) ----\n"); + TESTINSN_un_q("vqshl.s64 d0, d1, #1", d0, d1, i32, 1); + TESTINSN_un_q("vqshl.s64 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshl.s64 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshl.s64 d5, d4, #63", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s64 d5, d4, #60", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s64 d5, d4, #59", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s64 d5, d4, #58", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s64 d5, d4, #17", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s64 d5, d4, #63", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.s64 d5, d4, #60", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.s64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.s32 d10, d11, #1", d10, d11, i32, 1); + TESTINSN_un_q("vqshl.s32 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshl.s32 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshl.s32 d5, d4, #31", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s32 d5, d4, #28", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s32 d5, d4, #27", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s32 d5, d4, #26", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s32 d5, d4, #17", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s32 d5, d4, #31", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.s32 d5, d4, #29", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.s32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.s16 d9, d8, #1", d9, d8, i32, 1); + TESTINSN_un_q("vqshl.s16 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshl.s16 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshl.s16 d9, d8, #15", d9, d8, i32, 16); + TESTINSN_un_q("vqshl.s16 d5, d4, #12", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s16 d5, d4, #11", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s16 d5, d4, #10", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s16 d5, d4, #4", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s16 d5, d4, #15", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.s16 d5, d4, #12", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.s16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.s8 d0, d1, #1", d0, d1, i32, 1); + TESTINSN_un_q("vqshl.s8 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshl.s8 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshl.s8 d5, d4, #7", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s8 d25, d4, #4", d25, d4, i32, 16); + TESTINSN_un_q("vqshl.s8 d5, d4, #3", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s8 d5, d4, #2", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s8 d5, d4, #1", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.s8 d5, d4, #7", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.s8 d5, d4, #5", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.s8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.u64 d0, d1, #1", d0, d1, i32, 1); + TESTINSN_un_q("vqshl.u64 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshl.u64 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshl.u64 d5, d4, #63", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u64 d5, d4, #60", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u64 d5, d4, #59", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u64 d5, d4, #58", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u64 d5, d4, #17", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u64 d5, d4, #63", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.u64 d5, d4, #60", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.u64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.u32 d10, d11, #1", d10, d11, i32, 1); + TESTINSN_un_q("vqshl.u32 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshl.u32 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshl.u32 d5, d4, #31", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u32 d5, d4, #28", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u32 d5, d4, #27", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u32 d5, d4, #26", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u32 d5, d4, #17", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u32 d5, d4, #31", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.u32 d5, d4, #29", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.u32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.u16 d9, d8, #1", d9, d8, i32, 1); + TESTINSN_un_q("vqshl.u16 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshl.u16 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshl.u16 d9, d8, #15", d9, d8, i32, 16); + TESTINSN_un_q("vqshl.u16 d5, d4, #12", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u16 d5, d4, #11", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u16 d5, d4, #10", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u16 d5, d4, #4", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u16 d5, d4, #15", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.u16 d5, d4, #12", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.u16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshl.u8 d0, d1, #1", d0, d1, i32, 1); + TESTINSN_un_q("vqshl.u8 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshl.u8 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshl.u8 d5, d4, #7", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u8 d5, d4, #4", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u8 d5, d4, #3", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u8 d5, d4, #2", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u8 d5, d4, #1", d5, d4, i32, 16); + TESTINSN_un_q("vqshl.u8 d5, d4, #7", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.u8 d5, d4, #5", d5, d4, i32, -1); + TESTINSN_un_q("vqshl.u8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshlu.s64 d0, d1, #1", d0, d1, i32, 1); + TESTINSN_un_q("vqshlu.s64 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshlu.s64 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshlu.s64 d5, d4, #63", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s64 d5, d4, #60", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s64 d5, d4, #59", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s64 d5, d4, #58", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s64 d5, d4, #17", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s64 d5, d4, #63", d5, d4, i32, -1); + TESTINSN_un_q("vqshlu.s64 d5, d4, #60", d5, d4, i32, -1); + TESTINSN_un_q("vqshlu.s64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshlu.s32 d10, d11, #1", d10, d11, i32, 1); + TESTINSN_un_q("vqshlu.s32 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshlu.s32 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshlu.s32 d5, d4, #31", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s32 d25, d24, #28", d25, d24, i32, 16); + TESTINSN_un_q("vqshlu.s32 d5, d4, #27", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s32 d5, d4, #26", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s32 d5, d4, #17", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s32 d5, d24, #31", d5, d24, i32, -1); + TESTINSN_un_q("vqshlu.s32 d5, d4, #29", d5, d4, i32, -1); + TESTINSN_un_q("vqshlu.s32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshlu.s16 d9, d8, #1", d9, d8, i32, 1); + TESTINSN_un_q("vqshlu.s16 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshlu.s16 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshlu.s16 d9, d8, #15", d9, d8, i32, 16); + TESTINSN_un_q("vqshlu.s16 d5, d4, #12", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s16 d5, d4, #11", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s16 d5, d4, #10", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s16 d5, d4, #4", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s16 d15, d14, #15", d15, d14, i32, -1); + TESTINSN_un_q("vqshlu.s16 d5, d4, #12", d5, d4, i32, -1); + TESTINSN_un_q("vqshlu.s16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2); + TESTINSN_un_q("vqshlu.s8 d0, d1, #1", d0, d1, i32, 1); + TESTINSN_un_q("vqshlu.s8 d31, d30, #1", d31, d30, i32, -127); + TESTINSN_un_q("vqshlu.s8 d5, d4, #0", d5, d4, i32, -127); + TESTINSN_un_q("vqshlu.s8 d5, d4, #7", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s8 d5, d4, #4", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s8 d5, d4, #3", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s8 d5, d4, #2", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s8 d5, d4, #1", d5, d4, i32, 16); + TESTINSN_un_q("vqshlu.s8 d5, d4, #7", d5, d4, i32, -1); + TESTINSN_un_q("vqshlu.s8 d5, d4, #5", d5, d4, i32, -1); + TESTINSN_un_q("vqshlu.s8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2); + + printf("---- VQRSHL (register) ----\n"); + TESTINSN_bin_q("vqrshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1); + TESTINSN_bin_q("vqrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1); + TESTINSN_bin_q("vqrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3); + TESTINSN_bin_q("vqrshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14); + TESTINSN_bin_q("vqrshl.s64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26); + TESTINSN_bin_q("vqrshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60); + TESTINSN_bin_q("vqrshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30); + TESTINSN_bin_q("vqrshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4); + TESTINSN_bin_q("vqrshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9); + TESTINSN_bin_q("vqrshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7); + TESTINSN_bin_q("vqrshl.s32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3); + TESTINSN_bin_q("vqrshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31); + TESTINSN_bin_q("vqrshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3); + TESTINSN_bin_q("vqrshl.s16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1); + TESTINSN_bin_q("vqrshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31); + TESTINSN_bin_q("vqrshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13); + TESTINSN_bin_q("vqrshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30); + TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0); + TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0); + TESTINSN_bin_q("vqrshl.s32 d2, d7, d31", d2, d7, i32, -1, d31, i32, 0); + TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40); + TESTINSN_bin_q("vqrshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30); + TESTINSN_bin_q("vqrshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3); + TESTINSN_bin_q("vqrshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16); + TESTINSN_bin_q("vqrshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2); + TESTINSN_bin_q("vqrshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin_q("vqrshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1); + TESTINSN_bin_q("vqrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1); + TESTINSN_bin_q("vqrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3); + TESTINSN_bin_q("vqrshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14); + TESTINSN_bin_q("vqrshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26); + TESTINSN_bin_q("vqrshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60); + TESTINSN_bin_q("vqrshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30); + TESTINSN_bin_q("vqrshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4); + TESTINSN_bin_q("vqrshl.u32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9); + TESTINSN_bin_q("vqrshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7); + TESTINSN_bin_q("vqrshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1); + TESTINSN_bin_q("vqrshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3); + TESTINSN_bin_q("vqrshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31); + TESTINSN_bin_q("vqrshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3); + TESTINSN_bin_q("vqrshl.u16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1); + TESTINSN_bin_q("vqrshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31); + TESTINSN_bin_q("vqrshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13); + TESTINSN_bin_q("vqrshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30); + TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40); + TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1); + TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0); + TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0); + TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0); + TESTINSN_bin_q("vqrshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30); + TESTINSN_bin_q("vqrshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3); + TESTINSN_bin_q("vqrshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16); + TESTINSN_bin_q("vqrshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2); + TESTINSN_bin_q("vqrshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VRSHL (register) ----\n"); + TESTINSN_bin("vrshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1); + TESTINSN_bin("vrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1); + TESTINSN_bin("vrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3); + TESTINSN_bin("vrshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14); + TESTINSN_bin("vrshl.s64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26); + TESTINSN_bin("vrshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60); + TESTINSN_bin("vrshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30); + TESTINSN_bin("vrshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4); + TESTINSN_bin("vrshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9); + TESTINSN_bin("vrshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7); + TESTINSN_bin("vrshl.s32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1); + TESTINSN_bin("vrshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3); + TESTINSN_bin("vrshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31); + TESTINSN_bin("vrshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3); + TESTINSN_bin("vrshl.s16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1); + TESTINSN_bin("vrshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31); + TESTINSN_bin("vrshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13); + TESTINSN_bin("vrshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30); + TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin("vrshl.s8 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1); + TESTINSN_bin("vrshl.s16 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1); + TESTINSN_bin("vrshl.s32 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1); + TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1); + TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0); + TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0); + TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0); + TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40); + TESTINSN_bin("vrshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30); + TESTINSN_bin("vrshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3); + TESTINSN_bin("vrshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16); + TESTINSN_bin("vrshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2); + TESTINSN_bin("vrshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vrshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1); + TESTINSN_bin("vrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1); + TESTINSN_bin("vrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3); + TESTINSN_bin("vrshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14); + TESTINSN_bin("vrshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26); + TESTINSN_bin("vrshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60); + TESTINSN_bin("vrshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30); + TESTINSN_bin("vrshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4); + TESTINSN_bin("vrshl.u32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9); + TESTINSN_bin("vrshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7); + TESTINSN_bin("vrshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1); + TESTINSN_bin("vrshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3); + TESTINSN_bin("vrshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31); + TESTINSN_bin("vrshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3); + TESTINSN_bin("vrshl.u16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1); + TESTINSN_bin("vrshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31); + TESTINSN_bin("vrshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13); + TESTINSN_bin("vrshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30); + TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40); + TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1); + TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin("vrshl.u16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin("vrshl.u32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1); + TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1); + TESTINSN_bin("vrshl.u16 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1); + TESTINSN_bin("vrshl.u32 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1); + TESTINSN_bin("vrshl.u8 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1); + TESTINSN_bin("vrshl.u16 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1); + TESTINSN_bin("vrshl.u32 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1); + TESTINSN_bin("vrshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30); + TESTINSN_bin("vrshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3); + TESTINSN_bin("vrshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16); + TESTINSN_bin("vrshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2); + TESTINSN_bin("vrshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VMAX (integer) ----\n"); + TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121); + TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vmax.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120); + TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmax.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VMIN (integer) ----\n"); + TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121); + TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vmin.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120); + TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vmin.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VABD ----\n"); + TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, -120); + TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200); + TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, -140, d2, i32, 120); + TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vabd.u8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200); + TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vabd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VABA ----\n"); + TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vaba.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200); + TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vaba.u8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200); + TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vaba.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VTST ----\n"); + TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vtst.32 d3, d4, d5", d3, d4, i32, 140, d5, i32, 120); + TESTINSN_bin("vtst.16 d6, d7, d8", d6, d7, i32, 120, d8, i32, 120); + TESTINSN_bin("vtst.8 d9, d10, d12", d9, d10, i32, 140, d12, i32, 120); + TESTINSN_bin("vtst.8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vtst.16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1); + TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vtst.8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, 2); + TESTINSN_bin("vtst.16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1); + TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vtst.32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VCEQ ----\n"); + TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vceq.i32 d3, d4, d5", d3, d4, i32, 140, d5, i32, 120); + TESTINSN_bin("vceq.i16 d6, d7, d8", d6, d7, i32, 120, d8, i32, 120); + TESTINSN_bin("vceq.i8 d9, d10, d12", d9, d10, i32, 140, d12, i32, 120); + TESTINSN_bin("vceq.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vceq.i16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1); + TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vceq.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, 2); + TESTINSN_bin("vceq.i16 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 14) + 1); + TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vceq.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VMLA ----\n"); + TESTINSN_bin("vmla.i32 d0, d1, d2", d0, d1, i32, -24, d2, i32, 120); + TESTINSN_bin("vmla.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, 120); + TESTINSN_bin("vmla.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmla.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, -120); + TESTINSN_bin("vmla.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); + TESTINSN_bin("vmla.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmla.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); + TESTINSN_bin("vmla.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmla.i32 d10, d11, d15", d10, d11, i32, 24, d15, i32, -120); + + printf("---- VMLS ----\n"); + TESTINSN_bin("vmls.i32 d0, d1, d2", d0, d1, i32, -24, d2, i32, 120); + TESTINSN_bin("vmls.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin("vmls.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmls.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vmls.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); + TESTINSN_bin("vmls.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmls.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); + TESTINSN_bin("vmls.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmls.i32 d10, d11, d15", d10, d11, i32, -24, d15, i32, 120); + + printf("---- VMUL ----\n"); + TESTINSN_bin("vmul.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vmul.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin("vmul.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin("vmul.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vmul.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); + TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmul.i8 d10, d11, d12", d10, d11, i32, (1 << 25) + 0xfeb2, d12, i32, (1 << 13) + 0xdf); + TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin("vmul.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); + TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin("vmul.i32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 3, q2, i32, 3); + TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 12, q2, i8, 0x0f); + + printf("---- VMUL (by scalar) ----\n"); + TESTINSN_bin("vmul.i32 d0, d1, d4[0]", d0, d1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmul.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120); + TESTINSN_bin("vmul.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmul.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmul.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmul.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmul.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VMLA (by scalar) ----\n"); + TESTINSN_bin("vmla.i32 d0, d1, d4[0]", d0, d1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmla.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120); + TESTINSN_bin("vmla.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmla.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmla.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmla.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmla.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VMLS (by scalar) ----\n"); + TESTINSN_bin("vmls.i32 d0, d1, d4[0]", q0, q1, i32, 24, d4, i32, 120); + TESTINSN_bin("vmls.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120); + TESTINSN_bin("vmls.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin("vmls.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin("vmls.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin("vmls.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin("vmls.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + + printf("---- VRSHR ----\n"); + TESTINSN_un("vrshr.s8 d0, d1, #0", d0, d1, i32, -1); + TESTINSN_un("vrshr.s8 d0, d1, #1", d0, d1, i32, -1); + TESTINSN_un("vrshr.s16 d3, d4, #2", d3, d4, i32, -0x7c); + TESTINSN_un("vrshr.s32 d2, d5, #31", d2, d5, i32, -1); + TESTINSN_un("vrshr.s8 d6, d7, #7", d6, d7, i32, 0xffff); + TESTINSN_un("vrshr.s16 d8, d9, #12", d8, d9, i32, -10); + TESTINSN_un("vrshr.s32 d10, d11, #5", d10, d11, i32, 10234); + TESTINSN_un("vrshr.u8 d12, d13, #1", d12, d13, i32, -1); + TESTINSN_un("vrshr.u16 d14, d15, #11", d14, d15, i32, -1); + TESTINSN_un("vrshr.u32 d10, d11, #9", d10, d11, i32, 1000); + TESTINSN_un("vrshr.u8 d7, d13, #7", d7, d13, i32, -1); + TESTINSN_un("vrshr.u16 d8, d1, #5", d8, d1, i32, 0xabcf); + TESTINSN_un("vrshr.u32 d12, d3, #15", d12, d3, i32, -0x1b0); + TESTINSN_un("vrshr.u64 d0, d1, #42", d0, d1, i32, -1); + TESTINSN_un("vrshr.s64 d6, d7, #12", d6, d7, i32, 0xfac); + TESTINSN_un("vrshr.u64 d8, d4, #9", d8, d4, i32, 13560); + TESTINSN_un("vrshr.s64 d9, d12, #11", d9, d12, i32, 98710); + + printf("---- VRSRA ----\n"); + TESTINSN_un("vrsra.s8 d0, d1, #1", d0, d1, i32, -1); + TESTINSN_un("vrsra.s16 d3, d4, #2", d3, d4, i32, -0x7c); + TESTINSN_un("vrsra.s32 d2, d5, #31", d2, d5, i32, -1); + TESTINSN_un("vrsra.s8 d6, d7, #7", d6, d7, i32, 0xffff); + TESTINSN_un("vrsra.s16 d8, d9, #12", d8, d9, i32, -10); + TESTINSN_un("vrsra.s32 d10, d11, #5", d10, d11, i32, 10234); + TESTINSN_un("vrsra.u8 d12, d13, #1", d12, d13, i32, -1); + TESTINSN_un("vrsra.u16 d14, d15, #11", d14, d15, i32, -1); + TESTINSN_un("vrsra.u32 d10, d11, #9", d10, d11, i32, 1000); + TESTINSN_un("vrsra.u8 d7, d13, #7", d7, d13, i32, -1); + TESTINSN_un("vrsra.u16 d8, d1, #5", d8, d1, i32, 0xabcf); + TESTINSN_un("vrsra.u32 d12, d3, #15", d12, d3, i32, -0x1b0); + TESTINSN_un("vrsra.u64 d0, d1, #42", d0, d1, i32, -1); + TESTINSN_un("vrsra.s64 d6, d7, #12", d6, d7, i32, 0xfac); + TESTINSN_un("vrsra.u64 d8, d4, #9", d8, d4, i32, 13560); + TESTINSN_un("vrsra.s64 d9, d12, #11", d9, d12, i32, 98710); + + printf("---- VSHR ----\n"); + TESTINSN_un("vshr.s8 d0, d1, #0", d0, d1, i32, -1); + TESTINSN_un("vshr.s8 d0, d1, #1", d0, d1, i32, -1); + TESTINSN_un("vshr.s16 d3, d4, #2", d3, d4, i32, -0x7c); + TESTINSN_un("vshr.s32 d2, d5, #31", d2, d5, i32, -1); + TESTINSN_un("vshr.s8 d6, d7, #7", d6, d7, i32, 0xffff); + TESTINSN_un("vshr.s16 d8, d9, #12", d8, d9, i32, -10); + TESTINSN_un("vshr.s32 d10, d11, #5", d10, d11, i32, 10234); + TESTINSN_un("vshr.u8 d12, d13, #1", d12, d13, i32, -1); + TESTINSN_un("vshr.u16 d14, d15, #11", d14, d15, i32, -1); + TESTINSN_un("vshr.u32 d10, d11, #9", d10, d11, i32, 1000); + TESTINSN_un("vshr.u8 d7, d13, #7", d7, d13, i32, -1); + TESTINSN_un("vshr.u16 d8, d1, #5", d8, d1, i32, 0xabcf); + TESTINSN_un("vshr.u32 d12, d3, #15", d12, d3, i32, -0x1b0); + TESTINSN_un("vshr.u64 d0, d1, #42", d0, d1, i32, -1); + TESTINSN_un("vshr.s64 d6, d7, #12", d6, d7, i32, 0xfac); + TESTINSN_un("vshr.u64 d8, d4, #9", d8, d4, i32, 13560); + TESTINSN_un("vshr.s64 d9, d12, #11", d9, d12, i32, 98710); + + printf("---- VSRA ----\n"); + TESTINSN_un("vsra.s8 d0, d1, #1", d0, d1, i32, -1); + TESTINSN_un("vsra.s16 d3, d4, #2", d3, d4, i32, -0x7c); + TESTINSN_un("vsra.s32 d2, d5, #31", d2, d5, i32, -1); + TESTINSN_un("vsra.s8 d6, d7, #7", d6, d7, i32, 0xffff); + TESTINSN_un("vsra.s16 d8, d9, #12", d8, d9, i32, -10); + TESTINSN_un("vsra.s32 d10, d11, #5", d10, d11, i32, 10234); + TESTINSN_un("vsra.u8 d12, d13, #1", d12, d13, i32, -1); + TESTINSN_un("vsra.u16 d14, d15, #11", d14, d15, i32, -1); + TESTINSN_un("vsra.u32 d10, d11, #9", d10, d11, i32, 1000); + TESTINSN_un("vsra.u8 d7, d13, #7", d7, d13, i32, -1); + TESTINSN_un("vsra.u16 d8, d1, #5", d8, d1, i32, 0xabcf); + TESTINSN_un("vsra.u32 d12, d3, #15", d12, d3, i32, -0x1b0); + TESTINSN_un("vsra.u64 d0, d1, #42", d0, d1, i32, -1); + TESTINSN_un("vsra.s64 d6, d7, #12", d6, d7, i32, 0xfac); + TESTINSN_un("vsra.u64 d8, d4, #9", d8, d4, i32, 13560); + TESTINSN_un("vsra.s64 d9, d12, #11", d9, d12, i32, 98710); + + printf("---- VSRI ----\n"); + TESTINSN_un("vsri.16 d0, d1, #1", d0, d1, i32, -1); + TESTINSN_un("vsri.16 d3, d4, #2", d3, d4, i32, -0x7c); + TESTINSN_un("vsri.32 d2, d5, #31", d2, d5, i32, -1); + TESTINSN_un("vsri.8 d6, d7, #7", d6, d7, i32, 0xffff); + TESTINSN_un("vsri.16 d8, d9, #12", d8, d9, i32, -10); + TESTINSN_un("vsri.32 d10, d11, #5", d10, d11, i32, 10234); + TESTINSN_un("vsri.8 d12, d13, #1", d12, d13, i32, -1); + TESTINSN_un("vsri.16 d14, d15, #11", d14, d15, i32, -1); + TESTINSN_un("vsri.32 d10, d11, #9", d10, d11, i32, 1000); + TESTINSN_un("vsri.8 d7, d13, #7", d7, d13, i32, -1); + TESTINSN_un("vsri.16 d8, d1, #5", d8, d1, i32, 0xabcf); + TESTINSN_un("vsri.32 d12, d3, #15", d12, d3, i32, -0x1b0); + TESTINSN_un("vsri.64 d0, d1, #42", d0, d1, i32, -1); + TESTINSN_un("vsri.64 d6, d7, #12", d6, d7, i32, 0xfac); + TESTINSN_un("vsri.64 d8, d4, #9", d8, d4, i32, 13560); + TESTINSN_un("vsri.64 d9, d12, #11", d9, d12, i32, 98710); + + printf("---- VMOV (ARM core register to scalar) ----\n"); + TESTINSN_core_to_scalar("vmov.32 d0[0], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.32 d1[1], r3", d1, r3, 12); + TESTINSN_core_to_scalar("vmov.16 d0[0], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.16 d2[2], r6", d2, r6, 14); + TESTINSN_core_to_scalar("vmov.16 d3[3], r1", d3, r1, 17); + TESTINSN_core_to_scalar("vmov.8 d0[0], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.8 d0[1], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.8 d0[2], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.8 d0[3], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.8 d0[4], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.8 d0[5], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.8 d0[6], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.8 d31[7], r5", d31, r5, 13); + + printf("---- VMOV (scalar toARM core register) ----\n"); + TESTINSN_scalar_to_core("vmov.32 r5, d0[0]", r5, d0, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.32 r6, d5[1]", r6, d5, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r5, d31[0]", r5, d31, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r5, d30[1]", r5, d30, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r5, d31[2]", r5, d31, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r5, d31[3]", r5, d31, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[0]", r2, d4, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[1]", r2, d4, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[2]", r2, d4, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[3]", r2, d4, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[4]", r2, d4, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[5]", r2, d4, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[6]", r2, d4, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[7]", r2, d4, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s16 r5, d31[0]", r5, d31, i8, 128); + TESTINSN_scalar_to_core("vmov.s16 r5, d30[1]", r5, d30, i8, 128); + TESTINSN_scalar_to_core("vmov.s16 r5, d31[2]", r5, d31, i8, 128); + TESTINSN_scalar_to_core("vmov.s16 r5, d31[3]", r5, d31, i8, 128); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[0]", r2, d4, i8, 128); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[1]", r2, d4, i8, 128); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[2]", r2, d4, i8, 128); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[3]", r2, d4, i8, 128); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[4]", r2, d4, i8, 128); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[5]", r2, d4, i8, 130); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[6]", r2, d4, i8, 129); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[7]", r2, d4, i8, 131); + + printf("---- VLD1 (multiple single elements) ----\n"); + TESTINSN_VLDn("vld1.8 {d0}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.16 {d0}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.32 {d0}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.64 {d0}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.8 {d9}", d9, d9, d9, d9); + TESTINSN_VLDn("vld1.16 {d17}", d17, d17, d17, d17); + TESTINSN_VLDn("vld1.32 {d31}", d31, d31, d31, d31); + TESTINSN_VLDn("vld1.64 {d14}", d14, d14, d14, d14); + TESTINSN_VLDn("vld1.8 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VLDn("vld1.16 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VLDn("vld1.32 {d5-d6}", d5, d6, d5, d6); + TESTINSN_VLDn("vld1.64 {d30-d31}", d30, d31, d30, d31); + TESTINSN_VLDn("vld1.8 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn("vld1.16 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn("vld1.32 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn("vld1.64 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn("vld1.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn("vld1.16 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn("vld1.32 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn("vld1.64 {d0-d3}", d0, d1, d2, d3); + + printf("---- VLD1 (single element to one lane) ----\n"); + TESTINSN_VLDn("vld1.32 {d0[0]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.32 {d0[1]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.16 {d1[0]}", d1, d1, d1, d1); + TESTINSN_VLDn("vld1.16 {d1[1]}", d1, d1, d1, d1); + TESTINSN_VLDn("vld1.16 {d1[2]}", d1, d1, d1, d1); + TESTINSN_VLDn("vld1.16 {d1[3]}", d1, d1, d1, d1); + TESTINSN_VLDn("vld1.8 {d0[7]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.8 {d1[6]}", d1, d1, d1, d1); + TESTINSN_VLDn("vld1.8 {d0[5]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.8 {d0[4]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.8 {d20[3]}", d20, d20, d20, d20); + TESTINSN_VLDn("vld1.8 {d0[2]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.8 {d17[1]}", d17, d17, d17, d17); + TESTINSN_VLDn("vld1.8 {d30[0]}", d30, d30, d30, d30); + + printf("---- VLD1 (single element to all lanes) ----\n"); + TESTINSN_VLDn("vld1.8 {d0[]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.16 {d0[]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.32 {d0[]}", d0, d0, d0, d0); + TESTINSN_VLDn("vld1.8 {d9[]}", d9, d9, d9, d9); + TESTINSN_VLDn("vld1.16 {d17[]}", d17, d17, d17, d17); + TESTINSN_VLDn("vld1.32 {d31[]}", d31, d31, d31, d31); + TESTINSN_VLDn("vld1.8 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld1.16 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld1.32 {d5[],d6[]}", d5, d6, d5, d6); + + printf("---- VLD2 (multiple 2-elements) ----\n"); + TESTINSN_VLDn("vld2.8 {d30-d31}", d30, d31, d30, d31); + TESTINSN_VLDn("vld2.16 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.32 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.8 {d10,d12}", d10, d12, d10, d12); + TESTINSN_VLDn("vld2.16 {d20,d22}", d20, d22, d20, d22); + TESTINSN_VLDn("vld2.32 {d0,d2}", d0, d2, d0, d2); + TESTINSN_VLDn("vld2.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn("vld2.16 {d20-d23}", d20, d21, d22, d23); + TESTINSN_VLDn("vld2.32 {d0-d3}", d0, d1, d2, d3); + + printf("---- VLD2 (single 2-element structure to one lane) ----\n"); + TESTINSN_VLDn("vld2.32 {d0[0],d1[0]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.32 {d0[1],d1[1]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.32 {d0[0],d2[0]}", d0, d2, d0, d2); + TESTINSN_VLDn("vld2.32 {d0[1],d2[1]}", d0, d2, d0, d2); + TESTINSN_VLDn("vld2.16 {d1[0],d2[0]}", d1, d2, d1, d2); + TESTINSN_VLDn("vld2.16 {d1[1],d2[1]}", d1, d2, d1, d2); + TESTINSN_VLDn("vld2.16 {d1[2],d2[2]}", d1, d2, d1, d2); + TESTINSN_VLDn("vld2.16 {d1[3],d2[3]}", d1, d2, d1, d2); + TESTINSN_VLDn("vld2.16 {d1[0],d3[0]}", d1, d3, d1, d3); + TESTINSN_VLDn("vld2.16 {d1[1],d3[1]}", d1, d3, d1, d3); + TESTINSN_VLDn("vld2.16 {d1[2],d3[2]}", d1, d3, d1, d3); + TESTINSN_VLDn("vld2.16 {d1[3],d3[3]}", d1, d3, d1, d3); + TESTINSN_VLDn("vld2.8 {d0[7],d1[7]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.8 {d1[6],d2[6]}", d1, d2, d1, d2); + TESTINSN_VLDn("vld2.8 {d0[5],d1[5]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.8 {d0[4],d1[4]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.8 {d20[3],d21[3]}", d20, d21, d20, d21); + TESTINSN_VLDn("vld2.8 {d0[2],d1[2]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.8 {d17[1],d18[1]}", d17, d18, d17, d18); + TESTINSN_VLDn("vld2.8 {d30[0],d31[0]}", d30, d31, d30, d31); + + printf("---- VLD2 (2-elements to all lanes) ----\n"); + TESTINSN_VLDn("vld2.8 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.16 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.32 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn("vld2.8 {d9[],d11[]}", d9, d11, d9, d11); + TESTINSN_VLDn("vld2.16 {d17[],d18[]}", d17, d18, d17, d18); + TESTINSN_VLDn("vld2.32 {d30[],d31[]}", d30, d31, d30, d31); + TESTINSN_VLDn("vld2.8 {d0[],d2[]}", d0, d2, d0, d2); + TESTINSN_VLDn("vld2.16 {d0[],d2[]}", d0, d2, d0, d2); + TESTINSN_VLDn("vld2.32 {d5[],d7[]}", d5, d7, d5, d7); + + printf("---- VLD3 (multiple 3-elements) ----\n"); + TESTINSN_VLDn("vld3.8 {d20-d22}", d20, d21, d22, d20); + TESTINSN_VLDn("vld3.16 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn("vld3.32 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn("vld3.8 {d0,d2,d4}", d0, d2, d4, d0); + TESTINSN_VLDn("vld3.16 {d20,d22,d24}", d20, d22, d24, d20); + TESTINSN_VLDn("vld3.32 {d0,d2,d4}", d0, d2, d4, d0); + + printf("---- VLD3 (single 3-element structure to one lane) ----\n"); + TESTINSN_VLDn("vld3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2); + TESTINSN_VLDn("vld3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2); + TESTINSN_VLDn("vld3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2); + TESTINSN_VLDn("vld3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2); + TESTINSN_VLDn("vld3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2); + TESTINSN_VLDn("vld3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2); + TESTINSN_VLDn("vld3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5); + TESTINSN_VLDn("vld3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5); + TESTINSN_VLDn("vld3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5); + TESTINSN_VLDn("vld3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5); + TESTINSN_VLDn("vld3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2); + TESTINSN_VLDn("vld3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21); + TESTINSN_VLDn("vld3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18); + TESTINSN_VLDn("vld3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31); + + printf("---- VLD3 (3-elements to all lanes) ----\n"); + TESTINSN_VLDn("vld3.8 {d0[],d1[],d2[]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.16 {d0[],d1[],d2[]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.32 {d0[],d1[],d2[]}", d0, d1, d2, d1); + TESTINSN_VLDn("vld3.8 {d9[],d11[],d13[]}", d9, d11, d13, d11); + TESTINSN_VLDn("vld3.16 {d17[],d18[],d19[]}", d17, d18, d19, d18); + TESTINSN_VLDn("vld3.32 {d29[],d30[],d31[]}", d29, d30, d30, d31); + TESTINSN_VLDn("vld3.8 {d0[],d2[],d4[]}", d0, d2, d4, d2); + TESTINSN_VLDn("vld3.16 {d0[],d2[],d4[]}", d0, d2, d4, d2); + TESTINSN_VLDn("vld3.32 {d5[],d7[],d9[]}", d5, d7, d9, d7); + + printf("---- VLD4 (multiple 3-elements) ----\n"); + TESTINSN_VLDn("vld4.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.16 {d20-d23}", d20, d21, d22, d23); + TESTINSN_VLDn("vld4.32 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.8 {d0,d2,d4,d6}", d0, d2, d4, d6); + TESTINSN_VLDn("vld4.16 {d1,d3,d5,d7}", d1, d3, d5, d7); + TESTINSN_VLDn("vld4.32 {d20,d22,d24,d26}", d20, d22, d24, d26); + + printf("---- VLD4 (single 4-element structure to one lane) ----\n"); + TESTINSN_VLDn("vld4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4); + TESTINSN_VLDn("vld4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6); + TESTINSN_VLDn("vld4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6); + TESTINSN_VLDn("vld4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4); + TESTINSN_VLDn("vld4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4); + TESTINSN_VLDn("vld4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4); + TESTINSN_VLDn("vld4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4); + TESTINSN_VLDn("vld4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7); + TESTINSN_VLDn("vld4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7); + TESTINSN_VLDn("vld4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7); + TESTINSN_VLDn("vld4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7); + TESTINSN_VLDn("vld4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4); + TESTINSN_VLDn("vld4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23); + TESTINSN_VLDn("vld4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20); + TESTINSN_VLDn("vld4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31); + + printf("---- VLD4 (4-elements to all lanes) ----\n"); + TESTINSN_VLDn("vld4.8 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.16 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.32 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3); + TESTINSN_VLDn("vld4.8 {d9[],d11[],d13[],d15[]}", d9, d11, d13, d15); + TESTINSN_VLDn("vld4.16 {d17[],d18[],d19[],d20[]}", d17, d18, d19, d20); + TESTINSN_VLDn("vld4.32 {d28[],d29[],d30[],d31[]}", d28, d29, d30, d31); + TESTINSN_VLDn("vld4.8 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6); + TESTINSN_VLDn("vld4.16 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6); + TESTINSN_VLDn("vld4.32 {d5[],d7[],d9[],d11[]}", d5, d7, d9, d11); + + printf("---- VST1 (multiple single elements) ----\n"); + TESTINSN_VSTn("vst1.8 {d0}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.16 {d0}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.32 {d0}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.64 {d0}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.8 {d9}", d9, d9, d9, d9); + TESTINSN_VSTn("vst1.16 {d17}", d17, d17, d17, d17); + TESTINSN_VSTn("vst1.32 {d31}", d31, d31, d31, d31); + TESTINSN_VSTn("vst1.64 {d14}", d14, d14, d14, d14); + TESTINSN_VSTn("vst1.8 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VSTn("vst1.16 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VSTn("vst1.32 {d5-d6}", d5, d6, d5, d6); + TESTINSN_VSTn("vst1.64 {d30-d31}", d30, d31, d30, d31); + TESTINSN_VSTn("vst1.8 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn("vst1.16 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn("vst1.32 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn("vst1.64 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn("vst1.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn("vst1.16 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn("vst1.32 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn("vst1.64 {d0-d3}", d0, d1, d2, d3); + + printf("---- VST1 (single element from one lane) ----\n"); + TESTINSN_VSTn("vst1.32 {d0[0]}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.32 {d0[1]}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.16 {d1[0]}", d1, d1, d1, d1); + TESTINSN_VSTn("vst1.16 {d1[1]}", d1, d1, d1, d1); + TESTINSN_VSTn("vst1.16 {d1[2]}", d1, d1, d1, d1); + TESTINSN_VSTn("vst1.16 {d1[3]}", d1, d1, d1, d1); + TESTINSN_VSTn("vst1.8 {d0[7]}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.8 {d1[6]}", d1, d1, d1, d1); + TESTINSN_VSTn("vst1.8 {d0[5]}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.8 {d0[4]}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.8 {d20[3]}", d20, d20, d20, d20); + TESTINSN_VSTn("vst1.8 {d0[2]}", d0, d0, d0, d0); + TESTINSN_VSTn("vst1.8 {d17[1]}", d17, d17, d17, d17); + TESTINSN_VSTn("vst1.8 {d30[0]}", d30, d30, d30, d30); + + printf("---- VST2 (multiple 2-elements) ----\n"); + TESTINSN_VSTn("vst2.8 {d30-d31}", d30, d31, d30, d31); + TESTINSN_VSTn("vst2.16 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VSTn("vst2.32 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VSTn("vst2.8 {d10,d12}", d10, d12, d10, d12); + TESTINSN_VSTn("vst2.16 {d20,d22}", d20, d22, d20, d22); + TESTINSN_VSTn("vst2.32 {d0,d2}", d0, d2, d0, d2); + TESTINSN_VSTn("vst2.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn("vst2.16 {d20-d23}", d20, d21, d22, d23); + TESTINSN_VSTn("vst2.32 {d0-d3}", d0, d1, d2, d3); + + printf("---- VST2 (single 2-element structure from one lane) ----\n"); + TESTINSN_VSTn("vst2.32 {d0[0],d1[0]}", d0, d1, d0, d1); + TESTINSN_VSTn("vst2.32 {d0[1],d1[1]}", d0, d1, d0, d1); + TESTINSN_VSTn("vst2.32 {d0[0],d2[0]}", d0, d2, d0, d2); + TESTINSN_VSTn("vst2.32 {d0[1],d2[1]}", d0, d2, d0, d2); + TESTINSN_VSTn("vst2.16 {d1[0],d2[0]}", d1, d2, d1, d2); + TESTINSN_VSTn("vst2.16 {d1[1],d2[1]}", d1, d2, d1, d2); + TESTINSN_VSTn("vst2.16 {d1[2],d2[2]}", d1, d2, d1, d2); + TESTINSN_VSTn("vst2.16 {d1[3],d2[3]}", d1, d2, d1, d2); + TESTINSN_VSTn("vst2.16 {d1[0],d3[0]}", d1, d3, d1, d3); + TESTINSN_VSTn("vst2.16 {d1[1],d3[1]}", d1, d3, d1, d3); + TESTINSN_VSTn("vst2.16 {d1[2],d3[2]}", d1, d3, d1, d3); + TESTINSN_VSTn("vst2.16 {d1[3],d3[3]}", d1, d3, d1, d3); + TESTINSN_VSTn("vst2.8 {d0[7],d1[7]}", d0, d1, d0, d1); + TESTINSN_VSTn("vst2.8 {d1[6],d2[6]}", d1, d2, d1, d2); + TESTINSN_VSTn("vst2.8 {d0[5],d1[5]}", d0, d1, d0, d1); + TESTINSN_VSTn("vst2.8 {d0[4],d1[4]}", d0, d1, d0, d1); + TESTINSN_VSTn("vst2.8 {d20[3],d21[3]}", d20, d21, d20, d21); + TESTINSN_VSTn("vst2.8 {d0[2],d1[2]}", d0, d1, d0, d1); + TESTINSN_VSTn("vst2.8 {d17[1],d18[1]}", d17, d18, d17, d18); + TESTINSN_VSTn("vst2.8 {d30[0],d31[0]}", d30, d31, d30, d31); + + printf("---- VST3 (multiple 3-elements) ----\n"); + TESTINSN_VSTn("vst3.8 {d20-d22}", d20, d21, d22, d20); + TESTINSN_VSTn("vst3.16 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn("vst3.32 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn("vst3.8 {d0,d2,d4}", d0, d2, d4, d0); + TESTINSN_VSTn("vst3.16 {d20,d22,d24}", d20, d22, d24, d20); + TESTINSN_VSTn("vst3.32 {d0,d2,d4}", d0, d2, d4, d0); + + printf("---- VST3 (single 3-element structure from one lane) ----\n"); + TESTINSN_VSTn("vst3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1); + TESTINSN_VSTn("vst3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1); + TESTINSN_VSTn("vst3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2); + TESTINSN_VSTn("vst3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2); + TESTINSN_VSTn("vst3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2); + TESTINSN_VSTn("vst3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2); + TESTINSN_VSTn("vst3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2); + TESTINSN_VSTn("vst3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2); + TESTINSN_VSTn("vst3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5); + TESTINSN_VSTn("vst3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5); + TESTINSN_VSTn("vst3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5); + TESTINSN_VSTn("vst3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5); + TESTINSN_VSTn("vst3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1); + TESTINSN_VSTn("vst3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2); + TESTINSN_VSTn("vst3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1); + TESTINSN_VSTn("vst3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1); + TESTINSN_VSTn("vst3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21); + TESTINSN_VSTn("vst3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1); + TESTINSN_VSTn("vst3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18); + TESTINSN_VSTn("vst3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31); + + printf("---- VST4 (multiple 4-elements) ----\n"); + TESTINSN_VSTn("vst4.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn("vst4.16 {d20-d23}", d20, d21, d22, d23); + TESTINSN_VSTn("vst4.32 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn("vst4.8 {d0,d2,d4,d6}", d0, d2, d4, d6); + TESTINSN_VSTn("vst4.16 {d1,d3,d5,d7}", d1, d3, d5, d7); + TESTINSN_VSTn("vst4.32 {d20,d22,d24,d26}", d20, d22, d24, d26); + + printf("---- VST4 (single 4-element structure from one lane) ----\n"); + TESTINSN_VSTn("vst4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3); + TESTINSN_VSTn("vst4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4); + TESTINSN_VSTn("vst4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6); + TESTINSN_VSTn("vst4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6); + TESTINSN_VSTn("vst4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4); + TESTINSN_VSTn("vst4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4); + TESTINSN_VSTn("vst4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4); + TESTINSN_VSTn("vst4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4); + TESTINSN_VSTn("vst4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7); + TESTINSN_VSTn("vst4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7); + TESTINSN_VSTn("vst4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7); + TESTINSN_VSTn("vst4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7); + TESTINSN_VSTn("vst4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3); + TESTINSN_VSTn("vst4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4); + TESTINSN_VSTn("vst4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3); + TESTINSN_VSTn("vst4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3); + TESTINSN_VSTn("vst4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23); + TESTINSN_VSTn("vst4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3); + TESTINSN_VSTn("vst4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20); + TESTINSN_VSTn("vst4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31); + + printf("---- VLD1 (multiple single elements) ----\n"); + TESTINSN_VLDn_WB("vld1.8 {d0}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.16 {d0}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.32 {d0}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.64 {d0}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.8 {d9}", d9, d9, d9, d9); + TESTINSN_VLDn_WB("vld1.16 {d17}", d17, d17, d17, d17); + TESTINSN_VLDn_WB("vld1.32 {d31}", d31, d31, d31, d31); + TESTINSN_VLDn_WB("vld1.64 {d14}", d14, d14, d14, d14); + TESTINSN_VLDn_WB("vld1.8 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld1.16 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld1.32 {d5-d6}", d5, d6, d5, d6); + TESTINSN_VLDn_WB("vld1.64 {d30-d31}", d30, d31, d30, d31); + TESTINSN_VLDn_WB("vld1.8 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn_WB("vld1.16 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn_WB("vld1.32 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn_WB("vld1.64 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn_WB("vld1.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld1.16 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld1.32 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld1.64 {d0-d3}", d0, d1, d2, d3); + + printf("---- VLD1 (single element to one lane) ----\n"); + TESTINSN_VLDn_WB("vld1.32 {d0[0]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.32 {d0[1]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.16 {d1[0]}", d1, d1, d1, d1); + TESTINSN_VLDn_WB("vld1.16 {d1[1]}", d1, d1, d1, d1); + TESTINSN_VLDn_WB("vld1.16 {d1[2]}", d1, d1, d1, d1); + TESTINSN_VLDn_WB("vld1.16 {d1[3]}", d1, d1, d1, d1); + TESTINSN_VLDn_WB("vld1.8 {d0[7]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.8 {d1[6]}", d1, d1, d1, d1); + TESTINSN_VLDn_WB("vld1.8 {d0[5]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.8 {d0[4]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.8 {d20[3]}", d20, d20, d20, d20); + TESTINSN_VLDn_WB("vld1.8 {d0[2]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.8 {d17[1]}", d17, d17, d17, d17); + TESTINSN_VLDn_WB("vld1.8 {d30[0]}", d30, d30, d30, d30); + + printf("---- VLD1 (single element to all lanes) ----\n"); + TESTINSN_VLDn_WB("vld1.8 {d0[]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.16 {d0[]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.32 {d0[]}", d0, d0, d0, d0); + TESTINSN_VLDn_WB("vld1.8 {d9[]}", d9, d9, d9, d9); + TESTINSN_VLDn_WB("vld1.16 {d17[]}", d17, d17, d17, d17); + TESTINSN_VLDn_WB("vld1.32 {d31[]}", d31, d31, d31, d31); + TESTINSN_VLDn_WB("vld1.8 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld1.16 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld1.32 {d5[],d6[]}", d5, d6, d5, d6); + + printf("---- VLD2 (multiple 2-elements) ----\n"); + TESTINSN_VLDn_WB("vld2.8 {d30-d31}", d30, d31, d30, d31); + TESTINSN_VLDn_WB("vld2.16 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.32 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.8 {d10,d12}", d10, d12, d10, d12); + TESTINSN_VLDn_WB("vld2.16 {d20,d22}", d20, d22, d20, d22); + TESTINSN_VLDn_WB("vld2.32 {d0,d2}", d0, d2, d0, d2); + TESTINSN_VLDn_WB("vld2.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld2.16 {d20-d23}", d20, d21, d22, d23); + TESTINSN_VLDn_WB("vld2.32 {d0-d3}", d0, d1, d2, d3); + + printf("---- VLD2 (single 2-element structure to one lane) ----\n"); + TESTINSN_VLDn_WB("vld2.32 {d0[0],d1[0]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.32 {d0[1],d1[1]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.32 {d0[0],d2[0]}", d0, d2, d0, d2); + TESTINSN_VLDn_WB("vld2.32 {d0[1],d2[1]}", d0, d2, d0, d2); + TESTINSN_VLDn_WB("vld2.16 {d1[0],d2[0]}", d1, d2, d1, d2); + TESTINSN_VLDn_WB("vld2.16 {d1[1],d2[1]}", d1, d2, d1, d2); + TESTINSN_VLDn_WB("vld2.16 {d1[2],d2[2]}", d1, d2, d1, d2); + TESTINSN_VLDn_WB("vld2.16 {d1[3],d2[3]}", d1, d2, d1, d2); + TESTINSN_VLDn_WB("vld2.16 {d1[0],d3[0]}", d1, d3, d1, d3); + TESTINSN_VLDn_WB("vld2.16 {d1[1],d3[1]}", d1, d3, d1, d3); + TESTINSN_VLDn_WB("vld2.16 {d1[2],d3[2]}", d1, d3, d1, d3); + TESTINSN_VLDn_WB("vld2.16 {d1[3],d3[3]}", d1, d3, d1, d3); + TESTINSN_VLDn_WB("vld2.8 {d0[7],d1[7]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.8 {d1[6],d2[6]}", d1, d2, d1, d2); + TESTINSN_VLDn_WB("vld2.8 {d0[5],d1[5]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.8 {d0[4],d1[4]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.8 {d20[3],d21[3]}", d20, d21, d20, d21); + TESTINSN_VLDn_WB("vld2.8 {d0[2],d1[2]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.8 {d17[1],d18[1]}", d17, d18, d17, d18); + TESTINSN_VLDn_WB("vld2.8 {d30[0],d31[0]}", d30, d31, d30, d31); + + printf("---- VLD2 (2-elements to all lanes) ----\n"); + TESTINSN_VLDn_WB("vld2.8 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.16 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.32 {d0[],d1[]}", d0, d1, d0, d1); + TESTINSN_VLDn_WB("vld2.8 {d9[],d11[]}", d9, d11, d9, d11); + TESTINSN_VLDn_WB("vld2.16 {d17[],d18[]}", d17, d18, d17, d18); + TESTINSN_VLDn_WB("vld2.32 {d30[],d31[]}", d30, d31, d30, d31); + TESTINSN_VLDn_WB("vld2.8 {d0[],d2[]}", d0, d2, d0, d2); + TESTINSN_VLDn_WB("vld2.16 {d0[],d2[]}", d0, d2, d0, d2); + TESTINSN_VLDn_WB("vld2.32 {d5[],d7[]}", d5, d7, d5, d7); + + printf("---- VLD3 (multiple 3-elements) ----\n"); + TESTINSN_VLDn_WB("vld3.8 {d20-d22}", d20, d21, d22, d20); + TESTINSN_VLDn_WB("vld3.16 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn_WB("vld3.32 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VLDn_WB("vld3.8 {d0,d2,d4}", d0, d2, d4, d0); + TESTINSN_VLDn_WB("vld3.16 {d20,d22,d24}", d20, d22, d24, d20); + TESTINSN_VLDn_WB("vld3.32 {d0,d2,d4}", d0, d2, d4, d0); + + printf("---- VLD3 (single 3-element structure to one lane) ----\n"); + TESTINSN_VLDn_WB("vld3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2); + TESTINSN_VLDn_WB("vld3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2); + TESTINSN_VLDn_WB("vld3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2); + TESTINSN_VLDn_WB("vld3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2); + TESTINSN_VLDn_WB("vld3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2); + TESTINSN_VLDn_WB("vld3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2); + TESTINSN_VLDn_WB("vld3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5); + TESTINSN_VLDn_WB("vld3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5); + TESTINSN_VLDn_WB("vld3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5); + TESTINSN_VLDn_WB("vld3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5); + TESTINSN_VLDn_WB("vld3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2); + TESTINSN_VLDn_WB("vld3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21); + TESTINSN_VLDn_WB("vld3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18); + TESTINSN_VLDn_WB("vld3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31); + + printf("---- VLD3 (3-elements to all lanes) ----\n"); + TESTINSN_VLDn_WB("vld3.8 {d0[],d1[],d2[]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.16 {d0[],d1[],d2[]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.32 {d0[],d1[],d2[]}", d0, d1, d2, d1); + TESTINSN_VLDn_WB("vld3.8 {d9[],d11[],d13[]}", d9, d11, d13, d11); + TESTINSN_VLDn_WB("vld3.16 {d17[],d18[],d19[]}", d17, d18, d19, d18); + TESTINSN_VLDn_WB("vld3.32 {d29[],d30[],d31[]}", d29, d30, d30, d31); + TESTINSN_VLDn_WB("vld3.8 {d0[],d2[],d4[]}", d0, d2, d4, d2); + TESTINSN_VLDn_WB("vld3.16 {d0[],d2[],d4[]}", d0, d2, d4, d2); + TESTINSN_VLDn_WB("vld3.32 {d5[],d7[],d9[]}", d5, d7, d9, d7); + + printf("---- VLD4 (multiple 3-elements) ----\n"); + TESTINSN_VLDn_WB("vld4.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.16 {d20-d23}", d20, d21, d22, d23); + TESTINSN_VLDn_WB("vld4.32 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.8 {d0,d2,d4,d6}", d0, d2, d4, d6); + TESTINSN_VLDn_WB("vld4.16 {d1,d3,d5,d7}", d1, d3, d5, d7); + TESTINSN_VLDn_WB("vld4.32 {d20,d22,d24,d26}", d20, d22, d24, d26); + + printf("---- VLD4 (single 4-element structure to one lane) ----\n"); + TESTINSN_VLDn_WB("vld4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4); + TESTINSN_VLDn_WB("vld4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6); + TESTINSN_VLDn_WB("vld4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6); + TESTINSN_VLDn_WB("vld4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4); + TESTINSN_VLDn_WB("vld4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4); + TESTINSN_VLDn_WB("vld4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4); + TESTINSN_VLDn_WB("vld4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4); + TESTINSN_VLDn_WB("vld4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7); + TESTINSN_VLDn_WB("vld4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7); + TESTINSN_VLDn_WB("vld4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7); + TESTINSN_VLDn_WB("vld4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7); + TESTINSN_VLDn_WB("vld4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4); + TESTINSN_VLDn_WB("vld4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23); + TESTINSN_VLDn_WB("vld4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20); + TESTINSN_VLDn_WB("vld4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31); + + printf("---- VLD4 (4-elements to all lanes) ----\n"); + TESTINSN_VLDn_WB("vld4.8 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.16 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.32 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3); + TESTINSN_VLDn_WB("vld4.8 {d9[],d11[],d13[],d15[]}", d9, d11, d13, d15); + TESTINSN_VLDn_WB("vld4.16 {d17[],d18[],d19[],d20[]}", d17, d18, d19, d20); + TESTINSN_VLDn_WB("vld4.32 {d28[],d29[],d30[],d31[]}", d28, d29, d30, d31); + TESTINSN_VLDn_WB("vld4.8 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6); + TESTINSN_VLDn_WB("vld4.16 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6); + TESTINSN_VLDn_WB("vld4.32 {d5[],d7[],d9[],d11[]}", d5, d7, d9, d11); + + printf("---- VST1 (multiple single elements) ----\n"); + TESTINSN_VSTn_WB("vst1.8 {d0}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.16 {d0}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.32 {d0}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.64 {d0}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.8 {d9}", d9, d9, d9, d9); + TESTINSN_VSTn_WB("vst1.16 {d17}", d17, d17, d17, d17); + TESTINSN_VSTn_WB("vst1.32 {d31}", d31, d31, d31, d31); + TESTINSN_VSTn_WB("vst1.64 {d14}", d14, d14, d14, d14); + TESTINSN_VSTn_WB("vst1.8 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst1.16 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst1.32 {d5-d6}", d5, d6, d5, d6); + TESTINSN_VSTn_WB("vst1.64 {d30-d31}", d30, d31, d30, d31); + TESTINSN_VSTn_WB("vst1.8 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn_WB("vst1.16 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn_WB("vst1.32 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn_WB("vst1.64 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn_WB("vst1.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst1.16 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst1.32 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst1.64 {d0-d3}", d0, d1, d2, d3); + + printf("---- VST1 (single element from one lane) ----\n"); + TESTINSN_VSTn_WB("vst1.32 {d0[0]}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.32 {d0[1]}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.16 {d1[0]}", d1, d1, d1, d1); + TESTINSN_VSTn_WB("vst1.16 {d1[1]}", d1, d1, d1, d1); + TESTINSN_VSTn_WB("vst1.16 {d1[2]}", d1, d1, d1, d1); + TESTINSN_VSTn_WB("vst1.16 {d1[3]}", d1, d1, d1, d1); + TESTINSN_VSTn_WB("vst1.8 {d0[7]}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.8 {d1[6]}", d1, d1, d1, d1); + TESTINSN_VSTn_WB("vst1.8 {d0[5]}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.8 {d0[4]}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.8 {d20[3]}", d20, d20, d20, d20); + TESTINSN_VSTn_WB("vst1.8 {d0[2]}", d0, d0, d0, d0); + TESTINSN_VSTn_WB("vst1.8 {d17[1]}", d17, d17, d17, d17); + TESTINSN_VSTn_WB("vst1.8 {d30[0]}", d30, d30, d30, d30); + + printf("---- VST2 (multiple 2-elements) ----\n"); + TESTINSN_VSTn_WB("vst2.8 {d30-d31}", d30, d31, d30, d31); + TESTINSN_VSTn_WB("vst2.16 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst2.32 {d0-d1}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst2.8 {d10,d12}", d10, d12, d10, d12); + TESTINSN_VSTn_WB("vst2.16 {d20,d22}", d20, d22, d20, d22); + TESTINSN_VSTn_WB("vst2.32 {d0,d2}", d0, d2, d0, d2); + TESTINSN_VSTn_WB("vst2.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst2.16 {d20-d23}", d20, d21, d22, d23); + TESTINSN_VSTn_WB("vst2.32 {d0-d3}", d0, d1, d2, d3); + + printf("---- VST2 (single 2-element structure from one lane) ----\n"); + TESTINSN_VSTn_WB("vst2.32 {d0[0],d1[0]}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst2.32 {d0[1],d1[1]}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst2.32 {d0[0],d2[0]}", d0, d2, d0, d2); + TESTINSN_VSTn_WB("vst2.32 {d0[1],d2[1]}", d0, d2, d0, d2); + TESTINSN_VSTn_WB("vst2.16 {d1[0],d2[0]}", d1, d2, d1, d2); + TESTINSN_VSTn_WB("vst2.16 {d1[1],d2[1]}", d1, d2, d1, d2); + TESTINSN_VSTn_WB("vst2.16 {d1[2],d2[2]}", d1, d2, d1, d2); + TESTINSN_VSTn_WB("vst2.16 {d1[3],d2[3]}", d1, d2, d1, d2); + TESTINSN_VSTn_WB("vst2.16 {d1[0],d3[0]}", d1, d3, d1, d3); + TESTINSN_VSTn_WB("vst2.16 {d1[1],d3[1]}", d1, d3, d1, d3); + TESTINSN_VSTn_WB("vst2.16 {d1[2],d3[2]}", d1, d3, d1, d3); + TESTINSN_VSTn_WB("vst2.16 {d1[3],d3[3]}", d1, d3, d1, d3); + TESTINSN_VSTn_WB("vst2.8 {d0[7],d1[7]}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst2.8 {d1[6],d2[6]}", d1, d2, d1, d2); + TESTINSN_VSTn_WB("vst2.8 {d0[5],d1[5]}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst2.8 {d0[4],d1[4]}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst2.8 {d20[3],d21[3]}", d20, d21, d20, d21); + TESTINSN_VSTn_WB("vst2.8 {d0[2],d1[2]}", d0, d1, d0, d1); + TESTINSN_VSTn_WB("vst2.8 {d17[1],d18[1]}", d17, d18, d17, d18); + TESTINSN_VSTn_WB("vst2.8 {d30[0],d31[0]}", d30, d31, d30, d31); + + printf("---- VST3 (multiple 3-elements) ----\n"); + TESTINSN_VSTn_WB("vst3.8 {d20-d22}", d20, d21, d22, d20); + TESTINSN_VSTn_WB("vst3.16 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn_WB("vst3.32 {d0-d2}", d0, d1, d2, d0); + TESTINSN_VSTn_WB("vst3.8 {d0,d2,d4}", d0, d2, d4, d0); + TESTINSN_VSTn_WB("vst3.16 {d20,d22,d24}", d20, d22, d24, d20); + TESTINSN_VSTn_WB("vst3.32 {d0,d2,d4}", d0, d2, d4, d0); + + printf("---- VST3 (single 3-element structure from one lane) ----\n"); + TESTINSN_VSTn_WB("vst3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1); + TESTINSN_VSTn_WB("vst3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1); + TESTINSN_VSTn_WB("vst3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2); + TESTINSN_VSTn_WB("vst3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2); + TESTINSN_VSTn_WB("vst3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2); + TESTINSN_VSTn_WB("vst3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2); + TESTINSN_VSTn_WB("vst3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2); + TESTINSN_VSTn_WB("vst3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2); + TESTINSN_VSTn_WB("vst3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5); + TESTINSN_VSTn_WB("vst3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5); + TESTINSN_VSTn_WB("vst3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5); + TESTINSN_VSTn_WB("vst3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5); + TESTINSN_VSTn_WB("vst3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1); + TESTINSN_VSTn_WB("vst3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2); + TESTINSN_VSTn_WB("vst3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1); + TESTINSN_VSTn_WB("vst3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1); + TESTINSN_VSTn_WB("vst3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21); + TESTINSN_VSTn_WB("vst3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1); + TESTINSN_VSTn_WB("vst3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18); + TESTINSN_VSTn_WB("vst3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31); + + printf("---- VST4 (multiple 4-elements) ----\n"); + TESTINSN_VSTn_WB("vst4.8 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst4.16 {d20-d23}", d20, d21, d22, d23); + TESTINSN_VSTn_WB("vst4.32 {d0-d3}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst4.8 {d0,d2,d4,d6}", d0, d2, d4, d6); + TESTINSN_VSTn_WB("vst4.16 {d1,d3,d5,d7}", d1, d3, d5, d7); + TESTINSN_VSTn_WB("vst4.32 {d20,d22,d24,d26}", d20, d22, d24, d26); + + printf("---- VST4 (single 4-element structure from one lane) ----\n"); + TESTINSN_VSTn_WB("vst4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4); + TESTINSN_VSTn_WB("vst4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6); + TESTINSN_VSTn_WB("vst4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6); + TESTINSN_VSTn_WB("vst4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4); + TESTINSN_VSTn_WB("vst4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4); + TESTINSN_VSTn_WB("vst4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4); + TESTINSN_VSTn_WB("vst4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4); + TESTINSN_VSTn_WB("vst4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7); + TESTINSN_VSTn_WB("vst4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7); + TESTINSN_VSTn_WB("vst4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7); + TESTINSN_VSTn_WB("vst4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7); + TESTINSN_VSTn_WB("vst4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4); + TESTINSN_VSTn_WB("vst4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23); + TESTINSN_VSTn_WB("vst4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3); + TESTINSN_VSTn_WB("vst4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20); + TESTINSN_VSTn_WB("vst4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31); + + printf("---- VLD1 (multiple single elements) ----\n"); + TESTINSN_VLDn_RI("vld1.8 {d0}", d0, d0, d0, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.16 {d0}", d0, d0, d0, d0, r8, 13); + TESTINSN_VLDn_RI("vld1.32 {d0}", d0, d0, d0, d0, r5, 42); + TESTINSN_VLDn_RI("vld1.64 {d0}", d0, d0, d0, d0, r5, 0); + TESTINSN_VLDn_RI("vld1.8 {d9}", d9, d9, d9, d9, r5, 13); + TESTINSN_VLDn_RI("vld1.16 {d17}", d17, d17, d17, d17, r6, 13); + TESTINSN_VLDn_RI("vld1.32 {d31}", d31, d31, d31, d31, r5, -3); + TESTINSN_VLDn_RI("vld1.64 {d14}", d14, d14, d14, d14, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d0-d1}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld1.16 {d0-d1}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld1.32 {d5-d6}", d5, d6, d5, d6, r5, 13); + TESTINSN_VLDn_RI("vld1.64 {d30-d31}", d30, d31, d30, d31, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d0-d2}", d0, d1, d2, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.16 {d0-d2}", d0, d1, d2, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.32 {d0-d2}", d0, d1, d2, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.64 {d0-d2}", d0, d1, d2, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld1.16 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld1.32 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld1.64 {d0-d3}", d0, d1, d2, d3, r5, 13); + + printf("---- VLD1 (single element to one lane) ----\n"); + TESTINSN_VLDn_RI("vld1.32 {d0[0]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.32 {d0[1]}", d0, d0, d0, d0, r9, 42); + TESTINSN_VLDn_RI("vld1.16 {d1[0]}", d1, d1, d1, d1, r5, 13); + TESTINSN_VLDn_RI("vld1.16 {d1[1]}", d1, d1, d1, d1, r1, 0); + TESTINSN_VLDn_RI("vld1.16 {d1[2]}", d1, d1, d1, d1, r5, -3); + TESTINSN_VLDn_RI("vld1.16 {d1[3]}", d1, d1, d1, d1, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d0[7]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d1[6]}", d1, d1, d1, d1, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d0[5]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d0[4]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d20[3]}", d20, d20, d20, d20, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d0[2]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d17[1]}", d17, d17, d17, d17, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d30[0]}", d30, d30, d30, d30, r5, 13); + + printf("---- VLD1 (single element to all lanes) ----\n"); + TESTINSN_VLDn_RI("vld1.8 {d0[]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VLDn_RI("vld1.16 {d0[]}", d0, d0, d0, d0, r9, 42); + TESTINSN_VLDn_RI("vld1.32 {d0[]}", d0, d0, d0, d0, r1, 0); + TESTINSN_VLDn_RI("vld1.8 {d9[]}", d9, d9, d9, d9, r5, -3); + TESTINSN_VLDn_RI("vld1.16 {d17[]}", d17, d17, d17, d17, r5, 13); + TESTINSN_VLDn_RI("vld1.32 {d31[]}", d31, d31, d31, d31, r5, 13); + TESTINSN_VLDn_RI("vld1.8 {d0[],d1[]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld1.16 {d0[],d1[]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld1.32 {d5[],d6[]}", d5, d6, d5, d6, r5, 13); + + printf("---- VLD2 (multiple 2-elements) ----\n"); + TESTINSN_VLDn_RI("vld2.8 {d30-d31}", d30, d31, d30, d31, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d0-d1}", d0, d1, d0, d1, r9, 42); + TESTINSN_VLDn_RI("vld2.32 {d0-d1}", d0, d1, d0, d1, r1, 0); + TESTINSN_VLDn_RI("vld2.8 {d10,d12}", d10, d12, d10, d12, r5, -3); + TESTINSN_VLDn_RI("vld2.16 {d20,d22}", d20, d22, d20, d22, r5, 13); + TESTINSN_VLDn_RI("vld2.32 {d0,d2}", d0, d2, d0, d2, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d20-d23}", d20, d21, d22, d23, r5, 13); + TESTINSN_VLDn_RI("vld2.32 {d0-d3}", d0, d1, d2, d3, r5, 13); + + printf("---- VLD2 (single 2-element structure to one lane) ----\n"); + TESTINSN_VLDn_RI("vld2.32 {d0[0],d1[0]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld2.32 {d0[1],d1[1]}", d0, d1, d0, d1, r9, 42); + TESTINSN_VLDn_RI("vld2.32 {d0[0],d2[0]}", d0, d2, d0, d2, r1, 0); + TESTINSN_VLDn_RI("vld2.32 {d0[1],d2[1]}", d0, d2, d0, d2, r5, -3); + TESTINSN_VLDn_RI("vld2.16 {d1[0],d2[0]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d1[1],d2[1]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d1[2],d2[2]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d1[3],d2[3]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d1[0],d3[0]}", d1, d3, d1, d3, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d1[1],d3[1]}", d1, d3, d1, d3, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d1[2],d3[2]}", d1, d3, d1, d3, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d1[3],d3[3]}", d1, d3, d1, d3, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d0[7],d1[7]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d1[6],d2[6]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d0[5],d1[5]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d0[4],d1[4]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d20[3],d21[3]}", d20, d21, d20, d21, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d0[2],d1[2]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d17[1],d18[1]}", d17, d18, d17, d18, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d30[0],d31[0]}", d30, d31, d30, d31, r5, 13); + + printf("---- VLD2 (2-elements to all lanes) ----\n"); + TESTINSN_VLDn_RI("vld2.8 {d0[],d1[]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d0[],d1[]}", d0, d1, d0, d1, r9, 42); + TESTINSN_VLDn_RI("vld2.32 {d0[],d1[]}", d0, d1, d0, d1, r1, 0); + TESTINSN_VLDn_RI("vld2.8 {d9[],d11[]}", d9, d11, d9, d11, r5, -3); + TESTINSN_VLDn_RI("vld2.16 {d17[],d18[]}", d17, d18, d17, d18, r5, 13); + TESTINSN_VLDn_RI("vld2.32 {d30[],d31[]}", d30, d31, d30, d31, r5, 13); + TESTINSN_VLDn_RI("vld2.8 {d0[],d2[]}", d0, d2, d0, d2, r5, 13); + TESTINSN_VLDn_RI("vld2.16 {d0[],d2[]}", d0, d2, d0, d2, r5, 13); + TESTINSN_VLDn_RI("vld2.32 {d5[],d7[]}", d5, d7, d5, d7, r5, 13); + + printf("---- VLD3 (multiple 3-elements) ----\n"); + TESTINSN_VLDn_RI("vld3.8 {d20-d22}", d20, d21, d22, d20, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d0-d2}", d0, d1, d2, d0, r9, 42); + TESTINSN_VLDn_RI("vld3.32 {d0-d2}", d0, d1, d2, d0, r1, 0); + TESTINSN_VLDn_RI("vld3.8 {d0,d2,d4}", d0, d2, d4, d0, r5, -3); + TESTINSN_VLDn_RI("vld3.16 {d20,d22,d24}", d20, d22, d24, d20, r5, 13); + TESTINSN_VLDn_RI("vld3.32 {d0,d2,d4}", d0, d2, d4, d0, r5, 13); + + printf("---- VLD3 (single 3-element structure to one lane) ----\n"); + TESTINSN_VLDn_RI("vld3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VLDn_RI("vld3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1, r9, 42); + TESTINSN_VLDn_RI("vld3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2, r1, 0); + TESTINSN_VLDn_RI("vld3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2, r5, -3); + TESTINSN_VLDn_RI("vld3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31, r5, 13); + + printf("---- VLD3 (3-elements to all lanes) ----\n"); + TESTINSN_VLDn_RI("vld3.8 {d0[],d1[],d2[]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d0[],d1[],d2[]}", d0, d1, d2, d1, r9, 42); + TESTINSN_VLDn_RI("vld3.32 {d0[],d1[],d2[]}", d0, d1, d2, d1, r1, 0); + TESTINSN_VLDn_RI("vld3.8 {d9[],d11[],d13[]}", d9, d11, d13, d11, r5, -3); + TESTINSN_VLDn_RI("vld3.16 {d17[],d18[],d19[]}", d17, d18, d19, d18, r5, 13); + TESTINSN_VLDn_RI("vld3.32 {d29[],d30[],d31[]}", d29, d30, d30, d31, r5, 13); + TESTINSN_VLDn_RI("vld3.8 {d0[],d2[],d4[]}", d0, d2, d4, d2, r5, 13); + TESTINSN_VLDn_RI("vld3.16 {d0[],d2[],d4[]}", d0, d2, d4, d2, r5, 13); + TESTINSN_VLDn_RI("vld3.32 {d5[],d7[],d9[]}", d5, d7, d9, d7, r5, 13); + + printf("---- VLD4 (multiple 3-elements) ----\n"); + TESTINSN_VLDn_RI("vld4.8 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d20-d23}", d20, d21, d22, d23, r9, 0); + TESTINSN_VLDn_RI("vld4.32 {d0-d3}", d0, d1, d2, d3, r0, 42); + TESTINSN_VLDn_RI("vld4.8 {d0,d2,d4,d6}", d0, d2, d4, d6, r5, -3); + TESTINSN_VLDn_RI("vld4.16 {d1,d3,d5,d7}", d1, d3, d5, d7, r5, 13); + TESTINSN_VLDn_RI("vld4.32 {d20,d22,d24,d26}", d20, d22, d24, d26, r5, 13); + + printf("---- VLD4 (single 4-element structure to one lane) ----\n"); + TESTINSN_VLDn_RI("vld4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4, r9, 42); + TESTINSN_VLDn_RI("vld4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6, r1, 0); + TESTINSN_VLDn_RI("vld4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6, r5, -3); + TESTINSN_VLDn_RI("vld4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31, r5, 13); + + printf("---- VLD4 (4-elements to all lanes) ----\n"); + TESTINSN_VLDn_RI("vld4.8 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3, r9, 42); + TESTINSN_VLDn_RI("vld4.32 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3, r1, 0); + TESTINSN_VLDn_RI("vld4.8 {d9[],d11[],d13[],d15[]}", d9, d11, d13, d15, r5, -3); + TESTINSN_VLDn_RI("vld4.16 {d17[],d18[],d19[],d20[]}", d17, d18, d19, d20, r5, 13); + TESTINSN_VLDn_RI("vld4.32 {d28[],d29[],d30[],d31[]}", d28, d29, d30, d31, r5, 13); + TESTINSN_VLDn_RI("vld4.8 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6, r5, 13); + TESTINSN_VLDn_RI("vld4.16 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6, r5, 13); + TESTINSN_VLDn_RI("vld4.32 {d5[],d7[],d9[],d11[]}", d5, d7, d9, d11, r5, 13); + + printf("---- VST1 (multiple single elements) ----\n"); + TESTINSN_VSTn_RI("vst1.8 {d0}", d0, d0, d0, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.16 {d0}", d0, d0, d0, d0, r9, 42); + TESTINSN_VSTn_RI("vst1.32 {d0}", d0, d0, d0, d0, r5, 0); + TESTINSN_VSTn_RI("vst1.64 {d0}", d0, d0, d0, d0, r5, -3); + TESTINSN_VSTn_RI("vst1.8 {d9}", d9, d9, d9, d9, r5, 13); + TESTINSN_VSTn_RI("vst1.16 {d17}", d17, d17, d17, d17, r5, 13); + TESTINSN_VSTn_RI("vst1.32 {d31}", d31, d31, d31, d31, r5, 13); + TESTINSN_VSTn_RI("vst1.64 {d14}", d14, d14, d14, d14, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d0-d1}", d0, d1, d0, d1, r5, 13); + TESTINSN_VSTn_RI("vst1.16 {d0-d1}", d0, d1, d0, d1, r5, 13); + TESTINSN_VSTn_RI("vst1.32 {d5-d6}", d5, d6, d5, d6, r5, 13); + TESTINSN_VSTn_RI("vst1.64 {d30-d31}", d30, d31, d30, d31, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d0-d2}", d0, d1, d2, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.16 {d0-d2}", d0, d1, d2, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.32 {d0-d2}", d0, d1, d2, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.64 {d0-d2}", d0, d1, d2, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst1.16 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst1.32 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst1.64 {d0-d3}", d0, d1, d2, d3, r5, 13); + + printf("---- VST1 (single element from one lane) ----\n"); + TESTINSN_VSTn_RI("vst1.32 {d0[0]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.32 {d0[1]}", d0, d0, d0, d0, r9, 42); + TESTINSN_VSTn_RI("vst1.16 {d1[0]}", d1, d1, d1, d1, r1, 0); + TESTINSN_VSTn_RI("vst1.16 {d1[1]}", d1, d1, d1, d1, r5, -3); + TESTINSN_VSTn_RI("vst1.16 {d1[2]}", d1, d1, d1, d1, r5, 13); + TESTINSN_VSTn_RI("vst1.16 {d1[3]}", d1, d1, d1, d1, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d0[7]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d1[6]}", d1, d1, d1, d1, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d0[5]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d0[4]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d20[3]}", d20, d20, d20, d20, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d0[2]}", d0, d0, d0, d0, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d17[1]}", d17, d17, d17, d17, r5, 13); + TESTINSN_VSTn_RI("vst1.8 {d30[0]}", d30, d30, d30, d30, r5, 13); + + printf("---- VST2 (multiple 2-elements) ----\n"); + TESTINSN_VSTn_RI("vst2.8 {d30-d31}", d30, d31, d30, d31, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d0-d1}", d0, d1, d0, d1, r9, 42); + TESTINSN_VSTn_RI("vst2.32 {d0-d1}", d0, d1, d0, d1, r1, 0); + TESTINSN_VSTn_RI("vst2.8 {d10,d12}", d10, d12, d10, d12, r5, -3); + TESTINSN_VSTn_RI("vst2.16 {d20,d22}", d20, d22, d20, d22, r5, 13); + TESTINSN_VSTn_RI("vst2.32 {d0,d2}", d0, d2, d0, d2, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d20-d23}", d20, d21, d22, d23, r5, 13); + TESTINSN_VSTn_RI("vst2.32 {d0-d3}", d0, d1, d2, d3, r5, 13); + + printf("---- VST2 (single 2-element structure from one lane) ----\n"); + TESTINSN_VSTn_RI("vst2.32 {d0[0],d1[0]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VSTn_RI("vst2.32 {d0[1],d1[1]}", d0, d1, d0, d1, r9, 42); + TESTINSN_VSTn_RI("vst2.32 {d0[0],d2[0]}", d0, d2, d0, d2, r1, 0); + TESTINSN_VSTn_RI("vst2.32 {d0[1],d2[1]}", d0, d2, d0, d2, r5, -3); + TESTINSN_VSTn_RI("vst2.16 {d1[0],d2[0]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d1[1],d2[1]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d1[2],d2[2]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d1[3],d2[3]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d1[0],d3[0]}", d1, d3, d1, d3, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d1[1],d3[1]}", d1, d3, d1, d3, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d1[2],d3[2]}", d1, d3, d1, d3, r5, 13); + TESTINSN_VSTn_RI("vst2.16 {d1[3],d3[3]}", d1, d3, d1, d3, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d0[7],d1[7]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d1[6],d2[6]}", d1, d2, d1, d2, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d0[5],d1[5]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d0[4],d1[4]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d20[3],d21[3]}", d20, d21, d20, d21, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d0[2],d1[2]}", d0, d1, d0, d1, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d17[1],d18[1]}", d17, d18, d17, d18, r5, 13); + TESTINSN_VSTn_RI("vst2.8 {d30[0],d31[0]}", d30, d31, d30, d31, r5, 13); + + printf("---- VST3 (multiple 3-elements) ----\n"); + TESTINSN_VSTn_RI("vst3.8 {d20-d22}", d20, d21, d22, d20, r5, 13); + TESTINSN_VSTn_RI("vst3.16 {d0-d2}", d0, d1, d2, d0, r9, 42); + TESTINSN_VSTn_RI("vst3.32 {d0-d2}", d0, d1, d2, d0, r1, 0); + TESTINSN_VSTn_RI("vst3.8 {d0,d2,d4}", d0, d2, d4, d0, r5, -3); + TESTINSN_VSTn_RI("vst3.16 {d20,d22,d24}", d20, d22, d24, d20, r5, 13); + TESTINSN_VSTn_RI("vst3.32 {d0,d2,d4}", d0, d2, d4, d0, r5, 13); + + printf("---- VST3 (single 3-element structure from one lane) ----\n"); + TESTINSN_VSTn_RI("vst3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VSTn_RI("vst3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1, r9, 42); + TESTINSN_VSTn_RI("vst3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2, r1, 0); + TESTINSN_VSTn_RI("vst3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2, r5, -3); + TESTINSN_VSTn_RI("vst3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VSTn_RI("vst3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VSTn_RI("vst3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VSTn_RI("vst3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VSTn_RI("vst3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5, r5, 13); + TESTINSN_VSTn_RI("vst3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5, r5, 13); + TESTINSN_VSTn_RI("vst3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5, r5, 13); + TESTINSN_VSTn_RI("vst3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5, r5, 13); + TESTINSN_VSTn_RI("vst3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VSTn_RI("vst3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2, r5, 13); + TESTINSN_VSTn_RI("vst3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VSTn_RI("vst3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VSTn_RI("vst3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21, r5, 13); + TESTINSN_VSTn_RI("vst3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1, r5, 13); + TESTINSN_VSTn_RI("vst3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18, r5, 13); + TESTINSN_VSTn_RI("vst3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31, r5, 13); + + printf("---- VST4 (multiple 4-elements) ----\n"); + TESTINSN_VSTn_RI("vst4.8 {d0-d3}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst4.16 {d20-d23}", d20, d21, d22, d23, r9, 42); + TESTINSN_VSTn_RI("vst4.32 {d0-d3}", d0, d1, d2, d3, r1, 0); + TESTINSN_VSTn_RI("vst4.8 {d0,d2,d4,d6}", d0, d2, d4, d6, r5, -3); + TESTINSN_VSTn_RI("vst4.16 {d1,d3,d5,d7}", d1, d3, d5, d7, r5, 13); + TESTINSN_VSTn_RI("vst4.32 {d20,d22,d24,d26}", d20, d22, d24, d26, r5, 13); + + printf("---- VST4 (single 4-element structure from one lane) ----\n"); + TESTINSN_VSTn_RI("vst4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4, r9, 42); + TESTINSN_VSTn_RI("vst4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6, r1, 0); + TESTINSN_VSTn_RI("vst4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6, r5, -3); + TESTINSN_VSTn_RI("vst4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VSTn_RI("vst4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VSTn_RI("vst4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VSTn_RI("vst4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VSTn_RI("vst4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7, r5, 13); + TESTINSN_VSTn_RI("vst4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7, r5, 13); + TESTINSN_VSTn_RI("vst4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7, r5, 13); + TESTINSN_VSTn_RI("vst4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7, r5, 13); + TESTINSN_VSTn_RI("vst4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4, r5, 13); + TESTINSN_VSTn_RI("vst4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23, r5, 13); + TESTINSN_VSTn_RI("vst4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3, r5, 13); + TESTINSN_VSTn_RI("vst4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20, r5, 13); + TESTINSN_VSTn_RI("vst4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31, r5, 13); + + printf("---- VMOVN ----\n"); + TESTINSN_bin("vmovn.i32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24); + TESTINSN_bin("vmovn.i16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24); + TESTINSN_bin("vmovn.i64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24); + TESTINSN_bin("vmovn.i32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0); + TESTINSN_bin("vmovn.i16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef); + TESTINSN_bin("vmovn.i64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24); + + printf("---- VQMOVN ----\n"); + TESTINSN_bin_q("vqmovn.u32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24); + TESTINSN_bin_q("vqmovn.u16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24); + TESTINSN_bin_q("vqmovn.u64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24); + TESTINSN_bin_q("vqmovn.u32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0); + TESTINSN_bin_q("vqmovn.u16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef); + TESTINSN_bin_q("vqmovn.u64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24); + TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24); + TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24); + TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24); + TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0); + TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef); + TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24); + TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xff); + TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i8, 0xff, d11, i16, 0xff); + TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i8, 0xff, d1, i8, 0xff); + + printf("---- VQMOVN ----\n"); + TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24); + TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24); + TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24); + TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0); + TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef); + TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24); + TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xff); + TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i8, 0xff, d11, i16, 0xff); + TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i8, 0xff, d1, i8, 0xff); + + printf("---- VABS ----\n"); + TESTINSN_un("vabs.s32 d0, d1", d0, d1, i32, 0x73); + TESTINSN_un("vabs.s16 d15, d4", d15, d4, i32, 0x73); + TESTINSN_un("vabs.s8 d8, d7", d8, d7, i32, 0x73); + TESTINSN_un("vabs.s32 d0, d1", d0, d1, i32, 0xfe); + TESTINSN_un("vabs.s16 d31, d4", d31, d4, i32, 0xef); + TESTINSN_un("vabs.s8 d8, d7", d8, d7, i32, 0xde); + TESTINSN_un("vabs.s32 d0, d1", d0, d1, i16, 0xfe0a); + TESTINSN_un("vabs.s16 d15, d4", d15, d4, i16, 0xef0b); + TESTINSN_un("vabs.s8 d8, d7", d8, d7, i16, 0xde0c); + + printf("---- VQABS ----\n"); + TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 0x73); + TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 1 << 31); + TESTINSN_un_q("vqabs.s16 d0, d1", d0, d1, i32, 1 << 31); + TESTINSN_un_q("vqabs.s8 d0, d1", d0, d1, i32, 1 << 31); + TESTINSN_un_q("vqabs.s16 d15, d4", d15, d4, i32, 0x73); + TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i32, 0x73); + TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 0xfe); + TESTINSN_un_q("vqabs.s16 d31, d4", d31, d4, i32, 0xef); + TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i32, 0xde); + TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i16, 0xfe0a); + TESTINSN_un_q("vqabs.s16 d15, d4", d15, d4, i16, 0xef0b); + TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i16, 0xde0c); + + printf("---- VADDHN ----\n"); + TESTINSN_bin("vaddhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72); + TESTINSN_bin("vaddhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vaddhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vaddhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vaddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172); + TESTINSN_bin("vaddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172); + TESTINSN_bin("vaddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172); + TESTINSN_bin("vaddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72); + TESTINSN_bin("vaddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vaddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vaddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + + printf("---- VRADDHN ----\n"); + TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72); + TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vraddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172); + TESTINSN_bin("vraddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172); + TESTINSN_bin("vraddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172); + TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72); + TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vraddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0102); + TESTINSN_bin("vraddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0102); + TESTINSN_bin("vraddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0102); + TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x02); + TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02); + TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02); + TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02); + + printf("---- VSUBHN ----\n"); + TESTINSN_bin("vsubhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72); + TESTINSN_bin("vsubhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vsubhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vsubhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172); + TESTINSN_bin("vsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172); + TESTINSN_bin("vsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172); + TESTINSN_bin("vsubhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72); + TESTINSN_bin("vsubhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vsubhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vsubhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + + printf("---- VRSUBHN ----\n"); + TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72); + TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72); + TESTINSN_bin("vrsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172); + TESTINSN_bin("vrsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172); + TESTINSN_bin("vrsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172); + TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72); + TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72); + TESTINSN_bin("vrsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef93, q2, i32, 0x0102); + TESTINSN_bin("vrsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef93, q2, i32, 0x0102); + TESTINSN_bin("vrsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef93, q8, i32, 0x0102); + TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i8, 0x93, q1, i32, 0x02); + TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02); + TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02); + TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02); + + printf("---- VCEQ #0 ----\n"); + TESTINSN_un("vceq.i32 d0, d1, #0", d0, d1, i32, 0x21); + TESTINSN_un("vceq.i16 d2, d1, #0", d2, d1, i32, 0x21); + TESTINSN_un("vceq.i8 d10, d11, #0", d10, d11, i32, 0x21); + TESTINSN_un("vceq.i32 d0, d1, #0", d0, d1, i32, 0x0); + TESTINSN_un("vceq.i16 d2, d1, #0", d2, d1, i32, 0x0); + TESTINSN_un("vceq.i8 d10, d31, #0", d10, d31, i32, 0x0); + + printf("---- VCGT #0 ----\n"); + TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i32, 0x21); + TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i32, 0x21); + TESTINSN_un("vcgt.s8 d10, d31, #0", d10, d31, i32, 0x21); + TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i32, 0x0); + TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i32, 0x0); + TESTINSN_un("vcgt.s8 d10, d11, #0", d10, d11, i32, 0x0); + TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i8, 0xef); + TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i8, 0xed); + TESTINSN_un("vcgt.s8 d10, d11, #0", d10, d11, i8, 0xae); + + printf("---- VCGE #0 ----\n"); + TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0x21); + TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0x21); + TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i32, 0x21); + TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0x0); + TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0x0); + TESTINSN_un("vcge.s8 d10, d31, #0", d10, d31, i32, 0x0); + TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i8, 0xef); + TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i8, 0xed); + TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i8, 0xae); + TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0xef); + TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0xed); + TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i32, 0xae); + + printf("---- VCLE #0 ----\n"); + TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i32, 0x21); + TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i32, 0x21); + TESTINSN_un("vcle.s8 d10, d11, #0", d10, d11, i32, 0x21); + TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i32, 0x0); + TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i32, 0x0); + TESTINSN_un("vcle.s8 d10, d31, #0", d10, d31, i32, 0x0); + TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i8, 0xef); + TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i8, 0xed); + TESTINSN_un("vcle.s8 d10, d11, #0", d10, d11, i8, 0xae); + + printf("---- VCLT #0 ----\n"); + TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0x21); + TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0x21); + TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0x21); + TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0x0); + TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0x0); + TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0x0); + TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i8, 0xef); + TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i8, 0xed); + TESTINSN_un("vclt.s8 d10, d31, #0", d10, d31, i8, 0xae); + TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0xef); + TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0xed); + TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0xae); + + printf("---- VCNT ----\n"); + TESTINSN_un("vcnt.8 d0, d1", d0, d1, i32, 0xac3d25eb); + TESTINSN_un("vcnt.8 d11, d14", d11, d14, i32, 0xac3d25eb); + TESTINSN_un("vcnt.8 d6, d2", d6, d2, i32, 0xad0eb); + + printf("---- VCLS ----\n"); + TESTINSN_un("vcls.s8 d0, d1", d0, d1, i32, 0x21); + TESTINSN_un("vcls.s8 d30, d31", d30, d31, i8, 0x82); + TESTINSN_un("vcls.s16 d0, d1", d0, d1, i32, 0x21); + TESTINSN_un("vcls.s16 d31, d30", d31, d30, i8, 0x82); + TESTINSN_un("vcls.s32 d6, d1", d6, d1, i32, 0x21); + TESTINSN_un("vcls.s32 d30, d5", d30, d5, i8, 0x82); + TESTINSN_un("vcls.s8 d2, d4", d2, d4, i8, 0xff); + TESTINSN_un("vcls.s16 d2, d4", d2, d4, i8, 0xff); + TESTINSN_un("vcls.s32 d2, d4", d2, d4, i8, 0xff); + TESTINSN_un("vcls.s8 d2, d4", d2, d4, i16, 0xffef); + TESTINSN_un("vcls.s16 d2, d4", d2, d4, i16, 0xffef); + TESTINSN_un("vcls.s32 d2, d4", d2, d4, i16, 0xffef); + TESTINSN_un("vcls.s8 d2, d4", d2, d4, i8, 0x00); + TESTINSN_un("vcls.s16 d2, d4", d2, d4, i8, 0x00); + TESTINSN_un("vcls.s32 d2, d4", d2, d4, i8, 0x00); + TESTINSN_un("vcls.s8 d2, d4", d2, d4, i16, 0x00ef); + TESTINSN_un("vcls.s16 d2, d4", d2, d4, i16, 0x00ef); + TESTINSN_un("vcls.s32 d2, d4", d2, d4, i16, 0x00ef); + + printf("---- VCLZ ----\n"); + TESTINSN_un("vclz.i8 d0, d1", d0, d1, i32, 0x21); + TESTINSN_un("vclz.i8 d30, d31", d30, d31, i8, 0x82); + TESTINSN_un("vclz.i16 d0, d1", d0, d1, i32, 0x21); + TESTINSN_un("vclz.i16 d31, d30", d31, d30, i8, 0x82); + TESTINSN_un("vclz.i32 d6, d1", d6, d1, i32, 0x21); + TESTINSN_un("vclz.i32 d30, d5", d30, d5, i8, 0x82); + TESTINSN_un("vclz.i8 d2, d4", d2, d4, i8, 0xff); + TESTINSN_un("vclz.i16 d2, d4", d2, d4, i8, 0xff); + TESTINSN_un("vclz.i32 d2, d4", d2, d4, i8, 0xff); + TESTINSN_un("vclz.i8 d2, d4", d2, d4, i16, 0xffef); + TESTINSN_un("vclz.i16 d2, d4", d2, d4, i16, 0xffef); + TESTINSN_un("vclz.i32 d2, d4", d2, d4, i16, 0xffef); + TESTINSN_un("vclz.i8 d2, d4", d2, d4, i8, 0x00); + TESTINSN_un("vclz.i16 d2, d4", d2, d4, i8, 0x00); + TESTINSN_un("vclz.i32 d2, d4", d2, d4, i8, 0x00); + TESTINSN_un("vclz.i8 d2, d4", d2, d4, i16, 0x00ef); + TESTINSN_un("vclz.i16 d2, d4", d2, d4, i16, 0x00ef); + TESTINSN_un("vclz.i32 d2, d4", d2, d4, i16, 0x00ef); + + printf("---- VSLI ----\n"); + TESTINSN_un("vsli.16 d0, d1, #1", d0, d1, i32, 7); + TESTINSN_un("vsli.16 d3, d4, #2", d3, d4, i32, -0x7c); + TESTINSN_un("vsli.32 d2, d5, #31", d2, d5, i32, -1); + TESTINSN_un("vsli.8 d6, d7, #7", d6, d7, i32, 0xffff); + TESTINSN_un("vsli.16 d8, d9, #12", d8, d9, i32, -10); + TESTINSN_un("vsli.32 d10, d11, #5", d10, d11, i32, 10234); + TESTINSN_un("vsli.8 d12, d13, #1", d12, d13, i32, -1); + TESTINSN_un("vsli.16 d14, d15, #11", d14, d15, i32, -1); + TESTINSN_un("vsli.32 d10, d11, #9", d10, d11, i32, 1000); + TESTINSN_un("vsli.8 d7, d13, #7", d7, d13, i32, -1); + TESTINSN_un("vsli.16 d8, d1, #1", d8, d1, i32, 0xabcf); + TESTINSN_un("vsli.32 d12, d3, #15", d12, d3, i32, -0x1b0); + TESTINSN_un("vsli.64 d0, d1, #42", d0, d1, i32, -1); + TESTINSN_un("vsli.64 d6, d7, #12", d6, d7, i32, 0xfac); + TESTINSN_un("vsli.64 d8, d4, #9", d8, d4, i32, 13560); + TESTINSN_un("vsli.64 d9, d12, #11", d9, d12, i32, 98710); + + printf("---- VPADD ----\n"); + TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vpadd.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vpadd.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120); + TESTINSN_bin("vpadd.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpadd.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpadd.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VPADDL ----\n"); + TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, 24); + TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpaddl.u16 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpaddl.u8 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpaddl.u8 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.u16 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.u32 d10, d11", d10, d11, i32, 24); + TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, 24); + TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpaddl.s16 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpaddl.s8 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpaddl.s8 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.s16 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpaddl.s32 d10, d11", d10, d11, i32, 24); + + printf("---- VPADAL ----\n"); + TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, 24); + TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpadal.u16 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpadal.u8 d0, d1", d0, d1, i8, 140); + TESTINSN_un("vpadal.u8 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.u16 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.u32 d10, d11", d10, d11, i32, 24); + TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, 24); + TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpadal.s16 d0, d1", d0, d1, i32, 140); + TESTINSN_un("vpadal.s8 d0, d1", d0, d1, i8, 140); + TESTINSN_un("vpadal.s8 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.s16 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, (1 << 31) + 1); + TESTINSN_un("vpadal.s32 d10, d11", d10, d11, i32, 24); + + printf("---- VZIP ----\n"); + TESTINSN_dual("vzip.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34); + TESTINSN_dual("vzip.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34); + TESTINSN_dual("vzip.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34); + TESTINSN_dual("vzip.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d); + TESTINSN_dual("vzip.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d); + TESTINSN_dual("vzip.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d); + + printf("---- VUZP ----\n"); + TESTINSN_dual("vuzp.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34); + TESTINSN_dual("vuzp.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34); + TESTINSN_dual("vuzp.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34); + TESTINSN_dual("vuzp.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d); + TESTINSN_dual("vuzp.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d); + TESTINSN_dual("vuzp.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d); + + printf("---- VTRN ----\n"); + TESTINSN_dual("vtrn.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34); + TESTINSN_dual("vtrn.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34); + TESTINSN_dual("vtrn.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34); + TESTINSN_dual("vtrn.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d); + TESTINSN_dual("vtrn.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d); + TESTINSN_dual("vtrn.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d); + + printf("---- VSWP ----\n"); + TESTINSN_dual("vswp d0, d1", d0, i8, 0x12, d1, i8, 0x34); + TESTINSN_dual("vswp d1, d0", d0, i8, 0x12, d1, i8, 0x34); + TESTINSN_dual("vswp d10, d11", d10, i8, 0x12, d11, i8, 0x34); + TESTINSN_dual("vswp d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d); + TESTINSN_dual("vswp d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d); + TESTINSN_dual("vswp d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d); + + printf("---- VSHRN ----\n"); + TESTINSN_un("vshrn.i16 d0, q1, #1", d0, q1, i32, -1); + TESTINSN_un("vshrn.i16 d3, q4, #2", d3, q4, i32, -0x7c); + TESTINSN_un("vshrn.i32 d2, q5, #10", d2, q5, i32, -1); + TESTINSN_un("vshrn.i32 d2, q5, #1", d2, q5, i32, 0x7fffffff); + TESTINSN_un("vshrn.i64 d6, q7, #7", d6, q7, i32, 0xffff); + TESTINSN_un("vshrn.i16 d8, q9, #8", d8, q9, i32, -10); + TESTINSN_un("vshrn.i32 d10, q11, #5", d10, q11, i32, 10234); + TESTINSN_un("vshrn.i64 d12, q13, #1", d12, q13, i32, -1); + TESTINSN_un("vshrn.i16 d14, q15, #6", d14, q15, i32, -1); + TESTINSN_un("vshrn.i32 d10, q11, #9", d10, q11, i32, 1000); + TESTINSN_un("vshrn.i64 d7, q13, #7", d7, q13, i32, -1); + TESTINSN_un("vshrn.i16 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un("vshrn.i32 d12, q3, #15", d12, q3, i32, -0x1b0); + TESTINSN_un("vshrn.i64 d0, q1, #22", d0, q1, i32, -1); + TESTINSN_un("vshrn.i64 d6, q7, #12", d6, q7, i32, 0xfac); + TESTINSN_un("vshrn.i64 d8, q4, #9", d8, q4, i32, 13560); + TESTINSN_un("vshrn.i64 d9, q12, #11", d9, q12, i32, 98710); + + printf("---- VDUP ----\n"); + TESTINSN_un("vdup.8 d12, d2[0]", d12, d2, i32, 0xabc4657); + TESTINSN_un("vdup.8 d0, d3[2]", d0, d3, i32, 0x7a1b3); + TESTINSN_un("vdup.8 d1, d0[7]", d1, d0, i32, 0x713aaa); + TESTINSN_un("vdup.8 d10, d4[3]", d10, d4, i32, 0xaa713); + TESTINSN_un("vdup.8 d4, d28[4]", d4, d28, i32, 0x7b1c3); + TESTINSN_un("vdup.16 d17, d19[1]", d17, d19, i32, 0x713ffff); + TESTINSN_un("vdup.16 d15, d31[2]", d15, d31, i32, 0x7f00fa); + TESTINSN_un("vdup.16 d6, d2[0]", d6, d2, i32, 0xffabcde); + TESTINSN_un("vdup.16 d8, d22[3]", d8, d22, i32, 0x713); + TESTINSN_un("vdup.16 d9, d2[0]", d9, d2, i32, 0x713); + TESTINSN_un("vdup.32 d10, d17[1]", d10, d17, i32, 0x713); + TESTINSN_un("vdup.32 d15, d11[0]", d15, d11, i32, 0x3); + TESTINSN_un("vdup.32 d30, d29[1]", d30, d29, i32, 0xf00000aa); + TESTINSN_un("vdup.32 d22, d0[1]", d22, d0, i32, 0xf); + TESTINSN_un("vdup.32 d13, d13[0]", d13, d13, i32, -1); + + printf("---- VQDMULH ----\n"); + TESTINSN_bin_q("vqdmulh.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqdmulh.s32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin_q("vqdmulh.s16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmulh.s32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 30); + + printf("---- VQDMULH (by scalar) ----\n"); + TESTINSN_bin_q("vqdmulh.s32 d0, d1, d6[0]", d0, d1, i32, 24, d6, i32, 120); + TESTINSN_bin_q("vqdmulh.s32 d6, d7, d1[1]", d6, d7, i32, 140, d1, i32, -120); + TESTINSN_bin_q("vqdmulh.s16 d9, d11, d7[0]", d9, d11, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[1]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[1]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[2]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqdmulh.s32 d10, d31, d15[0]", d10, d31, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 31, d7, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s16 d10, d14, d7[3]", d10, d14, i32, 1 << 31, q15, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 30, d15, i32, 1 << 31); + TESTINSN_bin_q("vqdmulh.s16 d31, d14, d7[1]", d31, d14, i32, 1 << 31, d7, i32, 1 << 30); + + printf("---- VSHRN ----\n"); + TESTINSN_un("vshrn.i64 d2, q2, #1", d2, q2, i32, 0xabc4657); + TESTINSN_un("vshrn.i64 d3, q3, #0", d3, q3, i32, 0x7a1b3); + TESTINSN_un("vshrn.i64 d1, q0, #3", d1, q0, i32, 0x713aaa); + TESTINSN_un("vshrn.i64 d0, q4, #5", d0, q4, i32, 0xaa713); + TESTINSN_un("vshrn.i64 d4, q8, #11", d4, q8, i32, 0x7b1c3); + TESTINSN_un("vshrn.i16 d7, q12, #6", d7, q12, i32, 0x713ffff); + TESTINSN_un("vshrn.i16 d15, q11, #2", d15, q11, i32, 0x7f00fa); + TESTINSN_un("vshrn.i16 d6, q2, #4", d6, q2, i32, 0xffabc); + TESTINSN_un("vshrn.i16 d8, q12, #3", d8, q12, i32, 0x713); + TESTINSN_un("vshrn.i16 d9, q2, #7", d9, q2, i32, 0x713); + TESTINSN_un("vshrn.i32 d10, q13, #2", d10, q13, i32, 0x713); + TESTINSN_un("vshrn.i32 d15, q11, #1", d15, q11, i32, 0x3); + TESTINSN_un("vshrn.i32 d10, q9, #5", d10, q9, i32, 0xf00000aa); + TESTINSN_un("vshrn.i32 d12, q0, #6", d12, q0, i32, 0xf); + TESTINSN_un("vshrn.i32 d13, q13, #2", d13, q13, i32, -1); + + printf("---- VQSHRN ----\n"); + TESTINSN_un_q("vqshrn.s16 d0, q1, #1", d0, q1, i32, -1); + TESTINSN_un_q("vqshrn.s16 d3, q4, #2", d3, q4, i32, -0x7c); + TESTINSN_un_q("vqshrn.s32 d2, q5, #10", d2, q5, i32, -1); + TESTINSN_un_q("vqshrn.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff); + TESTINSN_un_q("vqshrn.s16 d2, q5, #1", d2, q5, i16, 0x7fff); + TESTINSN_un_q("vqshrn.s64 d6, q7, #7", d6, q7, i32, 0xffff); + TESTINSN_un_q("vqshrn.s16 d8, q9, #8", d8, q9, i32, -10); + TESTINSN_un_q("vqshrn.s32 d10, q11, #5", d10, q11, i32, 10234); + TESTINSN_un_q("vqshrn.s64 d12, q13, #1", d12, q13, i32, -1); + TESTINSN_un_q("vqshrn.s16 d14, q15, #6", d14, q15, i32, -1); + TESTINSN_un_q("vqshrn.s32 d10, q11, #9", d10, q11, i32, 1000); + TESTINSN_un_q("vqshrn.s64 d7, q13, #7", d7, q13, i32, -1); + TESTINSN_un_q("vqshrn.s16 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqshrn.s32 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqshrn.s32 d12, q3, #15", d12, q3, i32, -0x1b0); + TESTINSN_un_q("vqshrn.s64 d0, q1, #22", d0, q1, i32, -1); + TESTINSN_un_q("vqshrn.s64 d6, q7, #12", d6, q7, i32, 0xfac); + TESTINSN_un_q("vqshrn.s64 d8, q4, #9", d8, q4, i32, 13560); + TESTINSN_un_q("vqshrn.s64 d9, q12, #11", d9, q12, i32, 98710); + TESTINSN_un_q("vqshrn.u16 d0, q1, #1", d0, q1, i32, -1); + TESTINSN_un_q("vqshrn.u16 d3, q4, #2", d3, q4, i32, -0x7c); + TESTINSN_un_q("vqshrn.u32 d2, q5, #10", d2, q5, i32, -1); + TESTINSN_un_q("vqshrn.u32 d2, q5, #1", d2, q5, i32, 0x7fffffff); + TESTINSN_un_q("vqshrn.u16 d2, q5, #1", d2, q5, i16, 0x7fff); + TESTINSN_un_q("vqshrn.u64 d6, q7, #7", d6, q7, i32, 0xffff); + TESTINSN_un_q("vqshrn.u16 d8, q9, #8", d8, q9, i32, -10); + TESTINSN_un_q("vqshrn.u32 d10, q11, #5", d10, q11, i32, 10234); + TESTINSN_un_q("vqshrn.u64 d12, q13, #1", d12, q13, i32, -1); + TESTINSN_un_q("vqshrn.u16 d14, q15, #6", d14, q15, i32, -1); + TESTINSN_un_q("vqshrn.u32 d10, q11, #9", d10, q11, i32, 1000); + TESTINSN_un_q("vqshrn.u64 d7, q13, #7", d7, q13, i32, -1); + TESTINSN_un_q("vqshrn.u16 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqshrn.u32 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqshrn.u32 d12, q3, #15", d12, q3, i32, -0x1b0); + TESTINSN_un_q("vqshrn.u64 d0, q1, #22", d0, q1, i32, -1); + TESTINSN_un_q("vqshrn.u64 d6, q7, #12", d6, q7, i32, 0xfac); + TESTINSN_un_q("vqshrn.u64 d8, q4, #9", d8, q4, i32, 13560); + TESTINSN_un_q("vqshrn.u64 d9, q12, #11", d9, q12, i32, 98710); + + printf("---- VQSHRUN ----\n"); + TESTINSN_un_q("vqshrun.s16 d0, q1, #1", d0, q1, i32, -1); + TESTINSN_un_q("vqshrun.s16 d3, q4, #2", d3, q4, i32, -0x7c); + TESTINSN_un_q("vqshrun.s32 d2, q5, #10", d2, q5, i32, -1); + TESTINSN_un_q("vqshrun.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff); + TESTINSN_un_q("vqshrun.s16 d2, q5, #1", d2, q5, i16, 0x7fff); + TESTINSN_un_q("vqshrun.s64 d6, q7, #7", d6, q7, i32, 0xffff); + TESTINSN_un_q("vqshrun.s16 d8, q9, #8", d8, q9, i32, -10); + TESTINSN_un_q("vqshrun.s32 d10, q11, #5", d10, q11, i32, 10234); + TESTINSN_un_q("vqshrun.s64 d12, q13, #1", d12, q13, i32, -1); + TESTINSN_un_q("vqshrun.s16 d14, q15, #6", d14, q15, i32, -1); + TESTINSN_un_q("vqshrun.s32 d10, q11, #9", d10, q11, i32, 1000); + TESTINSN_un_q("vqshrun.s64 d7, q13, #7", d7, q13, i32, -1); + TESTINSN_un_q("vqshrun.s16 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqshrun.s32 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqshrun.s32 d12, q3, #15", d12, q3, i32, -0x1b0); + TESTINSN_un_q("vqshrun.s64 d0, q1, #22", d0, q1, i32, -1); + TESTINSN_un_q("vqshrun.s64 d6, q7, #12", d6, q7, i32, 0xfac); + TESTINSN_un_q("vqshrun.s64 d8, q4, #9", d8, q4, i32, 13560); + TESTINSN_un_q("vqshrun.s64 d9, q12, #11", d9, q12, i32, 98710); + + printf("---- VQRSHRN ----\n"); + TESTINSN_un_q("vqrshrn.s16 d0, q1, #1", d0, q1, i32, -1); + TESTINSN_un_q("vqrshrn.s16 d3, q4, #2", d3, q4, i32, -0x7c); + TESTINSN_un_q("vqrshrn.s32 d2, q5, #10", d2, q5, i32, -1); + TESTINSN_un_q("vqrshrn.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff); + TESTINSN_un_q("vqrshrn.s16 d2, q5, #1", d2, q5, i16, 0x7fff); + TESTINSN_un_q("vqrshrn.s64 d6, q7, #7", d6, q7, i32, 0xffff); + TESTINSN_un_q("vqrshrn.s16 d8, q9, #8", d8, q9, i32, -10); + TESTINSN_un_q("vqrshrn.s32 d10, q11, #5", d10, q11, i32, 10234); + TESTINSN_un_q("vqrshrn.s64 d12, q13, #1", d12, q13, i32, -1); + TESTINSN_un_q("vqrshrn.s16 d14, q15, #6", d14, q15, i32, -1); + TESTINSN_un_q("vqrshrn.s32 d10, q11, #9", d10, q11, i32, 1000); + TESTINSN_un_q("vqrshrn.s64 d7, q13, #7", d7, q13, i32, -1); + TESTINSN_un_q("vqrshrn.s16 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqrshrn.s32 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqrshrn.s32 d12, q3, #15", d12, q3, i32, -0x1b0); + TESTINSN_un_q("vqrshrn.s64 d0, q1, #22", d0, q1, i32, -1); + TESTINSN_un_q("vqrshrn.s64 d6, q7, #12", d6, q7, i32, 0xfac); + TESTINSN_un_q("vqrshrn.s64 d8, q4, #9", d8, q4, i32, 13560); + TESTINSN_un_q("vqrshrn.s64 d9, q12, #11", d9, q12, i32, 98710); + TESTINSN_un_q("vqrshrn.u16 d0, q1, #1", d0, q1, i32, -1); + TESTINSN_un_q("vqrshrn.u16 d3, q4, #2", d3, q4, i32, -0x7c); + TESTINSN_un_q("vqrshrn.u32 d2, q5, #10", d2, q5, i32, -1); + TESTINSN_un_q("vqrshrn.u32 d2, q5, #1", d2, q5, i32, 0x7fffffff); + TESTINSN_un_q("vqrshrn.u16 d2, q5, #1", d2, q5, i16, 0x7fff); + TESTINSN_un_q("vqrshrn.u64 d6, q7, #7", d6, q7, i32, 0xffff); + TESTINSN_un_q("vqrshrn.u16 d8, q9, #8", d8, q9, i32, -10); + TESTINSN_un_q("vqrshrn.u32 d10, q11, #5", d10, q11, i32, 10234); + TESTINSN_un_q("vqrshrn.u64 d12, q13, #1", d12, q13, i32, -1); + TESTINSN_un_q("vqrshrn.u16 d14, q15, #6", d14, q15, i32, -1); + TESTINSN_un_q("vqrshrn.u32 d10, q11, #9", d10, q11, i32, 1000); + TESTINSN_un_q("vqrshrn.u64 d7, q13, #7", d7, q13, i32, -1); + TESTINSN_un_q("vqrshrn.u16 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqrshrn.u32 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqrshrn.u32 d12, q3, #15", d12, q3, i32, -0x1b0); + TESTINSN_un_q("vqrshrn.u64 d0, q1, #22", d0, q1, i32, -1); + TESTINSN_un_q("vqrshrn.u64 d6, q7, #12", d6, q7, i32, 0xfac); + TESTINSN_un_q("vqrshrn.u64 d8, q4, #9", d8, q4, i32, 13560); + TESTINSN_un_q("vqrshrn.u64 d9, q12, #11", d9, q12, i32, 98710); + + printf("---- VQRSHRUN ----\n"); + TESTINSN_un_q("vqrshrun.s16 d0, q1, #1", d0, q1, i32, -1); + TESTINSN_un_q("vqrshrun.s16 d3, q4, #2", d3, q4, i32, -0x7c); + TESTINSN_un_q("vqrshrun.s32 d2, q5, #10", d2, q5, i32, -1); + TESTINSN_un_q("vqrshrun.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff); + TESTINSN_un_q("vqrshrun.s16 d2, q5, #1", d2, q5, i16, 0x7fff); + TESTINSN_un_q("vqrshrun.s64 d6, q7, #7", d6, q7, i32, 0xffff); + TESTINSN_un_q("vqrshrun.s16 d8, q9, #8", d8, q9, i32, -10); + TESTINSN_un_q("vqrshrun.s32 d10, q11, #5", d10, q11, i32, 10234); + TESTINSN_un_q("vqrshrun.s64 d12, q13, #1", d12, q13, i32, -1); + TESTINSN_un_q("vqrshrun.s16 d14, q15, #6", d14, q15, i32, -1); + TESTINSN_un_q("vqrshrun.s32 d10, q11, #9", d10, q11, i32, 1000); + TESTINSN_un_q("vqrshrun.s64 d7, q13, #7", d7, q13, i32, -1); + TESTINSN_un_q("vqrshrun.s16 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqrshrun.s32 d8, q1, #1", d8, q1, i32, 0xabcf); + TESTINSN_un_q("vqrshrun.s32 d12, q3, #15", d12, q3, i32, -0x1b0); + TESTINSN_un_q("vqrshrun.s64 d0, q1, #22", d0, q1, i32, -1); + TESTINSN_un_q("vqrshrun.s64 d6, q7, #12", d6, q7, i32, 0xfac); + TESTINSN_un_q("vqrshrun.s64 d8, q4, #9", d8, q4, i32, 13560); + TESTINSN_un_q("vqrshrun.s64 d9, q12, #11", d9, q12, i32, 98710); + + printf("---- VRSHRN ----\n"); + TESTINSN_un("vrshrn.i64 d2, q2, #1", d2, q2, i32, 0xabc4657); + TESTINSN_un("vrshrn.i64 d3, q3, #0", d3, q3, i32, 0x7a1b3); + TESTINSN_un("vrshrn.i64 d1, q0, #3", d1, q0, i32, 0x713aaa); + TESTINSN_un("vrshrn.i64 d0, q4, #5", d0, q4, i32, 0xaa713); + TESTINSN_un("vrshrn.i64 d4, q8, #11", d4, q8, i32, 0x7b1c3); + TESTINSN_un("vrshrn.i16 d7, q12, #6", d7, q12, i32, 0x713ffff); + TESTINSN_un("vrshrn.i16 d15, q11, #2", d15, q11, i32, 0x7f00fa); + TESTINSN_un("vrshrn.i16 d6, q2, #4", d6, q2, i32, 0xffabc); + TESTINSN_un("vrshrn.i16 d8, q12, #3", d8, q12, i32, 0x713); + TESTINSN_un("vrshrn.i16 d9, q2, #7", d9, q2, i32, 0x713); + TESTINSN_un("vrshrn.i32 d10, q13, #2", d10, q13, i32, 0x713); + TESTINSN_un("vrshrn.i32 d15, q11, #1", d15, q11, i32, 0x3); + TESTINSN_un("vrshrn.i32 d10, q9, #5", d10, q9, i32, 0xf00000aa); + TESTINSN_un("vrshrn.i32 d12, q0, #6", d12, q0, i32, 0xf); + TESTINSN_un("vrshrn.i32 d13, q13, #2", d13, q13, i32, -1); + + printf("---- VSHL (immediate) ----\n"); + TESTINSN_un("vshl.i64 d0, d1, #1", d0, d1, i32, 24); + TESTINSN_un("vshl.i64 d5, d2, #1", d5, d2, i32, (1 << 30)); + TESTINSN_un("vshl.i64 d9, d12, #2", d9, d12, i32, (1 << 31) + 2); + TESTINSN_un("vshl.i64 d11, d2, #12", d11, d2, i32, -1); + TESTINSN_un("vshl.i64 d15, d12, #63", d15, d12, i32, 5); + TESTINSN_un("vshl.i64 d5, d12, #62", d5, d12, i32, (1 << 31) + 1); + TESTINSN_un("vshl.i32 d0, d1, #1", d0, d1, i32, 24); + TESTINSN_un("vshl.i32 d5, d2, #1", d5, d2, i32, (1 << 30)); + TESTINSN_un("vshl.i32 d9, d12, #2", d9, d12, i32, (1 << 31) + 2); + TESTINSN_un("vshl.i32 d11, d2, #12", d11, d2, i32, -1); + TESTINSN_un("vshl.i32 d15, d12, #20", d15, d12, i32, 5); + TESTINSN_un("vshl.i32 d5, d12, #30", d5, d12, i32, (1 << 31) + 1); + TESTINSN_un("vshl.i16 d0, d1, #1", d0, d1, i16, 24); + TESTINSN_un("vshl.i16 d5, d2, #1", d5, d2, i32, (1 << 30)); + TESTINSN_un("vshl.i16 d9, d12, #2", d9, d12, i32, (1 << 31) + 2); + TESTINSN_un("vshl.i16 d11, d2, #12", d11, d2, i16, -1); + TESTINSN_un("vshl.i16 d15, d12, #3", d15, d12, i16, 5); + TESTINSN_un("vshl.i16 d5, d12, #14", d5, d12, i32, (1 << 31) + 1); + TESTINSN_un("vshl.i8 d0, d1, #1", d0, d1, i8, 24); + TESTINSN_un("vshl.i8 d5, d2, #1", d5, d2, i32, (1 << 30)); + TESTINSN_un("vshl.i8 d9, d12, #2", d9, d12, i32, (1 << 31) + 2); + TESTINSN_un("vshl.i8 d11, d2, #7", d11, d2, i8, -1); + TESTINSN_un("vshl.i8 d15, d12, #3", d15, d12, i8, 5); + TESTINSN_un("vshl.i8 d5, d12, #6", d5, d12, i32, (1 << 31) + 1); + + printf("---- VNEG ----\n"); + TESTINSN_un("vneg.s32 d0, d1", d0, d1, i32, 0x73); + TESTINSN_un("vneg.s16 d15, d4", d15, d4, i32, 0x73); + TESTINSN_un("vneg.s8 d8, d7", d8, d7, i32, 0x73); + TESTINSN_un("vneg.s32 d0, d1", d0, d1, i32, 0xfe); + TESTINSN_un("vneg.s16 d31, d4", d31, d4, i32, 0xef); + TESTINSN_un("vneg.s8 d8, d7", d8, d7, i32, 0xde); + TESTINSN_un("vneg.s32 d0, d1", d0, d1, i16, 0xfe0a); + TESTINSN_un("vneg.s16 d15, d4", d15, d4, i16, 0xef0b); + TESTINSN_un("vneg.s8 d8, d7", d8, d7, i16, 0xde0c); + + printf("---- VQNEG ----\n"); + TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 0x73); + TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 1 << 31); + TESTINSN_un_q("vqneg.s16 d0, d1", d0, d1, i32, 1 << 31); + TESTINSN_un_q("vqneg.s8 d0, d1", d0, d1, i32, 1 << 31); + TESTINSN_un_q("vqneg.s16 d15, d4", d15, d4, i32, 0x73); + TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i32, 0x73); + TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 0xfe); + TESTINSN_un_q("vqneg.s16 d31, d4", d31, d4, i32, 0xef); + TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i32, 0xde); + TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i16, 0xfe0a); + TESTINSN_un_q("vqneg.s16 d15, d4", d15, d4, i16, 0xef0b); + TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i16, 0xde0c); + + printf("---- VREV ----\n"); + TESTINSN_un("vrev64.8 d0, d1", d0, d1, i32, 0xaabbccdd); + TESTINSN_un("vrev64.16 d10, d31", d10, d31, i32, 0xaabbccdd); + TESTINSN_un("vrev64.32 d1, d14", d1, d14, i32, 0xaabbccdd); + TESTINSN_un("vrev32.8 d0, d1", d0, d1, i32, 0xaabbccdd); + TESTINSN_un("vrev32.16 d30, d15", d30, d15, i32, 0xaabbccdd); + TESTINSN_un("vrev16.8 d0, d1", d0, d1, i32, 0xaabbccdd); + + printf("---- VTBL ----\n"); + TESTINSN_tbl_1("vtbl.8 d0, {d2}, d1", d0, d1, i8, 0, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbl.8 d0, {d31}, d1", d0, d1, i8, 0x07, d31, i32, 0x12345678); + TESTINSN_tbl_1("vtbl.8 d0, {d20}, d1", d0, d1, i8, 1, d20, i32, 0x12345678); + TESTINSN_tbl_1("vtbl.8 d0, {d2}, d31", d0, d31, i8, 2, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07030501, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbl.8 d31, {d2}, d1", d31, d1, i16, 0x0104, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07080501, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07ed05ee, d2, i32, 0x12345678); + TESTINSN_tbl_2("vtbl.8 d0, {d2-d3}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d0, {d1-d2}, d3", d0, d3, i8, 0xa, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d0, {d30-d31}, d1", d0, d1, i8, 0xf, d30, i32, 0x12345678, d31, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 14, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x070e0e01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0d130f01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_3("vtbl.8 d0, {d2-d4}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d0, {d1-d3}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d0, {d29-d31}, d1", d0, d1, i8, 0x17, d29, i32, 0x12345678, d30, i32, 0xa1a2a3a4, d31, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 17, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0a031504, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x170efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0d130f11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x070f1511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_4("vtbl.8 d0, {d2-d5}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d0, {d1-d4}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd, d4, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d0, {d28-d31}, d1", d0, d1, i8, 0x17, d28, i32, 0x12345678, d29, i32, 0xa1a2a3a4, d30, i32, 0xcacbcccd, d31, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1a, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1f, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1a0315ff, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x171efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1d130f1a, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x17101c11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + + printf("---- VTBX ----\n"); + TESTINSN_tbl_1("vtbx.8 d0, {d2}, d1", d0, d1, i8, 0, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbx.8 d0, {d31}, d1", d0, d1, i8, 0x07, d31, i32, 0x12345678); + TESTINSN_tbl_1("vtbx.8 d0, {d20}, d1", d0, d1, i8, 1, d20, i32, 0x12345678); + TESTINSN_tbl_1("vtbx.8 d0, {d2}, d31", d0, d31, i8, 2, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07030501, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbx.8 d31, {d2}, d1", d31, d1, i16, 0x0104, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07080501, d2, i32, 0x12345678); + TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07ed05ee, d2, i32, 0x12345678); + TESTINSN_tbl_2("vtbx.8 d0, {d2-d3}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d0, {d1-d2}, d3", d0, d3, i8, 0xa, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d0, {d30-d31}, d1", d0, d1, i8, 0xf, d30, i32, 0x12345678, d31, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 14, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x070e0e01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0d130f01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4); + TESTINSN_tbl_3("vtbx.8 d0, {d2-d4}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d0, {d1-d3}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d0, {d29-d31}, d1", d0, d1, i8, 0x17, d29, i32, 0x12345678, d30, i32, 0xa1a2a3a4, d31, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 17, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0a031504, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x170efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0d130f11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x070f1511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd); + TESTINSN_tbl_4("vtbx.8 d0, {d2-d5}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d0, {d1-d4}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd, d4, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d0, {d28-d31}, d1", d0, d1, i8, 0x17, d28, i32, 0x12345678, d29, i32, 0xa1a2a3a4, d30, i32, 0xcacbcccd, d31, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1a, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1f, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1a0315ff, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x171efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1d130f1a, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x17101c11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb); + + printf("---- VPMAX (integer) ----\n"); + TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121); + TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120); + TESTINSN_bin("vpmax.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120); + TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120); + TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, 0x01202120, d2, i32, 120); + TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmax.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VPMIN (integer) ----\n"); + TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121); + TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121); + TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120); + TESTINSN_bin("vpmin.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120); + TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); + TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120); + TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120); + TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140); + TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120); + TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, 0x01202120, d2, i32, 120); + TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); + TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); + TESTINSN_bin("vpmin.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120); + + printf("---- VQRDMULH ----\n"); + TESTINSN_bin_q("vqrdmulh.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120); + TESTINSN_bin_q("vqrdmulh.s32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120); + TESTINSN_bin_q("vqrdmulh.s16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120); + TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqrdmulh.s32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqrdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, (1 << 31) + 1); + TESTINSN_bin_q("vqrdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 30, d31, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 30); + + printf("---- VQRDMULH (by scalar) ----\n"); + TESTINSN_bin_q("vqrdmulh.s32 d0, d1, d6[0]", d0, d1, i32, 24, d6, i32, 120); + TESTINSN_bin_q("vqrdmulh.s32 d6, d7, d1[1]", d6, d7, i32, 140, d1, i32, -120); + TESTINSN_bin_q("vqrdmulh.s16 d9, d11, d7[0]", d9, d11, i32, 0x140, d7, i32, 0x120); + TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[1]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[1]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31), d9, i32, 12); + TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[2]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); + TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); + TESTINSN_bin_q("vqrdmulh.s32 d10, d31, d15[0]", d10, d31, i32, 24, d15, i32, 120); + TESTINSN_bin_q("vqrdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 31, d7, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s16 d10, d14, d7[3]", d10, d14, i32, 1 << 31, q15, i32, (1 << 31) + 1); + TESTINSN_bin_q("vqrdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 30, d15, i32, 1 << 31); + TESTINSN_bin_q("vqrdmulh.s16 d31, d14, d7[1]", d31, d14, i32, 1 << 31, d7, i32, 1 << 30); + + printf("---- VADD (fp) ----\n"); + TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vadd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vadd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vadd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vadd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vadd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vadd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VSUB (fp) ----\n"); + TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); + TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089)); + TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vsub.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vsub.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vsub.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vsub.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vsub.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vsub.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VMUL (fp) ----\n"); + TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); + TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089)); + TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vmul.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vmul.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vmul.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vmul.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vmul.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vmul.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VMLA (fp) ----\n"); + TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); + TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089)); + TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin_f("vmla.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin_f("vmla.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin_f("vmla.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin_f("vmla.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin_f("vmla.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin_f("vmla.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VMLA (fp by scalar) ----\n"); + TESTINSN_bin_f("vmla.f32 d0, d1, d4[0]", d0, d1, i32, f2u(24), d4, i32, f2u(120)); + TESTINSN_bin_f("vmla.f32 d31, d8, d7[1]", d31, d8, i32, f2u(140), d7, i32, f2u(-120)); + TESTINSN_bin_f("vmla.f32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin_f("vmla.f32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin_f("vmla.f32 d17, d8, d1[1]", d17, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + TESTINSN_bin_f("vmla.f32 d7, d8, d1[0]", d7, d8, i32, f2u(1e22), d1, i32, f2u(1e-19)); + TESTINSN_bin_f("vmla.f32 d7, d24, d1[0]", d7, d24, i32, f2u(1e12), d1, i32, f2u(1e11)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VMLS (fp) ----\n"); + TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); + TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089)); + TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin_f("vmls.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin_f("vmls.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin_f("vmls.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin_f("vmls.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin_f("vmls.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin_f("vmls.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VMLS (fp by scalar) ----\n"); + TESTINSN_bin_f("vmls.f32 d0, d1, d4[0]", d0, d1, i32, f2u(24), d4, i32, f2u(120)); + TESTINSN_bin_f("vmls.f32 d31, d8, d7[1]", d31, d8, i32, f2u(140), d7, i32, f2u(-120)); + TESTINSN_bin_f("vmls.f32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2); + TESTINSN_bin_f("vmls.f32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12); + TESTINSN_bin_f("vmls.f32 d17, d8, d1[1]", d17, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2); + TESTINSN_bin_f("vmls.f32 d7, d8, d1[0]", d7, d8, i32, f2u(1e22), d1, i32, f2u(1e-19)); + TESTINSN_bin_f("vmls.f32 d7, d24, d1[0]", d7, d24, i32, f2u(1e12), d1, i32, f2u(1e11)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VABD (fp) ----\n"); + TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); + TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089)); + TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vabd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vabd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vabd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vabd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vabd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vabd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vabd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vabd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + + printf("---- VPADD (fp) ----\n"); + TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); + TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089)); + TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vpadd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vpadd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vpadd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vpadd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vpadd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vpadd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VCVT (integer <-> fp) ----\n"); + TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vcvt.u32.f32 d10, d11", d10, d11, i32, f2u(3e22)); + TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vcvt.u32.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vcvt.u32.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vcvt.s32.f32 d20, d21", d20, d21, i32, f2u(3e22)); + TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vcvt.s32.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vcvt.s32.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vcvt.f32.u32 d0, d1", d0, d1, i32, 7); + TESTINSN_un("vcvt.f32.u32 d10, d11", d10, d11, i32, 1 << 31); + TESTINSN_un("vcvt.f32.u32 d0, d1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vcvt.f32.u32 d24, d26", d24, d26, i32, (1U << 31) - 1); + TESTINSN_un("vcvt.f32.u32 d0, d14", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, 7); + TESTINSN_un("vcvt.f32.s32 d30, d31", d30, d31, i32, 1 << 31); + TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, (1U << 31) - 1); + TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(-INFINITY)); + TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VCVT (fixed <-> fp) ----\n"); + TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vcvt.u32.f32 d10, d11, #1", d10, d11, i32, f2u(3e22)); + TESTINSN_un("vcvt.u32.f32 d15, d4, #32", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vcvt.u32.f32 d15, d4, #7", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vcvt.u32.f32 d15, d4, #4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vcvt.u32.f32 d12, d8, #3", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vcvt.u32.f32 d12, d8, #3", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vcvt.s32.f32 d0, d1, #5", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vcvt.s32.f32 d20, d21, #1", d20, d21, i32, f2u(3e22)); + TESTINSN_un("vcvt.s32.f32 d15, d4, #8", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vcvt.s32.f32 d15, d4, #2", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vcvt.s32.f32 d15, d4, #1", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vcvt.s32.f32 d12, d8, #2", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vcvt.s32.f32 d12, d8, #2", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vcvt.f32.u32 d0, d1, #5", d0, d1, i32, 7); + TESTINSN_un("vcvt.f32.u32 d10, d11, #9", d10, d11, i32, 1 << 31); + TESTINSN_un("vcvt.f32.u32 d0, d1, #4", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vcvt.f32.u32 d24, d26, #6", d24, d26, i32, (1U << 31) - 1); + TESTINSN_un("vcvt.f32.u32 d0, d14, #5", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vcvt.f32.s32 d0, d1, #12", d0, d1, i32, 7); + TESTINSN_un("vcvt.f32.s32 d30, d31, #8", d30, d31, i32, 1 << 31); + TESTINSN_un("vcvt.f32.s32 d0, d1, #1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vcvt.f32.s32 d0, d1, #6", d0, d1, i32, (1U << 31) - 1); + TESTINSN_un("vcvt.f32.s32 d0, d14, #2", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(-INFINITY)); + TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VMAX (fp) ----\n"); + TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vmax.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vmax.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vmax.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vmax.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vmax.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vmax.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VMIN (fp) ----\n"); + TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vmin.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vmin.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vmin.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vmin.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vmin.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vmin.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VPMAX (fp) ----\n"); + TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vpmax.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vpmax.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vpmax.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vpmax.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vpmax.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vpmax.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VPMIN (fp) ----\n"); + TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vpmin.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vpmin.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vpmin.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vpmin.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vpmin.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vpmin.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VRECPE ----\n"); + TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(-653.2)); + TESTINSN_un("vrecpe.u32 d10, d11", d10, d11, i32, f2u(3e22)); + TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vrecpe.u32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vrecpe.u32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vrecpe.u32 d10, d11", d10, d11, i32, f2u(3e22)); + TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vrecpe.f32 d15, d4", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vrecpe.f32 d15, d4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vrecpe.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vrecpe.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, 7); + TESTINSN_un("vrecpe.f32 d10, d11", d10, d11, i32, 1 << 31); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) - 1); + TESTINSN_un("vrecpe.f32 d0, d14", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, 7); + TESTINSN_un("vrecpe.f32 d10, d11", d10, d11, i32, 1 << 31); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) - 1); + TESTINSN_un("vrecpe.f32 d0, d14", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VRECPS ----\n"); + TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); + TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089)); + TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vrecps.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vrecps.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vrecps.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vrecps.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vrecps.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vrecps.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VABS (fp) ----\n"); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, f2u(3e22)); + TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, f2u(3e22)); + TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, 7); + TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, 1 << 31); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) - 1); + TESTINSN_un("vabs.f32 d0, d14", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, 7); + TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, 1 << 31); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) - 1); + TESTINSN_un("vabs.f32 d0, d14", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VCGT (fp) ----\n"); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5)); + TESTINSN_bin("vcgt.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52)); + TESTINSN_bin("vcgt.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45)); + TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vcgt.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vcgt.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vcgt.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vcgt.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vcgt.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vcgt.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vcgt.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vcgt.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vcgt.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VCGE (fp) ----\n"); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5)); + TESTINSN_bin("vcge.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52)); + TESTINSN_bin("vcge.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45)); + TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vcge.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vcge.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vcge.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vcge.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vcge.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vcge.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vcge.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vcge.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vcge.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VACGT (fp) ----\n"); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5)); + TESTINSN_bin("vacgt.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52)); + TESTINSN_bin("vacgt.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45)); + TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vacgt.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vacgt.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vacgt.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vacgt.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vacgt.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vacgt.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vacgt.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vacgt.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vacgt.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VACGE (fp) ----\n"); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5)); + TESTINSN_bin("vacge.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52)); + TESTINSN_bin("vacge.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45)); + TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vacge.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vacge.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vacge.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vacge.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vacge.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vacge.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vacge.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vacge.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vacge.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VCEQ (fp) ----\n"); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5)); + TESTINSN_bin("vceq.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52)); + TESTINSN_bin("vceq.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45)); + TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vceq.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004)); + TESTINSN_bin("vceq.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2)); + TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vceq.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vceq.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vceq.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vceq.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vceq.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vceq.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vceq.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VCEQ (fp) #0 ----\n"); + TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, 0x01000000); + TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, 0x1); + TESTINSN_un("vceq.f32 d2, d1, #0", d2, d1, i32, 1 << 31); + TESTINSN_un("vceq.f32 d2, d1, #0", d2, d1, i32, f2u(23.04)); + TESTINSN_un("vceq.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04)); + TESTINSN_un("vceq.f32 d30, d15, #0", d30, d15, i32, 0x0); + TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VCGT (fp) #0 ----\n"); + TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, 0x01000000); + TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, 0x1); + TESTINSN_un("vcgt.f32 d2, d1, #0", d2, d1, i32, 1 << 31); + TESTINSN_un("vcgt.f32 d2, d1, #0", d2, d1, i32, f2u(23.04)); + TESTINSN_un("vcgt.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04)); + TESTINSN_un("vcgt.f32 d30, d15, #0", d30, d15, i32, 0x0); + TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VCLT (fp) #0 ----\n"); + TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, 0x01000000); + TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, 0x1); + TESTINSN_un("vclt.f32 d2, d1, #0", d2, d1, i32, 1 << 31); + TESTINSN_un("vclt.f32 d2, d1, #0", d2, d1, i32, f2u(23.04)); + TESTINSN_un("vclt.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04)); + TESTINSN_un("vclt.f32 d30, d15, #0", d30, d15, i32, 0x0); + TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VCGE (fp) #0 ----\n"); + TESTINSN_un("vcge.f32 d0, d1, #0", d0, d1, i32, 0x01000000); + TESTINSN_un("vcge.f32 d0, d1, #0", d0, d1, i32, 0x1); + TESTINSN_un("vcge.f32 d2, d1, #0", d2, d1, i32, 1 << 31); + TESTINSN_un("vcge.f32 d2, d1, #0", d2, d1, i32, f2u(23.04)); + TESTINSN_un("vcge.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04)); + TESTINSN_un("vcge.f32 d30, d15, #0", d30, d15, i32, 0x0); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VCLE (fp) #0 ----\n"); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, 0x01000000); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, 0x1); + TESTINSN_un("vcle.f32 d2, d1, #0", d2, d1, i32, 1 << 31); + TESTINSN_un("vcle.f32 d2, d1, #0", d2, d1, i32, f2u(23.04)); + TESTINSN_un("vcle.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04)); + TESTINSN_un("vcle.f32 d30, d15, #0", d30, d15, i32, 0x0); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VNEG (fp) ----\n"); + TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, 0x01000000); + TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, 0x1); + TESTINSN_un("vneg.f32 d2, d1", d2, d1, i32, 1 << 31); + TESTINSN_un("vneg.f32 d2, d1", d2, d1, i32, f2u(23.04)); + TESTINSN_un("vneg.f32 d2, d31", d2, d31, i32, f2u(-23.04)); + TESTINSN_un("vneg.f32 d30, d15", d30, d15, i32, 0x0); + TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(-INFINITY)); + + printf("---- VRSQRTS ----\n"); + TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687)); + TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346)); + TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476)); + TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065)); + TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76)); + TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); + TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089)); + TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065)); + TESTINSN_bin("vrsqrts.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009)); + TESTINSN_bin("vrsqrts.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107)); + TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6)); + TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109)); + TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); + TESTINSN_bin("vrsqrts.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47)); + TESTINSN_bin("vrsqrts.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676)); + TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876)); + TESTINSN_bin("vrsqrts.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245)); + TESTINSN_bin("vrsqrts.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY)); + TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY)); + + printf("---- VRSQRTE (fp) ----\n"); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, f2u(3e22)); + TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(3.2)); + TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, f2u(3e22)); + TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(3e9)); + TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-0.5)); + TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-7.1)); + TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, 7); + TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, 1 << 31); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) - 1); + TESTINSN_un("vrsqrte.f32 d0, d14", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, 7); + TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, 1 << 31); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) + 1); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) - 1); + TESTINSN_un("vrsqrte.f32 d0, d14", d0, d14, i32, 0x30a0bcef); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(NAN)); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(0.0)); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(INFINITY)); + TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(-INFINITY)); + + return 0; +} diff --git a/none/tests/arm/neon64.stderr.exp b/none/tests/arm/neon64.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/arm/neon64.stdout.exp b/none/tests/arm/neon64.stdout.exp new file mode 100644 index 0000000..a42cf78 --- /dev/null +++ b/none/tests/arm/neon64.stdout.exp @@ -0,0 +1,6388 @@ +----- VMOV (immediate) ----- +vmov.i32 d0, #0x7 :: Qd 0x00000007 0x00000007 +vmov.i32 d0, #0x7 :: Qd 0x00000007 0x00000007 +vmov.i16 d1, #0x7 :: Qd 0x00070007 0x00070007 +vmov.i16 d1, #0x7 :: Qd 0x00070007 0x00070007 +vmov.i8 d2, #0x7 :: Qd 0x07070707 0x07070707 +vmov.i8 d2, #0x7 :: Qd 0x07070707 0x07070707 +vmov.i32 d5, #0x700 :: Qd 0x00000700 0x00000700 +vmov.i32 d5, #0x700 :: Qd 0x00000700 0x00000700 +vmov.i16 d7, #0x700 :: Qd 0x07000700 0x07000700 +vmov.i16 d7, #0x700 :: Qd 0x07000700 0x07000700 +vmov.i32 d10, #0x70000 :: Qd 0x00070000 0x00070000 +vmov.i32 d10, #0x70000 :: Qd 0x00070000 0x00070000 +vmov.i32 d12, #0x7000000 :: Qd 0x07000000 0x07000000 +vmov.i32 d12, #0x7000000 :: Qd 0x07000000 0x07000000 +vmov.i32 d13, #0x7FF :: Qd 0x000007ff 0x000007ff +vmov.i32 d13, #0x7FF :: Qd 0x000007ff 0x000007ff +vmov.i32 d14, #0x7FFFF :: Qd 0x0007ffff 0x0007ffff +vmov.i32 d14, #0x7FFFF :: Qd 0x0007ffff 0x0007ffff +vmov.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00 +vmov.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00 +----- VMVN (immediate) ----- +vmvn.i32 d0, #0x7 :: Qd 0xfffffff8 0xfffffff8 +vmvn.i32 d0, #0x7 :: Qd 0xfffffff8 0xfffffff8 +vmvn.i16 d1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8 +vmvn.i16 d1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8 +vmvn.i8 d2, #0x7 :: Qd 0xf8f8f8f8 0xf8f8f8f8 +vmvn.i8 d2, #0x7 :: Qd 0xf8f8f8f8 0xf8f8f8f8 +vmvn.i32 d5, #0x700 :: Qd 0xfffff8ff 0xfffff8ff +vmvn.i32 d5, #0x700 :: Qd 0xfffff8ff 0xfffff8ff +vmvn.i16 d7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff +vmvn.i16 d7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff +vmvn.i32 d10, #0x70000 :: Qd 0xfff8ffff 0xfff8ffff +vmvn.i32 d10, #0x70000 :: Qd 0xfff8ffff 0xfff8ffff +vmvn.i32 d13, #0x7000000 :: Qd 0xf8ffffff 0xf8ffffff +vmvn.i32 d13, #0x7000000 :: Qd 0xf8ffffff 0xf8ffffff +vmvn.i32 d11, #0x7FF :: Qd 0xfffff800 0xfffff800 +vmvn.i32 d11, #0x7FF :: Qd 0xfffff800 0xfffff800 +vmvn.i32 d14, #0x7FFFF :: Qd 0xfff80000 0xfff80000 +vmvn.i32 d14, #0x7FFFF :: Qd 0xfff80000 0xfff80000 +vmvn.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff +vmvn.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff +----- VORR (immediate) ----- +vorr.i32 d0, #0x7 :: Qd 0x55555557 0x55555557 +vorr.i32 d0, #0x7 :: Qd 0x131b1a1f 0x121f1e1f +vorr.i16 d2, #0x7 :: Qd 0x55575557 0x55575557 +vorr.i16 d2, #0x7 :: Qd 0x131f1a1f 0x121f1e1f +vorr.i32 d8, #0x700 :: Qd 0x55555755 0x55555755 +vorr.i32 d8, #0x700 :: Qd 0x131b1f1b 0x121f1f1f +vorr.i16 d6, #0x700 :: Qd 0x57555755 0x57555755 +vorr.i16 d6, #0x700 :: Qd 0x171b1f1b 0x171f1f1f +vorr.i32 d14, #0x70000 :: Qd 0x55575555 0x55575555 +vorr.i32 d14, #0x70000 :: Qd 0x131f1a1b 0x121f1e1f +vorr.i32 d15, #0x7000000 :: Qd 0x57555555 0x57555555 +vorr.i32 d15, #0x7000000 :: Qd 0x171b1a1b 0x171f1e1f +----- VBIC (immediate) ----- +vbic.i32 d0, #0x7 :: Qd 0x55555550 0x55555550 +vbic.i32 d0, #0x7 :: Qd 0x131b1a18 0x121f1e18 +vbic.i16 d3, #0x7 :: Qd 0x55505550 0x55505550 +vbic.i16 d3, #0x7 :: Qd 0x13181a18 0x12181e18 +vbic.i32 d5, #0x700 :: Qd 0x55555055 0x55555055 +vbic.i32 d5, #0x700 :: Qd 0x131b181b 0x121f181f +vbic.i16 d8, #0x700 :: Qd 0x50555055 0x50555055 +vbic.i16 d8, #0x700 :: Qd 0x101b181b 0x101f181f +vbic.i32 d10, #0x70000 :: Qd 0x55505555 0x55505555 +vbic.i32 d10, #0x70000 :: Qd 0x13181a1b 0x12181e1f +vbic.i32 d15, #0x7000000 :: Qd 0x50555555 0x50555555 +vbic.i32 d15, #0x7000000 :: Qd 0x101b1a1b 0x101f1e1f +---- VMVN (register) ---- +vmvn d0, d1 :: Qd 0xffffffe7 0xffffffe7 Qm (i32)0x00000018 +vmvn d0, d1 :: Qd 0xeae2e6e2 0xebe3e0e3 Qm (i32)0x00000018 +vmvn d10, d15 :: Qd 0xffffffe7 0xffffffe7 Qm (i32)0x00000018 +vmvn d10, d15 :: Qd 0xeae2e6e2 0xebe3e0e3 Qm (i32)0x00000018 +vmvn d0, d14 :: Qd 0xffffffe7 0xffffffe7 Qm (i32)0x00000018 +vmvn d0, d14 :: Qd 0xeae2e6e2 0xebe3e0e3 Qm (i32)0x00000018 +---- VMOV (register) ---- +vmov d0, d1 :: Qd 0x00000018 0x00000018 Qm (i32)0x00000018 +vmov d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000018 +vmov d10, d15 :: Qd 0x00000018 0x00000018 Qm (i32)0x00000018 +vmov d10, d15 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000018 +vmov d0, d14 :: Qd 0x00000018 0x00000018 Qm (i32)0x00000018 +vmov d0, d14 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000018 +---- VDUP (ARM core register) (tested indirectly) ---- +vmov d0, d1 :: Qd 0x07070707 0x07070707 Qm (i8)0x00000007 +vmov d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i8)0x00000007 +vmov d10, d11 :: Qd 0x00070007 0x00070007 Qm (i16)0x00000007 +vmov d10, d11 :: Qd 0x151d191d 0x141c1f1c Qm (i16)0x00000007 +vmov d0, d15 :: Qd 0x00000007 0x00000007 Qm (i32)0x00000007 +vmov d0, d15 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000007 +---- VADD ---- +vadd.i32 d0, d1, d2 :: Qd 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 +vadd.i32 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 +vadd.i64 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i64 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i32 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i32 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i16 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i16 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i8 d0, d1, d2 :: Qd 0x00000004 0x00000004 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i8 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i8 d0, d1, d2 :: Qd 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i8 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i16 d0, d1, d2 :: Qd 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i16 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i32 d0, d1, d2 :: Qd 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i32 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i64 d0, d1, d2 :: Qd 0x00000004 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i64 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 +vadd.i32 d10, d11, d12 :: Qd 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 +vadd.i32 d10, d11, d12 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 +vadd.i64 d13, d14, d15 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 +vadd.i64 d13, d14, d15 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 +---- VSUB ---- +vsub.i32 d0, d1, d2 :: Qd 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vsub.i32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 +vsub.i64 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i64 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i32 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i16 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i16 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i8 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i8 d0, d1, d2 :: Qd 0x131b1aa3 0x121f1ea7 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i8 d0, d1, d2 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i16 d0, d1, d2 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i32 d0, d1, d2 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i64 d0, d1, d2 :: Qd 0xfffffffe 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i64 d0, d1, d2 :: Qd 0x931b1a18 0x921f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vsub.i32 d10, d11, d12 :: Qd 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vsub.i32 d10, d11, d12 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 +vsub.i64 d13, d14, d15 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vsub.i64 d13, d14, d15 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 +---- VAND ---- +vand d0, d1, d2 :: Qd 0x00240024 0x00240024 Qm (i8)0x00000024 Qn (i16)0x00000077 +vand d0, d1, d2 :: Qd 0x00130013 0x00170017 Qm (i8)0x00000024 Qn (i16)0x00000077 +vand d4, d6, d5 :: Qd 0x00570057 0x00570057 Qm (i8)0x000000ff Qn (i16)0x00000057 +vand d4, d6, d5 :: Qd 0x00130013 0x00170017 Qm (i8)0x000000ff Qn (i16)0x00000057 +vand d10, d11, d12 :: Qd 0xecececec 0xecececec Qm (i8)0x000000fe Qn (i8)0x000000ed +vand d10, d11, d12 :: Qd 0x01090809 0x000d0c0d Qm (i8)0x000000fe Qn (i8)0x000000ed +vand d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vand d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +---- VBIC ---- +vbic d0, d1, d2 :: Qd 0x24002400 0x24002400 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbic d0, d1, d2 :: Qd 0x13081a08 0x12081e08 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbic d4, d6, d5 :: Qd 0xffa8ffa8 0xffa8ffa8 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbic d4, d6, d5 :: Qd 0x13081a08 0x12081e08 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbic d10, d11, d12 :: Qd 0x12121212 0x12121212 Qm (i8)0x000000fe Qn (i8)0x000000ed +vbic d10, d11, d12 :: Qd 0x12121212 0x12121212 Qm (i8)0x000000fe Qn (i8)0x000000ed +vbic d15, d15, d15 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff +vbic d15, d15, d15 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff +---- VORR ---- +vorr d0, d1, d2 :: Qd 0x24772477 0x24772477 Qm (i8)0x00000024 Qn (i16)0x00000073 +vorr d0, d1, d2 :: Qd 0x137b1a7b 0x127f1e7f Qm (i8)0x00000024 Qn (i16)0x00000073 +vorr d7, d3, d0 :: Qd 0x24ff24ff 0x24ff24ff Qm (i8)0x00000024 Qn (i16)0x000000ff +vorr d7, d3, d0 :: Qd 0x13ff1aff 0x12ff1eff Qm (i8)0x00000024 Qn (i16)0x000000ff +vorr d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vorr d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vorr d2, d3, d15 :: Qd 0x0000003f 0x0000003f Qm (i32)0x00000024 Qn (i32)0x0000001f +vorr d2, d3, d15 :: Qd 0x131b1a1f 0x121f1e1f Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VORN ---- +vorn d0, d1, d2 :: Qd 0xffacffac 0xffacffac Qm (i8)0x00000024 Qn (i16)0x00000073 +vorn d0, d1, d2 :: Qd 0xff9fff9f 0xff9fff9f Qm (i8)0x00000024 Qn (i16)0x00000073 +vorn d7, d3, d0 :: Qd 0xff24ff24 0xff24ff24 Qm (i8)0x00000024 Qn (i16)0x000000ff +vorn d7, d3, d0 :: Qd 0xff1bff1b 0xff1fff1f Qm (i8)0x00000024 Qn (i16)0x000000ff +vorn d4, d4, d4 :: Qd 0xffffffff 0xffffffff Qm (i16)0x000000ff Qn (i16)0x000000ff +vorn d4, d4, d4 :: Qd 0xffffffff 0xffffffff Qm (i16)0x000000ff Qn (i16)0x000000ff +vorn d2, d3, d15 :: Qd 0xffffffe4 0xffffffe4 Qm (i32)0x00000024 Qn (i32)0x0000001f +vorn d2, d3, d15 :: Qd 0xfffffffb 0xffffffff Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VEOR ---- +veor d0, d1, d2 :: Qd 0x24532453 0x24532453 Qm (i8)0x00000024 Qn (i16)0x00000077 +veor d0, d1, d2 :: Qd 0x136c1a6c 0x12681e68 Qm (i8)0x00000024 Qn (i16)0x00000077 +veor d4, d6, d5 :: Qd 0xffa8ffa8 0xffa8ffa8 Qm (i8)0x000000ff Qn (i16)0x00000057 +veor d4, d6, d5 :: Qd 0x134c1a4c 0x12481e48 Qm (i8)0x000000ff Qn (i16)0x00000057 +veor d10, d11, d12 :: Qd 0x13131313 0x13131313 Qm (i8)0x000000fe Qn (i8)0x000000ed +veor d10, d11, d12 :: Qd 0xfef6f7f6 0xfff2f3f2 Qm (i8)0x000000fe Qn (i8)0x000000ed +veor d15, d15, d15 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff +veor d15, d15, d15 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff +veor d0, d1, d2 :: Qd 0x24572457 0x24572457 Qm (i8)0x00000024 Qn (i16)0x00000073 +veor d0, d1, d2 :: Qd 0x13681a68 0x126c1e6c Qm (i8)0x00000024 Qn (i16)0x00000073 +veor d7, d3, d0 :: Qd 0x24db24db 0x24db24db Qm (i8)0x00000024 Qn (i16)0x000000ff +veor d7, d3, d0 :: Qd 0x13e41ae4 0x12e01ee0 Qm (i8)0x00000024 Qn (i16)0x000000ff +veor d4, d4, d4 :: Qd 0x00000000 0x00000000 Qm (i16)0x000000ff Qn (i16)0x000000ff +veor d4, d4, d4 :: Qd 0x00000000 0x00000000 Qm (i16)0x000000ff Qn (i16)0x000000ff +veor d2, d3, d15 :: Qd 0x0000003b 0x0000003b Qm (i32)0x00000024 Qn (i32)0x0000001f +veor d2, d3, d15 :: Qd 0x131b1a04 0x121f1e00 Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VBSL ---- +vbsl d0, d1, d2 :: Qd 0x04260426 0x04260426 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbsl d0, d1, d2 :: Qd 0x11331033 0x10371437 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbsl d4, d6, d5 :: Qd 0x55575557 0x55575557 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbsl d4, d6, d5 :: Qd 0x11131013 0x10171417 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbsl d10, d11, d12 :: Qd 0xfcfcfcfc 0xfcfcfcfc Qm (i8)0x000000fe Qn (i8)0x000000ed +vbsl d10, d11, d12 :: Qd 0xb9b9b8b9 0xb8bdbcbd Qm (i8)0x000000fe Qn (i8)0x000000ed +vbsl d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbsl d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbsl d0, d1, d2 :: Qd 0x04260426 0x04260426 Qm (i8)0x00000024 Qn (i16)0x00000073 +vbsl d0, d1, d2 :: Qd 0x11331033 0x10371437 Qm (i8)0x00000024 Qn (i16)0x00000073 +vbsl d7, d3, d0 :: Qd 0x04ae04ae 0x04ae04ae Qm (i8)0x00000024 Qn (i16)0x000000ff +vbsl d7, d3, d0 :: Qd 0x11bb10bb 0x10bf14bf Qm (i8)0x00000024 Qn (i16)0x000000ff +vbsl d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbsl d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbsl d2, d3, d15 :: Qd 0x0000000e 0x0000000e Qm (i32)0x00000024 Qn (i32)0x0000001f +vbsl d2, d3, d15 :: Qd 0x1111101b 0x1015141f Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VBIT ---- +vbit d0, d1, d2 :: Qd 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbit d0, d1, d2 :: Qd 0x55135513 0x55175517 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbit d4, d6, d5 :: Qd 0x55575557 0x55575557 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbit d4, d6, d5 :: Qd 0x55135513 0x55175517 Qm (i8)0x000000ff Qn (i16)0x00000057 +vbit d10, d11, d12 :: Qd 0xfcfcfcfc 0xfcfcfcfc Qm (i8)0x000000fe Qn (i8)0x000000ed +vbit d10, d11, d12 :: Qd 0x11191819 0x101d1c1d Qm (i8)0x000000fe Qn (i8)0x000000ed +vbit d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbit d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbit d0, d1, d2 :: Qd 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x00000073 +vbit d0, d1, d2 :: Qd 0x55175517 0x55175517 Qm (i8)0x00000024 Qn (i16)0x00000073 +vbit d7, d3, d0 :: Qd 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x000000ff +vbit d7, d3, d0 :: Qd 0x551b551b 0x551f551f Qm (i8)0x00000024 Qn (i16)0x000000ff +vbit d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbit d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbit d2, d3, d15 :: Qd 0x55555544 0x55555544 Qm (i32)0x00000024 Qn (i32)0x0000001f +vbit d2, d3, d15 :: Qd 0x5555555b 0x5555555f Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VBIF ---- +vbif d0, d1, d2 :: Qd 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x00000077 +vbif d0, d1, d2 :: Qd 0x135d1a5d 0x125d1e5d Qm (i8)0x00000024 Qn (i16)0x00000077 +vbif d4, d6, d5 :: Qd 0xfffdfffd 0xfffdfffd Qm (i8)0x000000ff Qn (i16)0x00000057 +vbif d4, d6, d5 :: Qd 0x135d1a5d 0x125d1e5d Qm (i8)0x000000ff Qn (i16)0x00000057 +vbif d10, d11, d12 :: Qd 0x57575757 0x57575757 Qm (i8)0x000000fe Qn (i8)0x000000ed +vbif d10, d11, d12 :: Qd 0x57575757 0x57575757 Qm (i8)0x000000fe Qn (i8)0x000000ed +vbif d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbif d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff +vbif d0, d1, d2 :: Qd 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x00000073 +vbif d0, d1, d2 :: Qd 0x13591a59 0x125d1e5d Qm (i8)0x00000024 Qn (i16)0x00000073 +vbif d7, d3, d0 :: Qd 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x000000ff +vbif d7, d3, d0 :: Qd 0x13551a55 0x12551e55 Qm (i8)0x00000024 Qn (i16)0x000000ff +vbif d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbif d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff +vbif d2, d3, d15 :: Qd 0x00000035 0x00000035 Qm (i32)0x00000024 Qn (i32)0x0000001f +vbif d2, d3, d15 :: Qd 0x131b1a15 0x121f1e15 Qm (i32)0x00000024 Qn (i32)0x0000001f +---- VEXT ---- +vext.8 d0, d1, d2, #0 :: Qd 0x77777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d1, d2, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d1, d2, #1 :: Qd 0xff777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d1, d2, #1 :: Qd 0xff131b1a 0x1b121f1e Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d1, d2, #7 :: Qd 0xffffffff 0xffffff77 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d1, d2, #7 :: Qd 0xffffffff 0xffffff13 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d1, d2, #6 :: Qd 0xffffffff 0xffff7777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d1, d2, #6 :: Qd 0xffffffff 0xffff131b Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d10, d11, d12, #4 :: Qd 0xffffffff 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d10, d11, d12, #4 :: Qd 0xffffffff 0x131b1a1b Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d5, d15, #5 :: Qd 0xffffffff 0xff777777 Qm (i8)0x00000077 Qn (i8)0x000000ff +vext.8 d0, d5, d15, #5 :: Qd 0xffffffff 0xff131b1a Qm (i8)0x00000077 Qn (i8)0x000000ff +---- VHADD ---- +vhadd.s32 d0, d1, d2 :: Qd 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.s32 d0, d1, d2 :: Qd 0x098d8d49 0x090f8f4b Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.s32 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s32 d0, d1, d2 :: Qd 0x098d8d49 0x090f8f4b Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s16 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s16 d0, d1, d2 :: Qd 0x098d0d49 0x090f0f4b Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s8 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s8 d0, d1, d2 :: Qd 0x090d0d49 0x090f0f4b Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.s8 d0, d1, d2 :: Qd 0x03030303 0x03030303 Qm (i8)0x0000008d Qn (i8)0x00000079 +vhadd.s8 d0, d1, d2 :: Qd 0x464a494a 0x454c4b4c Qm (i8)0x0000008d Qn (i8)0x00000079 +vhadd.s8 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s8 d0, d1, d2 :: Qd 0xc90d0d0e 0xc90f0f10 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s16 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s16 d0, d1, d2 :: Qd 0xc98d0d0e 0xc90f0f10 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s32 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s32 d0, d1, d2 :: Qd 0xc98d8d0e 0xc90f8f10 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.s32 d10, d11, d12 :: Qd 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.s32 d10, d11, d12 :: Qd 0x098d8d49 0x090f8f4b Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.u32 d0, d1, d2 :: Qd 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.u32 d0, d1, d2 :: Qd 0x098d8d49 0x090f8f4b Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.u32 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u32 d0, d1, d2 :: Qd 0x098d8d49 0x090f8f4b Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u16 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u16 d0, d1, d2 :: Qd 0x098d0d49 0x090f0f4b Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u8 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u8 d0, d1, d2 :: Qd 0x090d0d49 0x090f0f4b Qm (i32)0x0000008c Qn (i32)0x00000078 +vhadd.u8 d0, d1, d2 :: Qd 0x83838383 0x83838383 Qm (i8)0x0000008d Qn (i8)0x00000079 +vhadd.u8 d0, d1, d2 :: Qd 0x464a494a 0x454c4b4c Qm (i8)0x0000008d Qn (i8)0x00000079 +vhadd.u8 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u8 d0, d1, d2 :: Qd 0x490d0d0e 0x490f0f10 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u16 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u16 d0, d1, d2 :: Qd 0x498d0d0e 0x490f0f10 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u32 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u32 d0, d1, d2 :: Qd 0x498d8d0e 0x490f8f10 Qm (i32)0x80000001 Qn (i32)0x80000002 +vhadd.u32 d10, d11, d12 :: Qd 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhadd.u32 d10, d11, d12 :: Qd 0x098d8d49 0x090f8f4b Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VHSUB ---- +vhsub.s32 d0, d1, d2 :: Qd 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.s32 d0, d1, d2 :: Qd 0x098d8cd1 0x090f8ed3 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.s32 d0, d1, d2 :: Qd 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s32 d0, d1, d2 :: Qd 0x098d8cd1 0x090f8ed3 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s16 d0, d1, d2 :: Qd 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s16 d0, d1, d2 :: Qd 0x098d0cd1 0x090f0ed3 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s8 d0, d1, d2 :: Qd 0x0000008a 0x0000008a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s8 d0, d1, d2 :: Qd 0x090d0dd1 0x090f0fd3 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.s8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s8 d0, d1, d2 :: Qd 0x490d0d0c 0x490f0f0e Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s16 d0, d1, d2 :: Qd 0x498d0d0c 0x490f0f0e Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s32 d0, d1, d2 :: Qd 0x498d8d0c 0x490f8f0e Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.s32 d10, d11, d12 :: Qd 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.s32 d10, d11, d12 :: Qd 0x098d8cd1 0x090f8ed3 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.u32 d0, d1, d2 :: Qd 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.u32 d0, d1, d2 :: Qd 0x098d8cd1 0x090f8ed3 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.u32 d0, d1, d2 :: Qd 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u32 d0, d1, d2 :: Qd 0x098d8cd1 0x090f8ed3 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u16 d0, d1, d2 :: Qd 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u16 d0, d1, d2 :: Qd 0x098d0cd1 0x090f0ed3 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u8 d0, d1, d2 :: Qd 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u8 d0, d1, d2 :: Qd 0x090d0dd1 0x090f0fd3 Qm (i32)0x0000008c Qn (i32)0x00000078 +vhsub.u8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u8 d0, d1, d2 :: Qd 0xc90d0d0c 0xc90f0f0e Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u16 d0, d1, d2 :: Qd 0xc98d0d0c 0xc90f0f0e Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u32 d0, d1, d2 :: Qd 0xc98d8d0c 0xc90f8f0e Qm (i32)0x80000001 Qn (i32)0x80000002 +vhsub.u32 d10, d11, d12 :: Qd 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078 +vhsub.u32 d10, d11, d12 :: Qd 0x098d8cd1 0x090f8ed3 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VQADD ---- +vqadd.s32 d0, d1, d2 :: Qd 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s16 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s16 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s8 d0, d1, d2 :: Qd 0x00000004 0x00000004 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s8 d0, d1, d2 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqadd.s8 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.s8 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s16 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.s16 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s32 d0, d1, d2 :: Qd 0x80000000 0x80000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.s32 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.s32 d10, d11, d12 :: Qd 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.s32 d10, d11, d12 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 d0, d1, d2 :: Qd 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u16 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u16 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqadd.u8 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u8 d0, d1, d2 :: Qd 0xff000003 0xff000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.u8 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u16 d0, d1, d2 :: Qd 0xffff0003 0xffff0003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.u16 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqadd.u32 d0, d1, d2 :: Qd 0x931b1a1d 0x921f1e21 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqadd.u32 d10, d11, d12 :: Qd 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqadd.u32 d10, d11, d12 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +---- VQSUB ---- +vqsub.s32 d0, d1, d2 :: Qd 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s16 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s16 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s8 d0, d1, d2 :: Qd 0x00000080 0x00000080 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqsub.s8 d0, d1, d2 :: Qd 0x131b1aa3 0x121f1ea7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqsub.s8 d0, d1, d2 :: Qd 0x7f1b1a19 0x7f1f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqsub.s16 d0, d1, d2 :: Qd 0x7fff1a19 0x7fff1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqsub.s32 d0, d1, d2 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.s32 d10, d11, d12 :: Qd 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.s32 d10, d11, d12 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqsub.u32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u16 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u16 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u8 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000 +vqsub.u8 d0, d1, d2 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000 +vqsub.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u8 d0, d1, d2 :: Qd 0x001b1a19 0x001f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u16 d0, d1, d2 :: Qd 0x00001a19 0x00001e1d Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000 +vqsub.u32 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqsub.u32 d10, d11, d12 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +---- VRHADD ---- +vrhadd.s32 d0, d1, d2 :: Qd 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000078 +vrhadd.s32 d0, d1, d2 :: Qd 0x098d8d4a 0x090f8f4c Qm (i32)0x00000019 Qn (i32)0x00000078 +vrhadd.s32 d0, d1, d2 :: Qd 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000079 +vrhadd.s32 d0, d1, d2 :: Qd 0x098d8d4a 0x090f8f4c Qm (i32)0x00000019 Qn (i32)0x00000079 +vrhadd.s32 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s32 d0, d1, d2 :: Qd 0x098d8d4a 0x090f8f4c Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s16 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s16 d0, d1, d2 :: Qd 0x098e0d4a 0x09100f4c Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s8 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s8 d0, d1, d2 :: Qd 0x0a0e0d4a 0x09100f4c Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s8 d5, d7, d5 :: Qd 0xca0e0d0f 0xc9100f11 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s16 d0, d1, d2 :: Qd 0xc98e0d0f 0xc9100f11 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s32 d0, d1, d2 :: Qd 0xc98d8d0f 0xc90f8f11 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s8 d5, d7, d5 :: Qd 0xca0e0d0f 0xc9100f11 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s16 d0, d1, d2 :: Qd 0xc98e0d0f 0xc9100f11 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s32 d0, d1, d2 :: Qd 0xc98d8d0f 0xc90f8f11 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.s8 d5, d7, d5 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s8 d5, d7, d5 :: Qd 0xca0e0d0f 0xc9100f11 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s16 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s16 d0, d1, d2 :: Qd 0xc98e0d0f 0xc9100f11 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s32 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s32 d0, d1, d2 :: Qd 0xc98d8d0f 0xc90f8f11 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.s32 d10, d11, d12 :: Qd 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vrhadd.s32 d10, d11, d12 :: Qd 0x098d8d4a 0x090f8f4c Qm (i32)0x00000018 Qn (i32)0x00000078 +vrhadd.u32 d0, d1, d2 :: Qd 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000078 +vrhadd.u32 d0, d1, d2 :: Qd 0x098d8d4a 0x090f8f4c Qm (i32)0x00000019 Qn (i32)0x00000078 +vrhadd.u32 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u32 d0, d1, d2 :: Qd 0x098d8d4a 0x090f8f4c Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u16 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u16 d0, d1, d2 :: Qd 0x098e0d4a 0x09100f4c Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u8 d0, d1, d2 :: Qd 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u8 d0, d1, d2 :: Qd 0x0a0e0d4a 0x09100f4c Qm (i32)0x0000008c Qn (i32)0x00000078 +vrhadd.u8 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u8 d0, d1, d2 :: Qd 0x4a0e0d0f 0x49100f11 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u16 d0, d1, d2 :: Qd 0x498e0d0f 0x49100f11 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u32 d0, d1, d2 :: Qd 0x498d8d0f 0x490f8f11 Qm (i32)0x80000001 Qn (i32)0x80000002 +vrhadd.u8 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u8 d0, d1, d2 :: Qd 0x4a0e0d0f 0x49100f11 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u16 d0, d1, d2 :: Qd 0x498e0d0f 0x49100f11 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u32 d0, d1, d2 :: Qd 0x498d8d0f 0x490f8f11 Qm (i32)0x80000001 Qn (i32)0x80000003 +vrhadd.u8 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u8 d0, d1, d2 :: Qd 0x4a0e0d0f 0x49100f11 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u16 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u16 d0, d1, d2 :: Qd 0x498e0d0f 0x49100f11 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u32 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u32 d0, d1, d2 :: Qd 0x498d8d0f 0x490f8f11 Qm (i32)0x80000004 Qn (i32)0x80000002 +vrhadd.u32 d10, d11, d12 :: Qd 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078 +vrhadd.u32 d10, d11, d12 :: Qd 0x098d8d4a 0x090f8f4c Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VCGT ---- +vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000019 Qn (i32)0x00000078 +vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000079 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000019 Qn (i32)0x00000079 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcgt.s8 d5, d7, d5 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.s8 d5, d7, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.s8 d5, d7, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.s32 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vcgt.s32 d10, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078 +vcgt.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000019 Qn (i32)0x00000078 +vcgt.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078 +vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x0000008c +vcgt.u8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u8 d0, d1, d2 :: Qd 0x00ffffff 0x00ffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000003 Qn (i32)0x80000002 +vcgt.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u8 d0, d1, d2 :: Qd 0x00ffffff 0x00ffffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcgt.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u8 d0, d1, d2 :: Qd 0x00ffffff 0x00ffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcgt.u32 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vcgt.u32 d10, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VCGE ---- +vcge.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000019 Qn (i32)0x00000078 +vcge.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000079 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000019 Qn (i32)0x00000079 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s16 d0, d1, d2 :: Qd 0xffff0000 0xffff0000 Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c +vcge.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.s8 d5, d7, d5 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s16 d0, d1, d2 :: Qd 0xffff0000 0xffff0000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.s32 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vcge.s32 d10, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +vcge.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078 +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000019 Qn (i32)0x00000078 +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078 +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x00000078 Qn (i32)0x00000078 +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x0000008c +vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u8 d0, d1, d2 :: Qd 0x00ffffff 0x00ffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000003 Qn (i32)0x80000002 +vcge.u8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u8 d0, d1, d2 :: Qd 0x00ffffff 0x00ffffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u16 d0, d1, d2 :: Qd 0xffff0000 0xffff0000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u8 d0, d1, d2 :: Qd 0x00ffffff 0x00ffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002 +vcge.u32 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vcge.u32 d10, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VSHL (register) ---- +vshl.s8 d0, d1, d2 :: Qd 0x00000030 0x00000030 Qm (i32)0x00000018 Qn (i32)0x00000001 +vshl.s8 d0, d1, d2 :: Qd 0x131b1a36 0x121f1e3e Qm (i32)0x00000018 Qn (i32)0x00000001 +vshl.s8 d8, d1, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000008 +vshl.s8 d8, d1, d12 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0x00000018 Qn (i32)0x00000008 +vshl.s8 d10, d31, d7 :: Qd 0x00000080 0x00000080 Qm (i32)0x00000018 Qn (i32)0x00000004 +vshl.s8 d10, d31, d7 :: Qd 0x131b1ab0 0x121f1ef0 Qm (i32)0x00000018 Qn (i32)0x00000004 +vshl.s16 d3, d8, d11 :: Qd 0x00000038 0x00000038 Qm (i32)0x0000000e Qn (i32)0x00000002 +vshl.s16 d3, d8, d11 :: Qd 0x131b686c 0x121f787c Qm (i32)0x0000000e Qn (i32)0x00000002 +vshl.s16 d5, d12, d14 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000001 +vshl.s16 d5, d12, d14 :: Qd 0x131b3436 0x121f3c3e Qm (i32)0x40000000 Qn (i32)0x00000001 +vshl.s16 d15, d2, d1 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x0000000b +vshl.s16 d15, d2, d1 :: Qd 0x131bd800 0x121ff800 Qm (i32)0x40000000 Qn (i32)0x0000000b +vshl.s32 d9, d12, d19 :: Qd 0x00000008 0x00000008 Qm (i32)0x80000002 Qn (i32)0x00000002 +vshl.s32 d9, d12, d19 :: Qd 0x4c6c686c 0x487c787c Qm (i32)0x80000002 Qn (i32)0x00000002 +vshl.s32 d11, d22, d0 :: Qd 0xfffff000 0xfffff000 Qm (i32)0xffffffff Qn (i32)0x0000000c +vshl.s32 d11, d22, d0 :: Qd 0xb1a1b000 0xf1e1f000 Qm (i32)0xffffffff Qn (i32)0x0000000c +vshl.s32 d5, d2, d3 :: Qd 0x00000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x00000015 +vshl.s32 d5, d2, d3 :: Qd 0x43600000 0xc3e00000 Qm (i32)0x40000000 Qn (i32)0x00000015 +vshl.s64 d15, d12, d4 :: Qd 0x00500000 0x00500000 Qm (i32)0x00000005 Qn (i32)0x00000014 +vshl.s64 d15, d12, d4 :: Qd 0xa1b121f1 0xe1f00000 Qm (i32)0x00000005 Qn (i32)0x00000014 +vshl.s64 d8, d2, d4 :: Qd 0x000000f0 0x000000f0 Qm (i32)0x0000000f Qn (i32)0x00000004 +vshl.s64 d8, d2, d4 :: Qd 0x31b1a1b1 0x21f1e1f0 Qm (i32)0x0000000f Qn (i32)0x00000004 +vshl.s64 d5, d12, d4 :: Qd 0x60000000 0x40000000 Qm (i32)0x80000001 Qn (i32)0x0000001e +vshl.s64 d5, d12, d4 :: Qd 0xc487c787 0xc0000000 Qm (i32)0x80000001 Qn (i32)0x0000001e +vshl.s64 d15, d2, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffabcd59 Qn (i32)0xabcdefab +vshl.s64 d15, d2, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xffabcd59 Qn (i32)0xabcdefab +vshl.s64 d8, d2, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000000f Qn (i32)0x00400bb5 +vshl.s64 d8, d2, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000000f Qn (i32)0x00400bb5 +vshl.s64 d5, d12, d4 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000001 Qn (i32)0x030abcff +vshl.s64 d5, d12, d4 :: Qd 0x098d8d0d 0x890f8f0f Qm (i32)0x80000001 Qn (i32)0x030abcff +vshl.u8 d0, d1, d2 :: Qd 0x00000030 0x00000030 Qm (i32)0x00000018 Qn (i32)0x00000001 +vshl.u8 d0, d1, d2 :: Qd 0x131b1a36 0x121f1e3e Qm (i32)0x00000018 Qn (i32)0x00000001 +vshl.u8 d8, d1, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000008 +vshl.u8 d8, d1, d12 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0x00000018 Qn (i32)0x00000008 +vshl.u8 d10, d11, d7 :: Qd 0x00000080 0x00000080 Qm (i32)0x00000018 Qn (i32)0x00000004 +vshl.u8 d10, d11, d7 :: Qd 0x131b1ab0 0x121f1ef0 Qm (i32)0x00000018 Qn (i32)0x00000004 +vshl.u16 d3, d8, d11 :: Qd 0x00000038 0x00000038 Qm (i32)0x0000000e Qn (i32)0x00000002 +vshl.u16 d3, d8, d11 :: Qd 0x131b686c 0x121f787c Qm (i32)0x0000000e Qn (i32)0x00000002 +vshl.u16 d5, d12, d14 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000001 +vshl.u16 d5, d12, d14 :: Qd 0x131b3436 0x121f3c3e Qm (i32)0x40000000 Qn (i32)0x00000001 +vshl.u16 d15, d2, d1 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x0000000b +vshl.u16 d15, d2, d1 :: Qd 0x131bd800 0x121ff800 Qm (i32)0x40000000 Qn (i32)0x0000000b +vshl.u32 d9, d12, d15 :: Qd 0x00000008 0x00000008 Qm (i32)0x80000002 Qn (i32)0x00000002 +vshl.u32 d9, d12, d15 :: Qd 0x4c6c686c 0x487c787c Qm (i32)0x80000002 Qn (i32)0x00000002 +vshl.u32 d11, d2, d0 :: Qd 0xfffff000 0xfffff000 Qm (i32)0xffffffff Qn (i32)0x0000000c +vshl.u32 d11, d2, d0 :: Qd 0xb1a1b000 0xf1e1f000 Qm (i32)0xffffffff Qn (i32)0x0000000c +vshl.u32 d5, d2, d3 :: Qd 0x00000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x00000015 +vshl.u32 d5, d2, d3 :: Qd 0x43600000 0xc3e00000 Qm (i32)0x40000000 Qn (i32)0x00000015 +vshl.u64 d15, d12, d4 :: Qd 0x00500000 0x00500000 Qm (i32)0x00000005 Qn (i32)0x00000014 +vshl.u64 d15, d12, d4 :: Qd 0xa1b121f1 0xe1f00000 Qm (i32)0x00000005 Qn (i32)0x00000014 +vshl.u64 d8, d2, d4 :: Qd 0x000000f0 0x000000f0 Qm (i32)0x0000000f Qn (i32)0x00000004 +vshl.u64 d8, d2, d4 :: Qd 0x31b1a1b1 0x21f1e1f0 Qm (i32)0x0000000f Qn (i32)0x00000004 +vshl.u64 d5, d12, d4 :: Qd 0x60000000 0x40000000 Qm (i32)0x80000001 Qn (i32)0x0000001e +vshl.u64 d5, d12, d4 :: Qd 0xc487c787 0xc0000000 Qm (i32)0x80000001 Qn (i32)0x0000001e +vshl.u64 d15, d2, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xffabcd59 Qn (i32)0xabcdefab +vshl.u64 d15, d2, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xffabcd59 Qn (i32)0xabcdefab +vshl.u64 d8, d2, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000000f Qn (i32)0x00400bb5 +vshl.u64 d8, d2, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000000f Qn (i32)0x00400bb5 +vshl.u64 d5, d12, d4 :: Qd 0x40000000 0xc0000000 Qm (i32)0x80000001 Qn (i32)0x030abcff +vshl.u64 d5, d12, d4 :: Qd 0x098d8d0d 0x890f8f0f Qm (i32)0x80000001 Qn (i32)0x030abcff +---- VQSHL (register) ---- +vqshl.s64 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 d0, d1, d2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 d3, d4, d5 :: Qd 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 d3, d4, d5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.s64 d3, d4, d5 :: Qd 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s64 d3, d4, d5 :: Qd 0x02636343 0x6243e3c3 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s64 d0, d1, d2 :: Qd 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000 +vqshl.s64 d0, d1, d2 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqshl.s64 d13, d14, d31 :: Qd 0xffffffff 0xfffffbff Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.s64 d13, d14, d31 :: Qd 0x00000004 0xc6c686c4 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.s32 d2, d8, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.s32 d2, d8, d4 :: Qd 0x0131b1a1 0x0121f1e1 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.s32 d12, d11, d13 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.s32 d12, d11, d13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.s32 d0, d1, d2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.s32 d9, d30, d11 :: Qd 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s32 d9, d30, d11 :: Qd 0x098d8d0d 0x090f8f0f Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s32 d13, d3, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqshl.s32 d13, d3, d5 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 08000000 +vqshl.s16 d11, d10, d2 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 d11, d10, d2 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 d3, d14, d7 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s16 d3, d14, d7 :: Qd 0x098d0343 0x090f03c3 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.s16 d0, d11, d2 :: Qd 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s16 d0, d11, d2 :: Qd 0x098d0d0d 0x090f0f0f Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.s16 d1, d2, d3 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 d1, d2, d3 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.s16 d3, d4, d5 :: Qd 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.s16 d3, d4, d5 :: Qd 0x098d0000 0x090f0000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.s16 d0, d15, d2 :: Qd 0x00007fff 0x00007fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s16 d0, d15, d2 :: Qd 0x131b7fff 0x121f7fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s8 d2, d7, d11 :: Qd 0xffffff80 0xffffff80 Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.s8 d2, d7, d11 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.s8 d13, d1, d2 :: Qd 0xffffff80 0xffffff80 Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s8 d13, d1, d2 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.s8 d3, d7, d5 :: Qd 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqshl.s8 d3, d7, d5 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 08000000 +vqshl.s8 d10, d11, d12 :: Qd 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000 +vqshl.s8 d10, d11, d12 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqshl.s8 d6, d7, d8 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.s8 d6, d7, d8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.s8 d10, d11, d12 :: Qd 0x0000007f 0x0000007f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqshl.s8 d10, d11, d12 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqshl.u64 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.u64 d0, d1, d2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.u64 d3, d4, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 08000000 +vqshl.u64 d3, d4, d5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqshl.u64 d3, d4, d5 :: Qd 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u64 d3, d4, d5 :: Qd 0x02636343 0x6243e3c3 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u64 d0, d1, d2 :: Qd 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000 +vqshl.u64 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqshl.u64 d13, d14, d15 :: Qd 0x0000003f 0xfffffbff Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.u64 d13, d14, d15 :: Qd 0x00000004 0xc6c686c4 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqshl.u32 d2, d8, d4 :: Qd 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.u32 d2, d8, d4 :: Qd 0x0131b1a1 0x0121f1e1 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqshl.u32 d12, d31, d13 :: Qd 0x007fffff 0x007fffff Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.u32 d12, d31, d13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqshl.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.u32 d0, d1, d2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqshl.u32 d9, d10, d11 :: Qd 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u32 d9, d10, d11 :: Qd 0x098d8d0d 0x090f8f0f Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u32 d13, d3, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u32 d13, d3, d5 :: Qd 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u16 d11, d10, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 d11, d10, d2 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 d3, d14, d7 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u16 d3, d14, d7 :: Qd 0x098d0343 0x090f03c3 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqshl.u16 d0, d11, d2 :: Qd 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u16 d0, d11, d2 :: Qd 0x098d0d0d 0x090f0f0f Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqshl.u16 d1, d2, d3 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 d1, d2, d3 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqshl.u16 d3, d4, d5 :: Qd 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.u16 d3, d4, d5 :: Qd 0x098d0000 0x090f0000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqshl.u16 d0, d15, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u16 d0, d15, d2 :: Qd 0x131bffff 0x121fffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.u8 d2, d7, d11 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqshl.u8 d13, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u8 d13, d1, d2 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqshl.u8 d3, d7, d5 :: Qd 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u8 d3, d7, d5 :: Qd 0x131b1ad8 0x121f1ef8 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqshl.u8 d10, d11, d12 :: Qd 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000 +vqshl.u8 d10, d11, d12 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqshl.u8 d6, d7, d8 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.u8 d6, d7, d8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqshl.u8 d10, d11, d12 :: Qd 0x000000ff 0x000000ff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqshl.u8 d10, d11, d12 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +---- VQSHL / VQSHLU (immediate) ---- +vqshl.s64 d0, d1, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshl.s64 d0, d1, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshl.s64 d31, d30, #1 :: Qd 0xffffff03 0xffffff02 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s64 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s64 d5, d4, #0 :: Qd 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s64 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s64 d5, d4, #63 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #63 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #60 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #60 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #59 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #59 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #58 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #58 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #17 :: Qd 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.s64 d5, d4, #17 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s64 d5, d4, #63 :: Qd 0x80000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqshl.s64 d5, d4, #63 :: Qd 0x7fffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.s64 d5, d4, #60 :: Qd 0xf0000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqshl.s64 d5, d4, #60 :: Qd 0x7fffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.s64 d5, d4, #7 :: Qd 0x80000000 0x00000000 Qm (i32)0x80000002 fpscr 08000000 +vqshl.s64 d5, d4, #7 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshl.s32 d10, d11, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshl.s32 d10, d11, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshl.s32 d31, d30, #1 :: Qd 0xffffff02 0xffffff02 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s32 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s32 d5, d4, #0 :: Qd 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s32 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s32 d5, d4, #31 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s32 d5, d4, #31 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s32 d5, d4, #28 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s32 d5, d4, #28 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s32 d5, d4, #27 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s32 d5, d4, #27 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s32 d5, d4, #26 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.s32 d5, d4, #26 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s32 d5, d4, #17 :: Qd 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.s32 d5, d4, #17 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s32 d5, d4, #31 :: Qd 0x80000000 0x80000000 Qm (i32)0xffffffff fpscr 00000000 +vqshl.s32 d5, d4, #31 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.s32 d5, d4, #29 :: Qd 0xe0000000 0xe0000000 Qm (i32)0xffffffff fpscr 00000000 +vqshl.s32 d5, d4, #29 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.s32 d5, d4, #7 :: Qd 0x80000000 0x80000000 Qm (i32)0x80000002 fpscr 08000000 +vqshl.s32 d5, d4, #7 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x80000002 fpscr 08000000 +vqshl.s16 d9, d8, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshl.s16 d9, d8, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshl.s16 d31, d30, #1 :: Qd 0xfffeff02 0xfffeff02 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s16 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s16 d5, d4, #0 :: Qd 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s16 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s16 d9, d8, #15 :: Qd 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s16 d9, d8, #15 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s16 d5, d4, #12 :: Qd 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s16 d5, d4, #12 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s16 d5, d4, #11 :: Qd 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s16 d5, d4, #11 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s16 d5, d4, #10 :: Qd 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.s16 d5, d4, #10 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s16 d5, d4, #4 :: Qd 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr 00000000 +vqshl.s16 d5, d4, #4 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x00000010 fpscr 08000000 +vqshl.s16 d5, d4, #15 :: Qd 0x80008000 0x80008000 Qm (i32)0xffffffff fpscr 00000000 +vqshl.s16 d5, d4, #15 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff fpscr 08000000 +vqshl.s16 d5, d4, #12 :: Qd 0xf000f000 0xf000f000 Qm (i32)0xffffffff fpscr 00000000 +vqshl.s16 d5, d4, #12 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff fpscr 08000000 +vqshl.s16 d5, d4, #7 :: Qd 0x80000100 0x80000100 Qm (i32)0x80000002 fpscr 08000000 +vqshl.s16 d5, d4, #7 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x80000002 fpscr 08000000 +vqshl.s8 d0, d1, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshl.s8 d0, d1, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshl.s8 d31, d30, #1 :: Qd 0xfefefe80 0xfefefe80 Qm (i32)0xffffff81 fpscr 08000000 +vqshl.s8 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s8 d5, d4, #0 :: Qd 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s8 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshl.s8 d5, d4, #7 :: Qd 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr 08000000 +vqshl.s8 d5, d4, #7 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0x00000010 fpscr 08000000 +vqshl.s8 d25, d4, #4 :: Qd 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr 08000000 +vqshl.s8 d25, d4, #4 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0x00000010 fpscr 08000000 +vqshl.s8 d5, d4, #3 :: Qd 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr 08000000 +vqshl.s8 d5, d4, #3 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0x00000010 fpscr 08000000 +vqshl.s8 d5, d4, #2 :: Qd 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr 00000000 +vqshl.s8 d5, d4, #2 :: Qd 0x4c6c686c 0x487c787c Qm (i32)0x00000010 fpscr 00000000 +vqshl.s8 d5, d4, #1 :: Qd 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr 00000000 +vqshl.s8 d5, d4, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000010 fpscr 00000000 +vqshl.s8 d5, d4, #7 :: Qd 0x80808080 0x80808080 Qm (i32)0xffffffff fpscr 00000000 +vqshl.s8 d5, d4, #7 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff fpscr 08000000 +vqshl.s8 d5, d4, #5 :: Qd 0xe0e0e0e0 0xe0e0e0e0 Qm (i32)0xffffffff fpscr 00000000 +vqshl.s8 d5, d4, #5 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff fpscr 08000000 +vqshl.s8 d5, d4, #2 :: Qd 0x80000008 0x80000008 Qm (i32)0x80000002 fpscr 08000000 +vqshl.s8 d5, d4, #2 :: Qd 0x4c6c686c 0x487c787c Qm (i32)0x80000002 fpscr 00000000 +vqshl.u64 d0, d1, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshl.u64 d0, d1, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshl.u64 d31, d30, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr 08000000 +vqshl.u64 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u64 d5, d4, #0 :: Qd 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u64 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #59 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #59 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #58 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #58 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #17 :: Qd 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u64 d5, d4, #17 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u64 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshl.u64 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshl.u32 d10, d11, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshl.u32 d10, d11, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshl.u32 d31, d30, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr 08000000 +vqshl.u32 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u32 d5, d4, #0 :: Qd 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u32 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u32 d5, d4, #28 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u32 d5, d4, #28 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u32 d5, d4, #27 :: Qd 0x80000000 0x80000000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u32 d5, d4, #27 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u32 d5, d4, #26 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u32 d5, d4, #26 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u32 d5, d4, #17 :: Qd 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u32 d5, d4, #17 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u32 d5, d4, #29 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u32 d5, d4, #29 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u32 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshl.u32 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshl.u16 d9, d8, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshl.u16 d9, d8, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshl.u16 d31, d30, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr 08000000 +vqshl.u16 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u16 d5, d4, #0 :: Qd 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u16 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u16 d9, d8, #15 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u16 d9, d8, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u16 d5, d4, #12 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u16 d5, d4, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u16 d5, d4, #11 :: Qd 0x00008000 0x00008000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u16 d5, d4, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u16 d5, d4, #10 :: Qd 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u16 d5, d4, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u16 d5, d4, #4 :: Qd 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u16 d5, d4, #4 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u16 d5, d4, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u16 d5, d4, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u16 d5, d4, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u16 d5, d4, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u16 d5, d4, #7 :: Qd 0xffff0100 0xffff0100 Qm (i32)0x80000002 fpscr 08000000 +vqshl.u16 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshl.u8 d0, d1, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshl.u8 d0, d1, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshl.u8 d31, d30, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr 08000000 +vqshl.u8 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u8 d5, d4, #0 :: Qd 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u8 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshl.u8 d5, d4, #7 :: Qd 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u8 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u8 d5, d4, #4 :: Qd 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u8 d5, d4, #4 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshl.u8 d5, d4, #3 :: Qd 0x00000080 0x00000080 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u8 d5, d4, #3 :: Qd 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u8 d5, d4, #2 :: Qd 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u8 d5, d4, #2 :: Qd 0x4c6c686c 0x487c787c Qm (i32)0x00000010 fpscr 00000000 +vqshl.u8 d5, d4, #1 :: Qd 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr 00000000 +vqshl.u8 d5, d4, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000010 fpscr 00000000 +vqshl.u8 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u8 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u8 d5, d4, #5 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u8 d5, d4, #5 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshl.u8 d5, d4, #2 :: Qd 0xff000008 0xff000008 Qm (i32)0x80000002 fpscr 08000000 +vqshl.u8 d5, d4, #2 :: Qd 0x4c6c686c 0x487c787c Qm (i32)0x80000002 fpscr 00000000 +vqshlu.s64 d0, d1, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshlu.s64 d0, d1, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshlu.s64 d31, d30, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000 +vqshlu.s64 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshlu.s64 d5, d4, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000 +vqshlu.s64 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshlu.s64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #59 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #59 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #58 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #58 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #17 :: Qd 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s64 d5, d4, #17 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s64 d5, d4, #63 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s64 d5, d4, #60 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s64 d5, d4, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 fpscr 08000000 +vqshlu.s64 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshlu.s32 d10, d11, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshlu.s32 d10, d11, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshlu.s32 d31, d30, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000 +vqshlu.s32 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshlu.s32 d5, d4, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000 +vqshlu.s32 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshlu.s32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s32 d25, d24, #28 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s32 d25, d24, #28 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s32 d5, d4, #27 :: Qd 0x80000000 0x80000000 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s32 d5, d4, #27 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s32 d5, d4, #26 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s32 d5, d4, #26 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s32 d5, d4, #17 :: Qd 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s32 d5, d4, #17 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s32 d5, d24, #31 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s32 d5, d24, #31 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s32 d5, d4, #29 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s32 d5, d4, #29 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s32 d5, d4, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000002 fpscr 08000000 +vqshlu.s32 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshlu.s16 d9, d8, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshlu.s16 d9, d8, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshlu.s16 d31, d30, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000 +vqshlu.s16 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshlu.s16 d5, d4, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000 +vqshlu.s16 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshlu.s16 d9, d8, #15 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s16 d9, d8, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s16 d5, d4, #12 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s16 d5, d4, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s16 d5, d4, #11 :: Qd 0x00008000 0x00008000 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s16 d5, d4, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s16 d5, d4, #10 :: Qd 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s16 d5, d4, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s16 d5, d4, #4 :: Qd 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s16 d5, d4, #4 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s16 d15, d14, #15 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s16 d15, d14, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s16 d5, d4, #12 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s16 d5, d4, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s16 d5, d4, #7 :: Qd 0x00000100 0x00000100 Qm (i32)0x80000002 fpscr 08000000 +vqshlu.s16 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr 08000000 +vqshlu.s8 d0, d1, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000 +vqshlu.s8 d0, d1, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr 00000000 +vqshlu.s8 d31, d30, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000 +vqshlu.s8 d31, d30, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr 00000000 +vqshlu.s8 d5, d4, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000 +vqshlu.s8 d5, d4, #0 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr 00000000 +vqshlu.s8 d5, d4, #7 :: Qd 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s8 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s8 d5, d4, #4 :: Qd 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s8 d5, d4, #4 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000 +vqshlu.s8 d5, d4, #3 :: Qd 0x00000080 0x00000080 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s8 d5, d4, #3 :: Qd 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s8 d5, d4, #2 :: Qd 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s8 d5, d4, #2 :: Qd 0x4c6c686c 0x487c787c Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s8 d5, d4, #1 :: Qd 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s8 d5, d4, #1 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000010 fpscr 00000000 +vqshlu.s8 d5, d4, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s8 d5, d4, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s8 d5, d4, #5 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s8 d5, d4, #5 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshlu.s8 d5, d4, #2 :: Qd 0x00000008 0x00000008 Qm (i32)0x80000002 fpscr 08000000 +vqshlu.s8 d5, d4, #2 :: Qd 0x4c6c686c 0x487c787c Qm (i32)0x80000002 fpscr 00000000 +---- VQRSHL (register) ---- +vqrshl.s64 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 d0, d1, d2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 d3, d4, d5 :: Qd 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 d3, d4, d5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.s64 d3, d4, d5 :: Qd 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s64 d3, d4, d5 :: Qd 0x02636343 0x6243e3c4 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s64 d0, d1, d2 :: Qd 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000 +vqrshl.s64 d0, d1, d2 :: Qd 0x7fffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqrshl.s64 d13, d14, d15 :: Qd 0xffffffff 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.s64 d13, d14, d15 :: Qd 0x00000004 0xc6c686c5 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.s32 d2, d8, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.s32 d2, d8, d4 :: Qd 0x0131b1a2 0x0121f1e2 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.s32 d12, d11, d13 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.s32 d12, d11, d13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.s32 d0, d1, d2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.s32 d9, d10, d11 :: Qd 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 d9, d10, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 d13, d3, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.s32 d13, d3, d5 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 08000000 +vqrshl.s16 d11, d10, d2 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 d11, d10, d2 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 d3, d14, d7 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s16 d3, d14, d7 :: Qd 0x098e0343 0x091003c4 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.s16 d0, d31, d2 :: Qd 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 d0, d31, d2 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 d1, d2, d3 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 d1, d2, d3 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.s16 d3, d4, d5 :: Qd 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.s16 d3, d4, d5 :: Qd 0x098e0001 0x09100001 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.s16 d0, d15, d2 :: Qd 0x00007fff 0x00007fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s16 d0, d15, d2 :: Qd 0x131b7fff 0x121f7fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s8 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 d2, d7, d11 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 d2, d7, d11 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 d2, d7, d11 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 d2, d7, d11 :: Qd 0x000000ff 0x000000ff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 d2, d7, d11 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.s8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s8 d2, d7, d11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s16 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s16 d2, d7, d11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s32 d2, d7, d31 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s32 d2, d7, d31 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.s8 d2, d7, d11 :: Qd 0xffffff80 0xffffff80 Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.s8 d2, d7, d11 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.s8 d13, d1, d2 :: Qd 0xffffff80 0xffffff80 Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s8 d13, d1, d2 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.s8 d3, d7, d5 :: Qd 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.s8 d3, d7, d5 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 08000000 +vqrshl.s8 d10, d11, d12 :: Qd 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000 +vqrshl.s8 d10, d11, d12 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqrshl.s8 d6, d7, d8 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.s8 d6, d7, d8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.s8 d10, d11, d12 :: Qd 0x0000007f 0x0000007f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqrshl.s8 d10, d11, d12 :: Qd 0x131b1a7f 0x121f1e7f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqrshl.u64 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.u64 d0, d1, d2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.u64 d3, d4, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 08000000 +vqrshl.u64 d3, d4, d5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000 +vqrshl.u64 d3, d4, d5 :: Qd 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u64 d3, d4, d5 :: Qd 0x02636343 0x6243e3c4 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u64 d0, d1, d2 :: Qd 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000 +vqrshl.u64 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 08000000 +vqrshl.u64 d13, d14, d15 :: Qd 0x0000003f 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.u64 d13, d14, d15 :: Qd 0x00000004 0xc6c686c5 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000 +vqrshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000 +vqrshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000 +vqrshl.u32 d2, d8, d4 :: Qd 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.u32 d2, d8, d4 :: Qd 0x0131b1a2 0x0121f1e2 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000 +vqrshl.u32 d12, d11, d13 :: Qd 0x00800000 0x00800000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.u32 d12, d11, d13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000 +vqrshl.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.u32 d0, d1, d2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000 +vqrshl.u32 d9, d10, d11 :: Qd 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 d9, d10, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 d13, d3, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u32 d13, d3, d5 :: Qd 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u16 d11, d10, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 d11, d10, d2 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 d3, d14, d7 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u16 d3, d14, d7 :: Qd 0x098e0343 0x091003c4 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000 +vqrshl.u16 d0, d31, d2 :: Qd 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 d0, d31, d2 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 d1, d2, d3 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 d1, d2, d3 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000 +vqrshl.u16 d3, d4, d5 :: Qd 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.u16 d3, d4, d5 :: Qd 0x098e0001 0x09100001 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000 +vqrshl.u16 d0, d15, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u16 d0, d15, d2 :: Qd 0x131bffff 0x121fffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.u8 d2, d7, d11 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000 +vqrshl.u8 d2, d7, d11 :: Qd 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 d2, d7, d11 :: Qd 0x8080807f 0x8080807f Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 d2, d7, d11 :: Qd 0x80007fff 0x80007fff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 d2, d7, d11 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000 +vqrshl.u8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u8 d2, d7, d11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u16 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u16 d2, d7, d11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u32 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u32 d2, d7, d11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000 +vqrshl.u8 d13, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u8 d13, d1, d2 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000 +vqrshl.u8 d3, d7, d5 :: Qd 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u8 d3, d7, d5 :: Qd 0x131b1ad8 0x121f1ef8 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000 +vqrshl.u8 d10, d11, d12 :: Qd 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000 +vqrshl.u8 d10, d11, d12 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 08000000 +vqrshl.u8 d6, d7, d8 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.u8 d6, d7, d8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000 +vqrshl.u8 d10, d11, d12 :: Qd 0x000000ff 0x000000ff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +vqrshl.u8 d10, d11, d12 :: Qd 0x131b1aff 0x121f1eff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000 +---- VRSHL (register) ---- +vrshl.s64 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 +vrshl.s64 d0, d1, d2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 +vrshl.s64 d3, d4, d5 :: Qd 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 +vrshl.s64 d3, d4, d5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 +vrshl.s64 d3, d4, d5 :: Qd 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd +vrshl.s64 d3, d4, d5 :: Qd 0x02636343 0x6243e3c4 Qm (i32)0xffffff81 Qn (i32)0xfffffffd +vrshl.s64 d0, d1, d2 :: Qd 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e +vrshl.s64 d0, d1, d2 :: Qd 0xc686c487 0xc787c000 Qm (i32)0x00000010 Qn (i32)0x0000000e +vrshl.s64 d13, d14, d15 :: Qd 0xffffffff 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 +vrshl.s64 d13, d14, d15 :: Qd 0x00000004 0xc6c686c5 Qm (i32)0xffffffef Qn (i32)0xffffffe6 +vrshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 +vrshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 +vrshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 +vrshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 +vrshl.s32 d2, d8, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc +vrshl.s32 d2, d8, d4 :: Qd 0x0131b1a2 0x0121f1e2 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc +vrshl.s32 d12, d11, d13 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 +vrshl.s32 d12, d11, d13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 +vrshl.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 +vrshl.s32 d0, d1, d2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 +vrshl.s32 d9, d10, d11 :: Qd 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff +vrshl.s32 d9, d10, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x80000008 Qn (i32)0xffffffff +vrshl.s32 d13, d3, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 +vrshl.s32 d13, d3, d5 :: Qd 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x08000000 Qn (i32)0x00000003 +vrshl.s16 d11, d10, d2 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 +vrshl.s16 d11, d10, d2 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 +vrshl.s16 d3, d14, d7 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd +vrshl.s16 d3, d14, d7 :: Qd 0x098e0343 0x091003c4 Qm (i32)0x80000000 Qn (i32)0xfffffffd +vrshl.s16 d0, d11, d2 :: Qd 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff +vrshl.s16 d0, d11, d2 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x80000100 Qn (i32)0xffffffff +vrshl.s16 d1, d2, d3 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 +vrshl.s16 d1, d2, d3 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 +vrshl.s16 d3, d4, d5 :: Qd 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 +vrshl.s16 d3, d4, d5 :: Qd 0x098e0001 0x09100001 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 +vrshl.s16 d0, d15, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x0000001e +vrshl.s16 d0, d15, d2 :: Qd 0x131b0000 0x121f0000 Qm (i32)0x00000001 Qn (i32)0x0000001e +vrshl.s8 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s16 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s32 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.s8 d2, d7, d31 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s8 d2, d7, d31 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s16 d2, d7, d31 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s16 d2, d7, d31 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s32 d2, d7, d31 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s32 d2, d7, d31 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.s8 d2, d7, d11 :: Qd 0x000000ff 0x000000ff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s16 d2, d7, d11 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s32 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.s8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s8 d2, d7, d11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s16 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s16 d2, d7, d11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s32 d2, d7, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s32 d2, d7, d11 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff Qn (i32)0x00000000 +vrshl.s8 d2, d7, d11 :: Qd 0xffffff00 0xffffff00 Qm (i32)0xffffffff Qn (i32)0x00000028 +vrshl.s8 d2, d7, d11 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0xffffffff Qn (i32)0x00000028 +vrshl.s8 d13, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0xfffffffc Qn (i32)0x0000001e +vrshl.s8 d13, d1, d2 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0xfffffffc Qn (i32)0x0000001e +vrshl.s8 d3, d7, d5 :: Qd 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 +vrshl.s8 d3, d7, d5 :: Qd 0x131b1ad8 0x121f1ef8 Qm (i32)0x8000000b Qn (i32)0x00000003 +vrshl.s8 d10, d11, d12 :: Qd 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 +vrshl.s8 d10, d11, d12 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0x00010000 Qn (i32)0x00000010 +vrshl.s8 d6, d7, d8 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 +vrshl.s8 d6, d7, d8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 +vrshl.s8 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vrshl.s8 d10, d11, d12 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0x00000018 Qn (i32)0x00000078 +vrshl.u64 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 +vrshl.u64 d0, d1, d2 :: Qd 0x26363436 0x243e3c3e Qm (i32)0x00000001 Qn (i32)0x00000001 +vrshl.u64 d3, d4, d5 :: Qd 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 +vrshl.u64 d3, d4, d5 :: Qd 0x26363436 0x243e3c3e Qm (i32)0xffffff81 Qn (i32)0x00000001 +vrshl.u64 d3, d4, d5 :: Qd 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd +vrshl.u64 d3, d4, d5 :: Qd 0x02636343 0x6243e3c4 Qm (i32)0xffffff81 Qn (i32)0xfffffffd +vrshl.u64 d0, d1, d2 :: Qd 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e +vrshl.u64 d0, d1, d2 :: Qd 0xc686c487 0xc787c000 Qm (i32)0x00000010 Qn (i32)0x0000000e +vrshl.u64 d13, d14, d15 :: Qd 0x0000003f 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 +vrshl.u64 d13, d14, d15 :: Qd 0x00000004 0xc6c686c5 Qm (i32)0xffffffef Qn (i32)0xffffffe6 +vrshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 +vrshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000001 Qm (i32)0x00000018 Qn (i32)0xffffffc4 +vrshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 +vrshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 +vrshl.u32 d2, d8, d4 :: Qd 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc +vrshl.u32 d2, d8, d4 :: Qd 0x0131b1a2 0x0121f1e2 Qm (i32)0xfffffff5 Qn (i32)0xfffffffc +vrshl.u32 d12, d11, d13 :: Qd 0x00800000 0x00800000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 +vrshl.u32 d12, d11, d13 :: Qd 0x00098d8d 0x00090f8f Qm (i32)0xffffff88 Qn (i32)0xfffffff7 +vrshl.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 +vrshl.u32 d0, d1, d2 :: Qd 0x00263634 0x00243e3c Qm (i32)0x00000022 Qn (i32)0xfffffff9 +vrshl.u32 d9, d10, d11 :: Qd 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff +vrshl.u32 d9, d10, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x80000008 Qn (i32)0xffffffff +vrshl.u32 d13, d3, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 +vrshl.u32 d13, d3, d5 :: Qd 0x98d8d0d8 0x90f8f0f8 Qm (i32)0x08000000 Qn (i32)0x00000003 +vrshl.u16 d11, d10, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 +vrshl.u16 d11, d10, d2 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 +vrshl.u16 d3, d14, d7 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd +vrshl.u16 d3, d14, d7 :: Qd 0x098e0343 0x091003c4 Qm (i32)0x80000000 Qn (i32)0xfffffffd +vrshl.u16 d0, d31, d2 :: Qd 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff +vrshl.u16 d0, d31, d2 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x80000100 Qn (i32)0xffffffff +vrshl.u16 d1, d2, d3 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 +vrshl.u16 d1, d2, d3 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 +vrshl.u16 d3, d4, d5 :: Qd 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 +vrshl.u16 d3, d4, d5 :: Qd 0x098e0001 0x09100001 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 +vrshl.u16 d0, d15, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x0000001e +vrshl.u16 d0, d15, d2 :: Qd 0x131b0000 0x121f0000 Qm (i32)0x00000001 Qn (i32)0x0000001e +vrshl.u8 d2, d7, d11 :: Qd 0xffffff00 0xffffff00 Qm (i32)0xffffffff Qn (i32)0x00000028 +vrshl.u8 d2, d7, d11 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0xffffffff Qn (i32)0x00000028 +vrshl.u8 d2, d7, d11 :: Qd 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u8 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u16 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u32 d2, d7, d11 :: Qd 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0x0000000f Qn (i32)0xffffffff +vrshl.u8 d2, d7, d11 :: Qd 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u8 d2, d7, d11 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u16 d2, d7, d11 :: Qd 0x80008000 0x80008000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u16 d2, d7, d11 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u32 d2, d7, d11 :: Qd 0x80000000 0x80000000 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u32 d2, d7, d11 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xffffffff Qn (i32)0xffffffff +vrshl.u8 d2, d7, d31 :: Qd 0x8080807f 0x8080807f Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u8 d2, d7, d31 :: Qd 0x0a0e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u16 d2, d7, d31 :: Qd 0x80007fff 0x80007fff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u16 d2, d7, d31 :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u32 d2, d7, d31 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u32 d2, d7, d31 :: Qd 0x098d8d0e 0x090f8f10 Qm (i32)0xfffffffe Qn (i32)0xffffffff +vrshl.u8 d13, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0xfffffffc Qn (i32)0x0000001e +vrshl.u8 d13, d1, d2 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0xfffffffc Qn (i32)0x0000001e +vrshl.u8 d3, d7, d5 :: Qd 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 +vrshl.u8 d3, d7, d5 :: Qd 0x131b1ad8 0x121f1ef8 Qm (i32)0x8000000b Qn (i32)0x00000003 +vrshl.u8 d10, d11, d12 :: Qd 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 +vrshl.u8 d10, d11, d12 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0x00010000 Qn (i32)0x00000010 +vrshl.u8 d6, d7, d8 :: Qd 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 +vrshl.u8 d6, d7, d8 :: Qd 0x131b1a6c 0x121f1e7c Qm (i32)0x40000000 Qn (i32)0x00000002 +vrshl.u8 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vrshl.u8 d10, d11, d12 :: Qd 0x131b1a00 0x121f1e00 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VMAX (integer) ---- +vmax.s32 d0, d1, d2 :: Qd 0x00000079 0x00000079 Qm (i32)0x00000019 Qn (i32)0x00000079 +vmax.s32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000019 Qn (i32)0x00000079 +vmax.s32 d0, d1, d2 :: Qd 0x000000fa 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000079 +vmax.s32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x000000fa Qn (i32)0x00000079 +vmax.s32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmax.s32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x0000008c Qn (i32)0x0000008c +vmax.s16 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x00000078 +vmax.s16 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x0000008c Qn (i32)0x00000078 +vmax.s8 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmax.s8 d0, d1, d2 :: Qd 0x131b1a78 0x121f1e78 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmax.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s8 d5, d7, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s16 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.s8 d5, d7, d5 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s8 d5, d7, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s16 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s16 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s32 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.s8 d5, d7, d5 :: Qd 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s8 d5, d7, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s16 d0, d1, d2 :: Qd 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s16 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s32 d0, d1, d2 :: Qd 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.s32 d10, d11, d12 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmax.s32 d10, d11, d12 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000018 Qn (i32)0x00000078 +vmax.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000019 Qn (i32)0x00000078 +vmax.u32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000019 Qn (i32)0x00000078 +vmax.u32 d0, d1, d2 :: Qd 0x000000fa 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000078 +vmax.u32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x000000fa Qn (i32)0x00000078 +vmax.u32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmax.u32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x0000008c Qn (i32)0x0000008c +vmax.u16 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x00000078 +vmax.u16 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x0000008c Qn (i32)0x00000078 +vmax.u8 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmax.u8 d0, d1, d2 :: Qd 0x131b1a78 0x121f1e78 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmax.u8 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u8 d0, d1, d2 :: Qd 0x801b1a1b 0x801f1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u16 d0, d1, d2 :: Qd 0x80001a1b 0x80001e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmax.u8 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u8 d0, d1, d2 :: Qd 0x801b1a1b 0x801f1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u16 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u16 d0, d1, d2 :: Qd 0x80001a1b 0x80001e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u32 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u32 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmax.u8 d0, d1, d2 :: Qd 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u8 d0, d1, d2 :: Qd 0x801b1a1b 0x801f1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u16 d0, d1, d2 :: Qd 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u16 d0, d1, d2 :: Qd 0x80001a1b 0x80001e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u32 d0, d1, d2 :: Qd 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmax.u32 d10, d11, d12 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmax.u32 d10, d11, d12 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VMIN (integer) ---- +vmin.s32 d0, d1, d2 :: Qd 0x00000019 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000079 +vmin.s32 d0, d1, d2 :: Qd 0x00000079 0x00000079 Qm (i32)0x00000019 Qn (i32)0x00000079 +vmin.s32 d0, d1, d2 :: Qd 0x00000079 0x00000079 Qm (i32)0x000000fa Qn (i32)0x00000079 +vmin.s32 d0, d1, d2 :: Qd 0x00000079 0x00000079 Qm (i32)0x000000fa Qn (i32)0x00000079 +vmin.s32 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmin.s32 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmin.s16 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmin.s16 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmin.s8 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmin.s8 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmin.s8 d5, d7, d5 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s16 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s32 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.s8 d5, d7, d5 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s8 d5, d7, d5 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s16 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s16 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s32 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s32 d0, d1, d2 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.s32 d10, d11, d12 :: Qd 0x00000018 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmin.s32 d10, d11, d12 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmin.u32 d0, d1, d2 :: Qd 0x00000019 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000078 +vmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000019 Qn (i32)0x00000078 +vmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x000000fa Qn (i32)0x00000078 +vmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x000000fa Qn (i32)0x00000078 +vmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmin.u16 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmin.u16 d0, d1, d2 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vmin.u8 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vmin.u8 d0, d1, d2 :: Qd 0x0000001b 0x0000001f Qm (i32)0x0000008c Qn (i32)0x0000008c +vmin.u8 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u8 d0, d1, d2 :: Qd 0x13000002 0x12000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u16 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u16 d0, d1, d2 :: Qd 0x131b0002 0x121f0002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u32 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vmin.u8 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u8 d0, d1, d2 :: Qd 0x13000003 0x12000003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u16 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u16 d0, d1, d2 :: Qd 0x131b0003 0x121f0003 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u32 d0, d1, d2 :: Qd 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vmin.u8 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u8 d0, d1, d2 :: Qd 0x13000002 0x12000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u16 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u16 d0, d1, d2 :: Qd 0x131b0002 0x121f0002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vmin.u32 d10, d11, d12 :: Qd 0x00000018 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmin.u32 d10, d11, d12 :: Qd 0x00000078 0x00000078 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VABD ---- +vabd.s32 d0, d1, d2 :: Qd 0x0000005f 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078 +vabd.s32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000019 Qn (i32)0x00000078 +vabd.s32 d0, d1, d2 :: Qd 0x00000060 0x00000060 Qm (i32)0x00000019 Qn (i32)0x00000079 +vabd.s32 d0, d1, d2 :: Qd 0x131b19a2 0x121f1da6 Qm (i32)0x00000019 Qn (i32)0x00000079 +vabd.s32 d0, d1, d2 :: Qd 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vabd.s32 d0, d1, d2 :: Qd 0x131b1a93 0x121f1e97 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vabd.s16 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.s16 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.s8 d0, d1, d2 :: Qd 0x000000ec 0x000000ec Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.s8 d0, d1, d2 :: Qd 0x131b1a5d 0x121f1e59 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.s8 d5, d7, d5 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s8 d5, d7, d5 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s8 d5, d7, d5 :: Qd 0x7f010101 0x7f010101 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabd.s8 d5, d7, d5 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabd.s8 d5, d7, d5 :: Qd 0x7f010137 0x7f010137 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabd.s8 d5, d7, d5 :: Qd 0x141c1b1d 0x13201f19 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabd.s16 d0, d1, d2 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s16 d0, d1, d2 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s32 d0, d1, d2 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s32 d0, d1, d2 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.s8 d5, d7, d5 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s8 d5, d7, d5 :: Qd 0x931b1a18 0x921f1e1c Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s16 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s16 d0, d1, d2 :: Qd 0x931b1a18 0x921f1e1c Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s32 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s32 d0, d1, d2 :: Qd 0x931b1a18 0x921f1e1c Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.s8 d5, d7, d5 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s8 d5, d7, d5 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s16 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s16 d0, d1, d2 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s32 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s32 d0, d1, d2 :: Qd 0x931b1a19 0x921f1e1d Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.s32 d10, d11, d12 :: Qd 0x00000060 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078 +vabd.s32 d10, d11, d12 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 +vabd.u32 d0, d1, d2 :: Qd 0x0000005f 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078 +vabd.u32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000019 Qn (i32)0x00000078 +vabd.u32 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.u32 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.u16 d0, d1, d2 :: Qd 0xfffffefc 0xfffffefc Qm (i32)0xffffff74 Qn (i32)0x00000078 +vabd.u16 d0, d1, d2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0xffffff74 Qn (i32)0x00000078 +vabd.u8 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.u8 d0, d1, d2 :: Qd 0x131b1a5d 0x121f1e59 Qm (i32)0x0000008c Qn (i32)0x00000078 +vabd.u8 d5, d7, d5 :: Qd 0x7fffff01 0x7fffff01 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabd.u8 d5, d7, d5 :: Qd 0x6d1b1a19 0x6e1f1e1d Qm (i32)0xffffff01 Qn (i32)0x80000002 +vabd.u8 d5, d7, d5 :: Qd 0x7fffff37 0x7fffff37 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabd.u8 d5, d7, d5 :: Qd 0xece4e51d 0xede0e119 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vabd.u8 d0, d1, d2 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u8 d0, d1, d2 :: Qd 0x6d1b1a19 0x6e1f1e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u16 d0, d1, d2 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u16 d0, d1, d2 :: Qd 0x6ce51a19 0x6de11e1d Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u32 d0, d1, d2 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u32 d0, d1, d2 :: Qd 0x6ce4e5e7 0x6de0e1e3 Qm (i32)0x80000001 Qn (i32)0x80000002 +vabd.u8 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u8 d0, d1, d2 :: Qd 0x6d1b1a18 0x6e1f1e1c Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u16 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u16 d0, d1, d2 :: Qd 0x6ce51a18 0x6de11e1c Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u32 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u32 d0, d1, d2 :: Qd 0x6ce4e5e8 0x6de0e1e4 Qm (i32)0x80000001 Qn (i32)0x80000003 +vabd.u8 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u8 d0, d1, d2 :: Qd 0x6d1b1a19 0x6e1f1e1d Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u16 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u16 d0, d1, d2 :: Qd 0x6ce51a19 0x6de11e1d Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u32 d0, d1, d2 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u32 d0, d1, d2 :: Qd 0x6ce4e5e7 0x6de0e1e3 Qm (i32)0x80000004 Qn (i32)0x80000002 +vabd.u32 d10, d11, d12 :: Qd 0x00000060 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078 +vabd.u32 d10, d11, d12 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VABA ---- +vaba.s32 d0, d1, d2 :: Qd 0x555555b4 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078 +vaba.s32 d0, d1, d2 :: Qd 0x68706ef8 0x677472fc Qm (i32)0x00000019 Qn (i32)0x00000078 +vaba.s32 d0, d1, d2 :: Qd 0x555555b5 0x555555b5 Qm (i32)0x00000019 Qn (i32)0x00000079 +vaba.s32 d0, d1, d2 :: Qd 0x68706ef7 0x677472fb Qm (i32)0x00000019 Qn (i32)0x00000079 +vaba.s32 d0, d1, d2 :: Qd 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s32 d0, d1, d2 :: Qd 0x68706ef8 0x677472fc Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s16 d0, d1, d2 :: Qd 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s16 d0, d1, d2 :: Qd 0x68706ef8 0x677472fc Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s8 d0, d1, d2 :: Qd 0x55555541 0x55555541 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s8 d0, d1, d2 :: Qd 0x68706fb2 0x677473ae Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.s8 d5, d7, d5 :: Qd 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s8 d5, d7, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s8 d5, d7, d5 :: Qd 0xff010103 0xff010103 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vaba.s8 d5, d7, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff01 Qn (i32)0x80000002 +vaba.s8 d5, d7, d5 :: Qd 0x7e00006f 0x7e00006f Qm (i32)0x80000001 Qn (i32)0xffffff38 +vaba.s8 d5, d7, d5 :: Qd 0x131b1a55 0x121f1e51 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vaba.s16 d0, d1, d2 :: Qd 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s16 d0, d1, d2 :: Qd 0xe8706f6e 0xe7747372 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s32 d0, d1, d2 :: Qd 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s32 d0, d1, d2 :: Qd 0xe8706f6e 0xe7747372 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.s8 d5, d7, d5 :: Qd 0x80000005 0x80000005 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s8 d5, d7, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s16 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s16 d0, d1, d2 :: Qd 0xe8706f6d 0xe7747371 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s32 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s32 d0, d1, d2 :: Qd 0xe8706f6d 0xe7747371 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.s8 d5, d7, d5 :: Qd 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s8 d5, d7, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s16 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s16 d0, d1, d2 :: Qd 0xe8706f6e 0xe7747372 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s32 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s32 d0, d1, d2 :: Qd 0xe8706f6e 0xe7747372 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.s32 d10, d11, d12 :: Qd 0x555555b5 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078 +vaba.s32 d10, d11, d12 :: Qd 0x68706ef8 0x677472fc Qm (i32)0x00000018 Qn (i32)0x00000078 +vaba.u32 d0, d1, d2 :: Qd 0x555555b4 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078 +vaba.u32 d0, d1, d2 :: Qd 0x68706ef8 0x677472fc Qm (i32)0x00000019 Qn (i32)0x00000078 +vaba.u32 d0, d1, d2 :: Qd 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u32 d0, d1, d2 :: Qd 0x68706ef8 0x677472fc Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u16 d0, d1, d2 :: Qd 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u16 d0, d1, d2 :: Qd 0x68706ef8 0x677472fc Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u8 d0, d1, d2 :: Qd 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u8 d0, d1, d2 :: Qd 0x68706fb2 0x677473ae Qm (i32)0x0000008c Qn (i32)0x00000078 +vaba.u8 d5, d7, d5 :: Qd 0xffffff03 0xffffff03 Qm (i32)0xffffff01 Qn (i32)0x80000002 +vaba.u8 d5, d7, d5 :: Qd 0xed1b1a1b 0xee1f1e1f Qm (i32)0xffffff01 Qn (i32)0x80000002 +vaba.u8 d5, d7, d5 :: Qd 0x7efefe6f 0x7efefe6f Qm (i32)0x80000001 Qn (i32)0xffffff38 +vaba.u8 d5, d7, d5 :: Qd 0xebe3e455 0xecdfe051 Qm (i32)0x80000001 Qn (i32)0xffffff38 +vaba.u8 d0, d1, d2 :: Qd 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u8 d0, d1, d2 :: Qd 0xc2706f6e 0xc3747372 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u16 d0, d1, d2 :: Qd 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u16 d0, d1, d2 :: Qd 0xc23a6f6e 0xc3367372 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u32 d0, d1, d2 :: Qd 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u32 d0, d1, d2 :: Qd 0xc23a3b3c 0xc3363738 Qm (i32)0x80000001 Qn (i32)0x80000002 +vaba.u8 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u8 d0, d1, d2 :: Qd 0xc2706f6d 0xc3747371 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u16 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u16 d0, d1, d2 :: Qd 0xc23a6f6d 0xc3367371 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u32 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u32 d0, d1, d2 :: Qd 0xc23a3b3d 0xc3363739 Qm (i32)0x80000001 Qn (i32)0x80000003 +vaba.u8 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u8 d0, d1, d2 :: Qd 0xc2706f6e 0xc3747372 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u16 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u16 d0, d1, d2 :: Qd 0xc23a6f6e 0xc3367372 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u32 d0, d1, d2 :: Qd 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u32 d0, d1, d2 :: Qd 0xc23a3b3c 0xc3363738 Qm (i32)0x80000004 Qn (i32)0x80000002 +vaba.u32 d10, d11, d12 :: Qd 0x555555b5 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078 +vaba.u32 d10, d11, d12 :: Qd 0x68706ef8 0x677472fc Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VTST ---- +vtst.32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +vtst.32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +vtst.32 d3, d4, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vtst.32 d3, d4, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078 +vtst.16 d6, d7, d8 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vtst.16 d6, d7, d8 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vtst.8 d9, d10, d12 :: Qd 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078 +vtst.8 d9, d10, d12 :: Qd 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078 +vtst.8 d0, d1, d2 :: Qd 0xff000000 0xff000000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vtst.8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 +vtst.16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00004001 Qn (i32)0x00004001 +vtst.16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00004001 Qn (i32)0x00004001 +vtst.32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vtst.32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 +vtst.8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x00000002 +vtst.8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x00000002 +vtst.16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00004001 Qn (i32)0x00004001 +vtst.16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00004001 Qn (i32)0x00004001 +vtst.32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x80000002 +vtst.32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000001 Qn (i32)0x80000002 +vtst.32 d10, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +vtst.32 d10, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VCEQ ---- +vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vceq.i32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078 +vceq.i32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078 +vceq.i16 d6, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078 +vceq.i16 d6, d7, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vceq.i8 d9, d10, d12 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078 +vceq.i8 d9, d10, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078 +vceq.i8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000002 +vceq.i8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vceq.i16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00004001 Qn (i32)0x00004001 +vceq.i16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00004001 Qn (i32)0x00004001 +vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vceq.i8 d0, d1, d2 :: Qd 0x00ffff00 0x00ffff00 Qm (i32)0x80000001 Qn (i32)0x00000002 +vceq.i8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x00000002 +vceq.i16 d0, d1, d2 :: Qd 0xffff0000 0xffff0000 Qm (i32)0x00000001 Qn (i32)0x00004001 +vceq.i16 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x00004001 +vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x80000002 +vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x80000002 +vceq.i32 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +vceq.i32 d10, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VMLA ---- +vmla.i32 d0, d1, d2 :: Qd 0x55554a15 0x55554a15 Qm (i32)0xffffffe8 Qn (i32)0x00000078 +vmla.i32 d0, d1, d2 :: Qd 0x4a0991fd 0xd3eb73dd Qm (i32)0xffffffe8 Qn (i32)0x00000078 +vmla.i32 d6, d7, d8 :: Qd 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmla.i32 d6, d7, d8 :: Qd 0x4a0991fd 0xd3eb73dd Qm (i32)0x0000008c Qn (i32)0x00000078 +vmla.i16 d9, d11, d12 :: Qd 0x5555bd55 0x5555bd55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmla.i16 d9, d11, d12 :: Qd 0x5555b3b5 0x55553835 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmla.i8 d0, d1, d2 :: Qd 0x555555b5 0x555555b5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmla.i8 d0, d1, d2 :: Qd 0x423a3bad 0x433637cd Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmla.i8 d10, d11, d12 :: Qd 0x5555559f 0x5555559f Qm (i32)0x00000021 Qn (i32)0x0000000a +vmla.i8 d10, d11, d12 :: Qd 0x55555563 0x5555558b Qm (i32)0x00000021 Qn (i32)0x0000000a +vmla.i16 d4, d5, d6 :: Qd 0x5555f557 0x5555f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmla.i16 d4, d5, d6 :: Qd 0x5555e98b 0x55557193 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmla.i32 d7, d8, d9 :: Qd 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i32 d7, d8, d9 :: Qd 0xfb8b898b 0xf9939193 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i8 d10, d13, d12 :: Qd 0x5555559f 0x5555559f Qm (i32)0x00000021 Qn (i32)0x0000000a +vmla.i8 d10, d13, d12 :: Qd 0x55555563 0x5555558b Qm (i32)0x00000021 Qn (i32)0x0000000a +vmla.i16 d4, d5, d6 :: Qd 0x55551751 0x55551751 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmla.i16 d4, d5, d6 :: Qd 0x5555e98b 0x55557193 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmla.i32 d7, d8, d9 :: Qd 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i32 d7, d8, d9 :: Qd 0xfb8b898b 0xf9939193 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i32 d10, d11, d15 :: Qd 0x55554a15 0x55554a15 Qm (i32)0x00000018 Qn (i32)0xffffff88 +vmla.i32 d10, d11, d15 :: Qd 0x60a118ad 0xd6bf36cd Qm (i32)0x00000018 Qn (i32)0xffffff88 +---- VMLS ---- +vmls.i32 d0, d1, d2 :: Qd 0x55556095 0x55556095 Qm (i32)0xffffffe8 Qn (i32)0x00000078 +vmls.i32 d0, d1, d2 :: Qd 0x60a118ad 0xd6bf36cd Qm (i32)0xffffffe8 Qn (i32)0x00000078 +vmls.i32 d6, d7, d8 :: Qd 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmls.i32 d6, d7, d8 :: Qd 0x4a0991fd 0xd3eb73dd Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmls.i16 d9, d11, d12 :: Qd 0x5555ed55 0x5555ed55 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmls.i16 d9, d11, d12 :: Qd 0x5555f6f5 0x55557275 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmls.i8 d0, d1, d2 :: Qd 0x555555b5 0x555555b5 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmls.i8 d0, d1, d2 :: Qd 0x555555ad 0x555555cd Qm (i32)0x0000008c Qn (i32)0x00000078 +vmls.i8 d10, d11, d12 :: Qd 0x5555550b 0x5555550b Qm (i32)0x00000021 Qn (i32)0x0000000a +vmls.i8 d10, d11, d12 :: Qd 0x55555547 0x5555551f Qm (i32)0x00000021 Qn (i32)0x0000000a +vmls.i16 d4, d5, d6 :: Qd 0x5555b553 0x5555b553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmls.i16 d4, d5, d6 :: Qd 0x5555c11f 0x55553917 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmls.i32 d7, d8, d9 :: Qd 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i32 d7, d8, d9 :: Qd 0xaf1f211f 0xb1171917 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i8 d10, d13, d12 :: Qd 0x5555550b 0x5555550b Qm (i32)0x00000021 Qn (i32)0x0000000a +vmls.i8 d10, d13, d12 :: Qd 0x55555547 0x5555551f Qm (i32)0x00000021 Qn (i32)0x0000000a +vmls.i16 d4, d5, d6 :: Qd 0x55559359 0x55559359 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmls.i16 d4, d5, d6 :: Qd 0x5555c11f 0x55553917 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmls.i32 d7, d8, d9 :: Qd 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i32 d7, d8, d9 :: Qd 0xaf1f211f 0xb1171917 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i32 d10, d11, d15 :: Qd 0x55556095 0x55556095 Qm (i32)0xffffffe8 Qn (i32)0x00000078 +vmls.i32 d10, d11, d15 :: Qd 0x60a118ad 0xd6bf36cd Qm (i32)0xffffffe8 Qn (i32)0x00000078 +---- VMUL ---- +vmul.i32 d0, d1, d2 :: Qd 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.i32 d0, d1, d2 :: Qd 0xf4b43ca8 0x7e961e88 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.i32 d6, d7, d8 :: Qd 0xffffbe60 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmul.i32 d6, d7, d8 :: Qd 0x0b4bc358 0x8169e178 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmul.i16 d9, d11, d12 :: Qd 0x00006800 0x00006800 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmul.i16 d9, d11, d12 :: Qd 0x00005e60 0x0000e2e0 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmul.i8 d0, d1, d2 :: Qd 0x000000a0 0x000000a0 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmul.i8 d0, d1, d2 :: Qd 0x000000a8 0x00000088 Qm (i32)0x0000008c Qn (i32)0x00000078 +vmul.i8 d10, d11, d12 :: Qd 0x0000004a 0x0000004a Qm (i32)0x00000021 Qn (i32)0x0000000a +vmul.i8 d10, d11, d12 :: Qd 0x0000000e 0x00000036 Qm (i32)0x00000021 Qn (i32)0x0000000a +vmul.i16 d4, d5, d6 :: Qd 0x0000a002 0x0000a002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmul.i16 d4, d5, d6 :: Qd 0x00009436 0x00001c3e Qm (i32)0x00004001 Qn (i32)0x00002002 +vmul.i32 d7, d8, d9 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i32 d7, d8, d9 :: Qd 0xa6363436 0xa43e3c3e Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i8 d10, d11, d12 :: Qd 0x0000c00e 0x0000c00e Qm (i32)0x0200feb2 Qn (i32)0x000020df +vmul.i8 d10, d11, d12 :: Qd 0x00004085 0x0000c001 Qm (i32)0x0200feb2 Qn (i32)0x000020df +vmul.i16 d4, d5, d6 :: Qd 0x00008866 0x00008866 Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmul.i16 d4, d5, d6 :: Qd 0x00009436 0x00001c3e Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmul.i32 d7, d8, d9 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmul.i32 d7, d8, d9 :: Qd 0xe5453944 0xd9756974 Qm (i32)0x80000000 Qn (i32)0x0000000c +vmul.i8 d10, d13, d12 :: Qd 0x0000004a 0x0000004a Qm (i32)0x00000021 Qn (i32)0x0000000a +vmul.i8 d10, d13, d12 :: Qd 0x0000000e 0x00000036 Qm (i32)0x00000021 Qn (i32)0x0000000a +vmul.i16 d4, d5, d6 :: Qd 0x0000c1fc 0x0000c1fc Qm (i32)0x100000fe Qn (i32)0x00002002 +vmul.i16 d4, d5, d6 :: Qd 0x00009436 0x00001c3e Qm (i32)0x100000fe Qn (i32)0x00002002 +vmul.i32 d7, d8, d9 :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i32 d7, d8, d9 :: Qd 0xa6363436 0xa43e3c3e Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i32 d10, d11, d15 :: Qd 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.i32 d10, d11, d15 :: Qd 0xf4b43ca8 0x7e961e88 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.p8 q0, q1, q2 :: Qd 0x00000005 0x00000005 Qm (i32)0x00000003 Qn (i32)0x00000003 +vmul.p8 q0, q1, q2 :: Qd 0x0000002d 0x00000021 Qm (i32)0x00000003 Qn (i32)0x00000003 +vmul.p8 q0, q1, q2 :: Qd 0x00000044 0x00000044 Qm (i32)0x0000000c Qn (i8)0x0000000f +vmul.p8 q0, q1, q2 :: Qd 0xe1999699 0xeea5aaa5 Qm (i32)0x0000000c Qn (i8)0x0000000f +---- VMUL (by scalar) ---- +vmul.i32 d0, d1, d4[0] :: Qd 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.i32 d0, d1, d4[0] :: Qd 0xf4b43ca8 0x7e961e88 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmul.i32 d31, d8, d7[1] :: Qd 0xffffbe60 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmul.i32 d31, d8, d7[1] :: Qd 0x0b4bc358 0x8169e178 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmul.i16 d30, d9, d7[3] :: Qd 0x00000000 0x00000000 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmul.i16 d30, d9, d7[3] :: Qd 0x00000000 0x00000000 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmul.i16 d4, d5, d6[2] :: Qd 0x0000a002 0x0000a002 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmul.i16 d4, d5, d6[2] :: Qd 0x86369436 0x043e1c3e Qm (i32)0x00004001 Qn (i32)0x00002002 +vmul.i32 d4, d8, d15[1] :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i32 d4, d8, d15[1] :: Qd 0xa6363436 0xa43e3c3e Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i16 d4, d5, d6[0] :: Qd 0xdffe8866 0xdffe8866 Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmul.i16 d4, d5, d6[0] :: Qd 0x86369436 0x043e1c3e Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmul.i32 d7, d8, d1[1] :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmul.i32 d7, d8, d1[1] :: Qd 0x1e893944 0x42e96974 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmul.i16 d4, d5, d6[0] :: Qd 0x2000c1fc 0x2000c1fc Qm (i32)0x100000fe Qn (i32)0x00002002 +vmul.i16 d4, d5, d6[0] :: Qd 0x86369436 0x043e1c3e Qm (i32)0x100000fe Qn (i32)0x00002002 +vmul.i32 d7, d8, d1[1] :: Qd 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmul.i32 d7, d8, d1[1] :: Qd 0xa6363436 0xa43e3c3e Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VMLA (by scalar) ---- +vmla.i32 d0, d1, d4[0] :: Qd 0x55556095 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078 +vmla.i32 d0, d1, d4[0] :: Qd 0x4a0991fd 0xd3eb73dd Qm (i32)0x00000018 Qn (i32)0x00000078 +vmla.i32 d31, d8, d7[1] :: Qd 0x555513b5 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmla.i32 d31, d8, d7[1] :: Qd 0x60a118ad 0xd6bf36cd Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmla.i16 d30, d9, d7[3] :: Qd 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmla.i16 d30, d9, d7[3] :: Qd 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmla.i16 d4, d5, d6[2] :: Qd 0x5555f557 0x5555f557 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmla.i16 d4, d5, d6[2] :: Qd 0xdb8be98b 0x59937193 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmla.i32 d4, d8, d15[1] :: Qd 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i32 d4, d8, d15[1] :: Qd 0xfb8b898b 0xf9939193 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i16 d4, d5, d6[0] :: Qd 0x3553ddbb 0x3553ddbb Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmla.i16 d4, d5, d6[0] :: Qd 0xdb8be98b 0x59937193 Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmla.i32 d7, d8, d1[1] :: Qd 0x55555555 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmla.i32 d7, d8, d1[1] :: Qd 0x73de8e99 0x983ebec9 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmla.i16 d4, d5, d6[0] :: Qd 0x75551751 0x75551751 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmla.i16 d4, d5, d6[0] :: Qd 0xdb8be98b 0x59937193 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmla.i32 d7, d8, d1[1] :: Qd 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.i32 d7, d8, d1[1] :: Qd 0xfb8b898b 0xf9939193 Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VMLS (by scalar) ---- +vmls.i32 d0, d1, d4[0] :: Qd 0x5555557d 0x5555557d Qm (i32)0x00000018 Qn (i32)0x00000078 +vmls.i32 d0, d1, d4[0] :: Qd 0x5555557d 0x5555557d Qm (i32)0x00000018 Qn (i32)0x00000078 +vmls.i32 d31, d8, d7[1] :: Qd 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmls.i32 d31, d8, d7[1] :: Qd 0x4a0991fd 0xd3eb73dd Qm (i32)0x0000008c Qn (i32)0xffffff88 +vmls.i16 d30, d9, d7[3] :: Qd 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmls.i16 d30, d9, d7[3] :: Qd 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120 +vmls.i16 d4, d5, d6[2] :: Qd 0x5555b553 0x5555b553 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmls.i16 d4, d5, d6[2] :: Qd 0xcf1fc11f 0x51173917 Qm (i32)0x00004001 Qn (i32)0x00002002 +vmls.i32 d4, d8, d15[1] :: Qd 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i32 d4, d8, d15[1] :: Qd 0xaf1f211f 0xb1171917 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i16 d4, d5, d6[0] :: Qd 0x7557ccef 0x7557ccef Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmls.i16 d4, d5, d6[0] :: Qd 0xcf1fc11f 0x51173917 Qm (i32)0xffff9433 Qn (i32)0x00002002 +vmls.i32 d7, d8, d1[1] :: Qd 0x55555555 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmls.i32 d7, d8, d1[1] :: Qd 0x36cc1c11 0x126bebe1 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmls.i16 d4, d5, d6[0] :: Qd 0x35559359 0x35559359 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmls.i16 d4, d5, d6[0] :: Qd 0xcf1fc11f 0x51173917 Qm (i32)0x100000fe Qn (i32)0x00002002 +vmls.i32 d7, d8, d1[1] :: Qd 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.i32 d7, d8, d1[1] :: Qd 0xaf1f211f 0xb1171917 Qm (i32)0x80000001 Qn (i32)0x80000002 +---- VRSHR ---- +vrshr.s8 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vrshr.s8 d0, d1, #0 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xffffffff +vrshr.s8 d0, d1, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshr.s8 d0, d1, #1 :: Qd 0x0b0f0d0f 0x0a0e100e Qm (i32)0xffffffff +vrshr.s16 d3, d4, #2 :: Qd 0x0000ffe1 0x0000ffe1 Qm (i32)0xffffff84 +vrshr.s16 d3, d4, #2 :: Qd 0x05470647 0x050707c7 Qm (i32)0xffffff84 +vrshr.s32 d2, d5, #31 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshr.s32 d2, d5, #31 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshr.s8 d6, d7, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000ffff +vrshr.s8 d6, d7, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000ffff +vrshr.s16 d8, d9, #12 :: Qd 0x00000000 0x00000000 Qm (i32)0xfffffff6 +vrshr.s16 d8, d9, #12 :: Qd 0x00010002 0x00010002 Qm (i32)0xfffffff6 +vrshr.s32 d10, d11, #5 :: Qd 0x00000140 0x00000140 Qm (i32)0x000027fa +vrshr.s32 d10, d11, #5 :: Qd 0x00a8e8c9 0x00a0e0f9 Qm (i32)0x000027fa +vrshr.u8 d12, d13, #1 :: Qd 0x80808080 0x80808080 Qm (i32)0xffffffff +vrshr.u8 d12, d13, #1 :: Qd 0x0b0f0d0f 0x0a0e100e Qm (i32)0xffffffff +vrshr.u16 d14, d15, #11 :: Qd 0x00200020 0x00200020 Qm (i32)0xffffffff +vrshr.u16 d14, d15, #11 :: Qd 0x00030003 0x00030004 Qm (i32)0xffffffff +vrshr.u32 d10, d11, #9 :: Qd 0x00000002 0x00000002 Qm (i32)0x000003e8 +vrshr.u32 d10, d11, #9 :: Qd 0x000a8e8d 0x000a0e10 Qm (i32)0x000003e8 +vrshr.u8 d7, d13, #7 :: Qd 0x02020202 0x02020202 Qm (i32)0xffffffff +vrshr.u8 d7, d13, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshr.u16 d8, d1, #5 :: Qd 0x0000055e 0x0000055e Qm (i32)0x0000abcf +vrshr.u16 d8, d1, #5 :: Qd 0x00a900c9 0x00a100f9 Qm (i32)0x0000abcf +vrshr.u32 d12, d3, #15 :: Qd 0x00020000 0x00020000 Qm (i32)0xfffffe50 +vrshr.u32 d12, d3, #15 :: Qd 0x00002a3a 0x00002838 Qm (i32)0xfffffe50 +vrshr.u64 d0, d1, #42 :: Qd 0x00000000 0x00400000 Qm (i32)0xffffffff +vrshr.u64 d0, d1, #42 :: Qd 0x00000000 0x00054746 Qm (i32)0xffffffff +vrshr.s64 d6, d7, #12 :: Qd 0x00000000 0xfac00001 Qm (i32)0x00000fac +vrshr.s64 d6, d7, #12 :: Qd 0x000151d1 0x91d141c2 Qm (i32)0x00000fac +vrshr.u64 d8, d4, #9 :: Qd 0x0000001a 0x7c00001a Qm (i32)0x000034f8 +vrshr.u64 d8, d4, #9 :: Qd 0x000a8e8c 0x8e8a0e10 Qm (i32)0x000034f8 +vrshr.s64 d9, d12, #11 :: Qd 0x00000030 0x32c00030 Qm (i32)0x00018196 +vrshr.s64 d9, d12, #11 :: Qd 0x0002a3a3 0x23a28384 Qm (i32)0x00018196 +---- VRSRA ---- +vrsra.s8 d0, d1, #1 :: Qd 0x55555555 0x55555555 Qm (i32)0xffffffff +vrsra.s8 d0, d1, #1 :: Qd 0x1e2a272a 0x1c2d2e2d Qm (i32)0xffffffff +vrsra.s16 d3, d4, #2 :: Qd 0x55555536 0x55555536 Qm (i32)0xffffff84 +vrsra.s16 d3, d4, #2 :: Qd 0x18622062 0x172625e6 Qm (i32)0xffffff84 +vrsra.s32 d2, d5, #31 :: Qd 0x55555555 0x55555555 Qm (i32)0xffffffff +vrsra.s32 d2, d5, #31 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff +vrsra.s8 d6, d7, #7 :: Qd 0x55555555 0x55555555 Qm (i32)0x0000ffff +vrsra.s8 d6, d7, #7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x0000ffff +vrsra.s16 d8, d9, #12 :: Qd 0x55555555 0x55555555 Qm (i32)0xfffffff6 +vrsra.s16 d8, d9, #12 :: Qd 0x131c1a1d 0x12201e21 Qm (i32)0xfffffff6 +vrsra.s32 d10, d11, #5 :: Qd 0x55555695 0x55555695 Qm (i32)0x000027fa +vrsra.s32 d10, d11, #5 :: Qd 0x13c402e4 0x12bfff18 Qm (i32)0x000027fa +vrsra.u8 d12, d13, #1 :: Qd 0xd5d5d5d5 0xd5d5d5d5 Qm (i32)0xffffffff +vrsra.u8 d12, d13, #1 :: Qd 0x1e2a272a 0x1c2d2e2d Qm (i32)0xffffffff +vrsra.u16 d14, d15, #11 :: Qd 0x55755575 0x55755575 Qm (i32)0xffffffff +vrsra.u16 d14, d15, #11 :: Qd 0x131e1a1e 0x12221e23 Qm (i32)0xffffffff +vrsra.u32 d10, d11, #9 :: Qd 0x55555557 0x55555557 Qm (i32)0x000003e8 +vrsra.u32 d10, d11, #9 :: Qd 0x1325a8a8 0x12292c2f Qm (i32)0x000003e8 +vrsra.u8 d7, d13, #7 :: Qd 0x57575757 0x57575757 Qm (i32)0xffffffff +vrsra.u8 d7, d13, #7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff +vrsra.u16 d8, d1, #5 :: Qd 0x55555ab3 0x55555ab3 Qm (i32)0x0000abcf +vrsra.u16 d8, d1, #5 :: Qd 0x13c41ae4 0x12c01f18 Qm (i32)0x0000abcf +vrsra.u32 d12, d3, #15 :: Qd 0x55575555 0x55575555 Qm (i32)0xfffffe50 +vrsra.u32 d12, d3, #15 :: Qd 0x131b4455 0x121f4657 Qm (i32)0xfffffe50 +vrsra.u64 d0, d1, #42 :: Qd 0x55555555 0x55955555 Qm (i32)0xffffffff +vrsra.u64 d0, d1, #42 :: Qd 0x131b1a1b 0x12246565 Qm (i32)0xffffffff +vrsra.s64 d6, d7, #12 :: Qd 0x55555556 0x50155556 Qm (i32)0x00000fac +vrsra.s64 d6, d7, #12 :: Qd 0x131c6bec 0xa3f05fe1 Qm (i32)0x00000fac +vrsra.u64 d8, d4, #9 :: Qd 0x5555556f 0xd155556f Qm (i32)0x000034f8 +vrsra.u64 d8, d4, #9 :: Qd 0x1325a8a7 0xa0a92c2f Qm (i32)0x000034f8 +vrsra.s64 d9, d12, #11 :: Qd 0x55555585 0x88155585 Qm (i32)0x00018196 +vrsra.s64 d9, d12, #11 :: Qd 0x131dbdbe 0x35c1a1a3 Qm (i32)0x00018196 +---- VSHR ---- +vshr.s8 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshr.s8 d0, d1, #0 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xffffffff +vshr.s8 d0, d1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshr.s8 d0, d1, #1 :: Qd 0x0a0e0c0e 0x0a0e0f0e Qm (i32)0xffffffff +vshr.s16 d3, d4, #2 :: Qd 0xffffffe1 0xffffffe1 Qm (i32)0xffffff84 +vshr.s16 d3, d4, #2 :: Qd 0x05470647 0x050707c7 Qm (i32)0xffffff84 +vshr.s32 d2, d5, #31 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshr.s32 d2, d5, #31 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff +vshr.s8 d6, d7, #7 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x0000ffff +vshr.s8 d6, d7, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000ffff +vshr.s16 d8, d9, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffff6 +vshr.s16 d8, d9, #12 :: Qd 0x00010001 0x00010001 Qm (i32)0xfffffff6 +vshr.s32 d10, d11, #5 :: Qd 0x0000013f 0x0000013f Qm (i32)0x000027fa +vshr.s32 d10, d11, #5 :: Qd 0x00a8e8c8 0x00a0e0f8 Qm (i32)0x000027fa +vshr.u8 d12, d13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff +vshr.u8 d12, d13, #1 :: Qd 0x0a0e0c0e 0x0a0e0f0e Qm (i32)0xffffffff +vshr.u16 d14, d15, #11 :: Qd 0x001f001f 0x001f001f Qm (i32)0xffffffff +vshr.u16 d14, d15, #11 :: Qd 0x00020003 0x00020003 Qm (i32)0xffffffff +vshr.u32 d10, d11, #9 :: Qd 0x00000001 0x00000001 Qm (i32)0x000003e8 +vshr.u32 d10, d11, #9 :: Qd 0x000a8e8c 0x000a0e0f Qm (i32)0x000003e8 +vshr.u8 d7, d13, #7 :: Qd 0x01010101 0x01010101 Qm (i32)0xffffffff +vshr.u8 d7, d13, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff +vshr.u16 d8, d1, #5 :: Qd 0x0000055e 0x0000055e Qm (i32)0x0000abcf +vshr.u16 d8, d1, #5 :: Qd 0x00a800c8 0x00a000f8 Qm (i32)0x0000abcf +vshr.u32 d12, d3, #15 :: Qd 0x0001ffff 0x0001ffff Qm (i32)0xfffffe50 +vshr.u32 d12, d3, #15 :: Qd 0x00002a3a 0x00002838 Qm (i32)0xfffffe50 +vshr.u64 d0, d1, #42 :: Qd 0x00000000 0x003fffff Qm (i32)0xffffffff +vshr.u64 d0, d1, #42 :: Qd 0x00000000 0x00054746 Qm (i32)0xffffffff +vshr.s64 d6, d7, #12 :: Qd 0x00000000 0xfac00000 Qm (i32)0x00000fac +vshr.s64 d6, d7, #12 :: Qd 0x000151d1 0x91d141c1 Qm (i32)0x00000fac +vshr.u64 d8, d4, #9 :: Qd 0x0000001a 0x7c00001a Qm (i32)0x000034f8 +vshr.u64 d8, d4, #9 :: Qd 0x000a8e8c 0x8e8a0e0f Qm (i32)0x000034f8 +vshr.s64 d9, d12, #11 :: Qd 0x00000030 0x32c00030 Qm (i32)0x00018196 +vshr.s64 d9, d12, #11 :: Qd 0x0002a3a3 0x23a28383 Qm (i32)0x00018196 +---- VSRA ---- +vsra.s8 d0, d1, #1 :: Qd 0x54545454 0x54545454 Qm (i32)0xffffffff +vsra.s8 d0, d1, #1 :: Qd 0x1d292629 0x1c2d2d2d Qm (i32)0xffffffff +vsra.s16 d3, d4, #2 :: Qd 0x55545536 0x55545536 Qm (i32)0xffffff84 +vsra.s16 d3, d4, #2 :: Qd 0x18622062 0x172625e6 Qm (i32)0xffffff84 +vsra.s32 d2, d5, #31 :: Qd 0x55555554 0x55555554 Qm (i32)0xffffffff +vsra.s32 d2, d5, #31 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff +vsra.s8 d6, d7, #7 :: Qd 0x55555454 0x55555454 Qm (i32)0x0000ffff +vsra.s8 d6, d7, #7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x0000ffff +vsra.s16 d8, d9, #12 :: Qd 0x55545554 0x55545554 Qm (i32)0xfffffff6 +vsra.s16 d8, d9, #12 :: Qd 0x131c1a1c 0x12201e20 Qm (i32)0xfffffff6 +vsra.s32 d10, d11, #5 :: Qd 0x55555694 0x55555694 Qm (i32)0x000027fa +vsra.s32 d10, d11, #5 :: Qd 0x13c402e3 0x12bfff17 Qm (i32)0x000027fa +vsra.u8 d12, d13, #1 :: Qd 0xd4d4d4d4 0xd4d4d4d4 Qm (i32)0xffffffff +vsra.u8 d12, d13, #1 :: Qd 0x1d292629 0x1c2d2d2d Qm (i32)0xffffffff +vsra.u16 d14, d15, #11 :: Qd 0x55745574 0x55745574 Qm (i32)0xffffffff +vsra.u16 d14, d15, #11 :: Qd 0x131d1a1e 0x12211e22 Qm (i32)0xffffffff +vsra.u32 d10, d11, #9 :: Qd 0x55555556 0x55555556 Qm (i32)0x000003e8 +vsra.u32 d10, d11, #9 :: Qd 0x1325a8a7 0x12292c2e Qm (i32)0x000003e8 +vsra.u8 d7, d13, #7 :: Qd 0x56565656 0x56565656 Qm (i32)0xffffffff +vsra.u8 d7, d13, #7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xffffffff +vsra.u16 d8, d1, #5 :: Qd 0x55555ab3 0x55555ab3 Qm (i32)0x0000abcf +vsra.u16 d8, d1, #5 :: Qd 0x13c31ae3 0x12bf1f17 Qm (i32)0x0000abcf +vsra.u32 d12, d3, #15 :: Qd 0x55575554 0x55575554 Qm (i32)0xfffffe50 +vsra.u32 d12, d3, #15 :: Qd 0x131b4455 0x121f4657 Qm (i32)0xfffffe50 +vsra.u64 d0, d1, #42 :: Qd 0x55555555 0x55955554 Qm (i32)0xffffffff +vsra.u64 d0, d1, #42 :: Qd 0x131b1a1b 0x12246565 Qm (i32)0xffffffff +vsra.s64 d6, d7, #12 :: Qd 0x55555556 0x50155555 Qm (i32)0x00000fac +vsra.s64 d6, d7, #12 :: Qd 0x131c6bec 0xa3f05fe0 Qm (i32)0x00000fac +vsra.u64 d8, d4, #9 :: Qd 0x5555556f 0xd155556f Qm (i32)0x000034f8 +vsra.u64 d8, d4, #9 :: Qd 0x1325a8a7 0xa0a92c2e Qm (i32)0x000034f8 +vsra.s64 d9, d12, #11 :: Qd 0x55555585 0x88155585 Qm (i32)0x00018196 +vsra.s64 d9, d12, #11 :: Qd 0x131dbdbe 0x35c1a1a2 Qm (i32)0x00018196 +---- VSRI ---- +vsri.16 d0, d1, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff +vsri.16 d0, d1, #1 :: Qd 0x0a8e0c8e 0x0a0e0f8e Qm (i32)0xffffffff +vsri.16 d3, d4, #2 :: Qd 0x7fff7fe1 0x7fff7fe1 Qm (i32)0xffffff84 +vsri.16 d3, d4, #2 :: Qd 0x05470647 0x050707c7 Qm (i32)0xffffff84 +vsri.32 d2, d5, #31 :: Qd 0x55555555 0x55555555 Qm (i32)0xffffffff +vsri.32 d2, d5, #31 :: Qd 0x131b1a1a 0x121f1e1e Qm (i32)0xffffffff +vsri.8 d6, d7, #7 :: Qd 0x54545555 0x54545555 Qm (i32)0x0000ffff +vsri.8 d6, d7, #7 :: Qd 0x121a1a1a 0x121e1e1e Qm (i32)0x0000ffff +vsri.16 d8, d9, #12 :: Qd 0x555f555f 0x555f555f Qm (i32)0xfffffff6 +vsri.16 d8, d9, #12 :: Qd 0x13111a11 0x12111e11 Qm (i32)0xfffffff6 +vsri.32 d10, d11, #5 :: Qd 0x5000013f 0x5000013f Qm (i32)0x000027fa +vsri.32 d10, d11, #5 :: Qd 0x10a8e8c8 0x10a0e0f8 Qm (i32)0x000027fa +vsri.8 d12, d13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff +vsri.8 d12, d13, #1 :: Qd 0x0a0e0c0e 0x0a0e0f0e Qm (i32)0xffffffff +vsri.16 d14, d15, #11 :: Qd 0x555f555f 0x555f555f Qm (i32)0xffffffff +vsri.16 d14, d15, #11 :: Qd 0x13021a03 0x12021e03 Qm (i32)0xffffffff +vsri.32 d10, d11, #9 :: Qd 0x55000001 0x55000001 Qm (i32)0x000003e8 +vsri.32 d10, d11, #9 :: Qd 0x130a8e8c 0x120a0e0f Qm (i32)0x000003e8 +vsri.8 d7, d13, #7 :: Qd 0x55555555 0x55555555 Qm (i32)0xffffffff +vsri.8 d7, d13, #7 :: Qd 0x121a1a1a 0x121e1e1e Qm (i32)0xffffffff +vsri.16 d8, d1, #5 :: Qd 0x5000555e 0x5000555e Qm (i32)0x0000abcf +vsri.16 d8, d1, #5 :: Qd 0x10a818c8 0x10a018f8 Qm (i32)0x0000abcf +vsri.32 d12, d3, #15 :: Qd 0x5555ffff 0x5555ffff Qm (i32)0xfffffe50 +vsri.32 d12, d3, #15 :: Qd 0x131a2a3a 0x121e2838 Qm (i32)0xfffffe50 +vsri.64 d0, d1, #42 :: Qd 0x55555555 0x557fffff Qm (i32)0xffffffff +vsri.64 d0, d1, #42 :: Qd 0x131b1a1b 0x12054746 Qm (i32)0xffffffff +vsri.64 d6, d7, #12 :: Qd 0x55500000 0xfac00000 Qm (i32)0x00000fac +vsri.64 d6, d7, #12 :: Qd 0x131151d1 0x91d141c1 Qm (i32)0x00000fac +vsri.64 d8, d4, #9 :: Qd 0x5500001a 0x7c00001a Qm (i32)0x000034f8 +vsri.64 d8, d4, #9 :: Qd 0x130a8e8c 0x8e8a0e0f Qm (i32)0x000034f8 +vsri.64 d9, d12, #11 :: Qd 0x55400030 0x32c00030 Qm (i32)0x00018196 +vsri.64 d9, d12, #11 :: Qd 0x1302a3a3 0x23a28383 Qm (i32)0x00018196 +---- VMOV (ARM core register to scalar) ---- +vmov.32 d0[0], r5 :: Qd 0x55555555 0x0000000d Qm 0x0000000d +vmov.32 d1[1], r3 :: Qd 0x0000000c 0x55555555 Qm 0x0000000c +vmov.16 d0[0], r5 :: Qd 0x55555555 0x5555000d Qm 0x0000000d +vmov.16 d2[2], r6 :: Qd 0x5555000e 0x55555555 Qm 0x0000000e +vmov.16 d3[3], r1 :: Qd 0x00115555 0x55555555 Qm 0x00000011 +vmov.8 d0[0], r5 :: Qd 0x55555555 0x5555550d Qm 0x0000000d +vmov.8 d0[1], r5 :: Qd 0x55555555 0x55550d55 Qm 0x0000000d +vmov.8 d0[2], r5 :: Qd 0x55555555 0x550d5555 Qm 0x0000000d +vmov.8 d0[3], r5 :: Qd 0x55555555 0x0d555555 Qm 0x0000000d +vmov.8 d0[4], r5 :: Qd 0x5555550d 0x55555555 Qm 0x0000000d +vmov.8 d0[5], r5 :: Qd 0x55550d55 0x55555555 Qm 0x0000000d +vmov.8 d0[6], r5 :: Qd 0x550d5555 0x55555555 Qm 0x0000000d +vmov.8 d31[7], r5 :: Qd 0x0d555555 0x55555555 Qm 0x0000000d +---- VMOV (scalar toARM core register) ---- +vmov.32 r5, d0[0] :: Rd 0x11223344 Qm (i32)0x11223344 +vmov.32 r6, d5[1] :: Rd 0x11223344 Qm (i32)0x11223344 +vmov.u16 r5, d31[0] :: Rd 0x00003344 Qm (i32)0x11223344 +vmov.u16 r5, d30[1] :: Rd 0x00001122 Qm (i32)0x11223344 +vmov.u16 r5, d31[2] :: Rd 0x00003344 Qm (i32)0x11223344 +vmov.u16 r5, d31[3] :: Rd 0x00001122 Qm (i32)0x11223344 +vmov.u8 r2, d4[0] :: Rd 0x00000044 Qm (i32)0x11223344 +vmov.u8 r2, d4[1] :: Rd 0x00000033 Qm (i32)0x11223344 +vmov.u8 r2, d4[2] :: Rd 0x00000022 Qm (i32)0x11223344 +vmov.u8 r2, d4[3] :: Rd 0x00000011 Qm (i32)0x11223344 +vmov.u8 r2, d4[4] :: Rd 0x00000044 Qm (i32)0x11223344 +vmov.u8 r2, d4[5] :: Rd 0x00000033 Qm (i32)0x11223344 +vmov.u8 r2, d4[6] :: Rd 0x00000022 Qm (i32)0x11223344 +vmov.u8 r2, d4[7] :: Rd 0x00000011 Qm (i32)0x11223344 +vmov.s16 r5, d31[0] :: Rd 0xffff8080 Qm (i8)0x00000080 +vmov.s16 r5, d30[1] :: Rd 0xffff8080 Qm (i8)0x00000080 +vmov.s16 r5, d31[2] :: Rd 0xffff8080 Qm (i8)0x00000080 +vmov.s16 r5, d31[3] :: Rd 0xffff8080 Qm (i8)0x00000080 +vmov.s8 r2, d4[0] :: Rd 0xffffff80 Qm (i8)0x00000080 +vmov.s8 r2, d4[1] :: Rd 0xffffff80 Qm (i8)0x00000080 +vmov.s8 r2, d4[2] :: Rd 0xffffff80 Qm (i8)0x00000080 +vmov.s8 r2, d4[3] :: Rd 0xffffff80 Qm (i8)0x00000080 +vmov.s8 r2, d4[4] :: Rd 0xffffff80 Qm (i8)0x00000080 +vmov.s8 r2, d4[5] :: Rd 0xffffff82 Qm (i8)0x00000082 +vmov.s8 r2, d4[6] :: Rd 0xffffff81 Qm (i8)0x00000081 +vmov.s8 r2, d4[7] :: Rd 0xffffff83 Qm (i8)0x00000083 +---- VLD1 (multiple single elements) ---- +vld1.8 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.16 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.32 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.64 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.8 {d9} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.16 {d17} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.32 {d31} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.64 {d14} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.8 {d0-d1} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 0 +vld1.16 {d0-d1} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 0 +vld1.32 {d5-d6} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 0 +vld1.64 {d30-d31} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 0 +vld1.8 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 0 +vld1.16 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 0 +vld1.32 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 0 +vld1.64 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 0 +vld1.8 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vld1.16 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vld1.32 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vld1.64 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +---- VLD1 (single element to one lane) ---- +vld1.32 {d0[0]} :: Result 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 delta 0 +vld1.32 {d0[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f delta 0 +vld1.16 {d1[0]} :: Result 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 delta 0 +vld1.16 {d1[1]} :: Result 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 delta 0 +vld1.16 {d1[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f delta 0 +vld1.16 {d1[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 delta 0 +vld1.8 {d0[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 delta 0 +vld1.8 {d1[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 delta 0 +vld1.8 {d0[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 delta 0 +vld1.8 {d0[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f delta 0 +vld1.8 {d20[3]} :: Result 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 delta 0 +vld1.8 {d0[2]} :: Result 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 delta 0 +vld1.8 {d17[1]} :: Result 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 delta 0 +vld1.8 {d30[0]} :: Result 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 delta 0 +---- VLD1 (single element to all lanes) ---- +vld1.8 {d0[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 0 +vld1.16 {d0[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 0 +vld1.32 {d0[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 0 +vld1.8 {d9[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 0 +vld1.16 {d17[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 0 +vld1.32 {d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 0 +vld1.8 {d0[],d1[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 0 +vld1.16 {d0[],d1[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 0 +vld1.32 {d5[],d6[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 0 +---- VLD2 (multiple 2-elements) ---- +vld2.8 {d30-d31} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f delta 0 +vld2.16 {d0-d1} :: Result 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c delta 0 +vld2.32 {d0-d1} :: Result 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d delta 0 +vld2.8 {d10,d12} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f delta 0 +vld2.16 {d20,d22} :: Result 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c delta 0 +vld2.32 {d0,d2} :: Result 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d delta 0 +vld2.8 {d0-d3} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x2c2b2f2f 0x2d2a2a2b 0x131a121e 0x1519141f 0x242b232e 0x262d252e delta 0 +vld2.16 {d20-d23} :: Result 0x1a1b1e1f 0x191d1f1c 0x2b2b2e2f 0x2d2a2e2b 0x131b121f 0x151d141c 0x242c232f 0x262d252a delta 0 +vld2.32 {d0-d3} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 0 +---- VLD2 (single 2-element structure to one lane) ---- +vld2.32 {d0[0],d1[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 delta 0 +vld2.32 {d0[1],d1[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b delta 0 +vld2.32 {d0[0],d2[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 delta 0 +vld2.32 {d0[1],d2[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b delta 0 +vld2.16 {d1[0],d2[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 delta 0 +vld2.16 {d1[1],d2[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 delta 0 +vld2.16 {d1[2],d2[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f delta 0 +vld2.16 {d1[3],d2[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 delta 0 +vld2.16 {d1[0],d3[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 delta 0 +vld2.16 {d1[1],d3[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 delta 0 +vld2.16 {d1[2],d3[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f delta 0 +vld2.16 {d1[3],d3[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 delta 0 +vld2.8 {d0[7],d1[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 delta 0 +vld2.8 {d1[6],d2[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 delta 0 +vld2.8 {d0[5],d1[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 delta 0 +vld2.8 {d0[4],d1[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e delta 0 +vld2.8 {d20[3],d21[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 delta 0 +vld2.8 {d0[2],d1[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 delta 0 +vld2.8 {d17[1],d18[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 delta 0 +vld2.8 {d30[0],d31[0]} :: Result 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 delta 0 +---- VLD2 (2-elements to all lanes) ---- +vld2.8 {d0[],d1[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld2.16 {d0[],d1[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 0 +vld2.32 {d0[],d1[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 0 +vld2.8 {d9[],d11[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld2.16 {d17[],d18[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 0 +vld2.32 {d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 0 +vld2.8 {d0[],d2[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld2.16 {d0[],d2[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 0 +vld2.32 {d5[],d7[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 0 +---- VLD3 (multiple 3-elements) ---- +vld3.8 {d20-d22} :: Result 0x1f1b121f 0x2b2f151d 0x1c131b1e 0x2c232f19 0x141c1a1f 0x242b2e1d 0x1f1b121f 0x2b2f151d delta 0 +vld3.16 {d0-d2} :: Result 0x131b1e1f 0x232f191d 0x1f1c121f 0x2b2b151d 0x141c1a1b 0x242c2e2f 0x131b1e1f 0x232f191d delta 0 +vld3.32 {d0-d2} :: Result 0x121f1e1f 0x151d191d 0x131b1a1b 0x232f2e2f 0x141c1f1c 0x242c2b2b 0x121f1e1f 0x151d191d delta 0 +vld3.8 {d0,d2,d4} :: Result 0x1f1b121f 0x2b2f151d 0x1c131b1e 0x2c232f19 0x141c1a1f 0x242b2e1d 0x1f1b121f 0x2b2f151d delta 0 +vld3.16 {d20,d22,d24} :: Result 0x131b1e1f 0x232f191d 0x1f1c121f 0x2b2b151d 0x141c1a1b 0x242c2e2f 0x131b1e1f 0x232f191d delta 0 +vld3.32 {d0,d2,d4} :: Result 0x121f1e1f 0x151d191d 0x131b1a1b 0x232f2e2f 0x141c1f1c 0x242c2b2b 0x121f1e1f 0x151d191d delta 0 +---- VLD3 (single 3-element structure to one lane) ---- +vld3.32 {d0[0],d1[0],d2[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b 0x55555555 delta 0 +vld3.32 {d0[1],d1[1],d2[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b delta 0 +vld3.32 {d0[0],d2[0],d4[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b 0x55555555 delta 0 +vld3.32 {d0[1],d2[1],d4[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b delta 0 +vld3.16 {d1[0],d2[0],d3[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555121f 0x55555555 delta 0 +vld3.16 {d1[1],d2[1],d3[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x121f5555 0x55555555 delta 0 +vld3.16 {d1[2],d2[2],d3[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555121f delta 0 +vld3.16 {d1[3],d2[3],d3[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x121f5555 delta 0 +vld3.16 {d1[0],d3[0],d5[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 delta 0 +vld3.16 {d1[1],d3[1],d5[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 delta 0 +vld3.16 {d1[2],d3[2],d5[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x5555121f 0x55555555 0x55551a1b delta 0 +vld3.16 {d1[3],d3[3],d5[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 delta 0 +vld3.8 {d0[7],d1[7],d2[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 delta 0 +vld3.8 {d1[6],d2[6],d3[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 delta 0 +vld3.8 {d0[5],d1[5],d2[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 delta 0 +vld3.8 {d0[4],d1[4],d2[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e delta 0 +vld3.8 {d20[3],d21[3],d22[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 delta 0 +vld3.8 {d0[2],d1[2],d2[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 delta 0 +vld3.8 {d17[1],d18[1],d19[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 delta 0 +vld3.8 {d29[0],d30[0],d31[0]} :: Result 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 delta 0 +---- VLD3 (3-elements to all lanes) ---- +vld3.8 {d0[],d1[],d2[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld3.16 {d0[],d1[],d2[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 0 +vld3.32 {d0[],d1[],d2[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x131b1a1b 0x131b1a1b delta 0 +vld3.8 {d9[],d11[],d13[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld3.16 {d17[],d18[],d19[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 0 +vld3.32 {d29[],d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c delta 0 +vld3.8 {d0[],d2[],d4[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld3.16 {d0[],d2[],d4[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 0 +vld3.32 {d5[],d7[],d9[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x131b1a1b 0x131b1a1b delta 0 +---- VLD4 (multiple 3-elements) ---- +vld4.8 {d0-d3} :: Result 0x1d1c1b1f 0x2a2b2b2f 0x191f1a1e 0x2d2e2b2e 0x1d1c1b1f 0x2d2a2c2f 0x15141312 0x26252423 delta 0 +vld4.16 {d20-d23} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 0 +vld4.32 {d0-d3} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 0 +vld4.8 {d0,d2,d4,d6} :: Result 0x1d1c1b1f 0x2a2b2b2f 0x191f1a1e 0x2d2e2b2e 0x1d1c1b1f 0x2d2a2c2f 0x15141312 0x26252423 delta 0 +vld4.16 {d1,d3,d5,d7} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 0 +vld4.32 {d20,d22,d24,d26} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 0 +---- VLD4 (single 4-element structure to one lane) ---- +vld4.32 {d0[0],d1[0],d2[0],d3[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d 0x55555555 delta 0 +vld4.32 {d0[1],d1[1],d2[1],d3[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x55555555 delta 0 +vld4.32 {d0[0],d2[0],d4[0],d6[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d 0x55555555 delta 0 +vld4.32 {d0[1],d2[1],d4[1],d6[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d delta 0 +vld4.16 {d1[0],d2[0],d3[0],d4[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b 0x55555555 delta 0 +vld4.16 {d1[1],d2[1],d3[1],d4[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 0x55555555 delta 0 +vld4.16 {d1[2],d2[2],d3[2],d4[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b delta 0 +vld4.16 {d1[3],d2[3],d3[3],d4[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 delta 0 +vld4.16 {d1[0],d3[0],d5[0],d7[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b 0x55555555 delta 0 +vld4.16 {d1[1],d3[1],d5[1],d7[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 0x55555555 delta 0 +vld4.16 {d1[2],d3[2],d5[2],d7[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b delta 0 +vld4.16 {d1[3],d3[3],d5[3],d7[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 delta 0 +vld4.8 {d0[7],d1[7],d2[7],d3[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x12555555 delta 0 +vld4.8 {d1[6],d2[6],d3[6],d4[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x55125555 delta 0 +vld4.8 {d0[5],d1[5],d2[5],d3[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551255 delta 0 +vld4.8 {d0[4],d1[4],d2[4],d3[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x55555512 delta 0 +vld4.8 {d20[3],d21[3],d22[3],d23[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x12555555 0x55555555 delta 0 +vld4.8 {d0[2],d1[2],d2[2],d3[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x55125555 0x55555555 delta 0 +vld4.8 {d17[1],d18[1],d19[1],d20[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551255 0x55555555 delta 0 +vld4.8 {d28[0],d29[0],d30[0],d31[0]} :: Result 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x55555512 0x55555555 delta 0 +---- VLD4 (4-elements to all lanes) ---- +vld4.8 {d0[],d1[],d2[],d3[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 0 +vld4.16 {d0[],d1[],d2[],d3[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 0 +vld4.32 {d0[],d1[],d2[],d3[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 0 +vld4.8 {d9[],d11[],d13[],d15[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 0 +vld4.16 {d17[],d18[],d19[],d20[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 0 +vld4.32 {d28[],d29[],d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 0 +vld4.8 {d0[],d2[],d4[],d6[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 0 +vld4.16 {d0[],d2[],d4[],d6[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 0 +vld4.32 {d5[],d7[],d9[],d11[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 0 +---- VST1 (multiple single elements) ---- +vst1.8 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.16 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.32 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.64 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d9} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.16 {d17} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.32 {d31} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.64 {d14} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d0-d1} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.16 {d0-d1} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.32 {d5-d6} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.64 {d30-d31} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 0 +vst1.16 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 0 +vst1.32 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 0 +vst1.64 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 0 +vst1.8 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vst1.16 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vst1.32 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vst1.64 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +---- VST1 (single element from one lane) ---- +vst1.32 {d0[0]} :: Result 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.32 {d0[1]} :: Result 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.16 {d1[0]} :: Result 0x55552e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.16 {d1[1]} :: Result 0x5555252a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.16 {d1[2]} :: Result 0x55552d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.16 {d1[3]} :: Result 0x5555262d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d0[7]} :: Result 0x55555526 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d1[6]} :: Result 0x5555552d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d0[5]} :: Result 0x5555552d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d0[4]} :: Result 0x5555552a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d20[3]} :: Result 0x55555525 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d0[2]} :: Result 0x5555552a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d17[1]} :: Result 0x5555552e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst1.8 {d30[0]} :: Result 0x5555552b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +---- VST2 (multiple 2-elements) ---- +vst2.8 {d30-d31} :: Result 0x2e2e2b2f 0x25232a2f 0x2d2b2a2b 0x26242d2c 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d0-d1} :: Result 0x2e2b2e2f 0x252a232f 0x2d2a2b2b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.32 {d0-d1} :: Result 0x232f2e2f 0x252a2e2b 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d10,d12} :: Result 0x2e2e2b2f 0x25232a2f 0x2d2b2a2b 0x26242d2c 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d20,d22} :: Result 0x2e2b2e2f 0x252a232f 0x2d2a2b2b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.32 {d0,d2} :: Result 0x232f2e2f 0x252a2e2b 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d0-d3} :: Result 0x2e1e2f1f 0x23122f1f 0x2b1a2b1b 0x24132c1b 0x2e1f2b1c 0x25142a1c 0x2d192a1d 0x26152d1d delta 0 +vst2.16 {d20-d23} :: Result 0x2e2f1e1f 0x232f121f 0x2b2b1a1b 0x242c131b 0x2e2b1f1c 0x252a141c 0x2d2a191d 0x262d151d delta 0 +vst2.32 {d0-d3} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 0 +---- VST2 (single 2-element structure from one lane) ---- +vst2.32 {d0[0],d1[0]} :: Result 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.32 {d0[1],d1[1]} :: Result 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.32 {d0[0],d2[0]} :: Result 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.32 {d0[1],d2[1]} :: Result 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d1[0],d2[0]} :: Result 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d1[1],d2[1]} :: Result 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d1[2],d2[2]} :: Result 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d1[3],d2[3]} :: Result 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d1[0],d3[0]} :: Result 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d1[1],d3[1]} :: Result 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d1[2],d3[2]} :: Result 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.16 {d1[3],d3[3]} :: Result 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d0[7],d1[7]} :: Result 0x55552624 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d1[6],d2[6]} :: Result 0x55552d2c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d0[5],d1[5]} :: Result 0x55552d2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d0[4],d1[4]} :: Result 0x55552a2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d20[3],d21[3]} :: Result 0x55552523 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d0[2],d1[2]} :: Result 0x55552a2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d17[1],d18[1]} :: Result 0x55552e2e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst2.8 {d30[0],d31[0]} :: Result 0x55552b2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +---- VST3 (multiple 3-elements) ---- +vst3.8 {d20-d22} :: Result 0x2e2f1c2b 0x1c2a2e1f 0x2314252f 0x2d2b1d2a 0x1d2d2b19 0x2415262c 0x55555555 0x55555555 delta 0 +vst3.16 {d0-d2} :: Result 0x1f1c2e2b 0x252a2e2f 0x232f141c 0x191d2d2a 0x262d2b2b 0x242c151d 0x55555555 0x55555555 delta 0 +vst3.32 {d0-d2} :: Result 0x252a2e2b 0x141c1f1c 0x232f2e2f 0x262d2d2a 0x151d191d 0x242c2b2b 0x55555555 0x55555555 delta 0 +vst3.8 {d0,d2,d4} :: Result 0x2e2f1c2b 0x1c2a2e1f 0x2314252f 0x2d2b1d2a 0x1d2d2b19 0x2415262c 0x55555555 0x55555555 delta 0 +vst3.16 {d20,d22,d24} :: Result 0x1f1c2e2b 0x252a2e2f 0x232f141c 0x191d2d2a 0x262d2b2b 0x242c151d 0x55555555 0x55555555 delta 0 +vst3.32 {d0,d2,d4} :: Result 0x252a2e2b 0x141c1f1c 0x232f2e2f 0x262d2d2a 0x151d191d 0x242c2b2b 0x55555555 0x55555555 delta 0 +---- VST3 (single 3-element structure from one lane) ---- +vst3.32 {d0[0],d1[0],d2[0]} :: Result 0x121f1e1f 0x252a2e2b 0x232f2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.32 {d0[1],d1[1],d2[1]} :: Result 0x131b1a1b 0x262d2d2a 0x242c2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.32 {d0[0],d2[0],d4[0]} :: Result 0x121f1e1f 0x252a2e2b 0x232f2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.32 {d0[1],d2[1],d4[1]} :: Result 0x131b1a1b 0x262d2d2a 0x242c2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.16 {d1[0],d2[0],d3[0]} :: Result 0x2e2b1e1f 0x55552e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.16 {d1[1],d2[1],d3[1]} :: Result 0x252a121f 0x5555232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.16 {d1[2],d2[2],d3[2]} :: Result 0x2d2a1a1b 0x55552b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.16 {d1[3],d2[3],d3[3]} :: Result 0x262d131b 0x5555242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.16 {d1[0],d3[0],d5[0]} :: Result 0x2e2f1e1f 0x55552e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.16 {d1[1],d3[1],d5[1]} :: Result 0x232f121f 0x5555252a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.16 {d1[2],d3[2],d5[2]} :: Result 0x2b2b1a1b 0x55552d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.16 {d1[3],d3[3],d5[3]} :: Result 0x242c131b 0x5555262d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.8 {d0[7],d1[7],d2[7]} :: Result 0x55242613 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.8 {d1[6],d2[6],d3[6]} :: Result 0x552c2d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.8 {d0[5],d1[5],d2[5]} :: Result 0x552b2d1a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.8 {d0[4],d1[4],d2[4]} :: Result 0x552b2a1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.8 {d20[3],d21[3],d22[3]} :: Result 0x55232512 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.8 {d0[2],d1[2],d2[2]} :: Result 0x552f2a1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.8 {d17[1],d18[1],d19[1]} :: Result 0x552e2e1e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst3.8 {d29[0],d30[0],d31[0]} :: Result 0x552b1f2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +---- VST4 (multiple 4-elements) ---- +vst4.8 {d0-d3} :: Result 0x2b2f1c1f 0x2e2e1f1e 0x2a2f1c1f 0x25231412 0x2a2b1d1b 0x2d2b191a 0x2d2c1d1b 0x26241513 delta 0 +vst4.16 {d20-d23} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 0 +vst4.32 {d0-d3} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 0 +vst4.8 {d0,d2,d4,d6} :: Result 0x2b2f1c1f 0x2e2e1f1e 0x2a2f1c1f 0x25231412 0x2a2b1d1b 0x2d2b191a 0x2d2c1d1b 0x26241513 delta 0 +vst4.16 {d1,d3,d5,d7} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 0 +vst4.32 {d20,d22,d24,d26} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 0 +---- VST4 (single 4-element structure from one lane) ---- +vst4.32 {d0[0],d1[0],d2[0],d3[0]} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.32 {d0[1],d1[1],d2[1],d3[1]} :: Result 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.32 {d0[0],d2[0],d4[0],d6[0]} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.32 {d0[1],d2[1],d4[1],d6[1]} :: Result 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.16 {d1[0],d2[0],d3[0],d4[0]} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.16 {d1[1],d2[1],d3[1],d4[1]} :: Result 0x141c121f 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.16 {d1[2],d2[2],d3[2],d4[2]} :: Result 0x191d1a1b 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.16 {d1[3],d2[3],d3[3],d4[3]} :: Result 0x151d131b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.16 {d1[0],d3[0],d5[0],d7[0]} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.16 {d1[1],d3[1],d5[1],d7[1]} :: Result 0x141c121f 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.16 {d1[2],d3[2],d5[2],d7[2]} :: Result 0x191d1a1b 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.16 {d1[3],d3[3],d5[3],d7[3]} :: Result 0x151d131b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.8 {d0[7],d1[7],d2[7],d3[7]} :: Result 0x26241513 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.8 {d1[6],d2[6],d3[6],d4[6]} :: Result 0x2d2c1d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.8 {d0[5],d1[5],d2[5],d3[5]} :: Result 0x2d2b191a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.8 {d0[4],d1[4],d2[4],d3[4]} :: Result 0x2a2b1d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.8 {d20[3],d21[3],d22[3],d23[3]} :: Result 0x25231412 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.8 {d0[2],d1[2],d2[2],d3[2]} :: Result 0x2a2f1c1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.8 {d17[1],d18[1],d19[1],d20[1]} :: Result 0x2e2e1f1e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +vst4.8 {d28[0],d29[0],d30[0],d31[0]} :: Result 0x2b2f1c1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 0 +---- VLD1 (multiple single elements) ---- +vld1.8 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 8 +vld1.16 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 8 +vld1.32 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 8 +vld1.64 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 8 +vld1.8 {d9} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 8 +vld1.16 {d17} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 8 +vld1.32 {d31} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 8 +vld1.64 {d14} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 8 +vld1.8 {d0-d1} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 16 +vld1.16 {d0-d1} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 16 +vld1.32 {d5-d6} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 16 +vld1.64 {d30-d31} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 16 +vld1.8 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 24 +vld1.16 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 24 +vld1.32 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 24 +vld1.64 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 24 +vld1.8 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 32 +vld1.16 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 32 +vld1.32 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 32 +vld1.64 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 32 +---- VLD1 (single element to one lane) ---- +vld1.32 {d0[0]} :: Result 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 delta 4 +vld1.32 {d0[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f delta 4 +vld1.16 {d1[0]} :: Result 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 delta 2 +vld1.16 {d1[1]} :: Result 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 delta 2 +vld1.16 {d1[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f delta 2 +vld1.16 {d1[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 delta 2 +vld1.8 {d0[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 delta 1 +vld1.8 {d1[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 delta 1 +vld1.8 {d0[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 delta 1 +vld1.8 {d0[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f delta 1 +vld1.8 {d20[3]} :: Result 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 delta 1 +vld1.8 {d0[2]} :: Result 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 delta 1 +vld1.8 {d17[1]} :: Result 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 delta 1 +vld1.8 {d30[0]} :: Result 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 delta 1 +---- VLD1 (single element to all lanes) ---- +vld1.8 {d0[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 1 +vld1.16 {d0[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 2 +vld1.32 {d0[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 4 +vld1.8 {d9[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 1 +vld1.16 {d17[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 2 +vld1.32 {d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 4 +vld1.8 {d0[],d1[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 1 +vld1.16 {d0[],d1[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 2 +vld1.32 {d5[],d6[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 4 +---- VLD2 (multiple 2-elements) ---- +vld2.8 {d30-d31} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f delta 16 +vld2.16 {d0-d1} :: Result 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c delta 16 +vld2.32 {d0-d1} :: Result 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d delta 16 +vld2.8 {d10,d12} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f delta 16 +vld2.16 {d20,d22} :: Result 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c delta 16 +vld2.32 {d0,d2} :: Result 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d delta 16 +vld2.8 {d0-d3} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x2c2b2f2f 0x2d2a2a2b 0x131a121e 0x1519141f 0x242b232e 0x262d252e delta 32 +vld2.16 {d20-d23} :: Result 0x1a1b1e1f 0x191d1f1c 0x2b2b2e2f 0x2d2a2e2b 0x131b121f 0x151d141c 0x242c232f 0x262d252a delta 32 +vld2.32 {d0-d3} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 32 +---- VLD2 (single 2-element structure to one lane) ---- +vld2.32 {d0[0],d1[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 delta 8 +vld2.32 {d0[1],d1[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b delta 8 +vld2.32 {d0[0],d2[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 delta 8 +vld2.32 {d0[1],d2[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b delta 8 +vld2.16 {d1[0],d2[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 delta 4 +vld2.16 {d1[1],d2[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 delta 4 +vld2.16 {d1[2],d2[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f delta 4 +vld2.16 {d1[3],d2[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 delta 4 +vld2.16 {d1[0],d3[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 delta 4 +vld2.16 {d1[1],d3[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 delta 4 +vld2.16 {d1[2],d3[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f delta 4 +vld2.16 {d1[3],d3[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 delta 4 +vld2.8 {d0[7],d1[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 delta 2 +vld2.8 {d1[6],d2[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 delta 2 +vld2.8 {d0[5],d1[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 delta 2 +vld2.8 {d0[4],d1[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e delta 2 +vld2.8 {d20[3],d21[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 delta 2 +vld2.8 {d0[2],d1[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 delta 2 +vld2.8 {d17[1],d18[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 delta 2 +vld2.8 {d30[0],d31[0]} :: Result 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 delta 2 +---- VLD2 (2-elements to all lanes) ---- +vld2.8 {d0[],d1[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 2 +vld2.16 {d0[],d1[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 4 +vld2.32 {d0[],d1[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 8 +vld2.8 {d9[],d11[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 2 +vld2.16 {d17[],d18[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 4 +vld2.32 {d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 8 +vld2.8 {d0[],d2[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 2 +vld2.16 {d0[],d2[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 4 +vld2.32 {d5[],d7[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 8 +---- VLD3 (multiple 3-elements) ---- +vld3.8 {d20-d22} :: Result 0x1f1b121f 0x2b2f151d 0x1c131b1e 0x2c232f19 0x141c1a1f 0x242b2e1d 0x1f1b121f 0x2b2f151d delta 24 +vld3.16 {d0-d2} :: Result 0x131b1e1f 0x232f191d 0x1f1c121f 0x2b2b151d 0x141c1a1b 0x242c2e2f 0x131b1e1f 0x232f191d delta 24 +vld3.32 {d0-d2} :: Result 0x121f1e1f 0x151d191d 0x131b1a1b 0x232f2e2f 0x141c1f1c 0x242c2b2b 0x121f1e1f 0x151d191d delta 24 +vld3.8 {d0,d2,d4} :: Result 0x1f1b121f 0x2b2f151d 0x1c131b1e 0x2c232f19 0x141c1a1f 0x242b2e1d 0x1f1b121f 0x2b2f151d delta 24 +vld3.16 {d20,d22,d24} :: Result 0x131b1e1f 0x232f191d 0x1f1c121f 0x2b2b151d 0x141c1a1b 0x242c2e2f 0x131b1e1f 0x232f191d delta 24 +vld3.32 {d0,d2,d4} :: Result 0x121f1e1f 0x151d191d 0x131b1a1b 0x232f2e2f 0x141c1f1c 0x242c2b2b 0x121f1e1f 0x151d191d delta 24 +---- VLD3 (single 3-element structure to one lane) ---- +vld3.32 {d0[0],d1[0],d2[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b 0x55555555 delta 12 +vld3.32 {d0[1],d1[1],d2[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b delta 12 +vld3.32 {d0[0],d2[0],d4[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b 0x55555555 delta 12 +vld3.32 {d0[1],d2[1],d4[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b delta 12 +vld3.16 {d1[0],d2[0],d3[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555121f 0x55555555 delta 6 +vld3.16 {d1[1],d2[1],d3[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x121f5555 0x55555555 delta 6 +vld3.16 {d1[2],d2[2],d3[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555121f delta 6 +vld3.16 {d1[3],d2[3],d3[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x121f5555 delta 6 +vld3.16 {d1[0],d3[0],d5[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 delta 6 +vld3.16 {d1[1],d3[1],d5[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 delta 6 +vld3.16 {d1[2],d3[2],d5[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x5555121f 0x55555555 0x55551a1b delta 6 +vld3.16 {d1[3],d3[3],d5[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 delta 6 +vld3.8 {d0[7],d1[7],d2[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 delta 3 +vld3.8 {d1[6],d2[6],d3[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 delta 3 +vld3.8 {d0[5],d1[5],d2[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 delta 3 +vld3.8 {d0[4],d1[4],d2[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e delta 3 +vld3.8 {d20[3],d21[3],d22[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 delta 3 +vld3.8 {d0[2],d1[2],d2[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 delta 3 +vld3.8 {d17[1],d18[1],d19[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 delta 3 +vld3.8 {d29[0],d30[0],d31[0]} :: Result 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 delta 3 +---- VLD3 (3-elements to all lanes) ---- +vld3.8 {d0[],d1[],d2[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 3 +vld3.16 {d0[],d1[],d2[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 6 +vld3.32 {d0[],d1[],d2[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x131b1a1b 0x131b1a1b delta 12 +vld3.8 {d9[],d11[],d13[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 3 +vld3.16 {d17[],d18[],d19[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 6 +vld3.32 {d29[],d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c delta 12 +vld3.8 {d0[],d2[],d4[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 3 +vld3.16 {d0[],d2[],d4[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 6 +vld3.32 {d5[],d7[],d9[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x131b1a1b 0x131b1a1b delta 12 +---- VLD4 (multiple 3-elements) ---- +vld4.8 {d0-d3} :: Result 0x1d1c1b1f 0x2a2b2b2f 0x191f1a1e 0x2d2e2b2e 0x1d1c1b1f 0x2d2a2c2f 0x15141312 0x26252423 delta 32 +vld4.16 {d20-d23} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 32 +vld4.32 {d0-d3} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 32 +vld4.8 {d0,d2,d4,d6} :: Result 0x1d1c1b1f 0x2a2b2b2f 0x191f1a1e 0x2d2e2b2e 0x1d1c1b1f 0x2d2a2c2f 0x15141312 0x26252423 delta 32 +vld4.16 {d1,d3,d5,d7} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 32 +vld4.32 {d20,d22,d24,d26} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 32 +---- VLD4 (single 4-element structure to one lane) ---- +vld4.32 {d0[0],d1[0],d2[0],d3[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d 0x55555555 delta 16 +vld4.32 {d0[1],d1[1],d2[1],d3[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x55555555 delta 16 +vld4.32 {d0[0],d2[0],d4[0],d6[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d 0x55555555 delta 16 +vld4.32 {d0[1],d2[1],d4[1],d6[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d delta 16 +vld4.16 {d1[0],d2[0],d3[0],d4[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b 0x55555555 delta 8 +vld4.16 {d1[1],d2[1],d3[1],d4[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 0x55555555 delta 8 +vld4.16 {d1[2],d2[2],d3[2],d4[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b delta 8 +vld4.16 {d1[3],d2[3],d3[3],d4[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 delta 8 +vld4.16 {d1[0],d3[0],d5[0],d7[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b 0x55555555 delta 8 +vld4.16 {d1[1],d3[1],d5[1],d7[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 0x55555555 delta 8 +vld4.16 {d1[2],d3[2],d5[2],d7[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b delta 8 +vld4.16 {d1[3],d3[3],d5[3],d7[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 delta 8 +vld4.8 {d0[7],d1[7],d2[7],d3[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x12555555 delta 4 +vld4.8 {d1[6],d2[6],d3[6],d4[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x55125555 delta 4 +vld4.8 {d0[5],d1[5],d2[5],d3[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551255 delta 4 +vld4.8 {d0[4],d1[4],d2[4],d3[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x55555512 delta 4 +vld4.8 {d20[3],d21[3],d22[3],d23[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x12555555 0x55555555 delta 4 +vld4.8 {d0[2],d1[2],d2[2],d3[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x55125555 0x55555555 delta 4 +vld4.8 {d17[1],d18[1],d19[1],d20[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551255 0x55555555 delta 4 +vld4.8 {d28[0],d29[0],d30[0],d31[0]} :: Result 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x55555512 0x55555555 delta 4 +---- VLD4 (4-elements to all lanes) ---- +vld4.8 {d0[],d1[],d2[],d3[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 4 +vld4.16 {d0[],d1[],d2[],d3[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 8 +vld4.32 {d0[],d1[],d2[],d3[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 16 +vld4.8 {d9[],d11[],d13[],d15[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 4 +vld4.16 {d17[],d18[],d19[],d20[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 8 +vld4.32 {d28[],d29[],d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 16 +vld4.8 {d0[],d2[],d4[],d6[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 4 +vld4.16 {d0[],d2[],d4[],d6[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 8 +vld4.32 {d5[],d7[],d9[],d11[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 16 +---- VST1 (multiple single elements) ---- +vst1.8 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst1.16 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst1.32 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst1.64 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst1.8 {d9} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst1.16 {d17} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst1.32 {d31} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst1.64 {d14} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst1.8 {d0-d1} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst1.16 {d0-d1} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst1.32 {d5-d6} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst1.64 {d30-d31} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst1.8 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 24 +vst1.16 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 24 +vst1.32 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 24 +vst1.64 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 24 +vst1.8 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 32 +vst1.16 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 32 +vst1.32 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 32 +vst1.64 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 32 +---- VST1 (single element from one lane) ---- +vst1.32 {d0[0]} :: Result 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst1.32 {d0[1]} :: Result 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst1.16 {d1[0]} :: Result 0x55552e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst1.16 {d1[1]} :: Result 0x5555252a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst1.16 {d1[2]} :: Result 0x55552d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst1.16 {d1[3]} :: Result 0x5555262d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst1.8 {d0[7]} :: Result 0x55555526 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1 +vst1.8 {d1[6]} :: Result 0x5555552d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1 +vst1.8 {d0[5]} :: Result 0x5555552d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1 +vst1.8 {d0[4]} :: Result 0x5555552a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1 +vst1.8 {d20[3]} :: Result 0x55555525 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1 +vst1.8 {d0[2]} :: Result 0x5555552a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1 +vst1.8 {d17[1]} :: Result 0x5555552e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1 +vst1.8 {d30[0]} :: Result 0x5555552b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1 +---- VST2 (multiple 2-elements) ---- +vst2.8 {d30-d31} :: Result 0x2e2e2b2f 0x25232a2f 0x2d2b2a2b 0x26242d2c 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst2.16 {d0-d1} :: Result 0x2e2b2e2f 0x252a232f 0x2d2a2b2b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst2.32 {d0-d1} :: Result 0x232f2e2f 0x252a2e2b 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst2.8 {d10,d12} :: Result 0x2e2e2b2f 0x25232a2f 0x2d2b2a2b 0x26242d2c 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst2.16 {d20,d22} :: Result 0x2e2b2e2f 0x252a232f 0x2d2a2b2b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst2.32 {d0,d2} :: Result 0x232f2e2f 0x252a2e2b 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst2.8 {d0-d3} :: Result 0x2e1e2f1f 0x23122f1f 0x2b1a2b1b 0x24132c1b 0x2e1f2b1c 0x25142a1c 0x2d192a1d 0x26152d1d delta 32 +vst2.16 {d20-d23} :: Result 0x2e2f1e1f 0x232f121f 0x2b2b1a1b 0x242c131b 0x2e2b1f1c 0x252a141c 0x2d2a191d 0x262d151d delta 32 +vst2.32 {d0-d3} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 32 +---- VST2 (single 2-element structure from one lane) ---- +vst2.32 {d0[0],d1[0]} :: Result 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst2.32 {d0[1],d1[1]} :: Result 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst2.32 {d0[0],d2[0]} :: Result 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst2.32 {d0[1],d2[1]} :: Result 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst2.16 {d1[0],d2[0]} :: Result 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst2.16 {d1[1],d2[1]} :: Result 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst2.16 {d1[2],d2[2]} :: Result 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst2.16 {d1[3],d2[3]} :: Result 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst2.16 {d1[0],d3[0]} :: Result 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst2.16 {d1[1],d3[1]} :: Result 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst2.16 {d1[2],d3[2]} :: Result 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst2.16 {d1[3],d3[3]} :: Result 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst2.8 {d0[7],d1[7]} :: Result 0x55552624 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst2.8 {d1[6],d2[6]} :: Result 0x55552d2c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst2.8 {d0[5],d1[5]} :: Result 0x55552d2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst2.8 {d0[4],d1[4]} :: Result 0x55552a2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst2.8 {d20[3],d21[3]} :: Result 0x55552523 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst2.8 {d0[2],d1[2]} :: Result 0x55552a2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst2.8 {d17[1],d18[1]} :: Result 0x55552e2e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +vst2.8 {d30[0],d31[0]} :: Result 0x55552b2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 2 +---- VST3 (multiple 3-elements) ---- +vst3.8 {d20-d22} :: Result 0x2e2f1c2b 0x1c2a2e1f 0x2314252f 0x2d2b1d2a 0x1d2d2b19 0x2415262c 0x55555555 0x55555555 delta 24 +vst3.16 {d0-d2} :: Result 0x1f1c2e2b 0x252a2e2f 0x232f141c 0x191d2d2a 0x262d2b2b 0x242c151d 0x55555555 0x55555555 delta 24 +vst3.32 {d0-d2} :: Result 0x252a2e2b 0x141c1f1c 0x232f2e2f 0x262d2d2a 0x151d191d 0x242c2b2b 0x55555555 0x55555555 delta 24 +vst3.8 {d0,d2,d4} :: Result 0x2e2f1c2b 0x1c2a2e1f 0x2314252f 0x2d2b1d2a 0x1d2d2b19 0x2415262c 0x55555555 0x55555555 delta 24 +vst3.16 {d20,d22,d24} :: Result 0x1f1c2e2b 0x252a2e2f 0x232f141c 0x191d2d2a 0x262d2b2b 0x242c151d 0x55555555 0x55555555 delta 24 +vst3.32 {d0,d2,d4} :: Result 0x252a2e2b 0x141c1f1c 0x232f2e2f 0x262d2d2a 0x151d191d 0x242c2b2b 0x55555555 0x55555555 delta 24 +---- VST3 (single 3-element structure from one lane) ---- +vst3.32 {d0[0],d1[0],d2[0]} :: Result 0x121f1e1f 0x252a2e2b 0x232f2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 12 +vst3.32 {d0[1],d1[1],d2[1]} :: Result 0x131b1a1b 0x262d2d2a 0x242c2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 12 +vst3.32 {d0[0],d2[0],d4[0]} :: Result 0x121f1e1f 0x252a2e2b 0x232f2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 12 +vst3.32 {d0[1],d2[1],d4[1]} :: Result 0x131b1a1b 0x262d2d2a 0x242c2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 12 +vst3.16 {d1[0],d2[0],d3[0]} :: Result 0x2e2b1e1f 0x55552e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 6 +vst3.16 {d1[1],d2[1],d3[1]} :: Result 0x252a121f 0x5555232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 6 +vst3.16 {d1[2],d2[2],d3[2]} :: Result 0x2d2a1a1b 0x55552b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 6 +vst3.16 {d1[3],d2[3],d3[3]} :: Result 0x262d131b 0x5555242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 6 +vst3.16 {d1[0],d3[0],d5[0]} :: Result 0x2e2f1e1f 0x55552e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 6 +vst3.16 {d1[1],d3[1],d5[1]} :: Result 0x232f121f 0x5555252a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 6 +vst3.16 {d1[2],d3[2],d5[2]} :: Result 0x2b2b1a1b 0x55552d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 6 +vst3.16 {d1[3],d3[3],d5[3]} :: Result 0x242c131b 0x5555262d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 6 +vst3.8 {d0[7],d1[7],d2[7]} :: Result 0x55242613 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 3 +vst3.8 {d1[6],d2[6],d3[6]} :: Result 0x552c2d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 3 +vst3.8 {d0[5],d1[5],d2[5]} :: Result 0x552b2d1a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 3 +vst3.8 {d0[4],d1[4],d2[4]} :: Result 0x552b2a1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 3 +vst3.8 {d20[3],d21[3],d22[3]} :: Result 0x55232512 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 3 +vst3.8 {d0[2],d1[2],d2[2]} :: Result 0x552f2a1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 3 +vst3.8 {d17[1],d18[1],d19[1]} :: Result 0x552e2e1e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 3 +vst3.8 {d29[0],d30[0],d31[0]} :: Result 0x552b1f2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 3 +---- VST4 (multiple 4-elements) ---- +vst4.8 {d0-d3} :: Result 0x2b2f1c1f 0x2e2e1f1e 0x2a2f1c1f 0x25231412 0x2a2b1d1b 0x2d2b191a 0x2d2c1d1b 0x26241513 delta 32 +vst4.16 {d20-d23} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 32 +vst4.32 {d0-d3} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 32 +vst4.8 {d0,d2,d4,d6} :: Result 0x2b2f1c1f 0x2e2e1f1e 0x2a2f1c1f 0x25231412 0x2a2b1d1b 0x2d2b191a 0x2d2c1d1b 0x26241513 delta 32 +vst4.16 {d1,d3,d5,d7} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 32 +vst4.32 {d20,d22,d24,d26} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 32 +---- VST4 (single 4-element structure from one lane) ---- +vst4.32 {d0[0],d1[0],d2[0],d3[0]} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst4.32 {d0[1],d1[1],d2[1],d3[1]} :: Result 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst4.32 {d0[0],d2[0],d4[0],d6[0]} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst4.32 {d0[1],d2[1],d4[1],d6[1]} :: Result 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 16 +vst4.16 {d1[0],d2[0],d3[0],d4[0]} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst4.16 {d1[1],d2[1],d3[1],d4[1]} :: Result 0x141c121f 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst4.16 {d1[2],d2[2],d3[2],d4[2]} :: Result 0x191d1a1b 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst4.16 {d1[3],d2[3],d3[3],d4[3]} :: Result 0x151d131b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst4.16 {d1[0],d3[0],d5[0],d7[0]} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst4.16 {d1[1],d3[1],d5[1],d7[1]} :: Result 0x141c121f 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst4.16 {d1[2],d3[2],d5[2],d7[2]} :: Result 0x191d1a1b 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst4.16 {d1[3],d3[3],d5[3],d7[3]} :: Result 0x151d131b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 8 +vst4.8 {d0[7],d1[7],d2[7],d3[7]} :: Result 0x26241513 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst4.8 {d1[6],d2[6],d3[6],d4[6]} :: Result 0x2d2c1d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst4.8 {d0[5],d1[5],d2[5],d3[5]} :: Result 0x2d2b191a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst4.8 {d0[4],d1[4],d2[4],d3[4]} :: Result 0x2a2b1d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst4.8 {d20[3],d21[3],d22[3],d23[3]} :: Result 0x25231412 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst4.8 {d0[2],d1[2],d2[2],d3[2]} :: Result 0x2a2f1c1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst4.8 {d17[1],d18[1],d19[1],d20[1]} :: Result 0x2e2e1f1e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +vst4.8 {d28[0],d29[0],d30[0],d31[0]} :: Result 0x2b2f1c1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 4 +---- VLD1 (multiple single elements) ---- +vld1.8 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.16 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.32 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.64 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.8 {d9} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.16 {d17} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.32 {d31} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.64 {d14} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b delta 0 +vld1.8 {d0-d1} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 0 +vld1.16 {d0-d1} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 0 +vld1.32 {d5-d6} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 0 +vld1.64 {d30-d31} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d delta 0 +vld1.8 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 0 +vld1.16 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 0 +vld1.32 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 0 +vld1.64 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b delta 0 +vld1.8 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vld1.16 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vld1.32 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +vld1.64 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 0 +---- VLD1 (single element to one lane) ---- +vld1.32 {d0[0]} :: Result 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 delta 0 +vld1.32 {d0[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f delta 0 +vld1.16 {d1[0]} :: Result 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 delta 0 +vld1.16 {d1[1]} :: Result 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 delta 0 +vld1.16 {d1[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f delta 0 +vld1.16 {d1[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 delta 0 +vld1.8 {d0[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 delta 0 +vld1.8 {d1[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 delta 0 +vld1.8 {d0[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 delta 0 +vld1.8 {d0[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f delta 0 +vld1.8 {d20[3]} :: Result 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 delta 0 +vld1.8 {d0[2]} :: Result 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 delta 0 +vld1.8 {d17[1]} :: Result 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 delta 0 +vld1.8 {d30[0]} :: Result 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 delta 0 +---- VLD1 (single element to all lanes) ---- +vld1.8 {d0[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 0 +vld1.16 {d0[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 0 +vld1.32 {d0[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 0 +vld1.8 {d9[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 0 +vld1.16 {d17[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 0 +vld1.32 {d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 0 +vld1.8 {d0[],d1[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f delta 0 +vld1.16 {d0[],d1[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f delta 0 +vld1.32 {d5[],d6[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f delta 0 +---- VLD2 (multiple 2-elements) ---- +vld2.8 {d30-d31} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f delta 0 +vld2.16 {d0-d1} :: Result 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c delta 0 +vld2.32 {d0-d1} :: Result 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d delta 0 +vld2.8 {d10,d12} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f delta 0 +vld2.16 {d20,d22} :: Result 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c delta 0 +vld2.32 {d0,d2} :: Result 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d delta 0 +vld2.8 {d0-d3} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x2c2b2f2f 0x2d2a2a2b 0x131a121e 0x1519141f 0x242b232e 0x262d252e delta 0 +vld2.16 {d20-d23} :: Result 0x1a1b1e1f 0x191d1f1c 0x2b2b2e2f 0x2d2a2e2b 0x131b121f 0x151d141c 0x242c232f 0x262d252a delta 0 +vld2.32 {d0-d3} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 0 +---- VLD2 (single 2-element structure to one lane) ---- +vld2.32 {d0[0],d1[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 delta 0 +vld2.32 {d0[1],d1[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b delta 0 +vld2.32 {d0[0],d2[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 delta 0 +vld2.32 {d0[1],d2[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b delta 0 +vld2.16 {d1[0],d2[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 delta 0 +vld2.16 {d1[1],d2[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 delta 0 +vld2.16 {d1[2],d2[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f delta 0 +vld2.16 {d1[3],d2[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 delta 0 +vld2.16 {d1[0],d3[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 delta 0 +vld2.16 {d1[1],d3[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 delta 0 +vld2.16 {d1[2],d3[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f delta 0 +vld2.16 {d1[3],d3[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 delta 0 +vld2.8 {d0[7],d1[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 delta 0 +vld2.8 {d1[6],d2[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 delta 0 +vld2.8 {d0[5],d1[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 delta 0 +vld2.8 {d0[4],d1[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e delta 0 +vld2.8 {d20[3],d21[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 delta 0 +vld2.8 {d0[2],d1[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 delta 0 +vld2.8 {d17[1],d18[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 delta 0 +vld2.8 {d30[0],d31[0]} :: Result 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 delta 0 +---- VLD2 (2-elements to all lanes) ---- +vld2.8 {d0[],d1[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld2.16 {d0[],d1[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 0 +vld2.32 {d0[],d1[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 0 +vld2.8 {d9[],d11[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld2.16 {d17[],d18[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 0 +vld2.32 {d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 0 +vld2.8 {d0[],d2[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld2.16 {d0[],d2[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f delta 0 +vld2.32 {d5[],d7[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b delta 0 +---- VLD3 (multiple 3-elements) ---- +vld3.8 {d20-d22} :: Result 0x1f1b121f 0x2b2f151d 0x1c131b1e 0x2c232f19 0x141c1a1f 0x242b2e1d 0x1f1b121f 0x2b2f151d delta 0 +vld3.16 {d0-d2} :: Result 0x131b1e1f 0x232f191d 0x1f1c121f 0x2b2b151d 0x141c1a1b 0x242c2e2f 0x131b1e1f 0x232f191d delta 0 +vld3.32 {d0-d2} :: Result 0x121f1e1f 0x151d191d 0x131b1a1b 0x232f2e2f 0x141c1f1c 0x242c2b2b 0x121f1e1f 0x151d191d delta 0 +vld3.8 {d0,d2,d4} :: Result 0x1f1b121f 0x2b2f151d 0x1c131b1e 0x2c232f19 0x141c1a1f 0x242b2e1d 0x1f1b121f 0x2b2f151d delta 0 +vld3.16 {d20,d22,d24} :: Result 0x131b1e1f 0x232f191d 0x1f1c121f 0x2b2b151d 0x141c1a1b 0x242c2e2f 0x131b1e1f 0x232f191d delta 0 +vld3.32 {d0,d2,d4} :: Result 0x121f1e1f 0x151d191d 0x131b1a1b 0x232f2e2f 0x141c1f1c 0x242c2b2b 0x121f1e1f 0x151d191d delta 0 +---- VLD3 (single 3-element structure to one lane) ---- +vld3.32 {d0[0],d1[0],d2[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b 0x55555555 delta 0 +vld3.32 {d0[1],d1[1],d2[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b delta 0 +vld3.32 {d0[0],d2[0],d4[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b 0x55555555 delta 0 +vld3.32 {d0[1],d2[1],d4[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b delta 0 +vld3.16 {d1[0],d2[0],d3[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555121f 0x55555555 delta 0 +vld3.16 {d1[1],d2[1],d3[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x121f5555 0x55555555 delta 0 +vld3.16 {d1[2],d2[2],d3[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555121f delta 0 +vld3.16 {d1[3],d2[3],d3[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x121f5555 delta 0 +vld3.16 {d1[0],d3[0],d5[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 delta 0 +vld3.16 {d1[1],d3[1],d5[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 delta 0 +vld3.16 {d1[2],d3[2],d5[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x5555121f 0x55555555 0x55551a1b delta 0 +vld3.16 {d1[3],d3[3],d5[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 delta 0 +vld3.8 {d0[7],d1[7],d2[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 delta 0 +vld3.8 {d1[6],d2[6],d3[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 delta 0 +vld3.8 {d0[5],d1[5],d2[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 delta 0 +vld3.8 {d0[4],d1[4],d2[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e delta 0 +vld3.8 {d20[3],d21[3],d22[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 delta 0 +vld3.8 {d0[2],d1[2],d2[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 delta 0 +vld3.8 {d17[1],d18[1],d19[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 delta 0 +vld3.8 {d29[0],d30[0],d31[0]} :: Result 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 delta 0 +---- VLD3 (3-elements to all lanes) ---- +vld3.8 {d0[],d1[],d2[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld3.16 {d0[],d1[],d2[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 0 +vld3.32 {d0[],d1[],d2[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x131b1a1b 0x131b1a1b delta 0 +vld3.8 {d9[],d11[],d13[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld3.16 {d17[],d18[],d19[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 0 +vld3.32 {d29[],d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c delta 0 +vld3.8 {d0[],d2[],d4[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e delta 0 +vld3.16 {d0[],d2[],d4[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f delta 0 +vld3.32 {d5[],d7[],d9[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x131b1a1b 0x131b1a1b delta 0 +---- VLD4 (multiple 3-elements) ---- +vld4.8 {d0-d3} :: Result 0x1d1c1b1f 0x2a2b2b2f 0x191f1a1e 0x2d2e2b2e 0x1d1c1b1f 0x2d2a2c2f 0x15141312 0x26252423 delta 0 +vld4.16 {d20-d23} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 0 +vld4.32 {d0-d3} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 0 +vld4.8 {d0,d2,d4,d6} :: Result 0x1d1c1b1f 0x2a2b2b2f 0x191f1a1e 0x2d2e2b2e 0x1d1c1b1f 0x2d2a2c2f 0x15141312 0x26252423 delta 0 +vld4.16 {d1,d3,d5,d7} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 0 +vld4.32 {d20,d22,d24,d26} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 0 +---- VLD4 (single 4-element structure to one lane) ---- +vld4.32 {d0[0],d1[0],d2[0],d3[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d 0x55555555 delta 0 +vld4.32 {d0[1],d1[1],d2[1],d3[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x55555555 delta 0 +vld4.32 {d0[0],d2[0],d4[0],d6[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d 0x55555555 delta 0 +vld4.32 {d0[1],d2[1],d4[1],d6[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d delta 0 +vld4.16 {d1[0],d2[0],d3[0],d4[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b 0x55555555 delta 0 +vld4.16 {d1[1],d2[1],d3[1],d4[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 0x55555555 delta 0 +vld4.16 {d1[2],d2[2],d3[2],d4[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b delta 0 +vld4.16 {d1[3],d2[3],d3[3],d4[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 delta 0 +vld4.16 {d1[0],d3[0],d5[0],d7[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b 0x55555555 delta 0 +vld4.16 {d1[1],d3[1],d5[1],d7[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 0x55555555 delta 0 +vld4.16 {d1[2],d3[2],d5[2],d7[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b delta 0 +vld4.16 {d1[3],d3[3],d5[3],d7[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 delta 0 +vld4.8 {d0[7],d1[7],d2[7],d3[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x12555555 delta 0 +vld4.8 {d1[6],d2[6],d3[6],d4[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x55125555 delta 0 +vld4.8 {d0[5],d1[5],d2[5],d3[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551255 delta 0 +vld4.8 {d0[4],d1[4],d2[4],d3[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x55555512 delta 0 +vld4.8 {d20[3],d21[3],d22[3],d23[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x12555555 0x55555555 delta 0 +vld4.8 {d0[2],d1[2],d2[2],d3[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x55125555 0x55555555 delta 0 +vld4.8 {d17[1],d18[1],d19[1],d20[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551255 0x55555555 delta 0 +vld4.8 {d28[0],d29[0],d30[0],d31[0]} :: Result 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x55555512 0x55555555 delta 0 +---- VLD4 (4-elements to all lanes) ---- +vld4.8 {d0[],d1[],d2[],d3[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 0 +vld4.16 {d0[],d1[],d2[],d3[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 0 +vld4.32 {d0[],d1[],d2[],d3[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 0 +vld4.8 {d9[],d11[],d13[],d15[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 0 +vld4.16 {d17[],d18[],d19[],d20[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 0 +vld4.32 {d28[],d29[],d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 0 +vld4.8 {d0[],d2[],d4[],d6[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212 delta 0 +vld4.16 {d0[],d2[],d4[],d6[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b delta 0 +vld4.32 {d5[],d7[],d9[],d11[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d delta 0 +---- VST1 (multiple single elements) ---- +vst1.8 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.16 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069420 +vst1.32 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069424 +vst1.64 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069428 +vst1.8 {d9} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.16 {d17} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.32 {d31} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.64 {d14} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d0-d1} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.16 {d0-d1} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.32 {d5-d6} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.64 {d30-d31} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 1069416 +vst1.16 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 1069416 +vst1.32 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 1069416 +vst1.64 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555 delta 1069416 +vst1.8 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 1069416 +vst1.16 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 1069416 +vst1.32 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 1069416 +vst1.64 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a delta 1069416 +---- VST1 (single element from one lane) ---- +vst1.32 {d0[0]} :: Result 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.32 {d0[1]} :: Result 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069420 +vst1.16 {d1[0]} :: Result 0x55552e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069424 +vst1.16 {d1[1]} :: Result 0x5555252a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069428 +vst1.16 {d1[2]} :: Result 0x55552d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.16 {d1[3]} :: Result 0x5555262d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d0[7]} :: Result 0x55555526 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d1[6]} :: Result 0x5555552d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d0[5]} :: Result 0x5555552d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d0[4]} :: Result 0x5555552a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d20[3]} :: Result 0x55555525 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d0[2]} :: Result 0x5555552a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d17[1]} :: Result 0x5555552e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst1.8 {d30[0]} :: Result 0x5555552b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +---- VST2 (multiple 2-elements) ---- +vst2.8 {d30-d31} :: Result 0x2e2e2b2f 0x25232a2f 0x2d2b2a2b 0x26242d2c 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.16 {d0-d1} :: Result 0x2e2b2e2f 0x252a232f 0x2d2a2b2b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069420 +vst2.32 {d0-d1} :: Result 0x232f2e2f 0x252a2e2b 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069424 +vst2.8 {d10,d12} :: Result 0x2e2e2b2f 0x25232a2f 0x2d2b2a2b 0x26242d2c 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069428 +vst2.16 {d20,d22} :: Result 0x2e2b2e2f 0x252a232f 0x2d2a2b2b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.32 {d0,d2} :: Result 0x232f2e2f 0x252a2e2b 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d0-d3} :: Result 0x2e1e2f1f 0x23122f1f 0x2b1a2b1b 0x24132c1b 0x2e1f2b1c 0x25142a1c 0x2d192a1d 0x26152d1d delta 1069416 +vst2.16 {d20-d23} :: Result 0x2e2f1e1f 0x232f121f 0x2b2b1a1b 0x242c131b 0x2e2b1f1c 0x252a141c 0x2d2a191d 0x262d151d delta 1069416 +vst2.32 {d0-d3} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a delta 1069416 +---- VST2 (single 2-element structure from one lane) ---- +vst2.32 {d0[0],d1[0]} :: Result 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.32 {d0[1],d1[1]} :: Result 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069420 +vst2.32 {d0[0],d2[0]} :: Result 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069424 +vst2.32 {d0[1],d2[1]} :: Result 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069428 +vst2.16 {d1[0],d2[0]} :: Result 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.16 {d1[1],d2[1]} :: Result 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.16 {d1[2],d2[2]} :: Result 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.16 {d1[3],d2[3]} :: Result 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.16 {d1[0],d3[0]} :: Result 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.16 {d1[1],d3[1]} :: Result 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.16 {d1[2],d3[2]} :: Result 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.16 {d1[3],d3[3]} :: Result 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d0[7],d1[7]} :: Result 0x55552624 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d1[6],d2[6]} :: Result 0x55552d2c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d0[5],d1[5]} :: Result 0x55552d2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d0[4],d1[4]} :: Result 0x55552a2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d20[3],d21[3]} :: Result 0x55552523 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d0[2],d1[2]} :: Result 0x55552a2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d17[1],d18[1]} :: Result 0x55552e2e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst2.8 {d30[0],d31[0]} :: Result 0x55552b2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +---- VST3 (multiple 3-elements) ---- +vst3.8 {d20-d22} :: Result 0x2e2f1c2b 0x1c2a2e1f 0x2314252f 0x2d2b1d2a 0x1d2d2b19 0x2415262c 0x55555555 0x55555555 delta 1069416 +vst3.16 {d0-d2} :: Result 0x1f1c2e2b 0x252a2e2f 0x232f141c 0x191d2d2a 0x262d2b2b 0x242c151d 0x55555555 0x55555555 delta 1069420 +vst3.32 {d0-d2} :: Result 0x252a2e2b 0x141c1f1c 0x232f2e2f 0x262d2d2a 0x151d191d 0x242c2b2b 0x55555555 0x55555555 delta 1069424 +vst3.8 {d0,d2,d4} :: Result 0x2e2f1c2b 0x1c2a2e1f 0x2314252f 0x2d2b1d2a 0x1d2d2b19 0x2415262c 0x55555555 0x55555555 delta 1069428 +vst3.16 {d20,d22,d24} :: Result 0x1f1c2e2b 0x252a2e2f 0x232f141c 0x191d2d2a 0x262d2b2b 0x242c151d 0x55555555 0x55555555 delta 1069416 +vst3.32 {d0,d2,d4} :: Result 0x252a2e2b 0x141c1f1c 0x232f2e2f 0x262d2d2a 0x151d191d 0x242c2b2b 0x55555555 0x55555555 delta 1069416 +---- VST3 (single 3-element structure from one lane) ---- +vst3.32 {d0[0],d1[0],d2[0]} :: Result 0x121f1e1f 0x252a2e2b 0x232f2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.32 {d0[1],d1[1],d2[1]} :: Result 0x131b1a1b 0x262d2d2a 0x242c2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069420 +vst3.32 {d0[0],d2[0],d4[0]} :: Result 0x121f1e1f 0x252a2e2b 0x232f2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069424 +vst3.32 {d0[1],d2[1],d4[1]} :: Result 0x131b1a1b 0x262d2d2a 0x242c2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069428 +vst3.16 {d1[0],d2[0],d3[0]} :: Result 0x2e2b1e1f 0x55552e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.16 {d1[1],d2[1],d3[1]} :: Result 0x252a121f 0x5555232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.16 {d1[2],d2[2],d3[2]} :: Result 0x2d2a1a1b 0x55552b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.16 {d1[3],d2[3],d3[3]} :: Result 0x262d131b 0x5555242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.16 {d1[0],d3[0],d5[0]} :: Result 0x2e2f1e1f 0x55552e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.16 {d1[1],d3[1],d5[1]} :: Result 0x232f121f 0x5555252a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.16 {d1[2],d3[2],d5[2]} :: Result 0x2b2b1a1b 0x55552d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.16 {d1[3],d3[3],d5[3]} :: Result 0x242c131b 0x5555262d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.8 {d0[7],d1[7],d2[7]} :: Result 0x55242613 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.8 {d1[6],d2[6],d3[6]} :: Result 0x552c2d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.8 {d0[5],d1[5],d2[5]} :: Result 0x552b2d1a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.8 {d0[4],d1[4],d2[4]} :: Result 0x552b2a1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.8 {d20[3],d21[3],d22[3]} :: Result 0x55232512 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.8 {d0[2],d1[2],d2[2]} :: Result 0x552f2a1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.8 {d17[1],d18[1],d19[1]} :: Result 0x552e2e1e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst3.8 {d29[0],d30[0],d31[0]} :: Result 0x552b1f2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +---- VST4 (multiple 4-elements) ---- +vst4.8 {d0-d3} :: Result 0x2b2f1c1f 0x2e2e1f1e 0x2a2f1c1f 0x25231412 0x2a2b1d1b 0x2d2b191a 0x2d2c1d1b 0x26241513 delta 1069416 +vst4.16 {d20-d23} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 1069420 +vst4.32 {d0-d3} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 1069424 +vst4.8 {d0,d2,d4,d6} :: Result 0x2b2f1c1f 0x2e2e1f1e 0x2a2f1c1f 0x25231412 0x2a2b1d1b 0x2d2b191a 0x2d2c1d1b 0x26241513 delta 1069428 +vst4.16 {d1,d3,d5,d7} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c delta 1069416 +vst4.32 {d20,d22,d24,d26} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a delta 1069416 +---- VST4 (single 4-element structure from one lane) ---- +vst4.32 {d0[0],d1[0],d2[0],d3[0]} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.32 {d0[1],d1[1],d2[1],d3[1]} :: Result 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069420 +vst4.32 {d0[0],d2[0],d4[0],d6[0]} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069424 +vst4.32 {d0[1],d2[1],d4[1],d6[1]} :: Result 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069428 +vst4.16 {d1[0],d2[0],d3[0],d4[0]} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.16 {d1[1],d2[1],d3[1],d4[1]} :: Result 0x141c121f 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.16 {d1[2],d2[2],d3[2],d4[2]} :: Result 0x191d1a1b 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.16 {d1[3],d2[3],d3[3],d4[3]} :: Result 0x151d131b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.16 {d1[0],d3[0],d5[0],d7[0]} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.16 {d1[1],d3[1],d5[1],d7[1]} :: Result 0x141c121f 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.16 {d1[2],d3[2],d5[2],d7[2]} :: Result 0x191d1a1b 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.16 {d1[3],d3[3],d5[3],d7[3]} :: Result 0x151d131b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.8 {d0[7],d1[7],d2[7],d3[7]} :: Result 0x26241513 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.8 {d1[6],d2[6],d3[6],d4[6]} :: Result 0x2d2c1d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.8 {d0[5],d1[5],d2[5],d3[5]} :: Result 0x2d2b191a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.8 {d0[4],d1[4],d2[4],d3[4]} :: Result 0x2a2b1d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.8 {d20[3],d21[3],d22[3],d23[3]} :: Result 0x25231412 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.8 {d0[2],d1[2],d2[2],d3[2]} :: Result 0x2a2f1c1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.8 {d17[1],d18[1],d19[1],d20[1]} :: Result 0x2e2e1f1e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +vst4.8 {d28[0],d29[0],d30[0],d31[0]} :: Result 0x2b2f1c1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 delta 1069416 +---- VMOVN ---- +vmovn.i32 d0, q0 :: Qd 0x00240024 0x00320032 Qm (i32)0x00000032 Qn (i32)0x00000024 +vmovn.i32 d0, q0 :: Qd 0x00240024 0x55555555 Qm (i32)0x00000032 Qn (i32)0x00000024 +vmovn.i16 d7, q5 :: Qd 0x00240024 0x00320032 Qm (i32)0x00000032 Qn (i32)0x00000024 +vmovn.i16 d7, q5 :: Qd 0x00240024 0x1b1b1f1f Qm (i32)0x00000032 Qn (i32)0x00000024 +vmovn.i64 d31, q0 :: Qd 0x00000024 0x00000032 Qm (i32)0x00000032 Qn (i32)0x00000024 +vmovn.i64 d31, q0 :: Qd 0x00000024 0x121f1e1f Qm (i32)0x00000032 Qn (i32)0x00000024 +vmovn.i32 d0, q0 :: Qd 0xf0f0f0f0 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000f0 +vmovn.i32 d0, q0 :: Qd 0xf0f0f0f0 0x55555555 Qm (i8)0x000000ff Qn (i8)0x000000f0 +vmovn.i16 d7, q5 :: Qd 0xefefefef 0xadadadad Qm (i16)0x0000dead Qn (i16)0x0000beef +vmovn.i16 d7, q5 :: Qd 0xefefefef 0x1b1b1f1f Qm (i16)0x0000dead Qn (i16)0x0000beef +vmovn.i64 d31, q0 :: Qd 0x24242424 0xff00fe0f Qm (i32)0xff00fe0f Qn (i8)0x00000024 +vmovn.i64 d31, q0 :: Qd 0x24242424 0x121f1e1f Qm (i32)0xff00fe0f Qn (i8)0x00000024 +---- VQMOVN ---- +vqmovn.u32 d0, q0 :: Qd 0x00240024 0x00320032 Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 00000000 +vqmovn.u32 d0, q0 :: Qd 0x00240024 0xffffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovn.u16 d7, q5 :: Qd 0x00240024 0x00320032 Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 00000000 +vqmovn.u16 d7, q5 :: Qd 0x00240024 0xffffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovn.u64 d31, q0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovn.u64 d31, q0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovn.u32 d0, q0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000f0 fpscr: 08000000 +vqmovn.u32 d0, q0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000f0 fpscr: 08000000 +vqmovn.u16 d7, q5 :: Qd 0xffffffff 0xffffffff Qm (i16)0x0000dead Qn (i16)0x0000beef fpscr: 08000000 +vqmovn.u16 d7, q5 :: Qd 0xffffffff 0xffffffff Qm (i16)0x0000dead Qn (i16)0x0000beef fpscr: 08000000 +vqmovn.u64 d31, q0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff00fe0f Qn (i8)0x00000024 fpscr: 08000000 +vqmovn.u64 d31, q0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff00fe0f Qn (i8)0x00000024 fpscr: 08000000 +vqmovn.s32 d0, q0 :: Qd 0x00240024 0x00320032 Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 00000000 +vqmovn.s32 d0, q0 :: Qd 0x00240024 0x7fff7fff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovn.s16 d7, q5 :: Qd 0x00240024 0x00320032 Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 00000000 +vqmovn.s16 d7, q5 :: Qd 0x00240024 0x7f7f7f7f Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovn.s64 d31, q0 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovn.s64 d31, q0 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovn.s32 d0, q0 :: Qd 0x80008000 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000f0 fpscr: 08000000 +vqmovn.s32 d0, q0 :: Qd 0x80008000 0x7fff7fff Qm (i8)0x000000ff Qn (i8)0x000000f0 fpscr: 08000000 +vqmovn.s16 d7, q5 :: Qd 0x80808080 0x80808080 Qm (i16)0x0000dead Qn (i16)0x0000beef fpscr: 08000000 +vqmovn.s16 d7, q5 :: Qd 0x80808080 0x7f7f7f7f Qm (i16)0x0000dead Qn (i16)0x0000beef fpscr: 08000000 +vqmovn.s64 d31, q0 :: Qd 0x7fffffff 0x80000000 Qm (i32)0xff00fe0f Qn (i8)0x00000024 fpscr: 08000000 +vqmovn.s64 d31, q0 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xff00fe0f Qn (i8)0x00000024 fpscr: 08000000 +vqmovn.s32 d0, q0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff fpscr: 00000000 +vqmovn.s32 d0, q0 :: Qd 0xffffffff 0x7fff7fff Qm (i8)0x000000ff Qn (i8)0x000000ff fpscr: 08000000 +vqmovn.s16 d7, q5 :: Qd 0x7f7f7f7f 0xffffffff Qm (i8)0x000000ff Qn (i16)0x000000ff fpscr: 08000000 +vqmovn.s16 d7, q5 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i8)0x000000ff Qn (i16)0x000000ff fpscr: 08000000 +vqmovn.s64 d31, q0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff fpscr: 00000000 +vqmovn.s64 d31, q0 :: Qd 0xffffffff 0x7fffffff Qm (i8)0x000000ff Qn (i8)0x000000ff fpscr: 08000000 +---- VQMOVN ---- +vqmovun.s32 d0, q0 :: Qd 0x00240024 0x00320032 Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 00000000 +vqmovun.s32 d0, q0 :: Qd 0x00240024 0xffffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovun.s16 d7, q5 :: Qd 0x00240024 0x00320032 Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 00000000 +vqmovun.s16 d7, q5 :: Qd 0x00240024 0xffffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovun.s64 d31, q0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovun.s64 d31, q0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000032 Qn (i32)0x00000024 fpscr: 08000000 +vqmovun.s32 d0, q0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000f0 fpscr: 08000000 +vqmovun.s32 d0, q0 :: Qd 0x00000000 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000f0 fpscr: 08000000 +vqmovun.s16 d7, q5 :: Qd 0x00000000 0x00000000 Qm (i16)0x0000dead Qn (i16)0x0000beef fpscr: 08000000 +vqmovun.s16 d7, q5 :: Qd 0x00000000 0xffffffff Qm (i16)0x0000dead Qn (i16)0x0000beef fpscr: 08000000 +vqmovun.s64 d31, q0 :: Qd 0xffffffff 0x00000000 Qm (i32)0xff00fe0f Qn (i8)0x00000024 fpscr: 08000000 +vqmovun.s64 d31, q0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff00fe0f Qn (i8)0x00000024 fpscr: 08000000 +vqmovun.s32 d0, q0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff fpscr: 08000000 +vqmovun.s32 d0, q0 :: Qd 0x00000000 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff fpscr: 08000000 +vqmovun.s16 d7, q5 :: Qd 0xffffffff 0x00000000 Qm (i8)0x000000ff Qn (i16)0x000000ff fpscr: 08000000 +vqmovun.s16 d7, q5 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i16)0x000000ff fpscr: 08000000 +vqmovun.s64 d31, q0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff fpscr: 08000000 +vqmovun.s64 d31, q0 :: Qd 0x00000000 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff fpscr: 08000000 +---- VABS ---- +vabs.s32 d0, d1 :: Qd 0x00000073 0x00000073 Qm (i32)0x00000073 +vabs.s32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000073 +vabs.s16 d15, d4 :: Qd 0x00000073 0x00000073 Qm (i32)0x00000073 +vabs.s16 d15, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000073 +vabs.s8 d8, d7 :: Qd 0x00000073 0x00000073 Qm (i32)0x00000073 +vabs.s8 d8, d7 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000073 +vabs.s32 d0, d1 :: Qd 0x000000fe 0x000000fe Qm (i32)0x000000fe +vabs.s32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x000000fe +vabs.s16 d31, d4 :: Qd 0x000000ef 0x000000ef Qm (i32)0x000000ef +vabs.s16 d31, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x000000ef +vabs.s8 d8, d7 :: Qd 0x00000022 0x00000022 Qm (i32)0x000000de +vabs.s8 d8, d7 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x000000de +vabs.s32 d0, d1 :: Qd 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a +vabs.s32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i16)0x0000fe0a +vabs.s16 d15, d4 :: Qd 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b +vabs.s16 d15, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i16)0x0000ef0b +vabs.s8 d8, d7 :: Qd 0x220c220c 0x220c220c Qm (i16)0x0000de0c +vabs.s8 d8, d7 :: Qd 0x151d191d 0x141c1f1c Qm (i16)0x0000de0c +---- VQABS ---- +vqabs.s32 d0, d1 :: Qd 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr 00000000 +vqabs.s32 d0, d1 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000073 fpscr 00000000 +vqabs.s32 d0, d1 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x80000000 fpscr 08000000 +vqabs.s32 d0, d1 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000000 fpscr 00000000 +vqabs.s16 d0, d1 :: Qd 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 fpscr 08000000 +vqabs.s16 d0, d1 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000000 fpscr 00000000 +vqabs.s8 d0, d1 :: Qd 0x7f000000 0x7f000000 Qm (i32)0x80000000 fpscr 08000000 +vqabs.s8 d0, d1 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x80000000 fpscr 00000000 +vqabs.s16 d15, d4 :: Qd 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr 00000000 +vqabs.s16 d15, d4 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000073 fpscr 00000000 +vqabs.s8 d8, d7 :: Qd 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr 00000000 +vqabs.s8 d8, d7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000073 fpscr 00000000 +vqabs.s32 d0, d1 :: Qd 0x000000fe 0x000000fe Qm (i32)0x000000fe fpscr 00000000 +vqabs.s32 d0, d1 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x000000fe fpscr 00000000 +vqabs.s16 d31, d4 :: Qd 0x000000ef 0x000000ef Qm (i32)0x000000ef fpscr 00000000 +vqabs.s16 d31, d4 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x000000ef fpscr 00000000 +vqabs.s8 d8, d7 :: Qd 0x00000022 0x00000022 Qm (i32)0x000000de fpscr 00000000 +vqabs.s8 d8, d7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x000000de fpscr 00000000 +vqabs.s32 d0, d1 :: Qd 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a fpscr 00000000 +vqabs.s32 d0, d1 :: Qd 0x131b1a1b 0x121f1e1f Qm (i16)0x0000fe0a fpscr 00000000 +vqabs.s16 d15, d4 :: Qd 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b fpscr 00000000 +vqabs.s16 d15, d4 :: Qd 0x131b1a1b 0x121f1e1f Qm (i16)0x0000ef0b fpscr 00000000 +vqabs.s8 d8, d7 :: Qd 0x220c220c 0x220c220c Qm (i16)0x0000de0c fpscr 00000000 +vqabs.s8 d8, d7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i16)0x0000de0c fpscr 00000000 +---- VADDHN ---- +vaddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vaddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vaddhn.i16 d0, q1, q2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vaddhn.i16 d0, q1, q2 :: Qd 0x1519141f 0x131a121e Qm (i32)0x00000073 Qn (i32)0x00000072 +vaddhn.i32 d0, q1, q2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vaddhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i32)0x00000073 Qn (i32)0x00000072 +vaddhn.i64 d0, q1, q2 :: Qd 0x000000e5 0x000000e5 Qm (i32)0x00000073 Qn (i32)0x00000072 +vaddhn.i64 d0, q1, q2 :: Qd 0x151d198f 0x131b1a8d Qm (i32)0x00000073 Qn (i32)0x00000072 +vaddhn.i16 d0, q15, q2 :: Qd 0xeff0eff0 0xeff0eff0 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vaddhn.i16 d0, q15, q2 :: Qd 0x151a1420 0x131b121f Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vaddhn.i32 d31, q1, q2 :: Qd 0xef73ef73 0xef73ef73 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vaddhn.i32 d31, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vaddhn.i64 d0, q1, q8 :: Qd 0xef73f0e5 0xef73f0e5 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vaddhn.i64 d0, q1, q8 :: Qd 0x151d1a8f 0x131b1b8d Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vaddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000072 +vaddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000072 +vaddhn.i16 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000072 +vaddhn.i16 d0, q1, q2 :: Qd 0x1519141f 0x131a121e Qm (i8)0x00000073 Qn (i32)0x00000072 +vaddhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000072 +vaddhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i8)0x00000073 Qn (i32)0x00000072 +vaddhn.i64 d0, q1, q2 :: Qd 0x737373e5 0x737373e5 Qm (i8)0x00000073 Qn (i32)0x00000072 +vaddhn.i64 d0, q1, q2 :: Qd 0x151d198f 0x131b1a8d Qm (i8)0x00000073 Qn (i32)0x00000072 +---- VRADDHN ---- +vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vraddhn.i16 d0, q1, q2 :: Qd 0x00010001 0x00010001 Qm (i32)0x00000073 Qn (i32)0x00000072 +vraddhn.i16 d0, q1, q2 :: Qd 0x151a1420 0x131b121f Qm (i32)0x00000073 Qn (i32)0x00000072 +vraddhn.i32 d0, q1, q2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vraddhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i32)0x00000073 Qn (i32)0x00000072 +vraddhn.i64 d0, q1, q2 :: Qd 0x000000e5 0x000000e5 Qm (i32)0x00000073 Qn (i32)0x00000072 +vraddhn.i64 d0, q1, q2 :: Qd 0x151d198f 0x131b1a8d Qm (i32)0x00000073 Qn (i32)0x00000072 +vraddhn.i16 d0, q15, q2 :: Qd 0xeff1eff1 0xeff1eff1 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vraddhn.i16 d0, q15, q2 :: Qd 0x151b1421 0x131c1220 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vraddhn.i32 d31, q1, q2 :: Qd 0xef74ef74 0xef74ef74 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vraddhn.i32 d31, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vraddhn.i64 d0, q1, q8 :: Qd 0xef73f0e6 0xef73f0e6 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vraddhn.i64 d0, q1, q8 :: Qd 0x151d1a8f 0x131b1b8d Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000072 +vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000072 +vraddhn.i16 d0, q1, q2 :: Qd 0x73747374 0x73747374 Qm (i8)0x00000073 Qn (i32)0x00000072 +vraddhn.i16 d0, q1, q2 :: Qd 0x151a1420 0x131b121f Qm (i8)0x00000073 Qn (i32)0x00000072 +vraddhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000072 +vraddhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i8)0x00000073 Qn (i32)0x00000072 +vraddhn.i64 d0, q1, q2 :: Qd 0x737373e5 0x737373e5 Qm (i8)0x00000073 Qn (i32)0x00000072 +vraddhn.i64 d0, q1, q2 :: Qd 0x151d198f 0x131b1a8d Qm (i8)0x00000073 Qn (i32)0x00000072 +vraddhn.i16 d0, q15, q2 :: Qd 0xeff0eff0 0xeff0eff0 Qm (i16)0x0000ef73 Qn (i32)0x00000102 +vraddhn.i16 d0, q15, q2 :: Qd 0x151a1420 0x131b121f Qm (i16)0x0000ef73 Qn (i32)0x00000102 +vraddhn.i32 d31, q1, q2 :: Qd 0xef74ef74 0xef74ef74 Qm (i16)0x0000ef73 Qn (i32)0x00000102 +vraddhn.i32 d31, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i16)0x0000ef73 Qn (i32)0x00000102 +vraddhn.i64 d0, q1, q8 :: Qd 0xef73f076 0xef73f076 Qm (i16)0x0000ef73 Qn (i32)0x00000102 +vraddhn.i64 d0, q1, q8 :: Qd 0x151d1a1f 0x131b1b1d Qm (i16)0x0000ef73 Qn (i32)0x00000102 +vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000002 +vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000002 +vraddhn.i16 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000002 +vraddhn.i16 d0, q1, q2 :: Qd 0x1519141f 0x131a121e Qm (i8)0x00000073 Qn (i32)0x00000002 +vraddhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000002 +vraddhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i8)0x00000073 Qn (i32)0x00000002 +vraddhn.i64 d0, q1, q2 :: Qd 0x73737375 0x73737375 Qm (i8)0x00000073 Qn (i32)0x00000002 +vraddhn.i64 d0, q1, q2 :: Qd 0x151d191f 0x131b1a1d Qm (i8)0x00000073 Qn (i32)0x00000002 +---- VSUBHN ---- +vsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vsubhn.i16 d0, q1, q2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vsubhn.i16 d0, q1, q2 :: Qd 0x1518141e 0x1319121d Qm (i32)0x00000073 Qn (i32)0x00000072 +vsubhn.i32 d0, q1, q2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vsubhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i32)0x00000073 Qn (i32)0x00000072 +vsubhn.i64 d0, q1, q2 :: Qd 0x00000001 0x00000001 Qm (i32)0x00000073 Qn (i32)0x00000072 +vsubhn.i64 d0, q1, q2 :: Qd 0x151d18ab 0x131b19a9 Qm (i32)0x00000073 Qn (i32)0x00000072 +vsubhn.i16 d0, q15, q2 :: Qd 0xefeeefee 0xefeeefee Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vsubhn.i16 d0, q15, q2 :: Qd 0x1517141d 0x1318121c Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vsubhn.i32 d31, q1, q2 :: Qd 0xef73ef73 0xef73ef73 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vsubhn.i32 d31, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vsubhn.i64 d0, q1, q8 :: Qd 0xef73ee01 0xef73ee01 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vsubhn.i64 d0, q1, q8 :: Qd 0x151d17ab 0x131b18a9 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000072 +vsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000072 +vsubhn.i16 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000072 +vsubhn.i16 d0, q1, q2 :: Qd 0x1518141e 0x1319121d Qm (i8)0x00000073 Qn (i32)0x00000072 +vsubhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000072 +vsubhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i8)0x00000073 Qn (i32)0x00000072 +vsubhn.i64 d0, q1, q2 :: Qd 0x73737301 0x73737301 Qm (i8)0x00000073 Qn (i32)0x00000072 +vsubhn.i64 d0, q1, q2 :: Qd 0x151d18ab 0x131b19a9 Qm (i8)0x00000073 Qn (i32)0x00000072 +---- VRSUBHN ---- +vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vrsubhn.i16 d0, q1, q2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vrsubhn.i16 d0, q1, q2 :: Qd 0x1519141f 0x131a121e Qm (i32)0x00000073 Qn (i32)0x00000072 +vrsubhn.i32 d0, q1, q2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000073 Qn (i32)0x00000072 +vrsubhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i32)0x00000073 Qn (i32)0x00000072 +vrsubhn.i64 d0, q1, q2 :: Qd 0x00000001 0x00000001 Qm (i32)0x00000073 Qn (i32)0x00000072 +vrsubhn.i64 d0, q1, q2 :: Qd 0x151d18ab 0x131b19a9 Qm (i32)0x00000073 Qn (i32)0x00000072 +vrsubhn.i16 d0, q15, q2 :: Qd 0xefeeefee 0xefeeefee Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vrsubhn.i16 d0, q15, q2 :: Qd 0x1518141e 0x1319121d Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vrsubhn.i32 d31, q1, q2 :: Qd 0xef74ef74 0xef74ef74 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vrsubhn.i32 d31, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vrsubhn.i64 d0, q1, q8 :: Qd 0xef73ee02 0xef73ee02 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vrsubhn.i64 d0, q1, q8 :: Qd 0x151d17ab 0x131b18a9 Qm (i16)0x0000ef73 Qn (i32)0x00000172 +vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000072 +vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000073 Qn (i32)0x00000072 +vrsubhn.i16 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000072 +vrsubhn.i16 d0, q1, q2 :: Qd 0x1519141f 0x131a121e Qm (i8)0x00000073 Qn (i32)0x00000072 +vrsubhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373 Qm (i8)0x00000073 Qn (i32)0x00000072 +vrsubhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i8)0x00000073 Qn (i32)0x00000072 +vrsubhn.i64 d0, q1, q2 :: Qd 0x73737301 0x73737301 Qm (i8)0x00000073 Qn (i32)0x00000072 +vrsubhn.i64 d0, q1, q2 :: Qd 0x151d18ab 0x131b19a9 Qm (i8)0x00000073 Qn (i32)0x00000072 +vrsubhn.i16 d0, q15, q2 :: Qd 0xf0eff0ef 0xf0eff0ef Qm (i16)0x0000ef93 Qn (i32)0x00000102 +vrsubhn.i16 d0, q15, q2 :: Qd 0x1518141e 0x1319121d Qm (i16)0x0000ef93 Qn (i32)0x00000102 +vrsubhn.i32 d31, q1, q2 :: Qd 0xef94ef94 0xef94ef94 Qm (i16)0x0000ef93 Qn (i32)0x00000102 +vrsubhn.i32 d31, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i16)0x0000ef93 Qn (i32)0x00000102 +vrsubhn.i64 d0, q1, q8 :: Qd 0xef93ee92 0xef93ee92 Qm (i16)0x0000ef93 Qn (i32)0x00000102 +vrsubhn.i64 d0, q1, q8 :: Qd 0x151d181b 0x131b1919 Qm (i16)0x0000ef93 Qn (i32)0x00000102 +vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000093 Qn (i32)0x00000002 +vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000093 Qn (i32)0x00000002 +vrsubhn.i16 d0, q1, q2 :: Qd 0x94949494 0x94949494 Qm (i8)0x00000093 Qn (i32)0x00000002 +vrsubhn.i16 d0, q1, q2 :: Qd 0x1519141f 0x131a121e Qm (i8)0x00000093 Qn (i32)0x00000002 +vrsubhn.i32 d0, q1, q2 :: Qd 0x93949394 0x93949394 Qm (i8)0x00000093 Qn (i32)0x00000002 +vrsubhn.i32 d0, q1, q2 :: Qd 0x151d141c 0x131b121f Qm (i8)0x00000093 Qn (i32)0x00000002 +vrsubhn.i64 d0, q1, q2 :: Qd 0x93939392 0x93939392 Qm (i8)0x00000093 Qn (i32)0x00000002 +vrsubhn.i64 d0, q1, q2 :: Qd 0x151d191b 0x131b1a19 Qm (i8)0x00000093 Qn (i32)0x00000002 +---- VCEQ #0 ---- +vceq.i32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vceq.i32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vceq.i16 d2, d1, #0 :: Qd 0xffff0000 0xffff0000 Qm (i32)0x00000021 +vceq.i16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vceq.i8 d10, d11, #0 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x00000021 +vceq.i8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vceq.i32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.i32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vceq.i16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.i16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vceq.i8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.i8 d10, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +---- VCGT #0 ---- +vcgt.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcgt.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcgt.s16 d2, d1, #0 :: Qd 0x0000ffff 0x0000ffff Qm (i32)0x00000021 +vcgt.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcgt.s8 d10, d31, #0 :: Qd 0x000000ff 0x000000ff Qm (i32)0x00000021 +vcgt.s8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcgt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ef +vcgt.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ef +vcgt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ed +vcgt.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ed +vcgt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ae +vcgt.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ae +---- VCGE #0 ---- +vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000021 +vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ef +vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ef +vcge.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ed +vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ed +vcge.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ae +vcge.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ae +vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000000ef +vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000000ef +vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000000ed +vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000000ed +vcge.s8 d10, d11, #0 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x000000ae +vcge.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000000ae +---- VCLE #0 ---- +vcle.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vcle.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vcle.s16 d2, d1, #0 :: Qd 0xffff0000 0xffff0000 Qm (i32)0x00000021 +vcle.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vcle.s8 d10, d11, #0 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x00000021 +vcle.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vcle.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.s8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.s8 d10, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ef +vcle.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ef +vcle.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ed +vcle.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ed +vcle.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ae +vcle.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ae +---- VCLT #0 ---- +vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021 +vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ef +vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ef +vclt.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ed +vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ed +vclt.s8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ae +vclt.s8 d10, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ae +vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x000000ef +vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x000000ef +vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x000000ed +vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x000000ed +vclt.s8 d10, d11, #0 :: Qd 0x000000ff 0x000000ff Qm (i32)0x000000ae +vclt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x000000ae +---- VCNT ---- +vcnt.8 d0, d1 :: Qd 0x04050306 0x04050306 Qm (i32)0xac3d25eb +vcnt.8 d0, d1 :: Qd 0x03040304 0x02030503 Qm (i32)0xac3d25eb +vcnt.8 d11, d14 :: Qd 0x04050306 0x04050306 Qm (i32)0xac3d25eb +vcnt.8 d11, d14 :: Qd 0x03040304 0x02030503 Qm (i32)0xac3d25eb +vcnt.8 d6, d2 :: Qd 0x00020306 0x00020306 Qm (i32)0x000ad0eb +vcnt.8 d6, d2 :: Qd 0x03040304 0x02030503 Qm (i32)0x000ad0eb +---- VCLS ---- +vcls.s8 d0, d1 :: Qd 0x07070701 0x07070701 Qm (i32)0x00000021 +vcls.s8 d0, d1 :: Qd 0x02020202 0x02020202 Qm (i32)0x00000021 +vcls.s8 d30, d31 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000082 +vcls.s8 d30, d31 :: Qd 0x02020202 0x02020202 Qm (i8)0x00000082 +vcls.s16 d0, d1 :: Qd 0x000f0009 0x000f0009 Qm (i32)0x00000021 +vcls.s16 d0, d1 :: Qd 0x00020002 0x00020002 Qm (i32)0x00000021 +vcls.s16 d31, d30 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000082 +vcls.s16 d31, d30 :: Qd 0x00020002 0x00020002 Qm (i8)0x00000082 +vcls.s32 d6, d1 :: Qd 0x00000019 0x00000019 Qm (i32)0x00000021 +vcls.s32 d6, d1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000021 +vcls.s32 d30, d5 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000082 +vcls.s32 d30, d5 :: Qd 0x00000002 0x00000002 Qm (i8)0x00000082 +vcls.s8 d2, d4 :: Qd 0x07070707 0x07070707 Qm (i8)0x000000ff +vcls.s8 d2, d4 :: Qd 0x02020202 0x02020202 Qm (i8)0x000000ff +vcls.s16 d2, d4 :: Qd 0x000f000f 0x000f000f Qm (i8)0x000000ff +vcls.s16 d2, d4 :: Qd 0x00020002 0x00020002 Qm (i8)0x000000ff +vcls.s32 d2, d4 :: Qd 0x0000001f 0x0000001f Qm (i8)0x000000ff +vcls.s32 d2, d4 :: Qd 0x00000002 0x00000002 Qm (i8)0x000000ff +vcls.s8 d2, d4 :: Qd 0x07020702 0x07020702 Qm (i16)0x0000ffef +vcls.s8 d2, d4 :: Qd 0x02020202 0x02020202 Qm (i16)0x0000ffef +vcls.s16 d2, d4 :: Qd 0x000a000a 0x000a000a Qm (i16)0x0000ffef +vcls.s16 d2, d4 :: Qd 0x00020002 0x00020002 Qm (i16)0x0000ffef +vcls.s32 d2, d4 :: Qd 0x0000000a 0x0000000a Qm (i16)0x0000ffef +vcls.s32 d2, d4 :: Qd 0x00000002 0x00000002 Qm (i16)0x0000ffef +vcls.s8 d2, d4 :: Qd 0x07070707 0x07070707 Qm (i8)0x00000000 +vcls.s8 d2, d4 :: Qd 0x02020202 0x02020202 Qm (i8)0x00000000 +vcls.s16 d2, d4 :: Qd 0x000f000f 0x000f000f Qm (i8)0x00000000 +vcls.s16 d2, d4 :: Qd 0x00020002 0x00020002 Qm (i8)0x00000000 +vcls.s32 d2, d4 :: Qd 0x0000001f 0x0000001f Qm (i8)0x00000000 +vcls.s32 d2, d4 :: Qd 0x00000002 0x00000002 Qm (i8)0x00000000 +vcls.s8 d2, d4 :: Qd 0x07020702 0x07020702 Qm (i16)0x000000ef +vcls.s8 d2, d4 :: Qd 0x02020202 0x02020202 Qm (i16)0x000000ef +vcls.s16 d2, d4 :: Qd 0x00070007 0x00070007 Qm (i16)0x000000ef +vcls.s16 d2, d4 :: Qd 0x00020002 0x00020002 Qm (i16)0x000000ef +vcls.s32 d2, d4 :: Qd 0x00000007 0x00000007 Qm (i16)0x000000ef +vcls.s32 d2, d4 :: Qd 0x00000002 0x00000002 Qm (i16)0x000000ef +---- VCLZ ---- +vclz.i8 d0, d1 :: Qd 0x08080802 0x08080802 Qm (i32)0x00000021 +vclz.i8 d0, d1 :: Qd 0x03030303 0x03030303 Qm (i32)0x00000021 +vclz.i8 d30, d31 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000082 +vclz.i8 d30, d31 :: Qd 0x03030303 0x03030303 Qm (i8)0x00000082 +vclz.i16 d0, d1 :: Qd 0x0010000a 0x0010000a Qm (i32)0x00000021 +vclz.i16 d0, d1 :: Qd 0x00030003 0x00030003 Qm (i32)0x00000021 +vclz.i16 d31, d30 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000082 +vclz.i16 d31, d30 :: Qd 0x00030003 0x00030003 Qm (i8)0x00000082 +vclz.i32 d6, d1 :: Qd 0x0000001a 0x0000001a Qm (i32)0x00000021 +vclz.i32 d6, d1 :: Qd 0x00000003 0x00000003 Qm (i32)0x00000021 +vclz.i32 d30, d5 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000082 +vclz.i32 d30, d5 :: Qd 0x00000003 0x00000003 Qm (i8)0x00000082 +vclz.i8 d2, d4 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff +vclz.i8 d2, d4 :: Qd 0x03030303 0x03030303 Qm (i8)0x000000ff +vclz.i16 d2, d4 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff +vclz.i16 d2, d4 :: Qd 0x00030003 0x00030003 Qm (i8)0x000000ff +vclz.i32 d2, d4 :: Qd 0x00000000 0x00000000 Qm (i8)0x000000ff +vclz.i32 d2, d4 :: Qd 0x00000003 0x00000003 Qm (i8)0x000000ff +vclz.i8 d2, d4 :: Qd 0x00000000 0x00000000 Qm (i16)0x0000ffef +vclz.i8 d2, d4 :: Qd 0x03030303 0x03030303 Qm (i16)0x0000ffef +vclz.i16 d2, d4 :: Qd 0x00000000 0x00000000 Qm (i16)0x0000ffef +vclz.i16 d2, d4 :: Qd 0x00030003 0x00030003 Qm (i16)0x0000ffef +vclz.i32 d2, d4 :: Qd 0x00000000 0x00000000 Qm (i16)0x0000ffef +vclz.i32 d2, d4 :: Qd 0x00000003 0x00000003 Qm (i16)0x0000ffef +vclz.i8 d2, d4 :: Qd 0x08080808 0x08080808 Qm (i8)0x00000000 +vclz.i8 d2, d4 :: Qd 0x03030303 0x03030303 Qm (i8)0x00000000 +vclz.i16 d2, d4 :: Qd 0x00100010 0x00100010 Qm (i8)0x00000000 +vclz.i16 d2, d4 :: Qd 0x00030003 0x00030003 Qm (i8)0x00000000 +vclz.i32 d2, d4 :: Qd 0x00000020 0x00000020 Qm (i8)0x00000000 +vclz.i32 d2, d4 :: Qd 0x00000003 0x00000003 Qm (i8)0x00000000 +vclz.i8 d2, d4 :: Qd 0x08000800 0x08000800 Qm (i16)0x000000ef +vclz.i8 d2, d4 :: Qd 0x03030303 0x03030303 Qm (i16)0x000000ef +vclz.i16 d2, d4 :: Qd 0x00080008 0x00080008 Qm (i16)0x000000ef +vclz.i16 d2, d4 :: Qd 0x00030003 0x00030003 Qm (i16)0x000000ef +vclz.i32 d2, d4 :: Qd 0x00000008 0x00000008 Qm (i16)0x000000ef +vclz.i32 d2, d4 :: Qd 0x00000003 0x00000003 Qm (i16)0x000000ef +---- VSLI ---- +vsli.16 d0, d1, #1 :: Qd 0x0001000f 0x0001000f Qm (i32)0x00000007 +vsli.16 d0, d1, #1 :: Qd 0x2a3b323b 0x28393e39 Qm (i32)0x00000007 +vsli.16 d3, d4, #2 :: Qd 0xfffdfe11 0xfffdfe11 Qm (i32)0xffffff84 +vsli.16 d3, d4, #2 :: Qd 0x54776477 0x50737c73 Qm (i32)0xffffff84 +vsli.32 d2, d5, #31 :: Qd 0xd5555555 0xd5555555 Qm (i32)0xffffffff +vsli.32 d2, d5, #31 :: Qd 0x931b1a1b 0x121f1e1f Qm (i32)0xffffffff +vsli.8 d6, d7, #7 :: Qd 0x5555d5d5 0x5555d5d5 Qm (i32)0x0000ffff +vsli.8 d6, d7, #7 :: Qd 0x939b9a9b 0x121f9e1f Qm (i32)0x0000ffff +vsli.16 d8, d9, #12 :: Qd 0xf5556555 0xf5556555 Qm (i32)0xfffffff6 +vsli.16 d8, d9, #12 :: Qd 0xd31bda1b 0xc21fce1f Qm (i32)0xfffffff6 +vsli.32 d10, d11, #5 :: Qd 0x0004ff55 0x0004ff55 Qm (i32)0x000027fa +vsli.32 d10, d11, #5 :: Qd 0xa3a323bb 0x8383e39f Qm (i32)0x000027fa +vsli.8 d12, d13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vsli.8 d12, d13, #1 :: Qd 0x2b3b323b 0x28393e39 Qm (i32)0xffffffff +vsli.16 d14, d15, #11 :: Qd 0xfd55fd55 0xfd55fd55 Qm (i32)0xffffffff +vsli.16 d14, d15, #11 :: Qd 0xeb1bea1b 0xe21fe61f Qm (i32)0xffffffff +vsli.32 d10, d11, #9 :: Qd 0x0007d155 0x0007d155 Qm (i32)0x000003e8 +vsli.32 d10, d11, #9 :: Qd 0x3a323a1b 0x383e381f Qm (i32)0x000003e8 +vsli.8 d7, d13, #7 :: Qd 0xd5d5d5d5 0xd5d5d5d5 Qm (i32)0xffffffff +vsli.8 d7, d13, #7 :: Qd 0x939b9a9b 0x121f9e1f Qm (i32)0xffffffff +vsli.16 d8, d1, #1 :: Qd 0x0001579f 0x0001579f Qm (i32)0x0000abcf +vsli.16 d8, d1, #1 :: Qd 0x2a3b323b 0x28393e39 Qm (i32)0x0000abcf +vsli.32 d12, d3, #15 :: Qd 0xff285555 0xff285555 Qm (i32)0xfffffe50 +vsli.32 d12, d3, #15 :: Qd 0x8c8e9a1b 0x0f8e1e1f Qm (i32)0xfffffe50 +vsli.64 d0, d1, #42 :: Qd 0xfffffd55 0x55555555 Qm (i32)0xffffffff +vsli.64 d0, d1, #42 :: Qd 0x707c721b 0x121f1e1f Qm (i32)0xffffffff +vsli.64 d6, d7, #12 :: Qd 0x00fac000 0x00fac555 Qm (i32)0x00000fac +vsli.64 d6, d7, #12 :: Qd 0xd191d141 0xc1f1ce1f Qm (i32)0x00000fac +vsli.64 d8, d4, #9 :: Qd 0x0069f000 0x0069f155 Qm (i32)0x000034f8 +vsli.64 d8, d4, #9 :: Qd 0x3a323a28 0x383e381f Qm (i32)0x000034f8 +vsli.64 d9, d12, #11 :: Qd 0x0c0cb000 0x0c0cb555 Qm (i32)0x00018196 +vsli.64 d9, d12, #11 :: Qd 0xe8c8e8a0 0xe0f8e61f Qm (i32)0x00018196 +---- VPADD ---- +vpadd.i32 d0, d1, d2 :: Qd 0x000000f0 0x00000030 Qm (i32)0x00000018 Qn (i32)0x00000078 +vpadd.i32 d0, d1, d2 :: Qd 0x000000f0 0x253a383a Qm (i32)0x00000018 Qn (i32)0x00000078 +vpadd.i32 d0, d1, d2 :: Qd 0x000000f0 0x00000118 Qm (i32)0x0000008c Qn (i32)0x00000078 +vpadd.i32 d0, d1, d2 :: Qd 0x000000f0 0x253a383a Qm (i32)0x0000008c Qn (i32)0x00000078 +vpadd.i16 d0, d1, d2 :: Qd 0x00780078 0x008c008c Qm (i32)0x0000008c Qn (i32)0x00000078 +vpadd.i16 d0, d1, d2 :: Qd 0x00780078 0x2d36303e Qm (i32)0x0000008c Qn (i32)0x00000078 +vpadd.i8 d0, d1, d2 :: Qd 0x00780078 0x008c008c Qm (i32)0x0000008c Qn (i32)0x00000078 +vpadd.i8 d0, d1, d2 :: Qd 0x00780078 0x2e35313d Qm (i32)0x0000008c Qn (i32)0x00000078 +vpadd.i8 d0, d1, d2 :: Qd 0x80028002 0x80018001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpadd.i8 d0, d1, d2 :: Qd 0x80028002 0x2e35313d Qm (i32)0x80000001 Qn (i32)0x80000002 +vpadd.i16 d0, d1, d2 :: Qd 0x80028002 0x80018001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpadd.i16 d0, d1, d2 :: Qd 0x80028002 0x2d36303e Qm (i32)0x80000001 Qn (i32)0x80000002 +vpadd.i32 d0, d1, d2 :: Qd 0x00000004 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpadd.i32 d0, d1, d2 :: Qd 0x00000004 0x253a383a Qm (i32)0x80000001 Qn (i32)0x80000002 +vpadd.i32 d10, d11, d12 :: Qd 0x000000f0 0x00000030 Qm (i32)0x00000018 Qn (i32)0x00000078 +vpadd.i32 d10, d11, d12 :: Qd 0x000000f0 0x253a383a Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VPADDL ---- +vpaddl.u32 d0, d1 :: Qd 0x00000000 0x00000030 Qm (i32)0x00000018 +vpaddl.u32 d0, d1 :: Qd 0x00000000 0x29393839 Qm (i32)0x00000018 +vpaddl.u32 d0, d1 :: Qd 0x00000000 0x00000118 Qm (i32)0x0000008c +vpaddl.u32 d0, d1 :: Qd 0x00000000 0x29393839 Qm (i32)0x0000008c +vpaddl.u16 d0, d1 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c +vpaddl.u16 d0, d1 :: Qd 0x00002e3a 0x00003338 Qm (i32)0x0000008c +vpaddl.u8 d0, d1 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c +vpaddl.u8 d0, d1 :: Qd 0x00320036 0x0030003b Qm (i32)0x0000008c +vpaddl.u8 d0, d1 :: Qd 0x00800001 0x00800001 Qm (i32)0x80000001 +vpaddl.u8 d0, d1 :: Qd 0x00320036 0x0030003b Qm (i32)0x80000001 +vpaddl.u16 d0, d1 :: Qd 0x00008001 0x00008001 Qm (i32)0x80000001 +vpaddl.u16 d0, d1 :: Qd 0x00002e3a 0x00003338 Qm (i32)0x80000001 +vpaddl.u32 d0, d1 :: Qd 0x00000001 0x00000002 Qm (i32)0x80000001 +vpaddl.u32 d0, d1 :: Qd 0x00000000 0x29393839 Qm (i32)0x80000001 +vpaddl.u32 d10, d11 :: Qd 0x00000000 0x00000030 Qm (i32)0x00000018 +vpaddl.u32 d10, d11 :: Qd 0x00000000 0x29393839 Qm (i32)0x00000018 +vpaddl.s32 d0, d1 :: Qd 0x00000000 0x00000030 Qm (i32)0x00000018 +vpaddl.s32 d0, d1 :: Qd 0x00000000 0x29393839 Qm (i32)0x00000018 +vpaddl.s32 d0, d1 :: Qd 0x00000000 0x00000118 Qm (i32)0x0000008c +vpaddl.s32 d0, d1 :: Qd 0x00000000 0x29393839 Qm (i32)0x0000008c +vpaddl.s16 d0, d1 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c +vpaddl.s16 d0, d1 :: Qd 0x00002e3a 0x00003338 Qm (i32)0x0000008c +vpaddl.s8 d0, d1 :: Qd 0x0000ff8c 0x0000ff8c Qm (i32)0x0000008c +vpaddl.s8 d0, d1 :: Qd 0x00320036 0x0030003b Qm (i32)0x0000008c +vpaddl.s8 d0, d1 :: Qd 0xff800001 0xff800001 Qm (i32)0x80000001 +vpaddl.s8 d0, d1 :: Qd 0x00320036 0x0030003b Qm (i32)0x80000001 +vpaddl.s16 d0, d1 :: Qd 0xffff8001 0xffff8001 Qm (i32)0x80000001 +vpaddl.s16 d0, d1 :: Qd 0x00002e3a 0x00003338 Qm (i32)0x80000001 +vpaddl.s32 d0, d1 :: Qd 0xffffffff 0x00000002 Qm (i32)0x80000001 +vpaddl.s32 d0, d1 :: Qd 0x00000000 0x29393839 Qm (i32)0x80000001 +vpaddl.s32 d10, d11 :: Qd 0x00000000 0x00000030 Qm (i32)0x00000018 +vpaddl.s32 d10, d11 :: Qd 0x00000000 0x29393839 Qm (i32)0x00000018 +---- VPADAL ---- +vpadal.u32 d0, d1 :: Qd 0x55555555 0x55555585 Qm (i32)0x00000018 +vpadal.u32 d0, d1 :: Qd 0x131b1a1b 0x3b585658 Qm (i32)0x00000018 +vpadal.u32 d0, d1 :: Qd 0x55555555 0x5555566d Qm (i32)0x0000008c +vpadal.u32 d0, d1 :: Qd 0x131b1a1b 0x3b585658 Qm (i32)0x0000008c +vpadal.u16 d0, d1 :: Qd 0x555555e1 0x555555e1 Qm (i32)0x0000008c +vpadal.u16 d0, d1 :: Qd 0x131b4855 0x121f5157 Qm (i32)0x0000008c +vpadal.u8 d0, d1 :: Qd 0x566d566d 0x566d566d Qm (i8)0x0000008c +vpadal.u8 d0, d1 :: Qd 0x134d1a51 0x124f1e5a Qm (i8)0x0000008c +vpadal.u8 d0, d1 :: Qd 0x55d55556 0x55d55556 Qm (i32)0x80000001 +vpadal.u8 d0, d1 :: Qd 0x134d1a51 0x124f1e5a Qm (i32)0x80000001 +vpadal.u16 d0, d1 :: Qd 0x5555d556 0x5555d556 Qm (i32)0x80000001 +vpadal.u16 d0, d1 :: Qd 0x131b4855 0x121f5157 Qm (i32)0x80000001 +vpadal.u32 d0, d1 :: Qd 0x55555556 0x55555557 Qm (i32)0x80000001 +vpadal.u32 d0, d1 :: Qd 0x131b1a1b 0x3b585658 Qm (i32)0x80000001 +vpadal.u32 d10, d11 :: Qd 0x55555555 0x55555585 Qm (i32)0x00000018 +vpadal.u32 d10, d11 :: Qd 0x131b1a1b 0x3b585658 Qm (i32)0x00000018 +vpadal.s32 d0, d1 :: Qd 0x55555555 0x55555585 Qm (i32)0x00000018 +vpadal.s32 d0, d1 :: Qd 0x131b1a1b 0x3b585658 Qm (i32)0x00000018 +vpadal.s32 d0, d1 :: Qd 0x55555555 0x5555566d Qm (i32)0x0000008c +vpadal.s32 d0, d1 :: Qd 0x131b1a1b 0x3b585658 Qm (i32)0x0000008c +vpadal.s16 d0, d1 :: Qd 0x555555e1 0x555555e1 Qm (i32)0x0000008c +vpadal.s16 d0, d1 :: Qd 0x131b4855 0x121f5157 Qm (i32)0x0000008c +vpadal.s8 d0, d1 :: Qd 0x546d546d 0x546d546d Qm (i8)0x0000008c +vpadal.s8 d0, d1 :: Qd 0x134d1a51 0x124f1e5a Qm (i8)0x0000008c +vpadal.s8 d0, d1 :: Qd 0x54d55556 0x54d55556 Qm (i32)0x80000001 +vpadal.s8 d0, d1 :: Qd 0x134d1a51 0x124f1e5a Qm (i32)0x80000001 +vpadal.s16 d0, d1 :: Qd 0x5554d556 0x5554d556 Qm (i32)0x80000001 +vpadal.s16 d0, d1 :: Qd 0x131b4855 0x121f5157 Qm (i32)0x80000001 +vpadal.s32 d0, d1 :: Qd 0x55555554 0x55555557 Qm (i32)0x80000001 +vpadal.s32 d0, d1 :: Qd 0x131b1a1b 0x3b585658 Qm (i32)0x80000001 +vpadal.s32 d10, d11 :: Qd 0x55555555 0x55555585 Qm (i32)0x00000018 +vpadal.s32 d10, d11 :: Qd 0x131b1a1b 0x3b585658 Qm (i32)0x00000018 +---- VZIP ---- +vzip.32 d0, d1 :: Qm 0x34343434 0x121f1e1f Qn 0x34343434 0x131b1a1b Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.32 d0, d1 :: Qm 0x34343434 0x121f1e1f Qn 0x34343434 0x131b1a1b Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.16 d1, d0 :: Qm 0x131b3434 0x1a1b3434 Qn 0x121f3434 0x1e1f3434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.16 d1, d0 :: Qm 0x131b3434 0x1a1b3434 Qn 0x121f3434 0x1e1f3434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.8 d10, d11 :: Qm 0x3412341f 0x341e341f Qn 0x3413341b 0x341a341b Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.8 d10, d11 :: Qm 0x3412341f 0x341e341f Qn 0x3413341b 0x341a341b Qm (i8)0x00000012 Qn (i8)0x00000034 +vzip.32 d0, d1 :: Qm 0x0a0b0c0d 0x121f1e1f Qn 0x0a0b0c0d 0x131b1a1b Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.32 d0, d1 :: Qm 0x0a0b0c0d 0x121f1e1f Qn 0x0a0b0c0d 0x131b1a1b Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.16 d1, d0 :: Qm 0x131b0a0b 0x1a1b0c0d Qn 0x121f0a0b 0x1e1f0c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.16 d1, d0 :: Qm 0x131b0a0b 0x1a1b0c0d Qn 0x121f0a0b 0x1e1f0c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.8 d30, d31 :: Qm 0x0a120b1f 0x0c1e0d1f Qn 0x0a130b1b 0x0c1a0d1b Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vzip.8 d30, d31 :: Qm 0x0a120b1f 0x0c1e0d1f Qn 0x0a130b1b 0x0c1a0d1b Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +---- VUZP ---- +vuzp.32 d0, d1 :: Qm 0x34343434 0x121f1e1f Qn 0x34343434 0x131b1a1b Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.32 d0, d1 :: Qm 0x34343434 0x121f1e1f Qn 0x34343434 0x131b1a1b Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.16 d1, d0 :: Qm 0x131b121f 0x34343434 Qn 0x1a1b1e1f 0x34343434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.16 d1, d0 :: Qm 0x131b121f 0x34343434 Qn 0x1a1b1e1f 0x34343434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.8 d10, d11 :: Qm 0x34343434 0x1b1b1f1f Qn 0x34343434 0x131a121e Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.8 d10, d11 :: Qm 0x34343434 0x1b1b1f1f Qn 0x34343434 0x131a121e Qm (i8)0x00000012 Qn (i8)0x00000034 +vuzp.32 d0, d1 :: Qm 0x0a0b0c0d 0x121f1e1f Qn 0x0a0b0c0d 0x131b1a1b Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.32 d0, d1 :: Qm 0x0a0b0c0d 0x121f1e1f Qn 0x0a0b0c0d 0x131b1a1b Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.16 d1, d0 :: Qm 0x131b121f 0x0a0b0a0b Qn 0x1a1b1e1f 0x0c0d0c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.16 d1, d0 :: Qm 0x131b121f 0x0a0b0a0b Qn 0x1a1b1e1f 0x0c0d0c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.8 d30, d31 :: Qm 0x0b0d0b0d 0x1b1b1f1f Qn 0x0a0c0a0c 0x131a121e Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vuzp.8 d30, d31 :: Qm 0x0b0d0b0d 0x1b1b1f1f Qn 0x0a0c0a0c 0x131a121e Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +---- VTRN ---- +vtrn.32 d0, d1 :: Qm 0x34343434 0x121f1e1f Qn 0x34343434 0x131b1a1b Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.32 d0, d1 :: Qm 0x34343434 0x121f1e1f Qn 0x34343434 0x131b1a1b Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.16 d1, d0 :: Qm 0x131b3434 0x121f3434 Qn 0x1a1b3434 0x1e1f3434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.16 d1, d0 :: Qm 0x131b3434 0x121f3434 Qn 0x1a1b3434 0x1e1f3434 Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.8 d10, d11 :: Qm 0x341b341b 0x341f341f Qn 0x3413341a 0x3412341e Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.8 d10, d11 :: Qm 0x341b341b 0x341f341f Qn 0x3413341a 0x3412341e Qm (i8)0x00000012 Qn (i8)0x00000034 +vtrn.32 d0, d1 :: Qm 0x0a0b0c0d 0x121f1e1f Qn 0x0a0b0c0d 0x131b1a1b Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.32 d0, d1 :: Qm 0x0a0b0c0d 0x121f1e1f Qn 0x0a0b0c0d 0x131b1a1b Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.16 d1, d0 :: Qm 0x131b0a0b 0x121f0a0b Qn 0x1a1b0c0d 0x1e1f0c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.16 d1, d0 :: Qm 0x131b0a0b 0x121f0a0b Qn 0x1a1b0c0d 0x1e1f0c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.8 d30, d31 :: Qm 0x0b1b0d1b 0x0b1f0d1f Qn 0x0a130c1a 0x0a120c1e Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vtrn.8 d30, d31 :: Qm 0x0b1b0d1b 0x0b1f0d1f Qn 0x0a130c1a 0x0a120c1e Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +---- VSWP ---- +vswp d0, d1 :: Qm 0x34343434 0x34343434 Qn 0x131b1a1b 0x121f1e1f Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp d0, d1 :: Qm 0x34343434 0x34343434 Qn 0x131b1a1b 0x121f1e1f Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp d1, d0 :: Qm 0x34343434 0x34343434 Qn 0x131b1a1b 0x121f1e1f Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp d1, d0 :: Qm 0x34343434 0x34343434 Qn 0x131b1a1b 0x121f1e1f Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp d10, d11 :: Qm 0x34343434 0x34343434 Qn 0x131b1a1b 0x121f1e1f Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp d10, d11 :: Qm 0x34343434 0x34343434 Qn 0x131b1a1b 0x121f1e1f Qm (i8)0x00000012 Qn (i8)0x00000034 +vswp d0, d1 :: Qm 0x0a0b0c0d 0x0a0b0c0d Qn 0x131b1a1b 0x121f1e1f Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp d0, d1 :: Qm 0x0a0b0c0d 0x0a0b0c0d Qn 0x131b1a1b 0x121f1e1f Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp d1, d0 :: Qm 0x0a0b0c0d 0x0a0b0c0d Qn 0x131b1a1b 0x121f1e1f Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp d1, d0 :: Qm 0x0a0b0c0d 0x0a0b0c0d Qn 0x131b1a1b 0x121f1e1f Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp d30, d31 :: Qm 0x0a0b0c0d 0x0a0b0c0d Qn 0x131b1a1b 0x121f1e1f Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +vswp d30, d31 :: Qm 0x0a0b0c0d 0x0a0b0c0d Qn 0x131b1a1b 0x121f1e1f Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d +---- VSHRN ---- +vshrn.i16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshrn.i16 d0, q1, #1 :: Qd 0x16959717 0x8e8e0e8e Qm (i32)0xffffffff +vshrn.i16 d3, q4, #2 :: Qd 0xffe1ffe1 0xffe1ffe1 Qm (i32)0xffffff84 +vshrn.i16 d3, q4, #2 :: Qd 0x0bcacb8b 0x474707c7 Qm (i32)0xffffff84 +vshrn.i32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshrn.i32 d2, q5, #10 :: Qd 0x0b0acbcb 0x47460707 Qm (i32)0xffffffff +vshrn.i32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff +vshrn.i32 d2, q5, #1 :: Qd 0x15959717 0x8c8e0f8e Qm (i32)0x7fffffff +vshrn.i64 d6, q7, #7 :: Qd 0xfe0001ff 0xfe0001ff Qm (i32)0x0000ffff +vshrn.i64 d6, q7, #7 :: Qd 0x56465e5c 0x3a28383e Qm (i32)0x0000ffff +vshrn.i16 d8, q9, #8 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffff6 +vshrn.i16 d8, q9, #8 :: Qd 0x242b232e 0x1519141f Qm (i32)0xfffffff6 +vshrn.i32 d10, q11, #5 :: Qd 0x013f013f 0x013f013f Qm (i32)0x000027fa +vshrn.i32 d10, q11, #5 :: Qd 0x61597971 0xe8c8e0f8 Qm (i32)0x000027fa +vshrn.i64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshrn.i64 d12, q13, #1 :: Qd 0x91979717 0x8a0e0f8e Qm (i32)0xffffffff +vshrn.i16 d14, q15, #6 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshrn.i16 d14, q15, #6 :: Qd 0x90ac8cb8 0x5464507c Qm (i32)0xffffffff +vshrn.i32 d10, q11, #9 :: Qd 0x00010001 0x00010001 Qm (i32)0x000003e8 +vshrn.i32 d10, q11, #9 :: Qd 0x16159797 0x8e8c0e0f Qm (i32)0x000003e8 +vshrn.i64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshrn.i64 d7, q13, #7 :: Qd 0x56465e5c 0x3a28383e Qm (i32)0xffffffff +vshrn.i16 d8, q1, #1 :: Qd 0x00e700e7 0x00e700e7 Qm (i32)0x0000abcf +vshrn.i16 d8, q1, #1 :: Qd 0x16959717 0x8e8e0e8e Qm (i32)0x0000abcf +vshrn.i32 d12, q3, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffe50 +vshrn.i32 d12, q3, #15 :: Qd 0x4858465e 0x2a3a2838 Qm (i32)0xfffffe50 +vshrn.i64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshrn.i64 d0, q1, #22 :: Qd 0xb0acac8c 0x74647450 Qm (i32)0xffffffff +vshrn.i64 d6, q7, #12 :: Qd 0xfac00000 0xfac00000 Qm (i32)0x00000fac +vshrn.i64 d6, q7, #12 :: Qd 0xb2b232f2 0x91d141c1 Qm (i32)0x00000fac +vshrn.i64 d8, q4, #9 :: Qd 0x7c00001a 0x7c00001a Qm (i32)0x000034f8 +vshrn.i64 d8, q4, #9 :: Qd 0x95919797 0x8e8a0e0f Qm (i32)0x000034f8 +vshrn.i64 d9, q12, #11 :: Qd 0x32c00030 0x32c00030 Qm (i32)0x00018196 +vshrn.i64 d9, q12, #11 :: Qd 0x656465e5 0x23a28383 Qm (i32)0x00018196 +---- VDUP ---- +vdup.8 d12, d2[0] :: Qd 0x57575757 0x57575757 Qm (i32)0x0abc4657 +vdup.8 d12, d2[0] :: Qd 0x1c1c1c1c 0x1c1c1c1c Qm (i32)0x0abc4657 +vdup.8 d0, d3[2] :: Qd 0x07070707 0x07070707 Qm (i32)0x0007a1b3 +vdup.8 d0, d3[2] :: Qd 0x1c1c1c1c 0x1c1c1c1c Qm (i32)0x0007a1b3 +vdup.8 d1, d0[7] :: Qd 0x00000000 0x00000000 Qm (i32)0x00713aaa +vdup.8 d1, d0[7] :: Qd 0x15151515 0x15151515 Qm (i32)0x00713aaa +vdup.8 d10, d4[3] :: Qd 0x00000000 0x00000000 Qm (i32)0x000aa713 +vdup.8 d10, d4[3] :: Qd 0x14141414 0x14141414 Qm (i32)0x000aa713 +vdup.8 d4, d28[4] :: Qd 0xc3c3c3c3 0xc3c3c3c3 Qm (i32)0x0007b1c3 +vdup.8 d4, d28[4] :: Qd 0x1d1d1d1d 0x1d1d1d1d Qm (i32)0x0007b1c3 +vdup.16 d17, d19[1] :: Qd 0x07130713 0x07130713 Qm (i32)0x0713ffff +vdup.16 d17, d19[1] :: Qd 0x141c141c 0x141c141c Qm (i32)0x0713ffff +vdup.16 d15, d31[2] :: Qd 0x00fa00fa 0x00fa00fa Qm (i32)0x007f00fa +vdup.16 d15, d31[2] :: Qd 0x191d191d 0x191d191d Qm (i32)0x007f00fa +vdup.16 d6, d2[0] :: Qd 0xbcdebcde 0xbcdebcde Qm (i32)0x0ffabcde +vdup.16 d6, d2[0] :: Qd 0x1f1c1f1c 0x1f1c1f1c Qm (i32)0x0ffabcde +vdup.16 d8, d22[3] :: Qd 0x00000000 0x00000000 Qm (i32)0x00000713 +vdup.16 d8, d22[3] :: Qd 0x151d151d 0x151d151d Qm (i32)0x00000713 +vdup.16 d9, d2[0] :: Qd 0x07130713 0x07130713 Qm (i32)0x00000713 +vdup.16 d9, d2[0] :: Qd 0x1f1c1f1c 0x1f1c1f1c Qm (i32)0x00000713 +vdup.32 d10, d17[1] :: Qd 0x00000713 0x00000713 Qm (i32)0x00000713 +vdup.32 d10, d17[1] :: Qd 0x151d191d 0x151d191d Qm (i32)0x00000713 +vdup.32 d15, d11[0] :: Qd 0x00000003 0x00000003 Qm (i32)0x00000003 +vdup.32 d15, d11[0] :: Qd 0x141c1f1c 0x141c1f1c Qm (i32)0x00000003 +vdup.32 d30, d29[1] :: Qd 0xf00000aa 0xf00000aa Qm (i32)0xf00000aa +vdup.32 d30, d29[1] :: Qd 0x151d191d 0x151d191d Qm (i32)0xf00000aa +vdup.32 d22, d0[1] :: Qd 0x0000000f 0x0000000f Qm (i32)0x0000000f +vdup.32 d22, d0[1] :: Qd 0x151d191d 0x151d191d Qm (i32)0x0000000f +vdup.32 d13, d13[0] :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vdup.32 d13, d13[0] :: Qd 0x141c1f1c 0x141c1f1c Qm (i32)0xffffffff +---- VQDMULH ---- +vqdmulh.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 d0, d1, d2 :: Qd 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 d6, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s32 d6, d7, d8 :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s16 d9, d11, d12 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 d9, d11, d12 :: Qd 0x0000003a 0x00000043 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6 :: Qd 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6 :: Qd 0x00000687 0x00000788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6 :: Qd 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6 :: Qd 0x00000687 0x00000788 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9 :: Qd 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s32 d7, d8, d9 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s16 d4, d5, d6 :: Qd 0x0000003f 0x0000003f Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6 :: Qd 0x00000687 0x00000788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 d10, d11, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 d10, d11, d15 :: Qd 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 d10, d30, d31 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmulh.s32 d10, d30, d31 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 d10, d30, d31 :: Qd 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmulh.s16 d10, d30, d31 :: Qd 0xece50000 0xede10000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 d10, d30, d31 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 d10, d30, d31 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 d10, d30, d31 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmulh.s16 d10, d30, d31 :: Qd 0x098d0000 0x090f0000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQDMULH (by scalar) ---- +vqdmulh.s32 d0, d1, d6[0] :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 d0, d1, d6[0] :: Qd 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 d6, d7, d1[1] :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s32 d6, d7, d1[1] :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqdmulh.s16 d9, d11, d7[0] :: Qd 0x00000002 0x00000002 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 d9, d11, d7[0] :: Qd 0x002a003a 0x00280043 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6[0] :: Qd 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6[0] :: Qd 0x04c70687 0x04880788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9[1] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6[1] :: Qd 0xffffe50b 0xffffe50b Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6[1] :: Qd 0x04c70687 0x04880788 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9[0] :: Qd 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s32 d7, d8, d9[0] :: Qd 0x00000001 0x00000001 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqdmulh.s16 d4, d5, d6[2] :: Qd 0x0400003f 0x0400003f Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s16 d4, d5, d6[2] :: Qd 0x04c70687 0x04880788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 d7, d8, d9[0] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqdmulh.s32 d10, d31, d15[0] :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 d10, d31, d15[0] :: Qd 0x00000011 0x00000010 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqdmulh.s32 d10, d14, d15[1] :: Qd 0xffffff88 0xffffff88 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 d10, d14, d15[1] :: Qd 0x00000011 0x00000010 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 d10, d14, d7[3] :: Qd 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqdmulh.s16 d10, d14, d7[3] :: Qd 0xece5e5e5 0xede1e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 d10, d14, d15[1] :: Qd 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s32 d10, d14, d15[1] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqdmulh.s16 d31, d14, d7[1] :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqdmulh.s16 d31, d14, d7[1] :: Qd 0x098d0d0d 0x090f0f0f Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VSHRN ---- +vshrn.i64 d2, q2, #1 :: Qd 0x855e232b 0x855e232b Qm (i32)0x0abc4657 +vshrn.i64 d2, q2, #1 :: Qd 0x91979717 0x8a0e0f8e Qm (i32)0x0abc4657 +vshrn.i64 d3, q3, #0 :: Qd 0x0007a1b3 0x0007a1b3 Qm (i32)0x0007a1b3 +vshrn.i64 d3, q3, #0 :: Qd 0x232f2e2f 0x141c1f1c Qm (i32)0x0007a1b3 +vshrn.i64 d1, q0, #3 :: Qd 0x400e2755 0x400e2755 Qm (i32)0x00713aaa +vshrn.i64 d1, q0, #3 :: Qd 0x6465e5c5 0xa28383e3 Qm (i32)0x00713aaa +vshrn.i64 d0, q4, #5 :: Qd 0x98005538 0x98005538 Qm (i32)0x000aa713 +vshrn.i64 d0, q4, #5 :: Qd 0x59197971 0xe8a0e0f8 Qm (i32)0x000aa713 +vshrn.i64 d4, q8, #11 :: Qd 0x386000f6 0x386000f6 Qm (i32)0x0007b1c3 +vshrn.i64 d4, q8, #11 :: Qd 0x656465e5 0x23a28383 Qm (i32)0x0007b1c3 +vshrn.i16 d7, q12, #6 :: Qd 0x1cff1cff 0x1cff1cff Qm (i32)0x0713ffff +vshrn.i16 d7, q12, #6 :: Qd 0x90ac8cb8 0x5464507c Qm (i32)0x0713ffff +vshrn.i16 d15, q11, #2 :: Qd 0x1f3e1f3e 0x1f3e1f3e Qm (i32)0x007f00fa +vshrn.i16 d15, q11, #2 :: Qd 0x0bcacb8b 0x474707c7 Qm (i32)0x007f00fa +vshrn.i16 d6, q2, #4 :: Qd 0x00ab00ab 0x00ab00ab Qm (i32)0x000ffabc +vshrn.i16 d6, q2, #4 :: Qd 0x42b232e2 0x519141f1 Qm (i32)0x000ffabc +vshrn.i16 d8, q12, #3 :: Qd 0x00e200e2 0x00e200e2 Qm (i32)0x00000713 +vshrn.i16 d8, q12, #3 :: Qd 0x856565c5 0xa32383e3 Qm (i32)0x00000713 +vshrn.i16 d9, q2, #7 :: Qd 0x000e000e 0x000e000e Qm (i32)0x00000713 +vshrn.i16 d9, q2, #7 :: Qd 0x4856465c 0x2a32283e Qm (i32)0x00000713 +vshrn.i32 d10, q13, #2 :: Qd 0x01c401c4 0x01c401c4 Qm (i32)0x00000713 +vshrn.i32 d10, q13, #2 :: Qd 0x0acacb8b 0x464707c7 Qm (i32)0x00000713 +vshrn.i32 d15, q11, #1 :: Qd 0x00010001 0x00010001 Qm (i32)0x00000003 +vshrn.i32 d15, q11, #1 :: Qd 0x15959717 0x8c8e0f8e Qm (i32)0x00000003 +vshrn.i32 d10, q9, #5 :: Qd 0x00050005 0x00050005 Qm (i32)0xf00000aa +vshrn.i32 d10, q9, #5 :: Qd 0x61597971 0xe8c8e0f8 Qm (i32)0xf00000aa +vshrn.i32 d12, q0, #6 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000000f +vshrn.i32 d12, q0, #6 :: Qd 0xb0acbcb8 0x7464707c Qm (i32)0x0000000f +vshrn.i32 d13, q13, #2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff +vshrn.i32 d13, q13, #2 :: Qd 0x0acacb8b 0x464707c7 Qm (i32)0xffffffff +---- VQSHRN ---- +vqshrn.s16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 00000000 +vqshrn.s16 d0, q1, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff fpscr 08000000 +vqshrn.s16 d3, q4, #2 :: Qd 0xffe1ffe1 0xffe1ffe1 Qm (i32)0xffffff84 fpscr 00000000 +vqshrn.s16 d3, q4, #2 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffff84 fpscr 08000000 +vqshrn.s32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 00000000 +vqshrn.s32 d2, q5, #10 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.s32 d2, q5, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x7fffffff fpscr 08000000 +vqshrn.s32 d2, q5, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x7fffffff fpscr 08000000 +vqshrn.s16 d2, q5, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i16)0x00007fff fpscr 08000000 +vqshrn.s16 d2, q5, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i16)0x00007fff fpscr 08000000 +vqshrn.s64 d6, q7, #7 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x0000ffff fpscr 08000000 +vqshrn.s64 d6, q7, #7 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x0000ffff fpscr 08000000 +vqshrn.s16 d8, q9, #8 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffff6 fpscr 00000000 +vqshrn.s16 d8, q9, #8 :: Qd 0x1519141f 0x131a121e Qm (i32)0xfffffff6 fpscr 00000000 +vqshrn.s32 d10, q11, #5 :: Qd 0x013f013f 0x013f013f Qm (i32)0x000027fa fpscr 00000000 +vqshrn.s32 d10, q11, #5 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x000027fa fpscr 08000000 +vqshrn.s64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 00000000 +vqshrn.s64 d12, q13, #1 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.s16 d14, q15, #6 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 00000000 +vqshrn.s16 d14, q15, #6 :: Qd 0x5464507c 0x4c684878 Qm (i32)0xffffffff fpscr 00000000 +vqshrn.s32 d10, q11, #9 :: Qd 0x00010001 0x00010001 Qm (i32)0x000003e8 fpscr 00000000 +vqshrn.s32 d10, q11, #9 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x000003e8 fpscr 08000000 +vqshrn.s64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 00000000 +vqshrn.s64 d7, q13, #7 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.s16 d8, q1, #1 :: Qd 0x00800080 0x00800080 Qm (i32)0x0000abcf fpscr 08000000 +vqshrn.s16 d8, q1, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0x0000abcf fpscr 08000000 +vqshrn.s32 d8, q1, #1 :: Qd 0x55e755e7 0x55e755e7 Qm (i32)0x0000abcf fpscr 00000000 +vqshrn.s32 d8, q1, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x0000abcf fpscr 08000000 +vqshrn.s32 d12, q3, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffe50 fpscr 00000000 +vqshrn.s32 d12, q3, #15 :: Qd 0x2a3a2838 0x2636243e Qm (i32)0xfffffe50 fpscr 00000000 +vqshrn.s64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 00000000 +vqshrn.s64 d0, q1, #22 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.s64 d6, q7, #12 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000fac fpscr 08000000 +vqshrn.s64 d6, q7, #12 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000fac fpscr 08000000 +vqshrn.s64 d8, q4, #9 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x000034f8 fpscr 08000000 +vqshrn.s64 d8, q4, #9 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x000034f8 fpscr 08000000 +vqshrn.s64 d9, q12, #11 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00018196 fpscr 08000000 +vqshrn.s64 d9, q12, #11 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00018196 fpscr 08000000 +vqshrn.u16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u16 d3, q4, #2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff84 fpscr 08000000 +vqshrn.u16 d3, q4, #2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff84 fpscr 08000000 +vqshrn.u32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff fpscr 08000000 +vqshrn.u32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff fpscr 08000000 +vqshrn.u16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i16)0x00007fff fpscr 08000000 +vqshrn.u16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i16)0x00007fff fpscr 08000000 +vqshrn.u64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000ffff fpscr 08000000 +vqshrn.u64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000ffff fpscr 08000000 +vqshrn.u16 d8, q9, #8 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffff6 fpscr 00000000 +vqshrn.u16 d8, q9, #8 :: Qd 0x1519141f 0x131a121e Qm (i32)0xfffffff6 fpscr 00000000 +vqshrn.u32 d10, q11, #5 :: Qd 0x013f013f 0x013f013f Qm (i32)0x000027fa fpscr 00000000 +vqshrn.u32 d10, q11, #5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000027fa fpscr 08000000 +vqshrn.u64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u16 d14, q15, #6 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u16 d14, q15, #6 :: Qd 0x5464507c 0x4c684878 Qm (i32)0xffffffff fpscr 00000000 +vqshrn.u32 d10, q11, #9 :: Qd 0x00010001 0x00010001 Qm (i32)0x000003e8 fpscr 00000000 +vqshrn.u32 d10, q11, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000003e8 fpscr 08000000 +vqshrn.u64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u16 d8, q1, #1 :: Qd 0x00ff00ff 0x00ff00ff Qm (i32)0x0000abcf fpscr 08000000 +vqshrn.u16 d8, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000abcf fpscr 08000000 +vqshrn.u32 d8, q1, #1 :: Qd 0x55e755e7 0x55e755e7 Qm (i32)0x0000abcf fpscr 00000000 +vqshrn.u32 d8, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000abcf fpscr 08000000 +vqshrn.u32 d12, q3, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffe50 fpscr 08000000 +vqshrn.u32 d12, q3, #15 :: Qd 0x2a3a2838 0x2636243e Qm (i32)0xfffffe50 fpscr 00000000 +vqshrn.u64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrn.u64 d6, q7, #12 :: Qd 0xfac00000 0xfac00000 Qm (i32)0x00000fac fpscr 00000000 +vqshrn.u64 d6, q7, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000fac fpscr 08000000 +vqshrn.u64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000034f8 fpscr 08000000 +vqshrn.u64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000034f8 fpscr 08000000 +vqshrn.u64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00018196 fpscr 08000000 +vqshrn.u64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00018196 fpscr 08000000 +---- VQSHRUN ---- +vqshrun.s16 d0, q1, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s16 d3, q4, #2 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff84 fpscr 08000000 +vqshrun.s16 d3, q4, #2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff84 fpscr 08000000 +vqshrun.s32 d2, q5, #10 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff fpscr 08000000 +vqshrun.s32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff fpscr 08000000 +vqshrun.s16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i16)0x00007fff fpscr 08000000 +vqshrun.s16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i16)0x00007fff fpscr 08000000 +vqshrun.s64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000ffff fpscr 08000000 +vqshrun.s64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000ffff fpscr 08000000 +vqshrun.s16 d8, q9, #8 :: Qd 0x00000000 0x00000000 Qm (i32)0xfffffff6 fpscr 08000000 +vqshrun.s16 d8, q9, #8 :: Qd 0x1519141f 0x131a121e Qm (i32)0xfffffff6 fpscr 00000000 +vqshrun.s32 d10, q11, #5 :: Qd 0x013f013f 0x013f013f Qm (i32)0x000027fa fpscr 00000000 +vqshrun.s32 d10, q11, #5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000027fa fpscr 08000000 +vqshrun.s64 d12, q13, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s16 d14, q15, #6 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s16 d14, q15, #6 :: Qd 0x5464507c 0x4c684878 Qm (i32)0xffffffff fpscr 00000000 +vqshrun.s32 d10, q11, #9 :: Qd 0x00010001 0x00010001 Qm (i32)0x000003e8 fpscr 00000000 +vqshrun.s32 d10, q11, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000003e8 fpscr 08000000 +vqshrun.s64 d7, q13, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s16 d8, q1, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000abcf fpscr 08000000 +vqshrun.s16 d8, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000abcf fpscr 08000000 +vqshrun.s32 d8, q1, #1 :: Qd 0x55e755e7 0x55e755e7 Qm (i32)0x0000abcf fpscr 00000000 +vqshrun.s32 d8, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000abcf fpscr 08000000 +vqshrun.s32 d12, q3, #15 :: Qd 0x00000000 0x00000000 Qm (i32)0xfffffe50 fpscr 08000000 +vqshrun.s32 d12, q3, #15 :: Qd 0x2a3a2838 0x2636243e Qm (i32)0xfffffe50 fpscr 00000000 +vqshrun.s64 d0, q1, #22 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqshrun.s64 d6, q7, #12 :: Qd 0xfac00000 0xfac00000 Qm (i32)0x00000fac fpscr 00000000 +vqshrun.s64 d6, q7, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000fac fpscr 08000000 +vqshrun.s64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000034f8 fpscr 08000000 +vqshrun.s64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000034f8 fpscr 08000000 +vqshrun.s64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00018196 fpscr 08000000 +vqshrun.s64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00018196 fpscr 08000000 +---- VQRSHRN ---- +vqrshrn.s16 d0, q1, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrn.s16 d0, q1, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.s16 d3, q4, #2 :: Qd 0x00e100e1 0x00e100e1 Qm (i32)0xffffff84 fpscr 00000000 +vqrshrn.s16 d3, q4, #2 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffff84 fpscr 08000000 +vqrshrn.s32 d2, q5, #10 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrn.s32 d2, q5, #10 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.s32 d2, q5, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x7fffffff fpscr 08000000 +vqrshrn.s32 d2, q5, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x7fffffff fpscr 08000000 +vqrshrn.s16 d2, q5, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i16)0x00007fff fpscr 08000000 +vqrshrn.s16 d2, q5, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i16)0x00007fff fpscr 08000000 +vqrshrn.s64 d6, q7, #7 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x0000ffff fpscr 08000000 +vqrshrn.s64 d6, q7, #7 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x0000ffff fpscr 08000000 +vqrshrn.s16 d8, q9, #8 :: Qd 0x00000000 0x00000000 Qm (i32)0xfffffff6 fpscr 00000000 +vqrshrn.s16 d8, q9, #8 :: Qd 0x1519141f 0x131a121e Qm (i32)0xfffffff6 fpscr 00000000 +vqrshrn.s32 d10, q11, #5 :: Qd 0x01400140 0x01400140 Qm (i32)0x000027fa fpscr 00000000 +vqrshrn.s32 d10, q11, #5 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x000027fa fpscr 08000000 +vqrshrn.s64 d12, q13, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrn.s64 d12, q13, #1 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.s16 d14, q15, #6 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrn.s16 d14, q15, #6 :: Qd 0x5464507c 0x4c684878 Qm (i32)0xffffffff fpscr 00000000 +vqrshrn.s32 d10, q11, #9 :: Qd 0x00020002 0x00020002 Qm (i32)0x000003e8 fpscr 00000000 +vqrshrn.s32 d10, q11, #9 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x000003e8 fpscr 08000000 +vqrshrn.s64 d7, q13, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrn.s64 d7, q13, #7 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.s16 d8, q1, #1 :: Qd 0x00800080 0x00800080 Qm (i32)0x0000abcf fpscr 08000000 +vqrshrn.s16 d8, q1, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0x0000abcf fpscr 08000000 +vqrshrn.s32 d8, q1, #1 :: Qd 0x55e855e8 0x55e855e8 Qm (i32)0x0000abcf fpscr 00000000 +vqrshrn.s32 d8, q1, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x0000abcf fpscr 08000000 +vqrshrn.s32 d12, q3, #15 :: Qd 0x00000000 0x00000000 Qm (i32)0xfffffe50 fpscr 00000000 +vqrshrn.s32 d12, q3, #15 :: Qd 0x2a3a2838 0x2636243e Qm (i32)0xfffffe50 fpscr 00000000 +vqrshrn.s64 d0, q1, #22 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrn.s64 d0, q1, #22 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.s64 d6, q7, #12 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000fac fpscr 08000000 +vqrshrn.s64 d6, q7, #12 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00000fac fpscr 08000000 +vqrshrn.s64 d8, q4, #9 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x000034f8 fpscr 08000000 +vqrshrn.s64 d8, q4, #9 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x000034f8 fpscr 08000000 +vqrshrn.s64 d9, q12, #11 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00018196 fpscr 08000000 +vqrshrn.s64 d9, q12, #11 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x00018196 fpscr 08000000 +vqrshrn.u16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u16 d3, q4, #2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff84 fpscr 08000000 +vqrshrn.u16 d3, q4, #2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff84 fpscr 08000000 +vqrshrn.u32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff fpscr 08000000 +vqrshrn.u32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff fpscr 08000000 +vqrshrn.u16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i16)0x00007fff fpscr 08000000 +vqrshrn.u16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i16)0x00007fff fpscr 08000000 +vqrshrn.u64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000ffff fpscr 08000000 +vqrshrn.u64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000ffff fpscr 08000000 +vqrshrn.u16 d8, q9, #8 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffff6 fpscr 08000000 +vqrshrn.u16 d8, q9, #8 :: Qd 0x1519141f 0x131a121e Qm (i32)0xfffffff6 fpscr 00000000 +vqrshrn.u32 d10, q11, #5 :: Qd 0x01400140 0x01400140 Qm (i32)0x000027fa fpscr 00000000 +vqrshrn.u32 d10, q11, #5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000027fa fpscr 08000000 +vqrshrn.u64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u16 d14, q15, #6 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u16 d14, q15, #6 :: Qd 0x5464507c 0x4c684878 Qm (i32)0xffffffff fpscr 00000000 +vqrshrn.u32 d10, q11, #9 :: Qd 0x00020002 0x00020002 Qm (i32)0x000003e8 fpscr 00000000 +vqrshrn.u32 d10, q11, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000003e8 fpscr 08000000 +vqrshrn.u64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u16 d8, q1, #1 :: Qd 0x00ff00ff 0x00ff00ff Qm (i32)0x0000abcf fpscr 08000000 +vqrshrn.u16 d8, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000abcf fpscr 08000000 +vqrshrn.u32 d8, q1, #1 :: Qd 0x55e855e8 0x55e855e8 Qm (i32)0x0000abcf fpscr 00000000 +vqrshrn.u32 d8, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000abcf fpscr 08000000 +vqrshrn.u32 d12, q3, #15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xfffffe50 fpscr 08000000 +vqrshrn.u32 d12, q3, #15 :: Qd 0x2a3a2838 0x2636243e Qm (i32)0xfffffe50 fpscr 00000000 +vqrshrn.u64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrn.u64 d6, q7, #12 :: Qd 0xfac00001 0xfac00001 Qm (i32)0x00000fac fpscr 00000000 +vqrshrn.u64 d6, q7, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000fac fpscr 08000000 +vqrshrn.u64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000034f8 fpscr 08000000 +vqrshrn.u64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000034f8 fpscr 08000000 +vqrshrn.u64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00018196 fpscr 08000000 +vqrshrn.u64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00018196 fpscr 08000000 +---- VQRSHRUN ---- +vqrshrun.s16 d0, q1, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrun.s16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrun.s16 d3, q4, #2 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff84 fpscr 08000000 +vqrshrun.s16 d3, q4, #2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffff84 fpscr 08000000 +vqrshrun.s32 d2, q5, #10 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrun.s32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrun.s32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff fpscr 08000000 +vqrshrun.s32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff fpscr 08000000 +vqrshrun.s16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i16)0x00007fff fpscr 08000000 +vqrshrun.s16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i16)0x00007fff fpscr 08000000 +vqrshrun.s64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000ffff fpscr 08000000 +vqrshrun.s64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000ffff fpscr 08000000 +vqrshrun.s16 d8, q9, #8 :: Qd 0x00000000 0x00000000 Qm (i32)0xfffffff6 fpscr 00000000 +vqrshrun.s16 d8, q9, #8 :: Qd 0x1519141f 0x131a121e Qm (i32)0xfffffff6 fpscr 00000000 +vqrshrun.s32 d10, q11, #5 :: Qd 0x01400140 0x01400140 Qm (i32)0x000027fa fpscr 00000000 +vqrshrun.s32 d10, q11, #5 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000027fa fpscr 08000000 +vqrshrun.s64 d12, q13, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrun.s64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrun.s16 d14, q15, #6 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrun.s16 d14, q15, #6 :: Qd 0x5464507c 0x4c684878 Qm (i32)0xffffffff fpscr 00000000 +vqrshrun.s32 d10, q11, #9 :: Qd 0x00020002 0x00020002 Qm (i32)0x000003e8 fpscr 00000000 +vqrshrun.s32 d10, q11, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000003e8 fpscr 08000000 +vqrshrun.s64 d7, q13, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrun.s64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrun.s16 d8, q1, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000abcf fpscr 08000000 +vqrshrun.s16 d8, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000abcf fpscr 08000000 +vqrshrun.s32 d8, q1, #1 :: Qd 0x55e855e8 0x55e855e8 Qm (i32)0x0000abcf fpscr 00000000 +vqrshrun.s32 d8, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x0000abcf fpscr 08000000 +vqrshrun.s32 d12, q3, #15 :: Qd 0x00000000 0x00000000 Qm (i32)0xfffffe50 fpscr 00000000 +vqrshrun.s32 d12, q3, #15 :: Qd 0x2a3a2838 0x2636243e Qm (i32)0xfffffe50 fpscr 00000000 +vqrshrun.s64 d0, q1, #22 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 +vqrshrun.s64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr 08000000 +vqrshrun.s64 d6, q7, #12 :: Qd 0xfac00001 0xfac00001 Qm (i32)0x00000fac fpscr 00000000 +vqrshrun.s64 d6, q7, #12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000fac fpscr 08000000 +vqrshrun.s64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000034f8 fpscr 08000000 +vqrshrun.s64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff Qm (i32)0x000034f8 fpscr 08000000 +vqrshrun.s64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00018196 fpscr 08000000 +vqrshrun.s64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00018196 fpscr 08000000 +---- VRSHRN ---- +vrshrn.i64 d2, q2, #1 :: Qd 0x855e232c 0x855e232c Qm (i32)0x0abc4657 +vrshrn.i64 d2, q2, #1 :: Qd 0x91979718 0x8a0e0f8e Qm (i32)0x0abc4657 +vrshrn.i64 d3, q3, #0 :: Qd 0x0007a1b3 0x0007a1b3 Qm (i32)0x0007a1b3 +vrshrn.i64 d3, q3, #0 :: Qd 0x232f2e2f 0x141c1f1c Qm (i32)0x0007a1b3 +vrshrn.i64 d1, q0, #3 :: Qd 0x400e2755 0x400e2755 Qm (i32)0x00713aaa +vrshrn.i64 d1, q0, #3 :: Qd 0x6465e5c6 0xa28383e4 Qm (i32)0x00713aaa +vrshrn.i64 d0, q4, #5 :: Qd 0x98005539 0x98005539 Qm (i32)0x000aa713 +vrshrn.i64 d0, q4, #5 :: Qd 0x59197971 0xe8a0e0f9 Qm (i32)0x000aa713 +vrshrn.i64 d4, q8, #11 :: Qd 0x386000f6 0x386000f6 Qm (i32)0x0007b1c3 +vrshrn.i64 d4, q8, #11 :: Qd 0x656465e6 0x23a28384 Qm (i32)0x0007b1c3 +vrshrn.i16 d7, q12, #6 :: Qd 0x1c001c00 0x1c001c00 Qm (i32)0x0713ffff +vrshrn.i16 d7, q12, #6 :: Qd 0x91ad8db9 0x5464507c Qm (i32)0x0713ffff +vrshrn.i16 d15, q11, #2 :: Qd 0x203f203f 0x203f203f Qm (i32)0x007f00fa +vrshrn.i16 d15, q11, #2 :: Qd 0x0bcbcc8c 0x474707c7 Qm (i32)0x007f00fa +vrshrn.i16 d6, q2, #4 :: Qd 0x01ac01ac 0x01ac01ac Qm (i32)0x000ffabc +vrshrn.i16 d6, q2, #4 :: Qd 0x43b333e3 0x529242f2 Qm (i32)0x000ffabc +vrshrn.i16 d8, q12, #3 :: Qd 0x00e200e2 0x00e200e2 Qm (i32)0x00000713 +vrshrn.i16 d8, q12, #3 :: Qd 0x866566c6 0xa42484e4 Qm (i32)0x00000713 +vrshrn.i16 d9, q2, #7 :: Qd 0x000e000e 0x000e000e Qm (i32)0x00000713 +vrshrn.i16 d9, q2, #7 :: Qd 0x4856465c 0x2a32283e Qm (i32)0x00000713 +vrshrn.i32 d10, q13, #2 :: Qd 0x01c501c5 0x01c501c5 Qm (i32)0x00000713 +vrshrn.i32 d10, q13, #2 :: Qd 0x0acbcb8c 0x464707c7 Qm (i32)0x00000713 +vrshrn.i32 d15, q11, #1 :: Qd 0x00020002 0x00020002 Qm (i32)0x00000003 +vrshrn.i32 d15, q11, #1 :: Qd 0x15969718 0x8c8f0f8e Qm (i32)0x00000003 +vrshrn.i32 d10, q9, #5 :: Qd 0x00050005 0x00050005 Qm (i32)0xf00000aa +vrshrn.i32 d10, q9, #5 :: Qd 0x61597971 0xe8c9e0f9 Qm (i32)0xf00000aa +vrshrn.i32 d12, q0, #6 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000000f +vrshrn.i32 d12, q0, #6 :: Qd 0xb0adbcb9 0x7464707c Qm (i32)0x0000000f +vrshrn.i32 d13, q13, #2 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff +vrshrn.i32 d13, q13, #2 :: Qd 0x0acbcb8c 0x464707c7 Qm (i32)0xffffffff +---- VSHL (immediate) ---- +vshl.i64 d0, d1, #1 :: Qd 0x00000030 0x00000030 Qm (i32)0x00000018 +vshl.i64 d0, d1, #1 :: Qd 0x2a3a323a 0x28383e38 Qm (i32)0x00000018 +vshl.i64 d5, d2, #1 :: Qd 0x80000000 0x80000000 Qm (i32)0x40000000 +vshl.i64 d5, d2, #1 :: Qd 0x2a3a323a 0x28383e38 Qm (i32)0x40000000 +vshl.i64 d9, d12, #2 :: Qd 0x0000000a 0x00000008 Qm (i32)0x80000002 +vshl.i64 d9, d12, #2 :: Qd 0x54746474 0x50707c70 Qm (i32)0x80000002 +vshl.i64 d11, d2, #12 :: Qd 0xffffffff 0xfffff000 Qm (i32)0xffffffff +vshl.i64 d11, d2, #12 :: Qd 0xd191d141 0xc1f1c000 Qm (i32)0xffffffff +vshl.i64 d15, d12, #63 :: Qd 0x80000000 0x00000000 Qm (i32)0x00000005 +vshl.i64 d15, d12, #63 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000005 +vshl.i64 d5, d12, #62 :: Qd 0x40000000 0x00000000 Qm (i32)0x80000001 +vshl.i64 d5, d12, #62 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 +vshl.i32 d0, d1, #1 :: Qd 0x00000030 0x00000030 Qm (i32)0x00000018 +vshl.i32 d0, d1, #1 :: Qd 0x2a3a323a 0x28383e38 Qm (i32)0x00000018 +vshl.i32 d5, d2, #1 :: Qd 0x80000000 0x80000000 Qm (i32)0x40000000 +vshl.i32 d5, d2, #1 :: Qd 0x2a3a323a 0x28383e38 Qm (i32)0x40000000 +vshl.i32 d9, d12, #2 :: Qd 0x00000008 0x00000008 Qm (i32)0x80000002 +vshl.i32 d9, d12, #2 :: Qd 0x54746474 0x50707c70 Qm (i32)0x80000002 +vshl.i32 d11, d2, #12 :: Qd 0xfffff000 0xfffff000 Qm (i32)0xffffffff +vshl.i32 d11, d2, #12 :: Qd 0xd191d000 0xc1f1c000 Qm (i32)0xffffffff +vshl.i32 d15, d12, #20 :: Qd 0x00500000 0x00500000 Qm (i32)0x00000005 +vshl.i32 d15, d12, #20 :: Qd 0x91d00000 0xf1c00000 Qm (i32)0x00000005 +vshl.i32 d5, d12, #30 :: Qd 0x40000000 0x40000000 Qm (i32)0x80000001 +vshl.i32 d5, d12, #30 :: Qd 0x40000000 0x00000000 Qm (i32)0x80000001 +vshl.i16 d0, d1, #1 :: Qd 0x00300030 0x00300030 Qm (i16)0x00000018 +vshl.i16 d0, d1, #1 :: Qd 0x2a3a323a 0x28383e38 Qm (i16)0x00000018 +vshl.i16 d5, d2, #1 :: Qd 0x80000000 0x80000000 Qm (i32)0x40000000 +vshl.i16 d5, d2, #1 :: Qd 0x2a3a323a 0x28383e38 Qm (i32)0x40000000 +vshl.i16 d9, d12, #2 :: Qd 0x00000008 0x00000008 Qm (i32)0x80000002 +vshl.i16 d9, d12, #2 :: Qd 0x54746474 0x50707c70 Qm (i32)0x80000002 +vshl.i16 d11, d2, #12 :: Qd 0xf000f000 0xf000f000 Qm (i16)0xffffffff +vshl.i16 d11, d2, #12 :: Qd 0xd000d000 0xc000c000 Qm (i16)0xffffffff +vshl.i16 d15, d12, #3 :: Qd 0x00280028 0x00280028 Qm (i16)0x00000005 +vshl.i16 d15, d12, #3 :: Qd 0xa8e8c8e8 0xa0e0f8e0 Qm (i16)0x00000005 +vshl.i16 d5, d12, #14 :: Qd 0x00004000 0x00004000 Qm (i32)0x80000001 +vshl.i16 d5, d12, #14 :: Qd 0x40004000 0x00000000 Qm (i32)0x80000001 +vshl.i8 d0, d1, #1 :: Qd 0x30303030 0x30303030 Qm (i8)0x00000018 +vshl.i8 d0, d1, #1 :: Qd 0x2a3a323a 0x28383e38 Qm (i8)0x00000018 +vshl.i8 d5, d2, #1 :: Qd 0x80000000 0x80000000 Qm (i32)0x40000000 +vshl.i8 d5, d2, #1 :: Qd 0x2a3a323a 0x28383e38 Qm (i32)0x40000000 +vshl.i8 d9, d12, #2 :: Qd 0x00000008 0x00000008 Qm (i32)0x80000002 +vshl.i8 d9, d12, #2 :: Qd 0x54746474 0x50707c70 Qm (i32)0x80000002 +vshl.i8 d11, d2, #7 :: Qd 0x80808080 0x80808080 Qm (i8)0xffffffff +vshl.i8 d11, d2, #7 :: Qd 0x80808080 0x00008000 Qm (i8)0xffffffff +vshl.i8 d15, d12, #3 :: Qd 0x28282828 0x28282828 Qm (i8)0x00000005 +vshl.i8 d15, d12, #3 :: Qd 0xa8e8c8e8 0xa0e0f8e0 Qm (i8)0x00000005 +vshl.i8 d5, d12, #6 :: Qd 0x00000040 0x00000040 Qm (i32)0x80000001 +vshl.i8 d5, d12, #6 :: Qd 0x40404040 0x0000c000 Qm (i32)0x80000001 +---- VNEG ---- +vneg.s32 d0, d1 :: Qd 0xffffff8d 0xffffff8d Qm (i32)0x00000073 +vneg.s32 d0, d1 :: Qd 0xeae2e6e3 0xebe3e0e4 Qm (i32)0x00000073 +vneg.s16 d15, d4 :: Qd 0x0000ff8d 0x0000ff8d Qm (i32)0x00000073 +vneg.s16 d15, d4 :: Qd 0xeae3e6e3 0xebe4e0e4 Qm (i32)0x00000073 +vneg.s8 d8, d7 :: Qd 0x0000008d 0x0000008d Qm (i32)0x00000073 +vneg.s8 d8, d7 :: Qd 0xebe3e7e3 0xece4e1e4 Qm (i32)0x00000073 +vneg.s32 d0, d1 :: Qd 0xffffff02 0xffffff02 Qm (i32)0x000000fe +vneg.s32 d0, d1 :: Qd 0xeae2e6e3 0xebe3e0e4 Qm (i32)0x000000fe +vneg.s16 d31, d4 :: Qd 0x0000ff11 0x0000ff11 Qm (i32)0x000000ef +vneg.s16 d31, d4 :: Qd 0xeae3e6e3 0xebe4e0e4 Qm (i32)0x000000ef +vneg.s8 d8, d7 :: Qd 0x00000022 0x00000022 Qm (i32)0x000000de +vneg.s8 d8, d7 :: Qd 0xebe3e7e3 0xece4e1e4 Qm (i32)0x000000de +vneg.s32 d0, d1 :: Qd 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a +vneg.s32 d0, d1 :: Qd 0xeae2e6e3 0xebe3e0e4 Qm (i16)0x0000fe0a +vneg.s16 d15, d4 :: Qd 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b +vneg.s16 d15, d4 :: Qd 0xeae3e6e3 0xebe4e0e4 Qm (i16)0x0000ef0b +vneg.s8 d8, d7 :: Qd 0x22f422f4 0x22f422f4 Qm (i16)0x0000de0c +vneg.s8 d8, d7 :: Qd 0xebe3e7e3 0xece4e1e4 Qm (i16)0x0000de0c +---- VQNEG ---- +vqneg.s32 d0, d1 :: Qd 0xffffff8d 0xffffff8d Qm (i32)0x00000073 fpscr 00000000 +vqneg.s32 d0, d1 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x00000073 fpscr 00000000 +vqneg.s32 d0, d1 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x80000000 fpscr 08000000 +vqneg.s32 d0, d1 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 fpscr 00000000 +vqneg.s16 d0, d1 :: Qd 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 fpscr 08000000 +vqneg.s16 d0, d1 :: Qd 0xece5e5e5 0xede1e1e1 Qm (i32)0x80000000 fpscr 00000000 +vqneg.s8 d0, d1 :: Qd 0x7f000000 0x7f000000 Qm (i32)0x80000000 fpscr 08000000 +vqneg.s8 d0, d1 :: Qd 0xede5e6e5 0xeee1e2e1 Qm (i32)0x80000000 fpscr 00000000 +vqneg.s16 d15, d4 :: Qd 0x0000ff8d 0x0000ff8d Qm (i32)0x00000073 fpscr 00000000 +vqneg.s16 d15, d4 :: Qd 0xece5e5e5 0xede1e1e1 Qm (i32)0x00000073 fpscr 00000000 +vqneg.s8 d8, d7 :: Qd 0x0000008d 0x0000008d Qm (i32)0x00000073 fpscr 00000000 +vqneg.s8 d8, d7 :: Qd 0xede5e6e5 0xeee1e2e1 Qm (i32)0x00000073 fpscr 00000000 +vqneg.s32 d0, d1 :: Qd 0xffffff02 0xffffff02 Qm (i32)0x000000fe fpscr 00000000 +vqneg.s32 d0, d1 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x000000fe fpscr 00000000 +vqneg.s16 d31, d4 :: Qd 0x0000ff11 0x0000ff11 Qm (i32)0x000000ef fpscr 00000000 +vqneg.s16 d31, d4 :: Qd 0xece5e5e5 0xede1e1e1 Qm (i32)0x000000ef fpscr 00000000 +vqneg.s8 d8, d7 :: Qd 0x00000022 0x00000022 Qm (i32)0x000000de fpscr 00000000 +vqneg.s8 d8, d7 :: Qd 0xede5e6e5 0xeee1e2e1 Qm (i32)0x000000de fpscr 00000000 +vqneg.s32 d0, d1 :: Qd 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a fpscr 00000000 +vqneg.s32 d0, d1 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i16)0x0000fe0a fpscr 00000000 +vqneg.s16 d15, d4 :: Qd 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b fpscr 00000000 +vqneg.s16 d15, d4 :: Qd 0xece5e5e5 0xede1e1e1 Qm (i16)0x0000ef0b fpscr 00000000 +vqneg.s8 d8, d7 :: Qd 0x22f422f4 0x22f422f4 Qm (i16)0x0000de0c fpscr 00000000 +vqneg.s8 d8, d7 :: Qd 0xede5e6e5 0xeee1e2e1 Qm (i16)0x0000de0c fpscr 00000000 +---- VREV ---- +vrev64.8 d0, d1 :: Qd 0xddccbbaa 0xddccbbaa Qm (i32)0xaabbccdd +vrev64.8 d0, d1 :: Qd 0x1c1f1c14 0x1d191d15 Qm (i32)0xaabbccdd +vrev64.16 d10, d31 :: Qd 0xccddaabb 0xccddaabb Qm (i32)0xaabbccdd +vrev64.16 d10, d31 :: Qd 0x1f1c141c 0x191d151d Qm (i32)0xaabbccdd +vrev64.32 d1, d14 :: Qd 0xaabbccdd 0xaabbccdd Qm (i32)0xaabbccdd +vrev64.32 d1, d14 :: Qd 0x141c1f1c 0x151d191d Qm (i32)0xaabbccdd +vrev32.8 d0, d1 :: Qd 0xddccbbaa 0xddccbbaa Qm (i32)0xaabbccdd +vrev32.8 d0, d1 :: Qd 0x1d191d15 0x1c1f1c14 Qm (i32)0xaabbccdd +vrev32.16 d30, d15 :: Qd 0xccddaabb 0xccddaabb Qm (i32)0xaabbccdd +vrev32.16 d30, d15 :: Qd 0x191d151d 0x1f1c141c Qm (i32)0xaabbccdd +vrev16.8 d0, d1 :: Qd 0xbbaaddcc 0xbbaaddcc Qm (i32)0xaabbccdd +vrev16.8 d0, d1 :: Qd 0x1d151d19 0x1c141c1f Qm (i32)0xaabbccdd +---- VTBL ---- +vtbl.8 d0, {d2}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d0, {d2}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d0, {d31}, d1 :: Qd 0x12121212 0x12121212 Qm (i8)0x00000007 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d0, {d31}, d1 :: Qd 0x12121212 0x12121212 Qm (i8)0x00000007 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d0, {d20}, d1 :: Qd 0x56565656 0x56565656 Qm (i8)0x00000001 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d0, {d20}, d1 :: Qd 0x56565656 0x56565656 Qm (i8)0x00000001 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d0, {d2}, d31 :: Qd 0x34343434 0x34343434 Qm (i8)0x00000002 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d0, {d2}, d31 :: Qd 0x34343434 0x34343434 Qm (i8)0x00000002 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d30, {d2}, d1 :: Qd 0x12125656 0x12125656 Qm (i32)0x07030501 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d30, {d2}, d1 :: Qd 0x12125656 0x12125656 Qm (i32)0x07030501 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d31, {d2}, d1 :: Qd 0x56785678 0x56785678 Qm (i16)0x00000104 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d31, {d2}, d1 :: Qd 0x56785678 0x56785678 Qm (i16)0x00000104 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d30, {d2}, d1 :: Qd 0x12005656 0x12005656 Qm (i32)0x07080501 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d30, {d2}, d1 :: Qd 0x12005656 0x12005656 Qm (i32)0x07080501 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d30, {d2}, d1 :: Qd 0x12005600 0x12005600 Qm (i32)0x07ed05ee Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d30, {d2}, d1 :: Qd 0x12005600 0x12005600 Qm (i32)0x07ed05ee Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbl.8 d0, {d2-d3}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d2-d3}, d1 :: Qd 0x1c1c1c1c 0x1c1c1c1c Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d1-d2}, d3 :: Qd 0xa2a2a2a2 0xa2a2a2a2 Qm (i8)0x0000000a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d1-d2}, d3 :: Qd 0xa2a2a2a2 0xa2a2a2a2 Qm (i8)0x0000000a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d30-d31}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d30-d31}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0x1d1d1d1d 0x1d1d1d1d Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa2a2a2a2 0xa2a2a2a2 Qm (i8)0x0000000e Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa2a2a2a2 0xa2a2a2a2 Qm (i8)0x0000000e Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0x12125656 0x12125656 Qm (i32)0x07030501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0x1514191f 0x1514191f Qm (i32)0x07030501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0xa4a25656 0xa4a25656 Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0xa4a2191f 0xa4a2191f Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0x12a2a256 0x12a2a256 Qm (i32)0x070e0e01 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0x15a2a21f 0x15a2a21f Qm (i32)0x070e0e01 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0xa300a156 0xa300a156 Qm (i32)0x0d130f01 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0xa300a11f 0xa300a11f Qm (i32)0x0d130f01 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0x12125600 0x12125600 Qm (i32)0x07030511 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d3}, d31 :: Qd 0x15141900 0x15141900 Qm (i32)0x07030511 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d2-d4}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d2-d4}, d1 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d1-d3}, d10 :: Qd 0xcccccccc 0xcccccccc Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d1-d3}, d10 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d29-d31}, d1 :: Qd 0xcacacaca 0xcacacaca Qm (i8)0x00000017 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d29-d31}, d1 :: Qd 0x15151515 0x15151515 Qm (i8)0x00000017 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0x1b1b1b1b 0x1b1b1b1b Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0xcdcdcdcd 0xcdcdcdcd Qm (i8)0x00000010 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0x1c1c1c1c 0x1c1c1c1c Qm (i8)0x00000010 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0xcccccccc 0xcccccccc Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d22-d24}, d1 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa212cc78 0xa212cc78 Qm (i32)0x0a031504 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa212191b 0xa212191b Qm (i32)0x0a031504 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa4a25656 0xa4a25656 Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa4a21a1e 0xa4a21a1e Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0xcaa200a1 0xcaa200a1 Qm (i32)0x170efe0f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0x15a200a1 0x15a200a1 Qm (i32)0x170efe0f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa3caa1cc 0xa3caa1cc Qm (i32)0x0d130f11 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa314a11f 0xa314a11f Qm (i32)0x0d130f11 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0x12a1cccc 0x12a1cccc Qm (i32)0x070f1511 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d30, {d2-d4}, d31 :: Qd 0x13a1191f 0x13a1191f Qm (i32)0x070f1511 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbl.8 d0, {d2-d5}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d2-d5}, d1 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d1-d4}, d10 :: Qd 0xcccccccc 0xcccccccc Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d1-d4}, d10 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d28-d31}, d1 :: Qd 0xcacacaca 0xcacacaca Qm (i8)0x00000017 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d28-d31}, d1 :: Qd 0x15151515 0x15151515 Qm (i8)0x00000017 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0xfdfdfdfd 0xfdfdfdfd Qm (i8)0x0000001a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0xfdfdfdfd 0xfdfdfdfd Qm (i8)0x0000001a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0x1b1b1b1b 0x1b1b1b1b Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0xcbcbcbcb 0xcbcbcbcb Qm (i8)0x00000016 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0x1d1d1d1d 0x1d1d1d1d Qm (i8)0x00000016 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0xfefefefe 0xfefefefe Qm (i8)0x0000001f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d0, {d22-d25}, d1 :: Qd 0xfefefefe 0xfefefefe Qm (i8)0x0000001f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0xfd12cc00 0xfd12cc00 Qm (i32)0x1a0315ff Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0xfd121900 0xfd121900 Qm (i32)0x1a0315ff Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0xa4a25656 0xa4a25656 Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0xa4a21a1e 0xa4a21a1e Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0xcafd00a1 0xcafd00a1 Qm (i32)0x171efe0f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0x15fd00a1 0x15fd00a1 Qm (i32)0x171efe0f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0xfccaa1fd 0xfccaa1fd Qm (i32)0x1d130f1a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0xfc14a1fd 0xfc14a1fd Qm (i32)0x1d130f1a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0xcacdfbcc 0xcacdfbcc Qm (i32)0x17101c11 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbl.8 d30, {d2-d5}, d31 :: Qd 0x151cfb1f 0x151cfb1f Qm (i32)0x17101c11 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +---- VTBX ---- +vtbx.8 d0, {d2}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d0, {d2}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d0, {d31}, d1 :: Qd 0x12121212 0x12121212 Qm (i8)0x00000007 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d0, {d31}, d1 :: Qd 0x12121212 0x12121212 Qm (i8)0x00000007 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d0, {d20}, d1 :: Qd 0x56565656 0x56565656 Qm (i8)0x00000001 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d0, {d20}, d1 :: Qd 0x56565656 0x56565656 Qm (i8)0x00000001 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d0, {d2}, d31 :: Qd 0x34343434 0x34343434 Qm (i8)0x00000002 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d0, {d2}, d31 :: Qd 0x34343434 0x34343434 Qm (i8)0x00000002 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d30, {d2}, d1 :: Qd 0x12125656 0x12125656 Qm (i32)0x07030501 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d30, {d2}, d1 :: Qd 0x12125656 0x12125656 Qm (i32)0x07030501 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d31, {d2}, d1 :: Qd 0x56785678 0x56785678 Qm (i16)0x00000104 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d31, {d2}, d1 :: Qd 0x56785678 0x56785678 Qm (i16)0x00000104 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d30, {d2}, d1 :: Qd 0x12555656 0x12555656 Qm (i32)0x07080501 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d30, {d2}, d1 :: Qd 0x12555656 0x12555656 Qm (i32)0x07080501 Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d30, {d2}, d1 :: Qd 0x12555655 0x12555655 Qm (i32)0x07ed05ee Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d30, {d2}, d1 :: Qd 0x12555655 0x12555655 Qm (i32)0x07ed05ee Qn1 (i32)0x12345678 Qn2 (i32)0x12345678 Qn3 (i32)0x12345678 Qn4 (i32)0x12345678 +vtbx.8 d0, {d2-d3}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d2-d3}, d1 :: Qd 0x1c1c1c1c 0x1c1c1c1c Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d1-d2}, d3 :: Qd 0xa2a2a2a2 0xa2a2a2a2 Qm (i8)0x0000000a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d1-d2}, d3 :: Qd 0xa2a2a2a2 0xa2a2a2a2 Qm (i8)0x0000000a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d30-d31}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d30-d31}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0x1d1d1d1d 0x1d1d1d1d Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa2a2a2a2 0xa2a2a2a2 Qm (i8)0x0000000e Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa2a2a2a2 0xa2a2a2a2 Qm (i8)0x0000000e Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0x12125656 0x12125656 Qm (i32)0x07030501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0x1514191f 0x1514191f Qm (i32)0x07030501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0xa4a25656 0xa4a25656 Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0xa4a2191f 0xa4a2191f Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0x12a2a256 0x12a2a256 Qm (i32)0x070e0e01 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0x15a2a21f 0x15a2a21f Qm (i32)0x070e0e01 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0xa355a156 0xa355a156 Qm (i32)0x0d130f01 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0xa355a11f 0xa355a11f Qm (i32)0x0d130f01 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0x12125655 0x12125655 Qm (i32)0x07030511 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d3}, d31 :: Qd 0x15141955 0x15141955 Qm (i32)0x07030511 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0x12345678 Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d2-d4}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d2-d4}, d1 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d1-d3}, d10 :: Qd 0xcccccccc 0xcccccccc Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d1-d3}, d10 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d29-d31}, d1 :: Qd 0xcacacaca 0xcacacaca Qm (i8)0x00000017 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d29-d31}, d1 :: Qd 0x15151515 0x15151515 Qm (i8)0x00000017 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1 Qm (i8)0x0000000f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0x1b1b1b1b 0x1b1b1b1b Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0xcdcdcdcd 0xcdcdcdcd Qm (i8)0x00000010 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0x1c1c1c1c 0x1c1c1c1c Qm (i8)0x00000010 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0xcccccccc 0xcccccccc Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d22-d24}, d1 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa212cc78 0xa212cc78 Qm (i32)0x0a031504 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa212191b 0xa212191b Qm (i32)0x0a031504 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa4a25656 0xa4a25656 Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa4a21a1e 0xa4a21a1e Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0xcaa255a1 0xcaa255a1 Qm (i32)0x170efe0f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0x15a255a1 0x15a255a1 Qm (i32)0x170efe0f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa3caa1cc 0xa3caa1cc Qm (i32)0x0d130f11 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa314a11f 0xa314a11f Qm (i32)0x0d130f11 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0x12a1cccc 0x12a1cccc Qm (i32)0x070f1511 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d30, {d2-d4}, d31 :: Qd 0x13a1191f 0x13a1191f Qm (i32)0x070f1511 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xa1a2a3a4 +vtbx.8 d0, {d2-d5}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d2-d5}, d1 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000000 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d1-d4}, d10 :: Qd 0xcccccccc 0xcccccccc Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d1-d4}, d10 :: Qd 0x1f1f1f1f 0x1f1f1f1f Qm (i8)0x00000011 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d28-d31}, d1 :: Qd 0xcacacaca 0xcacacaca Qm (i8)0x00000017 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d28-d31}, d1 :: Qd 0x15151515 0x15151515 Qm (i8)0x00000017 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3 Qm (i8)0x00000009 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0xfdfdfdfd 0xfdfdfdfd Qm (i8)0x0000001a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0xfdfdfdfd 0xfdfdfdfd Qm (i8)0x0000001a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0x78787878 0x78787878 Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0x1b1b1b1b 0x1b1b1b1b Qm (i8)0x00000004 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0xcbcbcbcb 0xcbcbcbcb Qm (i8)0x00000016 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0x1d1d1d1d 0x1d1d1d1d Qm (i8)0x00000016 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0xfefefefe 0xfefefefe Qm (i8)0x0000001f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d0, {d22-d25}, d1 :: Qd 0xfefefefe 0xfefefefe Qm (i8)0x0000001f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0xfd12cc55 0xfd12cc55 Qm (i32)0x1a0315ff Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0xfd121955 0xfd121955 Qm (i32)0x1a0315ff Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0xa4a25656 0xa4a25656 Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0xa4a21a1e 0xa4a21a1e Qm (i32)0x0c0a0501 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0xcafd55a1 0xcafd55a1 Qm (i32)0x171efe0f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0x15fd55a1 0x15fd55a1 Qm (i32)0x171efe0f Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0xfccaa1fd 0xfccaa1fd Qm (i32)0x1d130f1a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0xfc14a1fd 0xfc14a1fd Qm (i32)0x1d130f1a Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0xcacdfbcc 0xcacdfbcc Qm (i32)0x17101c11 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +vtbx.8 d30, {d2-d5}, d31 :: Qd 0x151cfb1f 0x151cfb1f Qm (i32)0x17101c11 Qn1 (i32)0x12345678 Qn2 (i32)0xa1a2a3a4 Qn3 (i32)0xcacbcccd Qn4 (i32)0xfefdfcfb +---- VPMAX (integer) ---- +vpmax.s32 d0, d1, d2 :: Qd 0x00000079 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000079 +vpmax.s32 d0, d1, d2 :: Qd 0x00000079 0x131b1a1b Qm (i32)0x00000019 Qn (i32)0x00000079 +vpmax.s32 d0, d1, d2 :: Qd 0x00000079 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000079 +vpmax.s32 d0, d1, d2 :: Qd 0x00000079 0x131b1a1b Qm (i32)0x000000fa Qn (i32)0x00000079 +vpmax.s32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vpmax.s32 d0, d1, d2 :: Qd 0x0000008c 0x131b1a1b Qm (i32)0x0000008c Qn (i32)0x0000008c +vpmax.s16 d0, d1, d2 :: Qd 0x00780078 0x01400140 Qm (i32)0x01200140 Qn (i32)0x00000078 +vpmax.s16 d0, d1, d2 :: Qd 0x00780078 0x1a1b1e1f Qm (i32)0x01200140 Qn (i32)0x00000078 +vpmax.s8 d0, d1, d2 :: Qd 0x00780078 0x00780078 Qm (i32)0x00000078 Qn (i32)0x00000078 +vpmax.s8 d0, d1, d2 :: Qd 0x00780078 0x1b1b1f1f Qm (i32)0x00000078 Qn (i32)0x00000078 +vpmax.s8 d5, d7, d5 :: Qd 0x00020002 0x00010001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.s8 d5, d7, d5 :: Qd 0x00020002 0x1b1b1f1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.s16 d0, d1, d2 :: Qd 0x00020002 0x00010001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.s16 d0, d1, d2 :: Qd 0x00020002 0x1a1b1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.s32 d0, d1, d2 :: Qd 0x80000002 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.s32 d0, d1, d2 :: Qd 0x80000002 0x131b1a1b Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.s8 d5, d7, d5 :: Qd 0x00030003 0x00010001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.s8 d5, d7, d5 :: Qd 0x00030003 0x1b1b1f1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.s16 d0, d1, d2 :: Qd 0x00030003 0x00010001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.s16 d0, d1, d2 :: Qd 0x00030003 0x1a1b1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.s32 d0, d1, d2 :: Qd 0x80000003 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.s32 d0, d1, d2 :: Qd 0x80000003 0x131b1a1b Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.s8 d5, d7, d5 :: Qd 0x00020002 0x00040004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.s8 d5, d7, d5 :: Qd 0x00020002 0x1b1b1f1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.s16 d0, d1, d2 :: Qd 0x00020002 0x00040004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.s16 d0, d1, d2 :: Qd 0x00020002 0x1a1b1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.s32 d0, d1, d2 :: Qd 0x80000002 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.s32 d0, d1, d2 :: Qd 0x80000002 0x131b1a1b Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.s32 d10, d11, d12 :: Qd 0x00000078 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078 +vpmax.s32 d10, d11, d12 :: Qd 0x00000078 0x131b1a1b Qm (i32)0x00000018 Qn (i32)0x00000078 +vpmax.u32 d0, d1, d2 :: Qd 0x00000078 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000078 +vpmax.u32 d0, d1, d2 :: Qd 0x00000078 0x131b1a1b Qm (i32)0x00000019 Qn (i32)0x00000078 +vpmax.u32 d0, d1, d2 :: Qd 0x00000078 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000078 +vpmax.u32 d0, d1, d2 :: Qd 0x00000078 0x131b1a1b Qm (i32)0x000000fa Qn (i32)0x00000078 +vpmax.u32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vpmax.u32 d0, d1, d2 :: Qd 0x0000008c 0x131b1a1b Qm (i32)0x0000008c Qn (i32)0x0000008c +vpmax.u16 d0, d1, d2 :: Qd 0x00780078 0x01400140 Qm (i32)0x01200140 Qn (i32)0x00000078 +vpmax.u16 d0, d1, d2 :: Qd 0x00780078 0x1a1b1e1f Qm (i32)0x01200140 Qn (i32)0x00000078 +vpmax.u8 d0, d1, d2 :: Qd 0x00780078 0x20212021 Qm (i32)0x01202120 Qn (i32)0x00000078 +vpmax.u8 d0, d1, d2 :: Qd 0x00780078 0x1b1b1f1f Qm (i32)0x01202120 Qn (i32)0x00000078 +vpmax.u8 d0, d1, d2 :: Qd 0x80028002 0x80018001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.u8 d0, d1, d2 :: Qd 0x80028002 0x1b1b1f1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x1a1b1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.u32 d0, d1, d2 :: Qd 0x80000002 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.u32 d0, d1, d2 :: Qd 0x80000002 0x131b1a1b Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmax.u8 d0, d1, d2 :: Qd 0x80038003 0x80018001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.u8 d0, d1, d2 :: Qd 0x80038003 0x1b1b1f1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x1a1b1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.u32 d0, d1, d2 :: Qd 0x80000003 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.u32 d0, d1, d2 :: Qd 0x80000003 0x131b1a1b Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmax.u8 d0, d1, d2 :: Qd 0x80028002 0x80048004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.u8 d0, d1, d2 :: Qd 0x80028002 0x1b1b1f1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x1a1b1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.u32 d0, d1, d2 :: Qd 0x80000002 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.u32 d0, d1, d2 :: Qd 0x80000002 0x131b1a1b Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmax.u32 d10, d11, d12 :: Qd 0x00000078 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078 +vpmax.u32 d10, d11, d12 :: Qd 0x00000078 0x131b1a1b Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VPMIN (integer) ---- +vpmin.s32 d0, d1, d2 :: Qd 0x00000079 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000079 +vpmin.s32 d0, d1, d2 :: Qd 0x00000079 0x121f1e1f Qm (i32)0x00000019 Qn (i32)0x00000079 +vpmin.s32 d0, d1, d2 :: Qd 0x00000079 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000079 +vpmin.s32 d0, d1, d2 :: Qd 0x00000079 0x121f1e1f Qm (i32)0x000000fa Qn (i32)0x00000079 +vpmin.s32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vpmin.s32 d0, d1, d2 :: Qd 0x0000008c 0x121f1e1f Qm (i32)0x0000008c Qn (i32)0x0000008c +vpmin.s16 d0, d1, d2 :: Qd 0x00000000 0x01200120 Qm (i32)0x01200140 Qn (i32)0x00000078 +vpmin.s16 d0, d1, d2 :: Qd 0x00000000 0x131b121f Qm (i32)0x01200140 Qn (i32)0x00000078 +vpmin.s8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078 +vpmin.s8 d0, d1, d2 :: Qd 0x00000000 0x131a121e Qm (i32)0x00000078 Qn (i32)0x00000078 +vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x131a121e Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x131b121f Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.s32 d0, d1, d2 :: Qd 0x80000002 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.s32 d0, d1, d2 :: Qd 0x80000002 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x131a121e Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x131b121f Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.s32 d0, d1, d2 :: Qd 0x80000003 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.s32 d0, d1, d2 :: Qd 0x80000003 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x131a121e Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x80008000 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x131b121f Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.s32 d0, d1, d2 :: Qd 0x80000002 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.s32 d0, d1, d2 :: Qd 0x80000002 0x121f1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.s32 d10, d11, d12 :: Qd 0x00000078 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078 +vpmin.s32 d10, d11, d12 :: Qd 0x00000078 0x121f1e1f Qm (i32)0x00000018 Qn (i32)0x00000078 +vpmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000078 +vpmin.u32 d0, d1, d2 :: Qd 0x00000078 0x121f1e1f Qm (i32)0x00000019 Qn (i32)0x00000078 +vpmin.u32 d0, d1, d2 :: Qd 0x00000078 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000078 +vpmin.u32 d0, d1, d2 :: Qd 0x00000078 0x121f1e1f Qm (i32)0x000000fa Qn (i32)0x00000078 +vpmin.u32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c +vpmin.u32 d0, d1, d2 :: Qd 0x0000008c 0x121f1e1f Qm (i32)0x0000008c Qn (i32)0x0000008c +vpmin.u16 d0, d1, d2 :: Qd 0x00000000 0x01200120 Qm (i32)0x01200140 Qn (i32)0x00000078 +vpmin.u16 d0, d1, d2 :: Qd 0x00000000 0x131b121f Qm (i32)0x01200140 Qn (i32)0x00000078 +vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x01200120 Qm (i32)0x01202120 Qn (i32)0x00000078 +vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x131a121e Qm (i32)0x01202120 Qn (i32)0x00000078 +vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x131a121e Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.u16 d0, d1, d2 :: Qd 0x00020002 0x00010001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.u16 d0, d1, d2 :: Qd 0x00020002 0x131b121f Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.u32 d0, d1, d2 :: Qd 0x80000002 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.u32 d0, d1, d2 :: Qd 0x80000002 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000002 +vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x131a121e Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.u16 d0, d1, d2 :: Qd 0x00030003 0x00010001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.u16 d0, d1, d2 :: Qd 0x00030003 0x131b121f Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.u32 d0, d1, d2 :: Qd 0x80000003 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.u32 d0, d1, d2 :: Qd 0x80000003 0x121f1e1f Qm (i32)0x80000001 Qn (i32)0x80000003 +vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x131a121e Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.u16 d0, d1, d2 :: Qd 0x00020002 0x00040004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.u16 d0, d1, d2 :: Qd 0x00020002 0x131b121f Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.u32 d0, d1, d2 :: Qd 0x80000002 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.u32 d0, d1, d2 :: Qd 0x80000002 0x121f1e1f Qm (i32)0x80000004 Qn (i32)0x80000002 +vpmin.u32 d10, d11, d12 :: Qd 0x00000078 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078 +vpmin.u32 d10, d11, d12 :: Qd 0x00000078 0x121f1e1f Qm (i32)0x00000018 Qn (i32)0x00000078 +---- VQRDMULH ---- +vqrdmulh.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 d0, d1, d2 :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 d6, d7, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s32 d6, d7, d8 :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s16 d9, d11, d12 :: Qd 0x00000003 0x00000003 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 d9, d11, d12 :: Qd 0x0000003b 0x00000044 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6 :: Qd 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6 :: Qd 0x00000687 0x00000788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6 :: Qd 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6 :: Qd 0x00000687 0x00000788 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9 :: Qd 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9 :: Qd 0x00000002 0x00000002 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6 :: Qd 0x00000040 0x00000040 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6 :: Qd 0x00000687 0x00000788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 d10, d11, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 d10, d11, d15 :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 d10, d30, d31 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000 +vqrdmulh.s32 d10, d30, d31 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s16 d10, d30, d31 :: Qd 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 08000000 +vqrdmulh.s16 d10, d30, d31 :: Qd 0xece50000 0xede10000 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 00000000 +vqrdmulh.s32 d10, d30, d31 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 d10, d30, d31 :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s16 d10, d30, d31 :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqrdmulh.s16 d10, d30, d31 :: Qd 0x098e0000 0x09100000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VQRDMULH (by scalar) ---- +vqrdmulh.s32 d0, d1, d6[0] :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 d0, d1, d6[0] :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 d6, d7, d1[1] :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s32 d6, d7, d1[1] :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000 +vqrdmulh.s16 d9, d11, d7[0] :: Qd 0x00000003 0x00000003 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 d9, d11, d7[0] :: Qd 0x002b003b 0x00290044 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6[0] :: Qd 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6[0] :: Qd 0x04c70687 0x04880788 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9[1] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6[1] :: Qd 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6[1] :: Qd 0x04c70687 0x04880788 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9[0] :: Qd 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9[0] :: Qd 0x00000002 0x00000002 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6[2] :: Qd 0x04000040 0x04000040 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s16 d4, d5, d6[2] :: Qd 0x04c70687 0x04880788 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 d7, d8, d9[0] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000 +vqrdmulh.s32 d10, d31, d15[0] :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 d10, d31, d15[0] :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000 +vqrdmulh.s32 d10, d14, d15[1] :: Qd 0xffffff88 0xffffff88 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 d10, d14, d15[1] :: Qd 0x00000012 0x00000011 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s16 d10, d14, d7[3] :: Qd 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 08000000 +vqrdmulh.s16 d10, d14, d7[3] :: Qd 0xece5e5e5 0xede1e1e1 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 00000000 +vqrdmulh.s32 d10, d14, d15[1] :: Qd 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s32 d10, d14, d15[1] :: Qd 0xece4e5e5 0xede0e1e1 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000 +vqrdmulh.s16 d31, d14, d7[1] :: Qd 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +vqrdmulh.s16 d31, d14, d7[1] :: Qd 0x098e0d0e 0x09100f10 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000 +---- VADD (fp) ---- +vadd.f32 d0, d5, d2 :: Qd 0xc1b43ac6 0xc1b43ac6 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vadd.f32 d0, d5, d2 :: Qd 0xc2364659 0xc2364659 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vadd.f32 d3, d4, d5 :: Qd 0xc8a931cf 0xc8a931cf Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vadd.f32 d3, d4, d5 :: Qd 0x44a84000 0x44a84000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vadd.f32 d10, d11, d2 :: Qd 0x45398860 0x45398860 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vadd.f32 d10, d11, d2 :: Qd 0xc732da7a 0xc732da7a Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vadd.f32 d9, d5, d7 :: Qd 0x47dc9261 0x47dc9261 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vadd.f32 d9, d5, d7 :: Qd 0x46855200 0x46855200 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vadd.f32 d0, d5, d2 :: Qd 0xc88faac0 0xc88faac0 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vadd.f32 d0, d5, d2 :: Qd 0xc872bcb1 0xc872bcb1 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vadd.f32 d3, d4, d5 :: Qd 0x44ab5c08 0x44ab5c08 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vadd.f32 d3, d4, d5 :: Qd 0x44a84003 0x44a84003 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vadd.f32 d10, d11, d2 :: Qd 0x4742b4e6 0x4742b4e6 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vadd.f32 d10, d11, d2 :: Qd 0x44882666 0x44882666 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vadd.f32 d9, d5, d7 :: Qd 0x49d5e6b8 0x49d5e6b8 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vadd.f32 d9, d5, d7 :: Qd 0x49d5e008 0x49d5e008 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vadd.f32 d0, d11, d12 :: Qd 0x48b0b752 0x48b0b752 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vadd.f32 d0, d11, d12 :: Qd 0x45b75812 0x45b75812 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vadd.f32 d7, d1, d6 :: Qd 0x420802fd 0x420802fd Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vadd.f32 d7, d1, d6 :: Qd 0x3b210e02 0x3b210e02 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vadd.f32 d0, d1, d2 :: Qd 0x4532d000 0x4532d000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vadd.f32 d0, d1, d2 :: Qd 0x42d60000 0x42d60000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vadd.f32 d3, d4, d5 :: Qd 0x450d299a 0x450d299a Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vadd.f32 d3, d4, d5 :: Qd 0x44ad1333 0x44ad1333 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vadd.f32 d10, d11, d2 :: Qd 0x44152592 0x44152592 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vadd.f32 d10, d11, d2 :: Qd 0x42da0000 0x42da0000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vadd.f32 d9, d5, d7 :: Qd 0x4573a000 0x4573a000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vadd.f32 d9, d5, d7 :: Qd 0x44db0000 0x44db0000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vadd.f32 d0, d11, d12 :: Qd 0xc5b695c3 0xc5b695c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vadd.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0xc5b4d3c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vadd.f32 d7, d1, d6 :: Qd 0x43e07a2a 0x43e07a2a Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vadd.f32 d7, d1, d6 :: Qd 0xc0e96d19 0xc0e96d19 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vadd.f32 d0, d5, d2 :: Qd 0x44053ee0 0x44053ee0 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vadd.f32 d0, d5, d2 :: Qd 0xbb965394 0xbb965394 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vadd.f32 d10, d13, d15 :: Qd 0xc4838fb4 0xc4838fb4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vadd.f32 d10, d13, d15 :: Qd 0xc40dcfae 0xc40dcfae Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vadd.f32 d10, d13, d15 :: Qd 0x488c3d8e 0x488c3d8e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vadd.f32 d10, d13, d15 :: Qd 0x4608d008 0x4608d008 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vadd.f32 d0, d1, d2 :: Qd 0x4efa8dc5 0x4efa8dc5 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vadd.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e920233 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vadd.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vadd.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vadd.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vadd.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vadd.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vadd.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x00000000 +vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vadd.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vadd.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x00000000 +vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vadd.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vadd.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x00000000 +vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VSUB (fp) ---- +vsub.f32 d0, d5, d2 :: Qd 0x428937a8 0x428937a8 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vsub.f32 d0, d5, d2 :: Qd 0x42364659 0x42364659 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vsub.f32 d3, d4, d5 :: Qd 0xc8aa824f 0xc8aa824f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vsub.f32 d3, d4, d5 :: Qd 0xc4a84000 0xc4a84000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vsub.f32 d10, d11, d2 :: Qd 0x47b8a6bd 0x47b8a6bd Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vsub.f32 d10, d11, d2 :: Qd 0x4732da7a 0x4732da7a Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vsub.f32 d9, d5, d7 :: Qd 0x4799e961 0x4799e961 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vsub.f32 d9, d5, d7 :: Qd 0xc6855200 0xc6855200 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vsub.f32 d0, d5, d2 :: Qd 0x484623e2 0x484623e2 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vsub.f32 d0, d5, d2 :: Qd 0x4872bcb1 0x4872bcb1 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vsub.f32 d3, d4, d5 :: Qd 0xc4a54000 0xc4a54000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vsub.f32 d3, d4, d5 :: Qd 0xc4a84000 0xc4a84000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vsub.f32 d10, d11, d2 :: Qd 0x473a3200 0x473a3200 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vsub.f32 d10, d11, d2 :: Qd 0xc4882000 0xc4882000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vsub.f32 d9, d5, d7 :: Qd 0xc9d5d958 0xc9d5d958 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vsub.f32 d9, d5, d7 :: Qd 0xc9d5e008 0xc9d5e008 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vsub.f32 d0, d11, d12 :: Qd 0x48aafc92 0x48aafc92 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vsub.f32 d0, d11, d12 :: Qd 0xc5b75812 0xc5b75812 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vsub.f32 d7, d1, d6 :: Qd 0x4207fdf5 0x4207fdf5 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vsub.f32 d7, d1, d6 :: Qd 0xbb210e02 0xbb210e02 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vsub.f32 d0, d1, d2 :: Qd 0x45257000 0x45257000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vsub.f32 d0, d1, d2 :: Qd 0xc2d60000 0xc2d60000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vsub.f32 d3, d4, d5 :: Qd 0xc3ff4ccc 0xc3ff4ccc Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vsub.f32 d3, d4, d5 :: Qd 0xc4ad1333 0xc4ad1333 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vsub.f32 d10, d11, d2 :: Qd 0x43bd4b23 0x43bd4b23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vsub.f32 d10, d11, d2 :: Qd 0xc2da0000 0xc2da0000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vsub.f32 d9, d5, d7 :: Qd 0x43c50000 0x43c50000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vsub.f32 d9, d5, d7 :: Qd 0xc4db0000 0xc4db0000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vsub.f32 d0, d11, d12 :: Qd 0x45b311c3 0x45b311c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vsub.f32 d0, d11, d12 :: Qd 0x45b4d3c3 0x45b4d3c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vsub.f32 d7, d1, d6 :: Qd 0x43e7c592 0x43e7c592 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vsub.f32 d7, d1, d6 :: Qd 0x40e96d19 0x40e96d19 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vsub.f32 d0, d5, d2 :: Qd 0x44053f76 0x44053f76 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vsub.f32 d0, d5, d2 :: Qd 0x3b965394 0x3b965394 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vsub.f32 d10, d13, d15 :: Qd 0x42a3ffa4 0x42a3ffa4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vsub.f32 d10, d13, d15 :: Qd 0x440dcfae 0x440dcfae Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vsub.f32 d10, d13, d15 :: Qd 0x4883b08e 0x4883b08e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vsub.f32 d10, d13, d15 :: Qd 0xc608d008 0xc608d008 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vsub.f32 d0, d1, d2 :: Qd 0xcda5da84 0xcda5da84 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vsub.f32 d0, d1, d2 :: Qd 0xce920233 0xce920233 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vsub.f32 d0, d1, d2 :: Qd 0xbf800000 0xbf800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vsub.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vsub.f32 d0, d1, d2 :: Qd 0xbf800000 0xbf800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vsub.f32 d0, d1, d2 :: Qd 0xbf800000 0xbf800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vsub.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vsub.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x00000000 +vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vsub.f32 d0, d1, d2 :: Qd 0xbf800000 0xbf800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vsub.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x00000000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vsub.f32 d0, d1, d2 :: Qd 0xbf800000 0xbf800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vsub.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x00000000 +vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMUL (fp) ---- +vmul.f32 d0, d5, d2 :: Qd 0xc4833ce4 0xc4833ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmul.f32 d0, d5, d2 :: Qd 0x95dcde5d 0x94e29647 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmul.f32 d3, d4, d5 :: Qd 0xcddf4321 0xcddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmul.f32 d3, d4, d5 :: Qd 0x184bdfd0 0x17512718 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmul.f32 d10, d11, d2 :: Qd 0xcf050e7f 0xcf050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmul.f32 d10, d11, d2 :: Qd 0x9ad8b90a 0x99de557a Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmul.f32 d9, d5, d7 :: Qd 0x4ec3063f 0x4ec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmul.f32 d9, d5, d7 :: Qd 0x1a218c7d 0x1925bb3c Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmul.f32 d0, d5, d2 :: Qd 0x5029254c 0x5029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmul.f32 d0, d5, d2 :: Qd 0x9c131100 0x9b16dfc1 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmul.f32 d3, d4, d5 :: Qd 0x46fc6000 0x46fc6000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmul.f32 d3, d4, d5 :: Qd 0x184bdfd0 0x17512718 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmul.f32 d10, d11, d2 :: Qd 0x4c4a89cd 0x4c4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmul.f32 d10, d11, d2 :: Qd 0x1824f283 0x172937c8 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmul.f32 d9, d5, d7 :: Qd 0x4db2c947 0x4db2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmul.f32 d9, d5, d7 :: Qd 0x1d819474 0x1c84ef4f Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmul.f32 d0, d11, d12 :: Qd 0x4ef90536 0x4ef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmul.f32 d0, d11, d12 :: Qd 0x195e2a0a 0x1863ea8b Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmul.f32 d7, d1, d6 :: Qd 0x3dab1f7a 0x3dab1f7a Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmul.f32 d7, d1, d6 :: Qd 0x0ec327cf 0x0dc8354d Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmul.f32 d0, d1, d2 :: Qd 0x488fe2c0 0x488fe2c0 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmul.f32 d0, d1, d2 :: Qd 0x1681a7d3 0x1585032e Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmul.f32 d3, d4, d5 :: Qd 0x4993b8e3 0x4993b8e3 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmul.f32 d3, d4, d5 :: Qd 0x1851b88c 0x17572694 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmul.f32 d10, d11, d2 :: Qd 0x474f9afc 0x474f9afc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmul.f32 d10, d11, d2 :: Qd 0x1684143b 0x15877fa6 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmul.f32 d9, d5, d7 :: Qd 0x4a657ac0 0x4a657ac0 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmul.f32 d9, d5, d7 :: Qd 0x1884af55 0x17881ec5 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmul.f32 d0, d11, d12 :: Qd 0x489eee1e 0x489eee1e Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmul.f32 d0, d11, d12 :: Qd 0x995b1d4f 0x9860c99a Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmul.f32 d7, d1, d6 :: Qd 0xc5500239 0xc5500239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmul.f32 d7, d1, d6 :: Qd 0x948d6cdc 0x9391163a Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmul.f32 d0, d5, d2 :: Qd 0xc01c7d07 0xc01c7d07 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmul.f32 d0, d5, d2 :: Qd 0x8f3627de 0x8e3adf32 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmul.f32 d10, d13, d15 :: Qd 0x488666a6 0x488666a6 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmul.f32 d10, d13, d15 :: Qd 0x97abd669 0x96b04959 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmul.f32 d10, d13, d15 :: Qd 0x4f115379 0x4f115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmul.f32 d10, d13, d15 :: Qd 0x19a5c7d1 0x18aa129c Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmul.f32 d0, d1, d2 :: Qd 0x5d6e81fd 0x5d6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmul.f32 d0, d1, d2 :: Qd 0x2230ec71 0x21358117 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmul.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmul.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmul.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmul.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmul.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmul.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmul.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmul.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmul.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmul.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMLA (fp) ---- +vmla.f32 d0, d5, d2 :: Qd 0xc4831ce4 0xc4831ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmla.f32 d0, d5, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmla.f32 d3, d4, d5 :: Qd 0xcddf4321 0xcddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmla.f32 d3, d4, d5 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmla.f32 d10, d11, d2 :: Qd 0xcf050e7f 0xcf050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmla.f32 d10, d11, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmla.f32 d9, d5, d7 :: Qd 0x4ec3063f 0x4ec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmla.f32 d9, d5, d7 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmla.f32 d0, d5, d2 :: Qd 0x5029254c 0x5029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmla.f32 d0, d5, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmla.f32 d3, d4, d5 :: Qd 0x46fc6200 0x46fc6200 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmla.f32 d3, d4, d5 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmla.f32 d10, d11, d2 :: Qd 0x4c4a89cd 0x4c4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmla.f32 d10, d11, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmla.f32 d9, d5, d7 :: Qd 0x4db2c947 0x4db2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmla.f32 d9, d5, d7 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmla.f32 d0, d11, d12 :: Qd 0x4ef90536 0x4ef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmla.f32 d0, d11, d12 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmla.f32 d7, d1, d6 :: Qd 0x3f8ab1f8 0x3f8ab1f8 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmla.f32 d7, d1, d6 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmla.f32 d0, d1, d2 :: Qd 0x488fe2e0 0x488fe2e0 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmla.f32 d3, d4, d5 :: Qd 0x4993b8eb 0x4993b8eb Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmla.f32 d3, d4, d5 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmla.f32 d10, d11, d2 :: Qd 0x474f9bfc 0x474f9bfc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmla.f32 d10, d11, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmla.f32 d9, d5, d7 :: Qd 0x4a657ac4 0x4a657ac4 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmla.f32 d9, d5, d7 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmla.f32 d0, d11, d12 :: Qd 0x489eee3e 0x489eee3e Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmla.f32 d0, d11, d12 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmla.f32 d7, d1, d6 :: Qd 0xc54ff239 0xc54ff239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmla.f32 d7, d1, d6 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmla.f32 d0, d5, d2 :: Qd 0xbfb8fa0e 0xbfb8fa0e Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmla.f32 d0, d5, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmla.f32 d10, d13, d15 :: Qd 0x488666c6 0x488666c6 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmla.f32 d10, d13, d15 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmla.f32 d10, d13, d15 :: Qd 0x4f115379 0x4f115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmla.f32 d10, d13, d15 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmla.f32 d0, d1, d2 :: Qd 0x5d6e81fd 0x5d6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMLA (fp by scalar) ---- +vmla.f32 d0, d1, d4[0] :: Qd 0x45341000 0x45341000 Qm (i32)0x41c00000 Qn (i32)0x42f00000 +vmla.f32 d0, d1, d4[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x41c00000 Qn (i32)0x42f00000 +vmla.f32 d31, d8, d7[1] :: Qd 0xc6833e00 0xc6833e00 Qm (i32)0x430c0000 Qn (i32)0xc2f00000 +vmla.f32 d31, d8, d7[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x430c0000 Qn (i32)0xc2f00000 +vmla.f32 d4, d8, d15[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.f32 d4, d8, d15[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.f32 d7, d8, d1[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmla.f32 d7, d8, d1[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmla.f32 d17, d8, d1[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.f32 d17, d8, d1[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmla.f32 d7, d8, d1[0] :: Qd 0x447a3fff 0x447a3fff Qm (i32)0x64078678 Qn (i32)0x1fec1e4a +vmla.f32 d7, d8, d1[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x64078678 Qn (i32)0x1fec1e4a +vmla.f32 d7, d24, d1[0] :: Qd 0x65a96816 0x65a96816 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7 +vmla.f32 d7, d24, d1[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMLS (fp) ---- +vmls.f32 d0, d5, d2 :: Qd 0x44835ce4 0x44835ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmls.f32 d0, d5, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmls.f32 d3, d4, d5 :: Qd 0x4ddf4321 0x4ddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmls.f32 d3, d4, d5 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmls.f32 d10, d11, d2 :: Qd 0x4f050e7f 0x4f050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmls.f32 d10, d11, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmls.f32 d9, d5, d7 :: Qd 0xcec3063f 0xcec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmls.f32 d9, d5, d7 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmls.f32 d0, d5, d2 :: Qd 0xd029254c 0xd029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmls.f32 d0, d5, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmls.f32 d3, d4, d5 :: Qd 0xc6fc5e00 0xc6fc5e00 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmls.f32 d3, d4, d5 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vmls.f32 d10, d11, d2 :: Qd 0xcc4a89cd 0xcc4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmls.f32 d10, d11, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vmls.f32 d9, d5, d7 :: Qd 0xcdb2c947 0xcdb2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmls.f32 d9, d5, d7 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmls.f32 d0, d11, d12 :: Qd 0xcef90536 0xcef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmls.f32 d0, d11, d12 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmls.f32 d7, d1, d6 :: Qd 0x3f6a9c11 0x3f6a9c11 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmls.f32 d7, d1, d6 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmls.f32 d0, d1, d2 :: Qd 0xc88fe2a0 0xc88fe2a0 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmls.f32 d3, d4, d5 :: Qd 0xc993b8db 0xc993b8db Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmls.f32 d3, d4, d5 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmls.f32 d10, d11, d2 :: Qd 0xc74f99fc 0xc74f99fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmls.f32 d10, d11, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmls.f32 d9, d5, d7 :: Qd 0xca657abc 0xca657abc Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmls.f32 d9, d5, d7 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmls.f32 d0, d11, d12 :: Qd 0xc89eedfe 0xc89eedfe Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmls.f32 d0, d11, d12 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmls.f32 d7, d1, d6 :: Qd 0x45501239 0x45501239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmls.f32 d7, d1, d6 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmls.f32 d0, d5, d2 :: Qd 0x405c7d07 0x405c7d07 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmls.f32 d0, d5, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmls.f32 d10, d13, d15 :: Qd 0xc8866686 0xc8866686 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmls.f32 d10, d13, d15 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmls.f32 d10, d13, d15 :: Qd 0xcf115379 0xcf115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmls.f32 d10, d13, d15 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmls.f32 d0, d1, d2 :: Qd 0xdd6e81fd 0xdd6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMLS (fp by scalar) ---- +vmls.f32 d0, d1, d4[0] :: Qd 0xc533f000 0xc533f000 Qm (i32)0x41c00000 Qn (i32)0x42f00000 +vmls.f32 d0, d1, d4[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x41c00000 Qn (i32)0x42f00000 +vmls.f32 d31, d8, d7[1] :: Qd 0x46834200 0x46834200 Qm (i32)0x430c0000 Qn (i32)0xc2f00000 +vmls.f32 d31, d8, d7[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x430c0000 Qn (i32)0xc2f00000 +vmls.f32 d4, d8, d15[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.f32 d4, d8, d15[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.f32 d7, d8, d1[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmls.f32 d7, d8, d1[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c +vmls.f32 d17, d8, d1[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.f32 d17, d8, d1[1] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002 +vmls.f32 d7, d8, d1[0] :: Qd 0xc479bfff 0xc479bfff Qm (i32)0x64078678 Qn (i32)0x1fec1e4a +vmls.f32 d7, d8, d1[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x64078678 Qn (i32)0x1fec1e4a +vmls.f32 d7, d24, d1[0] :: Qd 0xe5a96816 0xe5a96816 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7 +vmls.f32 d7, d24, d1[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VABD (fp) ---- +vabd.f32 d0, d5, d2 :: Qd 0x428937a8 0x428937a8 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vabd.f32 d0, d5, d2 :: Qd 0x42364659 0x42364659 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vabd.f32 d3, d4, d5 :: Qd 0x48aa824f 0x48aa824f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vabd.f32 d3, d4, d5 :: Qd 0x44a84000 0x44a84000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vabd.f32 d10, d11, d2 :: Qd 0x47b8a6bd 0x47b8a6bd Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vabd.f32 d10, d11, d2 :: Qd 0x4732da7a 0x4732da7a Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vabd.f32 d9, d5, d7 :: Qd 0x4799e961 0x4799e961 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vabd.f32 d9, d5, d7 :: Qd 0x46855200 0x46855200 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vabd.f32 d0, d5, d2 :: Qd 0x484623e2 0x484623e2 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vabd.f32 d0, d5, d2 :: Qd 0x4872bcb1 0x4872bcb1 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vabd.f32 d3, d4, d5 :: Qd 0x44a54000 0x44a54000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vabd.f32 d3, d4, d5 :: Qd 0x44a84000 0x44a84000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vabd.f32 d10, d11, d2 :: Qd 0x473a3200 0x473a3200 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vabd.f32 d10, d11, d2 :: Qd 0x44882000 0x44882000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vabd.f32 d9, d5, d7 :: Qd 0x49d5d958 0x49d5d958 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vabd.f32 d9, d5, d7 :: Qd 0x49d5e008 0x49d5e008 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vabd.f32 d0, d11, d12 :: Qd 0x48aafc92 0x48aafc92 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vabd.f32 d0, d11, d12 :: Qd 0x45b75812 0x45b75812 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vabd.f32 d7, d1, d6 :: Qd 0x4207fdf5 0x4207fdf5 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vabd.f32 d7, d1, d6 :: Qd 0x3b210e02 0x3b210e02 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vabd.f32 d0, d1, d2 :: Qd 0x45257000 0x45257000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vabd.f32 d0, d1, d2 :: Qd 0x42d60000 0x42d60000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vabd.f32 d3, d4, d5 :: Qd 0x43ff4ccc 0x43ff4ccc Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vabd.f32 d3, d4, d5 :: Qd 0x44ad1333 0x44ad1333 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vabd.f32 d10, d11, d2 :: Qd 0x43bd4b23 0x43bd4b23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vabd.f32 d10, d11, d2 :: Qd 0x42da0000 0x42da0000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vabd.f32 d9, d5, d7 :: Qd 0x43c50000 0x43c50000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vabd.f32 d9, d5, d7 :: Qd 0x44db0000 0x44db0000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vabd.f32 d0, d11, d12 :: Qd 0x45b311c3 0x45b311c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vabd.f32 d0, d11, d12 :: Qd 0x45b4d3c3 0x45b4d3c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vabd.f32 d7, d1, d6 :: Qd 0x43e7c592 0x43e7c592 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vabd.f32 d7, d1, d6 :: Qd 0x40e96d19 0x40e96d19 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vabd.f32 d0, d5, d2 :: Qd 0x44053f76 0x44053f76 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vabd.f32 d0, d5, d2 :: Qd 0x3b965394 0x3b965394 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vabd.f32 d10, d13, d15 :: Qd 0x42a3ffa4 0x42a3ffa4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vabd.f32 d10, d13, d15 :: Qd 0x440dcfae 0x440dcfae Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vabd.f32 d10, d13, d15 :: Qd 0x4883b08e 0x4883b08e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vabd.f32 d10, d13, d15 :: Qd 0x4608d008 0x4608d008 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vabd.f32 d0, d1, d2 :: Qd 0x4da5da84 0x4da5da84 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vabd.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e920233 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +---- VPADD (fp) ---- +vpadd.f32 d0, d5, d2 :: Qd 0xc2b64659 0x423851ec Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vpadd.f32 d0, d5, d2 :: Qd 0xc2b64659 0x1342e1a3 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vpadd.f32 d3, d4, d5 :: Qd 0x45284000 0xc929da0f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vpadd.f32 d3, d4, d5 :: Qd 0x45284000 0x1342e1a3 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vpadd.f32 d10, d11, d2 :: Qd 0xc7b2da7a 0x47be7300 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vpadd.f32 d10, d11, d2 :: Qd 0xc7b2da7a 0x1342e1a3 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vpadd.f32 d9, d5, d7 :: Qd 0x47055200 0x483b3de1 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vpadd.f32 d9, d5, d7 :: Qd 0x47055200 0x1342e1a3 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vpadd.f32 d0, d5, d2 :: Qd 0xc8f2bcb1 0xc7b2633d Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vpadd.f32 d0, d5, d2 :: Qd 0xc8f2bcb1 0x1342e1a3 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vpadd.f32 d3, d4, d5 :: Qd 0x45284000 0x42400000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vpadd.f32 d3, d4, d5 :: Qd 0x45284000 0x1342e1a3 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vpadd.f32 d10, d11, d2 :: Qd 0x45082000 0x47be7300 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vpadd.f32 d10, d11, d2 :: Qd 0x45082000 0x1342e1a3 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vpadd.f32 d9, d5, d7 :: Qd 0x4a55e008 0x43d60000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vpadd.f32 d9, d5, d7 :: Qd 0x4a55e008 0x1342e1a3 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vpadd.f32 d0, d11, d12 :: Qd 0x46375812 0x492dd9f2 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vpadd.f32 d0, d11, d12 :: Qd 0x46375812 0x1342e1a3 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vpadd.f32 d7, d1, d6 :: Qd 0x3ba10e02 0x42880079 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vpadd.f32 d7, d1, d6 :: Qd 0x3ba10e02 0x1342e1a3 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vpadd.f32 d0, d1, d2 :: Qd 0x43560000 0x45ac2000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vpadd.f32 d0, d1, d2 :: Qd 0x43560000 0x1342e1a3 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vpadd.f32 d3, d4, d5 :: Qd 0x452d1333 0x44da8000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vpadd.f32 d3, d4, d5 :: Qd 0x452d1333 0x1342e1a3 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vpadd.f32 d10, d11, d2 :: Qd 0x435a0000 0x4473cb23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vpadd.f32 d10, d11, d2 :: Qd 0x435a0000 0x1342e1a3 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vpadd.f32 d9, d5, d7 :: Qd 0x455b0000 0x45862000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vpadd.f32 d9, d5, d7 :: Qd 0x455b0000 0x1342e1a3 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vpadd.f32 d0, d11, d12 :: Qd 0xc634d3c3 0xc2e10000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vpadd.f32 d0, d11, d12 :: Qd 0xc634d3c3 0x1342e1a3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vpadd.f32 d7, d1, d6 :: Qd 0xc1696d19 0x44641fde Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vpadd.f32 d7, d1, d6 :: Qd 0xc1696d19 0x1342e1a3 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vpadd.f32 d0, d5, d2 :: Qd 0xbc165394 0x44853f2b Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vpadd.f32 d0, d5, d2 :: Qd 0xbc165394 0x1342e1a3 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vpadd.f32 d10, d13, d15 :: Qd 0xc48dcfae 0xc4729f73 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vpadd.f32 d10, d13, d15 :: Qd 0xc48dcfae 0x1342e1a3 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vpadd.f32 d10, d13, d15 :: Qd 0x4688d008 0x4907f70e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vpadd.f32 d10, d13, d15 :: Qd 0x4688d008 0x1342e1a3 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vpadd.f32 d0, d1, d2 :: Qd 0x4f120233 0x4ed11724 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vpadd.f32 d0, d1, d2 :: Qd 0x4f120233 0x1342e1a3 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x1342e1a3 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x1342e1a3 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x1342e1a3 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x1342e1a3 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x1342e1a3 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x1342e1a3 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x1342e1a3 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x1342e1a3 Qm (i32)0x00000000 Qn (i32)0x00000000 +vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x1342e1a3 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x1342e1a3 Qm (i32)0x00000000 Qn (i32)0xff800000 +vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x1342e1a3 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x1342e1a3 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x1342e1a3 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x1342e1a3 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x1342e1a3 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x1342e1a3 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x1342e1a3 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x1342e1a3 Qm (i32)0xff800000 Qn (i32)0x00000000 +vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x1342e1a3 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x1342e1a3 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VCVT (integer <-> fp) ---- +vcvt.u32.f32 d0, d1 :: Qd 0x00000003 0x00000003 Qm (i32)0x404ccccd +vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x404ccccd +vcvt.u32.f32 d10, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vcvt.u32.f32 d10, d11 :: Qd 0x00000000 0x00000000 Qm (i32)0x64cb49b4 +vcvt.u32.f32 d15, d4 :: Qd 0xb2d05e00 0xb2d05e00 Qm (i32)0x4f32d05e +vcvt.u32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0x4f32d05e +vcvt.u32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.u32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.u32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.u32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.u32.f32 d12, d8 :: Qd 0x00000007 0x00000007 Qm (i32)0x40fff800 +vcvt.u32.f32 d12, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0x40fff800 +vcvt.u32.f32 d12, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.u32.f32 d12, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.s32.f32 d0, d1 :: Qd 0x00000003 0x00000003 Qm (i32)0x404ccccd +vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x404ccccd +vcvt.s32.f32 d20, d21 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x64cb49b4 +vcvt.s32.f32 d20, d21 :: Qd 0x00000000 0x00000000 Qm (i32)0x64cb49b4 +vcvt.s32.f32 d15, d4 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x4f32d05e +vcvt.s32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0x4f32d05e +vcvt.s32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.s32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.s32.f32 d15, d4 :: Qd 0xfffffff9 0xfffffff9 Qm (i32)0xc0e33333 +vcvt.s32.f32 d15, d4 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.s32.f32 d12, d8 :: Qd 0x00000007 0x00000007 Qm (i32)0x40fff800 +vcvt.s32.f32 d12, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0x40fff800 +vcvt.s32.f32 d12, d8 :: Qd 0xfffffff9 0xfffffff9 Qm (i32)0xc0fff800 +vcvt.s32.f32 d12, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.f32.u32 d0, d1 :: Qd 0x40e00000 0x40e00000 Qm (i32)0x00000007 +vcvt.f32.u32 d0, d1 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x00000007 +vcvt.f32.u32 d10, d11 :: Qd 0x4f000000 0x4f000000 Qm (i32)0x80000000 +vcvt.f32.u32 d10, d11 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x80000000 +vcvt.f32.u32 d0, d1 :: Qd 0x4f000000 0x4f000000 Qm (i32)0x80000001 +vcvt.f32.u32 d0, d1 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x80000001 +vcvt.f32.u32 d24, d26 :: Qd 0x4f000000 0x4f000000 Qm (i32)0x7fffffff +vcvt.f32.u32 d24, d26 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x7fffffff +vcvt.f32.u32 d0, d14 :: Qd 0x4e4282f4 0x4e4282f4 Qm (i32)0x30a0bcef +vcvt.f32.u32 d0, d14 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x30a0bcef +vcvt.f32.s32 d0, d1 :: Qd 0x40e00000 0x40e00000 Qm (i32)0x00000007 +vcvt.f32.s32 d0, d1 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x00000007 +vcvt.f32.s32 d30, d31 :: Qd 0xcf000000 0xcf000000 Qm (i32)0x80000000 +vcvt.f32.s32 d30, d31 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x80000000 +vcvt.f32.s32 d0, d1 :: Qd 0xcf000000 0xcf000000 Qm (i32)0x80000001 +vcvt.f32.s32 d0, d1 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x80000001 +vcvt.f32.s32 d0, d1 :: Qd 0x4f000000 0x4f000000 Qm (i32)0x7fffffff +vcvt.f32.s32 d0, d1 :: Qd 0x4da8e8c9 0x4da0e0f9 Qm (i32)0x7fffffff +vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.u32.f32 d0, d1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.s32.f32 d0, d1 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x7f800000 +vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcvt.s32.f32 d0, d1 :: Qd 0x80000000 0x80000000 Qm (i32)0xff800000 +vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VCVT (fixed <-> fp) ---- +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000019 0x00000019 Qm (i32)0x404ccccd +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x404ccccd +vcvt.u32.f32 d10, d11, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vcvt.u32.f32 d10, d11, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0x64cb49b4 +vcvt.u32.f32 d15, d4, #32 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vcvt.u32.f32 d15, d4, #32 :: Qd 0x00000000 0x00000000 Qm (i32)0x4f32d05e +vcvt.u32.f32 d15, d4, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.u32.f32 d15, d4, #7 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.u32.f32 d15, d4, #4 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.u32.f32 d15, d4, #4 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.u32.f32 d12, d8, #3 :: Qd 0x0000003f 0x0000003f Qm (i32)0x40fff800 +vcvt.u32.f32 d12, d8, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x40fff800 +vcvt.u32.f32 d12, d8, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.u32.f32 d12, d8, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.s32.f32 d0, d1, #5 :: Qd 0x00000066 0x00000066 Qm (i32)0x404ccccd +vcvt.s32.f32 d0, d1, #5 :: Qd 0x00000000 0x00000000 Qm (i32)0x404ccccd +vcvt.s32.f32 d20, d21, #1 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x64cb49b4 +vcvt.s32.f32 d20, d21, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0x64cb49b4 +vcvt.s32.f32 d15, d4, #8 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x4f32d05e +vcvt.s32.f32 d15, d4, #8 :: Qd 0x00000000 0x00000000 Qm (i32)0x4f32d05e +vcvt.s32.f32 d15, d4, #2 :: Qd 0xfffffffe 0xfffffffe Qm (i32)0xbf000000 +vcvt.s32.f32 d15, d4, #2 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf000000 +vcvt.s32.f32 d15, d4, #1 :: Qd 0xfffffff2 0xfffffff2 Qm (i32)0xc0e33333 +vcvt.s32.f32 d15, d4, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0e33333 +vcvt.s32.f32 d12, d8, #2 :: Qd 0x0000001f 0x0000001f Qm (i32)0x40fff800 +vcvt.s32.f32 d12, d8, #2 :: Qd 0x00000000 0x00000000 Qm (i32)0x40fff800 +vcvt.s32.f32 d12, d8, #2 :: Qd 0xffffffe1 0xffffffe1 Qm (i32)0xc0fff800 +vcvt.s32.f32 d12, d8, #2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc0fff800 +vcvt.f32.u32 d0, d1, #5 :: Qd 0x3e600000 0x3e600000 Qm (i32)0x00000007 +vcvt.f32.u32 d0, d1, #5 :: Qd 0x4b28e8c9 0x4b20e0f9 Qm (i32)0x00000007 +vcvt.f32.u32 d10, d11, #9 :: Qd 0x4a800000 0x4a800000 Qm (i32)0x80000000 +vcvt.f32.u32 d10, d11, #9 :: Qd 0x4928e8c9 0x4920e0f9 Qm (i32)0x80000000 +vcvt.f32.u32 d0, d1, #4 :: Qd 0x4d000000 0x4d000000 Qm (i32)0x80000001 +vcvt.f32.u32 d0, d1, #4 :: Qd 0x4ba8e8c9 0x4ba0e0f9 Qm (i32)0x80000001 +vcvt.f32.u32 d24, d26, #6 :: Qd 0x4c000000 0x4c000000 Qm (i32)0x7fffffff +vcvt.f32.u32 d24, d26, #6 :: Qd 0x4aa8e8c9 0x4aa0e0f9 Qm (i32)0x7fffffff +vcvt.f32.u32 d0, d14, #5 :: Qd 0x4bc282f4 0x4bc282f4 Qm (i32)0x30a0bcef +vcvt.f32.u32 d0, d14, #5 :: Qd 0x4b28e8c9 0x4b20e0f9 Qm (i32)0x30a0bcef +vcvt.f32.s32 d0, d1, #12 :: Qd 0x3ae00000 0x3ae00000 Qm (i32)0x00000007 +vcvt.f32.s32 d0, d1, #12 :: Qd 0x47a8e8c9 0x47a0e0f9 Qm (i32)0x00000007 +vcvt.f32.s32 d30, d31, #8 :: Qd 0xcb000000 0xcb000000 Qm (i32)0x80000000 +vcvt.f32.s32 d30, d31, #8 :: Qd 0x49a8e8c9 0x49a0e0f9 Qm (i32)0x80000000 +vcvt.f32.s32 d0, d1, #1 :: Qd 0xce800000 0xce800000 Qm (i32)0x80000001 +vcvt.f32.s32 d0, d1, #1 :: Qd 0x4d28e8c9 0x4d20e0f9 Qm (i32)0x80000001 +vcvt.f32.s32 d0, d1, #6 :: Qd 0x4c000000 0x4c000000 Qm (i32)0x7fffffff +vcvt.f32.s32 d0, d1, #6 :: Qd 0x4aa8e8c9 0x4aa0e0f9 Qm (i32)0x7fffffff +vcvt.f32.s32 d0, d14, #2 :: Qd 0x4d4282f4 0x4d4282f4 Qm (i32)0x30a0bcef +vcvt.f32.s32 d0, d14, #2 :: Qd 0x4ca8e8c9 0x4ca0e0f9 Qm (i32)0x30a0bcef +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.u32.f32 d0, d1, #3 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +vcvt.s32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.s32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcvt.s32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.s32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcvt.s32.f32 d0, d1, #3 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x7f800000 +vcvt.s32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcvt.s32.f32 d0, d1, #3 :: Qd 0x80000000 0x80000000 Qm (i32)0xff800000 +vcvt.s32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VMAX (fp) ---- +vmax.f32 d0, d5, d2 :: Qd 0x41b851ec 0x41b851ec Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmax.f32 d0, d5, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmax.f32 d3, d4, d5 :: Qd 0x44a84000 0x44a84000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmax.f32 d3, d4, d5 :: Qd 0x44a84000 0x44a84000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmax.f32 d10, d11, d2 :: Qd 0x473e7300 0x473e7300 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmax.f32 d10, d11, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmax.f32 d9, d5, d7 :: Qd 0x47bb3de1 0x47bb3de1 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmax.f32 d9, d5, d7 :: Qd 0x46855200 0x46855200 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmax.f32 d0, d5, d2 :: Qd 0xc732633d 0xc732633d Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmax.f32 d0, d5, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmax.f32 d3, d4, d5 :: Qd 0x44a84003 0x44a84003 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vmax.f32 d3, d4, d5 :: Qd 0x44a84003 0x44a84003 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vmax.f32 d10, d11, d2 :: Qd 0x473e73b3 0x473e73b3 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vmax.f32 d10, d11, d2 :: Qd 0x44882666 0x44882666 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vmax.f32 d9, d5, d7 :: Qd 0x49d5e008 0x49d5e008 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmax.f32 d9, d5, d7 :: Qd 0x49d5e008 0x49d5e008 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmax.f32 d0, d11, d12 :: Qd 0x48add9f2 0x48add9f2 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmax.f32 d0, d11, d12 :: Qd 0x45b75812 0x45b75812 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmax.f32 d7, d1, d6 :: Qd 0x42080079 0x42080079 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmax.f32 d7, d1, d6 :: Qd 0x3b210e02 0x3b210e02 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmax.f32 d0, d1, d2 :: Qd 0x452c2000 0x452c2000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmax.f32 d0, d1, d2 :: Qd 0x42d60000 0x42d60000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmax.f32 d3, d4, d5 :: Qd 0x44ad1333 0x44ad1333 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmax.f32 d3, d4, d5 :: Qd 0x44ad1333 0x44ad1333 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmax.f32 d10, d11, d2 :: Qd 0x43f3cb23 0x43f3cb23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmax.f32 d10, d11, d2 :: Qd 0x42da0000 0x42da0000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmax.f32 d9, d5, d7 :: Qd 0x45062000 0x45062000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmax.f32 d9, d5, d7 :: Qd 0x44db0000 0x44db0000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmax.f32 d0, d11, d12 :: Qd 0xc2610000 0xc2610000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmax.f32 d0, d11, d12 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmax.f32 d7, d1, d6 :: Qd 0x43e41fde 0x43e41fde Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmax.f32 d7, d1, d6 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmax.f32 d0, d5, d2 :: Qd 0x44053f2b 0x44053f2b Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmax.f32 d0, d5, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmax.f32 d10, d13, d15 :: Qd 0xc3f29f73 0xc3f29f73 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmax.f32 d10, d13, d15 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmax.f32 d10, d13, d15 :: Qd 0x4887f70e 0x4887f70e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmax.f32 d10, d13, d15 :: Qd 0x4608d008 0x4608d008 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmax.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e920233 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmax.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e920233 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x3a800000 0x3a800000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x3a800000 Qn (i32)0xba800000 +vmax.f32 d0, d1, d2 :: Qd 0x3a800000 0x3a800000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vmax.f32 d0, d1, d2 :: Qd 0x3a800000 0x3a800000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vmax.f32 d0, d1, d2 :: Qd 0x45126004 0x45126004 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vmax.f32 d0, d1, d2 :: Qd 0x45125ffc 0x45125ffc Qm (i32)0x45126004 Qn (i32)0x45125ffc +vmax.f32 d0, d1, d2 :: Qd 0xc5125ffc 0xc5125ffc Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vmax.f32 d0, d1, d2 :: Qd 0x47bff200 0x47bff200 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vmax.f32 d0, d1, d2 :: Qd 0x47bff200 0x47bff200 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0xff800000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x00000000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmax.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmax.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VMIN (fp) ---- +vmin.f32 d0, d5, d2 :: Qd 0xc2364659 0xc2364659 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmin.f32 d0, d5, d2 :: Qd 0xc2364659 0xc2364659 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vmin.f32 d3, d4, d5 :: Qd 0xc8a9da0f 0xc8a9da0f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmin.f32 d3, d4, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vmin.f32 d10, d11, d2 :: Qd 0xc732da7a 0xc732da7a Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmin.f32 d10, d11, d2 :: Qd 0xc732da7a 0xc732da7a Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vmin.f32 d9, d5, d7 :: Qd 0x46855200 0x46855200 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmin.f32 d9, d5, d7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vmin.f32 d0, d5, d2 :: Qd 0xc872bcb1 0xc872bcb1 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmin.f32 d0, d5, d2 :: Qd 0xc872bcb1 0xc872bcb1 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vmin.f32 d3, d4, d5 :: Qd 0x41c70126 0x41c70126 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vmin.f32 d3, d4, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vmin.f32 d10, d11, d2 :: Qd 0x44882666 0x44882666 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vmin.f32 d10, d11, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vmin.f32 d9, d5, d7 :: Qd 0x43560000 0x43560000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmin.f32 d9, d5, d7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vmin.f32 d0, d11, d12 :: Qd 0x45b75812 0x45b75812 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmin.f32 d0, d11, d12 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vmin.f32 d7, d1, d6 :: Qd 0x3b210e02 0x3b210e02 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmin.f32 d7, d1, d6 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vmin.f32 d0, d1, d2 :: Qd 0x42d60000 0x42d60000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vmin.f32 d3, d4, d5 :: Qd 0x445a8000 0x445a8000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmin.f32 d3, d4, d5 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vmin.f32 d10, d11, d2 :: Qd 0x42da0000 0x42da0000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmin.f32 d10, d11, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vmin.f32 d9, d5, d7 :: Qd 0x44db0000 0x44db0000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmin.f32 d9, d5, d7 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x45062000 Qn (i32)0x44db0000 +vmin.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0xc5b4d3c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmin.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0xc5b4d3c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vmin.f32 d7, d1, d6 :: Qd 0xc0e96d19 0xc0e96d19 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmin.f32 d7, d1, d6 :: Qd 0xc0e96d19 0xc0e96d19 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vmin.f32 d0, d5, d2 :: Qd 0xbb965394 0xbb965394 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmin.f32 d0, d5, d2 :: Qd 0xbb965394 0xbb965394 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vmin.f32 d10, d13, d15 :: Qd 0xc40dcfae 0xc40dcfae Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmin.f32 d10, d13, d15 :: Qd 0xc40dcfae 0xc40dcfae Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vmin.f32 d10, d13, d15 :: Qd 0x4608d008 0x4608d008 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmin.f32 d10, d13, d15 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vmin.f32 d0, d1, d2 :: Qd 0x4e511724 0x4e511724 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0xba800000 0xba800000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vmin.f32 d0, d1, d2 :: Qd 0xba800000 0xba800000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vmin.f32 d0, d1, d2 :: Qd 0xba800000 0xba800000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xba800000 Qn (i32)0x3a800000 +vmin.f32 d0, d1, d2 :: Qd 0x45125ffc 0x45125ffc Qm (i32)0x45126004 Qn (i32)0x45125ffc +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x45126004 Qn (i32)0x45125ffc +vmin.f32 d0, d1, d2 :: Qd 0xc5126004 0xc5126004 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vmin.f32 d0, d1, d2 :: Qd 0xc5126004 0xc5126004 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vmin.f32 d0, d1, d2 :: Qd 0x47ae5e00 0x47ae5e00 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x3f800000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x7f800000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x3f800000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmin.f32 d0, d1, d2 :: Qd 0x131b1a1b 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x7f800000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VPMAX (fp) ---- +vpmax.f32 d0, d5, d2 :: Qd 0xc2364659 0x41b851ec Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vpmax.f32 d0, d5, d2 :: Qd 0xc2364659 0x131b1a1b Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vpmax.f32 d3, d4, d5 :: Qd 0x44a84000 0xc8a9da0f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vpmax.f32 d3, d4, d5 :: Qd 0x44a84000 0x131b1a1b Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vpmax.f32 d10, d11, d2 :: Qd 0xc732da7a 0x473e7300 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vpmax.f32 d10, d11, d2 :: Qd 0xc732da7a 0x131b1a1b Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vpmax.f32 d9, d5, d7 :: Qd 0x46855200 0x47bb3de1 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vpmax.f32 d9, d5, d7 :: Qd 0x46855200 0x131b1a1b Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vpmax.f32 d0, d5, d2 :: Qd 0xc872bcb1 0xc732633d Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vpmax.f32 d0, d5, d2 :: Qd 0xc872bcb1 0x131b1a1b Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vpmax.f32 d3, d4, d5 :: Qd 0x44a84003 0x41c70126 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vpmax.f32 d3, d4, d5 :: Qd 0x44a84003 0x131b1a1b Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vpmax.f32 d10, d11, d2 :: Qd 0x44882666 0x473e73b3 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vpmax.f32 d10, d11, d2 :: Qd 0x44882666 0x131b1a1b Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vpmax.f32 d9, d5, d7 :: Qd 0x49d5e008 0x43560000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vpmax.f32 d9, d5, d7 :: Qd 0x49d5e008 0x131b1a1b Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vpmax.f32 d0, d11, d12 :: Qd 0x45b75812 0x48add9f2 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vpmax.f32 d0, d11, d12 :: Qd 0x45b75812 0x131b1a1b Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vpmax.f32 d7, d1, d6 :: Qd 0x3b210e02 0x42080079 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vpmax.f32 d7, d1, d6 :: Qd 0x3b210e02 0x131b1a1b Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vpmax.f32 d0, d1, d2 :: Qd 0x42d60000 0x452c2000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vpmax.f32 d0, d1, d2 :: Qd 0x42d60000 0x131b1a1b Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vpmax.f32 d3, d4, d5 :: Qd 0x44ad1333 0x445a8000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vpmax.f32 d3, d4, d5 :: Qd 0x44ad1333 0x131b1a1b Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vpmax.f32 d10, d11, d2 :: Qd 0x42da0000 0x43f3cb23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vpmax.f32 d10, d11, d2 :: Qd 0x42da0000 0x131b1a1b Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vpmax.f32 d9, d5, d7 :: Qd 0x44db0000 0x45062000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vpmax.f32 d9, d5, d7 :: Qd 0x44db0000 0x131b1a1b Qm (i32)0x45062000 Qn (i32)0x44db0000 +vpmax.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0xc2610000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vpmax.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0x131b1a1b Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vpmax.f32 d7, d1, d6 :: Qd 0xc0e96d19 0x43e41fde Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vpmax.f32 d7, d1, d6 :: Qd 0xc0e96d19 0x131b1a1b Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vpmax.f32 d0, d5, d2 :: Qd 0xbb965394 0x44053f2b Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vpmax.f32 d0, d5, d2 :: Qd 0xbb965394 0x131b1a1b Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vpmax.f32 d10, d13, d15 :: Qd 0xc40dcfae 0xc3f29f73 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vpmax.f32 d10, d13, d15 :: Qd 0xc40dcfae 0x131b1a1b Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vpmax.f32 d10, d13, d15 :: Qd 0x4608d008 0x4887f70e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vpmax.f32 d10, d13, d15 :: Qd 0x4608d008 0x131b1a1b Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vpmax.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e511724 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vpmax.f32 d0, d1, d2 :: Qd 0x4e920233 0x131b1a1b Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x131b1a1b Qm (i32)0x00000000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0xba800000 0x3a800000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vpmax.f32 d0, d1, d2 :: Qd 0xba800000 0x131b1a1b Qm (i32)0x3a800000 Qn (i32)0xba800000 +vpmax.f32 d0, d1, d2 :: Qd 0x3a800000 0xba800000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vpmax.f32 d0, d1, d2 :: Qd 0x3a800000 0x131b1a1b Qm (i32)0xba800000 Qn (i32)0x3a800000 +vpmax.f32 d0, d1, d2 :: Qd 0x45125ffc 0x45126004 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vpmax.f32 d0, d1, d2 :: Qd 0x45125ffc 0x131b1a1b Qm (i32)0x45126004 Qn (i32)0x45125ffc +vpmax.f32 d0, d1, d2 :: Qd 0xc5126004 0xc5125ffc Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vpmax.f32 d0, d1, d2 :: Qd 0xc5126004 0x131b1a1b Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vpmax.f32 d0, d1, d2 :: Qd 0x47bff200 0x47ae5e00 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vpmax.f32 d0, d1, d2 :: Qd 0x47bff200 0x131b1a1b Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x131b1a1b Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x131b1a1b Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x131b1a1b Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x131b1a1b Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x131b1a1b Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x131b1a1b Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x131b1a1b Qm (i32)0x00000000 Qn (i32)0x3f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x131b1a1b Qm (i32)0x00000000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x131b1a1b Qm (i32)0x00000000 Qn (i32)0x7f800000 +vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x131b1a1b Qm (i32)0x00000000 Qn (i32)0xff800000 +vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x131b1a1b Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x131b1a1b Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x131b1a1b Qm (i32)0x7f800000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x131b1a1b Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x131b1a1b Qm (i32)0x7f800000 Qn (i32)0xff800000 +vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x131b1a1b Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x131b1a1b Qm (i32)0xff800000 Qn (i32)0x3f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x131b1a1b Qm (i32)0xff800000 Qn (i32)0x00000000 +vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x131b1a1b Qm (i32)0xff800000 Qn (i32)0x7f800000 +vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x131b1a1b Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VPMIN (fp) ---- +vpmin.f32 d0, d5, d2 :: Qd 0xc2364659 0x41b851ec Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vpmin.f32 d0, d5, d2 :: Qd 0xc2364659 0x121f1e1f Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vpmin.f32 d3, d4, d5 :: Qd 0x44a84000 0xc8a9da0f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vpmin.f32 d3, d4, d5 :: Qd 0x44a84000 0x121f1e1f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vpmin.f32 d10, d11, d2 :: Qd 0xc732da7a 0x473e7300 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vpmin.f32 d10, d11, d2 :: Qd 0xc732da7a 0x121f1e1f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vpmin.f32 d9, d5, d7 :: Qd 0x46855200 0x47bb3de1 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vpmin.f32 d9, d5, d7 :: Qd 0x46855200 0x121f1e1f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vpmin.f32 d0, d5, d2 :: Qd 0xc872bcb1 0xc732633d Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vpmin.f32 d0, d5, d2 :: Qd 0xc872bcb1 0x121f1e1f Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vpmin.f32 d3, d4, d5 :: Qd 0x44a84003 0x41c70126 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vpmin.f32 d3, d4, d5 :: Qd 0x44a84003 0x121f1e1f Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vpmin.f32 d10, d11, d2 :: Qd 0x44882666 0x473e73b3 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vpmin.f32 d10, d11, d2 :: Qd 0x44882666 0x121f1e1f Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vpmin.f32 d9, d5, d7 :: Qd 0x49d5e008 0x43560000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vpmin.f32 d9, d5, d7 :: Qd 0x49d5e008 0x121f1e1f Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vpmin.f32 d0, d11, d12 :: Qd 0x45b75812 0x48add9f2 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vpmin.f32 d0, d11, d12 :: Qd 0x45b75812 0x121f1e1f Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vpmin.f32 d7, d1, d6 :: Qd 0x3b210e02 0x42080079 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vpmin.f32 d7, d1, d6 :: Qd 0x3b210e02 0x121f1e1f Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vpmin.f32 d0, d1, d2 :: Qd 0x42d60000 0x452c2000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vpmin.f32 d0, d1, d2 :: Qd 0x42d60000 0x121f1e1f Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vpmin.f32 d3, d4, d5 :: Qd 0x44ad1333 0x445a8000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vpmin.f32 d3, d4, d5 :: Qd 0x44ad1333 0x121f1e1f Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vpmin.f32 d10, d11, d2 :: Qd 0x42da0000 0x43f3cb23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vpmin.f32 d10, d11, d2 :: Qd 0x42da0000 0x121f1e1f Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vpmin.f32 d9, d5, d7 :: Qd 0x44db0000 0x45062000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vpmin.f32 d9, d5, d7 :: Qd 0x44db0000 0x121f1e1f Qm (i32)0x45062000 Qn (i32)0x44db0000 +vpmin.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0xc2610000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vpmin.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0x121f1e1f Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vpmin.f32 d7, d1, d6 :: Qd 0xc0e96d19 0x43e41fde Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vpmin.f32 d7, d1, d6 :: Qd 0xc0e96d19 0x121f1e1f Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vpmin.f32 d0, d5, d2 :: Qd 0xbb965394 0x44053f2b Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vpmin.f32 d0, d5, d2 :: Qd 0xbb965394 0x121f1e1f Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vpmin.f32 d10, d13, d15 :: Qd 0xc40dcfae 0xc3f29f73 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vpmin.f32 d10, d13, d15 :: Qd 0xc40dcfae 0x121f1e1f Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vpmin.f32 d10, d13, d15 :: Qd 0x4608d008 0x4887f70e Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vpmin.f32 d10, d13, d15 :: Qd 0x4608d008 0x121f1e1f Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vpmin.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e511724 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vpmin.f32 d0, d1, d2 :: Qd 0x4e920233 0x121f1e1f Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0xba800000 0x3a800000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vpmin.f32 d0, d1, d2 :: Qd 0xba800000 0x121f1e1f Qm (i32)0x3a800000 Qn (i32)0xba800000 +vpmin.f32 d0, d1, d2 :: Qd 0x3a800000 0xba800000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vpmin.f32 d0, d1, d2 :: Qd 0x3a800000 0x121f1e1f Qm (i32)0xba800000 Qn (i32)0x3a800000 +vpmin.f32 d0, d1, d2 :: Qd 0x45125ffc 0x45126004 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vpmin.f32 d0, d1, d2 :: Qd 0x45125ffc 0x121f1e1f Qm (i32)0x45126004 Qn (i32)0x45125ffc +vpmin.f32 d0, d1, d2 :: Qd 0xc5126004 0xc5125ffc Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vpmin.f32 d0, d1, d2 :: Qd 0xc5126004 0x121f1e1f Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vpmin.f32 d0, d1, d2 :: Qd 0x47bff200 0x47ae5e00 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vpmin.f32 d0, d1, d2 :: Qd 0x47bff200 0x121f1e1f Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x121f1e1f Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x3f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0x7f800000 +vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x121f1e1f Qm (i32)0x00000000 Qn (i32)0xff800000 +vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x121f1e1f Qm (i32)0x7f800000 Qn (i32)0xff800000 +vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x3f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x00000000 +vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0x7f800000 +vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x121f1e1f Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VRECPE ---- +vrecpe.u32 d0, d1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x404ccccd +vrecpe.u32 d0, d1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x404ccccd +vrecpe.u32 d0, d1 :: Qd 0xa7000000 0xa7000000 Qm (i32)0xc4234ccd +vrecpe.u32 d0, d1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc4234ccd +vrecpe.u32 d10, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vrecpe.u32 d10, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vrecpe.u32 d15, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vrecpe.u32 d15, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vrecpe.u32 d15, d4 :: Qd 0xab800000 0xab800000 Qm (i32)0xbf000000 +vrecpe.u32 d15, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0xbf000000 +vrecpe.u32 d15, d4 :: Qd 0xaa000000 0xaa000000 Qm (i32)0xc0e33333 +vrecpe.u32 d15, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc0e33333 +vrecpe.u32 d12, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x40fff800 +vrecpe.u32 d12, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x40fff800 +vrecpe.u32 d12, d8 :: Qd 0xaa000000 0xaa000000 Qm (i32)0xc0fff800 +vrecpe.u32 d12, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc0fff800 +vrecpe.u32 d0, d1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x404ccccd +vrecpe.u32 d0, d1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x404ccccd +vrecpe.u32 d10, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vrecpe.u32 d10, d11 :: Qd 0xffffffff 0xffffffff Qm (i32)0x64cb49b4 +vrecpe.u32 d15, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vrecpe.u32 d15, d4 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4f32d05e +vrecpe.f32 d15, d4 :: Qd 0xbfff8000 0xbfff8000 Qm (i32)0xbf000000 +vrecpe.f32 d15, d4 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0xbf000000 +vrecpe.f32 d15, d4 :: Qd 0xbe100000 0xbe100000 Qm (i32)0xc0e33333 +vrecpe.f32 d15, d4 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0xc0e33333 +vrecpe.f32 d12, d8 :: Qd 0x3e000000 0x3e000000 Qm (i32)0x40fff800 +vrecpe.f32 d12, d8 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x40fff800 +vrecpe.f32 d12, d8 :: Qd 0xbe000000 0xbe000000 Qm (i32)0xc0fff800 +vrecpe.f32 d12, d8 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0xc0fff800 +vrecpe.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000007 +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x00000007 +vrecpe.f32 d10, d11 :: Qd 0xff800000 0xff800000 Qm (i32)0x80000000 +vrecpe.f32 d10, d11 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x80000000 +vrecpe.f32 d0, d1 :: Qd 0xff800000 0xff800000 Qm (i32)0x80000001 +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x80000001 +vrecpe.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x7fffffff +vrecpe.f32 d0, d14 :: Qd 0x4e4c0000 0x4e4c0000 Qm (i32)0x30a0bcef +vrecpe.f32 d0, d14 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x30a0bcef +vrecpe.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000007 +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x00000007 +vrecpe.f32 d10, d11 :: Qd 0xff800000 0xff800000 Qm (i32)0x80000000 +vrecpe.f32 d10, d11 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x80000000 +vrecpe.f32 d0, d1 :: Qd 0xff800000 0xff800000 Qm (i32)0x80000001 +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x80000001 +vrecpe.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x7fffffff +vrecpe.f32 d0, d14 :: Qd 0x4e4c0000 0x4e4c0000 Qm (i32)0x30a0bcef +vrecpe.f32 d0, d14 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x30a0bcef +vrecpe.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x7fc00000 +vrecpe.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x00000000 +vrecpe.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0x7f800000 +vrecpe.f32 d0, d1 :: Qd 0x80000000 0x80000000 Qm (i32)0xff800000 +vrecpe.f32 d0, d1 :: Qd 0x69d08000 0x6ad18000 Qm (i32)0xff800000 +---- VRECPS ---- +vrecps.f32 d0, d5, d2 :: Qd 0x44837ce4 0x44837ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vrecps.f32 d0, d5, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vrecps.f32 d3, d4, d5 :: Qd 0x4ddf4321 0x4ddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vrecps.f32 d3, d4, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vrecps.f32 d10, d11, d2 :: Qd 0x4f050e7f 0x4f050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vrecps.f32 d10, d11, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vrecps.f32 d9, d5, d7 :: Qd 0xcec3063f 0xcec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vrecps.f32 d9, d5, d7 :: Qd 0x40000000 0x40000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vrecps.f32 d0, d5, d2 :: Qd 0xd029254c 0xd029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vrecps.f32 d0, d5, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vrecps.f32 d3, d4, d5 :: Qd 0xc6fc5c00 0xc6fc5c00 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vrecps.f32 d3, d4, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vrecps.f32 d10, d11, d2 :: Qd 0xcc4a89cc 0xcc4a89cc Qm (i32)0x473e7300 Qn (i32)0x44882000 +vrecps.f32 d10, d11, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vrecps.f32 d9, d5, d7 :: Qd 0xcdb2c947 0xcdb2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vrecps.f32 d9, d5, d7 :: Qd 0x40000000 0x40000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vrecps.f32 d0, d11, d12 :: Qd 0xcef90536 0xcef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vrecps.f32 d0, d11, d12 :: Qd 0x40000000 0x40000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vrecps.f32 d7, d1, d6 :: Qd 0x3ff54e08 0x3ff54e08 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vrecps.f32 d7, d1, d6 :: Qd 0x40000000 0x40000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vrecps.f32 d0, d1, d2 :: Qd 0xc88fe280 0xc88fe280 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vrecps.f32 d3, d4, d5 :: Qd 0xc993b8d3 0xc993b8d3 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vrecps.f32 d3, d4, d5 :: Qd 0x40000000 0x40000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vrecps.f32 d10, d11, d2 :: Qd 0xc74f98fc 0xc74f98fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vrecps.f32 d10, d11, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vrecps.f32 d9, d5, d7 :: Qd 0xca657ab8 0xca657ab8 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vrecps.f32 d9, d5, d7 :: Qd 0x40000000 0x40000000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vrecps.f32 d0, d11, d12 :: Qd 0xc89eedde 0xc89eedde Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vrecps.f32 d0, d11, d12 :: Qd 0x40000000 0x40000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vrecps.f32 d7, d1, d6 :: Qd 0x45502239 0x45502239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vrecps.f32 d7, d1, d6 :: Qd 0x40000000 0x40000000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vrecps.f32 d0, d5, d2 :: Qd 0x408e3e84 0x408e3e84 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vrecps.f32 d0, d5, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vrecps.f32 d10, d13, d15 :: Qd 0xc8866666 0xc8866666 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vrecps.f32 d10, d13, d15 :: Qd 0x40000000 0x40000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vrecps.f32 d10, d13, d15 :: Qd 0xcf115379 0xcf115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vrecps.f32 d10, d13, d15 :: Qd 0x40000000 0x40000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vrecps.f32 d0, d1, d2 :: Qd 0xdd6e81fd 0xdd6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VABS (fp) ---- +vabs.f32 d0, d1 :: Qd 0x404ccccd 0x404ccccd Qm (i32)0x404ccccd +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x404ccccd +vabs.f32 d10, d11 :: Qd 0x64cb49b4 0x64cb49b4 Qm (i32)0x64cb49b4 +vabs.f32 d10, d11 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x64cb49b4 +vabs.f32 d15, d4 :: Qd 0x4f32d05e 0x4f32d05e Qm (i32)0x4f32d05e +vabs.f32 d15, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x4f32d05e +vabs.f32 d15, d4 :: Qd 0x3f000000 0x3f000000 Qm (i32)0xbf000000 +vabs.f32 d15, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xbf000000 +vabs.f32 d15, d4 :: Qd 0x40e33333 0x40e33333 Qm (i32)0xc0e33333 +vabs.f32 d15, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xc0e33333 +vabs.f32 d12, d8 :: Qd 0x40fff800 0x40fff800 Qm (i32)0x40fff800 +vabs.f32 d12, d8 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x40fff800 +vabs.f32 d12, d8 :: Qd 0x40fff800 0x40fff800 Qm (i32)0xc0fff800 +vabs.f32 d12, d8 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xc0fff800 +vabs.f32 d0, d1 :: Qd 0x404ccccd 0x404ccccd Qm (i32)0x404ccccd +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x404ccccd +vabs.f32 d10, d11 :: Qd 0x64cb49b4 0x64cb49b4 Qm (i32)0x64cb49b4 +vabs.f32 d10, d11 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x64cb49b4 +vabs.f32 d15, d4 :: Qd 0x4f32d05e 0x4f32d05e Qm (i32)0x4f32d05e +vabs.f32 d15, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x4f32d05e +vabs.f32 d15, d4 :: Qd 0x3f000000 0x3f000000 Qm (i32)0xbf000000 +vabs.f32 d15, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xbf000000 +vabs.f32 d15, d4 :: Qd 0x40e33333 0x40e33333 Qm (i32)0xc0e33333 +vabs.f32 d15, d4 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xc0e33333 +vabs.f32 d12, d8 :: Qd 0x40fff800 0x40fff800 Qm (i32)0x40fff800 +vabs.f32 d12, d8 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x40fff800 +vabs.f32 d12, d8 :: Qd 0x40fff800 0x40fff800 Qm (i32)0xc0fff800 +vabs.f32 d12, d8 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xc0fff800 +vabs.f32 d0, d1 :: Qd 0x00000007 0x00000007 Qm (i32)0x00000007 +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000007 +vabs.f32 d10, d11 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 +vabs.f32 d10, d11 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x80000000 +vabs.f32 d0, d1 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000001 +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x80000001 +vabs.f32 d0, d1 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x7fffffff +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x7fffffff +vabs.f32 d0, d14 :: Qd 0x30a0bcef 0x30a0bcef Qm (i32)0x30a0bcef +vabs.f32 d0, d14 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x30a0bcef +vabs.f32 d0, d1 :: Qd 0x00000007 0x00000007 Qm (i32)0x00000007 +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000007 +vabs.f32 d10, d11 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 +vabs.f32 d10, d11 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x80000000 +vabs.f32 d0, d1 :: Qd 0x00000001 0x00000001 Qm (i32)0x80000001 +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x80000001 +vabs.f32 d0, d1 :: Qd 0x7fffffff 0x7fffffff Qm (i32)0x7fffffff +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x7fffffff +vabs.f32 d0, d14 :: Qd 0x30a0bcef 0x30a0bcef Qm (i32)0x30a0bcef +vabs.f32 d0, d14 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x30a0bcef +vabs.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x7fc00000 +vabs.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x00000000 +vabs.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0x7f800000 +vabs.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 +vabs.f32 d0, d1 :: Qd 0x151d191d 0x141c1f1c Qm (i32)0xff800000 +---- VCGT (fp) ---- +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vcgt.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vcgt.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vcgt.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vcgt.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vcgt.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vcgt.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vcgt.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vcgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vcgt.f32 d10, d31, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vcgt.f32 d10, d31, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vcgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vcgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vcgt.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vcgt.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vcgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vcgt.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vcgt.f32 d20, d21, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vcgt.f32 d20, d21, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vcgt.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000 +vcgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vcgt.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vcgt.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vcgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vcgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vcgt.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vcgt.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vcgt.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vcgt.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0xff800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0xff800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VCGE (fp) ---- +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vcge.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vcge.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vcge.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vcge.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vcge.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vcge.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vcge.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vcge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vcge.f32 d10, d31, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vcge.f32 d10, d31, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vcge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vcge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vcge.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vcge.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vcge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vcge.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vcge.f32 d20, d21, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vcge.f32 d20, d21, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vcge.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000 +vcge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vcge.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vcge.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vcge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vcge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vcge.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vcge.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vcge.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vcge.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0xff800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0xff800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000 +vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VACGT (fp) ---- +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vacgt.f32 d2, d15, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vacgt.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vacgt.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vacgt.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vacgt.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vacgt.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vacgt.f32 d3, d4, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vacgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vacgt.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vacgt.f32 d10, d11, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vacgt.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vacgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vacgt.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vacgt.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vacgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vacgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vacgt.f32 d10, d31, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vacgt.f32 d10, d31, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vacgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vacgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vacgt.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vacgt.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vacgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vacgt.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vacgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vacgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vacgt.f32 d20, d21, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vacgt.f32 d20, d21, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vacgt.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000 +vacgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vacgt.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vacgt.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vacgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vacgt.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vacgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vacgt.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vacgt.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vacgt.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vacgt.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vacgt.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x3f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VACGE (fp) ---- +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vacge.f32 d2, d15, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vacge.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vacge.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vacge.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333 +vacge.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vacge.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vacge.f32 d3, d4, d5 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vacge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vacge.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vacge.f32 d10, d11, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vacge.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vacge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vacge.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vacge.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vacge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vacge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vacge.f32 d10, d31, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vacge.f32 d10, d31, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vacge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vacge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vacge.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vacge.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vacge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vacge.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vacge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vacge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vacge.f32 d20, d21, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vacge.f32 d20, d21, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vacge.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000 +vacge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vacge.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vacge.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vacge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vacge.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vacge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vacge.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vacge.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vacge.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vacge.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vacge.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xba800000 Qn (i32)0x3a800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x3f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x7f800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000 +vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VCEQ (fp) ---- +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000 +vceq.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vceq.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8 +vceq.f32 d15, d7, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0x43677333 Qn (i32)0x43677333 +vceq.f32 d15, d7, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0x43677333 Qn (i32)0x43677333 +vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vceq.f32 d10, d11, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vceq.f32 d10, d11, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x41c70126 Qn (i32)0x44a84003 +vceq.f32 d10, d31, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vceq.f32 d10, d31, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x473e73b3 Qn (i32)0x44882666 +vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vceq.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vceq.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vceq.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vceq.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vceq.f32 d20, d21, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vceq.f32 d20, d21, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vceq.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vceq.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vceq.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vceq.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vceq.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vceq.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vceq.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vceq.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vceq.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x45126004 Qn (i32)0x45125ffc +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47bff200 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vceq.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vceq.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000 +vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VCEQ (fp) #0 ---- +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x01000000 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x01000000 +vceq.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000001 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 +vceq.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000000 +vceq.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 +vceq.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec +vceq.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec +vceq.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vceq.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vceq.f32 d30, d15, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.f32 d30, d15, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vceq.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VCGT (fp) #0 ---- +vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x01000000 +vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x01000000 +vcgt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 +vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000001 +vcgt.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 +vcgt.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000000 +vcgt.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x41b851ec +vcgt.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x41b851ec +vcgt.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vcgt.f32 d2, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc1b851ec +vcgt.f32 d30, d15, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.f32 d30, d15, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fc00000 +vcgt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7f800000 +vcgt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 +---- VCLT (fp) #0 ---- +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x01000000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x01000000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 +vclt.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 +vclt.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 +vclt.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec +vclt.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec +vclt.f32 d2, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc1b851ec +vclt.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vclt.f32 d30, d15, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.f32 d30, d15, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vclt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 +vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VCGE (fp) #0 ---- +vcge.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x01000000 +vcge.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x01000000 +vcge.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000001 +vcge.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000001 +vcge.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000000 +vcge.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000000 +vcge.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x41b851ec +vcge.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x41b851ec +vcge.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vcge.f32 d2, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc1b851ec +vcge.f32 d30, d15, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcge.f32 d30, d15, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VCLE (fp) #0 ---- +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x01000000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x01000000 +vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000001 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000001 +vcle.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x80000000 +vcle.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 +vcle.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec +vcle.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x41b851ec +vcle.f32 d2, d31, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xc1b851ec +vcle.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xc1b851ec +vcle.f32 d30, d15, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.f32 d30, d15, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7fc00000 +vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0xff800000 +vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xff800000 +---- VNEG (fp) ---- +vneg.f32 d0, d1 :: Qd 0x81000000 0x81000000 Qm (i32)0x01000000 +vneg.f32 d0, d1 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0x01000000 +vneg.f32 d0, d1 :: Qd 0x80000001 0x80000001 Qm (i32)0x00000001 +vneg.f32 d0, d1 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0x00000001 +vneg.f32 d2, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x80000000 +vneg.f32 d2, d1 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0x80000000 +vneg.f32 d2, d1 :: Qd 0xc1b851ec 0xc1b851ec Qm (i32)0x41b851ec +vneg.f32 d2, d1 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0x41b851ec +vneg.f32 d2, d31 :: Qd 0x41b851ec 0x41b851ec Qm (i32)0xc1b851ec +vneg.f32 d2, d31 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0xc1b851ec +vneg.f32 d30, d15 :: Qd 0x80000000 0x80000000 Qm (i32)0x00000000 +vneg.f32 d30, d15 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0x00000000 +vneg.f32 d0, d1 :: Qd 0xffc00000 0xffc00000 Qm (i32)0x7fc00000 +vneg.f32 d0, d1 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0x7fc00000 +vneg.f32 d0, d1 :: Qd 0x80000000 0x80000000 Qm (i32)0x00000000 +vneg.f32 d0, d1 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0x00000000 +vneg.f32 d0, d1 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 +vneg.f32 d0, d1 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0x7f800000 +vneg.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 +vneg.f32 d0, d1 :: Qd 0x951d191d 0x941c1f1c Qm (i32)0xff800000 +---- VRSQRTS ---- +vrsqrts.f32 d0, d5, d2 :: Qd 0x44039ce4 0x44039ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vrsqrts.f32 d0, d5, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x41b851ec Qn (i32)0xc2364659 +vrsqrts.f32 d3, d4, d5 :: Qd 0x4d5f4321 0x4d5f4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vrsqrts.f32 d3, d4, d5 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000 +vrsqrts.f32 d10, d11, d2 :: Qd 0x4e850e7f 0x4e850e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vrsqrts.f32 d10, d11, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a +vrsqrts.f32 d9, d5, d7 :: Qd 0xce43063f 0xce43063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vrsqrts.f32 d9, d5, d7 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200 +vrsqrts.f32 d0, d5, d2 :: Qd 0xcfa9254c 0xcfa9254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vrsqrts.f32 d0, d5, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1 +vrsqrts.f32 d3, d4, d5 :: Qd 0xc67c5a00 0xc67c5a00 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vrsqrts.f32 d3, d4, d5 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x41c00000 Qn (i32)0x44a84000 +vrsqrts.f32 d10, d11, d2 :: Qd 0xcbca89cc 0xcbca89cc Qm (i32)0x473e7300 Qn (i32)0x44882000 +vrsqrts.f32 d10, d11, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x473e7300 Qn (i32)0x44882000 +vrsqrts.f32 d9, d5, d7 :: Qd 0xcd32c947 0xcd32c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vrsqrts.f32 d9, d5, d7 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x43560000 Qn (i32)0x49d5e008 +vrsqrts.f32 d0, d11, d12 :: Qd 0xce790536 0xce790536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vrsqrts.f32 d0, d11, d12 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812 +vrsqrts.f32 d7, d1, d6 :: Qd 0x3fbaa704 0x3fbaa704 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vrsqrts.f32 d7, d1, d6 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x42080079 Qn (i32)0x3b210e02 +vrsqrts.f32 d0, d1, d2 :: Qd 0xc80fe260 0xc80fe260 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x452c2000 Qn (i32)0x42d60000 +vrsqrts.f32 d3, d4, d5 :: Qd 0xc913b8cb 0xc913b8cb Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vrsqrts.f32 d3, d4, d5 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333 +vrsqrts.f32 d10, d11, d2 :: Qd 0xc6cf97fc 0xc6cf97fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vrsqrts.f32 d10, d11, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000 +vrsqrts.f32 d9, d5, d7 :: Qd 0xc9e57ab4 0xc9e57ab4 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vrsqrts.f32 d9, d5, d7 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x45062000 Qn (i32)0x44db0000 +vrsqrts.f32 d0, d11, d12 :: Qd 0xc81eedbe 0xc81eedbe Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vrsqrts.f32 d0, d11, d12 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3 +vrsqrts.f32 d7, d1, d6 :: Qd 0x44d03239 0x44d03239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vrsqrts.f32 d7, d1, d6 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19 +vrsqrts.f32 d0, d5, d2 :: Qd 0x402e3e84 0x402e3e84 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vrsqrts.f32 d0, d5, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x44053f2b Qn (i32)0xbb965394 +vrsqrts.f32 d10, d13, d15 :: Qd 0xc8066646 0xc8066646 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vrsqrts.f32 d10, d13, d15 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae +vrsqrts.f32 d10, d13, d15 :: Qd 0xce915379 0xce915379 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vrsqrts.f32 d10, d13, d15 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x4887f70e Qn (i32)0x4608d008 +vrsqrts.f32 d0, d1, d2 :: Qd 0xdcee81fd 0xdcee81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x4e511724 Qn (i32)0x4e920233 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x3f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x00000000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000 +vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x7f800000 Qn (i32)0x3f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000 +vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0xff800000 Qn (i32)0x3f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000 +---- VRSQRTE (fp) ---- +vrsqrte.f32 d0, d1 :: Qd 0x3f0f0000 0x3f0f0000 Qm (i32)0x404ccccd +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x404ccccd +vrsqrte.f32 d10, d11 :: Qd 0x2ccb0000 0x2ccb0000 Qm (i32)0x64cb49b4 +vrsqrte.f32 d10, d11 :: Qd 0x54a30000 0x55238000 Qm (i32)0x64cb49b4 +vrsqrte.f32 d15, d4 :: Qd 0x37998000 0x37998000 Qm (i32)0x4f32d05e +vrsqrte.f32 d15, d4 :: Qd 0x54a30000 0x55238000 Qm (i32)0x4f32d05e +vrsqrte.f32 d15, d4 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xbf000000 +vrsqrte.f32 d15, d4 :: Qd 0x54a30000 0x55238000 Qm (i32)0xbf000000 +vrsqrte.f32 d15, d4 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xc0e33333 +vrsqrte.f32 d15, d4 :: Qd 0x54a30000 0x55238000 Qm (i32)0xc0e33333 +vrsqrte.f32 d12, d8 :: Qd 0x3eb50000 0x3eb50000 Qm (i32)0x40fff800 +vrsqrte.f32 d12, d8 :: Qd 0x54a30000 0x55238000 Qm (i32)0x40fff800 +vrsqrte.f32 d12, d8 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xc0fff800 +vrsqrte.f32 d12, d8 :: Qd 0x54a30000 0x55238000 Qm (i32)0xc0fff800 +vrsqrte.f32 d0, d1 :: Qd 0x3f0f0000 0x3f0f0000 Qm (i32)0x404ccccd +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x404ccccd +vrsqrte.f32 d10, d11 :: Qd 0x2ccb0000 0x2ccb0000 Qm (i32)0x64cb49b4 +vrsqrte.f32 d10, d11 :: Qd 0x54a30000 0x55238000 Qm (i32)0x64cb49b4 +vrsqrte.f32 d15, d4 :: Qd 0x37998000 0x37998000 Qm (i32)0x4f32d05e +vrsqrte.f32 d15, d4 :: Qd 0x54a30000 0x55238000 Qm (i32)0x4f32d05e +vrsqrte.f32 d15, d4 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xbf000000 +vrsqrte.f32 d15, d4 :: Qd 0x54a30000 0x55238000 Qm (i32)0xbf000000 +vrsqrte.f32 d15, d4 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xc0e33333 +vrsqrte.f32 d15, d4 :: Qd 0x54a30000 0x55238000 Qm (i32)0xc0e33333 +vrsqrte.f32 d12, d8 :: Qd 0x3eb50000 0x3eb50000 Qm (i32)0x40fff800 +vrsqrte.f32 d12, d8 :: Qd 0x54a30000 0x55238000 Qm (i32)0x40fff800 +vrsqrte.f32 d12, d8 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xc0fff800 +vrsqrte.f32 d12, d8 :: Qd 0x54a30000 0x55238000 Qm (i32)0xc0fff800 +vrsqrte.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000007 +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x00000007 +vrsqrte.f32 d10, d11 :: Qd 0xff800000 0xff800000 Qm (i32)0x80000000 +vrsqrte.f32 d10, d11 :: Qd 0x54a30000 0x55238000 Qm (i32)0x80000000 +vrsqrte.f32 d0, d1 :: Qd 0xff800000 0xff800000 Qm (i32)0x80000001 +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x80000001 +vrsqrte.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x7fffffff +vrsqrte.f32 d0, d14 :: Qd 0x46e48000 0x46e48000 Qm (i32)0x30a0bcef +vrsqrte.f32 d0, d14 :: Qd 0x54a30000 0x55238000 Qm (i32)0x30a0bcef +vrsqrte.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000007 +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x00000007 +vrsqrte.f32 d10, d11 :: Qd 0xff800000 0xff800000 Qm (i32)0x80000000 +vrsqrte.f32 d10, d11 :: Qd 0x54a30000 0x55238000 Qm (i32)0x80000000 +vrsqrte.f32 d0, d1 :: Qd 0xff800000 0xff800000 Qm (i32)0x80000001 +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x80000001 +vrsqrte.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x7fffffff +vrsqrte.f32 d0, d14 :: Qd 0x46e48000 0x46e48000 Qm (i32)0x30a0bcef +vrsqrte.f32 d0, d14 :: Qd 0x54a30000 0x55238000 Qm (i32)0x30a0bcef +vrsqrte.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x7fc00000 +vrsqrte.f32 d0, d1 :: Qd 0x7f800000 0x7f800000 Qm (i32)0x00000000 +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x00000000 +vrsqrte.f32 d0, d1 :: Qd 0x00000000 0x00000000 Qm (i32)0x7f800000 +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0x7f800000 +vrsqrte.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 +vrsqrte.f32 d0, d1 :: Qd 0x54a30000 0x55238000 Qm (i32)0xff800000 diff --git a/none/tests/arm/neon64.vgtest b/none/tests/arm/neon64.vgtest new file mode 100644 index 0000000..dffebc4 --- /dev/null +++ b/none/tests/arm/neon64.vgtest @@ -0,0 +1,2 @@ +prog: neon64 +vgopts: -q diff --git a/none/tests/arm/v6intARM.c b/none/tests/arm/v6intARM.c new file mode 100644 index 0000000..761485c --- /dev/null +++ b/none/tests/arm/v6intARM.c @@ -0,0 +1,918 @@ + +/* How to compile: + gcc -O -g -Wall -mcpu=cortex-a8 -o testarmv6int testarmv6int.c +*/ + +#include + +/* test macros to generate and output the result of a single instruction */ +#define TESTINST2(instruction, RMval, RD, RM, carryin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "movs %3,%3;" \ + "msrne cpsr_f,#(1<<29);" \ + "msreq cpsr_f,#0;" \ + "mov " #RM ",%2;" \ + /* set #RD to 0x55555555 so we can see which parts get overwritten */ \ + "mov " #RD ", #0x55" "\n\t" \ + "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \ + "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (carryin) \ + : #RD, #RM, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, RMval, \ + carryin ? 1 : 0, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + +#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "movs %4,%4;" \ + "msrne cpsr_f,#(1<<29);" \ + "msreq cpsr_f,#0;" \ + "mov " #RM ",%2;" \ + "mov " #RN ",%3;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (RNval), "r" (carryin) \ + : #RD, #RM, #RN, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, RMval, RNval, \ + carryin ? 1 : 0, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + +#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "movs %5,%5;" \ + "msrne cpsr_f,#(1<<29);" \ + "msreq cpsr_f,#0;" \ + "mov " #RM ",%2;" \ + "mov " #RN ",%3;" \ + "mov " #RS ",%4;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (RNval), "r" (RSval), "r" (carryin) \ + : #RD, #RM, #RN, #RS, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, RMval, RNval, RSval, \ + carryin ? 1 : 0, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + +#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ +{ \ + unsigned int out; \ + unsigned int out2; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "movs %7,%7;" \ + "msrne cpsr_f,#(1<<29);" \ + "msreq cpsr_f,#0;" \ + "mov " #RD ",%3;" \ + "mov " #RD2 ",%4;" \ + "mov " #RM ",%5;" \ + "mov " #RS ",%6;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mov %1," #RD2 ";" \ + "mrs %2,cpsr;" \ + : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \ + : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (carryin) \ + : #RD, #RD2, #RM, #RS, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, out2, RMval, RSval, \ + carryin ? 1 : 0, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + +/* helpers */ +#define TESTCARRY { int c = 0; for (c = 0; c < 2; c++) { +#define TESTCARRYEND }} + + + + +int main(int argc, char **argv) +{ + + printf("MOV\n"); + TESTINST2("mov r0, r1", 1, r0, r1, 0); + TESTINST2("cpy r0, r1", 1, r0, r1, 0); + TESTINST2("mov r0, #0", 0, r0, r1, 0); + TESTINST2("mov r0, #1", 0, r0, r1, 0); + TESTCARRY + TESTINST2("movs r0, r1", 1, r0, r1, c); + TESTINST2("movs r0, r1", 0, r0, r1, c); + TESTINST2("movs r0, r1", 0x80000000, r0, r1, c); + TESTINST2("movs r0, #0", 0, r0, r1, c); + TESTINST2("movs r0, #1", 0, r0, r1, c); + TESTCARRYEND + + printf("MVN\n"); + TESTINST2("mvn r0, r1", 1, r0, r1, 0); + TESTCARRY + TESTINST2("mvns r0, r1", 1, r0, r1, c); + TESTINST2("mvns r0, r1", 0, r0, r1, c); + TESTINST2("mvns r0, r1", 0x80000000, r0, r1, c); + TESTCARRYEND + + printf("ADD\n"); + TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0); + + printf("ADC\n"); + TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1); + + printf("LSL\n"); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0); + + TESTINST3("lsl r0, r1, r2", 0x1, 0, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0x1, 1, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0x1, 31, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0x2, 31, r0, r1, r2, 0); + + printf("LSLS\n"); + TESTCARRY + TESTINST3("lsls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0x1, 0, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0x1, 1, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0x1, 31, r0, r1, r2, c); + TESTINST3("lsls r0, r1, r2", 0x2, 31, r0, r1, r2, c); + TESTCARRYEND + + printf("LSL immediate\n"); + TESTCARRY + TESTINST2("lsl r0, r1, #0", 0xffffffff, r0, r1, c); + TESTINST2("lsl r0, r1, #1", 0xffffffff, r0, r1, c); + TESTINST2("lsl r0, r1, #31", 0xffffffff, r0, r1, c); + TESTINST2("lsl r0, r1, #0", 0x1, r0, r1, c); + TESTINST2("lsl r0, r1, #1", 0x1, r0, r1, c); + TESTINST2("lsl r0, r1, #31", 0x1, r0, r1, c); + TESTINST2("lsl r0, r1, #31", 0x2, r0, r1, c); + TESTCARRYEND + + printf("LSLS immediate\n"); + TESTCARRY + TESTINST2("lsls r0, r1, #0", 0xffffffff, r0, r1, c); + TESTINST2("lsls r0, r1, #1", 0xffffffff, r0, r1, c); + TESTINST2("lsls r0, r1, #31", 0xffffffff, r0, r1, c); + TESTINST2("lsls r0, r1, #0", 0x1, r0, r1, c); + TESTINST2("lsls r0, r1, #1", 0x1, r0, r1, c); + TESTINST2("lsls r0, r1, #31", 0x1, r0, r1, c); + TESTINST2("lsls r0, r1, #31", 0x2, r0, r1, c); + TESTCARRYEND + + printf("LSR\n"); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0); + + printf("LSRS\n"); + TESTCARRY + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c); + TESTCARRYEND + + printf("LSR immediate\n"); + TESTINST2("lsr r0, r1, #0", 0xffffffff, r0, r1, 0); + TESTINST2("lsr r0, r1, #1", 0xffffffff, r0, r1, 0); + TESTINST2("lsr r0, r1, #31", 0xffffffff, r0, r1, 0); + TESTINST2("lsr r0, r1, #32", 0xffffffff, r0, r1, 0); + TESTINST2("lsr r0, r1, #16", 0x00010000, r0, r1, 0); + TESTINST2("lsr r0, r1, #17", 0x00010000, r0, r1, 0); + TESTINST2("lsr r0, r1, #18", 0x00010000, r0, r1, 0); + + printf("LSRS immediate\n"); + TESTCARRY + TESTINST2("lsrs r0, r1, #0", 0xffffffff, r0, r1, c); + TESTINST2("lsrs r0, r1, #1", 0xffffffff, r0, r1, c); + TESTINST2("lsrs r0, r1, #31", 0xffffffff, r0, r1, c); + TESTINST2("lsrs r0, r1, #32", 0xffffffff, r0, r1, c); + TESTINST2("lsrs r0, r1, #16", 0x00010000, r0, r1, c); + TESTINST2("lsrs r0, r1, #17", 0x00010000, r0, r1, c); + TESTINST2("lsrs r0, r1, #18", 0x00010000, r0, r1, c); + TESTCARRYEND + + printf("ASR\n"); + TESTCARRY + TESTINST3("asr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, c); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, c); + TESTCARRYEND + + printf("ASRS\n"); + TESTCARRY + TESTINST3("asrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, c); + TESTCARRYEND + + TESTCARRY + TESTINST3("asrs r0, r1, r2", 0x8, 0, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x8, 1, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x8, 2, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x8, 3, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x8, 4, r0, r1, r2, c); + TESTINST3("asrs r0, r1, r2", 0x8, 5, r0, r1, r2, c); + TESTCARRYEND + + TESTINST3("asrs r0, r1, r2", 0x80000001, 1, r0, r1, r2, 0); + TESTINST3("asrs r0, r1, r2", 0x80000001, 2, r0, r1, r2, 0); + + printf("ASR immediate\n"); + TESTINST2("asr r0, r1, #0", 0xffffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #1", 0xffffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #31", 0xffffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #32", 0xffffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #0", 0x7fffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #1", 0x7fffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #31", 0x7fffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #32", 0x7fffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #16", 0x00010000, r0, r1, 0); + TESTINST2("asr r0, r1, #17", 0x00010000, r0, r1, 0); + TESTINST2("asr r0, r1, #18", 0x00010000, r0, r1, 0); + + printf("ASRS immediate\n"); + TESTCARRY + TESTINST2("asrs r0, r1, #0", 0xffffffff, r0, r1, c); + TESTINST2("asrs r0, r1, #1", 0xffffffff, r0, r1, c); + TESTINST2("asrs r0, r1, #31", 0xffffffff, r0, r1, c); + TESTINST2("asrs r0, r1, #32", 0xffffffff, r0, r1, c); + TESTINST2("asrs r0, r1, #0", 0x7fffffff, r0, r1, c); + TESTINST2("asrs r0, r1, #1", 0x7fffffff, r0, r1, c); + TESTINST2("asrs r0, r1, #31", 0x7fffffff, r0, r1, c); + TESTINST2("asrs r0, r1, #32", 0x7fffffff, r0, r1, c); + TESTINST2("asrs r0, r1, #16", 0x00010000, r0, r1, c); + TESTINST2("asrs r0, r1, #17", 0x00010000, r0, r1, c); + TESTINST2("asrs r0, r1, #18", 0x00010000, r0, r1, c); + TESTCARRYEND + + printf("ROR\n"); + TESTCARRY + TESTINST3("ror r0, r1, r2", 0x00088000, 0, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x80088000, 1, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 1, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 2, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 31, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 32, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 33, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 63, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 64, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 255, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 256, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x80088000, 256, r0, r1, r2, c); + TESTINST3("ror r0, r1, r2", 0x00088000, 257, r0, r1, r2, c); + TESTCARRYEND + + printf("RORS\n"); + TESTCARRY + TESTINST3("rors r0, r1, r2", 0x00088000, 0, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x80088000, 0, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 1, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 2, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 31, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 32, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 33, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 63, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 64, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 255, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 256, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x80088000, 256, r0, r1, r2, c); + TESTINST3("rors r0, r1, r2", 0x00088000, 257, r0, r1, r2, c); + TESTCARRYEND + + printf("ROR immediate\n"); + TESTCARRY + TESTINST2("ror r0, r1, #0", 0x00088000, r0, r1, c); + TESTINST2("ror r0, r1, #1", 0x00088000, r0, r1, c); + TESTINST2("ror r0, r1, #31", 0x00088000, r0, r1, c); + TESTINST2("ror r0, r1, #16", 0x00010000, r0, r1, c); + TESTINST2("ror r0, r1, #17", 0x00010000, r0, r1, c); + TESTINST2("ror r0, r1, #18", 0x00010000, r0, r1, c); + TESTCARRYEND + + printf("RORS immediate\n"); + TESTCARRY + TESTINST2("rors r0, r1, #0", 0x00088000, r0, r1, c); + TESTINST2("rors r0, r1, #1", 0x00088000, r0, r1, c); + TESTINST2("rors r0, r1, #31", 0x00088000, r0, r1, c); + TESTINST2("rors r0, r1, #16", 0x00010000, r0, r1, c); + TESTINST2("rors r0, r1, #17", 0x00010000, r0, r1, c); + TESTINST2("rors r0, r1, #18", 0x00010000, r0, r1, c); + TESTCARRYEND + + printf("shift with barrel shifter\n"); + TESTCARRY + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 0, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 1, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 31, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 32, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 255, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 256, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c); + TESTCARRYEND + + TESTCARRY + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 0, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 1, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 2, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 3, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 4, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 5, r0, r1, r2, r3, c); + TESTCARRYEND + + TESTCARRY + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, c); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, c); + TESTCARRYEND + + TESTCARRY + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c); + + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, c); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, c); + TESTCARRYEND + + TESTCARRY + TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); + TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); + TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); + TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); + TESTCARRYEND + + printf("MUL\n"); + TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); + + printf("MULS\n"); + TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); + + printf("MLA\n"); + TESTINST4("mla r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); + + printf("MLAS\n"); + TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); + + printf("MLS\n"); + TESTINST4("mls r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); + + printf("UMULL\n"); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); + + printf("SMULL\n"); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); + + printf("UMLAL\n"); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); + + printf("SMLAL\n"); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); + + printf("CLZ\n"); + TESTCARRY + TESTINST2("clz r0, r1", 0, r0, r1, c); + TESTINST2("clz r0, r1", 1, r0, r1, c); + TESTINST2("clz r0, r1", 0x10, r0, r1, c); + TESTINST2("clz r0, r1", 0xffffffff, r0, r1, c); + TESTCARRYEND + + printf("extend instructions\n"); + TESTINST2("uxtb r0, r1", 0, r0, r1, 0); + TESTINST2("uxtb r0, r1", 1, r0, r1, 0); + TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0); + TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0, r0, r1, 0); + TESTINST2("sxtb r0, r1", 1, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0); + + TESTINST2("uxth r0, r1", 0, r0, r1, 0); + TESTINST2("uxth r0, r1", 1, r0, r1, 0); + TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0); + TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0, r0, r1, 0); + TESTINST2("sxth r0, r1", 1, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0); + + TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0); + + TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0); + + printf("------------ BFI ------------\n"); + + /* bfi rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */ + TESTINST2("bfi r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfi r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfi r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("bfi r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfi r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfi r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0); + + printf("------------ BFC ------------\n"); + + /* bfi rDst, #lsb-in-dst, #number-of-bits-to-copy */ + TESTINST2("bfc r0, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfc r0, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfc r0, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("bfc r0, #19, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #20, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #21, #11", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfc r0, #0, #32", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #1, #31", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfc r0, #29, #3", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #30, #2", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #31, #1", 0xFFFFFFFF, r0, r1, 0); + + printf("------------ SBFX ------------\n"); + + /* sbfx rDst, rSrc, #lsb, #width */ + TESTINST2("sbfx r0, r1, #0, #1", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #0, #1", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000002, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000003, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #0, #2", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #0, #2", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000002, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000003, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0); + + printf("------------ UBFX ------------\n"); + + /* ubfx rDst, rSrc, #lsb, #width */ + TESTINST2("ubfx r0, r1, #0, #1", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #0, #1", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000002, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000003, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #0, #2", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #0, #2", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000002, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000003, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0); + + printf("------------ SMULL{B,T}{B,T} ------------\n"); + /* SMULxx rD, rN, rM */ + + TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff, r0, r1, r2, 0); + + printf("------------ SXTAB ------------\n"); + TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, + r0, r1, r2, 0); + + printf("------------ UXTAB ------------\n"); + TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, + r0, r1, r2, 0); + + printf("------------ SXTAH ------------\n"); + TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, + r0, r1, r2, 0); + + printf("------------ UXTAH ------------\n"); + TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, + r0, r1, r2, 0); + + printf("------------ PLD/PLDW (begin) ------------\n"); + /* These don't have any effect on the architected state, so, + uh, there's no result values to check. Just _do_ some of + them and check Valgrind's instruction decoder eats them up + without complaining. */ + { int alocal; + printf("pld reg +/- imm12 cases\n"); + __asm__ __volatile__( "pld [%0, #128]" : :/*in*/"r"(&alocal) ); + __asm__ __volatile__( "pld [%0, #-128]" : :/*in*/"r"(&alocal) ); + __asm__ __volatile__( "pld [r15, #-128]" : :/*in*/"r"(&alocal) ); + + // apparently pldw is v7 only + //__asm__ __volatile__( "pldw [%0, #128]" : :/*in*/"r"(&alocal) ); + //__asm__ __volatile__( "pldw [%0, #-128]" : :/*in*/"r"(&alocal) ); + //__asm__ __volatile__( "pldw [r15, #128]" : :/*in*/"r"(&alocal) ); + + printf("pld reg +/- shifted reg cases\n"); + __asm__ __volatile__( "pld [%0, %1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, LSL #1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, LSR #1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, ASR #1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, ROR #1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, RRX]" : : /*in*/"r"(&alocal), "r"(0) ); + } + printf("------------ PLD/PLDW (done) ------------\n"); + + printf("------------ RBIT ------------\n"); + TESTINST2("rbit r0, r1", 0x00000000, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x80000000, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x00000001, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x31415927, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x14141562, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xabe8391f, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x9028aa80, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xead1fc6d, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x35c98c55, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x534af1eb, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x45511b08, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x90077f71, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xde8ca84b, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xe37a0dda, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xe5b83d4b, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xbb6d14ec, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x68983cc9, r0, r1, 0); + + printf("------------ REV ------------\n"); + TESTINST2("rev r0, r1", 0x00000000, r0, r1, 0); + TESTINST2("rev r0, r1", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("rev r0, r1", 0x80000000, r0, r1, 0); + TESTINST2("rev r0, r1", 0x00000001, r0, r1, 0); + TESTINST2("rev r0, r1", 0x31415927, r0, r1, 0); + TESTINST2("rev r0, r1", 0x14141562, r0, r1, 0); + TESTINST2("rev r0, r1", 0xabe8391f, r0, r1, 0); + TESTINST2("rev r0, r1", 0x9028aa80, r0, r1, 0); + TESTINST2("rev r0, r1", 0xead1fc6d, r0, r1, 0); + TESTINST2("rev r0, r1", 0x35c98c55, r0, r1, 0); + TESTINST2("rev r0, r1", 0x534af1eb, r0, r1, 0); + TESTINST2("rev r0, r1", 0x45511b08, r0, r1, 0); + TESTINST2("rev r0, r1", 0x90077f71, r0, r1, 0); + TESTINST2("rev r0, r1", 0xde8ca84b, r0, r1, 0); + TESTINST2("rev r0, r1", 0xe37a0dda, r0, r1, 0); + TESTINST2("rev r0, r1", 0xe5b83d4b, r0, r1, 0); + TESTINST2("rev r0, r1", 0xbb6d14ec, r0, r1, 0); + TESTINST2("rev r0, r1", 0x68983cc9, r0, r1, 0); + + printf("------------ REV16 ------------\n"); + TESTINST2("rev16 r0, r1", 0x00000000, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x80000000, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x00000001, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x31415927, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x14141562, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xabe8391f, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x9028aa80, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xead1fc6d, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x35c98c55, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x534af1eb, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x45511b08, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x90077f71, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xde8ca84b, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xe37a0dda, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xe5b83d4b, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xbb6d14ec, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x68983cc9, r0, r1, 0); + + printf("------------ NOP (begin) ------------\n"); + printf("nop\n"); + __asm__ __volatile__("nop" ::: "memory","cc"); + printf("nopeq\n"); + __asm__ __volatile__("nopeq" ::: "memory","cc"); + printf("nopne\n"); + __asm__ __volatile__("nopne" ::: "memory","cc"); + printf("------------ NOP (end) ------------\n"); + + return 0; +} diff --git a/none/tests/arm/v6intARM.stderr.exp b/none/tests/arm/v6intARM.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/arm/v6intARM.stdout.exp b/none/tests/arm/v6intARM.stdout.exp new file mode 100644 index 0000000..2dbd1ee --- /dev/null +++ b/none/tests/arm/v6intARM.stdout.exp @@ -0,0 +1,801 @@ +MOV +mov r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +cpy r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +mov r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +mov r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000 +movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z +movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 0, cpsr 0x80000000 N +movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z +movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000 +movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C +movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000 ZC +movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 1, cpsr 0xa0000000 N C +movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000 ZC +movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 1, cpsr 0x20000000 C +MVN +mvn r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x00000000 +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x80000000 N +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 0, cpsr 0x80000000 N +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 0, cpsr 0x00000000 +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 1, cpsr 0xa0000000 N C +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 1, cpsr 0xa0000000 N C +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 1, cpsr 0x20000000 C +ADD +adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z +adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x00000000 +adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000 +adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000 +adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, carryin 0, cpsr 0x60000000 ZC +adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x90000000 N V +adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, carryin 0, cpsr 0x30000000 CV +adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, carryin 0, cpsr 0x80000000 N +ADC +adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z +adcs r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, carryin 1, cpsr 0x00000000 +LSL +lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 0, cpsr 0x00000000 +lsl r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 0, cpsr 0x00000000 +LSLS +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N +lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x60000000 ZC +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x80000000 N +lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000 +lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000 +lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 0, cpsr 0x80000000 N +lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 0, cpsr 0x60000000 ZC +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x60000000 ZC +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 1, cpsr 0x20000000 C +lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 1, cpsr 0x00000000 +lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 1, cpsr 0x80000000 N +lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 1, cpsr 0x60000000 ZC +LSL immediate +lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 0, cpsr 0x00000000 +lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 0, cpsr 0x00000000 +lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 0, cpsr 0x00000000 +lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x00000000 +lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 0, cpsr 0x00000000 +lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0x20000000 C +lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 1, cpsr 0x20000000 C +lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 1, cpsr 0x20000000 C +lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C +lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 1, cpsr 0x20000000 C +lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 1, cpsr 0x20000000 C +lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 1, cpsr 0x20000000 C +LSLS immediate +lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N +lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C +lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C +lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 0, cpsr 0x00000000 +lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x80000000 N +lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 0, cpsr 0x60000000 ZC +lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C +lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C +lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C +lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C +lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 1, cpsr 0x00000000 +lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 1, cpsr 0x80000000 N +lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 1, cpsr 0x60000000 ZC +LSR +lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000 +lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000 +LSRS +lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N +lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x60000000 ZC +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C +lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x60000000 ZC +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000 Z +LSR immediate +lsr r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +lsr r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +lsr r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000 +lsr r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000 +lsr r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000 +lsr r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000 +lsr r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000 +LSRS immediate +lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N +lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 0, cpsr 0x20000000 C +lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x20000000 C +lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x60000000 ZC +lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000 +lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x60000000 ZC +lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x40000000 Z +lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C +lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 1, cpsr 0x20000000 C +lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 1, cpsr 0x20000000 C +lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x60000000 ZC +lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000 +lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x60000000 ZC +lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x40000000 Z +ASR +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 0, cpsr 0x00000000 +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 1, cpsr 0x20000000 C +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 1, cpsr 0x20000000 C +ASRS +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x80000000 N +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 0, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 0, cpsr 0x60000000 ZC +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 1, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 1, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 1, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 1, cpsr 0x60000000 ZC +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 1, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 1, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 1, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 1, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, carryin 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, carryin 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, carryin 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, carryin 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, carryin 0, cpsr 0x60000000 ZC +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, carryin 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, carryin 1, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, carryin 1, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, carryin 1, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, carryin 1, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, carryin 1, cpsr 0x60000000 ZC +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, carryin 1, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0xc0000000 rm 0x80000001, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xe0000000 rm 0x80000001, rn 0x00000002, carryin 0, cpsr 0x80000000 N +ASR immediate +asr r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +asr r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +asr r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +asr r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +asr r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000 +asr r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000 +asr r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x00000000 +asr r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x00000000 +asr r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000 +asr r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000 +asr r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000 +ASRS immediate +asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N +asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C +asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000 +asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 0, cpsr 0x20000000 C +asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x60000000 ZC +asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x40000000 Z +asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000 +asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x60000000 ZC +asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x40000000 Z +asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C +asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 1, cpsr 0x20000000 C +asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 1, cpsr 0x20000000 C +asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 1, cpsr 0x60000000 ZC +asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 1, cpsr 0x40000000 Z +asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000 +asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x60000000 ZC +asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x40000000 Z +ROR +ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x40044000 rm 0x80088000, rn 0x00000001, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 0, cpsr 0x00000000 +ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x40044000 rm 0x80088000, rn 0x00000001, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 1, cpsr 0x20000000 C +ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 1, cpsr 0x20000000 C +RORS +rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 0, cpsr 0x80000000 N +rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 0, cpsr 0x80000000 N +rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 0, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 1, cpsr 0x20000000 C +rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C +rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 1, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 1, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 1, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 1, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 1, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 1, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 1, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 1, cpsr 0x00000000 +rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 1, cpsr 0x20000000 C +rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C +rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 1, cpsr 0x00000000 +ROR immediate +ror r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 0, cpsr 0x00000000 +ror r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 0, cpsr 0x00000000 +ror r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 0, cpsr 0x00000000 +ror r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000 +ror r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 0, cpsr 0x00000000 +ror r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 0, cpsr 0x00000000 +ror r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 1, cpsr 0x20000000 C +ror r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 1, cpsr 0x20000000 C +ror r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 1, cpsr 0x20000000 C +ror r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x20000000 C +ror r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 1, cpsr 0x20000000 C +ror r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 1, cpsr 0x20000000 C +RORS immediate +rors r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 0, cpsr 0x00000000 +rors r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 0, cpsr 0x00000000 +rors r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 0, cpsr 0x00000000 +rors r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000 +rors r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 0, cpsr 0xa0000000 N C +rors r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 0, cpsr 0x00000000 +rors r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 1, cpsr 0x20000000 C +rors r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 1, cpsr 0x00000000 +rors r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 1, cpsr 0x00000000 +rors r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000 +rors r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 1, cpsr 0xa0000000 N C +rors r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 1, cpsr 0x00000000 +shift with barrel shifter +add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000000, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x3fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x00000020, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x000000ff, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000100, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000 +add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000000, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x3fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000001, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x0000001f, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x00000020, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x000000ff, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000100, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000008 rm 0x00000000, rn 0x00000008 rs 0x00000000, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000004 rm 0x00000000, rn 0x00000008 rs 0x00000001, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000002 rm 0x00000000, rn 0x00000008 rs 0x00000002, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000008 rs 0x00000003, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000004, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000005, carryin 0, cpsr 0x00000000 +add r0, r1, r2, asr r3 :: rd 0x00000008 rm 0x00000000, rn 0x00000008 rs 0x00000000, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000004 rm 0x00000000, rn 0x00000008 rs 0x00000001, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000002 rm 0x00000000, rn 0x00000008 rs 0x00000002, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000008 rs 0x00000003, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000004, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000005, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 0, cpsr 0x00000000 +add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 1, cpsr 0x20000000 C +add r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 1, cpsr 0x20000000 C +adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x40000000 Z +adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x40000000 Z +adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x40000000 Z +adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x40000000 Z +adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 0, cpsr 0x80000000 N +adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 0, cpsr 0x00000000 +adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x80000000 N +adds r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x80000000 N +adds r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x80000000 N +adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x40000000 Z +adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x40000000 Z +adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x80000000 N +adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x80000000 N +adds r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x00000000 +adds r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x00000000 +adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x40000000 Z +adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x40000000 Z +adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x80000000 N +adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 1, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 1, cpsr 0x80000000 N +adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 1, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 1, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 1, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 1, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 1, cpsr 0x00000000 +adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 1, cpsr 0x80000000 N +adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 1, cpsr 0x00000000 +adcs r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N +adcs r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N +adcs r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x80000000 N +adcs r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +adcs r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x60000000 ZC +adcs r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x60000000 ZC +adcs r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x80000000 N +adcs r0, r1, r2, lsr r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x90000000 N V +MUL +mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 +mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 +mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 +mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 +mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 +mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 +MULS +muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z +muls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x40000000 Z +muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x40000000 Z +muls r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 +muls r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 +muls r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x80000000 N +MLA +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mla r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mla r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000 +MLAS +mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mlas r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mlas r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mlas r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x80000000 N +MLS +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mls r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mls r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 +mls r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000 +UMULL +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 +umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +umull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 +umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 +umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000 Z +umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000 Z +umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000 Z +umulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +umulls r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 +umulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x80000000 N +SMULL +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 +smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +smull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 +smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 +smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000 Z +smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000 Z +smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000 Z +smulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +smulls r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 +smulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 +UMLAL +umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 +umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +umlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 +umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 +umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000 Z +umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x80000000 N +umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000 Z +umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000 Z +umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +umlals r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 +umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x80000000 N +SMLAL +smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 +smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 +smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +smlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 +smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 +smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000 Z +smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 +smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x80000000 N +smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000 Z +smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000 Z +smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 +smlals r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 +smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 +CLZ +clz r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 0, cpsr 0x00000000 +clz r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 0, cpsr 0x00000000 +clz r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 0, cpsr 0x00000000 +clz r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000 +clz r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 1, cpsr 0x20000000 C +clz r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 1, cpsr 0x20000000 C +clz r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 1, cpsr 0x20000000 C +clz r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x20000000 C +extend instructions +uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000 +uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, carryin 0, cpsr 0x00000000 +sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, carryin 0, cpsr 0x00000000 +sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +uxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +uxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, carryin 0, cpsr 0x00000000 +uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +sxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +sxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, carryin 0, cpsr 0x00000000 +sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, carryin 0, cpsr 0x00000000 +sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, carryin 0, cpsr 0x00000000 +sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, carryin 0, cpsr 0x00000000 +sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000 +uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, carryin 0, cpsr 0x00000000 +uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, carryin 0, cpsr 0x00000000 +uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, carryin 0, cpsr 0x00000000 +uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, carryin 0, cpsr 0x00000000 +uxtb16 r0, r1 :: rd 0x00ff00ff rm 0xffffffff, carryin 0, cpsr 0x00000000 +uxtb16 r0, r1, ror #16 :: rd 0x00ff0000 rm 0x0000ffff, carryin 0, cpsr 0x00000000 +sxtb16 r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +sxtb16 r0, r1 :: rd 0xffffffff rm 0x00ff00ff, carryin 0, cpsr 0x00000000 +sxtb16 r0, r1 :: rd 0x007f007f rm 0x007f007f, carryin 0, cpsr 0x00000000 +------------ BFI ------------ +bfi r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +bfi r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +bfi r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +bfi r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfi r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfi r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfi r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfi r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfi r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfi r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfi r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +------------ BFC ------------ +bfc r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +bfc r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +bfc r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +bfc r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfc r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfc r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfc r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfc r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfc r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfc r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +bfc r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 +------------ SBFX ------------ +sbfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +sbfx r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +------------ UBFX ------------ +ubfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +ubfx r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 +------------ SMULL{B,T}{B,T} ------------ +smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, carryin 0, cpsr 0x00000000 +smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, carryin 0, cpsr 0x00000000 +smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, carryin 0, cpsr 0x00000000 +smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, carryin 0, cpsr 0x00000000 +smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, carryin 0, cpsr 0x00000000 +------------ SXTAB ------------ +sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 +sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 +sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 +sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 +------------ UXTAB ------------ +uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 +uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 +uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 +uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 +------------ SXTAH ------------ +sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +sxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +sxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 +sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 +sxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 +sxtah r0, r1, r2, ROR #0 :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 +------------ UXTAH ------------ +uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +uxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +uxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 +uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 +uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 +uxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 +uxtah r0, r1, r2, ROR #0 :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 +------------ PLD/PLDW (begin) ------------ +pld reg +/- imm12 cases +pld reg +/- shifted reg cases +------------ PLD/PLDW (done) ------------ +------------ RBIT ------------ +rbit r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x00000001 rm 0x80000000, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0xe49a828c rm 0x31415927, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x46a82828 rm 0x14141562, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0xf89c17d5 rm 0xabe8391f, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x01551409 rm 0x9028aa80, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0xb63f8b57 rm 0xead1fc6d, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0xaa3193ac rm 0x35c98c55, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0xd78f52ca rm 0x534af1eb, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x10d88aa2 rm 0x45511b08, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x8efee009 rm 0x90077f71, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0xd215317b rm 0xde8ca84b, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x5bb05ec7 rm 0xe37a0dda, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0xd2bc1da7 rm 0xe5b83d4b, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x3728b6dd rm 0xbb6d14ec, carryin 0, cpsr 0x00000000 +rbit r0, r1 :: rd 0x933c1916 rm 0x68983cc9, carryin 0, cpsr 0x00000000 +------------ REV ------------ +rev r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x00000080 rm 0x80000000, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x01000000 rm 0x00000001, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x27594131 rm 0x31415927, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x62151414 rm 0x14141562, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x1f39e8ab rm 0xabe8391f, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x80aa2890 rm 0x9028aa80, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x6dfcd1ea rm 0xead1fc6d, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x558cc935 rm 0x35c98c55, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0xebf14a53 rm 0x534af1eb, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x081b5145 rm 0x45511b08, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x717f0790 rm 0x90077f71, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x4ba88cde rm 0xde8ca84b, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0xda0d7ae3 rm 0xe37a0dda, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0x4b3db8e5 rm 0xe5b83d4b, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0xec146dbb rm 0xbb6d14ec, carryin 0, cpsr 0x00000000 +rev r0, r1 :: rd 0xc93c9868 rm 0x68983cc9, carryin 0, cpsr 0x00000000 +------------ REV16 ------------ +rev16 r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x00800000 rm 0x80000000, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x00000100 rm 0x00000001, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x41312759 rm 0x31415927, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x14146215 rm 0x14141562, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0xe8ab1f39 rm 0xabe8391f, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x289080aa rm 0x9028aa80, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0xd1ea6dfc rm 0xead1fc6d, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0xc935558c rm 0x35c98c55, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x4a53ebf1 rm 0x534af1eb, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x5145081b rm 0x45511b08, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x0790717f rm 0x90077f71, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x8cde4ba8 rm 0xde8ca84b, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x7ae3da0d rm 0xe37a0dda, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0xb8e54b3d rm 0xe5b83d4b, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x6dbbec14 rm 0xbb6d14ec, carryin 0, cpsr 0x00000000 +rev16 r0, r1 :: rd 0x9868c93c rm 0x68983cc9, carryin 0, cpsr 0x00000000 +------------ NOP (begin) ------------ +nop +nopeq +nopne +------------ NOP (end) ------------ diff --git a/none/tests/arm/v6intARM.vgtest b/none/tests/arm/v6intARM.vgtest new file mode 100644 index 0000000..b2489f2 --- /dev/null +++ b/none/tests/arm/v6intARM.vgtest @@ -0,0 +1,2 @@ +prog: v6intARM +vgopts: -q diff --git a/none/tests/arm/v6intThumb.c b/none/tests/arm/v6intThumb.c new file mode 100644 index 0000000..99215f2 --- /dev/null +++ b/none/tests/arm/v6intThumb.c @@ -0,0 +1,5856 @@ + +/* How to compile: + gcc -O -g -Wall -mcpu=cortex-a8 -o testarmv6int testarmv6int.c +*/ + +#include + +static int gen_cvin(cvin) +{ + int r = ((cvin & 2) ? (1<<29) : 0) | ((cvin & 1) ? (1<<28) : 0); + r |= (1 << 31) | (1 << 30); + return r; +} + +/* test macros to generate and output the result of a single instruction */ + + +// 1 registers in the insn, zero args: rD = op() +#define TESTINST1(instruction, RD, cvin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_f, %2;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (gen_cvin(cvin)) \ + : #RD, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, \ + cvin, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + + + +// 1 registers in the insn, one args: rD = op(rD) +#define TESTINST1x(instruction, RDval, RD, cvin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_f, %2;" \ + "mov " #RD ",%3;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (gen_cvin(cvin)), "r"(RDval) \ + : #RD, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, \ + cvin, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + +// 2 registers in the insn, one arg: rD = op(rM) +#define TESTINST2(instruction, RMval, RD, RM, cvin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_f, %3;" \ + "mov " #RM ",%2;" \ + /* set #RD to 0x55555555 so we can see which parts get overwritten */ \ + "mov " #RD ", #0x55" "\n\t" \ + "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \ + "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (gen_cvin(cvin)) \ + : #RD, #RM, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, RMval, \ + cvin, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + + +// 2 registers in the insn, two args: rD = op(rD, rM) +#define TESTINST2x(instruction, RDval, RMval, RD, RM, cvin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_f, %3;" \ + "mov " #RM ",%2;" \ + "mov " #RD ",%4;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (gen_cvin(cvin)), "r"(RDval) \ + : #RD, #RM, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, RMval, \ + cvin, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + + + +#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, cvin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_f, %4;" \ + "mov " #RM ",%2;" \ + "mov " #RN ",%3;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (RNval), "r" (gen_cvin(cvin)) \ + : #RD, #RM, #RN, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, RMval, RNval, \ + cvin, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + +#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, cvin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_f, %5;" \ + "mov " #RM ",%2;" \ + "mov " #RN ",%3;" \ + "mov " #RS ",%4;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (RNval), "r" (RSval), "r" (gen_cvin(cvin)) \ + : #RD, #RM, #RN, #RS, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, RMval, RNval, RSval, \ + cvin, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + +#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \ +{ \ + unsigned int out; \ + unsigned int out2; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_f, %7;" \ + "mov " #RD ",%3;" \ + "mov " #RD2 ",%4;" \ + "mov " #RM ",%5;" \ + "mov " #RS ",%6;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mov %1," #RD2 ";" \ + "mrs %2,cpsr;" \ + : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \ + : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (gen_cvin(cvin)) \ + : #RD, #RD2, #RM, #RS, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \ + instruction, out, out2, RMval, RSval, \ + cvin, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ' \ + ); \ +} + +/* helpers */ +#define NOCARRY { int cv = 0; { +#define TESTCARRY { int cv = 0; for (cv = 0; cv < 4; cv++) { +#define TESTCARRYEND }} + +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +static int old_main(void) +{ + + printf("MOV\n"); + TESTINST2("mov r0, r1", 1, r0, r1, 0); + TESTINST2("cpy r0, r1", 1, r0, r1, 0); + TESTINST2("mov r0, #0", 0, r0, r1, 0); + TESTINST2("mov r0, #1", 0, r0, r1, 0); + TESTCARRY + TESTINST2("movs r0, r1", 1, r0, r1, cv); + TESTINST2("movs r0, r1", 0, r0, r1, cv); + TESTINST2("movs r0, r1", 0x80000000, r0, r1, cv); + TESTINST2("movs r0, #0", 0, r0, r1, cv); + TESTINST2("movs r0, #1", 0, r0, r1, cv); + TESTCARRYEND + + printf("MVN\n"); + TESTINST2("mvn r0, r1", 1, r0, r1, 0); + TESTCARRY + TESTINST2("mvns r0, r1", 1, r0, r1, cv); + TESTINST2("mvns r0, r1", 0, r0, r1, cv); + TESTINST2("mvns r0, r1", 0x80000000, r0, r1, cv); + TESTCARRYEND + + printf("ADD\n"); + TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0); + TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0); + + printf("ADC\n"); + TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1); + + printf("LSL\n"); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0); + + TESTINST3("lsl r0, r1, r2", 0x1, 0, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0x1, 1, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0x1, 31, r0, r1, r2, 0); + TESTINST3("lsl r0, r1, r2", 0x2, 31, r0, r1, r2, 0); + + printf("LSLS\n"); + TESTCARRY + TESTINST3("lsls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0x1, 0, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0x1, 1, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0x1, 31, r0, r1, r2, cv); + TESTINST3("lsls r0, r1, r2", 0x2, 31, r0, r1, r2, cv); + TESTCARRYEND + + printf("LSL immediate\n"); + TESTCARRY + TESTINST2("lsl r0, r1, #0", 0xffffffff, r0, r1, cv); + TESTINST2("lsl r0, r1, #1", 0xffffffff, r0, r1, cv); + TESTINST2("lsl r0, r1, #31", 0xffffffff, r0, r1, cv); + TESTINST2("lsl r0, r1, #0", 0x1, r0, r1, cv); + TESTINST2("lsl r0, r1, #1", 0x1, r0, r1, cv); + TESTINST2("lsl r0, r1, #31", 0x1, r0, r1, cv); + TESTINST2("lsl r0, r1, #31", 0x2, r0, r1, cv); + TESTCARRYEND + + printf("LSLS immediate\n"); + TESTCARRY + TESTINST2("lsls r0, r1, #0", 0xffffffff, r0, r1, cv); + TESTINST2("lsls r0, r1, #1", 0xffffffff, r0, r1, cv); + TESTINST2("lsls r0, r1, #31", 0xffffffff, r0, r1, cv); + TESTINST2("lsls r0, r1, #0", 0x1, r0, r1, cv); + TESTINST2("lsls r0, r1, #1", 0x1, r0, r1, cv); + TESTINST2("lsls r0, r1, #31", 0x1, r0, r1, cv); + TESTINST2("lsls r0, r1, #31", 0x2, r0, r1, cv); + TESTCARRYEND + + printf("LSR\n"); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0); + TESTINST3("lsr r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0); + + printf("LSRS\n"); + TESTCARRY + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv); + TESTINST3("lsrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv); + TESTCARRYEND + + printf("LSR immediate\n"); + TESTINST2("lsr r0, r1, #0", 0xffffffff, r0, r1, 0); + TESTINST2("lsr r0, r1, #1", 0xffffffff, r0, r1, 0); + TESTINST2("lsr r0, r1, #31", 0xffffffff, r0, r1, 0); + TESTINST2("lsr r0, r1, #32", 0xffffffff, r0, r1, 0); + TESTINST2("lsr r0, r1, #16", 0x00010000, r0, r1, 0); + TESTINST2("lsr r0, r1, #17", 0x00010000, r0, r1, 0); + TESTINST2("lsr r0, r1, #18", 0x00010000, r0, r1, 0); + + printf("LSRS immediate\n"); + TESTCARRY + TESTINST2("lsrs r0, r1, #0", 0xffffffff, r0, r1, cv); + TESTINST2("lsrs r0, r1, #1", 0xffffffff, r0, r1, cv); + TESTINST2("lsrs r0, r1, #31", 0xffffffff, r0, r1, cv); + TESTINST2("lsrs r0, r1, #32", 0xffffffff, r0, r1, cv); + TESTINST2("lsrs r0, r1, #16", 0x00010000, r0, r1, cv); + TESTINST2("lsrs r0, r1, #17", 0x00010000, r0, r1, cv); + TESTINST2("lsrs r0, r1, #18", 0x00010000, r0, r1, cv); + TESTCARRYEND + + printf("ASR\n"); + TESTCARRY + TESTINST3("asr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, cv); + TESTINST3("asr r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, cv); + TESTCARRYEND + + printf("ASRS\n"); + TESTCARRY + TESTINST3("asrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, cv); + TESTCARRYEND + + TESTCARRY + TESTINST3("asrs r0, r1, r2", 0x8, 0, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x8, 1, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x8, 2, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x8, 3, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x8, 4, r0, r1, r2, cv); + TESTINST3("asrs r0, r1, r2", 0x8, 5, r0, r1, r2, cv); + TESTCARRYEND + + TESTINST3("asrs r0, r1, r2", 0x80000001, 1, r0, r1, r2, 0); + TESTINST3("asrs r0, r1, r2", 0x80000001, 2, r0, r1, r2, 0); + + printf("ASR immediate\n"); + TESTINST2("asr r0, r1, #0", 0xffffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #1", 0xffffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #31", 0xffffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #32", 0xffffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #0", 0x7fffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #1", 0x7fffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #31", 0x7fffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #32", 0x7fffffff, r0, r1, 0); + TESTINST2("asr r0, r1, #16", 0x00010000, r0, r1, 0); + TESTINST2("asr r0, r1, #17", 0x00010000, r0, r1, 0); + TESTINST2("asr r0, r1, #18", 0x00010000, r0, r1, 0); + + printf("ASRS immediate\n"); + TESTCARRY + TESTINST2("asrs r0, r1, #0", 0xffffffff, r0, r1, cv); + TESTINST2("asrs r0, r1, #1", 0xffffffff, r0, r1, cv); + TESTINST2("asrs r0, r1, #31", 0xffffffff, r0, r1, cv); + TESTINST2("asrs r0, r1, #32", 0xffffffff, r0, r1, cv); + TESTINST2("asrs r0, r1, #0", 0x7fffffff, r0, r1, cv); + TESTINST2("asrs r0, r1, #1", 0x7fffffff, r0, r1, cv); + TESTINST2("asrs r0, r1, #31", 0x7fffffff, r0, r1, cv); + TESTINST2("asrs r0, r1, #32", 0x7fffffff, r0, r1, cv); + TESTINST2("asrs r0, r1, #16", 0x00010000, r0, r1, cv); + TESTINST2("asrs r0, r1, #17", 0x00010000, r0, r1, cv); + TESTINST2("asrs r0, r1, #18", 0x00010000, r0, r1, cv); + TESTCARRYEND + +#if 0 + printf("ROR\n"); + TESTCARRY + TESTINST3("ror r0, r1, r2", 0x00088000, 0, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x80088000, 1, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 1, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 2, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 31, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 32, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 33, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 63, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 64, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 255, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 256, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x80088000, 256, r0, r1, r2, cv); + TESTINST3("ror r0, r1, r2", 0x00088000, 257, r0, r1, r2, cv); + TESTCARRYEND + + printf("RORS\n"); + TESTCARRY + TESTINST3("rors r0, r1, r2", 0x00088000, 0, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x80088000, 0, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 1, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 2, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 31, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 32, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 33, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 63, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 64, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 255, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 256, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x80088000, 256, r0, r1, r2, cv); + TESTINST3("rors r0, r1, r2", 0x00088000, 257, r0, r1, r2, cv); + TESTCARRYEND + + printf("ROR immediate\n"); + TESTCARRY + TESTINST2("ror r0, r1, #0", 0x00088000, r0, r1, cv); + TESTINST2("ror r0, r1, #1", 0x00088000, r0, r1, cv); + TESTINST2("ror r0, r1, #31", 0x00088000, r0, r1, cv); + TESTINST2("ror r0, r1, #16", 0x00010000, r0, r1, cv); + TESTINST2("ror r0, r1, #17", 0x00010000, r0, r1, cv); + TESTINST2("ror r0, r1, #18", 0x00010000, r0, r1, cv); + TESTCARRYEND + + printf("RORS immediate\n"); + TESTCARRY + TESTINST2("rors r0, r1, #0", 0x00088000, r0, r1, cv); + TESTINST2("rors r0, r1, #1", 0x00088000, r0, r1, cv); + TESTINST2("rors r0, r1, #31", 0x00088000, r0, r1, cv); + TESTINST2("rors r0, r1, #16", 0x00010000, r0, r1, cv); + TESTINST2("rors r0, r1, #17", 0x00010000, r0, r1, cv); + TESTINST2("rors r0, r1, #18", 0x00010000, r0, r1, cv); + TESTCARRYEND +#endif +#if 0 + printf("shift with barrel shifter\n"); + TESTCARRY + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 0, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 1, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 31, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 32, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 255, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 256, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv); + TESTCARRYEND + + TESTCARRY + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 0, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 1, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 2, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 3, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 4, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 5, r0, r1, r2, r3, cv); + TESTCARRYEND + + TESTCARRY + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, cv); + TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, cv); + TESTCARRYEND +#endif +#if 0 + TESTCARRY + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv); + + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, cv); + TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, cv); + TESTCARRYEND +#endif + +#if 0 + TESTCARRY + TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); + TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); + TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); + TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); + TESTCARRYEND +#endif + + printf("MUL\n"); + TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); + +#if 0 + printf("MULS\n"); + TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); +#endif + + printf("MLA\n"); + TESTINST4("mla r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); + +#if 0 + printf("MLAS\n"); + TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); +#endif + + printf("MLS\n"); + TESTINST4("mls r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); + + printf("UMULL\n"); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#if 0 + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif + printf("SMULL\n"); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#if 0 + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif + +#if 0 + printf("UMLAL\n"); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif +#if 0 + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif +#if 0 + printf("SMLAL\n"); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif +#if 0 + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif + printf("CLZ\n"); + TESTCARRY + TESTINST2("clz r0, r1", 0, r0, r1, cv); + TESTINST2("clz r0, r1", 1, r0, r1, cv); + TESTINST2("clz r0, r1", 0x10, r0, r1, cv); + TESTINST2("clz r0, r1", 0xffffffff, r0, r1, cv); + TESTCARRYEND + + printf("extend instructions\n"); + TESTINST2("uxtb r0, r1", 0, r0, r1, 0); + TESTINST2("uxtb r0, r1", 1, r0, r1, 0); + TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0); + TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0, r0, r1, 0); + TESTINST2("sxtb r0, r1", 1, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0); + + TESTINST2("uxth r0, r1", 0, r0, r1, 0); + TESTINST2("uxth r0, r1", 1, r0, r1, 0); + TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0); + TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0, r0, r1, 0); + TESTINST2("sxth r0, r1", 1, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0); + + TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0); +#if 0 + TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0); +#endif + printf("------------ BFI ------------\n"); + + /* bfi rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */ + TESTINST2("bfi r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfi r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfi r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("bfi r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfi r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfi r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0); + + printf("------------ BFC ------------\n"); + + /* bfi rDst, #lsb-in-dst, #number-of-bits-to-copy */ + TESTINST2("bfc r0, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfc r0, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfc r0, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("bfc r0, #19, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #20, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #21, #11", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfc r0, #0, #32", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #1, #31", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfc r0, #29, #3", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #30, #2", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #31, #1", 0xFFFFFFFF, r0, r1, 0); + + printf("------------ SBFX ------------\n"); + + /* sbfx rDst, rSrc, #lsb, #width */ + TESTINST2("sbfx r0, r1, #0, #1", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #0, #1", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000002, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000003, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #0, #2", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #0, #2", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000002, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000003, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0); + + printf("------------ UBFX ------------\n"); + + /* ubfx rDst, rSrc, #lsb, #width */ + TESTINST2("ubfx r0, r1, #0, #1", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #0, #1", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000002, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000003, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #0, #2", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #0, #2", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000002, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000003, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0); + + printf("------------ SMULL{B,T}{B,T} ------------\n"); + /* SMULxx rD, rN, rM */ + + TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff, r0, r1, r2, 0); + + printf("------------ SXTAB ------------\n"); + TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, + r0, r1, r2, 0); +#if 0 + printf("------------ SXTAB16 ------------\n"); + TESTINST3("sxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("sxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("sxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182899, + r0, r1, r2, 0); +#endif + printf("------------ UXTAB ------------\n"); + TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, + r0, r1, r2, 0); +#if 0 + printf("------------ UXTAB16 ------------\n"); + TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182899, + r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182899, + r0, r1, r2, 0); +#endif + printf("------------ SXTAH ------------\n"); + TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, + r0, r1, r2, 0); + + printf("------------ UXTAH ------------\n"); + TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, + r0, r1, r2, 0); + + TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, + r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, + r0, r1, r2, 0); +#if 0 + printf("------------ PLD/PLDW (begin) ------------\n"); + /* These don't have any effect on the architected state, so, + uh, there's no result values to check. Just _do_ some of + them and check Valgrind's instruction decoder eats them up + without complaining. */ + { int alocal; + printf("pld reg +/- imm12 cases\n"); + __asm__ __volatile__( "pld [%0, #128]" : :/*in*/"r"(&alocal) ); + __asm__ __volatile__( "pld [%0, #-128]" : :/*in*/"r"(&alocal) ); + __asm__ __volatile__( "pld [r15, #-128]" : :/*in*/"r"(&alocal) ); + + // apparently pldw is v7 only + //__asm__ __volatile__( "pldw [%0, #128]" : :/*in*/"r"(&alocal) ); + //__asm__ __volatile__( "pldw [%0, #-128]" : :/*in*/"r"(&alocal) ); + //__asm__ __volatile__( "pldw [r15, #128]" : :/*in*/"r"(&alocal) ); + + printf("pld reg +/- shifted reg cases\n"); + __asm__ __volatile__( "pld [%0, %1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, LSL #1]" : : /*in*/"r"(&alocal), "r"(0) ); +#if 0 + __asm__ __volatile__( "pld [%0, %1, LSR #1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, ASR #1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, ROR #1]" : : /*in*/"r"(&alocal), "r"(0) ); + __asm__ __volatile__( "pld [%0, %1, RRX]" : : /*in*/"r"(&alocal), "r"(0) ); +#endif + } + printf("------------ PLD/PLDW (done) ------------\n"); +#endif + + return 0; +} + + +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + + +int main ( void ) +{ + // 16 bit instructions + + printf("CMP-16 0x10a\n"); + TESTCARRY + TESTINST3("cmp r3, r6", 0, 0, r6/*fake*/, r3, r6, 0); + TESTINST3("cmp r3, r6", 1, 0, r6/*fake*/, r3, r6, 0); + TESTINST3("cmp r3, r6", 0, 1, r6/*fake*/, r3, r6, 0); + TESTINST3("cmp r3, r6", -1, 0, r6/*fake*/, r3, r6, 0); + TESTINST3("cmp r3, r6", 0, -1, r6/*fake*/, r3, r6, 0); + TESTINST3("cmp r3, r6", 0, 0x80000000, r6/*fake*/, r3, r6, 0); + TESTINST3("cmp r3, r6", 0x80000000, 0, r6/*fake*/, r3, r6, 0); + TESTCARRYEND + + printf("CMN-16 0x10a\n"); + TESTCARRY + TESTINST3("cmn r3, r6", 0, 0, r6/*fake*/, r3, r6, 0); + TESTINST3("cmn r3, r6", 1, 0, r6/*fake*/, r3, r6, 0); + TESTINST3("cmn r3, r6", 0, 1, r6/*fake*/, r3, r6, 0); + TESTINST3("cmn r3, r6", -1, 0, r6/*fake*/, r3, r6, 0); + TESTINST3("cmn r3, r6", 0, -1, r6/*fake*/, r3, r6, 0); + TESTINST3("cmn r3, r6", 0, 0x80000000, r6/*fake*/, r3, r6, 0); + TESTINST3("cmn r3, r6", 0x80000000, 0, r6/*fake*/, r3, r6, 0); + TESTCARRYEND + + printf("TST-16 0x108\n"); + TESTCARRY + TESTINST3("tst r3, r6", 0, 0, r6/*fake*/, r3, r6, cv); + TESTINST3("tst r3, r6", 1, 0, r6/*fake*/, r3, r6, cv); + TESTINST3("tst r3, r6", 0, 1, r6/*fake*/, r3, r6, cv); + TESTINST3("tst r3, r6", 1, 1, r6/*fake*/, r3, r6, cv); + TESTINST3("tst r3, r6", -1, 0, r6/*fake*/, r3, r6, cv); + TESTINST3("tst r3, r6", 0, -1, r6/*fake*/, r3, r6, cv); + TESTINST3("tst r3, r6", -1, -1, r6/*fake*/, r3, r6, cv); + TESTCARRYEND + + printf("NEGS-16 0x109\n"); + TESTINST2("negs r0, r1", 1, r0, r1, 0); + TESTCARRY + TESTINST2("negs r0, r1", 1, r0, r1, cv); + TESTINST2("negs r0, r1", 0, r0, r1, cv); + TESTINST2("negs r0, r1", 0x80000000, r0, r1, cv); + TESTINST2("negs r0, r1", 0x80000001, r0, r1, cv); + TESTINST2("negs r0, r1", 0xFFFFFFFF, r0, r1, cv); + TESTINST2("negs r0, r1", 0x7FFFFFFF, r0, r1, cv); + TESTCARRYEND + + printf("MVNS-16 0x10F\n"); + TESTINST2("mvns r0, r1", 1, r0, r1, 0); + TESTCARRY + TESTINST2("mvns r0, r1", 1, r0, r1, cv); + TESTINST2("mvns r0, r1", 0, r0, r1, cv); + TESTINST2("mvns r0, r1", 0x80000000, r0, r1, cv); + TESTINST2("mvns r0, r1", 0x80000001, r0, r1, cv); + TESTINST2("mvns r0, r1", 0xFFFFFFFF, r0, r1, cv); + TESTINST2("mvns r0, r1", 0x7FFFFFFF, r0, r1, cv); + TESTCARRYEND + + printf("ORRS-16 0x10C\n"); + TESTCARRY + TESTINST2x("orrs r1, r2", 0x31415927, 0x27181728, r1, r2, cv); + TESTINST2x("orrs r1, r2", 0x00000000, 0x00000000, r1, r2, cv); + TESTINST2x("orrs r1, r2", 0x00000001, 0x00000000, r1, r2, cv); + TESTINST2x("orrs r1, r2", 0x00000000, 0x00000001, r1, r2, cv); + TESTINST2x("orrs r1, r2", 0x80000000, 0x00000000, r1, r2, cv); + TESTINST2x("orrs r1, r2", 0x00000000, 0x80000000, r1, r2, cv); + TESTINST2x("orrs r1, r2", 0x80000000, 0x80000000, r1, r2, cv); + TESTCARRYEND + + printf("ANDS-16 0x100\n"); + TESTCARRY + TESTINST2x("ands r1, r2", 0x31415927, 0x27181728, r1, r2, cv); + TESTINST2x("ands r1, r2", 0x00000000, 0x00000000, r1, r2, cv); + TESTINST2x("ands r1, r2", 0x00000001, 0x00000000, r1, r2, cv); + TESTINST2x("ands r1, r2", 0x00000000, 0x00000001, r1, r2, cv); + TESTINST2x("ands r1, r2", 0x80000000, 0x00000000, r1, r2, cv); + TESTINST2x("ands r1, r2", 0x00000000, 0x80000000, r1, r2, cv); + TESTINST2x("ands r1, r2", 0x80000000, 0x80000000, r1, r2, cv); + TESTCARRYEND + + printf("EORS-16 0x101\n"); + TESTCARRY + TESTINST2x("eors r1, r2", 0x31415927, 0x27181728, r1, r2, cv); + TESTINST2x("eors r1, r2", 0x00000000, 0x00000000, r1, r2, cv); + TESTINST2x("eors r1, r2", 0x00000001, 0x00000000, r1, r2, cv); + TESTINST2x("eors r1, r2", 0x00000000, 0x00000001, r1, r2, cv); + TESTINST2x("eors r1, r2", 0x80000000, 0x00000000, r1, r2, cv); + TESTINST2x("eors r1, r2", 0x00000000, 0x80000000, r1, r2, cv); + TESTINST2x("eors r1, r2", 0x80000000, 0x80000000, r1, r2, cv); + TESTCARRYEND + + printf("MULS-16 0x10d\n"); + TESTCARRY + TESTINST2x("muls r1, r2", 0x31415927, 0x27181728, r1, r2, cv); + TESTINST2x("muls r1, r2", 0x00000000, 0x00000000, r1, r2, cv); + TESTINST2x("muls r1, r2", 0x00000001, 0x00000000, r1, r2, cv); + TESTINST2x("muls r1, r2", 0x00000000, 0x00000001, r1, r2, cv); + TESTINST2x("muls r1, r2", 0x80000000, 0x00000000, r1, r2, cv); + TESTINST2x("muls r1, r2", 0x00000000, 0x80000000, r1, r2, cv); + TESTINST2x("muls r1, r2", 0x80000000, 0x80000000, r1, r2, cv); + TESTCARRYEND + + printf("BICS-16 0x10E\n"); + TESTCARRY + TESTINST2x("bics r1, r2", 0x31415927, 0x27181728, r1, r2, cv); + TESTINST2x("bics r1, r2", 0x00000000, 0x00000000, r1, r2, cv); + TESTINST2x("bics r1, r2", 0x00000001, 0x00000000, r1, r2, cv); + TESTINST2x("bics r1, r2", 0x00000000, 0x00000001, r1, r2, cv); + TESTINST2x("bics r1, r2", 0x80000000, 0x00000000, r1, r2, cv); + TESTINST2x("bics r1, r2", 0x00000000, 0x80000000, r1, r2, cv); + TESTINST2x("bics r1, r2", 0x80000000, 0x80000000, r1, r2, cv); + TESTCARRYEND + + printf("ADCS-16 0x105\n"); + TESTCARRY + TESTINST2x("adcs r1, r2", 0x31415927, 0x27181728, r1, r2, cv); + TESTINST2x("adcs r1, r2", 0x00000000, 0x00000000, r1, r2, cv); + TESTINST2x("adcs r1, r2", 0x00000001, 0x00000000, r1, r2, cv); + TESTINST2x("adcs r1, r2", 0x00000000, 0x00000001, r1, r2, cv); + TESTINST2x("adcs r1, r2", 0x80000000, 0x00000000, r1, r2, cv); + TESTINST2x("adcs r1, r2", 0x00000000, 0x80000000, r1, r2, cv); + TESTINST2x("adcs r1, r2", 0x80000000, 0x80000000, r1, r2, cv); + TESTCARRYEND + + printf("SBCS-16 0x100\n"); + TESTCARRY + TESTINST2x("sbcs r1, r2", 0x31415927, 0x27181728, r1, r2, cv); + TESTINST2x("sbcs r1, r2", 0x00000000, 0x00000000, r1, r2, cv); + TESTINST2x("sbcs r1, r2", 0x00000001, 0x00000000, r1, r2, cv); + TESTINST2x("sbcs r1, r2", 0x00000000, 0x00000001, r1, r2, cv); + TESTINST2x("sbcs r1, r2", 0x80000000, 0x00000000, r1, r2, cv); + TESTINST2x("sbcs r1, r2", 0x00000000, 0x80000000, r1, r2, cv); + TESTINST2x("sbcs r1, r2", 0x80000000, 0x80000000, r1, r2, cv); + TESTCARRYEND + + printf("UXTB-16 0x2CB\n"); + TESTCARRY + TESTINST2("uxtb r1, r2", 0x31415927, r1, r2, cv); + TESTINST2("uxtb r1, r2", 0x31415997, r1, r2, cv); + TESTCARRYEND + + printf("SXTB-16 0x2C9\n"); + TESTCARRY + TESTINST2("sxtb r1, r2", 0x31415927, r1, r2, cv); + TESTINST2("sxtb r1, r2", 0x31415997, r1, r2, cv); + TESTCARRYEND + + printf("UXTH-16 0x2CA\n"); + TESTCARRY + TESTINST2("uxth r1, r2", 0x31415927, r1, r2, cv); + TESTINST2("uxth r1, r2", 0x31419597, r1, r2, cv); + TESTCARRYEND + + printf("SXTH-16 0x2C8\n"); + TESTCARRY + TESTINST2("sxth r1, r2", 0x31415927, r1, r2, cv); + TESTINST2("sxth r1, r2", 0x31419597, r1, r2, cv); + TESTCARRYEND + + printf("LSLS-16 0x102\n"); + TESTCARRY + TESTINST2x("lsls r1, r2", 0x31415927, 0x00000000, r1, r2, cv); + TESTINST2x("lsls r1, r2", 0x31415927, 0x00000001, r1, r2, cv); + TESTINST2x("lsls r1, r2", 0x31415927, 0x00000002, r1, r2, cv); + TESTINST2x("lsls r1, r2", 0x31415927, 0x0000000F, r1, r2, cv); + TESTINST2x("lsls r1, r2", 0x31415927, 0x00000010, r1, r2, cv); + TESTINST2x("lsls r1, r2", 0x31415927, 0x0000001F, r1, r2, cv); + TESTINST2x("lsls r1, r2", 0x31415927, 0x00000020, r1, r2, cv); + TESTINST2x("lsls r1, r2", 0x31415927, 0x00000021, r1, r2, cv); + TESTCARRYEND + + printf("LSRS-16 0x103\n"); + TESTCARRY + TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000000, r1, r2, cv); + TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000001, r1, r2, cv); + TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000002, r1, r2, cv); + TESTINST2x("lsrs r1, r2", 0x31415927, 0x0000000F, r1, r2, cv); + TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000010, r1, r2, cv); + TESTINST2x("lsrs r1, r2", 0x31415927, 0x0000001F, r1, r2, cv); + TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000020, r1, r2, cv); + TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000021, r1, r2, cv); + TESTCARRYEND + + printf("ASRS-16 0x104\n"); + TESTCARRY + TESTINST2x("asrs r1, r2", 0x31415927, 0x00000000, r1, r2, cv); + TESTINST2x("asrs r1, r2", 0x91415927, 0x00000001, r1, r2, cv); + TESTINST2x("asrs r1, r2", 0x31415927, 0x00000002, r1, r2, cv); + TESTINST2x("asrs r1, r2", 0x91415927, 0x0000000F, r1, r2, cv); + TESTINST2x("asrs r1, r2", 0x31415927, 0x00000010, r1, r2, cv); + TESTINST2x("asrs r1, r2", 0x91415927, 0x0000001F, r1, r2, cv); + TESTINST2x("asrs r1, r2", 0x31415927, 0x00000020, r1, r2, cv); + TESTINST2x("asrs r1, r2", 0x91415927, 0x00000021, r1, r2, cv); + TESTCARRYEND + + printf("RORS-16 0x107\n"); + TESTCARRY + TESTINST2x("rors r1, r2", 0x31415927, 0x00000000, r1, r2, cv); + TESTINST2x("rors r1, r2", 0x31415927, 0x00000001, r1, r2, cv); + TESTINST2x("rors r1, r2", 0x31415927, 0x00000002, r1, r2, cv); + TESTINST2x("rors r1, r2", 0x31415927, 0x0000000F, r1, r2, cv); + TESTINST2x("rors r1, r2", 0x31415927, 0x00000010, r1, r2, cv); + TESTINST2x("rors r1, r2", 0x31415927, 0x0000001F, r1, r2, cv); + TESTINST2x("rors r1, r2", 0x31415927, 0x00000020, r1, r2, cv); + TESTINST2x("rors r1, r2", 0x31415927, 0x00000021, r1, r2, cv); + TESTCARRYEND + + printf("ADD(HI)-16\n"); + TESTCARRY + TESTINST2x("add r5, r12", 0x31415927, 0x12345678, r5, r12, cv); + TESTINST2x("add r4, r9 ", 0x31415927, 0x12345678, r4, r9, cv); + TESTCARRYEND + + printf("CMP(HI)-16 0x10a\n"); + TESTCARRY + TESTINST3("cmp r5, r12", 0, 0, r12/*fake*/, r5, r12, 0); + TESTINST3("cmp r5, r12", 1, 0, r12/*fake*/, r5, r12, 0); + TESTINST3("cmp r5, r12", 0, 1, r12/*fake*/, r5, r12, 0); + TESTINST3("cmp r5, r12", -1, 0, r12/*fake*/, r5, r12, 0); + TESTINST3("cmp r5, r12", 0, -1, r12/*fake*/, r5, r12, 0); + TESTINST3("cmp r5, r12", 0, 0x80000000, r12/*fake*/, r5, r12, 0); + TESTINST3("cmp r5, r12", 0x80000000, 0, r12/*fake*/, r5, r12, 0); + TESTCARRYEND + + printf("MOV(HI)-16\n"); + TESTCARRY + TESTINST2x("mov r5, r12", 0x31415927, 0x12345678, r5, r12, cv); + TESTINST2x("mov r4, r9 ", 0x31415927, 0x12345678, r4, r9, cv); + TESTCARRYEND + + printf("ADDS-16 Rd, Rn, #imm3\n"); + TESTCARRY + TESTINST2x("adds r1, r2, #1", 0x31415927, 0x27181728, r1, r2, cv); + TESTINST2x("adds r1, r2, #7", 0x31415927, 0x97181728, r1, r2, cv); + TESTCARRYEND + + printf("ADDS-16 Rd, Rn, Rm\n"); + TESTCARRY + TESTINST3("adds r1, r2, r3", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0, 0, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 1, 0, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0, 1, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", -1, 0, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0, -1, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds r1, r2, r3", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("SUBS-16 Rd, Rn, Rm\n"); + TESTCARRY + TESTINST3("subs r1, r2, r3", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0, 0, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 1, 0, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0, 1, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", -1, 0, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0, -1, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs r1, r2, r3", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("ADDS-16 Rn, #uimm8\n"); + TESTCARRY + TESTINST1x("adds r1, #0 ", 0x31415927, r1, cv); + TESTINST1x("adds r1, #255", 0x31415927, r1, cv); + TESTINST1x("adds r1, #0 ", 0x91415927, r1, cv); + TESTINST1x("adds r1, #255", 0x91415927, r1, cv); + TESTCARRYEND + + printf("SUBS-16 Rn, #uimm8\n"); + TESTCARRY + TESTINST1x("subs r1, #0 ", 0x31415927, r1, cv); + TESTINST1x("subs r1, #255", 0x31415927, r1, cv); + TESTINST1x("subs r1, #0 ", 0x91415927, r1, cv); + TESTINST1x("subs r1, #255", 0x91415927, r1, cv); + TESTCARRYEND + + printf("CMP-16 Rn, #uimm8\n"); + TESTCARRY + TESTINST1x("cmp r1, #0x80 ", 0x00000080, r1, cv); + TESTINST1x("cmp r1, #0x7f ", 0x00000080, r1, cv); + TESTINST1x("cmp r1, #0x81 ", 0x00000080, r1, cv); + TESTINST1x("cmp r1, #0x80 ", 0xffffff80, r1, cv); + TESTINST1x("cmp r1, #0x7f ", 0xffffff80, r1, cv); + TESTINST1x("cmp r1, #0x81 ", 0xffffff80, r1, cv); + TESTINST1x("cmp r1, #0x01 ", 0x80000000, r1, cv); + TESTCARRYEND + + printf("MOVS-16 Rn, #uimm8\n"); + TESTCARRY + TESTINST1x("movs r1, #0 ", 0x31415927, r1, cv); + TESTINST1x("movs r1, #0x7f", 0x31415927, r1, cv); + TESTINST1x("movs r1, #0x80", 0x31415927, r1, cv); + TESTINST1x("movs r1, #0x81", 0x31415927, r1, cv); + TESTINST1x("movs r1, #0xff", 0x31415927, r1, cv); + TESTCARRYEND + + printf("LSLS-16 Rd, Rm, imm5\n"); + TESTCARRY + TESTINST2("lsls r1, r2, #0 ", 0x31415927, r1, r2, cv); + TESTINST2("lsls r1, r2, #1 ", 0x31415927, r1, r2, cv); + TESTINST2("lsls r1, r2, #2 ", 0x31415927, r1, r2, cv); + TESTINST2("lsls r1, r2, #0xF ", 0x31415927, r1, r2, cv); + TESTINST2("lsls r1, r2, #0x10", 0x31415927, r1, r2, cv); + TESTINST2("lsls r1, r2, #0x1F", 0x31415927, r1, r2, cv); + TESTCARRYEND + + printf("LSRS-16 Rd, Rm, imm5\n"); + TESTCARRY + TESTINST2("lsrs r1, r2, #0 ", 0x31415927, r1, r2, cv); + TESTINST2("lsrs r1, r2, #1 ", 0x31415927, r1, r2, cv); + TESTINST2("lsrs r1, r2, #2 ", 0x31415927, r1, r2, cv); + TESTINST2("lsrs r1, r2, #0xF ", 0x31415927, r1, r2, cv); + TESTINST2("lsrs r1, r2, #0x10", 0x31415927, r1, r2, cv); + TESTINST2("lsrs r1, r2, #0x1F", 0x31415927, r1, r2, cv); + TESTCARRYEND + + printf("ASRS-16 Rd, Rm, imm5\n"); + TESTCARRY + TESTINST2("asrs r1, r2, #0 ", 0x31415927, r1, r2, cv); + TESTINST2("asrs r1, r2, #1 ", 0x91415927, r1, r2, cv); + TESTINST2("asrs r1, r2, #2 ", 0x31415927, r1, r2, cv); + TESTINST2("asrs r1, r2, #0xF ", 0x91415927, r1, r2, cv); + TESTINST2("asrs r1, r2, #0x10", 0x31415927, r1, r2, cv); + TESTINST2("asrs r1, r2, #0x1F", 0x91415927, r1, r2, cv); + TESTCARRYEND + + // 32 bit instructions + + printf("(T3) ADD{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("adds.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("adds.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("adds.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("adds.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("adds.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("add.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("add.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("add.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("add.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("add.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("add.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("add.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("add.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("add.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("add.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("add.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("add.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("add.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) CMP.W Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST1x("cmp.w r1, #0xffffffff", 0x31415927, r1, cv); + TESTINST1x("cmp.w r1, #0xee00ee00", 0x31415927, r1, cv); + TESTINST1x("cmp.w r1, #255 ", 0, r1, cv); + TESTINST1x("cmp.w r1, #0 ", 1, r1, cv); + TESTINST1x("cmp.w r1, #1 ", 0, r1, cv); + TESTINST1x("cmp.w r1, #0 ", -1, r1, cv); + TESTINST1x("cmp.w r1, #-1 ", 0, r1, cv); + TESTINST1x("cmp.w r1, #0x80000000", 0, r1, cv); + TESTINST1x("cmp.w r1, #0 ", 0x80000000, r1, cv); + TESTINST1x("cmp.w r1, #0x80000000", 0x80000000, r1, cv); + TESTINST1x("cmp.w r1, #0x80000000", 0x7fffffff, r1, cv); + TESTINST1x("cmp.w r1, #0xff000000", 0x80000000, r1, cv); + TESTINST1x("cmp.w r1, #0x0dd00000", 0x7fffffff, r1, cv); + TESTCARRYEND + + printf("(T3) CMN.W Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST1x("cmn.w r1, #0xffffffff", 0x31415927, r1, cv); + TESTINST1x("cmn.w r1, #0xee00ee00", 0x31415927, r1, cv); + TESTINST1x("cmn.w r1, #255 ", 0, r1, cv); + TESTINST1x("cmn.w r1, #0 ", 1, r1, cv); + TESTINST1x("cmn.w r1, #1 ", 0, r1, cv); + TESTINST1x("cmn.w r1, #0 ", -1, r1, cv); + TESTINST1x("cmn.w r1, #-1 ", 0, r1, cv); + TESTINST1x("cmn.w r1, #0x80000000", 0, r1, cv); + TESTINST1x("cmn.w r1, #0 ", 0x80000000, r1, cv); + TESTINST1x("cmn.w r1, #0x80000000", 0x80000000, r1, cv); + TESTINST1x("cmn.w r1, #0x80000000", 0x7fffffff, r1, cv); + TESTINST1x("cmn.w r1, #0xff000000", 0x80000000, r1, cv); + TESTINST1x("cmn.w r1, #0x0dd00000", 0x7fffffff, r1, cv); + TESTCARRYEND + + printf("(T3) TST.W Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST1x("tst.w r1, #0xffffffff", 0x31415927, r1, cv); + TESTINST1x("tst.w r1, #0xee00ee00", 0x31415927, r1, cv); + TESTINST1x("tst.w r1, #255 ", 0, r1, cv); + TESTINST1x("tst.w r1, #0 ", 1, r1, cv); + TESTINST1x("tst.w r1, #1 ", 0, r1, cv); + TESTINST1x("tst.w r1, #0 ", -1, r1, cv); + TESTINST1x("tst.w r1, #-1 ", 0, r1, cv); + TESTINST1x("tst.w r1, #0x80000000", 0, r1, cv); + TESTINST1x("tst.w r1, #0 ", 0x80000000, r1, cv); + TESTINST1x("tst.w r1, #0x80000000", 0x80000000, r1, cv); + TESTINST1x("tst.w r1, #0x80000000", 0x7fffffff, r1, cv); + TESTINST1x("tst.w r1, #0xff000000", 0x80000000, r1, cv); + TESTINST1x("tst.w r1, #0x0dd00000", 0x7fffffff, r1, cv); + TESTCARRYEND + + printf("(T3) TEQ.W Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST1x("teq.w r1, #0xffffffff", 0x31415927, r1, cv); + TESTINST1x("teq.w r1, #0xee00ee00", 0x31415927, r1, cv); + TESTINST1x("teq.w r1, #255 ", 0, r1, cv); + TESTINST1x("teq.w r1, #0 ", 1, r1, cv); + TESTINST1x("teq.w r1, #1 ", 0, r1, cv); + TESTINST1x("teq.w r1, #0 ", -1, r1, cv); + TESTINST1x("teq.w r1, #-1 ", 0, r1, cv); + TESTINST1x("teq.w r1, #0x80000000", 0, r1, cv); + TESTINST1x("teq.w r1, #0 ", 0x80000000, r1, cv); + TESTINST1x("teq.w r1, #0x80000000", 0x80000000, r1, cv); + TESTINST1x("teq.w r1, #0x80000000", 0x7fffffff, r1, cv); + TESTINST1x("teq.w r1, #0xff000000", 0x80000000, r1, cv); + TESTINST1x("teq.w r1, #0x0dd00000", 0x7fffffff, r1, cv); + TESTCARRYEND + + printf("(T3) SUB{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("subs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("subs.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("subs.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("subs.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("subs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("sub.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("sub.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("sub.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("sub.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) RSB{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("rsbs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("rsbs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("rsb.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) ADC{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("adcs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("adcs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("adc.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("adc.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("adc.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("adc.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) SBC{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("sbcs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("sbcs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("sbc.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) AND{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("ands.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("ands.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("ands.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("ands.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("ands.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("and.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("and.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("and.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("and.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("and.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("and.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("and.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("and.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("and.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("and.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("and.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("and.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("and.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) ORR{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("orrs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("orrs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("orr.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("orr.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("orr.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("orr.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) EOR{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("eors.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("eors.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("eors.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("eors.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("eors.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("eor.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("eor.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("eor.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("eor.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) BIC{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("bics.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("bics.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("bics.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("bics.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("bics.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("bic.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("bic.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("bic.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("bic.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T3) ORN{S}.W Rd, Rn, #constT [allegedly]\n"); + TESTCARRY + TESTINST2("orns.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("orns.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("orns.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("orns.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("orns.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv); + TESTINST2("orn.w r1, r2, #255 ", 0, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0 ", 1, r1, r2, cv); + TESTINST2("orn.w r1, r2, #1 ", 0, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0 ", -1, r1, r2, cv); + TESTINST2("orn.w r1, r2, #-1 ", 0, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0x80000000", 0, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0 ", 0x80000000, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv); + TESTINST2("orn.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv); + TESTCARRYEND + + printf("ADD{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adds.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("add.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("SUBB{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("subs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sub.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("RSB{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("rsb.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("ADC{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("adc.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("SBC{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("sbc.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + +#if 0 + printf("XXX{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("xxx.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND +#endif + + printf("AND{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("ands.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("and.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("ORR{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orrs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orr.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("EOR{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eors.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("eor.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("BIC{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bics.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("bic.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("ORN{S}.W Rd, Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orns.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTINST3("orn.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv); + TESTCARRYEND + + printf("(T?) LSL{S}.W Rd, Rn, Rm\n"); + TESTCARRY + TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv); + TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv); + TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv); + TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv); + TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv); + TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv); + TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv); + TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv); + TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv); + TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv); + TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv); + TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv); + TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv); + TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv); + TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv); + TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv); + TESTCARRYEND + + printf("(T?) LSR{S}.W Rd, Rn, Rm\n"); + TESTCARRY + TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv); + TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv); + TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv); + TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv); + TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv); + TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv); + TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv); + TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv); + TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv); + TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv); + TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv); + TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv); + TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv); + TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv); + TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv); + TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv); + TESTCARRYEND + + printf("(T?) ASR{S}.W Rd, Rn, Rm\n"); + TESTCARRY + TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv); + TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x00000001, r1, r2, r3, cv); + TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv); + TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x0000000F, r1, r2, r3, cv); + TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv); + TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x0000001F, r1, r2, r3, cv); + TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv); + TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x00000021, r1, r2, r3, cv); + TESTINST3("asr.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv); + TESTINST3("asr.w r1, r2, r3", 0x91415927, 0x00000001, r1, r2, r3, cv); + TESTINST3("asr.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv); + TESTINST3("asr.w r1, r2, r3", 0x91415927, 0x0000000F, r1, r2, r3, cv); + TESTINST3("asr.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv); + TESTINST3("asr.w r1, r2, r3", 0x91415927, 0x0000001F, r1, r2, r3, cv); + TESTINST3("asr.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv); + TESTINST3("asr.w r1, r2, r3", 0x91415927, 0x00000021, r1, r2, r3, cv); + TESTCARRYEND + +#if 0 + // not handled by vex + printf("(T?) ROR{S}.W Rd, Rn, Rm\n"); + TESTCARRY + TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv); + TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv); + TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv); + TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv); + TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv); + TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv); + TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv); + TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv); + TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv); + TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv); + TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv); + TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv); + TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv); + TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv); + TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv); + TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv); + TESTCARRYEND +#endif + + printf("MVN{S}.W Rd, Rn, shift, and MOV{S}.W ditto\n"); + TESTCARRY + TESTINST2("lsls.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #15", 0x7fffffff, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #31", 0x7fffffff, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #15", 0x7fffffff, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #31", 0x7fffffff, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #15", 0x7fffffff, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #31", 0x7fffffff, r1, r2, cv); + TESTINST2("rors.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("rors.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("rors.w r1, r2, #15", 0x7fffffff, r1, r2, cv); + TESTINST2("rors.w r1, r2, #31", 0x7fffffff, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #15", 0x7fffffff, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #31", 0x7fffffff, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #15", 0x7fffffff, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #31", 0x7fffffff, r1, r2, cv); + TESTINST2("asr.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("asr.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("asr.w r1, r2, #15", 0x7fffffff, r1, r2, cv); + TESTINST2("asr.w r1, r2, #31", 0x7fffffff, r1, r2, cv); + TESTINST2("ror.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("ror.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("ror.w r1, r2, #15", 0x7fffffff, r1, r2, cv); + TESTINST2("ror.w r1, r2, #31", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #15", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #31", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #15", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #31", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #15", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #31", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #15", 0x7fffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #31", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #15", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #31", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #15", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #31", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #15", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #31", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #0 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #1 ", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #15", 0x7fffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #31", 0x7fffffff, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #0 ", 0x00000000, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #1 ", 0x00000000, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #15", 0x00000000, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #31", 0x00000000, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #0 ", 0x00000000, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #1 ", 0x00000000, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #15", 0x00000000, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #31", 0x00000000, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #0 ", 0x00000000, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #1 ", 0x00000000, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #15", 0x00000000, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #31", 0x00000000, r1, r2, cv); + TESTINST2("rors.w r1, r2, #0 ", 0x00000000, r1, r2, cv); + TESTINST2("rors.w r1, r2, #1 ", 0x00000000, r1, r2, cv); + TESTINST2("rors.w r1, r2, #15", 0x00000000, r1, r2, cv); + TESTINST2("rors.w r1, r2, #31", 0x00000000, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #0 ", 0x00000000, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #1 ", 0x00000000, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #15", 0x00000000, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #31", 0x00000000, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #0 ", 0x00000000, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #1 ", 0x00000000, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #15", 0x00000000, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #31", 0x00000000, r1, r2, cv); + TESTINST2("asr.w r1, r2, #0 ", 0x00000000, r1, r2, cv); + TESTINST2("asr.w r1, r2, #1 ", 0x00000000, r1, r2, cv); + TESTINST2("asr.w r1, r2, #15", 0x00000000, r1, r2, cv); + TESTINST2("asr.w r1, r2, #31", 0x00000000, r1, r2, cv); + TESTINST2("ror.w r1, r2, #0 ", 0x00000000, r1, r2, cv); + TESTINST2("ror.w r1, r2, #1 ", 0x00000000, r1, r2, cv); + TESTINST2("ror.w r1, r2, #15", 0x00000000, r1, r2, cv); + TESTINST2("ror.w r1, r2, #31", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #0 ", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #1 ", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #15", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #31", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #0 ", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #1 ", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #15", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #31", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #0 ", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #1 ", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #15", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #31", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #0 ", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #1 ", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #15", 0x00000000, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #31", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #0 ", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #1 ", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #15", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #31", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #0 ", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #1 ", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #15", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #31", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #0 ", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #1 ", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #15", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #31", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #0 ", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #1 ", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #15", 0x00000000, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #31", 0x00000000, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #0 ", 0x00000001, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #1 ", 0x00000001, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #15", 0x00000001, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #31", 0x00000001, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #0 ", 0x00000001, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #1 ", 0x00000001, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #15", 0x00000001, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #31", 0x00000001, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #0 ", 0x00000001, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #1 ", 0x00000001, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #15", 0x00000001, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #31", 0x00000001, r1, r2, cv); + TESTINST2("rors.w r1, r2, #0 ", 0x00000001, r1, r2, cv); + TESTINST2("rors.w r1, r2, #1 ", 0x00000001, r1, r2, cv); + TESTINST2("rors.w r1, r2, #15", 0x00000001, r1, r2, cv); + TESTINST2("rors.w r1, r2, #31", 0x00000001, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #0 ", 0x00000001, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #1 ", 0x00000001, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #15", 0x00000001, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #31", 0x00000001, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #0 ", 0x00000001, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #1 ", 0x00000001, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #15", 0x00000001, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #31", 0x00000001, r1, r2, cv); + TESTINST2("asr.w r1, r2, #0 ", 0x00000001, r1, r2, cv); + TESTINST2("asr.w r1, r2, #1 ", 0x00000001, r1, r2, cv); + TESTINST2("asr.w r1, r2, #15", 0x00000001, r1, r2, cv); + TESTINST2("asr.w r1, r2, #31", 0x00000001, r1, r2, cv); + TESTINST2("ror.w r1, r2, #0 ", 0x00000001, r1, r2, cv); + TESTINST2("ror.w r1, r2, #1 ", 0x00000001, r1, r2, cv); + TESTINST2("ror.w r1, r2, #15", 0x00000001, r1, r2, cv); + TESTINST2("ror.w r1, r2, #31", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #0 ", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #1 ", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #15", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #31", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #0 ", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #1 ", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #15", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #31", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #0 ", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #1 ", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #15", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #31", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #0 ", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #1 ", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #15", 0x00000001, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #31", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #0 ", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #1 ", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #15", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #31", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #0 ", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #1 ", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #15", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #31", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #0 ", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #1 ", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #15", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #31", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #0 ", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #1 ", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #15", 0x00000001, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #31", 0x00000001, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #15", 0x9218abcd, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #31", 0x9218abcd, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #15", 0x9218abcd, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #31", 0x9218abcd, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #15", 0x9218abcd, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #31", 0x9218abcd, r1, r2, cv); + TESTINST2("rors.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("rors.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("rors.w r1, r2, #15", 0x9218abcd, r1, r2, cv); + TESTINST2("rors.w r1, r2, #31", 0x9218abcd, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #15", 0x9218abcd, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #31", 0x9218abcd, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #15", 0x9218abcd, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #31", 0x9218abcd, r1, r2, cv); + TESTINST2("asr.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("asr.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("asr.w r1, r2, #15", 0x9218abcd, r1, r2, cv); + TESTINST2("asr.w r1, r2, #31", 0x9218abcd, r1, r2, cv); + TESTINST2("ror.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("ror.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("ror.w r1, r2, #15", 0x9218abcd, r1, r2, cv); + TESTINST2("ror.w r1, r2, #31", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #15", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #31", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #15", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #31", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #15", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #31", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #15", 0x9218abcd, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #31", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #15", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #31", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #15", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #31", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #15", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #31", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #0 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #1 ", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #15", 0x9218abcd, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #31", 0x9218abcd, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #15", 0xffffffff, r1, r2, cv); + TESTINST2("lsls.w r1, r2, #31", 0xffffffff, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #15", 0xffffffff, r1, r2, cv); + TESTINST2("lsrs.w r1, r2, #31", 0xffffffff, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #15", 0xffffffff, r1, r2, cv); + TESTINST2("asrs.w r1, r2, #31", 0xffffffff, r1, r2, cv); + TESTINST2("rors.w r1, r2, #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("rors.w r1, r2, #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("rors.w r1, r2, #15", 0xffffffff, r1, r2, cv); + TESTINST2("rors.w r1, r2, #31", 0xffffffff, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #15", 0xffffffff, r1, r2, cv); + TESTINST2("lsl.w r1, r2, #31", 0xffffffff, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #15", 0xffffffff, r1, r2, cv); + TESTINST2("lsr.w r1, r2, #31", 0xffffffff, r1, r2, cv); + TESTINST2("asr.w r1, r2, #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("asr.w r1, r2, #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("asr.w r1, r2, #15", 0xffffffff, r1, r2, cv); + TESTINST2("asr.w r1, r2, #31", 0xffffffff, r1, r2, cv); + TESTINST2("ror.w r1, r2, #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("ror.w r1, r2, #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("ror.w r1, r2, #15", 0xffffffff, r1, r2, cv); + TESTINST2("ror.w r1, r2, #31", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #15", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsl #31", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #15", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, lsr #31", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #15", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, asr #31", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #15", 0xffffffff, r1, r2, cv); + TESTINST2("mvns.w r1, r2, ror #31", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #15", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsl #31", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #15", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, lsr #31", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #15", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, asr #31", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #0 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #1 ", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #15", 0xffffffff, r1, r2, cv); + TESTINST2("mvn.w r1, r2, ror #31", 0xffffffff, r1, r2, cv); + TESTCARRYEND + + printf("(T?) TST.W Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST2x("tst.w r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("tst.w r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("tst.w r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("tst.w r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("tst.w r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("tst.w r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("tst.w r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("tst.w r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("tst.w r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv); + TESTINST2x("tst.w r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv); + TESTINST2x("tst.w r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv); + TESTINST2x("tst.w r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv); + TESTCARRYEND + + printf("(T?) TEQ.W Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST2x("teq.w r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("teq.w r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("teq.w r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("teq.w r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("teq.w r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("teq.w r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("teq.w r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("teq.w r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("teq.w r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv); + TESTINST2x("teq.w r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv); + TESTINST2x("teq.w r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv); + TESTINST2x("teq.w r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv); + TESTCARRYEND + + printf("(T?) CMP.W Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST2x("cmp.w r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, lsr #2", 0x15555555, 0x55555555, r1, r2, cv); + TESTINST2x("cmp.w r1, r2, ror #1", 0x55555555, 0xaaaaaaaa, r1, r2, cv); + TESTCARRYEND + + printf("(T?) CMN.W Rn, Rm, {shift}\n"); + TESTCARRY + TESTINST2x("cmn.w r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, lsr #2", 0x15555555, 0x55555555, r1, r2, cv); + TESTINST2x("cmn.w r1, r2, ror #1", 0x55555555, 0xaaaaaaaa, r1, r2, cv); + TESTCARRYEND + + printf("(T2) MOV{S}.W Rd, #constT\n"); + TESTCARRY + TESTINST1("movs.w r9, 0x00000000", r9, cv); + TESTINST1("movs.w r9, 0x000000FF", r9, cv); + TESTINST1("movs.w r9, 0x0000007F", r9, cv); + TESTINST1("movs.w r9, 0x00FF00FF", r9, cv); + TESTINST1("movs.w r9, 0x007F007F", r9, cv); + TESTINST1("movs.w r9, 0x43434343", r9, cv); + TESTINST1("movs.w r9, 0x93939393", r9, cv); + TESTINST1("movs.w r9, 0x93000000", r9, cv); + TESTINST1("movs.w r9, 0x43000000", r9, cv); + TESTINST1("movs.w r9, 0x09300000", r9, cv); + TESTINST1("movs.w r9, 0x04300000", r9, cv); + TESTINST1("movs.w r9, 0x00930000", r9, cv); + TESTINST1("movs.w r9, 0x00430000", r9, cv); + TESTINST1("movs.w r9, 0x00000930", r9, cv); + TESTINST1("movs.w r9, 0x00000430", r9, cv); + TESTINST1("movs.w r9, 0x00000093", r9, cv); + TESTINST1("movs.w r9, 0x00000043", r9, cv); + TESTINST1("mov.w r9, 0x00000000", r9, cv); + TESTINST1("mov.w r9, 0x000000FF", r9, cv); + TESTINST1("mov.w r9, 0x0000007F", r9, cv); + TESTINST1("mov.w r9, 0x00FF00FF", r9, cv); + TESTINST1("mov.w r9, 0x007F007F", r9, cv); + TESTINST1("mov.w r9, 0x43434343", r9, cv); + TESTINST1("mov.w r9, 0x93939393", r9, cv); + TESTINST1("mov.w r9, 0x93000000", r9, cv); + TESTINST1("mov.w r9, 0x43000000", r9, cv); + TESTINST1("mov.w r9, 0x09300000", r9, cv); + TESTINST1("mov.w r9, 0x04300000", r9, cv); + TESTINST1("mov.w r9, 0x00930000", r9, cv); + TESTINST1("mov.w r9, 0x00430000", r9, cv); + TESTINST1("mov.w r9, 0x00000930", r9, cv); + TESTINST1("mov.w r9, 0x00000430", r9, cv); + TESTINST1("mov.w r9, 0x00000093", r9, cv); + TESTINST1("mov.w r9, 0x00000043", r9, cv); + TESTCARRYEND + + printf("(T2) MVN{S}.W Rd, #constT\n"); + TESTCARRY + TESTINST1("mvns.w r9, 0x00000000", r9, cv); + TESTINST1("mvns.w r9, 0x000000FF", r9, cv); + TESTINST1("mvns.w r9, 0x0000007F", r9, cv); + TESTINST1("mvns.w r9, 0x00FF00FF", r9, cv); + TESTINST1("mvns.w r9, 0x007F007F", r9, cv); + TESTINST1("mvns.w r9, 0x43434343", r9, cv); + TESTINST1("mvns.w r9, 0x93939393", r9, cv); + TESTINST1("mvns.w r9, 0x93000000", r9, cv); + TESTINST1("mvns.w r9, 0x43000000", r9, cv); + TESTINST1("mvns.w r9, 0x09300000", r9, cv); + TESTINST1("mvns.w r9, 0x04300000", r9, cv); + TESTINST1("mvns.w r9, 0x00930000", r9, cv); + TESTINST1("mvns.w r9, 0x00430000", r9, cv); + TESTINST1("mvns.w r9, 0x00000930", r9, cv); + TESTINST1("mvns.w r9, 0x00000430", r9, cv); + TESTINST1("mvns.w r9, 0x00000093", r9, cv); + TESTINST1("mvns.w r9, 0x00000043", r9, cv); + TESTINST1("mvn.w r9, 0x00000000", r9, cv); + TESTINST1("mvn.w r9, 0x000000FF", r9, cv); + TESTINST1("mvn.w r9, 0x0000007F", r9, cv); + TESTINST1("mvn.w r9, 0x00FF00FF", r9, cv); + TESTINST1("mvn.w r9, 0x007F007F", r9, cv); + TESTINST1("mvn.w r9, 0x43434343", r9, cv); + TESTINST1("mvn.w r9, 0x93939393", r9, cv); + TESTINST1("mvn.w r9, 0x93000000", r9, cv); + TESTINST1("mvn.w r9, 0x43000000", r9, cv); + TESTINST1("mvn.w r9, 0x09300000", r9, cv); + TESTINST1("mvn.w r9, 0x04300000", r9, cv); + TESTINST1("mvn.w r9, 0x00930000", r9, cv); + TESTINST1("mvn.w r9, 0x00430000", r9, cv); + TESTINST1("mvn.w r9, 0x00000930", r9, cv); + TESTINST1("mvn.w r9, 0x00000430", r9, cv); + TESTINST1("mvn.w r9, 0x00000093", r9, cv); + TESTINST1("mvn.w r9, 0x00000043", r9, cv); + TESTCARRYEND + + printf("(T1) RBIT Rd, Rm\n"); + TESTINST2("rbit r0, r1", 0x00000000, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x80000000, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x00000001, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x31415927, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x14141562, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xabe8391f, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x9028aa80, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xead1fc6d, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x35c98c55, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x534af1eb, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x45511b08, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x90077f71, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xde8ca84b, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xe37a0dda, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xe5b83d4b, r0, r1, 0); + TESTINST2("rbit r0, r1", 0xbb6d14ec, r0, r1, 0); + TESTINST2("rbit r0, r1", 0x68983cc9, r0, r1, 0); + + printf("(T1) REV Rd, Rm ------------\n"); + TESTINST2("rev r0, r1", 0x00000000, r0, r1, 0); + TESTINST2("rev r0, r1", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("rev r0, r1", 0x80000000, r0, r1, 0); + TESTINST2("rev r0, r1", 0x00000001, r0, r1, 0); + TESTINST2("rev r0, r1", 0x31415927, r0, r1, 0); + TESTINST2("rev r0, r1", 0x14141562, r0, r1, 0); + TESTINST2("rev r0, r1", 0xabe8391f, r0, r1, 0); + TESTINST2("rev r0, r1", 0x9028aa80, r0, r1, 0); + TESTINST2("rev r0, r1", 0xead1fc6d, r0, r1, 0); + TESTINST2("rev r0, r1", 0x35c98c55, r0, r1, 0); + TESTINST2("rev r0, r1", 0x534af1eb, r0, r1, 0); + TESTINST2("rev r0, r1", 0x45511b08, r0, r1, 0); + TESTINST2("rev r0, r1", 0x90077f71, r0, r1, 0); + TESTINST2("rev r0, r1", 0xde8ca84b, r0, r1, 0); + TESTINST2("rev r0, r1", 0xe37a0dda, r0, r1, 0); + TESTINST2("rev r0, r1", 0xe5b83d4b, r0, r1, 0); + TESTINST2("rev r0, r1", 0xbb6d14ec, r0, r1, 0); + TESTINST2("rev r0, r1", 0x68983cc9, r0, r1, 0); + + printf("(T2) REV Rd, Rm ------------\n"); + TESTINST2("rev r8, r9", 0x00000000, r8, r9, 0); + TESTINST2("rev r8, r9", 0xFFFFFFFF, r8, r9, 0); + TESTINST2("rev r8, r9", 0x80000000, r8, r9, 0); + TESTINST2("rev r8, r9", 0x00000001, r8, r9, 0); + TESTINST2("rev r8, r9", 0x31415927, r8, r9, 0); + TESTINST2("rev r8, r9", 0x14141562, r8, r9, 0); + TESTINST2("rev r8, r9", 0xabe8391f, r8, r9, 0); + TESTINST2("rev r8, r9", 0x9028aa80, r8, r9, 0); + TESTINST2("rev r8, r9", 0xead1fc6d, r8, r9, 0); + TESTINST2("rev r8, r9", 0x35c98c55, r8, r9, 0); + TESTINST2("rev r8, r9", 0x534af1eb, r8, r9, 0); + TESTINST2("rev r8, r9", 0x45511b08, r8, r9, 0); + TESTINST2("rev r8, r9", 0x90077f71, r8, r9, 0); + TESTINST2("rev r8, r9", 0xde8ca84b, r8, r9, 0); + TESTINST2("rev r8, r9", 0xe37a0dda, r8, r9, 0); + TESTINST2("rev r8, r9", 0xe5b83d4b, r8, r9, 0); + TESTINST2("rev r8, r9", 0xbb6d14ec, r8, r9, 0); + TESTINST2("rev r8, r9", 0x68983cc9, r8, r9, 0); + + printf("(T1) REV16 Rd, Rm ------------\n"); + TESTINST2("rev16 r0, r1", 0x00000000, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x80000000, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x00000001, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x31415927, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x14141562, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xabe8391f, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x9028aa80, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xead1fc6d, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x35c98c55, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x534af1eb, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x45511b08, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x90077f71, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xde8ca84b, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xe37a0dda, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xe5b83d4b, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0xbb6d14ec, r0, r1, 0); + TESTINST2("rev16 r0, r1", 0x68983cc9, r0, r1, 0); + + printf("(T2) REV16 Rd, Rm ------------\n"); + TESTINST2("rev16 r8, r9", 0x00000000, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0xFFFFFFFF, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x80000000, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x00000001, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x31415927, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x14141562, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0xabe8391f, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x9028aa80, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0xead1fc6d, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x35c98c55, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x534af1eb, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x45511b08, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x90077f71, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0xde8ca84b, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0xe37a0dda, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0xe5b83d4b, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0xbb6d14ec, r8, r9, 0); + TESTINST2("rev16 r8, r9", 0x68983cc9, r8, r9, 0); + + printf("------------ NOP (begin) ------------\n"); + printf("nop\n"); + __asm__ __volatile__("nop" ::: "memory","cc"); + printf("nop.w\n"); + __asm__ __volatile__("nop.w" ::: "memory","cc"); + printf("------------ NOP (end) ------------\n"); + + // plus whatever stuff we can throw in from the old ARM test program + old_main(); + + return 0; +} diff --git a/none/tests/arm/v6intThumb.stderr.exp b/none/tests/arm/v6intThumb.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/arm/v6intThumb.stdout.exp b/none/tests/arm/v6intThumb.stdout.exp new file mode 100644 index 0000000..dfb0acb --- /dev/null +++ b/none/tests/arm/v6intThumb.stdout.exp @@ -0,0 +1,17337 @@ +CMP-16 0x10a +cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +CMN-16 0x10a +cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +TST-16 0x108 +tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +NEGS-16 0x109 +negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x90000000 N V +negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 0, cpsr 0x00000000 +negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x00000000 +negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x80000000 N +negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 1, cpsr 0x00000000 +negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x00000000 +negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N V +negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 2, cpsr 0x00000000 +negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x00000000 +negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N +negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N V +negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 3, cpsr 0x00000000 +negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x00000000 +negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +MVNS-16 0x10F +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000 +mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 0, cpsr 0x00000000 +mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x10000000 V +mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 1, cpsr 0x10000000 V +mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 2, cpsr 0x20000000 C +mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 2, cpsr 0x20000000 C +mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV +mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 3, cpsr 0x30000000 CV +mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +ORRS-16 0x10C +orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 2, cpsr 0x20000000 C +orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 3, cpsr 0x30000000 CV +orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +ANDS-16 0x100 +ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 0, cpsr 0x00000000 +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 2, cpsr 0x20000000 C +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 3, cpsr 0x30000000 CV +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +EORS-16 0x101 +eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 0, cpsr 0x00000000 +eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z +eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 2, cpsr 0x20000000 C +eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 3, cpsr 0x30000000 CV +eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +MULS-16 0x10d +muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 0, cpsr 0x80000000 N +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z +muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z +muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 1, cpsr 0x90000000 N V +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 2, cpsr 0xa0000000 N C +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 3, cpsr 0xb0000000 N CV +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +BICS-16 0x10E +bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 0, cpsr 0x00000000 +bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 2, cpsr 0x20000000 C +bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 3, cpsr 0x30000000 CV +bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ADCS-16 0x105 +adcs r1, r2 :: rd 0x5859704f rm 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +adcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adcs r1, r2 :: rd 0x5859704f rm 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000 +adcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adcs r1, r2 :: rd 0x58597050 rm 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs r1, r2 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs r1, r2 :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs r1, r2 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adcs r1, r2 :: rd 0x58597050 rm 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs r1, r2 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs r1, r2 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs r1, r2 :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs r1, r2 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV +SBCS-16 0x100 +sbcs r1, r2 :: rd 0x0a2941fe rm 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs r1, r2 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs r1, r2 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs r1, r2 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs r1, r2 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000 +sbcs r1, r2 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs r1, r2 :: rd 0x0a2941fe rm 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs r1, r2 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs r1, r2 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs r1, r2 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs r1, r2 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x00000000 +sbcs r1, r2 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs r1, r2 :: rd 0x0a2941ff rm 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs r1, r2 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +sbcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs r1, r2 :: rd 0x0a2941ff rm 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs r1, r2 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N +sbcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +UXTB-16 0x2CB +uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 1, cpsr 0xd0000000 NZ V +uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 2, cpsr 0xe0000000 NZC +uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV +SXTB-16 0x2C9 +sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 0, cpsr 0xc0000000 NZ +sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 1, cpsr 0xd0000000 NZ V +sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 2, cpsr 0xe0000000 NZC +sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV +UXTH-16 0x2CA +uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 0, cpsr 0xc0000000 NZ +uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 1, cpsr 0xd0000000 NZ V +uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 2, cpsr 0xe0000000 NZC +uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV +SXTH-16 0x2C8 +sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 0, cpsr 0xc0000000 NZ +sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 1, cpsr 0xd0000000 NZ V +sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 2, cpsr 0xe0000000 NZC +sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV +LSLS-16 0x102 +lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 0, cpsr 0x00000000 +lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 0, cpsr 0x80000000 N +lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 0, cpsr 0x80000000 N +lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 0, cpsr 0x20000000 C +lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C +lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x60000000 ZC +lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 0, cpsr 0x40000000 Z +lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 1, cpsr 0x90000000 N V +lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 1, cpsr 0x90000000 N V +lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 1, cpsr 0x30000000 CV +lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV +lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x70000000 ZCV +lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 1, cpsr 0x50000000 Z V +lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 2, cpsr 0x00000000 +lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 2, cpsr 0x80000000 N +lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 2, cpsr 0x80000000 N +lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 2, cpsr 0x20000000 C +lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C +lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x60000000 ZC +lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 2, cpsr 0x40000000 Z +lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 3, cpsr 0x10000000 V +lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 3, cpsr 0x90000000 N V +lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 3, cpsr 0x90000000 N V +lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 3, cpsr 0x30000000 CV +lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV +lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x70000000 ZCV +lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 3, cpsr 0x50000000 Z V +LSRS-16 0x103 +lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 0, cpsr 0x20000000 C +lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 0, cpsr 0x20000000 C +lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 0, cpsr 0x20000000 C +lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 0, cpsr 0x00000000 +lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 0, cpsr 0x40000000 Z +lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x40000000 Z +lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 0, cpsr 0x40000000 Z +lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 1, cpsr 0x30000000 CV +lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 1, cpsr 0x30000000 CV +lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 1, cpsr 0x30000000 CV +lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 1, cpsr 0x10000000 V +lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 1, cpsr 0x50000000 Z V +lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x50000000 Z V +lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 1, cpsr 0x50000000 Z V +lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 2, cpsr 0x20000000 C +lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 2, cpsr 0x20000000 C +lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 2, cpsr 0x00000000 +lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 2, cpsr 0x40000000 Z +lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x40000000 Z +lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 2, cpsr 0x40000000 Z +lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 3, cpsr 0x30000000 CV +lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 3, cpsr 0x30000000 CV +lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 3, cpsr 0x10000000 V +lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 3, cpsr 0x50000000 Z V +lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x50000000 Z V +lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 3, cpsr 0x50000000 Z V +ASRS-16 0x104 +asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 0, cpsr 0x20000000 C +asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C +asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 0, cpsr 0x00000000 +asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 0, cpsr 0x80000000 N +asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x40000000 Z +asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 0, cpsr 0xa0000000 N C +asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 1, cpsr 0x30000000 CV +asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV +asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 1, cpsr 0x10000000 V +asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 1, cpsr 0x90000000 N V +asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x50000000 Z V +asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV +asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 2, cpsr 0x20000000 C +asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C +asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 2, cpsr 0x00000000 +asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 2, cpsr 0x80000000 N +asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x40000000 Z +asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 2, cpsr 0xa0000000 N C +asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 3, cpsr 0x30000000 CV +asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV +asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 3, cpsr 0x10000000 V +asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 3, cpsr 0x90000000 N V +asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x50000000 Z V +asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV +RORS-16 0x107 +rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 0, cpsr 0xa0000000 N C +rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C +rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 0, cpsr 0x00000000 +rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 0, cpsr 0x00000000 +rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 0, cpsr 0x00000000 +rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 0, cpsr 0xa0000000 N C +rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV +rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV +rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 1, cpsr 0x10000000 V +rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 1, cpsr 0x10000000 V +rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 1, cpsr 0x10000000 V +rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV +rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 2, cpsr 0xa0000000 N C +rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C +rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 2, cpsr 0x00000000 +rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 2, cpsr 0x00000000 +rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 2, cpsr 0x00000000 +rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 2, cpsr 0xa0000000 N C +rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV +rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV +rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 3, cpsr 0x10000000 V +rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 3, cpsr 0x10000000 V +rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 3, cpsr 0x10000000 V +rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV +ADD(HI)-16 +add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ +add r4, r9 :: rd 0x4375af9f rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ +add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V +add r4, r9 :: rd 0x4375af9f rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V +add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC +add r4, r9 :: rd 0x4375af9f rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC +add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV +add r4, r9 :: rd 0x4375af9f rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV +CMP(HI)-16 0x10a +cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +MOV(HI)-16 +mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ +mov r4, r9 :: rd 0x12345678 rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ +mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V +mov r4, r9 :: rd 0x12345678 rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V +mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC +mov r4, r9 :: rd 0x12345678 rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC +mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV +mov r4, r9 :: rd 0x12345678 rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV +ADDS-16 Rd, Rn, #imm3 +adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 0, cpsr 0x00000000 +adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 0, cpsr 0x80000000 N +adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 1, cpsr 0x00000000 +adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 1, cpsr 0x80000000 N +adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 2, cpsr 0x00000000 +adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 2, cpsr 0x80000000 N +adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 3, cpsr 0x00000000 +adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 3, cpsr 0x80000000 N +ADDS-16 Rd, Rn, Rm +adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV +adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +SUBS-16 Rd, Rn, Rm +subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +ADDS-16 Rn, #uimm8 +adds r1, #0 :: rd 0x31415927, c:v-in 0, cpsr 0x00000000 +adds r1, #255 :: rd 0x31415a26, c:v-in 0, cpsr 0x00000000 +adds r1, #0 :: rd 0x91415927, c:v-in 0, cpsr 0x80000000 N +adds r1, #255 :: rd 0x91415a26, c:v-in 0, cpsr 0x80000000 N +adds r1, #0 :: rd 0x31415927, c:v-in 1, cpsr 0x00000000 +adds r1, #255 :: rd 0x31415a26, c:v-in 1, cpsr 0x00000000 +adds r1, #0 :: rd 0x91415927, c:v-in 1, cpsr 0x80000000 N +adds r1, #255 :: rd 0x91415a26, c:v-in 1, cpsr 0x80000000 N +adds r1, #0 :: rd 0x31415927, c:v-in 2, cpsr 0x00000000 +adds r1, #255 :: rd 0x31415a26, c:v-in 2, cpsr 0x00000000 +adds r1, #0 :: rd 0x91415927, c:v-in 2, cpsr 0x80000000 N +adds r1, #255 :: rd 0x91415a26, c:v-in 2, cpsr 0x80000000 N +adds r1, #0 :: rd 0x31415927, c:v-in 3, cpsr 0x00000000 +adds r1, #255 :: rd 0x31415a26, c:v-in 3, cpsr 0x00000000 +adds r1, #0 :: rd 0x91415927, c:v-in 3, cpsr 0x80000000 N +adds r1, #255 :: rd 0x91415a26, c:v-in 3, cpsr 0x80000000 N +SUBS-16 Rn, #uimm8 +subs r1, #0 :: rd 0x31415927, c:v-in 0, cpsr 0x20000000 C +subs r1, #255 :: rd 0x31415828, c:v-in 0, cpsr 0x20000000 C +subs r1, #0 :: rd 0x91415927, c:v-in 0, cpsr 0xa0000000 N C +subs r1, #255 :: rd 0x91415828, c:v-in 0, cpsr 0xa0000000 N C +subs r1, #0 :: rd 0x31415927, c:v-in 1, cpsr 0x20000000 C +subs r1, #255 :: rd 0x31415828, c:v-in 1, cpsr 0x20000000 C +subs r1, #0 :: rd 0x91415927, c:v-in 1, cpsr 0xa0000000 N C +subs r1, #255 :: rd 0x91415828, c:v-in 1, cpsr 0xa0000000 N C +subs r1, #0 :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C +subs r1, #255 :: rd 0x31415828, c:v-in 2, cpsr 0x20000000 C +subs r1, #0 :: rd 0x91415927, c:v-in 2, cpsr 0xa0000000 N C +subs r1, #255 :: rd 0x91415828, c:v-in 2, cpsr 0xa0000000 N C +subs r1, #0 :: rd 0x31415927, c:v-in 3, cpsr 0x20000000 C +subs r1, #255 :: rd 0x31415828, c:v-in 3, cpsr 0x20000000 C +subs r1, #0 :: rd 0x91415927, c:v-in 3, cpsr 0xa0000000 N C +subs r1, #255 :: rd 0x91415828, c:v-in 3, cpsr 0xa0000000 N C +CMP-16 Rn, #uimm8 +cmp r1, #0x80 :: rd 0x00000080, c:v-in 0, cpsr 0x60000000 ZC +cmp r1, #0x7f :: rd 0x00000080, c:v-in 0, cpsr 0x20000000 C +cmp r1, #0x81 :: rd 0x00000080, c:v-in 0, cpsr 0x80000000 N +cmp r1, #0x80 :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C +cmp r1, #0x7f :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C +cmp r1, #0x81 :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C +cmp r1, #0x01 :: rd 0x80000000, c:v-in 0, cpsr 0x30000000 CV +cmp r1, #0x80 :: rd 0x00000080, c:v-in 1, cpsr 0x60000000 ZC +cmp r1, #0x7f :: rd 0x00000080, c:v-in 1, cpsr 0x20000000 C +cmp r1, #0x81 :: rd 0x00000080, c:v-in 1, cpsr 0x80000000 N +cmp r1, #0x80 :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C +cmp r1, #0x7f :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C +cmp r1, #0x81 :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C +cmp r1, #0x01 :: rd 0x80000000, c:v-in 1, cpsr 0x30000000 CV +cmp r1, #0x80 :: rd 0x00000080, c:v-in 2, cpsr 0x60000000 ZC +cmp r1, #0x7f :: rd 0x00000080, c:v-in 2, cpsr 0x20000000 C +cmp r1, #0x81 :: rd 0x00000080, c:v-in 2, cpsr 0x80000000 N +cmp r1, #0x80 :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C +cmp r1, #0x7f :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C +cmp r1, #0x81 :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C +cmp r1, #0x01 :: rd 0x80000000, c:v-in 2, cpsr 0x30000000 CV +cmp r1, #0x80 :: rd 0x00000080, c:v-in 3, cpsr 0x60000000 ZC +cmp r1, #0x7f :: rd 0x00000080, c:v-in 3, cpsr 0x20000000 C +cmp r1, #0x81 :: rd 0x00000080, c:v-in 3, cpsr 0x80000000 N +cmp r1, #0x80 :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C +cmp r1, #0x7f :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C +cmp r1, #0x81 :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C +cmp r1, #0x01 :: rd 0x80000000, c:v-in 3, cpsr 0x30000000 CV +MOVS-16 Rn, #uimm8 +movs r1, #0 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z +movs r1, #0x7f :: rd 0x0000007f, c:v-in 0, cpsr 0x00000000 +movs r1, #0x80 :: rd 0x00000080, c:v-in 0, cpsr 0x00000000 +movs r1, #0x81 :: rd 0x00000081, c:v-in 0, cpsr 0x00000000 +movs r1, #0xff :: rd 0x000000ff, c:v-in 0, cpsr 0x00000000 +movs r1, #0 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +movs r1, #0x7f :: rd 0x0000007f, c:v-in 1, cpsr 0x10000000 V +movs r1, #0x80 :: rd 0x00000080, c:v-in 1, cpsr 0x10000000 V +movs r1, #0x81 :: rd 0x00000081, c:v-in 1, cpsr 0x10000000 V +movs r1, #0xff :: rd 0x000000ff, c:v-in 1, cpsr 0x10000000 V +movs r1, #0 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +movs r1, #0x7f :: rd 0x0000007f, c:v-in 2, cpsr 0x20000000 C +movs r1, #0x80 :: rd 0x00000080, c:v-in 2, cpsr 0x20000000 C +movs r1, #0x81 :: rd 0x00000081, c:v-in 2, cpsr 0x20000000 C +movs r1, #0xff :: rd 0x000000ff, c:v-in 2, cpsr 0x20000000 C +movs r1, #0 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +movs r1, #0x7f :: rd 0x0000007f, c:v-in 3, cpsr 0x30000000 CV +movs r1, #0x80 :: rd 0x00000080, c:v-in 3, cpsr 0x30000000 CV +movs r1, #0x81 :: rd 0x00000081, c:v-in 3, cpsr 0x30000000 CV +movs r1, #0xff :: rd 0x000000ff, c:v-in 3, cpsr 0x30000000 CV +LSLS-16 Rd, Rm, imm5 +lsls r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +lsls r1, r2, #1 :: rd 0x6282b24e rm 0x31415927, c:v-in 0, cpsr 0x00000000 +lsls r1, r2, #2 :: rd 0xc505649c rm 0x31415927, c:v-in 0, cpsr 0x80000000 N +lsls r1, r2, #0xF :: rd 0xac938000 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N +lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C +lsls r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +lsls r1, r2, #1 :: rd 0x6282b24e rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +lsls r1, r2, #2 :: rd 0xc505649c rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V +lsls r1, r2, #0xF :: rd 0xac938000 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V +lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV +lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 1, cpsr 0xb0000000 N CV +lsls r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +lsls r1, r2, #1 :: rd 0x6282b24e rm 0x31415927, c:v-in 2, cpsr 0x00000000 +lsls r1, r2, #2 :: rd 0xc505649c rm 0x31415927, c:v-in 2, cpsr 0x80000000 N +lsls r1, r2, #0xF :: rd 0xac938000 rm 0x31415927, c:v-in 2, cpsr 0x80000000 N +lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +lsls r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +lsls r1, r2, #1 :: rd 0x6282b24e rm 0x31415927, c:v-in 3, cpsr 0x10000000 V +lsls r1, r2, #2 :: rd 0xc505649c rm 0x31415927, c:v-in 3, cpsr 0x90000000 N V +lsls r1, r2, #0xF :: rd 0xac938000 rm 0x31415927, c:v-in 3, cpsr 0x90000000 N V +lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV +LSRS-16 Rd, Rm, imm5 +lsrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +lsrs r1, r2, #1 :: rd 0x18a0ac93 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +lsrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +lsrs r1, r2, #0xF :: rd 0x00006282 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0x40000000 Z +lsrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +lsrs r1, r2, #1 :: rd 0x18a0ac93 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV +lsrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV +lsrs r1, r2, #0xF :: rd 0x00006282 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV +lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0x50000000 Z V +lsrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +lsrs r1, r2, #1 :: rd 0x18a0ac93 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +lsrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +lsrs r1, r2, #0xF :: rd 0x00006282 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 2, cpsr 0x00000000 +lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0x40000000 Z +lsrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +lsrs r1, r2, #1 :: rd 0x18a0ac93 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +lsrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +lsrs r1, r2, #0xF :: rd 0x00006282 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 3, cpsr 0x10000000 V +lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0x50000000 Z V +ASRS-16 Rd, Rm, imm5 +asrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +asrs r1, r2, #1 :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 0, cpsr 0xa0000000 N C +asrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +asrs r1, r2, #0xF :: rd 0xffff2282 rm 0x91415927, c:v-in 0, cpsr 0xa0000000 N C +asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 0, cpsr 0x80000000 N +asrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +asrs r1, r2, #1 :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 1, cpsr 0xb0000000 N CV +asrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV +asrs r1, r2, #0xF :: rd 0xffff2282 rm 0x91415927, c:v-in 1, cpsr 0xb0000000 N CV +asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 1, cpsr 0x90000000 N V +asrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +asrs r1, r2, #1 :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 2, cpsr 0xa0000000 N C +asrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +asrs r1, r2, #0xF :: rd 0xffff2282 rm 0x91415927, c:v-in 2, cpsr 0xa0000000 N C +asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 2, cpsr 0x00000000 +asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 2, cpsr 0x80000000 N +asrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +asrs r1, r2, #1 :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 3, cpsr 0xb0000000 N CV +asrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +asrs r1, r2, #0xF :: rd 0xffff2282 rm 0x91415927, c:v-in 3, cpsr 0xb0000000 N CV +asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 3, cpsr 0x10000000 V +asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 3, cpsr 0x90000000 N V +(T3) ADD{S}.W Rd, Rn, #constT [allegedly] +adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +adds.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x30000000 CV +adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +add.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0x20000000 C +adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0x20000000 C +adds.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV +adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +add.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +adds.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV +adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +add.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 3, cpsr 0x20000000 C +adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 3, cpsr 0x20000000 C +adds.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +add.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) CMP.W Rn, #constT [allegedly] +cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x00000000 +cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x00000000 +cmp.w r1, #255 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmp.w r1, #0 :: rd 0x00000001, c:v-in 0, cpsr 0x20000000 C +cmp.w r1, #1 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmp.w r1, #0 :: rd 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +cmp.w r1, #-1 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000 +cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x90000000 N V +cmp.w r1, #0 :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N +cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x00000000 +cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x00000000 +cmp.w r1, #255 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N +cmp.w r1, #0 :: rd 0x00000001, c:v-in 1, cpsr 0x20000000 C +cmp.w r1, #1 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N +cmp.w r1, #0 :: rd 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +cmp.w r1, #-1 :: rd 0x00000000, c:v-in 1, cpsr 0x00000000 +cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x90000000 N V +cmp.w r1, #0 :: rd 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x80000000 N +cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x00000000 +cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x00000000 +cmp.w r1, #255 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N +cmp.w r1, #0 :: rd 0x00000001, c:v-in 2, cpsr 0x20000000 C +cmp.w r1, #1 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N +cmp.w r1, #0 :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +cmp.w r1, #-1 :: rd 0x00000000, c:v-in 2, cpsr 0x00000000 +cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x90000000 N V +cmp.w r1, #0 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x80000000 N +cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x00000000 +cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x00000000 +cmp.w r1, #255 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N +cmp.w r1, #0 :: rd 0x00000001, c:v-in 3, cpsr 0x20000000 C +cmp.w r1, #1 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N +cmp.w r1, #0 :: rd 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +cmp.w r1, #-1 :: rd 0x00000000, c:v-in 3, cpsr 0x00000000 +cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x90000000 N V +cmp.w r1, #0 :: rd 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x80000000 N +cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +(T3) CMN.W Rn, #constT [allegedly] +cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x20000000 C +cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x20000000 C +cmn.w r1, #255 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn.w r1, #0 :: rd 0x00000001, c:v-in 0, cpsr 0x00000000 +cmn.w r1, #1 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn.w r1, #0 :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N +cmn.w r1, #-1 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N +cmn.w r1, #0 :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N +cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x30000000 CV +cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x20000000 C +cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x20000000 C +cmn.w r1, #255 :: rd 0x00000000, c:v-in 1, cpsr 0x00000000 +cmn.w r1, #0 :: rd 0x00000001, c:v-in 1, cpsr 0x00000000 +cmn.w r1, #1 :: rd 0x00000000, c:v-in 1, cpsr 0x00000000 +cmn.w r1, #0 :: rd 0xffffffff, c:v-in 1, cpsr 0x80000000 N +cmn.w r1, #-1 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N +cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N +cmn.w r1, #0 :: rd 0x80000000, c:v-in 1, cpsr 0x80000000 N +cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x30000000 CV +cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C +cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C +cmn.w r1, #255 :: rd 0x00000000, c:v-in 2, cpsr 0x00000000 +cmn.w r1, #0 :: rd 0x00000001, c:v-in 2, cpsr 0x00000000 +cmn.w r1, #1 :: rd 0x00000000, c:v-in 2, cpsr 0x00000000 +cmn.w r1, #0 :: rd 0xffffffff, c:v-in 2, cpsr 0x80000000 N +cmn.w r1, #-1 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N +cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N +cmn.w r1, #0 :: rd 0x80000000, c:v-in 2, cpsr 0x80000000 N +cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV +cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x30000000 CV +cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x20000000 C +cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x20000000 C +cmn.w r1, #255 :: rd 0x00000000, c:v-in 3, cpsr 0x00000000 +cmn.w r1, #0 :: rd 0x00000001, c:v-in 3, cpsr 0x00000000 +cmn.w r1, #1 :: rd 0x00000000, c:v-in 3, cpsr 0x00000000 +cmn.w r1, #0 :: rd 0xffffffff, c:v-in 3, cpsr 0x80000000 N +cmn.w r1, #-1 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N +cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N +cmn.w r1, #0 :: rd 0x80000000, c:v-in 3, cpsr 0x80000000 N +cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x30000000 CV +cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +(T3) TST.W Rn, #constT [allegedly] +tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x00000000 +tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x00000000 +tst.w r1, #255 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, #0 :: rd 0x00000001, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, #1 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, #0 :: rd 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, #-1 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +tst.w r1, #0 :: rd 0x80000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x00000000 +tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x10000000 V +tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x10000000 V +tst.w r1, #255 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, #0 :: rd 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, #1 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, #0 :: rd 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, #-1 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x70000000 ZCV +tst.w r1, #0 :: rd 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C +tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C +tst.w r1, #255 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +tst.w r1, #0 :: rd 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +tst.w r1, #1 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +tst.w r1, #0 :: rd 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +tst.w r1, #-1 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +tst.w r1, #0 :: rd 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x00000000 +tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x30000000 CV +tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x30000000 CV +tst.w r1, #255 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +tst.w r1, #0 :: rd 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +tst.w r1, #1 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +tst.w r1, #0 :: rd 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +tst.w r1, #-1 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +tst.w r1, #0 :: rd 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +(T3) TEQ.W Rn, #constT [allegedly] +teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x80000000 N +teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x80000000 N +teq.w r1, #255 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000 +teq.w r1, #0 :: rd 0x00000001, c:v-in 0, cpsr 0x00000000 +teq.w r1, #1 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000 +teq.w r1, #0 :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N +teq.w r1, #-1 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N +teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +teq.w r1, #0 :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N +teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x20000000 C +teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x00000000 +teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x90000000 N V +teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x90000000 N V +teq.w r1, #255 :: rd 0x00000000, c:v-in 1, cpsr 0x10000000 V +teq.w r1, #0 :: rd 0x00000001, c:v-in 1, cpsr 0x10000000 V +teq.w r1, #1 :: rd 0x00000000, c:v-in 1, cpsr 0x10000000 V +teq.w r1, #0 :: rd 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +teq.w r1, #-1 :: rd 0x00000000, c:v-in 1, cpsr 0x90000000 N V +teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV +teq.w r1, #0 :: rd 0x80000000, c:v-in 1, cpsr 0x90000000 N V +teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x30000000 CV +teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +teq.w r1, #255 :: rd 0x00000000, c:v-in 2, cpsr 0x20000000 C +teq.w r1, #0 :: rd 0x00000001, c:v-in 2, cpsr 0x20000000 C +teq.w r1, #1 :: rd 0x00000000, c:v-in 2, cpsr 0x20000000 C +teq.w r1, #0 :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +teq.w r1, #-1 :: rd 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +teq.w r1, #0 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x20000000 C +teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x00000000 +teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV +teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV +teq.w r1, #255 :: rd 0x00000000, c:v-in 3, cpsr 0x30000000 CV +teq.w r1, #0 :: rd 0x00000001, c:v-in 3, cpsr 0x30000000 CV +teq.w r1, #1 :: rd 0x00000000, c:v-in 3, cpsr 0x30000000 CV +teq.w r1, #0 :: rd 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +teq.w r1, #-1 :: rd 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +teq.w r1, #0 :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x30000000 CV +teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +(T3) SUB{S}.W Rd, Rn, #constT [allegedly] +subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sub.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sub.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sub.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sub.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) RSB{S}.W Rd, Rn, #constT [allegedly] +rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +rsb.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +rsb.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +rsb.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +rsb.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) ADC{S}.W Rd, Rn, #constT [allegedly] +adcs.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C +adcs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x30000000 CV +adcs.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adc.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0x20000000 C +adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0x20000000 C +adcs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV +adcs.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adc.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +adcs.w r1, r2, #255 :: rd 0x00000100 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, #0 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, #1 :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, #0 :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adc.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #255 :: rd 0x00000100 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #1 :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0 :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x20000000 C +adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 3, cpsr 0x20000000 C +adcs.w r1, r2, #255 :: rd 0x00000100 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, #0 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, #1 :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, #0 :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adc.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #255 :: rd 0x00000100 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #1 :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0 :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) SBC{S}.W Rd, Rn, #constT [allegedly] +sbcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, #0 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +sbcs.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, #0 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sbc.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, #0 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000 Z +sbcs.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, #0 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sbc.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sbc.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sbc.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) AND{S}.W Rd, Rn, #constT [allegedly] +ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +and.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +and.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0x00000000 +and.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +and.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) ORR{S}.W Rd, Rn, #constT [allegedly] +orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +orr.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +orr.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000 +orr.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +orr.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) EOR{S}.W Rd, Rn, #constT [allegedly] +eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +eor.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +eor.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000 +eor.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +eor.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) BIC{S}.W Rd, Rn, #constT [allegedly] +bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +bic.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +bic.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000 +bic.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +bic.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T3) ORN{S}.W Rd, Rn, #constT [allegedly] +orns.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orns.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0x20000000 C +orns.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orns.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, #0x0dd00000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orn.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, #0x0dd00000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orns.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0x30000000 CV +orns.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orns.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, #0x0dd00000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orn.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, #0x0dd00000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +orns.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, #0x0dd00000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +orn.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, #0x0dd00000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +orns.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, #0x0dd00000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +orn.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, #0x0dd00000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ADD{S}.W Rd, Rn, Rm, {shift} +adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +add.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +add.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +add.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +add.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z +add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z +add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000 Z +adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adds.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adds.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x00000000 +adds.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x00000000 +add.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +SUBB{S}.W Rd, Rn, Rm, {shift} +subs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sub.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +subs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sub.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +subs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sub.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +subs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C +subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sub.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +RSB{S}.W Rd, Rn, Rm, {shift} +rsbs.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V +rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsb.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +rsbs.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsb.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +rsbs.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V +rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsb.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +rsbs.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +rsb.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ADC{S}.W Rd, Rn, Rm, {shift} +adcs.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +adc.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV +adcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +adcs.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +adc.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z +adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z +adcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +adcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +adcs.w r1, r2, r3, lsl #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +adc.w r1, r2, r3, lsl #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +adc.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +adcs.w r1, r2, r3, lsl #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +adc.w r1, r2, r3, lsl #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000 +adc.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +adcs.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +adc.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +SBC{S}.W Rd, Rn, Rm, {shift} +sbcs.w r1, r2, r3, lsl #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C +sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +sbc.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV +sbc.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV +sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV +sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbc.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +sbcs.w r1, r2, r3, lsl #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N +sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C +sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z +sbc.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV +sbc.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbc.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +sbcs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +sbc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +sbcs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000 +sbc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C +sbc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N +sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC +sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C +sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +AND{S}.W Rd, Rn, Rm, {shift} +ands.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +and.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +ands.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +and.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +ands.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +and.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +ands.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +and.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +ands.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +and.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +and.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ands.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +and.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +ands.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +and.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000 +ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +ands.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +and.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +ands.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +and.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +ands.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +and.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ands.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +ands.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +and.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ORR{S}.W Rd, Rn, Rm, {shift} +orrs.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +orr.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +orr.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orr.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orr.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orrs.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +orr.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +orr.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orr.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orr.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orrs.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +orr.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +orr.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orrs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orr.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orr.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orrs.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +orr.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +orr.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orrs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orrs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orr.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orr.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +EOR{S}.W Rd, Rn, Rm, {shift} +eors.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +eor.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +eors.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +eor.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +eors.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +eor.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000 +eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +eors.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +eor.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +BIC{S}.W Rd, Rn, Rm, {shift} +bics.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 +bic.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +bic.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bic.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bic.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +bics.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V +bic.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bic.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bic.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +bics.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000 +bic.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000 +bic.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bic.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +bic.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x40000000 Z +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000 +bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +bics.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bic.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +bics.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V +bic.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bic.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +bic.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x50000000 Z V +bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +bics.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +bic.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ORN{S}.W Rd, Rn, Rm, {shift} +orns.w r1, r2, r3, lsl #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0xb1cfd9af rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xb1cfd9af rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, lsl #1 :: rd 0xf1cfd9af rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, lsr #1 :: rd 0xb573fd6f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffd9ef rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #1 :: rd 0x3573fd6f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #15 :: rd 0x3141d9ef rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000 +orn.w r1, r2, r3, lsl #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xf1cfd9af rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xb573fd6f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffffd9ef rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0x3573fd6f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0x3141d9ef rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +orns.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C +orns.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +orns.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +orns.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +orns.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +orns.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +orn.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z +orn.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000 +orn.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orn.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000 +orns.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +orns.w r1, r2, r3, lsl #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0xb1cfd9af rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xb1cfd9af rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, lsl #1 :: rd 0xf1cfd9af rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, lsr #1 :: rd 0xb573fd6f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffd9ef rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #1 :: rd 0x3573fd6f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #15 :: rd 0x3141d9ef rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V +orn.w r1, r2, r3, lsl #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xf1cfd9af rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xb573fd6f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffffd9ef rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0x3573fd6f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0x3141d9ef rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +orns.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +orns.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +orns.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +orns.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +orns.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +orn.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V +orn.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V +orn.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orn.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +orns.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +orns.w r1, r2, r3, lsl #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0xb1cfd9af rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xb1cfd9af rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #1 :: rd 0xf1cfd9af rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsr #1 :: rd 0xb573fd6f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffd9ef rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, asr #1 :: rd 0x3573fd6f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +orns.w r1, r2, r3, asr #15 :: rd 0x3141d9ef rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +orns.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000 +orn.w r1, r2, r3, lsl #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xf1cfd9af rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xb573fd6f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffffd9ef rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0x3573fd6f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0x3141d9ef rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +orns.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +orns.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +orns.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +orns.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +orns.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +orns.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +orn.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orns.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orns.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z +orn.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orns.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orns.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000 +orn.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +orns.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orn.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000 +orns.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +orns.w r1, r2, r3, lsl #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0xb1cfd9af rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xb1cfd9af rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0xf9e7f9f7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xfd73fd6f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0xfffff9ef rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #1 :: rd 0xf1cfd9af rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsr #1 :: rd 0xb573fd6f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffd9ef rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, asr #1 :: rd 0x3573fd6f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #15 :: rd 0x3141d9ef rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V +orn.w r1, r2, r3, lsl #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xf1cfd9af rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xf56bffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xb573fd6f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffffd9ef rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0x79e7f9f7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0x3573fd6f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0x3141d9ef rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V +orns.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +orns.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +orns.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +orns.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +orns.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +orns.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +orn.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V +orn.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orns.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V +orn.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +orns.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orn.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orns.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +orns.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +orns.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orns.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +orn.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +orn.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T?) LSL{S}.W Rd, Rn, Rm +lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x80000000 N +lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0x80000000 N +lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x20000000 C +lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C +lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x60000000 ZC +lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z +lsl.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ +lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x90000000 N V +lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0x90000000 N V +lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x30000000 CV +lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV +lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x70000000 ZCV +lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V +lsl.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V +lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x80000000 N +lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0x80000000 N +lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x20000000 C +lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C +lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x60000000 ZC +lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z +lsl.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC +lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V +lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x90000000 N V +lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0x90000000 N V +lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x30000000 CV +lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV +lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x70000000 ZCV +lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V +lsl.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV +(T?) LSR{S}.W Rd, Rn, Rm +lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C +lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x20000000 C +lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0x20000000 C +lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x00000000 +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0x40000000 Z +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x40000000 Z +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z +lsr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ +lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0x30000000 CV +lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x30000000 CV +lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0x30000000 CV +lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x10000000 V +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0x50000000 Z V +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x50000000 Z V +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V +lsr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V +lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x00000000 +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0x40000000 Z +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x40000000 Z +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z +lsr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC +lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x10000000 V +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0x50000000 Z V +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x50000000 Z V +lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V +lsr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV +(T?) ASR{S}.W Rd, Rn, Rm +asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x20000000 C +asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C +asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x00000000 +asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 0, cpsr 0x80000000 N +asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x40000000 Z +asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 0, cpsr 0xa0000000 N C +asr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ +asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x30000000 CV +asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV +asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x10000000 V +asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 1, cpsr 0x90000000 N V +asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x50000000 Z V +asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV +asr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V +asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x20000000 C +asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C +asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x00000000 +asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 2, cpsr 0x80000000 N +asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x40000000 Z +asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 2, cpsr 0xa0000000 N C +asr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC +asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x30000000 CV +asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV +asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x10000000 V +asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 3, cpsr 0x90000000 N V +asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x50000000 Z V +asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV +asr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV +MVN{S}.W Rd, Rn, shift, and MOV{S}.W ditto +lsls.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +lsrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +lsrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +lsrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +asrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +asrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +asrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +rors.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +rors.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +rors.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +rors.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +lsl.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvns.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +mvn.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsls.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +lsls.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +lsls.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +lsls.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +lsrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +asrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +rors.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +rors.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +rors.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +rors.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +lsl.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvns.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvn.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsls.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +lsls.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +lsls.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +lsrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z +asrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000 ZC +asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z +rors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +rors.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +rors.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +rors.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +lsl.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvns.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0x00000000 +mvns.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvn.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsls.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +lsls.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 0, cpsr 0x20000000 C +lsls.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +lsrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +lsrs.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000 C +lsrs.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +asrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +asrs.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C +asrs.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +asrs.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +rors.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +rors.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C +rors.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +rors.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +lsl.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvns.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +mvns.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +mvns.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +mvns.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +mvns.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 0, cpsr 0x40000000 Z +mvns.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000 +mvns.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +mvns.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N +mvn.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ +lsls.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +lsrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +lsrs.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C +lsrs.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C +lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C +asrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +asrs.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +asrs.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +asrs.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +rors.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rors.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +rors.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +lsl.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +ror.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvns.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C +mvns.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +mvns.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +mvns.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +mvns.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +mvns.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z +mvns.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +mvns.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +mvns.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +mvn.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsls.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +lsrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +lsrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +asrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +asrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +asrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +rors.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +rors.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +rors.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +rors.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsl.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvns.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +mvn.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsls.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +lsls.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +lsls.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +lsls.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +lsrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +asrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +rors.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +rors.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +rors.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +rors.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +lsl.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvns.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvn.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +lsls.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsls.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsls.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +lsrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +asrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV +asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V +rors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +rors.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +rors.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +rors.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsl.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvns.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +mvns.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvn.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsls.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +lsls.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 1, cpsr 0x30000000 CV +lsls.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +lsrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +lsrs.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000 CV +lsrs.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +asrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +asrs.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV +asrs.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +asrs.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +rors.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +rors.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV +rors.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +rors.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +lsl.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvns.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +mvns.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +mvns.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +mvns.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +mvns.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 1, cpsr 0x50000000 Z V +mvns.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V +mvns.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +mvns.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V +mvn.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V +lsls.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +lsrs.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +lsrs.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +asrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +asrs.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +asrs.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +asrs.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +rors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +rors.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +rors.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +rors.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsl.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsr.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +asr.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +ror.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvns.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +mvns.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +mvns.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +mvns.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +mvns.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +mvns.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V +mvns.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +mvns.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +mvns.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +mvn.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsls.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N +lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +lsrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +asrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +asrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +asrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +rors.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +rors.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +lsl.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvns.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x00000000 +mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +mvn.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsls.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +lsls.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +lsls.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +lsls.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +lsrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +asrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +rors.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +rors.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +rors.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +rors.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +lsl.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvns.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N +mvn.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +lsls.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +lsls.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +lsls.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +lsrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000 Z +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000 Z +asrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC +asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000 Z +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000 Z +rors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +rors.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +rors.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +lsl.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvns.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0x00000000 +mvns.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +mvn.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsls.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C +lsls.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C +lsls.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000 +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N +lsrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C +lsrs.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000 +lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000 +asrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C +asrs.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C +asrs.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N +asrs.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N +rors.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000 +rors.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 2, cpsr 0x00000000 +lsl.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvns.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 2, cpsr 0x00000000 +mvns.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 2, cpsr 0x00000000 +mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 2, cpsr 0x40000000 Z +mvns.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N +mvns.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N +mvn.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC +lsls.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsrs.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C +lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C +asrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +asrs.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +asrs.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +asrs.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +rors.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsl.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsr.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +asr.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +ror.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvns.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C +mvns.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvns.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +mvn.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsls.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V +lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +asrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +asrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +asrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +rors.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +rors.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsl.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvns.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V +mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +mvn.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsls.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +lsls.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +lsls.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +lsls.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +lsrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +asrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +rors.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +rors.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +rors.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +rors.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +lsl.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvns.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V +mvn.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +lsls.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +lsls.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V +lsls.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +lsrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +asrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV +asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000 Z V +rors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +rors.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V +rors.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V +lsl.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvns.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0x10000000 V +mvns.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +mvn.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsls.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV +lsls.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV +lsls.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V +lsrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV +lsrs.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V +lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V +asrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV +asrs.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV +asrs.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V +asrs.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V +rors.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V +rors.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V +lsl.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvns.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V +mvns.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V +mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 3, cpsr 0x50000000 Z V +mvns.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V +mvns.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V +mvn.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV +lsls.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsls.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsrs.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +asrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +asrs.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +asrs.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +asrs.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +rors.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsl.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsr.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +asr.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +ror.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvns.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +mvns.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvns.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +mvn.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +(T?) TST.W Rn, Rm, {shift} +tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x20000000 C +tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N +tst.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x40000000 Z +tst.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +tst.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x30000000 CV +tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V +tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V +tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V +tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x90000000 N V +tst.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x50000000 Z V +tst.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V +tst.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x20000000 C +tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +tst.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N +tst.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x40000000 Z +tst.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N +tst.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x30000000 CV +tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V +tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V +tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V +tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V +tst.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x90000000 N V +tst.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x50000000 Z V +tst.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N V +tst.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +(T?) TEQ.W Rn, Rm, {shift} +teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x20000000 C +teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N +teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +teq.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x00000000 +teq.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N +teq.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x00000000 +teq.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x20000000 C +teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x30000000 CV +teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V +teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x90000000 N V +teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V +teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +teq.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x10000000 V +teq.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x90000000 N V +teq.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x10000000 V +teq.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x30000000 CV +teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x20000000 C +teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N +teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +teq.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x00000000 +teq.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N +teq.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x00000000 +teq.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x30000000 CV +teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V +teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x90000000 N V +teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V +teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000 V +teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000 V +teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000 V +teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000 V +teq.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x10000000 V +teq.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x90000000 N V +teq.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x10000000 V +teq.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +(T?) CMP.W Rn, Rm, {shift} +cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N +cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N +cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N +cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C +cmp.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x20000000 C +cmp.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x30000000 CV +cmp.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +cmp.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x20000000 C +cmp.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 0, cpsr 0x60000000 ZC +cmp.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0x60000000 ZC +cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N +cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N +cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000 +cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N +cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C +cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C +cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C +cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C +cmp.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x20000000 C +cmp.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x30000000 CV +cmp.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +cmp.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x20000000 C +cmp.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 1, cpsr 0x60000000 ZC +cmp.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 1, cpsr 0x60000000 ZC +cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N +cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N +cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N +cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +cmp.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x20000000 C +cmp.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x30000000 CV +cmp.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N +cmp.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +cmp.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 2, cpsr 0x60000000 ZC +cmp.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 2, cpsr 0x60000000 ZC +cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N +cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N +cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000 +cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N +cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C +cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C +cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C +cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C +cmp.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x20000000 C +cmp.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x30000000 CV +cmp.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N +cmp.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x20000000 C +cmp.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 3, cpsr 0x60000000 ZC +cmp.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 3, cpsr 0x60000000 ZC +(T?) CMN.W Rn, Rm, {shift} +cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N +cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000 +cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +cmn.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x30000000 CV +cmn.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N +cmn.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x30000000 CV +cmn.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x30000000 CV +cmn.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 0, cpsr 0x00000000 +cmn.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0x90000000 N V +cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000 +cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000 +cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N +cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000 +cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000 +cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000 +cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000 +cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000 +cmn.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x30000000 CV +cmn.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x80000000 N +cmn.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV +cmn.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x30000000 CV +cmn.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 1, cpsr 0x00000000 +cmn.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 1, cpsr 0x90000000 N V +cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N +cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000 +cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000 +cmn.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x30000000 CV +cmn.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N +cmn.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV +cmn.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x30000000 CV +cmn.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 2, cpsr 0x00000000 +cmn.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 2, cpsr 0x90000000 N V +cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000 +cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000 +cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N +cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000 +cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000 +cmn.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x30000000 CV +cmn.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x80000000 N +cmn.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV +cmn.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +cmn.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 3, cpsr 0x00000000 +cmn.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 3, cpsr 0x90000000 N V +(T2) MOV{S}.W Rd, #constT +movs.w r9, 0x00000000 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z +movs.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x43434343 :: rd 0x43434343, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x93939393 :: rd 0x93939393, c:v-in 0, cpsr 0x80000000 N +movs.w r9, 0x93000000 :: rd 0x93000000, c:v-in 0, cpsr 0xa0000000 N C +movs.w r9, 0x43000000 :: rd 0x43000000, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x09300000 :: rd 0x09300000, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x04300000 :: rd 0x04300000, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x00930000 :: rd 0x00930000, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x00430000 :: rd 0x00430000, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x00000930 :: rd 0x00000930, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x00000430 :: rd 0x00000430, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x00000093 :: rd 0x00000093, c:v-in 0, cpsr 0x00000000 +movs.w r9, 0x00000043 :: rd 0x00000043, c:v-in 0, cpsr 0x00000000 +mov.w r9, 0x00000000 :: rd 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x43434343 :: rd 0x43434343, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x93939393 :: rd 0x93939393, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x93000000 :: rd 0x93000000, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x43000000 :: rd 0x43000000, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x09300000 :: rd 0x09300000, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x04300000 :: rd 0x04300000, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x00930000 :: rd 0x00930000, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x00430000 :: rd 0x00430000, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x00000930 :: rd 0x00000930, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x00000430 :: rd 0x00000430, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x00000093 :: rd 0x00000093, c:v-in 0, cpsr 0xc0000000 NZ +mov.w r9, 0x00000043 :: rd 0x00000043, c:v-in 0, cpsr 0xc0000000 NZ +movs.w r9, 0x00000000 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +movs.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x43434343 :: rd 0x43434343, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x93939393 :: rd 0x93939393, c:v-in 1, cpsr 0x90000000 N V +movs.w r9, 0x93000000 :: rd 0x93000000, c:v-in 1, cpsr 0xb0000000 N CV +movs.w r9, 0x43000000 :: rd 0x43000000, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x09300000 :: rd 0x09300000, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x04300000 :: rd 0x04300000, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x00930000 :: rd 0x00930000, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x00430000 :: rd 0x00430000, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x00000930 :: rd 0x00000930, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x00000430 :: rd 0x00000430, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x00000093 :: rd 0x00000093, c:v-in 1, cpsr 0x10000000 V +movs.w r9, 0x00000043 :: rd 0x00000043, c:v-in 1, cpsr 0x10000000 V +mov.w r9, 0x00000000 :: rd 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x43434343 :: rd 0x43434343, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x93939393 :: rd 0x93939393, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x93000000 :: rd 0x93000000, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x43000000 :: rd 0x43000000, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x09300000 :: rd 0x09300000, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x04300000 :: rd 0x04300000, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x00930000 :: rd 0x00930000, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x00430000 :: rd 0x00430000, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x00000930 :: rd 0x00000930, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x00000430 :: rd 0x00000430, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x00000093 :: rd 0x00000093, c:v-in 1, cpsr 0xd0000000 NZ V +mov.w r9, 0x00000043 :: rd 0x00000043, c:v-in 1, cpsr 0xd0000000 NZ V +movs.w r9, 0x00000000 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +movs.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 2, cpsr 0x20000000 C +movs.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 2, cpsr 0x20000000 C +movs.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 2, cpsr 0x20000000 C +movs.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 2, cpsr 0x20000000 C +movs.w r9, 0x43434343 :: rd 0x43434343, c:v-in 2, cpsr 0x20000000 C +movs.w r9, 0x93939393 :: rd 0x93939393, c:v-in 2, cpsr 0xa0000000 N C +movs.w r9, 0x93000000 :: rd 0x93000000, c:v-in 2, cpsr 0xa0000000 N C +movs.w r9, 0x43000000 :: rd 0x43000000, c:v-in 2, cpsr 0x00000000 +movs.w r9, 0x09300000 :: rd 0x09300000, c:v-in 2, cpsr 0x00000000 +movs.w r9, 0x04300000 :: rd 0x04300000, c:v-in 2, cpsr 0x00000000 +movs.w r9, 0x00930000 :: rd 0x00930000, c:v-in 2, cpsr 0x00000000 +movs.w r9, 0x00430000 :: rd 0x00430000, c:v-in 2, cpsr 0x00000000 +movs.w r9, 0x00000930 :: rd 0x00000930, c:v-in 2, cpsr 0x00000000 +movs.w r9, 0x00000430 :: rd 0x00000430, c:v-in 2, cpsr 0x00000000 +movs.w r9, 0x00000093 :: rd 0x00000093, c:v-in 2, cpsr 0x20000000 C +movs.w r9, 0x00000043 :: rd 0x00000043, c:v-in 2, cpsr 0x20000000 C +mov.w r9, 0x00000000 :: rd 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x43434343 :: rd 0x43434343, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x93939393 :: rd 0x93939393, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x93000000 :: rd 0x93000000, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x43000000 :: rd 0x43000000, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x09300000 :: rd 0x09300000, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x04300000 :: rd 0x04300000, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x00930000 :: rd 0x00930000, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x00430000 :: rd 0x00430000, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x00000930 :: rd 0x00000930, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x00000430 :: rd 0x00000430, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x00000093 :: rd 0x00000093, c:v-in 2, cpsr 0xe0000000 NZC +mov.w r9, 0x00000043 :: rd 0x00000043, c:v-in 2, cpsr 0xe0000000 NZC +movs.w r9, 0x00000000 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +movs.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 3, cpsr 0x30000000 CV +movs.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 3, cpsr 0x30000000 CV +movs.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 3, cpsr 0x30000000 CV +movs.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 3, cpsr 0x30000000 CV +movs.w r9, 0x43434343 :: rd 0x43434343, c:v-in 3, cpsr 0x30000000 CV +movs.w r9, 0x93939393 :: rd 0x93939393, c:v-in 3, cpsr 0xb0000000 N CV +movs.w r9, 0x93000000 :: rd 0x93000000, c:v-in 3, cpsr 0xb0000000 N CV +movs.w r9, 0x43000000 :: rd 0x43000000, c:v-in 3, cpsr 0x10000000 V +movs.w r9, 0x09300000 :: rd 0x09300000, c:v-in 3, cpsr 0x10000000 V +movs.w r9, 0x04300000 :: rd 0x04300000, c:v-in 3, cpsr 0x10000000 V +movs.w r9, 0x00930000 :: rd 0x00930000, c:v-in 3, cpsr 0x10000000 V +movs.w r9, 0x00430000 :: rd 0x00430000, c:v-in 3, cpsr 0x10000000 V +movs.w r9, 0x00000930 :: rd 0x00000930, c:v-in 3, cpsr 0x10000000 V +movs.w r9, 0x00000430 :: rd 0x00000430, c:v-in 3, cpsr 0x10000000 V +movs.w r9, 0x00000093 :: rd 0x00000093, c:v-in 3, cpsr 0x30000000 CV +movs.w r9, 0x00000043 :: rd 0x00000043, c:v-in 3, cpsr 0x30000000 CV +mov.w r9, 0x00000000 :: rd 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x43434343 :: rd 0x43434343, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x93939393 :: rd 0x93939393, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x93000000 :: rd 0x93000000, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x43000000 :: rd 0x43000000, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x09300000 :: rd 0x09300000, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x04300000 :: rd 0x04300000, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x00930000 :: rd 0x00930000, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x00430000 :: rd 0x00430000, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x00000930 :: rd 0x00000930, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x00000430 :: rd 0x00000430, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x00000093 :: rd 0x00000093, c:v-in 3, cpsr 0xf0000000 NZCV +mov.w r9, 0x00000043 :: rd 0x00000043, c:v-in 3, cpsr 0xf0000000 NZCV +(T2) MVN{S}.W Rd, #constT +mvns.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 0, cpsr 0x00000000 +mvns.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 0, cpsr 0x20000000 C +mvns.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 0, cpsr 0x80000000 N +mvns.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 0, cpsr 0x80000000 N +mvn.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 0, cpsr 0xc0000000 NZ +mvn.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 0, cpsr 0xc0000000 NZ +mvns.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 1, cpsr 0x10000000 V +mvns.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 1, cpsr 0x30000000 CV +mvns.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 1, cpsr 0x90000000 N V +mvns.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 1, cpsr 0x90000000 N V +mvn.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 1, cpsr 0xd0000000 NZ V +mvn.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 1, cpsr 0xd0000000 NZ V +mvns.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 2, cpsr 0x20000000 C +mvns.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 2, cpsr 0x20000000 C +mvns.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 2, cpsr 0x80000000 N +mvns.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 2, cpsr 0x80000000 N +mvns.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 2, cpsr 0x80000000 N +mvns.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 2, cpsr 0x80000000 N +mvns.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 2, cpsr 0x80000000 N +mvns.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 2, cpsr 0x80000000 N +mvns.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 2, cpsr 0x80000000 N +mvns.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 2, cpsr 0xa0000000 N C +mvns.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 2, cpsr 0xa0000000 N C +mvn.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 2, cpsr 0xe0000000 NZC +mvn.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 2, cpsr 0xe0000000 NZC +mvns.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 3, cpsr 0x30000000 CV +mvns.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 3, cpsr 0x30000000 CV +mvns.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 3, cpsr 0x90000000 N V +mvns.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 3, cpsr 0x90000000 N V +mvns.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 3, cpsr 0x90000000 N V +mvns.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 3, cpsr 0x90000000 N V +mvns.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 3, cpsr 0x90000000 N V +mvns.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 3, cpsr 0x90000000 N V +mvns.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 3, cpsr 0x90000000 N V +mvns.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 3, cpsr 0xb0000000 N CV +mvns.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 3, cpsr 0xb0000000 N CV +mvn.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 3, cpsr 0xf0000000 NZCV +mvn.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 3, cpsr 0xf0000000 NZCV +(T1) RBIT Rd, Rm +rbit r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x00000001 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0xe49a828c rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x46a82828 rm 0x14141562, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0xf89c17d5 rm 0xabe8391f, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x01551409 rm 0x9028aa80, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0xb63f8b57 rm 0xead1fc6d, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0xaa3193ac rm 0x35c98c55, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0xd78f52ca rm 0x534af1eb, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x10d88aa2 rm 0x45511b08, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x8efee009 rm 0x90077f71, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0xd215317b rm 0xde8ca84b, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x5bb05ec7 rm 0xe37a0dda, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0xd2bc1da7 rm 0xe5b83d4b, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x3728b6dd rm 0xbb6d14ec, c:v-in 0, cpsr 0xc0000000 NZ +rbit r0, r1 :: rd 0x933c1916 rm 0x68983cc9, c:v-in 0, cpsr 0xc0000000 NZ +(T1) REV Rd, Rm ------------ +rev r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x00000080 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x01000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x27594131 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x62151414 rm 0x14141562, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x1f39e8ab rm 0xabe8391f, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x80aa2890 rm 0x9028aa80, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x6dfcd1ea rm 0xead1fc6d, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x558cc935 rm 0x35c98c55, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0xebf14a53 rm 0x534af1eb, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x081b5145 rm 0x45511b08, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x717f0790 rm 0x90077f71, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x4ba88cde rm 0xde8ca84b, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0xda0d7ae3 rm 0xe37a0dda, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0x4b3db8e5 rm 0xe5b83d4b, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0xec146dbb rm 0xbb6d14ec, c:v-in 0, cpsr 0xc0000000 NZ +rev r0, r1 :: rd 0xc93c9868 rm 0x68983cc9, c:v-in 0, cpsr 0xc0000000 NZ +(T2) REV Rd, Rm ------------ +rev r8, r9 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x00000080 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x01000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x27594131 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x62151414 rm 0x14141562, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x1f39e8ab rm 0xabe8391f, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x80aa2890 rm 0x9028aa80, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x6dfcd1ea rm 0xead1fc6d, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x558cc935 rm 0x35c98c55, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0xebf14a53 rm 0x534af1eb, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x081b5145 rm 0x45511b08, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x717f0790 rm 0x90077f71, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x4ba88cde rm 0xde8ca84b, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0xda0d7ae3 rm 0xe37a0dda, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0x4b3db8e5 rm 0xe5b83d4b, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0xec146dbb rm 0xbb6d14ec, c:v-in 0, cpsr 0xc0000000 NZ +rev r8, r9 :: rd 0xc93c9868 rm 0x68983cc9, c:v-in 0, cpsr 0xc0000000 NZ +(T1) REV16 Rd, Rm ------------ +rev16 r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x00800000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x00000100 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x41312759 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x14146215 rm 0x14141562, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0xe8ab1f39 rm 0xabe8391f, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x289080aa rm 0x9028aa80, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0xd1ea6dfc rm 0xead1fc6d, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0xc935558c rm 0x35c98c55, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x4a53ebf1 rm 0x534af1eb, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x5145081b rm 0x45511b08, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x0790717f rm 0x90077f71, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x8cde4ba8 rm 0xde8ca84b, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x7ae3da0d rm 0xe37a0dda, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0xb8e54b3d rm 0xe5b83d4b, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x6dbbec14 rm 0xbb6d14ec, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r0, r1 :: rd 0x9868c93c rm 0x68983cc9, c:v-in 0, cpsr 0xc0000000 NZ +(T2) REV16 Rd, Rm ------------ +rev16 r8, r9 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x00800000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x00000100 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x41312759 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x14146215 rm 0x14141562, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0xe8ab1f39 rm 0xabe8391f, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x289080aa rm 0x9028aa80, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0xd1ea6dfc rm 0xead1fc6d, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0xc935558c rm 0x35c98c55, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x4a53ebf1 rm 0x534af1eb, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x5145081b rm 0x45511b08, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x0790717f rm 0x90077f71, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x8cde4ba8 rm 0xde8ca84b, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x7ae3da0d rm 0xe37a0dda, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0xb8e54b3d rm 0xe5b83d4b, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x6dbbec14 rm 0xbb6d14ec, c:v-in 0, cpsr 0xc0000000 NZ +rev16 r8, r9 :: rd 0x9868c93c rm 0x68983cc9, c:v-in 0, cpsr 0xc0000000 NZ +------------ NOP (begin) ------------ +nop +nop.w +------------ NOP (end) ------------ +MOV +mov r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +cpy r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mov r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mov r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N +movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z +movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000 +movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000 +movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000 Z +movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N +movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V +movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V +movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z +movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N +movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC +movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C +movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x00000000 +movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x40000000 Z +movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N +movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV +movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV +MVN +mvn r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000 +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x10000000 V +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 2, cpsr 0x20000000 C +mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV +ADD +adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N +adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0x90000000 N V +adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, c:v-in 0, cpsr 0x30000000 CV +adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +ADC +adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z +adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z +LSL +lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +LSLS +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0x60000000 ZC +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0x80000000 N +lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 0, cpsr 0x80000000 N +lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 0, cpsr 0x60000000 ZC +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV +lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0x70000000 ZCV +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000 Z V +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000 Z V +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000 Z V +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0x90000000 N V +lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 1, cpsr 0x90000000 N V +lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 1, cpsr 0x70000000 ZCV +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0x60000000 ZC +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000 Z +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xa0000000 N C +lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 2, cpsr 0x80000000 N +lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 2, cpsr 0x60000000 ZC +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV +lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0x70000000 ZCV +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000 Z V +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000 Z V +lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000 Z V +lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xb0000000 N CV +lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V +lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 3, cpsr 0x90000000 N V +lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 3, cpsr 0x70000000 ZCV +LSL immediate +lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V +lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC +lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV +LSLS immediate +lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000 +lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0x80000000 N +lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 0, cpsr 0x60000000 ZC +lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V +lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V +lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 1, cpsr 0x70000000 ZCV +lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C +lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000 +lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0x80000000 N +lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 2, cpsr 0x60000000 ZC +lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV +lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V +lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V +lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 3, cpsr 0x70000000 ZCV +LSR +lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ +LSRS +lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0x60000000 ZC +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0x30000000 CV +lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0x30000000 CV +lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0x30000000 CV +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0x70000000 ZCV +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000 Z V +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000 Z V +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000 Z V +lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0x20000000 C +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0x60000000 ZC +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000 Z +lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0x30000000 CV +lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0x30000000 CV +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0x70000000 ZCV +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000 Z V +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000 Z V +lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000 Z V +LSR immediate +lsr r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ +lsr r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ +LSRS immediate +lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C +lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C +lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC +lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0x00000000 +lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x60000000 ZC +lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x40000000 Z +lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV +lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV +lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 1, cpsr 0x10000000 V +lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x70000000 ZCV +lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x50000000 Z V +lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C +lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C +lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC +lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 2, cpsr 0x00000000 +lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x60000000 ZC +lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x40000000 Z +lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV +lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV +lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 3, cpsr 0x10000000 V +lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x70000000 ZCV +lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x50000000 Z V +ASR +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 1, cpsr 0xd0000000 NZ V +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 2, cpsr 0xe0000000 NZC +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV +asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 3, cpsr 0xf0000000 NZCV +ASRS +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0x80000000 N +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 0, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 0, cpsr 0x60000000 ZC +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0x90000000 N V +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 1, cpsr 0x30000000 CV +asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 1, cpsr 0x30000000 CV +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 1, cpsr 0x70000000 ZCV +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 1, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 1, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 2, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 2, cpsr 0x60000000 ZC +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 2, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 2, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV +asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 3, cpsr 0x30000000 CV +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 3, cpsr 0x70000000 ZCV +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 3, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 3, cpsr 0x30000000 CV +asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 0, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 0, cpsr 0x60000000 ZC +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 0, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 1, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 1, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 1, cpsr 0x70000000 ZCV +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 1, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C +asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 2, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 2, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 2, cpsr 0x00000000 +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 2, cpsr 0x60000000 ZC +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 2, cpsr 0x40000000 Z +asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV +asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 3, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 3, cpsr 0x10000000 V +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 3, cpsr 0x70000000 ZCV +asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 3, cpsr 0x50000000 Z V +asrs r0, r1, r2 :: rd 0xc0000000 rm 0x80000001, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, r2 :: rd 0xe0000000 rm 0x80000001, rn 0x00000002, c:v-in 0, cpsr 0x80000000 N +ASR immediate +asr r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ +asr r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ +ASRS immediate +asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N +asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C +asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000 +asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C +asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC +asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z +asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0x00000000 +asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x60000000 ZC +asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x40000000 Z +asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V +asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV +asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V +asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV +asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV +asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V +asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 1, cpsr 0x10000000 V +asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x70000000 ZCV +asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x50000000 Z V +asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C +asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C +asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC +asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x40000000 Z +asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 2, cpsr 0x00000000 +asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x60000000 ZC +asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x40000000 Z +asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV +asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV +asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV +asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x50000000 Z V +asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 3, cpsr 0x10000000 V +asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x70000000 ZCV +asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x50000000 Z V +MUL +mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ +mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ +MLA +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mla r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mla r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +MLS +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mls r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mls r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +mls r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +UMULL +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +umull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ +umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +SMULL +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +smull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ +smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +CLZ +clz r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +clz r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +clz r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ +clz r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +clz r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V +clz r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V +clz r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V +clz r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V +clz r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC +clz r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC +clz r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC +clz r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC +clz r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV +clz r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV +clz r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV +clz r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV +extend instructions +uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +uxth r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +uxth r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ +uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +sxth r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sxth r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, c:v-in 0, cpsr 0xc0000000 NZ +sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ +sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, c:v-in 0, cpsr 0xc0000000 NZ +sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, c:v-in 0, cpsr 0xc0000000 NZ +sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, c:v-in 0, cpsr 0xc0000000 NZ +uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, c:v-in 0, cpsr 0xc0000000 NZ +------------ BFI ------------ +bfi r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfi r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +------------ BFC ------------ +bfc r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +bfc r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ +------------ SBFX ------------ +sbfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +sbfx r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +------------ UBFX ------------ +ubfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +ubfx r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ +------------ SMULL{B,T}{B,T} ------------ +smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, c:v-in 0, cpsr 0xc0000000 NZ +smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, c:v-in 0, cpsr 0xc0000000 NZ +smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, c:v-in 0, cpsr 0xc0000000 NZ +smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, c:v-in 0, cpsr 0xc0000000 NZ +smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, c:v-in 0, cpsr 0xc0000000 NZ +------------ SXTAB ------------ +sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ +sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ +sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ +sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ +------------ UXTAB ------------ +uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ +uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ +uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ +uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ +------------ SXTAH ------------ +sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +sxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +sxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ +sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ +sxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ +sxtah r0, r1, r2, ROR #0 :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ +------------ UXTAH ------------ +uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +uxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +uxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ +uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ +uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ +uxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ +uxtah r0, r1, r2, ROR #0 :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ diff --git a/none/tests/arm/v6intThumb.vgtest b/none/tests/arm/v6intThumb.vgtest new file mode 100644 index 0000000..362326d --- /dev/null +++ b/none/tests/arm/v6intThumb.vgtest @@ -0,0 +1,2 @@ +prog: v6intThumb +vgopts: -q diff --git a/none/tests/arm/v6media.c b/none/tests/arm/v6media.c new file mode 100644 index 0000000..af2ae8b --- /dev/null +++ b/none/tests/arm/v6media.c @@ -0,0 +1,4093 @@ + +/* How to compile: + gcc -g -Wall -mcpu=cortex-a8 -o v6mediaA -marm none/tests/arm/v6media.c + or + gcc -g -Wall -mcpu=cortex-a8 -o v6mediaT -mthumb none/tests/arm/v6media.c +*/ + +#include + +static int gen_cin(cin) +{ + int r = ((cin & 1) ? (1<<29) : 0); + //r |= (1 << 31) | (1 << 30); + return r; +} + +/* test macros to generate and output the result of a single instruction */ +#define TESTINST2(instruction, RMval, RD, RM, carryin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_fs, %3;" \ + "mov " #RM ",%2;" \ + /* set #RD to 0x55555555 so we can see which parts get overwritten */ \ + "mov " #RD ", #0x55" "\n\t" \ + "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \ + "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (gen_cin(carryin)) \ + : #RD, #RM, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \ + instruction, out, RMval, \ + carryin ? 1 : 0, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ', \ + ((1<<27) & cpsr) ? 'Q' : ' ', \ + (cpsr >> 19) & 1, (cpsr >> 18) & 1, (cpsr >> 17) & 1, (cpsr >> 16) & 1 \ + ); \ +} + +#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_fs, %4;" \ + "mov " #RM ",%2;" \ + "mov " #RN ",%3;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (RNval), "r" (gen_cin(carryin)) \ + : #RD, #RM, #RN, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \ + instruction, out, RMval, RNval, \ + carryin ? 1 : 0, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ', \ + ((1<<27) & cpsr) ? 'Q' : ' ', \ + (cpsr >> 19) & 1, (cpsr >> 18) & 1, (cpsr >> 17) & 1, (cpsr >> 16) & 1 \ + ); \ +} + +#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \ +{ \ + unsigned int out; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_fs, %5;" \ + "mov " #RM ",%2;" \ + "mov " #RN ",%3;" \ + "mov " #RS ",%4;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mrs %1,cpsr;" \ + : "=&r" (out), "=&r" (cpsr) \ + : "r" (RMval), "r" (RNval), "r" (RSval), "r" (gen_cin(carryin)) \ + : #RD, #RM, #RN, #RS, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \ + instruction, out, RMval, RNval, RSval, \ + carryin ? 1 : 0, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ', \ + ((1<<27) & cpsr) ? 'Q' : ' ', \ + (cpsr >> 19) & 1, (cpsr >> 18) & 1, (cpsr >> 17) & 1, (cpsr >> 16) & 1 \ + ); \ +} + +#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ +{ \ + unsigned int out; \ + unsigned int out2; \ + unsigned int cpsr; \ +\ + __asm__ volatile( \ + "msr cpsr_fs, %7;" \ + "mov " #RD ",%3;" \ + "mov " #RD2 ",%4;" \ + "mov " #RM ",%5;" \ + "mov " #RS ",%6;" \ + instruction ";" \ + "mov %0," #RD ";" \ + "mov %1," #RD2 ";" \ + "mrs %2,cpsr;" \ + : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \ + : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (gen_cin(carryin)) \ + : #RD, #RD2, #RM, #RS, "cc", "memory" \ + ); \ + printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \ + instruction, out, out2, RMval, RSval, \ + carryin ? 1 : 0, \ + cpsr & 0xffff0000, \ + ((1<<31) & cpsr) ? 'N' : ' ', \ + ((1<<30) & cpsr) ? 'Z' : ' ', \ + ((1<<29) & cpsr) ? 'C' : ' ', \ + ((1<<28) & cpsr) ? 'V' : ' ', \ + ((1<<27) & cpsr) ? 'Q' : ' ', \ + (cpsr >> 19) & 1, (cpsr >> 18) & 1, (cpsr >> 17) & 1, (cpsr >> 16) & 1 \ + ); \ +} + +/* helpers */ +#define TESTCARRY { int c = 0; for (c = 0; c < 2; c++) { +#define TESTCARRYEND }} + + + + +int main(int argc, char **argv) +{ + printf("MUL\n"); + TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); + TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); + +#if 0 + printf("MULS\n"); + TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); + TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); +#endif + + printf("MLA\n"); + TESTINST4("mla r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mla r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); + +#if 0 + printf("MLAS\n"); + TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); +#endif + + printf("MLS\n"); + TESTINST4("mls r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); + TESTINST4("mls r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); + + printf("UMULL\n"); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#if 0 + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif + printf("SMULL\n"); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#if 0 + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif + + printf("UMLAL\n"); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#if 0 + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif + + printf("SMLAL\n"); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#if 0 + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0); + TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0); +#endif + + printf("CLZ\n"); + TESTCARRY + TESTINST2("clz r0, r1", 0, r0, r1, c); + TESTINST2("clz r0, r1", 1, r0, r1, c); + TESTINST2("clz r0, r1", 0x10, r0, r1, c); + TESTINST2("clz r0, r1", 0xffffffff, r0, r1, c); + TESTCARRYEND + + printf("extend instructions\n"); + TESTINST2("uxtb r0, r1", 0, r0, r1, 0); + TESTINST2("uxtb r0, r1", 1, r0, r1, 0); + TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0); + TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0, r0, r1, 0); + TESTINST2("sxtb r0, r1", 1, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0); + TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0); + + TESTINST2("uxth r0, r1", 0, r0, r1, 0); + TESTINST2("uxth r0, r1", 1, r0, r1, 0); + TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0); + TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0, r0, r1, 0); + TESTINST2("sxth r0, r1", 1, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0); + TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0); + + TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0); + TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0); + + TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0); + TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0); + + printf("------------ BFI ------------\n"); + /* bfi rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */ + TESTINST2("bfi r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfi r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfi r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("bfi r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfi r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfi r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfi r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0); + + printf("------------ BFC ------------\n"); + /* bfi rDst, #lsb-in-dst, #number-of-bits-to-copy */ + TESTINST2("bfc r0, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfc r0, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("bfc r0, #2, #11", 0xAAAAAAAA, r0, r1, 0); + + TESTINST2("bfc r0, #19, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #20, #11", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #21, #11", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfc r0, #0, #32", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #1, #31", 0xFFFFFFFF, r0, r1, 0); + + TESTINST2("bfc r0, #29, #3", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #30, #2", 0xFFFFFFFF, r0, r1, 0); + TESTINST2("bfc r0, #31, #1", 0xFFFFFFFF, r0, r1, 0); + + printf("------------ SBFX ------------\n"); + /* sbfx rDst, rSrc, #lsb, #width */ + TESTINST2("sbfx r0, r1, #0, #1", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #0, #1", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000002, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #1", 0x00000003, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #0, #2", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #0, #2", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000000, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000001, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000002, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #2", 0x00000003, r0, r1, 0); + + TESTINST2("sbfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("sbfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0); + + printf("------------ UBFX ------------\n"); + /* ubfx rDst, rSrc, #lsb, #width */ + TESTINST2("ubfx r0, r1, #0, #1", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #0, #1", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000002, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #1", 0x00000003, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #0, #2", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #0, #2", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000000, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000001, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000002, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #2", 0x00000003, r0, r1, 0); + + TESTINST2("ubfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0); + TESTINST2("ubfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0); + + printf("------------ SMUL{B,T}{B,T} ------------\n"); + /* SMULbb rD, rN, rM */ + TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0); +TESTINST3("smulbb r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0); + /* SMULtt rD, rN, rM */ + TESTINST3("smultt r0, r1, r2", 0x00000003, 0x00000004, r0, r1, r2, 0); + TESTINST3("smultt r0, r1, r2", 0x00010003, 0x00020004, r0, r1, r2, 0); + TESTINST3("smultt r0, r1, r2", 0x80010003, 0x7fff0004, r0, r1, r2, 0); + TESTINST3("smultt r0, r1, r2", 0x7fff0003, 0x7fff0004, r0, r1, r2, 0); + TESTINST3("smultt r0, r1, r2", 0xffff0003, 0xffff0004, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0); +TESTINST3("smultt r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0); + /* SMULtb rD, rN, rM */ + TESTINST3("smultb r0, r1, r2", 0x00000003, 0x00040000, r0, r1, r2, 0); + TESTINST3("smultb r0, r1, r2", 0x00010003, 0x00040002, r0, r1, r2, 0); + TESTINST3("smultb r0, r1, r2", 0x80010003, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smultb r0, r1, r2", 0x7fff0003, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smultb r0, r1, r2", 0xffff0003, 0x0004ffff, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0); +TESTINST3("smultb r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0); + /* SMULbt rD, rN, rM */ + TESTINST3("smulbt r0, r1, r2", 0x00030000, 0x00000004, r0, r1, r2, 0); + TESTINST3("smulbt r0, r1, r2", 0x00030001, 0x00020004, r0, r1, r2, 0); + TESTINST3("smulbt r0, r1, r2", 0x00038001, 0x7fff0004, r0, r1, r2, 0); + TESTINST3("smulbt r0, r1, r2", 0x00037fff, 0x7fff0004, r0, r1, r2, 0); + TESTINST3("smulbt r0, r1, r2", 0x0003ffff, 0xffff0004, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0); +TESTINST3("smulbt r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0); + + printf("-------------- SMULW{B,T} --------------\n"); + /* SMULWB rD, rN, rM : Rn x Rm[31..16] */ + TESTINST3("smulwb r0, r1, r2", 0x00000003, 0x00020004, r0, r1, r2, 0); + TESTINST3("smulwb r0, r1, r2", 0x00010003, 0x47ff0004, r0, r1, r2, 0); + TESTINST3("smulwb r0, r1, r2", 0x80010003, 0x7fff0004, r0, r1, r2, 0); + TESTINST3("smulwb r0, r1, r2", 0x7fff0003, 0x7fff0004, r0, r1, r2, 0); + TESTINST3("smulwb r0, r1, r2", 0xffff0003, 0xffff0004, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0); +TESTINST3("smulwb r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0); + /* SMULWT rD, rN, rM - Rn x Rm[15.. 0] */ + TESTINST3("smulwt r0, r1, r2", 0x00000003, 0x00040000, r0, r1, r2, 0); + TESTINST3("smulwt r0, r1, r2", 0x00010003, 0x00040002, r0, r1, r2, 0); + TESTINST3("smulwt r0, r1, r2", 0x80010003, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smulwt r0, r1, r2", 0x7fff0003, 0x00047fff, r0, r1, r2, 0); + TESTINST3("smulwt r0, r1, r2", 0xffff0003, 0x0004ffff, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0); +TESTINST3("smulwt r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0); + + printf("------------ PKHBT / PKHTB ------------\n"); + /* PKHBT */ + TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhbt r0, r1, r2, lsl #22", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhbt r0, r1, r2, lsl #31", 0x11223344, 0x55667788, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0x50c28082, 0xc1553709, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0x17962e8f, 0x69ec0212, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0xc57243b7, 0x03fa9bb5, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0x7eb226ac, 0xf52e9fbf, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0xbce0f026, 0x7fcbe5a9, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0xa5757252, 0x2dd01366, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0xf4a477c1, 0x5e4b1cbf, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0x76723a21, 0x464a21cc, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0x74d01105, 0xe8108f1b, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2", 0xc1273e2c, 0xcd90d604, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #8", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #12", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #24", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #31", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #8", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #12", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #24", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #31", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #8", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #12", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #24", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #31", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #0", 0xd5dc5407, 0xf87b961e, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #1", 0xd65db979, 0xc61b323b, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #2", 0xa3268abe, 0xed2cbf78, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #3", 0xbf73f0a5, 0x2fb714c9, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x281703ed, 0x925ef472, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #8", 0xeaa652c7, 0x137741f4, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #12", 0x71fbde8b, 0xdba5bd25, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x884c0ad8, 0xc00b821a, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #24", 0xe1bb8606, 0x58293969, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #31", 0xa3cfd624, 0x6077fb1f, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x40b094e2, 0x17913309, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x5388b5cd, 0x86582032, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x5de41558, 0xccfa1c7e, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x23ba1b46, 0x4437983c, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x48d06549, 0xa9085781, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #8", 0xc6b4ac58, 0xb2aead21, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #12", 0xc2bdf597, 0xdde1e6a4, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x852e3a72, 0x157b0dea, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #24", 0xe7aa57b4, 0x1584bd74, r0,r1,r2, 0); +TESTINST3("pkhbt r0, r1, r2, lsl #31", 0xd4b64d54, 0xc53aaba9, r0,r1,r2, 0); + /* PKHTB */ + TESTINST3("pkhtb r0, r1, r2, asr #0", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhtb r0, r1, r2, asr #1", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhtb r0, r1, r2, asr #2", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhtb r0, r1, r2, asr #3", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhtb r0, r1, r2, asr #4", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhtb r0, r1, r2, asr #16", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhtb r0, r1, r2, asr #22", 0x11223344, 0x55667788, r0,r1,r2, 0); + TESTINST3("pkhtb r0, r1, r2, asr #31", 0x11223344, 0x55667788, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0x50c28082, 0xc1553709, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0x17962e8f, 0x69ec0212, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0xc57243b7, 0x03fa9bb5, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0x7eb226ac, 0xf52e9fbf, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0xbce0f026, 0x7fcbe5a9, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0xa5757252, 0x2dd01366, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0xf4a477c1, 0x5e4b1cbf, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0x76723a21, 0x464a21cc, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0x74d01105, 0xe8108f1b, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2", 0xc1273e2c, 0xcd90d604, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #0", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #1", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #2", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #3", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #4", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #8", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #12", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #16", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #24", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #31", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #32", 0x5f986e68, 0x35232047, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #0", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #1", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #2", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #3", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #4", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #8", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #12", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #16", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #24", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #31", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #32", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #0", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #1", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #2", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #3", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #4", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #8", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #12", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #16", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #24", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #31", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #32", 0x216158cb, 0x57a50a01, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #0", 0xd5dc5407, 0xf87b961e, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #1", 0xd65db979, 0xc61b323b, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #2", 0xa3268abe, 0xed2cbf78, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #3", 0xbf73f0a5, 0x2fb714c9, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #4", 0x281703ed, 0x925ef472, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #8", 0xeaa652c7, 0x137741f4, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #12", 0x71fbde8b, 0xdba5bd25, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #16", 0x884c0ad8, 0xc00b821a, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #24", 0xe1bb8606, 0x58293969, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #31", 0xa3cfd624, 0x6077fb1f, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #32", 0xa3cfd624, 0x6077fb1f, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #0", 0x40b094e2, 0x17913309, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #1", 0x5388b5cd, 0x86582032, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #2", 0x5de41558, 0xccfa1c7e, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #3", 0x23ba1b46, 0x4437983c, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #4", 0x48d06549, 0xa9085781, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #8", 0xc6b4ac58, 0xb2aead21, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #12", 0xc2bdf597, 0xdde1e6a4, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #16", 0x852e3a72, 0x157b0dea, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #24", 0xe7aa57b4, 0x1584bd74, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #31", 0xd4b64d54, 0xc53aaba9, r0,r1,r2, 0); +TESTINST3("pkhtb r0, r1, r2, asr #32", 0xd4b64d54, 0xc53aaba9, r0,r1,r2, 0); + + printf("----------------- USAT ----------------- \n"); + TESTINST2("usat r0, #0, r1", 0x0123abcd, r0, r1, 0); + TESTINST2("usat r0, #1, r1", 0x0123abcd, r0, r1, 0); + TESTINST2("usat r0, #5, r1", 0x0123abcd, r0, r1, 0); + TESTINST2("usat r0, #8, r1", 0x0123abcd, r0, r1, 0); + TESTINST2("usat r0, #11, r1", 0x11110000, r0, r1, 0); + TESTINST2("usat r0, #13, r1", 0x11110000, r0, r1, 0); + TESTINST2("usat r0, #15, r1", 0x11110000, r0, r1, 0); +TESTINST2("usat r0, #0, r1", 0xebbff82b, r0, r1, 0); +TESTINST2("usat r0, #31, r1, lsl #0", 0x5f986e68, r0, r1, 0); +TESTINST2("usat r0, #31, r1, lsl #0", 0xe7aa57b4, r0, r1, 0); +TESTINST2("usat r0, #31, r1, lsl #0", 0x89d2ef86, r0, r1, 0); +TESTINST2("usat r0, #31, r1, lsl #8", 0xc53aaba9, r0, r1, 0); +TESTINST2("usat r0, #31, r1, lsl #8", 0x216158cb, r0, r1, 0); +TESTINST2("usat r0, #31, r1, lsl #8", 0x3cd6cd94, r0, r1, 0); +TESTINST2("usat r0, #0, r1, lsl #0", 0xf87b961e, r0, r1, 0); +TESTINST2("usat r0, #0, r1, lsl #0", 0xc61b323b, r0, r1, 0); +TESTINST2("usat r0, #0, r1, lsl #0", 0xa3268abe, r0, r1, 0); +TESTINST2("usat r0, #0, r1, lsl #8", 0xbf73f0a5, r0, r1, 0); +TESTINST2("usat r0, #0, r1, lsl #8", 0x925ef472, r0, r1, 0); +TESTINST2("usat r0, #0, r1, lsl #8", 0x137741f4, r0, r1, 0); +TESTINST2("usat r0, #24, r1, lsl #2", 0x50c28082, r0, r1, 0); +TESTINST2("usat r0, #16, r1, lsl #3", 0x17962e8f, r0, r1, 0); +TESTINST2("usat r0, #12, r1, lsl #4", 0xc57243b7, r0, r1, 0); +TESTINST2("usat r0, #8, r1, lsl #8", 0xf20fb90f, r0, r1, 0); +TESTINST2("usat r0, #4, r1, lsl #12", 0xbb151055, r0, r1, 0); +TESTINST2("usat r0, #3, r1, lsl #16", 0x957440d2, r0, r1, 0); +TESTINST2("usat r0, #2, r1, lsl #24", 0x728b7771, r0, r1, 0); +TESTINST2("usat r0, #1, r1, lsl #31", 0xf13c20f3, r0, r1, 0); +TESTINST2("usat r0, #0, r1", 0xebbff82b, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #0", 0x5f986e68, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #0", 0xe7aa57b4, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #0", 0x89d2ef86, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #8", 0xc53aaba9, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #8", 0x216158cb, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #8", 0x3cd6cd94, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #0", 0xf87b961e, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #0", 0xc61b323b, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #0", 0xa3268abe, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #8", 0xbf73f0a5, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #8", 0x925ef472, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #8", 0x137741f4, r0, r1, 0); +TESTINST2("usat r0, #24, r1, asr #2", 0x50c28082, r0, r1, 0); +TESTINST2("usat r0, #16, r1, asr #3", 0x17962e8f, r0, r1, 0); +TESTINST2("usat r0, #12, r1, asr #4", 0xc57243b7, r0, r1, 0); +TESTINST2("usat r0, #8, r1, asr #8", 0xf20fb90f, r0, r1, 0); +TESTINST2("usat r0, #4, r1, asr #12", 0xbb151055, r0, r1, 0); +TESTINST2("usat r0, #3, r1, asr #16", 0x957440d2, r0, r1, 0); +TESTINST2("usat r0, #2, r1, asr #24", 0x728b7771, r0, r1, 0); +TESTINST2("usat r0, #1, r1, asr #31", 0xf13c20f3, r0, r1, 0); +TESTINST2("usat r0, #0, r1", 0xebbff82b, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #0", 0x5f986e68, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #0", 0xe7aa57b4, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #0", 0x89d2ef86, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #8", 0xc53aaba9, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #8", 0x216158cb, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #8", 0x3cd6cd94, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #0", 0xf87b961e, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #0", 0xc61b323b, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #0", 0xa3268abe, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #8", 0xbf73f0a5, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #8", 0x925ef472, r0, r1, 0); +TESTINST2("usat r0, #0, r1, asr #8", 0x137741f4, r0, r1, 0); +TESTINST2("usat r0, #24, r1, asr #2", 0x50c28082, r0, r1, 0); +TESTINST2("usat r0, #16, r1, asr #3", 0x17962e8f, r0, r1, 0); +TESTINST2("usat r0, #12, r1, asr #4", 0xc57243b7, r0, r1, 0); +TESTINST2("usat r0, #8, r1, asr #8", 0xf20fb90f, r0, r1, 0); +TESTINST2("usat r0, #4, r1, asr #12", 0xbb151055, r0, r1, 0); +TESTINST2("usat r0, #3, r1, asr #16", 0x957440d2, r0, r1, 0); +TESTINST2("usat r0, #2, r1, asr #24", 0x728b7771, r0, r1, 0); +TESTINST2("usat r0, #1, r1, asr #31", 0xf13c20f3, r0, r1, 0); +#ifndef __thumb__ +TESTINST2("usat r0, #0, r1, asr #32", 0xa9085781, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #32", 0x40b094e2, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #32", 0x17913309, r0, r1, 0); +TESTINST2("usat r0, #31, r1, asr #32", 0x5388b5cd, r0, r1, 0); +TESTINST2("usat r0, #24, r1, asr #32", 0x86582032, r0, r1, 0); +TESTINST2("usat r0, #16, r1, asr #32", 0x5de41558, r0, r1, 0); +TESTINST2("usat r0, #12, r1, asr #32", 0xccfa1c7e, r0, r1, 0); +TESTINST2("usat r0, #8, r1, asr #32", 0x23ba1b46, r0, r1, 0); +TESTINST2("usat r0, #4, r1, asr #32", 0x4437983c, r0, r1, 0); +TESTINST2("usat r0, #3, r1, asr #32", 0x48d06549, r0, r1, 0); +TESTINST2("usat r0, #2, r1, asr #32", 0xa9085781, r0, r1, 0); +TESTINST2("usat r0, #1, r1, asr #32", 0xc6b4ac58, r0, r1, 0); +#endif + + printf("------------ USAT16 sat_imm ------------ \n"); + TESTINST2("usat16 r0, #0, r1", 0x0123abcd, r0, r1, 0); + TESTINST2("usat16 r0, #1, r1", 0xffcdabcd, r0, r1, 0); + TESTINST2("usat16 r0, #5, r1", 0x0123feff, r0, r1, 0); + TESTINST2("usat16 r0, #8, r1", 0x0123abcd, r0, r1, 0); + TESTINST2("usat16 r0, #11, r1", 0x11110000, r0, r1, 0); + TESTINST2("usat16 r0, #13, r1", 0x1111f111, r0, r1, 0); + TESTINST2("usat16 r0, #15, r1", 0x00001111, r0, r1, 0); +TESTINST2("usat16 r0, #0, r1", 0xebbff82b, r0, r1, 0); +TESTINST2("usat16 r0, #1, r1", 0xebbff82b, r0, r1, 0); +TESTINST2("usat16 r0, #3, r1", 0x50c28082, r0, r1, 0); +TESTINST2("usat16 r0, #5, r1", 0x17962e8f, r0, r1, 0); +TESTINST2("usat16 r0, #8, r1", 0xc57243b7, r0, r1, 0); +TESTINST2("usat16 r0, #10, r1", 0xf20fb90f, r0, r1, 0); +TESTINST2("usat16 r0, #11, r1", 0xbb151055, r0, r1, 0); +TESTINST2("usat16 r0, #13, r1", 0x957440d2, r0, r1, 0); +TESTINST2("usat16 r0, #14, r1", 0x728b7771, r0, r1, 0); +TESTINST2("usat16 r0, #15, r1", 0xf13c20f3, r0, r1, 0); +TESTINST2("usat16 r0, #0, r1", 0x86398371, r0, r1, 0); +TESTINST2("usat16 r0, #1, r1", 0x03d0fb78, r0, r1, 0); +TESTINST2("usat16 r0, #3, r1", 0xd0d49b7c, r0, r1, 0); +TESTINST2("usat16 r0, #5, r1", 0x76354a58, r0, r1, 0); +TESTINST2("usat16 r0, #8, r1", 0x9fa45fb7, r0, r1, 0); +TESTINST2("usat16 r0, #10, r1", 0x7572bdec, r0, r1, 0); +TESTINST2("usat16 r0, #11, r1", 0xfea59eb6, r0, r1, 0); +TESTINST2("usat16 r0, #13, r1", 0xf2669090, r0, r1, 0); +TESTINST2("usat16 r0, #14, r1", 0xbc1ff573, r0, r1, 0); +TESTINST2("usat16 r0, #15, r1", 0x7eb226ac, r0, r1, 0); +TESTINST2("usat16 r0, #0, r1", 0x22b65db1, r0, r1, 0); +TESTINST2("usat16 r0, #1, r1", 0x776c41c7, r0, r1, 0); +TESTINST2("usat16 r0, #3, r1", 0xe50dd77c, r0, r1, 0); +TESTINST2("usat16 r0, #5, r1", 0xd6f9a698, r0, r1, 0); +TESTINST2("usat16 r0, #8, r1", 0xeda5110c, r0, r1, 0); +TESTINST2("usat16 r0, #10, r1", 0x0be36f70, r0, r1, 0); +TESTINST2("usat16 r0, #11, r1", 0xd759eb72, r0, r1, 0); +TESTINST2("usat16 r0, #13, r1", 0xd9c4b1f4, r0, r1, 0); +TESTINST2("usat16 r0, #14, r1", 0xa29eb320, r0, r1, 0); +TESTINST2("usat16 r0, #15, r1", 0xcf1e4487, r0, r1, 0); +TESTINST2("usat16 r0, #0, r1", 0x2eb68500, r0, r1, 0); +TESTINST2("usat16 r0, #1, r1", 0xcdb7ed11, r0, r1, 0); +TESTINST2("usat16 r0, #3, r1", 0x2eaea305, r0, r1, 0); +TESTINST2("usat16 r0, #5, r1", 0x6ebd04d9, r0, r1, 0); +TESTINST2("usat16 r0, #8, r1", 0xa5ec1aa8, r0, r1, 0); +TESTINST2("usat16 r0, #10, r1", 0x72f33509, r0, r1, 0); +TESTINST2("usat16 r0, #11, r1", 0xa3e6f759, r0, r1, 0); +TESTINST2("usat16 r0, #13, r1", 0xfaceab39, r0, r1, 0); +TESTINST2("usat16 r0, #14, r1", 0x2738f0ff, r0, r1, 0); +TESTINST2("usat16 r0, #15, r1", 0xe79fd570, r0, r1, 0); +TESTINST2("usat16 r0, #0, r1", 0x55ea3e4e, r0, r1, 0); +TESTINST2("usat16 r0, #1, r1", 0x2b62ba5a, r0, r1, 0); +TESTINST2("usat16 r0, #3, r1", 0x9b41bfb1, r0, r1, 0); +TESTINST2("usat16 r0, #5, r1", 0x557c7ba2, r0, r1, 0); +TESTINST2("usat16 r0, #8, r1", 0x2973c051, r0, r1, 0); +TESTINST2("usat16 r0, #10, r1", 0x6a228b19, r0, r1, 0); +TESTINST2("usat16 r0, #11, r1", 0x0cdafabe, r0, r1, 0); +TESTINST2("usat16 r0, #13, r1", 0x50865114, r0, r1, 0); +TESTINST2("usat16 r0, #14, r1", 0xd83b849b, r0, r1, 0); +TESTINST2("usat16 r0, #15, r1", 0xca5e5605, r0, r1, 0); + + printf("---------------- UADD16 ---------------- \n"); + TESTINST3("uadd16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + + TESTINST3("uadd16 r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00000001, 0x00000000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00000000, 0x00000001, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00000001, 0x00000001, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00000000, 0x0000ffff, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x0000ffff, 0x00000000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); + + TESTINST3("uadd16 r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00010000, 0x00000000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00000000, 0x00010000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00010000, 0x00010000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0x00000000, 0xffff0000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0xffff0000, 0x00000000, r0, r1, r2, 0); + TESTINST3("uadd16 r0, r1, r2", 0xffff0000, 0xffff0000, r0, r1, r2, 0); + +TESTINST3("uadd16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("uadd16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("---------------- SADD16 ---------------- \n"); + TESTINST3("sadd16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + + TESTINST3("sadd16 r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00000001, 0x00000000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00000000, 0x00000001, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00000001, 0x00000001, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00000000, 0x0000ffff, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x0000ffff, 0x00000000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); + + TESTINST3("sadd16 r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00010000, 0x00000000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00000000, 0x00010000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00010000, 0x00010000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0x00000000, 0xffff0000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0xffff0000, 0x00000000, r0, r1, r2, 0); + TESTINST3("sadd16 r0, r1, r2", 0xffff0000, 0xffff0000, r0, r1, r2, 0); + +TESTINST3("sadd16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("sadd16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("---------------- USUB16 ---------------- \n"); + TESTINST3("usub16 r0, r1, r2", 0x04000022, 0x03000011, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + + TESTINST3("usub16 r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00000001, 0x00000000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00000000, 0x00000001, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00000001, 0x00000001, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00000000, 0x0000ffff, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x0000ffff, 0x00000000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); + + TESTINST3("usub16 r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00010000, 0x00000000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00000000, 0x00010000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00010000, 0x00010000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0x00000000, 0xffff0000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0xffff0000, 0x00000000, r0, r1, r2, 0); + TESTINST3("usub16 r0, r1, r2", 0xffff0000, 0xffff0000, r0, r1, r2, 0); + +TESTINST3("usub16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("usub16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("---------------- SSUB16 ---------------- \n"); + TESTINST3("ssub16 r0, r1, r2", 0x04000022, 0x03000011, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + + TESTINST3("ssub16 r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00000001, 0x00000000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00000000, 0x00000001, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00000001, 0x00000001, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00000000, 0x0000ffff, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x0000ffff, 0x00000000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); + + TESTINST3("ssub16 r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00010000, 0x00000000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00000000, 0x00010000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00010000, 0x00010000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0x00000000, 0xffff0000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0xffff0000, 0x00000000, r0, r1, r2, 0); + TESTINST3("ssub16 r0, r1, r2", 0xffff0000, 0xffff0000, r0, r1, r2, 0); + +TESTINST3("ssub16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("ssub16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("---------------- UADD8 ----------------- \n"); + TESTINST3("uadd8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("uadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("uadd8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("uadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("uadd8 r0, r1, r2", 0x00000318, 0xff00ff09, r0, r1, r2, 0); + TESTINST3("uadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("uadd8 r0, r1, r2", 0x00020318, 0xff07ff09, r0, r1, r2, 0); + TESTINST3("uadd8 r0, r1, r2", 0xff07ff09, 0x00020318, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("uadd8 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("---------------- USUB8 ----------------- \n"); + TESTINST3("usub8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("usub8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("usub8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("usub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("usub8 r0, r1, r2", 0x00000318, 0xff00ff09, r0, r1, r2, 0); + TESTINST3("usub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("usub8 r0, r1, r2", 0x00020318, 0xff07ff09, r0, r1, r2, 0); + TESTINST3("usub8 r0, r1, r2", 0xff07ff09, 0x00020318, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("usub8 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("---------------- QADD16 ---------------- \n"); + TESTINST3("qadd16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("qadd16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("qadd16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("qadd16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("qadd16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("---------------- QSUB16 ---------------- \n"); + TESTINST3("qsub16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("qsub16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("qsub16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("qsub16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("qsub16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("----------------- QSAX ----------------- \n"); + TESTINST3("qsax r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("qsax r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("qsax r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0); + TESTINST3("qsax r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("qsax r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("qsax r0, r1, r2", 0x00030003, 0x00640064, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("qsax r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("----------------- QASX ----------------- \n"); + TESTINST3("qasx r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("qasx r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("qasx r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0); + TESTINST3("qasx r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("qasx r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("qasx r0, r1, r2", 0x00030003, 0x00640064, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("qasx r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("----------------- SASX ----------------- \n"); + TESTINST3("sasx r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("sasx r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("sasx r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0); + TESTINST3("sasx r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("sasx r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("sasx r0, r1, r2", 0x00030003, 0x00640064, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("sasx r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("----------------- SMUAD ----------------- \n"); + TESTINST3("smuad r0, r1, r2", 0x80008000, 0x80008000, r0, r1, r2, 0); + TESTINST3("smuad r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("smuad r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("smuad r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("smuad r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("smuad r0, r1, r2", 0xffffffff, 0xfffc0001, r0, r1, r2, 0); + TESTINST3("smuad r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("smuad r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + printf("----------------- SMUADX ---------------- \n"); + TESTINST3("smuadx r0, r1, r2", 0x80008000, 0x80008000, r0, r1, r2, 0); + TESTINST3("smuadx r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("smuadx r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("smuadx r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("smuadx r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("smuadx r0, r1, r2", 0xffffffff, 0xfffc0001, r0, r1, r2, 0); + TESTINST3("smuadx r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("smuadx r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("----------------- SMLAD ----------------- \n"); + TESTINST4("smlad r0, r1, r2, r3", + 0x80008000, 0x80008000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("smlad r0, r1, r2, r3", + 0x7fff7fff, 0x00000000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("smlad r0, r1, r2, r3", + 0x7fff7fff, 0x00010001, 0x00000001, r0, r1, r2, r3, 0); + TESTINST4("smlad r0, r1, r2, r3", + 0x80008000, 0xffffffff, 0x0000001f, r0, r1, r2, r3, 0); + TESTINST4("smlad r0, r1, r2, r3", + 0x00640064, 0x00030003, 0x00000020, r0, r1, r2, r3, 0); + TESTINST4("smlad r0, r1, r2, r3", + 0xffffffff, 0xfffc0001, 0x000000ff, r0, r1, r2, r3, 0); + TESTINST4("smlad r0, r1, r2, r3", + 0xfff70fff, 0x00030003, 0x00000100, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("smlad r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + + printf("----------------- SMLADX ----------------- \n"); + TESTINST4("smladx r0, r1, r2, r3", + 0x80008000, 0x80008000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("smladx r0, r1, r2, r3", + 0x7fff7fff, 0x00000000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("smladx r0, r1, r2, r3", + 0x7fff7fff, 0x00010001, 0x00000001, r0, r1, r2, r3, 0); + TESTINST4("smladx r0, r1, r2, r3", + 0x80008000, 0xffffffff, 0x0000001f, r0, r1, r2, r3, 0); + TESTINST4("smladx r0, r1, r2, r3", + 0x00640064, 0x00030003, 0x00000020, r0, r1, r2, r3, 0); + TESTINST4("smladx r0, r1, r2, r3", + 0xffffffff, 0xfffc0001, 0x000000ff, r0, r1, r2, r3, 0); + TESTINST4("smladx r0, r1, r2, r3", + 0xfff70fff, 0x00030003, 0x00000100, r0, r1, r2, r3, 0); +TESTINST4("smladx r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smladx r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smladx r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); + + printf("------------ SMLABB, SMLATT, SMLATB, SMLABT ------------\n"); + /* smlabb rD, rN, rM, rA */ + TESTINST4("smlabb r0, r1, r2, r3", + 0x00030000, 0x00040000, 0x00000000, r0,r1,r2,r3, 0); + TESTINST4("smlabb r0, r1, r2, r3", + 0x00030001, 0x00040002, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlabb r0, r1, r2, r3", + 0x00038001, 0x00047fff, 0x00005fff, r0,r1,r2,r3, 0); + TESTINST4("smlabb r0, r1, r2, r3", + 0x00037fff, 0x00047fff, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlabb r0, r1, r2, r3", + 0x0003ffff, 0x0004ffff, 0x7fff7fff, r0,r1,r2,r3, 0); + TESTINST4("smlabb r0, r1, r2, r3", + 0x0003fffc, 0x0004ffff, 0xffffffff, r0,r1,r2,r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("smlabb r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + /* smlatt rD, rN, rM, rA */ + TESTINST4("smlatt r0, r1, r2, r3", + 0x00000003, 0x00000004, 0x00000000, r0,r1,r2,r3, 0); + TESTINST4("smlatt r0, r1, r2, r3", + 0x00010003, 0x00020004, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlatt r0, r1, r2, r3", + 0x80010003, 0x7fff0004, 0x00005fff, r0,r1,r2,r3, 0); + TESTINST4("smlatt r0, r1, r2, r3", + 0x7fff0003, 0x7fff0004, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlatt r0, r1, r2, r3", + 0xffff0003, 0xffff0004, 0x7fff7fff, r0,r1,r2,r3, 0); + TESTINST4("smlatt r0, r1, r2, r3", + 0xfffc0003, 0xffff0004, 0xffffffff, r0,r1,r2,r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("smlatt r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + /* smlatb rD, rN, rM, rA */ + TESTINST4("smlatb r0, r1, r2, r3", + 0x00000003, 0x00040000, 0x00000000, r0,r1,r2,r3, 0); + TESTINST4("smlatb r0, r1, r2, r3", + 0x00010003, 0x00040002, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlatb r0, r1, r2, r3", + 0x80010003, 0x00047fff, 0x00005fff, r0,r1,r2,r3, 0); + TESTINST4("smlatb r0, r1, r2, r3", + 0x7fff0003, 0x00047fff, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlatb r0, r1, r2, r3", + 0xffff0003, 0x0004ffff, 0x7fff7fff, r0,r1,r2,r3, 0); + TESTINST4("smlatb r0, r1, r2, r3", + 0xfffc0003, 0x0004ffff, 0xffffffff, r0,r1,r2,r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("smlatb r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + /* smlabt rD, rN, rM, rA */ + TESTINST4("smlabt r0, r1, r2, r3", + 0x00030000, 0x00000004, 0x00000000, r0,r1,r2,r3, 0); + TESTINST4("smlabt r0, r1, r2, r3", + 0x00030001, 0x00020004, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlabt r0, r1, r2, r3", + 0x00038001, 0x7fff0004, 0x00005fff, r0,r1,r2,r3, 0); + TESTINST4("smlabt r0, r1, r2, r3", + 0x00037fff, 0x7fff0004, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlabt r0, r1, r2, r3", + 0x0003ffff, 0xffff0004, 0x7fff7fff, r0,r1,r2,r3, 0); + TESTINST4("smlabt r0, r1, r2, r3", + 0x0003fffc, 0xffff0004, 0xffffffff, r0,r1,r2,r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("smlabt r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + + printf("------------ UQSUB8 -----------------------------------\n"); + TESTINST3("uqsub8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("uqsub8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("uqsub8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("uqsub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("uqsub8 r0, r1, r2", 0x00000318, 0xff00ff09, r0, r1, r2, 0); + TESTINST3("uqsub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("uqsub8 r0, r1, r2", 0x00020318, 0xff07ff09, r0, r1, r2, 0); + TESTINST3("uqsub8 r0, r1, r2", 0xff07ff09, 0x00020318, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uqsub8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ UQADD8 -----------------------------------\n"); + TESTINST3("uqadd8 r0, r1, r2", 0x0009ffff, 0x001800aa, r0, r1, r2, 0); + TESTINST3("uqadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("uqadd8 r0, r1, r2", 0x00aa0018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("uqadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("uqadd8 r0, r1, r2", 0x0000aa18, 0xff00ff09, r0, r1, r2, 0); + TESTINST3("uqadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("uqadd8 r0, r1, r2", 0xff9fefcc, 0xff9ffedd, r0, r1, r2, 0); + TESTINST3("uqadd8 r0, r1, r2", 0xff07ff09, 0xaa020318, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uqadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ SEL --------------------------------------\n"); + TESTINST3("sel r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("sel r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("sel r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("sel r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("sel r0, r1, r2", 0xfffcffff, 0xffff0001, r0, r1, r2, 0); + TESTINST3("sel r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sel r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ QSUB8-------------------------------------\n"); + TESTINST3("qsub8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("qsub8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("qsub8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("qsub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("qsub8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("qsub8 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0); + TESTINST3("qsub8 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0); + TESTINST3("qsub8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("qsub8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ QADD8-------------------------------------\n"); + TESTINST3("qadd8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("qadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("qadd8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("qadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("qadd8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("qadd8 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0); + TESTINST3("qadd8 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0); + TESTINST3("qadd8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("qadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ SHADD8 -----------------------------------\n"); + TESTINST3("shadd8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("shadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("shadd8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("shadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("shadd8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("shadd8 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0); + TESTINST3("shadd8 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0); + TESTINST3("shadd8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("shadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ UHADD8 -----------------------------------\n"); + TESTINST3("uhadd8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0); + TESTINST3("uhadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0); + TESTINST3("uhadd8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0); + TESTINST3("uhadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0); + TESTINST3("uhadd8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("uhadd8 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0); + TESTINST3("uhadd8 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0); + TESTINST3("uhadd8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uhadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("----------------- SSAT ----------------- \n"); + TESTINST2("ssat r0, #1, r1, LSL #31", 0x80008000, r0, r1, 0); + TESTINST2("ssat r0, #6, r1, LSL #24", 0x80008000, r0, r1, 0); + TESTINST2("ssat r0, #8, r1, ASR #18", 0x80008000, r0, r1, 0); + TESTINST2("ssat r0, #12, r1, ASR #16", 0x80008000, r0, r1, 0); + TESTINST2("ssat r0, #16, r1, LSL #12", 0xffff0009, r0, r1, 0); + TESTINST2("ssat r0, #18, r1, LSL #8", 0xffff0009, r0, r1, 0); + TESTINST2("ssat r0, #24, r1, ASR #6", 0xffff0009, r0, r1, 0); + TESTINST2("ssat r0, #31, r1, ASR #1", 0xffff0009, r0, r1, 0); +TESTINST2("ssat r0, #1, r1", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #1, r1", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #1, r1", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #1, r1", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #32, r1", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #32, r1", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #32, r1", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #32, r1", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #32, r1", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #32, r1", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, LSL #31", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #3, r1, LSL #28", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #6, r1, LSL #24", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #8, r1, ASR #18", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #12, r1, ASR #16", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #16, r1, LSL #12", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #18, r1, LSL #8", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #24, r1, ASR #6", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #28, r1, ASR #3", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #31, r1, ASR #1", 0xffc134df, r0, r1, 0); +#ifndef __thumb__ +TESTINST2("ssat r0, #1, r1, ASR #32", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #1, r1, ASR #32", 0xffc134df, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0x256bfdd6, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0xc02a0c05, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0xee2fa46e, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0x97a7da20, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0xa231d5e6, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0x10e1968a, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0x0e089270, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0x9e8e0185, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0x3096f12e, r0, r1, 0); +TESTINST2("ssat r0, #32, r1, ASR #32", 0xffc134df, r0, r1, 0); +#endif + + printf("---------------- SADD8 ----------------- \n"); + TESTINST3("sadd8 r0, r1, r2", 0x00f7ffff, 0x00e800fd, r0, r1, r2, 0); + TESTINST3("sadd8 r0, r1, r2", 0x00e800fd, 0x00f7ffff, r0, r1, r2, 0); + TESTINST3("sadd8 r0, r1, r2", 0x00fd00e8, 0xffff00f7, r0, r1, r2, 0); + TESTINST3("sadd8 r0, r1, r2", 0xffff00f7, 0x00fd0018, r0, r1, r2, 0); + TESTINST3("sadd8 r0, r1, r2", 0x0000fd18, 0xff00fff7, r0, r1, r2, 0); + TESTINST3("sadd8 r0, r1, r2", 0xffff00f7, 0x00fd00e8, r0, r1, r2, 0); + TESTINST3("sadd8 r0, r1, r2", 0x00fefd18, 0xff07fff7, r0, r1, r2, 0); + TESTINST3("sadd8 r0, r1, r2", 0xff07fff7, 0x00fefde8, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("---------------- SSUB8 ----------------- \n"); + TESTINST3("ssub8 r0, r1, r2", 0x00f7ffff, 0x00e800fd, r0, r1, r2, 0); + TESTINST3("ssub8 r0, r1, r2", 0x00e800fd, 0x00f7ffff, r0, r1, r2, 0); + TESTINST3("ssub8 r0, r1, r2", 0x00fd00e8, 0xffff00f7, r0, r1, r2, 0); + TESTINST3("ssub8 r0, r1, r2", 0xffff00f7, 0x00fd0018, r0, r1, r2, 0); + TESTINST3("ssub8 r0, r1, r2", 0x0000fd18, 0xff00fff7, r0, r1, r2, 0); + TESTINST3("ssub8 r0, r1, r2", 0xffff00f7, 0x00fd00e8, r0, r1, r2, 0); + TESTINST3("ssub8 r0, r1, r2", 0x00fefd18, 0xff07fff7, r0, r1, r2, 0); + TESTINST3("ssub8 r0, r1, r2", 0xff07fff7, 0x00fefde8, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("ssub8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ SXTAB ------------\n"); + TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, r0, r1, r2, 0); + + TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, r0, r1, r2, 0); + +TESTINST3("sxtab r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("sxtab r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("sxtab r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("sxtab r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sxtab r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ UXTAB ------------\n"); + TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, r0, r1, r2, 0); + + TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, r0, r1, r2, 0); + +TESTINST3("uxtab r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtab r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtab r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtab r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtab r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("----------- UXTAB16 -----------\n"); + TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182819, r0, r1, r2, 0); + + TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182899, r0, r1, r2, 0); + TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x3141FFFF, 0x27182899, r0, r1, r2, 0); + +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ SXTAH ------------\n"); + TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, r0, r1, r2, 0); + + TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, r0, r1, r2, 0); + TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, r0, r1, r2, 0); + +TESTINST3("sxtah r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("sxtah r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("sxtah r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("sxtah r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("sxtah r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ UXTAH ------------\n"); + TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, r0, r1, r2, 0); + + TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, r0, r1, r2, 0); + TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, r0, r1, r2, 0); + +TESTINST3("uxtah r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtah r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtah r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + +TESTINST3("uxtah r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("uxtah r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); + + printf("------------ SMLAWB ------------\n"); + /* smlawb rD, rN, rM, rA */ + TESTINST4("smlawb r0, r1, r2, r3", + 0x00030000, 0x00040000, 0x00000000, r0,r1,r2,r3, 0); + TESTINST4("smlawb r0, r1, r2, r3", + 0x00030001, 0x00040002, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlawb r0, r1, r2, r3", + 0x00038001, 0x00047fff, 0x00005fff, r0,r1,r2,r3, 0); + TESTINST4("smlawb r0, r1, r2, r3", + 0x00037fff, 0x00047fff, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlawb r0, r1, r2, r3", + 0x0003ffff, 0x0004ffff, 0x7fff7fff, r0,r1,r2,r3, 0); + TESTINST4("smlawb r0, r1, r2, r3", + 0x0003fffc, 0x0004ffff, 0xffffffff, r0,r1,r2,r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("smlawb r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + + printf("------------ SMLAWT ------------\n"); + /* smlawt rD, rN, rM, rA */ + TESTINST4("smlawt r0, r1, r2, r3", + 0x00030000, 0x00040000, 0x00000000, r0,r1,r2,r3, 0); + TESTINST4("smlawt r0, r1, r2, r3", + 0x00030001, 0x00040002, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlawt r0, r1, r2, r3", + 0x00038001, 0x00047fff, 0x00005fff, r0,r1,r2,r3, 0); + TESTINST4("smlawt r0, r1, r2, r3", + 0x00037fff, 0x00047fff, 0x00007fff, r0,r1,r2,r3, 0); + TESTINST4("smlawt r0, r1, r2, r3", + 0x0003ffff, 0x0004ffff, 0x7fff7fff, r0,r1,r2,r3, 0); + TESTINST4("smlawt r0, r1, r2, r3", + 0x0003fffc, 0x0004ffff, 0xffffffff, r0,r1,r2,r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("smlawt r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + + + printf("----------------- SMLSD ----------------- \n"); + TESTINST4("smlsd r0, r1, r2, r3", + 0x80008000, 0x80008000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("smlsd r0, r1, r2, r3", + 0x7fff7fff, 0x00000000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("smlsd r0, r1, r2, r3", + 0x7fff7fff, 0x00010001, 0x00000001, r0, r1, r2, r3, 0); + TESTINST4("smlsd r0, r1, r2, r3", + 0x80008000, 0xffffffff, 0x0000001f, r0, r1, r2, r3, 0); + TESTINST4("smlsd r0, r1, r2, r3", + 0x00640064, 0x00030003, 0x00000020, r0, r1, r2, r3, 0); + TESTINST4("smlsd r0, r1, r2, r3", + 0xffffffff, 0xfffc0001, 0x000000ff, r0, r1, r2, r3, 0); + TESTINST4("smlsd r0, r1, r2, r3", + 0xfff70fff, 0x00030003, 0x00000100, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("smlsd r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + + printf("----------------- SMLSDX ----------------- \n"); + TESTINST4("smlsdx r0, r1, r2, r3", + 0x80008000, 0x80008000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("smlsdx r0, r1, r2, r3", + 0x7fff7fff, 0x00000000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("smlsdx r0, r1, r2, r3", + 0x7fff7fff, 0x00010001, 0x00000001, r0, r1, r2, r3, 0); + TESTINST4("smlsdx r0, r1, r2, r3", + 0x80008000, 0xffffffff, 0x0000001f, r0, r1, r2, r3, 0); + TESTINST4("smlsdx r0, r1, r2, r3", + 0x00640064, 0x00030003, 0x00000020, r0, r1, r2, r3, 0); + TESTINST4("smlsdx r0, r1, r2, r3", + 0xffffffff, 0xfffc0001, 0x000000ff, r0, r1, r2, r3, 0); + TESTINST4("smlsdx r0, r1, r2, r3", + 0xfff70fff, 0x00030003, 0x00000100, r0, r1, r2, r3, 0); +TESTINST4("smlsdx r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("smlsdx r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("smlsdx r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); + + + printf("----------------- SMUSD ----------------- \n"); + TESTINST3("smusd r0, r1, r2", 0x80008000, 0x80008000, r0, r1, r2, 0); + TESTINST3("smusd r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("smusd r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("smusd r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("smusd r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("smusd r0, r1, r2", 0xffffffff, 0xfffc0001, r0, r1, r2, 0); + TESTINST3("smusd r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("smusd r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + printf("----------------- SMUSDX ---------------- \n"); + TESTINST3("smusdx r0, r1, r2", 0x80008000, 0x80008000, r0, r1, r2, 0); + TESTINST3("smusdx r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("smusdx r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("smusdx r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("smusdx r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("smusdx r0, r1, r2", 0xffffffff, 0xfffc0001, r0, r1, r2, 0); + TESTINST3("smusdx r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("smusdx r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("----------------- USAD8 ---------------- \n"); + TESTINST3("usad8 r0, r1, r2", 0x80008000, 0x80008000, r0, r1, r2, 0); + TESTINST3("usad8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0); + TESTINST3("usad8 r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0); + TESTINST3("usad8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0); + TESTINST3("usad8 r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0); + TESTINST3("usad8 r0, r1, r2", 0xffffffff, 0xfffc0001, r0, r1, r2, 0); + TESTINST3("usad8 r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0); +TESTINST3("usad8 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0); + + printf("----------------- USADA8 ----------------- \n"); + TESTINST4("usada8 r0, r1, r2, r3", + 0x80008000, 0x80008000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("usada8 r0, r1, r2, r3", + 0x7fff7fff, 0x00000000, 0x00000000, r0, r1, r2, r3, 0); + TESTINST4("usada8 r0, r1, r2, r3", + 0x7fff7fff, 0x00010001, 0x00000001, r0, r1, r2, r3, 0); + TESTINST4("usada8 r0, r1, r2, r3", + 0x80008000, 0xffffffff, 0x0000001f, r0, r1, r2, r3, 0); + TESTINST4("usada8 r0, r1, r2, r3", + 0x00640064, 0x00030003, 0x00000020, r0, r1, r2, r3, 0); + TESTINST4("usada8 r0, r1, r2, r3", + 0xffffffff, 0xfffc0001, 0x000000ff, r0, r1, r2, r3, 0); + TESTINST4("usada8 r0, r1, r2, r3", + 0xfff70fff, 0x00030003, 0x00000100, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0); +TESTINST4("usada8 r0, r1, r2, r3", + 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0); + + + + +/* +TESTINST3("theinsn", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0); +TESTINST3("theinsn", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0); +TESTINST3("theinsn", 0x299da970, 0xe8108f1b, r0, r1, r2, 0); +TESTINST3("theinsn", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0); +TESTINST3("theinsn", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0); +TESTINST3("theinsn", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0); +TESTINST3("theinsn", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0); +TESTINST3("theinsn", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0); +TESTINST3("theinsn", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0); +TESTINST3("theinsn", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0); +*/ + + return 0; +} diff --git a/none/tests/arm/v6media.stderr.exp b/none/tests/arm/v6media.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/arm/v6media.stdout.exp b/none/tests/arm/v6media.stdout.exp new file mode 100644 index 0000000..2e8e9d8 --- /dev/null +++ b/none/tests/arm/v6media.stdout.exp @@ -0,0 +1,3173 @@ +MUL +mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +MLA +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mla r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mla r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +MLS +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mls r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mls r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +mls r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +UMULL +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +SMULL +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +UMLAL +umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +SMLAL +smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +CLZ +clz r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +clz r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +clz r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +clz r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +clz r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 1, cpsr 0x20000000 C ge[3:0]=0000 +clz r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 1, cpsr 0x20000000 C ge[3:0]=0000 +clz r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 1, cpsr 0x20000000 C ge[3:0]=0000 +clz r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x20000000 C ge[3:0]=0000 +extend instructions +uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb16 r0, r1 :: rd 0x00ff00ff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtb16 r0, r1, ror #16 :: rd 0x00ff0000 rm 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtb16 r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtb16 r0, r1 :: rd 0xffffffff rm 0x00ff00ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtb16 r0, r1 :: rd 0x007f007f rm 0x007f007f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ BFI ------------ +bfi r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfi r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ BFC ------------ +bfc r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +bfc r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ SBFX ------------ +sbfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sbfx r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ UBFX ------------ +ubfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ubfx r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ SMUL{B,T}{B,T} ------------ +smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xffcb2e38 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x07a8b29d rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xff5c9d7c rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xfecbe07c rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xff042c1a rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x01484910 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x0dd1cd08 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x023a5a06 rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xd832f800 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x0056d6f4 rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x10c39d25 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x07035c90 rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xe8fa4ae9 rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xea7e2dc4 rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xfbb41d80 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf7c8c69a rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x0792e7b8 rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf437f0b0 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf602272f rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xfe76ad20 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xc8ea11a0 rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x0cb3fcd3 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xefe9fcf3 rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xef9befb8 rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x26be8fe0 rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf1b742a0 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x20456454 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xeed72dd0 rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x0fd5b9da rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x0440f214 rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf21aba04 rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf39d9f16 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xd2cefb78 rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x03c56208 rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xea7902bc rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x1c6ede49 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf16e45b5 rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf8597100 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x0dc69ed8 rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x028565c4 rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x0e6bd97c rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xd61a32e0 rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x09b06e51 rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xc9215a70 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xed3740f0 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf7045ab6 rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x06632384 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xe1d4f1da rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0x20d81c27 rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbb r0, r1, r2 :: rd 0xf81cf537 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00000004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x00000002 rm 0x00010003, rn 0x00020004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xc000ffff rm 0x80010003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x3fff0001 rm 0x7fff0003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x00000001 rm 0xffff0003, rn 0xffff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xf961a794 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xfe995f90 rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xfff8ec65 rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xffb2ef91 rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x11e3356c rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xf47479d7 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xf357ff64 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xf6f7b4c6 rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x12125961 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xe37ea72a rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x215567c7 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x1d17a20d rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x1fe4089e rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x23125d5d rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x0c590fd8 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x07e4f4bf rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xfcef02be rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xde8dc080 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xd809e8f8 rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x0d7aa233 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xe1e51788 rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x080b03d8 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x1bd44694 rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x0439c92c rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x09573b0f rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x12eb1314 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x0161f097 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x0938f4b4 rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xe832b3a0 rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xf2e3e9ec rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x14ddd088 rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xefff9438 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xf2bf54b4 rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xe71bc6a2 rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xef6388cd rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xd1d70c79 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x0528ed18 rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x064f5290 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x2a26c1f2 rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xfb18e4a9 rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xe748a42c rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x069a597e rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x02afb688 rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xead49311 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xf080ee3a rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xf40b8308 rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xff48ec80 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x002937f8 rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0xfb59e3d2 rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultt r0, r1, r2 :: rd 0x1a0108a8 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00040000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x00000002 rm 0x00010003, rn 0x00040002, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xc000ffff rm 0x80010003, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x3fff0001 rm 0x7fff0003, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x00000001 rm 0xffff0003, rn 0x0004ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x05ec6cac rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfefee06d rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x000bf85c rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfe0b9cf3 rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf17ba3d7 rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfed1e48c rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x07d9b884 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x023049f2 rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x0ee5e6a0 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfd726def rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xee5e2381 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf96881f8 rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x14d7ecc2 rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xe2e60a96 rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfc2bf7c0 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xef9a9946 rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfeac4758 rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf98ccce0 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xeea90989 rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfddc2f4e rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x36a1ba64 rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xe48c78a4 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xee231715 rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x0f77aa68 rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x0e4d01f8 rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf49d0772 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x15bd279c rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x1080777c rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xc9e2bc84 rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf07dc20c rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf558e25c rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf065a516 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x12e41cc8 rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x37346b50 rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf63870d3 rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x1ed8f6a9 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xef674168 rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xdb25a6c0 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf3f3fe24 rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xff192223 rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x11cafd44 rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xf29ea4e8 rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x03d8464c rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x212f12e8 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x08e8ae60 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfcb6112a rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfee60308 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x21080a58 rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0xfd62dd9a rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smultb r0, r1, r2 :: rd 0x078646b8 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00000004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00020004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0xffff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x003b0448 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x0aaeb690 rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x0060973d rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xffd08bd4 rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x01364bc8 rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x0c8ba034 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xe9b87ac8 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xf6ce2d62 rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xcfb878c0 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x03c99878 rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xe04ec043 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xe10c4b16 rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xdcc68d47 rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x19eb600e rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x0ddba470 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x03f4a7f1 rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x11803376 rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xc2e84f40 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xe8f92748 rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x09ad81d0 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x1e5af140 rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xfc4730f2 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x190f938c rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xfb85a144 rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x194e6d3c rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x17bb7c40 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x020d6b25 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xf668f470 rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x06f70390 rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x03987f34 rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x1b37e8b8 rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xf34c9c38 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x1fb3fdec rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xfe4cb6ed rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xdb6f35c4 rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xd573f619 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x0487909b rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x014f56c0 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xcfcc90ac rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x0db4b44c rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xebf7a214 rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x14acfbe8 rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x06c513f6 rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x23010c06 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x20ac71c1 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xdf589e78 rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x04259640 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xffda5ab2 rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0x3a6a827b rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulbt r0, r1, r2 :: rd 0xe4be6035 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +-------------- SMULW{B,T} -------------- +smulwb r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00020004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x00000004 rm 0x00010003, rn 0x47ff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfffe0004 rm 0x80010003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x0001fffc rm 0x7fff0003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfffffffc rm 0xffff0003, rn 0xffff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x05ec94f3 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfefee815 rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x000c1f84 rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfe0bd12f rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf17bdc1c rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfed1def8 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x07d9c655 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x023044ba rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x0ee61cf2 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfd7265d6 rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xee5df32b rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf96888fb rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x14d7d5bc rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xe2e5f514 rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfc2bf374 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xef9b0af4 rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfeac4eea rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf98cd965 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xeea930ea rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfddc3ed2 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x36a2015b rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xe48c1390 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xee2306fe rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x0f77e42d rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x0e4d28b6 rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf49cf929 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x15bd47e1 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x1080adae rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xc9e26000 rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf07dc64c rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf558d476 rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf06598b3 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x12e451be rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x3733fc9d rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf6389d95 rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x1ed91317 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xef67760b rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xdb259f19 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf3f3ee6c rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xff191737 rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x11cad579 rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xf29efaa6 rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x03d8048b rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x212f5a21 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x08e8e0a7 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfcb6082e rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfee5f817 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x2108411e rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0xfd62fe72 rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwb r0, r1, r2 :: rd 0x07863ed4 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00040000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x00000004 rm 0x00010003, rn 0x00040002, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xfffe0004 rm 0x80010003, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x0001fffc rm 0x7fff0003, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xfffffffc rm 0xffff0003, rn 0x0004ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xf9617a93 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xfe996a3e rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xfff8d53e rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xffb2f79c rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x11e2f016 rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xf4744347 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xf357e91c rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xf6f7ca4e rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x12129b46 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xe37e4cc9 rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x2155c326 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x1d178319 rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x1fe3e564 rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x23127748 rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x0c591db3 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x07e4be02 rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xfcef143e rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xde8e0170 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xd80a43b9 rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x0d7a4073 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xe1e4f06c rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x080b2175 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x1bd45fa3 rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x0439d8f4 rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x0957545d rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x12eb2acf rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x0161f2a4 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x093912fd rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xe8328aef rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xf2e3ed84 rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x14ddebbf rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xefff8784 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xf2bf2f8b rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xe71bf88b rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xef63d4d3 rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xd1d6e1ec rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x0528dcba rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x064f53df rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x2a26f8ef rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xfb18a94a rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xe748db71 rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x069a2f2d rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x02af8897 rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xead465a1 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xf08096c5 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xf40b6260 rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xff48e565 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x0029383c rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0xfb5a1e3c rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smulwt r0, r1, r2 :: rd 0x1a00ed66 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ PKHBT / PKHTB ------------ +pkhbt r0, r1, r2, lsl #0 :: rd 0x55663344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #1 :: rd 0xaacc3344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #2 :: rd 0x55993344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #3 :: rd 0xab333344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #4 :: rd 0x56673344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #16 :: rd 0x77883344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #22 :: rd 0xe2003344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #31 :: rd 0x00003344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0xc1558082 rm 0x50c28082, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0x69ec2e8f rm 0x17962e8f, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0x03fa43b7 rm 0xc57243b7, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0xf52e26ac rm 0x7eb226ac, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0x7fcbf026 rm 0xbce0f026, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0x2dd07252 rm 0xa5757252, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0x5e4b77c1 rm 0xf4a477c1, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0x464a3a21 rm 0x76723a21, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0xe8101105 rm 0x74d01105, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2 :: rd 0xcd903e2c rm 0xc1273e2c, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #0 :: rd 0x35236e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #1 :: rd 0x6a466e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #2 :: rd 0xd48c6e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #3 :: rd 0xa9196e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #4 :: rd 0x52326e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #8 :: rd 0x23206e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #12 :: rd 0x32046e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #16 :: rd 0x20476e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #24 :: rd 0x47006e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #31 :: rd 0x80006e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #0 :: rd 0x89d26261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #1 :: rd 0x13a56261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #2 :: rd 0x274b6261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #3 :: rd 0x4e976261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #4 :: rd 0x9d2e6261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #8 :: rd 0xd2ef6261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #12 :: rd 0x2ef86261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #16 :: rd 0xef866261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #24 :: rd 0x86006261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #31 :: rd 0x00006261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #0 :: rd 0x57a558cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #1 :: rd 0xaf4a58cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #2 :: rd 0x5e9458cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #3 :: rd 0xbd2858cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #4 :: rd 0x7a5058cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #8 :: rd 0xa50a58cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #12 :: rd 0x50a058cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #16 :: rd 0x0a0158cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #24 :: rd 0x010058cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #31 :: rd 0x800058cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #0 :: rd 0xf87b5407 rm 0xd5dc5407, rn 0xf87b961e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #1 :: rd 0x8c36b979 rm 0xd65db979, rn 0xc61b323b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #2 :: rd 0xb4b28abe rm 0xa3268abe, rn 0xed2cbf78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #3 :: rd 0x7db8f0a5 rm 0xbf73f0a5, rn 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #4 :: rd 0x25ef03ed rm 0x281703ed, rn 0x925ef472, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #8 :: rd 0x774152c7 rm 0xeaa652c7, rn 0x137741f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #12 :: rd 0x5bd2de8b rm 0x71fbde8b, rn 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #16 :: rd 0x821a0ad8 rm 0x884c0ad8, rn 0xc00b821a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #24 :: rd 0x69008606 rm 0xe1bb8606, rn 0x58293969, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #31 :: rd 0x8000d624 rm 0xa3cfd624, rn 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #0 :: rd 0x179194e2 rm 0x40b094e2, rn 0x17913309, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #1 :: rd 0x0cb0b5cd rm 0x5388b5cd, rn 0x86582032, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #2 :: rd 0x33e81558 rm 0x5de41558, rn 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #3 :: rd 0x21bc1b46 rm 0x23ba1b46, rn 0x4437983c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #4 :: rd 0x90856549 rm 0x48d06549, rn 0xa9085781, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #8 :: rd 0xaeadac58 rm 0xc6b4ac58, rn 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #12 :: rd 0x1e6af597 rm 0xc2bdf597, rn 0xdde1e6a4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #16 :: rd 0x0dea3a72 rm 0x852e3a72, rn 0x157b0dea, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #24 :: rd 0x740057b4 rm 0xe7aa57b4, rn 0x1584bd74, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhbt r0, r1, r2, lsl #31 :: rd 0x80004d54 rm 0xd4b64d54, rn 0xc53aaba9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #0 :: rd 0x11220000 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #1 :: rd 0x11223bc4 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #2 :: rd 0x11229de2 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #3 :: rd 0x1122cef1 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #4 :: rd 0x11226778 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #16 :: rd 0x11225566 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #22 :: rd 0x11220155 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #31 :: rd 0x11220000 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0x50c23709 rm 0x50c28082, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0x17960212 rm 0x17962e8f, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0xc5729bb5 rm 0xc57243b7, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0x7eb29fbf rm 0x7eb226ac, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0xbce0e5a9 rm 0xbce0f026, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0xa5751366 rm 0xa5757252, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0xf4a41cbf rm 0xf4a477c1, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0x767221cc rm 0x76723a21, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0x74d08f1b rm 0x74d01105, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2 :: rd 0xc127d604 rm 0xc1273e2c, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #0 :: rd 0x5f980000 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #1 :: rd 0x5f989023 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #2 :: rd 0x5f98c811 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #3 :: rd 0x5f986408 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #4 :: rd 0x5f983204 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #8 :: rd 0x5f982320 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #12 :: rd 0x5f985232 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #16 :: rd 0x5f983523 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #24 :: rd 0x5f980035 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #31 :: rd 0x5f980000 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #32 :: rd 0x5f980000 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #0 :: rd 0x36f2ffff rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #1 :: rd 0x36f277c3 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #2 :: rd 0x36f2bbe1 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #3 :: rd 0x36f25df0 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #4 :: rd 0x36f22ef8 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #8 :: rd 0x36f2d2ef rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #12 :: rd 0x36f29d2e rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #16 :: rd 0x36f289d2 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #24 :: rd 0x36f2ff89 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #31 :: rd 0x36f2ffff rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #32 :: rd 0x36f2ffff rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #0 :: rd 0x21610000 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #1 :: rd 0x21618500 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #2 :: rd 0x21614280 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #3 :: rd 0x2161a140 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #4 :: rd 0x216150a0 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #8 :: rd 0x2161a50a rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #12 :: rd 0x21617a50 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #16 :: rd 0x216157a5 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #24 :: rd 0x21610057 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #31 :: rd 0x21610000 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #32 :: rd 0x21610000 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #0 :: rd 0xd5dcffff rm 0xd5dc5407, rn 0xf87b961e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #1 :: rd 0xd65d991d rm 0xd65db979, rn 0xc61b323b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #2 :: rd 0xa3262fde rm 0xa3268abe, rn 0xed2cbf78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #3 :: rd 0xbf73e299 rm 0xbf73f0a5, rn 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #4 :: rd 0x2817ef47 rm 0x281703ed, rn 0x925ef472, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #8 :: rd 0xeaa67741 rm 0xeaa652c7, rn 0x137741f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #12 :: rd 0x71fbba5b rm 0x71fbde8b, rn 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #16 :: rd 0x884cc00b rm 0x884c0ad8, rn 0xc00b821a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #24 :: rd 0xe1bb0058 rm 0xe1bb8606, rn 0x58293969, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #31 :: rd 0xa3cf0000 rm 0xa3cfd624, rn 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #32 :: rd 0xa3cf0000 rm 0xa3cfd624, rn 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #0 :: rd 0x40b00000 rm 0x40b094e2, rn 0x17913309, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #1 :: rd 0x53881019 rm 0x5388b5cd, rn 0x86582032, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #2 :: rd 0x5de4871f rm 0x5de41558, rn 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #3 :: rd 0x23baf307 rm 0x23ba1b46, rn 0x4437983c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #4 :: rd 0x48d08578 rm 0x48d06549, rn 0xa9085781, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #8 :: rd 0xc6b4aead rm 0xc6b4ac58, rn 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #12 :: rd 0xc2bdde1e rm 0xc2bdf597, rn 0xdde1e6a4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #16 :: rd 0x852e157b rm 0x852e3a72, rn 0x157b0dea, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #24 :: rd 0xe7aa0015 rm 0xe7aa57b4, rn 0x1584bd74, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #31 :: rd 0xd4b6ffff rm 0xd4b64d54, rn 0xc53aaba9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +pkhtb r0, r1, r2, asr #32 :: rd 0xd4b6ffff rm 0xd4b64d54, rn 0xc53aaba9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- USAT ----------------- +usat r0, #0, r1 :: rd 0x00000000 rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #1, r1 :: rd 0x00000001 rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #5, r1 :: rd 0x0000001f rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #8, r1 :: rd 0x000000ff rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #11, r1 :: rd 0x000007ff rm 0x11110000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #13, r1 :: rd 0x00001fff rm 0x11110000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #15, r1 :: rd 0x00007fff rm 0x11110000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, lsl #0 :: rd 0x5f986e68 rm 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #31, r1, lsl #0 :: rd 0x00000000 rm 0xe7aa57b4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, lsl #0 :: rd 0x00000000 rm 0x89d2ef86, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, lsl #8 :: rd 0x3aaba900 rm 0xc53aaba9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #31, r1, lsl #8 :: rd 0x6158cb00 rm 0x216158cb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #31, r1, lsl #8 :: rd 0x00000000 rm 0x3cd6cd94, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, lsl #0 :: rd 0x00000000 rm 0xf87b961e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, lsl #0 :: rd 0x00000000 rm 0xc61b323b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, lsl #0 :: rd 0x00000000 rm 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, lsl #8 :: rd 0x00000000 rm 0xbf73f0a5, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, lsl #8 :: rd 0x00000000 rm 0x925ef472, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, lsl #8 :: rd 0x00000000 rm 0x137741f4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #24, r1, lsl #2 :: rd 0x00ffffff rm 0x50c28082, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #16, r1, lsl #3 :: rd 0x00000000 rm 0x17962e8f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #12, r1, lsl #4 :: rd 0x00000fff rm 0xc57243b7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #8, r1, lsl #8 :: rd 0x000000ff rm 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #4, r1, lsl #12 :: rd 0x0000000f rm 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #3, r1, lsl #16 :: rd 0x00000007 rm 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #2, r1, lsl #24 :: rd 0x00000003 rm 0x728b7771, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #1, r1, lsl #31 :: rd 0x00000000 rm 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, asr #0 :: rd 0x5f986e68 rm 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #31, r1, asr #0 :: rd 0x00000000 rm 0xe7aa57b4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, asr #0 :: rd 0x00000000 rm 0x89d2ef86, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, asr #8 :: rd 0x00000000 rm 0xc53aaba9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, asr #8 :: rd 0x00216158 rm 0x216158cb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #31, r1, asr #8 :: rd 0x003cd6cd rm 0x3cd6cd94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xf87b961e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xc61b323b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0xbf73f0a5, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0x925ef472, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0x137741f4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #24, r1, asr #2 :: rd 0x00ffffff rm 0x50c28082, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #16, r1, asr #3 :: rd 0x0000ffff rm 0x17962e8f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #12, r1, asr #4 :: rd 0x00000000 rm 0xc57243b7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #8, r1, asr #8 :: rd 0x00000000 rm 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #4, r1, asr #12 :: rd 0x00000000 rm 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #3, r1, asr #16 :: rd 0x00000000 rm 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #2, r1, asr #24 :: rd 0x00000003 rm 0x728b7771, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #1, r1, asr #31 :: rd 0x00000000 rm 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, asr #0 :: rd 0x5f986e68 rm 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #31, r1, asr #0 :: rd 0x00000000 rm 0xe7aa57b4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, asr #0 :: rd 0x00000000 rm 0x89d2ef86, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, asr #8 :: rd 0x00000000 rm 0xc53aaba9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #31, r1, asr #8 :: rd 0x00216158 rm 0x216158cb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #31, r1, asr #8 :: rd 0x003cd6cd rm 0x3cd6cd94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xf87b961e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xc61b323b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0xbf73f0a5, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0x925ef472, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0x137741f4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #24, r1, asr #2 :: rd 0x00ffffff rm 0x50c28082, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #16, r1, asr #3 :: rd 0x0000ffff rm 0x17962e8f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #12, r1, asr #4 :: rd 0x00000000 rm 0xc57243b7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #8, r1, asr #8 :: rd 0x00000000 rm 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #4, r1, asr #12 :: rd 0x00000000 rm 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #3, r1, asr #16 :: rd 0x00000000 rm 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #2, r1, asr #24 :: rd 0x00000003 rm 0x728b7771, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat r0, #1, r1, asr #31 :: rd 0x00000000 rm 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +------------ USAT16 sat_imm ------------ +usat16 r0, #0, r1 :: rd 0x00000000 rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #1, r1 :: rd 0x00000000 rm 0xffcdabcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #5, r1 :: rd 0x001f0000 rm 0x0123feff, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #8, r1 :: rd 0x00ff0000 rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #11, r1 :: rd 0x07ff0000 rm 0x11110000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #13, r1 :: rd 0x11110000 rm 0x1111f111, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #15, r1 :: rd 0x00001111 rm 0x00001111, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat16 r0, #0, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #1, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #3, r1 :: rd 0x00070000 rm 0x50c28082, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #5, r1 :: rd 0x001f001f rm 0x17962e8f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #8, r1 :: rd 0x000000ff rm 0xc57243b7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #10, r1 :: rd 0x00000000 rm 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #11, r1 :: rd 0x000007ff rm 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #13, r1 :: rd 0x00001fff rm 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #14, r1 :: rd 0x3fff3fff rm 0x728b7771, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #15, r1 :: rd 0x000020f3 rm 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #0, r1 :: rd 0x00000000 rm 0x86398371, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #1, r1 :: rd 0x00010000 rm 0x03d0fb78, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #3, r1 :: rd 0x00000000 rm 0xd0d49b7c, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #5, r1 :: rd 0x001f001f rm 0x76354a58, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #8, r1 :: rd 0x000000ff rm 0x9fa45fb7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #10, r1 :: rd 0x03ff0000 rm 0x7572bdec, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #11, r1 :: rd 0x00000000 rm 0xfea59eb6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #13, r1 :: rd 0x00000000 rm 0xf2669090, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #14, r1 :: rd 0x00000000 rm 0xbc1ff573, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #15, r1 :: rd 0x7eb226ac rm 0x7eb226ac, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usat16 r0, #0, r1 :: rd 0x00000000 rm 0x22b65db1, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #1, r1 :: rd 0x00010001 rm 0x776c41c7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #3, r1 :: rd 0x00000000 rm 0xe50dd77c, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #5, r1 :: rd 0x00000000 rm 0xd6f9a698, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #8, r1 :: rd 0x000000ff rm 0xeda5110c, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #10, r1 :: rd 0x03ff03ff rm 0x0be36f70, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #11, r1 :: rd 0x00000000 rm 0xd759eb72, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #13, r1 :: rd 0x00000000 rm 0xd9c4b1f4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #14, r1 :: rd 0x00000000 rm 0xa29eb320, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #15, r1 :: rd 0x00004487 rm 0xcf1e4487, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #0, r1 :: rd 0x00000000 rm 0x2eb68500, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #1, r1 :: rd 0x00000000 rm 0xcdb7ed11, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #3, r1 :: rd 0x00070000 rm 0x2eaea305, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #5, r1 :: rd 0x001f001f rm 0x6ebd04d9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #8, r1 :: rd 0x000000ff rm 0xa5ec1aa8, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #10, r1 :: rd 0x03ff03ff rm 0x72f33509, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #11, r1 :: rd 0x00000000 rm 0xa3e6f759, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #13, r1 :: rd 0x00000000 rm 0xfaceab39, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #14, r1 :: rd 0x27380000 rm 0x2738f0ff, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #15, r1 :: rd 0x00000000 rm 0xe79fd570, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #0, r1 :: rd 0x00000000 rm 0x55ea3e4e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #1, r1 :: rd 0x00010000 rm 0x2b62ba5a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #3, r1 :: rd 0x00000000 rm 0x9b41bfb1, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #5, r1 :: rd 0x001f001f rm 0x557c7ba2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #8, r1 :: rd 0x00ff0000 rm 0x2973c051, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #10, r1 :: rd 0x03ff0000 rm 0x6a228b19, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #11, r1 :: rd 0x07ff0000 rm 0x0cdafabe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #13, r1 :: rd 0x1fff1fff rm 0x50865114, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #14, r1 :: rd 0x00000000 rm 0xd83b849b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +usat16 r0, #15, r1 :: rd 0x00005605 rm 0xca5e5605, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +---------------- UADD16 ---------------- +uadd16 r0, r1, r2 :: rd 0x00210002 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x00210002 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x00020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x00020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x0000ffff rm 0x00000000, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x0000ffff rm 0x0000ffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x0000fffe rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x00010000 rm 0x00010000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x00010000 rm 0x00000000, rn 0x00010000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x00020000 rm 0x00010000, rn 0x00010000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0xffff0000 rm 0x00000000, rn 0xffff0000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0xffff0000 rm 0xffff0000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0xfffe0000 rm 0xffff0000, rn 0xffff0000, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0xa299daa0 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x5d604bd2 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x915a7c18 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x24416b8a rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xf96272fb rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x0e34f4ba rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0xd14ed502 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0xc4a74327 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x164d7875 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xf06d4ac2 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0xa622c6c7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0xbc067e14 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xf988807c rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0xc318e39d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0x2a863276 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xba34e1af rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x9490883e rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x70c1dfbb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x77f5007b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0x3ae9b324 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x672fef32 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x67ae5b14 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0xfb099476 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0xc4f739a4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0xae6f11cf rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0x541b7a29 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x639faa4d rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x1713cd42 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x4a22ee8f rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x8f73708c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0x0ba1c6ef rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0x3c80c488 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x316e6d4e rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xed7176b3 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0x3919bcb5 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x1b2b3c05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0xdbc459b0 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xf8623908 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x7b31e04a rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x73302af1 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0xb6cee004 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uadd16 r0, r1, r2 :: rd 0x09dd64ff rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x428be5e7 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x0ac31feb rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xba32d245 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xa8fa218b rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x5c3d09b6 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd16 r0, r1, r2 :: rd 0x4ab260a3 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd16 r0, r1, r2 :: rd 0x01a8204f rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd16 r0, r1, r2 :: rd 0xe7f2fb84 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +---------------- SADD16 ---------------- +sadd16 r0, r1, r2 :: rd 0x00210002 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00210002 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x0000ffff rm 0x00000000, rn 0x0000ffff, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x0000ffff rm 0x0000ffff, rn 0x00000000, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x0000fffe rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00010000 rm 0x00010000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00010000 rm 0x00000000, rn 0x00010000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x00020000 rm 0x00010000, rn 0x00010000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0xffff0000 rm 0x00000000, rn 0xffff0000, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0xffff0000 rm 0xffff0000, rn 0x00000000, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0xfffe0000 rm 0xffff0000, rn 0xffff0000, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0xa299daa0 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0x5d604bd2 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x915a7c18 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x24416b8a rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0xf96272fb rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0x0e34f4ba rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0xd14ed502 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0xc4a74327 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x164d7875 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0xf06d4ac2 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0xa622c6c7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0xbc067e14 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0xf988807c rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0xc318e39d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0x2a863276 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0xba34e1af rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0x9490883e rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0x70c1dfbb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x77f5007b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0x3ae9b324 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0x672fef32 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x67ae5b14 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0xfb099476 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0xc4f739a4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0xae6f11cf rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0x541b7a29 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x639faa4d rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0x1713cd42 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x4a22ee8f rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x8f73708c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0x0ba1c6ef rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x3c80c488 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x316e6d4e rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0xed7176b3 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0x3919bcb5 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x1b2b3c05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0xdbc459b0 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0xf8623908 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd16 r0, r1, r2 :: rd 0x7b31e04a rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0x73302af1 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0xb6cee004 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0x09dd64ff rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x428be5e7 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd16 r0, r1, r2 :: rd 0x0ac31feb rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0xba32d245 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0xa8fa218b rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd16 r0, r1, r2 :: rd 0x5c3d09b6 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x4ab260a3 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0x01a8204f rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd16 r0, r1, r2 :: rd 0xe7f2fb84 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +---------------- USUB16 ---------------- +usub16 r0, r1, r2 :: rd 0x01000011 rm 0x04000022, rn 0x03000011, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0xfff1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0x000f0004 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x0004000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0xfffcfff1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x0000ffff rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x0000ffff, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x0000ffff rm 0x0000ffff, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x00000000 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x00010000 rm 0x00010000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0xffff0000 rm 0x00000000, rn 0x00010000, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0x00000000 rm 0x00010000, rn 0x00010000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x00010000 rm 0x00000000, rn 0xffff0000, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0xffff0000 rm 0xffff0000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x00000000 rm 0xffff0000, rn 0xffff0000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x0ddd2e96 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0xbd1665e6 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0xd15beae8 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x4e6a7bb7 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0xd7b27558 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0x7a8a604e rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x18d3c68b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x470fcd95 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0x54ff70a0 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0x48b6bcc7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x0e1430e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x1e3e5e64 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0x14660cb9 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x76fece8e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0x74f87b6f rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0xf654ff30 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0x8ca36d9d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0x01cbdfd1 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x10013180 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x82190050 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x8536192e rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0xee978d94 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0xbd5742b4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x0cc7dad7 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x67b1e579 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x2457eadf rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x2c2f516a rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x4cd8b123 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0xaaa74f6c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0x9363dc09 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0xd3c2f4bc rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0xb2fcbe52 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0xf7170bfd rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0x11bd3ef7 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0x6529dc05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x009aef2c rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x36ec7b38 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub16 r0, r1, r2 :: rd 0xc931cb82 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0xae920223 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0x654244dc rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0x333f9e0b rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x1ea1fc75 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0xf4bf49d3 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x0e56e605 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x64da14c9 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub16 r0, r1, r2 :: rd 0x2ce16b08 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x4b66e5cb rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub16 r0, r1, r2 :: rd 0xf0929e5d rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub16 r0, r1, r2 :: rd 0x081e8b18 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +---------------- SSUB16 ---------------- +ssub16 r0, r1, r2 :: rd 0x01000011 rm 0x04000022, rn 0x03000011, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0xfff1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0x000f0004 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x0004000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0xfffcfff1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x0000ffff rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x0000ffff, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x0000ffff rm 0x0000ffff, rn 0x00000000, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x00000000 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x00010000 rm 0x00010000, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0xffff0000 rm 0x00000000, rn 0x00010000, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x00000000 rm 0x00010000, rn 0x00010000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x00010000 rm 0x00000000, rn 0xffff0000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0xffff0000 rm 0xffff0000, rn 0x00000000, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x00000000 rm 0xffff0000, rn 0xffff0000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x0ddd2e96 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0xbd1665e6 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0xd15beae8 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0x4e6a7bb7 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0xd7b27558 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x7a8a604e rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x18d3c68b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x470fcd95 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x54ff70a0 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x48b6bcc7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x0e1430e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x1e3e5e64 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x14660cb9 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x76fece8e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x74f87b6f rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0xf654ff30 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0x8ca36d9d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x01cbdfd1 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x10013180 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x82190050 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x8536192e rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0xee978d94 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0xbd5742b4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x0cc7dad7 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x67b1e579 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0x2457eadf rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x2c2f516a rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x4cd8b123 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0xaaa74f6c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x9363dc09 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0xd3c2f4bc rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0xb2fcbe52 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0xf7170bfd rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x11bd3ef7 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x6529dc05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0x009aef2c rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x36ec7b38 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0xc931cb82 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0xae920223 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x654244dc rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x333f9e0b rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub16 r0, r1, r2 :: rd 0x1ea1fc75 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0xf4bf49d3 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x0e56e605 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0x64da14c9 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x2ce16b08 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub16 r0, r1, r2 :: rd 0x4b66e5cb rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub16 r0, r1, r2 :: rd 0xf0929e5d rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub16 r0, r1, r2 :: rd 0x081e8b18 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +---------------- UADD8 ----------------- +uadd8 r0, r1, r2 :: rd 0x0021ff02 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +uadd8 r0, r1, r2 :: rd 0x0021ff02 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +uadd8 r0, r1, r2 :: rd 0xff020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +uadd8 r0, r1, r2 :: rd 0xff020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +uadd8 r0, r1, r2 :: rd 0xff000221 rm 0x00000318, rn 0xff00ff09, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +uadd8 r0, r1, r2 :: rd 0xff020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +uadd8 r0, r1, r2 :: rd 0xff090221 rm 0x00020318, rn 0xff07ff09, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +uadd8 r0, r1, r2 :: rd 0xff090221 rm 0xff07ff09, rn 0x00020318, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +uadd8 r0, r1, r2 :: rd 0xa299daa0 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +uadd8 r0, r1, r2 :: rd 0x5c604bd2 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +uadd8 r0, r1, r2 :: rd 0x915a7b18 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +uadd8 r0, r1, r2 :: rd 0x23416b8a rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +uadd8 r0, r1, r2 :: rd 0xf86272fb rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +uadd8 r0, r1, r2 :: rd 0x0d34f4ba rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +uadd8 r0, r1, r2 :: rd 0xd04ed402 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +uadd8 r0, r1, r2 :: rd 0xc3a74227 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +uadd8 r0, r1, r2 :: rd 0x154d7875 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +uadd8 r0, r1, r2 :: rd 0xef6d4ac2 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +uadd8 r0, r1, r2 :: rd 0xa522c6c7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +uadd8 r0, r1, r2 :: rd 0xbb067d14 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd8 r0, r1, r2 :: rd 0xf888807c rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +uadd8 r0, r1, r2 :: rd 0xc218e39d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +uadd8 r0, r1, r2 :: rd 0x29863176 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +uadd8 r0, r1, r2 :: rd 0xb934e1af rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +uadd8 r0, r1, r2 :: rd 0x9490873e rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +uadd8 r0, r1, r2 :: rd 0x70c1dfbb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +uadd8 r0, r1, r2 :: rd 0x77f5007b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +uadd8 r0, r1, r2 :: rd 0x3ae9b224 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +uadd8 r0, r1, r2 :: rd 0x662fee32 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +uadd8 r0, r1, r2 :: rd 0x67ae5a14 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +uadd8 r0, r1, r2 :: rd 0xfa099476 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +uadd8 r0, r1, r2 :: rd 0xc4f739a4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +uadd8 r0, r1, r2 :: rd 0xad6f11cf rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +uadd8 r0, r1, r2 :: rd 0x531b7929 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +uadd8 r0, r1, r2 :: rd 0x629fa94d rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +uadd8 r0, r1, r2 :: rd 0x1613cc42 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +uadd8 r0, r1, r2 :: rd 0x4922ed8f rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +uadd8 r0, r1, r2 :: rd 0x8f736f8c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +uadd8 r0, r1, r2 :: rd 0x0ba1c6ef rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +uadd8 r0, r1, r2 :: rd 0x3c80c388 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +uadd8 r0, r1, r2 :: rd 0x316e6c4e rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +uadd8 r0, r1, r2 :: rd 0xed7176b3 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +uadd8 r0, r1, r2 :: rd 0x3819bbb5 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +uadd8 r0, r1, r2 :: rd 0x1b2b3c05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +uadd8 r0, r1, r2 :: rd 0xdbc459b0 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +uadd8 r0, r1, r2 :: rd 0xf7623808 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +uadd8 r0, r1, r2 :: rd 0x7b31df4a rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +uadd8 r0, r1, r2 :: rd 0x72302af1 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +uadd8 r0, r1, r2 :: rd 0xb6cedf04 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +uadd8 r0, r1, r2 :: rd 0x09dd64ff rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +uadd8 r0, r1, r2 :: rd 0x418be5e7 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +uadd8 r0, r1, r2 :: rd 0x0ac31feb rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +uadd8 r0, r1, r2 :: rd 0xb932d245 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +uadd8 r0, r1, r2 :: rd 0xa8fa218b rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +uadd8 r0, r1, r2 :: rd 0x5b3d09b6 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +uadd8 r0, r1, r2 :: rd 0x4ab260a3 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +uadd8 r0, r1, r2 :: rd 0x01a81f4f rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +uadd8 r0, r1, r2 :: rd 0xe7f2fb84 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +---------------- USUB8 ----------------- +usub8 r0, r1, r2 :: rd 0x00f1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +usub8 r0, r1, r2 :: rd 0x000f0104 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub8 r0, r1, r2 :: rd 0x0104000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub8 r0, r1, r2 :: rd 0xfffc00f1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +usub8 r0, r1, r2 :: rd 0x0100040f rm 0x00000318, rn 0xff00ff09, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +usub8 r0, r1, r2 :: rd 0xfffc00f1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +usub8 r0, r1, r2 :: rd 0x01fb040f rm 0x00020318, rn 0xff07ff09, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +usub8 r0, r1, r2 :: rd 0xff05fcf1 rm 0xff07ff09, rn 0x00020318, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +usub8 r0, r1, r2 :: rd 0x0edd2e96 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +usub8 r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +usub8 r0, r1, r2 :: rd 0xbd1665e6 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +usub8 r0, r1, r2 :: rd 0xd15bebe8 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub8 r0, r1, r2 :: rd 0x4e6a7cb7 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +usub8 r0, r1, r2 :: rd 0xd7b27658 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +usub8 r0, r1, r2 :: rd 0x7a8a604e rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +usub8 r0, r1, r2 :: rd 0x19d3c68b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +usub8 r0, r1, r2 :: rd 0x470fce95 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +usub8 r0, r1, r2 :: rd 0x55ff70a0 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +usub8 r0, r1, r2 :: rd 0x49b6bcc7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +usub8 r0, r1, r2 :: rd 0x0f1431e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +usub8 r0, r1, r2 :: rd 0x1e3e5e64 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +usub8 r0, r1, r2 :: rd 0x14660db9 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +usub8 r0, r1, r2 :: rd 0x77fecf8e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub8 r0, r1, r2 :: rd 0x75f87b6f rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +usub8 r0, r1, r2 :: rd 0xf654ff30 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +usub8 r0, r1, r2 :: rd 0x8ca36d9d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +usub8 r0, r1, r2 :: rd 0x01cbe0d1 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +usub8 r0, r1, r2 :: rd 0x10013280 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +usub8 r0, r1, r2 :: rd 0x82190050 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +usub8 r0, r1, r2 :: rd 0x85361a2e rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +usub8 r0, r1, r2 :: rd 0xee978e94 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +usub8 r0, r1, r2 :: rd 0xbe5743b4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +usub8 r0, r1, r2 :: rd 0x0dc7dbd7 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +usub8 r0, r1, r2 :: rd 0x67b1e579 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +usub8 r0, r1, r2 :: rd 0x2457ebdf rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub8 r0, r1, r2 :: rd 0x2c2f526a rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +usub8 r0, r1, r2 :: rd 0x4dd8b123 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +usub8 r0, r1, r2 :: rd 0xaba74f6c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +usub8 r0, r1, r2 :: rd 0x9363dc09 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +usub8 r0, r1, r2 :: rd 0xd4c2f5bc rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub8 r0, r1, r2 :: rd 0xb3fcbe52 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +usub8 r0, r1, r2 :: rd 0xf7170cfd rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +usub8 r0, r1, r2 :: rd 0x12bd3ff7 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +usub8 r0, r1, r2 :: rd 0x6529dc05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +usub8 r0, r1, r2 :: rd 0x019aef2c rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +usub8 r0, r1, r2 :: rd 0x37ec7c38 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +usub8 r0, r1, r2 :: rd 0xc931cb82 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +usub8 r0, r1, r2 :: rd 0xae920223 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +usub8 r0, r1, r2 :: rd 0x664245dc rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +usub8 r0, r1, r2 :: rd 0x333f9e0b rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +usub8 r0, r1, r2 :: rd 0x1fa1fd75 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +usub8 r0, r1, r2 :: rd 0xf4bf49d3 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +usub8 r0, r1, r2 :: rd 0x0f56e605 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +usub8 r0, r1, r2 :: rd 0x64da15c9 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +usub8 r0, r1, r2 :: rd 0x2de16b08 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +usub8 r0, r1, r2 :: rd 0x4c66e6cb rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usub8 r0, r1, r2 :: rd 0xf1929f5d rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +usub8 r0, r1, r2 :: rd 0x091e8b18 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +---------------- QADD16 ---------------- +qadd16 r0, r1, r2 :: rd 0x00210002 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x00210002 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x00020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x00020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xa299daa0 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x5d604bd2 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x7fff8000 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x24418000 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xf96272fb rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x0e34f4ba rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xd14ed502 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x7fff4327 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x164d8000 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xf06d4ac2 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x7fffc6c7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xbc068000 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xf9887fff rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xc318e39d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x2a868000 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xba34e1af rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x94907fff rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x70c1dfbb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x8000007b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x80007fff rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x672f7fff rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x67ae5b14 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xfb099476 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xc4f739a4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xae6f11cf rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x541b7a29 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x80007fff rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x1713cd42 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x4a22ee8f rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x8f738000 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x0ba1c6ef rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x3c807fff rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x316e8000 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xed718000 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x3919bcb5 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x1b2b3c05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xdbc48000 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xf8623908 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x8000e04a rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x73308000 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xb6cee004 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x09dd64ff rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x428be5e7 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x0ac31feb rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xba32d245 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xa8fa8000 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x5c3d09b6 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x4ab260a3 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0x01a8204f rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd16 r0, r1, r2 :: rd 0xe7f2fb84 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +---------------- QSUB16 ---------------- +qsub16 r0, r1, r2 :: rd 0xfff1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x000f0004 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x0004000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xfffcfff1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x0ddd8000 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xbd1665e6 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xd15beae8 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x80008000 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x7fff7558 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x8000604e rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x18d3c68b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x470fcd95 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x54ff70a0 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x48b67fff rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x0e1430e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x1e3e5e64 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x14660cb9 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x76fece8e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x74f87b6f rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xf654ff30 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x7fff6d9d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x01cbdfd1 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x10013180 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x82190050 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x7fff192e rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x7fff7fff rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xbd5742b4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x0cc77fff rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x8000e579 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x2457eadf rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x8000516a rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x4cd87fff rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xaaa74f6c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x7fffdc09 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xd3c2f4bc rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xb2fcbe52 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xf7170bfd rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x11bd3ef7 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x8000dc05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x009aef2c rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x80008000 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xc931cb82 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xae920223 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x65428000 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x80009e0b rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x1ea1fc75 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xf4bf49d3 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x0e56e605 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x64da14c9 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x2ce16b08 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x4b66e5cb rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0xf0927fff rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub16 r0, r1, r2 :: rd 0x081e7fff rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- QSAX ----------------- +qsax r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7ffe7fff rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x80018000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x00610067 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xff9f0067 rm 0x00030003, rn 0x00640064, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x82368000 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xbbc64b44 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7fff5b21 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x3a7dd4ac rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x80004cd5 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7fffd04a rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xeb92460a rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x306f5ac3 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x593e8aa4 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x35a52b68 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7fff707d rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x3e75ae75 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xfad75d15 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x004dcf84 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7fff8000 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x6476d12d rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x80eb12d5 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7fff18bb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xac8bab3b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x800007c6 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x80007fff rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x557f2b5d rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7fff973e rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xc5af41fc rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x421f4727 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x938e7fff rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x8000ea3a rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xe3b57fff rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7fff4e7e rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x0c7dd262 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x5a0f8d9b rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xa03b7fff rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x1ab7d509 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x3ce9bc85 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x668c1184 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x902a6706 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x38ed9203 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x80003adb rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x97cdaee6 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7c7af8d9 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xc0748000 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x80006cd4 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x3bdd0323 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x14b53fe1 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0xee24b213 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7fff8000 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x7538520d rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x0da022dd rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x382467e1 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsax r0, r1, r2 :: rd 0x3fd23338 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- QASX ----------------- +qasx r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x7fff7ffe rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x80008001 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x00670061 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x0067ff9f rm 0x00030003, rn 0x00640064, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x2e40ba3d rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x5deeaa38 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xb25186dd rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xbb1f81c6 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x1f88a1dd rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x32a47fff rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x8000ef46 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x7fffaeef rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x041ebb66 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x0fc77fff rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xfc6c1311 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x8ba50083 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x1cef7fff rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xd73120d2 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x02b6a6be rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xcab67fff rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x09f97499 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x37c1349d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xcd353511 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xe6477fff rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x6c150536 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x7fff48e5 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xf8417fff rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xbc9f3a5c rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x80007fff rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x283eb99c rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x23b27fff rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x800099e4 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xea335134 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x8000ed96 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x44f5155d rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x70072843 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xc9b38000 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xa79fc62b rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xe44aea28 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xf02ab104 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xa371b6d9 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xf68f8000 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xac95fce6 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xa5488000 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x5b9ce9aa rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x02089636 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x254fdf39 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xeacd29dd rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xda640637 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x8d4bf91a rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x13e622b1 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0x7fff2391 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xba1656cb rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qasx r0, r1, r2 :: rd 0xb03e5364 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SASX ----------------- +sasx r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x80007ffe rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0x7fff8001 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0x00670061 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x0067ff9f rm 0x00030003, rn 0x00640064, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0x2e40ba3d rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0x5deeaa38 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0xb25186dd rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xbb1f81c6 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0x1f88a1dd rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0x32a499c8 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x6046ef46 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xad0baeef rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0x041ebb66 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0x0fc78ffa rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0xfc6c1311 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x8ba50083 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x1cef81cb rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0xd73120d2 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x02b6a6be rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0xcab68bf1 rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x09f97499 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x37c1349d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0xcd353511 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0xe647dcde rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x6c150536 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x976548e5 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0xf8418acc rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0xbc9f3a5c rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x7917a57f rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x283eb99c rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0x23b2aaf2 rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x5f8d99e4 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xea335134 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x2d9ded96 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0x44f5155d rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x70072843 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0xc9b35697 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xa79fc62b rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xe44aea28 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xf02ab104 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xa371b6d9 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xf68f7965 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xac95fce6 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0xa548343b rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0x5b9ce9aa rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0x02089636 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0x254fdf39 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sasx r0, r1, r2 :: rd 0xeacd29dd rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0xda640637 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0x8d4bf91a rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sasx r0, r1, r2 :: rd 0x13e622b1 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0x88782391 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sasx r0, r1, r2 :: rd 0xba1656cb rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sasx r0, r1, r2 :: rd 0xb03e5364 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +----------------- SMUAD ----------------- +smuad r0, r1, r2 :: rd 0x80000000 rm 0x80008000, rn 0x80008000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x0000fffe rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x00010000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x00000258 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x00000003 rm 0xffffffff, rn 0xfffc0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x00002fe2 rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xdede9cb1 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x02608ef4 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x171c6357 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x143f9593 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xdd110aba rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xc570b2ec rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xe97b9768 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x265801e0 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x0b037b42 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xf240a3db rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xf62fb1c8 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x12780145 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x0691798f rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x03d85a8d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x1acea470 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xe96a4974 rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x1d4ea2dd rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xee624082 rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x110f3afe rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x42a15948 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x32ca703d rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x00a6620b rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xc026f485 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xfdf6ad50 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xd7e10590 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xfe23ce76 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x327a6d06 rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xd0bf2ffa rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xe1415fd7 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x13319aee rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xecd5df72 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x27421fcb rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x0d65652d rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x1287343c rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x036d5124 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xeb8f9e2a rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x1c044eb7 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xca87d3fd rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x0c9512d8 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x32ceb0f5 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xda0472f0 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xd7be7034 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x040f97cc rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xfba979f6 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x05f0ddd8 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x2d5e498a rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xfb3f197b rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0x085893fc rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xe84c6565 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuad r0, r1, r2 :: rd 0xeda071c4 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SMUADX ---------------- +smuadx r0, r1, r2 :: rd 0x80000000 rm 0x80008000, rn 0x80008000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x0000fffe rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x00010000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x00000258 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x00000003 rm 0xffffffff, rn 0xfffc0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x00002fe2 rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x0c7d0a11 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x026a9a7c rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xe7ded456 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xf390e6c9 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xd0a195a8 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xce40b14c rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x1d063948 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x1c93fef0 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x0117f53b rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xeb07829d rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xd29fa17a rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x0fe7ad54 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xf8cd24d4 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x02deb401 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xfa6bb070 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xe7ef0f02 rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xe3654f90 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xdac8ea82 rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xfffc2b7e rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xb97e8122 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x3048302f rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x0be45ef2 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xbf1167ed rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x0209cf08 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xf7b39cd0 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x0c2cff55 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xcd7c2f85 rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x1f64ffb8 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xe2e395bb rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x2cc61db8 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x090e8f6a rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x163fdcc4 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xe7f54466 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x052f76a4 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xf6506ba9 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xf84db305 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x0bca2d24 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xcb0116b8 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x029b3b24 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xd068271d rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x29954740 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xdac588b7 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xfcd1f36c rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x024b26ca rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x06f653e6 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x21b7614a rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xf85e232b rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x11f523ba rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0x04e080e7 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smuadx r0, r1, r2 :: rd 0xfe0168fc rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SMLAD ----------------- +smlad r0, r1, r2, r3 :: rd 0x80000000 rm 0x80008000, rn 0x80008000 rs 0x00000000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x0000ffff rm 0x7fff7fff, rn 0x00010001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x0001001f rm 0x80008000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x00000278 rm 0x00640064, rn 0x00030003 rs 0x00000020, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x00000102 rm 0xffffffff, rn 0xfffc0001 rs 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x000030e2 rm 0xfff70fff, rn 0x00030003 rs 0x00000100, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x62e906cb rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xbdfa058d rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x132facec rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x94fd1e4f rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xd3a8b06c rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xfed933b9 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xbfb7c8c7 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x87826758 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xe9176301 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x23a346d9 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xaa26f4cc rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x18a2cb54 rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x7b87d52b rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x090f2dfd rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x516de33a rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xf5860663 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xc743547a rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x8f412c7f rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x5b9a2a7c rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x3e1eae90 rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x460a7598 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x9ce3256b rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x2f2d1057 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xdb70b536 rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x47476ea7 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xa98d7719 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x8e608a4b rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xe66cced8 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xe9e21a30 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xd4d7fe4a rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x5607de5f rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x84b77889 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x949f6c87 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x39036479 rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x9a767683 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x21c2fb62 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x2473a541 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x18d37e68 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x42a38017 rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x591d6066 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x8a977ce3 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x7cb70fa8 rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x116c76e8 rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x6a0f70ed rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x17c9dd9b rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xa4a1fbcf rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x7beb0ad6 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x183c60b5 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x00b7b139 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0xc79bbb47 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlad r0, r1, r2, r3 :: rd 0x0f5e5bec rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SMLADX ----------------- +smladx r0, r1, r2, r3 :: rd 0x80000000 rm 0x80008000, rn 0x80008000 rs 0x00000000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0x0000ffff rm 0x7fff7fff, rn 0x00010001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0x0001001f rm 0x80008000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0x00000278 rm 0x00640064, rn 0x00030003 rs 0x00000020, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0x00000102 rm 0xffffffff, rn 0xfffc0001 rs 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0x000030e2 rm 0xfff70fff, rn 0x00030003 rs 0x00000100, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0x5639ee73 rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0xc5eafef5 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smladx r0, r1, r2, r3 :: rd 0x39ba1d8c rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ SMLABB, SMLATT, SMLATB, SMLABT ------------ +smlabb r0, r1, r2, r3 :: rd 0x00000000 rm 0x00030000, rn 0x00040000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x00008001 rm 0x00030001, rn 0x00040002 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xc0015ffe rm 0x00038001, rn 0x00047fff rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x3fff8000 rm 0x00037fff, rn 0x00047fff rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x7fff8000 rm 0x0003ffff, rn 0x0004ffff rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x00000003 rm 0x0003fffc, rn 0x0004ffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x54dcfca7 rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xb9bef227 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x153b4744 rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x8a0c31fb rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xd4e3d8d4 rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x084deed9 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xb44a4e42 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x78bba4e4 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xe370e823 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x248056d7 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xa0bc6afd rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x30935611 rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x8b5b77e1 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x04dde729 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x530d7e10 rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xdb5218a5 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xb6e8d187 rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xaf23f094 rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x6606bb89 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x5ba1b213 rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x45c47d16 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x9e30058b rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x56df2997 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xd2991046 rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x3dc259b1 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x96166d79 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x8636392e rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xe7b29f81 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x08a72bb8 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x9ea9e2ca rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x4075d0f7 rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x8e7e199f rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xb4ec51d4 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x56fd0b6f rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x7f33d7e4 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x0666387a rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xf8578d3b rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x1f9f9fe0 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x63afa7cb rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x5960736c rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x88c74551 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x79890b42 rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xff6a0b78 rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x50b1bfe3 rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x1badfbcb rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x93c2e0ef rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x88604d49 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x458622b3 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x232dd133 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0xc928c69c rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabb r0, r1, r2, r3 :: rd 0x04300a90 rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x00000000 rm 0x00000003, rn 0x00000004 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x00008001 rm 0x00010003, rn 0x00020004 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xc0015ffe rm 0x80010003, rn 0x7fff0004 rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x3fff8000 rm 0x7fff0003, rn 0x7fff0004 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x7fff8000 rm 0xffff0003, rn 0xffff0004 rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x00000003 rm 0xfffc0003, rn 0xffff0004 rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x6da4788c rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xaf1e56a5 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x29fc0b5c rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x94c3dbda rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xd37b24ec rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x018e0a6a rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xbc3f81fc rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x8cfe240c rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xdb82cee5 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xf1d93837 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xb7fd93e9 rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x17c68a0c rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x9352e808 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xf3cfe6ad rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x3c1a768e rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xf5d9aae3 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x98a68dcb rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x7a6d2da3 rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x76f4dc06 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x42f4f79c rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x40f68d64 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x90a0e1fd rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x3881ee4d rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xd5d1c16e rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x52557a3f rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xc625b6c1 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x8d588b8f rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xe672ad90 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xe692b574 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xb7b56582 rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x525ce15f rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x7c355080 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x68f68a3b rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x1b138539 rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x9ba81adf rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x2d19cab9 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x10b5b3f8 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x1c472748 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x36598a4f rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x69a8ef0c rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x8b6dc924 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x82f9ea0f rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x09b31cae rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x5fa7d2d6 rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xf19d6ecb rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x92f6d2bf rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0x674d4ded rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xefc97b3f rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xff440fb9 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xec1805b7 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatt r0, r1, r2, r3 :: rd 0xfd3e0a6b rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x00000000 rm 0x00000003, rn 0x00040000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x00008001 rm 0x00010003, rn 0x00040002 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xc0015ffe rm 0x80010003, rn 0x00047fff rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x3fff8000 rm 0x7fff0003, rn 0x00047fff rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x7fff8000 rm 0xffff0003, rn 0x0004ffff rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x00000003 rm 0xfffc0003, rn 0x0004ffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x680d6c2f rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xc35917c7 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x325b20bc rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x9d69f440 rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xd4370054 rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x091ff500 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xb21ff2d8 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x71f82a30 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xc9653619 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xf63f799a rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xa6679b89 rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x2a05361e rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x9a127c08 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xf5d1a121 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x3839dd9c rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xd3f4bd83 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x9aac6fb7 rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xa4e49fda rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x7a97a5c6 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x5311a34b rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x403f808c rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x9796e87b rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x6ab5581d rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xcefcb21e rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x3a5534e1 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xcf1a27e1 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x8b3fc986 rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xe7af6e55 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x004dd8e0 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x5045227f rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x4815eff7 rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x7852cb64 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x6abbe852 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x26e6b11f rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x82b6eeac rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x31fc8463 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xfc5bf193 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x2488f008 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x3b5c0f7b rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x7cc2fe64 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x5be18a33 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x7f17b6ab rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xff50e330 rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x686b554f rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xe327a38a rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x9751921f rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x6bdba395 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xf59d74c1 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0x3127286b rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xdf1acafc rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlatb r0, r1, r2, r3 :: rd 0xe263202d rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x00000000 rm 0x00030000, rn 0x00000004 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x00008001 rm 0x00030001, rn 0x00020004 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xc0015ffe rm 0x00038001, rn 0x7fff0004 rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x3fff8000 rm 0x00037fff, rn 0x7fff0004 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x7fff8000 rm 0x0003ffff, rn 0xffff0004 rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x00000003 rm 0x0003fffc, rn 0xffff0004 rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x4dc4f0ac rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xad752a6d rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x3366a284 rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x89f2ea60 rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xd5270eb0 rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xfd71063a rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xcf383f4e rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x84d50b52 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xcfb4740b rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xe68d7e29 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xbe862fdd rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x3354fb41 rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x79abb1e1 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xfdfd2861 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x440550e5 rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xdcc2b0a5 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xb1c7335b rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x5b8baa12 rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x575ff409 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x55d0c59a rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x3d8c3b46 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x8f1ce2fd rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x8376d405 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xe5b406ca rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x5014d953 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x9f18f9d5 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x86916f29 rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xe6e571eb rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x198e7544 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x617b7602 rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x43cc4e75 rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x8c12acf1 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xb774acb2 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x6a7e0a27 rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x725b4c55 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x081e00c5 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x094073e8 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x33268ce0 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x65e1c8d7 rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x6a26e9b4 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x89a610c0 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x9c151fa4 rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x09ee866e rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x4e05cb6e rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xfd99a3fb rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x9022f557 rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x94433a01 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x4b7f7e58 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0x1e7bf393 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xe9c0c3b9 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlabt r0, r1, r2, r3 :: rd 0xe521a181 rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ UQSUB8 ----------------------------------- +uqsub8 r0, r1, r2 :: rd 0x0000fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x000f0000 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x0000000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0xfffc0000 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x0000000f rm 0x00000318, rn 0xff00ff09, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0xfffc0000 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x0000000f rm 0x00020318, rn 0xff07ff09, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0xff05fc00 rm 0xff07ff09, rn 0x00020318, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00000000 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00003299 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x0000a51f rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x8c0f275c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x1e2e0000 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x72a40000 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x006d0000 rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00003f6a rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x50000000 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00a3007e rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00610c00 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x03000f00 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x4a001d1e rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00520000 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x30005000 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00000068 rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x60000061 rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x48180022 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x091d815b rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x002e003c rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00000754 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00004213 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x380007c7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x0000baee rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00000000 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x46ce0364 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x45000000 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x57009001 rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x29620000 rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x11000000 rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x2d004200 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x19273100 rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x008d6cc2 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x3423a500 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00003800 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00107b00 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x0000b100 rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x71000000 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x006f0000 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x35000000 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x37005289 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x99659500 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00943b00 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x008d1a55 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x280000f7 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x28470000 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x6c000000 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00341400 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x42641600 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00000000 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqsub8 r0, r1, r2 :: rd 0x00210084 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ UQADD8 ----------------------------------- +uqadd8 r0, r1, r2 :: rd 0x0021ffff rm 0x0009ffff, rn 0x001800aa, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x0021ffff rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffff0021 rm 0x00aa0018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffff0021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xff00ff21 rm 0x0000aa18, rn 0xff00ff09, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffff0021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffffff rm 0xff9fefcc, rn 0xff9ffedd, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xff09ff21 rm 0xff07ff09, rn 0xaa020318, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xff0fffff rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xbeffb8ff rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x5effa5ff rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x90ff299c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x3432cdc1 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xeeff22ff rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffff78ff rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffcfd4 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xfffffbc2 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xa0ffffff rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffffff rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x77ff13e4 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffff98 rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xfff0ffff rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xd2ff8aa8 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x10bbffff rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffff9b rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x78504af8 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffffcd rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xc0ffffff rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x71ffffff rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffd617 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x9ea63dc7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffecff rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xc3ffff97 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xfff4d378 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xcdc8fdff rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xc90fe85f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffe0ffff rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xefffffdf rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x4fff50ff rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xd5ff95ff rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffa5caff rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x7a49ffff rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xe4fffff3 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffbae90c rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x6afeb51c rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x77ff9dd8 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffcbffff rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xfffff5ff rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x91ff78ff rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xfffbcdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x8aff7dff rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffadff8b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffffff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xff75ffff rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffd290ff rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xf9ffffdd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0x7c8a906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xddcb39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uqadd8 r0, r1, r2 :: rd 0xffffdbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ SEL -------------------------------------- +sel r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x00010001 rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xffffffff rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x00030003 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xffff0001 rm 0xfffcffff, rn 0xffff0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x00030003 rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xce0ce1ed rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xaae3433f rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x32fa0095 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x02c90120 rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x0b02c58a rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x3e2e1bd7 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xdd914bf7 rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xf2b64835 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x5ef1f1a8 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x815bb75b rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xef9e9fd9 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x3ada0280 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x90f9833d rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x9a4ff1b8 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x51f31d95 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x0872f25a rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x91edc21d rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x181c436b rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xe7b87e39 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x82aceb7a rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x6cc9bfa8 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x81874a02 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x33921b00 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xd7ce1909 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x85fbf196 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x6e13680a rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x44858efc rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x390d2c2f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x953ff6ec rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x6ffed89f rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x11bd07d1 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x5e6e32dd rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xec0c2f30 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x231348c0 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x95bca5d8 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xc1553709 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x69ec0212 rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x03fa9bb5 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xf52e9fbf rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x7fcbe5a9 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x2dd01366 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x5e4b1cbf rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x464a21cc rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xe8108f1b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xcd90d604 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x8217b7df rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x7acb4de3 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x868e7c7d rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x1d133d3d rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0x8f6d3264 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sel r0, r1, r2 :: rd 0xde99ac2f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ QSUB8------------------------------------- +qsub8 r0, r1, r2 :: rd 0x00f1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x000f0104 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x0104000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0xfffc00f1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7ffe81fe rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x81018101 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0xeaf77a6e rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x6a7f3299 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0xfa0da51f rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x8c0f275c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x1e2e437f rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x80a4ec7f rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0xf86de2cd rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x2b7f8080 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x80a21972 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7fa37f80 rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0xd7610cdd rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x03e00f7f rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x4a521d1e rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7f80e4ee rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x806e507e rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x00d7ae80 rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x60f37b61 rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x4818c480 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x091d8180 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7f2eeb80 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x997f0754 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7ff98013 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x387f07c7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x65fcbaee rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7f48666b rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x80ce0364 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x807f7f8c rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x80f59001 rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x29802bbf rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x80677f7f rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x2dcf42e6 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x1980317f rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0xf88d80c2 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x3423a57f rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7fe13843 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7f1080fa rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x9826b1f8 rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x71c3676e rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x9480f2d3 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x80fa2bfe rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x37d35289 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x9980957f rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0xfe943bdd rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x418d1a55 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x28f1b6f7 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x2847dd65 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x803cf6e0 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7f3480e3 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x426416f1 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x7ff1d5fc rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qsub8 r0, r1, r2 :: rd 0x43217f84 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ QADD8------------------------------------- +qadd8 r0, r1, r2 :: rd 0x0021ff02 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x0021ff02 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xff020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xff020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xff007f00 rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x80ff80ff rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x860f3c48 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xbe457f17 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x5e01a580 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x90a1297f rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x3432cdc1 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xee00224e rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xb28f78bb rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x0f1ccfd4 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x0c84fbc2 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xa0590a34 rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xb59d808f rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x779413e4 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x8044807f rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x19f0c680 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xd2547fa8 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x107f921c rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x82cdff7f rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x78504af8 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xd78d7dcd rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xc086c130 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x712085a4 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x0080d617 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x7fa63dc7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x1398ec00 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xc33e4897 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x22f47f78 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xcdc8fd84 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xc90fe85f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x80e01797 rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xef6354df rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x4f805088 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x7f037f3a rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xd0a5ca22 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x7a493506 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xe48082f3 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x187fe90c rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x6afeb51c rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x77b79dd8 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x80cb8080 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x3390f580 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x7f807855 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x55fbcdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x7f287d80 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x11ad807f rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xc28080ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x80758023 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x60d27fa6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xf9800c7f rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0x7c7f7f6b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xdd7f397f rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +qadd8 r0, r1, r2 :: rd 0xff80dbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ SHADD8 ----------------------------------- +shadd8 r0, r1, r2 :: rd 0x0010ff01 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x0010ff01 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xff010010 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xff010010 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x3fff3fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xff003f00 rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xc000c000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xbfffbfff rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xc3071e24 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xdf225c0b rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x2f00d2a4 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xc8d0144e rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x1a19e6e0 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xf7001127 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xd9c73cdd rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x070ee7ea rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x06c2fde1 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xd02c051a rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xdacea5c7 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x3bca09f2 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xb522914c rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x0cf8e3af rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xe92a45d4 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x085dc90e rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xc1e6ff4d rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x3c2825fc rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xebc63ee6 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xe0c3e018 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x3810c2d2 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x0083eb0b rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x4fd31ee3 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x09ccf600 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xe11f24cb rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x11fa693c rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xe6e4fec2 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xe407f42f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xa9f00bcb rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xf7312aef rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x27a428c4 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x6a014a1d rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xe8d2e511 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x3d241a03 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xf2acc1f9 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x0c5df406 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x35ffda0e rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x3bdbceec rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xbfe598a8 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x19c8faa8 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x48b93c2a rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x2afde6fe rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x45143eba rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x08d69c45 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xe188b1ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x963aa511 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x30e948d3 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xfca8066e rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0x3e454835 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xee651c62 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +shadd8 r0, r1, r2 :: rd 0xffa9edf1 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ UHADD8 ----------------------------------- +uhadd8 r0, r1, r2 :: rd 0x00107f81 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x00107f81 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x7f810010 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x7f810010 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x3f7f3f7f rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x7f803f80 rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x40004000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xbf7fbf7f rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xc3079ea4 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x5fa25c8b rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x2f8052a4 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x48d0144e rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x1a196660 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x778011a7 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xd9c73cdd rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x878e676a rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x86c27d61 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x50ac859a rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xdacea5c7 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x3bca0972 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xb5a2914c rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x8c78e3af rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x69aa4554 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x085dc98e rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xc1e67f4d rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x3c28257c rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xebc6be66 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x60c3e098 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x3890c2d2 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x80836b0b rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x4f531e63 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x89cc7680 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x619fa44b rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x917a693c rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x66647ec2 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x6407742f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xa9708bcb rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x77b1aa6f rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x27a428c4 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x6a814a9d rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xe8526591 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x3d249a83 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x72acc179 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x8c5d7406 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x357f5a0e rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x3bdb4e6c rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xbf6598a8 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x99c87aa8 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x48b93caa rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xaa7d667e rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x45943eba rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x88569c45 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xe188b17f rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x963aa591 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0xb06948d3 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x7ca8866e rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x3e454835 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x6e651c62 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uhadd8 r0, r1, r2 :: rd 0x7fa96d71 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SSAT ----------------- +ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0x00000000 rm 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0x80008000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0x80008000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0xffff0009, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0xffff0009, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0xfffffc00 rm 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0xffff8004 rm 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1 :: rd 0x00000000 rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #1, r1 :: rd 0xffffffff rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #1, r1 :: rd 0xffffffff rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #1, r1 :: rd 0xffffffff rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #32, r1 :: rd 0xa231d5e6 rm 0xa231d5e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #32, r1 :: rd 0x10e1968a rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #32, r1 :: rd 0x0e089270 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #32, r1 :: rd 0x9e8e0185 rm 0x9e8e0185, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #32, r1 :: rd 0x3096f12e rm 0x3096f12e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #32, r1 :: rd 0xffc134df rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x256bfdd6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0xffffffff rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0xee2fa46e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x97a7da20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0xa231d5e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0xffffffff rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x3096f12e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #1, r1, LSL #31 :: rd 0xffffffff rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0x00000003 rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0x00000003 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0xfffffffc rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0x00000000 rm 0x97a7da20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0x00000003 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0xfffffffc rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0x00000000 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0x00000003 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0xfffffffc rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #3, r1, LSL #28 :: rd 0xfffffffc rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0x0000007f rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0x0000007f rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0x0000007f rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0x0000007f rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #8, r1, ASR #18 :: rd 0xfffffff0 rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0x000007ff rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0x000007ff rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0x000007ff rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0x000007ff rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #12, r1, ASR #16 :: rd 0xffffffc1 rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0x007fffff rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0xff800000 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0xffb8be91 rm 0xee2fa46e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0xff800000 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0xff800000 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0x0043865a rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0x00382249 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0xff800000 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0x007fffff rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #24, r1, ASR #6 :: rd 0xffff04d3 rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0x04ad7fba rm 0x256bfdd6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0xf8054180 rm 0xc02a0c05, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0xfdc5f48d rm 0xee2fa46e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0xf8000000 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0xf8000000 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0x021c32d1 rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0x01c1124e rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0xf8000000 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0x0612de25 rm 0x3096f12e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #28, r1, ASR #3 :: rd 0xfff8269b rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0x12b5feeb rm 0x256bfdd6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0xe0150602 rm 0xc02a0c05, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0xf717d237 rm 0xee2fa46e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0xcbd3ed10 rm 0x97a7da20, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0xd118eaf3 rm 0xa231d5e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0x0870cb45 rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0x07044938 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0xcf4700c2 rm 0x9e8e0185, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0x184b7897 rm 0x3096f12e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssat r0, #31, r1, ASR #1 :: rd 0xffe09a6f rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +---------------- SADD8 ----------------- +sadd8 r0, r1, r2 :: rd 0x00dffffc rm 0x00f7ffff, rn 0x00e800fd, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +sadd8 r0, r1, r2 :: rd 0x00dffffc rm 0x00e800fd, rn 0x00f7ffff, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +sadd8 r0, r1, r2 :: rd 0xfffc00df rm 0x00fd00e8, rn 0xffff00f7, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +sadd8 r0, r1, r2 :: rd 0xfffc000f rm 0xffff00f7, rn 0x00fd0018, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd8 r0, r1, r2 :: rd 0xff00fc0f rm 0x0000fd18, rn 0xff00fff7, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +sadd8 r0, r1, r2 :: rd 0xfffc00df rm 0xffff00f7, rn 0x00fd00e8, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +sadd8 r0, r1, r2 :: rd 0xff05fc0f rm 0x00fefd18, rn 0xff07fff7, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +sadd8 r0, r1, r2 :: rd 0xff05fcdf rm 0xff07fff7, rn 0x00fefde8, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +sadd8 r0, r1, r2 :: rd 0x860f3c48 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +sadd8 r0, r1, r2 :: rd 0xbe45b817 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +sadd8 r0, r1, r2 :: rd 0x5e01a549 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd8 r0, r1, r2 :: rd 0x90a1299c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd8 r0, r1, r2 :: rd 0x3432cdc1 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd8 r0, r1, r2 :: rd 0xee00224e rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +sadd8 r0, r1, r2 :: rd 0xb28f78bb rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +sadd8 r0, r1, r2 :: rd 0x0f1ccfd4 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd8 r0, r1, r2 :: rd 0x0c84fbc2 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +sadd8 r0, r1, r2 :: rd 0xa0590a34 rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +sadd8 r0, r1, r2 :: rd 0xb59d4a8f rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd8 r0, r1, r2 :: rd 0x779413e4 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +sadd8 r0, r1, r2 :: rd 0x6a442398 rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +sadd8 r0, r1, r2 :: rd 0x19f0c65e rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +sadd8 r0, r1, r2 :: rd 0xd2548aa8 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +sadd8 r0, r1, r2 :: rd 0x10bb921c rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +sadd8 r0, r1, r2 :: rd 0x82cdff9b rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +sadd8 r0, r1, r2 :: rd 0x78504af8 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +sadd8 r0, r1, r2 :: rd 0xd78d7dcd rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +sadd8 r0, r1, r2 :: rd 0xc086c130 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +sadd8 r0, r1, r2 :: rd 0x712085a4 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +sadd8 r0, r1, r2 :: rd 0x0007d617 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +sadd8 r0, r1, r2 :: rd 0x9ea63dc7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +sadd8 r0, r1, r2 :: rd 0x1398ec00 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +sadd8 r0, r1, r2 :: rd 0xc33e4897 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +sadd8 r0, r1, r2 :: rd 0x22f4d378 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +sadd8 r0, r1, r2 :: rd 0xcdc8fd84 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd8 r0, r1, r2 :: rd 0xc90fe85f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +sadd8 r0, r1, r2 :: rd 0x53e01797 rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +sadd8 r0, r1, r2 :: rd 0xef6354df rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +sadd8 r0, r1, r2 :: rd 0x4f495088 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +sadd8 r0, r1, r2 :: rd 0xd503953a rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd8 r0, r1, r2 :: rd 0xd0a5ca22 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +sadd8 r0, r1, r2 :: rd 0x7a493506 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd8 r0, r1, r2 :: rd 0xe45982f3 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd8 r0, r1, r2 :: rd 0x18bae90c rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +sadd8 r0, r1, r2 :: rd 0x6afeb51c rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +sadd8 r0, r1, r2 :: rd 0x77b79dd8 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +sadd8 r0, r1, r2 :: rd 0x7ecb3051 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd8 r0, r1, r2 :: rd 0x3390f550 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +sadd8 r0, r1, r2 :: rd 0x91737855 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +sadd8 r0, r1, r2 :: rd 0x55fbcdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +sadd8 r0, r1, r2 :: rd 0x8a287d75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +sadd8 r0, r1, r2 :: rd 0x11ad388b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +sadd8 r0, r1, r2 :: rd 0xc21162ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sadd8 r0, r1, r2 :: rd 0x2c754b23 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +sadd8 r0, r1, r2 :: rd 0x60d290a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +sadd8 r0, r1, r2 :: rd 0xf9500cdd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +sadd8 r0, r1, r2 :: rd 0x7c8a906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +sadd8 r0, r1, r2 :: rd 0xddcb39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +sadd8 r0, r1, r2 :: rd 0xff53dbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +---------------- SSUB8 ----------------- +ssub8 r0, r1, r2 :: rd 0x000fff02 rm 0x00f7ffff, rn 0x00e800fd, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +ssub8 r0, r1, r2 :: rd 0x00f101fe rm 0x00e800fd, rn 0x00f7ffff, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +ssub8 r0, r1, r2 :: rd 0x01fe00f1 rm 0x00fd00e8, rn 0xffff00f7, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +ssub8 r0, r1, r2 :: rd 0xff0200df rm 0xffff00f7, rn 0x00fd0018, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +ssub8 r0, r1, r2 :: rd 0x0100fe21 rm 0x0000fd18, rn 0xff00fff7, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +ssub8 r0, r1, r2 :: rd 0xff02000f rm 0xffff00f7, rn 0x00fd00e8, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +ssub8 r0, r1, r2 :: rd 0x01f7fe21 rm 0x00fefd18, rn 0xff07fff7, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +ssub8 r0, r1, r2 :: rd 0xff09020f rm 0xff07fff7, rn 0x00fefde8, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +ssub8 r0, r1, r2 :: rd 0xeaf77a6e rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub8 r0, r1, r2 :: rd 0x6a7f3299 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +ssub8 r0, r1, r2 :: rd 0xfa0da51f rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00050000 ge[3:0]=0101 +ssub8 r0, r1, r2 :: rd 0x8c0f275c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +ssub8 r0, r1, r2 :: rd 0x1e2e43ad rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub8 r0, r1, r2 :: rd 0x72a4eca0 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +ssub8 r0, r1, r2 :: rd 0xf86de2cd rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +ssub8 r0, r1, r2 :: rd 0x2bb03f6a rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub8 r0, r1, r2 :: rd 0x50a21972 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub8 r0, r1, r2 :: rd 0x9ea39c7e rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +ssub8 r0, r1, r2 :: rd 0xd7610cdd rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +ssub8 r0, r1, r2 :: rd 0x03e00fe4 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +ssub8 r0, r1, r2 :: rd 0x4a521d1e rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub8 r0, r1, r2 :: rd 0xe552e4ee rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +ssub8 r0, r1, r2 :: rd 0x306e507e rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +ssub8 r0, r1, r2 :: rd 0x00d7ae68 rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +ssub8 r0, r1, r2 :: rd 0x60f37b61 rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +ssub8 r0, r1, r2 :: rd 0x4818c422 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub8 r0, r1, r2 :: rd 0x091d815b rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub8 r0, r1, r2 :: rd 0xbc2eeb3c rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub8 r0, r1, r2 :: rd 0x998e0754 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +ssub8 r0, r1, r2 :: rd 0xfef94213 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00090000 ge[3:0]=1001 +ssub8 r0, r1, r2 :: rd 0x388207c7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +ssub8 r0, r1, r2 :: rd 0x65fcbaee rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +ssub8 r0, r1, r2 :: rd 0xb948666b rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x000f0000 ge[3:0]=1111 +ssub8 r0, r1, r2 :: rd 0x46ce0364 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00030000 ge[3:0]=0011 +ssub8 r0, r1, r2 :: rd 0x45bee18c rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00060000 ge[3:0]=0110 +ssub8 r0, r1, r2 :: rd 0x57f59001 rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +ssub8 r0, r1, r2 :: rd 0x29622bbf rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +ssub8 r0, r1, r2 :: rd 0x1167a4a1 rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00070000 ge[3:0]=0111 +ssub8 r0, r1, r2 :: rd 0x2dcf42e6 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +ssub8 r0, r1, r2 :: rd 0x19273180 rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +ssub8 r0, r1, r2 :: rd 0xf88d6cc2 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub8 r0, r1, r2 :: rd 0x3423a586 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +ssub8 r0, r1, r2 :: rd 0xbae13843 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +ssub8 r0, r1, r2 :: rd 0x96107bfa rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub8 r0, r1, r2 :: rd 0x9826b1f8 rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +ssub8 r0, r1, r2 :: rd 0x71c3676e rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +ssub8 r0, r1, r2 :: rd 0x946ff2d3 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +ssub8 r0, r1, r2 :: rd 0x35fa2bfe rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +ssub8 r0, r1, r2 :: rd 0x37d35289 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x000a0000 ge[3:0]=1010 +ssub8 r0, r1, r2 :: rd 0x9965957f rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00010000 ge[3:0]=0001 +ssub8 r0, r1, r2 :: rd 0xfe943bdd rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00020000 ge[3:0]=0010 +ssub8 r0, r1, r2 :: rd 0x418d1a55 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x000b0000 ge[3:0]=1011 +ssub8 r0, r1, r2 :: rd 0x28f1b6f7 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +ssub8 r0, r1, r2 :: rd 0x2847dd65 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x000d0000 ge[3:0]=1101 +ssub8 r0, r1, r2 :: rd 0x6c3cf6e0 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00040000 ge[3:0]=0100 +ssub8 r0, r1, r2 :: rd 0xed3414e3 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x000c0000 ge[3:0]=1100 +ssub8 r0, r1, r2 :: rd 0x426416f1 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +ssub8 r0, r1, r2 :: rd 0xbff1d5fc rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00080000 ge[3:0]=1000 +ssub8 r0, r1, r2 :: rd 0x43218384 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x000e0000 ge[3:0]=1110 +------------ SXTAB ------------ +sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0xf7b0b19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0x44de5cef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0x299da958 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0xf5818cc8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0xaa5e93c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0xe607443d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0x73c28fe6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0x5f77534b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0x4e5e06ef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #24 :: rd 0x21ba2f91 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0xf7b0b189 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0x44de5cf3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0x299da980 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0xf5818c8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0xaa5e945b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0xe607438e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0x73c28fee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0x5f775341 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0x4e5e07cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #16 :: rd 0x21ba2f4c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0xf7b0b15a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0x44de5cca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0x299da8ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0xf5818cd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0xaa5e93fb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0xe6074410 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0x73c290dc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0x5f77536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0x4e5e0792 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #8 :: rd 0x21ba2f5f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0xf7b0b0fd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0x44de5c75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0x299da98b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0xf5818cff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0xaa5e9423 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0xe60743a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0x73c290dd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0x5f77536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0x4e5e07c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtab r0, r1, r2, ROR #0 :: rd 0x21ba2fe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ UXTAB ------------ +uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0xf7b0b19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0x44de5cef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0x299daa58 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0xf5818dc8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0xaa5e94c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0xe607443d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0x73c290e6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0x5f77534b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0x4e5e07ef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #24 :: rd 0x21ba3091 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0xf7b0b189 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0x44de5cf3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0x299da980 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0xf5818d8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0xaa5e945b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0xe607448e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0x73c290ee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0x5f775341 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0x4e5e07cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #16 :: rd 0x21ba304c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0xf7b0b15a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0x44de5cca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0x299da9ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0xf5818dd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0xaa5e94fb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0xe6074410 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0x73c290dc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0x5f77536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0x4e5e0792 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #8 :: rd 0x21ba305f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0xf7b0b1fd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0x44de5d75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0x299da98b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0xf5818cff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0xaa5e9523 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0xe60744a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0x73c290dd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0x5f77536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0x4e5e07c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab r0, r1, r2, ROR #0 :: rd 0x21ba2fe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------- UXTAB16 ----------- +uxtab16 r0, r1, r2, ROR #24 :: rd 0x3169594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0x315a593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0x3168594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x31595940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0x3169594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0x31da593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0x3168594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x315959c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x31590098 rm 0x3141ffff, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0xf7ccb19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0x44ff5cef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0x2a2caa58 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0xf6578dc8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0xab1594c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0xe654443d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0x743e90e6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0x5fb4534b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0x4e9007ef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #24 :: rd 0x22663091 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0xf86fb189 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0x45aa5cf3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0x29b8a980 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0xf5858d8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0xab3d945b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0xe6ea448e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0x743f90ee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0x5fb45341 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0x4ec207cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #16 :: rd 0x21e9304c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0xf80eb15a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0x45245cca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0x2a85a9ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0xf64e8dd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0xaae094fb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0xe6814410 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0x744890dc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0x5f94536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0x4eed0792 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #8 :: rd 0x2298305f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0xf7fbb1fd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x45285d75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x29ada98b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0xf6118cff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0xaa759523 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0xe6d244a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x745090dd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x5f8a536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x4ecb07c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtab16 r0, r1, r2, ROR #0 :: rd 0x22532fe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ SXTAH ------------ +sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0xf7b0709c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0x44de28ef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0x299dc558 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0xf58191c8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0xaa5e73c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0xe607273d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0x73c30de6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0x5f77904b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0x4e5e6bef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #24 :: rd 0x21ba5f91 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0xf7b10f89 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0x44dea2f3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0x299d9180 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0xf5815a8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0xaa5e165b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0xe607be8e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0x73c216ee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0x5f777041 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0x4e5d96cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #16 :: rd 0x21ba0e4c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0xf7b0fc5a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0x44dea6ca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0x299db9ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0xf5811dd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0xaa5eabfb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0xe6070f10 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0x73c21edc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0x5f77666b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0x4e5e7492 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #8 :: rd 0x21b9c95f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0xf7b0cdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0x44de7e75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0x299d388b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0xf58162ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0xaa5e4c23 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0xe60791a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0x73c30cdd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0x5f77906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0x4e5e39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +sxtah r0, r1, r2, ROR #0 :: rd 0x21b9dbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ UXTAH ------------ +uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0xf7b1709c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0x44df28ef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0x299dc558 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0xf58191c8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0xaa5f73c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0xe608273d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0x73c30de6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0x5f77904b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0x4e5e6bef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #24 :: rd 0x21ba5f91 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0xf7b10f89 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0x44dea2f3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0x299e9180 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0xf5825a8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0xaa5f165b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0xe607be8e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0x73c316ee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0x5f777041 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0x4e5e96cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #16 :: rd 0x21bb0e4c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0xf7b0fc5a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0x44dea6ca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0x299db9ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0xf5821dd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0xaa5eabfb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0xe6080f10 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0x73c31edc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0x5f77666b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0x4e5e7492 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #8 :: rd 0x21bac95f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0xf7b0cdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0x44de7e75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0x299e388b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0xf58262ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0xaa5f4c23 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0xe60791a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0x73c30cdd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0x5f77906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0x4e5e39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +uxtah r0, r1, r2, ROR #0 :: rd 0x21badbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ SMLAWB ------------ +smlawb r0, r1, r2, r3 :: rd 0x00000000 rm 0x00030000, rn 0x00040000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x00008005 rm 0x00030001, rn 0x00040002 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x00021ffb rm 0x00038001, rn 0x00047fff rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x00023ffb rm 0x00037fff, rn 0x00047fff rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x7fff7ffb rm 0x0003ffff, rn 0x0004ffff rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xfffffffb rm 0x0003fffc, rn 0x0004ffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x680d6173 rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xc35926a2 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x325b09ef rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x9d69f479 rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xd4370081 rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x091ffa82 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xb21ff650 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x71f824b4 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xc96543ad rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xf63f3303 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xa667bfed rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x2a05279f rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x9a12643c rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xf5d16216 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x3839f2ef rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xd3f4bd2f rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x9aac2190 rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xa4e48a53 rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x7a97c3d4 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x53119e74 rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x403f77f9 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x9796f4bd rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x6ab56efa rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xcefcb7bc rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x3a5529d2 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xcf1a0b48 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x8b3fb131 rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xe7af6e4f rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x004dc7a9 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x5044cbb6 rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x4815f3a1 rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x7852d3e6 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x6abc13fa rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x26e68b3e rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x82b6ed7a rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x31fcc2c3 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xfc5c0550 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x2488ec94 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x3b5bc19c rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x7cc2edd8 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x5be1895c rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x7f17c10f rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xff50eae9 rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x686b5fb6 rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xe32758d1 rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x9751380e rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x6bdbb832 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xf59d9d33 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0x312729de rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xdf1b15ef rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawb r0, r1, r2, r3 :: rd 0xe263324d rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +------------ SMLAWT ------------ +smlawt r0, r1, r2, r3 :: rd 0x0000000c rm 0x00030000, rn 0x00040000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x0000800b rm 0x00030001, rn 0x00040002 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x0000600d rm 0x00038001, rn 0x00047fff rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x0000800c rm 0x00037fff, rn 0x00047fff rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x7fff800e rm 0x0003ffff, rn 0x0004ffff rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x0000000e rm 0x0003fffc, rn 0x0004ffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x6da466b8 rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xaf1e5936 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x29fc12ba rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x94c3dbf9 rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xd37b255c rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x018e2608 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xbc3fa062 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x8cfe2aa9 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xdb82c8bd rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xf1d94974 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xb7fd69f7 rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x17c64d1c rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x9352be8d rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xf3cfbc0a rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x3c1a7cd9 rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xf5d9abff rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x98a6483f rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x7a6d6e7f rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x76f50a2d rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x42f4ecf4 rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x40f692b1 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x90a0df2c rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x388197e7 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xd5d1da27 rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x52558183 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xc625a32b rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x8d586ad3 rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xe672acbc rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xe6924c56 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xb7b5c4f6 rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x525ce860 rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x7c355696 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x68f6b86c rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x1b1346ab rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x9ba80cd4 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x2d19ffa5 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x10b5d89e rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x1c47375b rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x36592e87 rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x69a8ef46 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x8b6dc92c rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x82f9bb1d rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x09b32eeb rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x5fa7da91 rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xf19d5ef3 rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x92f68b28 rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0x674d6e6d rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xefc9a9ab rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xff440c7a rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xec180db5 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlawt r0, r1, r2, r3 :: rd 0xfd3dfd7c rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SMLSD ----------------- +smlsd r0, r1, r2, r3 :: rd 0x00000000 rm 0x80008000, rn 0x80008000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x00000001 rm 0x7fff7fff, rn 0x00010001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x0000001f rm 0x80008000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x00000020 rm 0x00640064, rn 0x00030003 rs 0x00000020, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x000000fa rm 0xffffffff, rn 0xfffc0001 rs 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x00003118 rm 0xfff70fff, rn 0x00030003 rs 0x00000100, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x46d0f283 rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xb583dec1 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x1746e19c rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x7f1b45a7 rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xd61f013c rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x11c2a9f9 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xa8dcd3bd rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x69f4e270 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xddca6d45 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x255d66d5 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x9751e12e rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x4883e0ce rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x9b2f1a97 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x00aca055 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x54ad18e6 rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xc11e2ae7 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xa68e4e94 rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xcf06b4a9 rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x70734c96 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x7924b596 rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x457e8494 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x9f7ce5ab rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x7e9142d7 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xc9c16b56 rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x343d44bb rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x829f63d9 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x7e0be811 rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xe8f8702a rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x276c3d40 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x687bc74a rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x2ae3c38f rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x9844bab5 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xd5393721 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x74f6b265 rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x63f13945 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xeb097592 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xcc3b7535 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x266bc158 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x84bbcf7f rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x59a38672 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x86f70dbf rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x765b06dc rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xed67a008 rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x37540ed9 rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x1f9219fb rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x82e3c60f rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x94d58fbc rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x72cfe4b1 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0x45a3f12d rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xcab5d1f1 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsd r0, r1, r2, r3 :: rd 0xf901b934 rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SMLSDX ----------------- +smlsdx r0, r1, r2, r3 :: rd 0x00000000 rm 0x80008000, rn 0x80008000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x00000001 rm 0x7fff7fff, rn 0x00010001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x0000001f rm 0x80008000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x00000020 rm 0x00640064, rn 0x00030003 rs 0x00000020, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x00000104 rm 0xffffffff, rn 0xfffc0001 rs 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x00003118 rm 0xfff70fff, rn 0x00030003 rs 0x00000100, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x454ff2e5 rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x94ff55e5 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smlsdx r0, r1, r2, r3 :: rd 0x2d13277c rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SMUSD ----------------- +smusd r0, r1, r2 :: rd 0x00000000 rm 0x80008000, rn 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x00000000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x00000000 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfffffffb rm 0xffffffff, rn 0xfffc0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x00003018 rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xce34b55d rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfa4adabc rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xf6979877 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x15ee447f rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x1a9387ea rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x1fea1186 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x080346b8 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xdc040e5c rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x13e77b1e rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xffe387a7 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xca9b1438 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x09d4b1fb rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x0845d8f1 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfd699dbf rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x32ee1760 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfa9f544c rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x06f20025 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfc2edfa6 rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xeceafe3e rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xf7433540 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x3cf4b625 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x0e50389b rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x2f492fe5 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xffd5e3f0 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xcb341cd8 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x1da1e53a rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x054b896e rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x27561296 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xe20e04b5 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x08ade092 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x16ffadf6 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x23eeaf4d rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x14357393 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x1202b054 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfdac91b0 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x18f241d6 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x19740601 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x19630603 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xf00000d8 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x25d80217 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xe3943e90 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x296fe090 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfd3eacb0 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfbaee4f2 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xfcd34768 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x3271444a rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xee903517 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0x088d586c rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xe8c20fe7 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusd r0, r1, r2 :: rd 0xeca01324 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- SMUSDX ---------------- +smusdx r0, r1, r2 :: rd 0x00000000 rm 0x80008000, rn 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x00000000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x00000000 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x00000005 rm 0xffffffff, rn 0xfffc0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x00003018 rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x2736f3c3 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xfa46a46c rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x0bb05b66 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xf0fb306d rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x29972290 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x08012346 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xec029f58 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xe6acf7c4 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x109d90fb rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xf029ea71 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x4561697a rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xfd14d1e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xf737e18c rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xff9e13e5 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x2ba97aa0 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xf6196582 rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x02be8154 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x2100cda6 rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x088cbebe rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xe7588d2e rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x3ae1bf67 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xed670286 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x30bd684d rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xffd04078 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xdcb13ca8 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x1ffb7935 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xfa5db4ab rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xeead44e0 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x1c43f3ff rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xd6a0cf18 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x0f9c4c9e rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x0fa6b378 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xe397d23a rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xfd2d124c rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x095a673f rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x103df305 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x0162e6e8 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x185f9408 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x0a38b0dc rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xde986a0f rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x21143e00 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x2680955f rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x0119caa0 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x0240d6b2 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x04d292e6 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x28492bf6 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x126e47f9 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xedf2199a rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0x017c667d rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +smusdx r0, r1, r2 :: rd 0xf989459c rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- USAD8 ---------------- +usad8 r0, r1, r2 :: rd 0x00000000 rm 0x80008000, rn 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000002fc rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000002fa rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000002fc rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000c2 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000200 rm 0xffffffff, rn 0xfffc0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000002fe rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000f5 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001eb rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001a4 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000159 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000017d rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000020d rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001f2 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000010b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000165 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001dc rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000019e rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000148 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001e2 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000ce rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000012e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000187 rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000008f rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000247 rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001db rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000c3 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000eb rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000019d rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000187 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000270 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000094 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001ac rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000b1 rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000019f rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000014d rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000169 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000fd rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000b9 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000014b rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000002f rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000009d rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000b7 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000a4 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000018f rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001b5 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000109 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001c1 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000df rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000010c rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000033d rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000d8 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000001c2 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x000000e9 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x0000019d rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000263 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usad8 r0, r1, r2 :: rd 0x00000178 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +----------------- USADA8 ----------------- +usada8 r0, r1, r2, r3 :: rd 0x00000000 rm 0x80008000, rn 0x80008000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x000002fc rm 0x7fff7fff, rn 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x000002fb rm 0x7fff7fff, rn 0x00010001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x0000031b rm 0x80008000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x000000e2 rm 0x00640064, rn 0x00030003 rs 0x00000020, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x000002ff rm 0xffffffff, rn 0xfffc0001 rs 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x000003fe rm 0xfff70fff, rn 0x00030003 rs 0x00000100, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x5f986f9f rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xaae34485 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x2c07a752 rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x89d2f028 rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xd4b64e72 rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x0b02c745 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xb0d20909 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x7e376337 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xd5dc54cd rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xf2b649b5 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xae930b31 rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x2fb715ac rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xa3268ca5 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xef9ea125 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x3dba12a8 rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xdba5be64 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x884c0c0b rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x9a4ff36e rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x81616ede rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x6077fcbf rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x40b095c5 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x91edc3c5 rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x60340920 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xccfa1dcc rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x48d06674 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xb2aeae68 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x852e3acd rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xe7b880b6 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x0557c7bf rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x81874b24 rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x3ccad57b rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x85fbf300 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x89437103 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x390d2df8 rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x80657de1 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x11bd091b rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xe4999ce3 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x23134a53 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x5765b35d rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x69ec0392 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x899d936b rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x7fcbe728 rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xf7b0b27d rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x464a22cf rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xf5818eb6 rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x8217b8b6 rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x73c291ba rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x1d133df3 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0x21ba3032 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xeda512a7 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000 +usada8 r0, r1, r2, r3 :: rd 0xf20fb99e rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000 diff --git a/none/tests/arm/v6media.vgtest b/none/tests/arm/v6media.vgtest new file mode 100644 index 0000000..275239d --- /dev/null +++ b/none/tests/arm/v6media.vgtest @@ -0,0 +1,2 @@ +prog: v6media +vgopts: -q diff --git a/none/tests/arm/vfp.c b/none/tests/arm/vfp.c new file mode 100644 index 0000000..7d7f0dc --- /dev/null +++ b/none/tests/arm/vfp.c @@ -0,0 +1,2277 @@ + +/* Can be compiled both as ARM or Thumb using + gcc -Wall -g -O0 -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -m{arm,thumb} -o vfp vfp.c +*/ + +#include +#include +#include + +#ifndef __thumb__ +// ARM +#define MOVE_to_FPSCR_from_R4 \ + ".word 0xEEE14A10 @ vmsr FPSCR, r4\n\t" +#define MOVE_to_R4_from_FPSCR \ + ".word 0xEEF14A10 @ vmrs r4, FPSCR\n\t" +#endif + +#ifdef __thumb__ +// Thumb +#define MOVE_to_FPSCR_from_R4 \ + ".word 0x4A10EEE1 @ vmsr FPSCR, r4\n\t" +#define MOVE_to_R4_from_FPSCR \ + ".word 0x4A10EEF1 @ vmrs r4, FPSCR\n\t" +#endif + +static inline unsigned int f2u(float x) { + union { + float f; + unsigned int u; + } cvt; + cvt.f = x; + return cvt.u; +} + +static inline unsigned int f2u0(double x) { + union { + double f; + unsigned int u[2]; + } cvt; + cvt.f = x; + return cvt.u[0]; +} + +static inline unsigned int f2u1(double x) { + union { + double f; + unsigned int u[2]; + } cvt; + cvt.f = x; + return cvt.u[1]; +} + +/* test macros to generate and output the result of a single instruction */ + +const unsigned int mem[] = { + 0x121f1e1f, 0x131b1a1b, 0x141c1f1c, 0x151d191d, + 0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a, + 0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a, + 0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c +}; + +#define TESTINSN_vmovf32_imm(instruction, DD, imm) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + instruction ", #"#imm"\n\t"\ + "vstmia %0, {" #DD "}\n\t" \ + : \ + : "r" (out) \ + : #DD, "memory" \ + ); \ + printf("%s, #" #imm " :: Sd 0x%08x\n", \ + instruction, out[0]); \ +} + +#define TESTINSN_vmov_core_single(instruction, RN, SD, SDval) \ +{ \ + unsigned int out[1]; \ +\ + printf(#SD" 0x%08x\t", SDval); \ + __asm__ volatile( \ + "mov " #RN ", #0\n\t" \ + "vmov.f32 " #SD ", %1\n\t" \ + instruction "\n\t" \ + "str " #RN ", [%0]\n\t" \ + : \ + : "r" (out), "r" (SDval) \ + : #SD, #RN, "memory" \ + ); \ + printf("%s :: "#RN" 0x%08x\n", \ + instruction, out[0]); \ +} + +#define TESTINSN_vmov_single_core(instruction, SD, RN, RNval) \ +{ \ + unsigned int out[1]; \ +\ + printf(#RN" 0x%08x\t", RNval); \ + __asm__ volatile( \ + "mov " #RN ", %1\n\t" \ + "vmov " #SD ", #0x40000000\n\t" \ + instruction "\n\t"\ + "vstmia %0, {" #SD "}\n\t" \ + : \ + : "r" (out), "r" (RNval) \ + : #SD, #RN, "memory" \ + ); \ + printf("%s :: "#SD" 0x%08x\n", \ + instruction, out[0]); \ +} + +#define TESTINSN_vmov_2core_2single(instruction, RD1, RD2, SN, SM, SNval, SMval) \ +{ \ + unsigned int out[2]; \ +\ + printf("\t\t\t "#SN" 0x%08x "#SM" 0x%08x\n", SNval, SMval); \ + __asm__ volatile( \ + "vmov " #SN ", %1\n\t" \ + "vmov " #SM ", %2\n\t" \ + "mov " #RD1 ", #0x4\n\t" \ + "mov " #RD2 ", #0x4\n\t" \ + instruction "\n\t"\ + "str " #RD1 ", [%0]\n\t" \ + "str " #RD2 ", [%0, #+4]\n\t" \ + : \ + : "r" (out), "r" (SNval), "r" (SMval) \ + : #RD1, #RD2, #SN, #SM, "memory" \ + ); \ + printf("%s :: "#RD1" 0x%08x "#RD2" 0x%08x\n", \ + instruction, out[0], out[1]); \ +} + +#define TESTINSN_vmov_2single_2core(instruction, SD1, SD2, RN, RM, RNval, RMval) \ +{ \ + unsigned int out[2]; \ +\ + printf("\t\t\t "#RN" 0x%08x "#RM" 0x%08x\n", RNval, RMval); \ + __asm__ volatile( \ + "mov " #RN ", %1\n\t" \ + "mov " #RM ", %2\n\t" \ + "vmov " #SD1 ", #0x40000000\n\t" \ + "vmov " #SD2 ", #0x40000000\n\t" \ + instruction "\n\t"\ + "vstmia %0, {" #SD1 ", " #SD2 " }\n\t" \ + : \ + : "r" (out), "r" (RNval), "r" (RMval) \ + : #SD1, #SD2, #RN, #RM, "memory" \ + ); \ + printf("%s :: "#SD1" 0x%08x "#SD2" 0x%08x\n", \ + instruction, out[0], out[1]); \ +} + +#define TESTINSN_vmov_double_2core(instruction, DD, RN, RM, RNval, RMval) \ +{ \ + unsigned int out[2]; \ +\ + printf(#RN" 0x%08x "#RM" 0x%08x\t", RNval, RMval); \ + __asm__ volatile( \ + "mov " #RN ", %1\n\t" \ + "mov " #RM ", %2\n\t" \ + "vmov.i8 " #DD ", #0x55\n\t" \ + instruction "\n\t"\ + "vstmia %0, {" #DD "}\n\t" \ + : \ + : "r" (out), "r" (RNval), "r" (RMval) \ + : #DD, #RN, #RM, "memory" \ + ); \ + printf("%s :: "#DD" 0x%08x 0x%08x\n", \ + instruction, out[0], out[1]); \ +} + +#define TESTINSN_vmov_2core_double(instruction, RD1, RD2, DN, DNval0, DNval1) \ +{ \ + unsigned int out[2]; \ +\ + printf(#DN" 0x%08x 0x%08x\t", DNval0, DNval1); \ + __asm__ volatile( \ + "mov " #RD1 ", #55\n\t" \ + "mov " #RD2 ", #55\n\t" \ + "vmov " #DN ", %1, %2\n\t" \ + instruction "\n\t" \ + "str " #RD1 ", [%0]\n\t" \ + "str " #RD2 ", [%0, #+4]\n\t" \ + : \ + : "r" (out), "r" (DNval0), "r" (DNval1) \ + : #DN, #RD1, #RD2, "memory" \ + ); \ + printf("%s :: "#RD1" 0x%08x "#RD2" 0x%08x\n", \ + instruction, out[0], out[1]); \ +} + +#define TESTINSN_un_f64(instruction, DD, DM, DMtype, DMval0, DMval1) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #DD ", #0x55" "\n\t" \ + "vmov " #DM ", %1, %2 \n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #DD "}\n\t" \ + : \ + : "r" (out), "r" (DMval0), "r" (DMval1) \ + : #DD, #DM, "memory" \ + ); \ + printf("%s :: Dd 0x%08x 0x%08x Dm (" #DMtype ")0x%08x %08x\n", \ + instruction, out[1], out[0], DMval1, DMval0); \ +} + +#define TESTINSN_un_f32(instruction, SD, SM, SMtype, SMval) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov.f32 " #SM ", %1\n\t" \ + "vmov.f32 " #SD ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #SD "}\n\t" \ + : \ + : "r" (out), "r" (SMval), "r" (0xffffaaaa) \ + : #SD, #SM, "memory" \ + ); \ + printf("%s :: Sd 0x%08x Sm (" #SMtype ")0x%08x\n", \ + instruction, out[0], SMval); \ +} + +#define TESTINSN_un_cvt_ds(instruction, DD, SM, SMval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov " #SM ", %1\n\t" \ + "vmov " #DD ", %2, %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #DD "}\n\t" \ + : \ + : "r" (out), "r" (SMval), "r" (0xffffaaaa) \ + : #DD, #SM, "memory" \ + ); \ + printf("%s :: Dd 0x%08x 0x%08x Sm 0x%08x\n", \ + instruction, out[1], out[0], SMval); \ +} + +#define TESTINSN_un_cvt_sd(instruction, SD, DM, DMval0, DMval1) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #SD ", %3\n\t" \ + "vmov " #DM ", %1, %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #SD "}\n\t" \ + : \ + : "r" (out), "r" (DMval0), "r" (DMval1), "r" (0xffffaaaa) \ + : #SD, #DM, "memory" \ + ); \ + printf("%s :: Sd 0x%08x Dm 0x%08x %08x\n", \ + instruction, out[0], DMval1, DMval0); \ +} + +#define TESTINSN_cvt_i32_f64(instruction, SD, DM, DMval0, DMval1) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #DM ", %1, %2\n\t" \ + "vmov " #SD ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #SD "}\n\t" \ + : \ + : "r" (out), "r" (DMval0), "r" (DMval1), "r" (0xffffaaaa) \ + : #SD, #DM, "memory" \ + ); \ + printf("%s :: Sd 0x%08x Dm 0x%08x %08x\n", \ + instruction, out[0], DMval1, DMval0); \ +} + +#define TESTINSN_cvt_f64_i32(instruction, DD, SM, SMval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov " #SM ", %1\n\t" \ + "vmov " #DD ", %2, %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #DD "}\n\t" \ + : \ + : "r" (out), "r" (SMval), "r" (0xfffffff0) \ + : #DD, #SM, "memory" \ + ); \ + printf("%s :: Dd 0x%08x %08x Sm 0x%08x\n", \ + instruction, out[0], out[1], SMval); \ +} + +#define TESTINSN_un_f64_q_vmrs(instruction, DD, DM, DMtype, DMval, RN) \ +{ \ + unsigned int out[2]; \ + unsigned int fpscr; \ +\ + __asm__ volatile( \ + "vmov.i8 " #DD ", #0x55" "\n\t" \ + "mov r4, #0\n\t" \ + ".word 0xEEE14A10 @ vmsr FPSCR, "#RN"\n\t" \ + "vdup." #DMtype " " #DM ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %1, {" #DD "}\n\t" \ + ".word 0xEEF14A10 @ vmrs "#RN", FPSCR\n\t" \ + "mov %0, r4" \ + : "=r" (fpscr) \ + : "r" (out), "r" (DMval) \ + : #DD, #DM, "memory", #RN \ + ); \ + printf("%s :: Dd 0x%08x 0x%08x Dm (" #DMtype ")0x%08x fpscr %08x\n", \ + instruction, out[1], out[0], DMval, fpscr); \ +} + +#define TESTINSN_core_to_scalar(instruction, DD, DM, DMval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #DD ", #0x55" "\n\t" \ + "mov " #DM ", %1\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #DD "}\n\t" \ + : \ + : "r" (out), "r" (DMval) \ + : #DD, #DM, "memory" \ + ); \ + printf("%s :: Dd 0x%08x 0x%08x Dm 0x%08x\n", \ + instruction, out[1], out[0], DMval); \ +} + +#define TESTINSN_vldr_f64(instruction, DD, RN, RNval, imm) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #DD ", #0x55" "\n\t" \ + "mov " #RN ", %1\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #DD "}\n\t" \ + : \ + : "r" (out), "r" (RNval) \ + : #DD, #RN, "memory" \ + ); \ + printf("%s :: Dd 0x%08x 0x%08x *(int*) (Rn + shift) 0x%04x\n", \ + instruction, out[1], out[0], *(int*) (RNval + imm)); \ +} + +#define TESTINSN_vldr_f32(instruction, SD, RN, RNval, imm) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #SD ", %3" "\n\t" \ + "mov " #RN ", %1\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #SD "}\n\t" \ + : \ + : "r" (out), "r" (RNval), "r" (imm), "r" (0xffffffaa) \ + : #SD, #RN, "memory" \ + ); \ + printf("%s :: Sd 0x%08x *(int*) (Rn + shift) 0x%04x\n", \ + instruction, out[0], *(int*) (RNval + imm)); \ +} + +#define TESTINSN_vstr64(instruction, DD, DDval, RM, RMval, imm) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #DD ", #" #DDval "\n\t" \ + "add %1, %1, #" #imm "\n\t" \ + "mov " #RM ", #0x55\n\t" \ + "str " #RM ", [%1]\n\t" \ + "str " #RM ", [%1, #4]\n\t" \ + "sub %1, %1, #" #imm "\n\t" \ + "mov " #RM ", %1\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #DD "}\n\t" \ + : \ + : "r" (out), "r" (RMval) \ + : #DD, #RM, "memory" \ + ); \ + printf("%s :: Dd 0x%08x 0x%08x *(int*) (Rm + shift) 0x%04x\n", \ + instruction, out[1], out[0], *(int*) (RMval + imm)); \ +} + +#define TESTINSN_vstr32(instruction, SD, RM, RMval, imm) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #SD ", #0xbe280000\n\t" \ + "mov " #RM ", #0x55\n\t" \ + "str " #RM ", [%1, #" #imm "]\n\t" \ + "mov " #RM ", %1\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #SD "}\n\t" \ + : \ + : "r" (out), "r" (RMval) \ + : #SD, #RM, "memory" \ + ); \ + printf("%s :: Sd 0x%08x, *(int*) (Rm + shift) 0x%04x\n", \ + instruction, out[0], *(int*) (RMval + imm)); \ +} + +#define TESTINSN_scalar_to_core(instruction, QD, QM, QMtype, QMval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "mov " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + instruction "\n\t" \ + "str " #QD ", [%0]\n\t" \ + : \ + : "r" (out), "r" (QMval) \ + : #QD, #QM, "memory" \ + ); \ + printf("%s :: Rd 0x%08x Qm (" #QMtype ")0x%08x\n", \ + instruction, out[0], QMval); \ +} + +#define TESTINSN_VLDn(instruction, QD1, QD2, QD3, QD4) \ +{ \ + unsigned int out[8]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD1 ", #0x55" "\n\t" \ + "vmov.i8 " #QD2 ", #0x55" "\n\t" \ + "vmov.i8 " #QD3 ", #0x55" "\n\t" \ + "vmov.i8 " #QD4 ", #0x55" "\n\t" \ + instruction ", [%1]\n\t" \ + "mov r4, %0\n\t" \ + "vstmia %0!, {" #QD1 "}\n\t" \ + "vstmia %0!, {" #QD2 "}\n\t" \ + "vstmia %0!, {" #QD3 "}\n\t" \ + "vstmia %0!, {" #QD4 "}\n\t" \ + "mov %0, r4\n\t" \ + : \ + : "r" (out), "r" (mem) \ + : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\ + "0x%08x 0x%08x 0x%08x 0x%08x\n", \ + instruction, out[0], out[1], out[2], out[3], out[4],\ + out[5], out[6], out[7]); \ +} + +#define TESTINSN_VSTMIAnoWB(instruction, RN, QD, QDval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", " #QDval "\n\t" \ + "mov " #RN ", %0\n\t" \ + instruction "\n\t" \ + : \ + : "r" (out), "r" (mem) \ + : #QD, "memory", #RN \ + ); \ + printf("%s :: Result 0x%08x 0x%08x\n", \ + instruction, out[0], out[1]); \ +} + +#define TESTINSN_VSTMIAnoWB32(instruction, RN, SD, SDval) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #SD ", %2\n\t" \ + "mov " #RN ", %0\n\t" \ + instruction "\n\t" \ + : \ + : "r" (out), "r" (mem), "r" (SDval) \ + : #SD, "memory", #RN \ + ); \ + printf("%s :: Result 0x%08x\n", \ + instruction, out[0]); \ +} + +#define TESTINSN_VSTMIAWB(RN, QD1, QD2) \ +{ \ + unsigned int out[4]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD1 ", #0xa0" "\n\t" \ + "vmov.i8 " #QD2 ", #0xb1" "\n\t" \ + "mov " #RN ", %0\n\t" \ + "vstmia " #RN "!, {" #QD1 "}\n\t" \ + "vstmia " #RN "!, {" #QD2 "}\n\t" \ + : \ + : "r" (out), "r" (mem) \ + : #QD1, #QD2, "memory", #RN \ + ); \ + printf("vstmia "#RN"!, "#QD1"; vstmia "#RN"!, "#QD2" :: Result 0x%08x 0x%08x 0x%08x 0x%08x\n", \ + out[0], out[1], out[2], out[3]); \ +} + +#define TESTINSN_VSTMIAWB32(RN, SD1, SD2) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov " #SD1 ", #0xbff80000" "\n\t" \ + "vmov " #SD2 ", #0x3fa80000" "\n\t" \ + "mov " #RN ", %0\n\t" \ + "vstmia " #RN "!, {" #SD1 "}\n\t" \ + "vstmia " #RN "!, {" #SD2 "}\n\t" \ + : \ + : "r" (out), "r" (mem) \ + : #SD1, #SD2, "memory", #RN \ + ); \ + printf("vstmia " #RN "!, "#SD1"; vstmia "#RN"!, "#SD2" :: Result 0x%08x 0x%08x\n", \ + out[0], out[1]); \ +} + +#define TESTINSN_VSTMDB(RN, QD1, QD2) \ +{ \ + unsigned int out[4]; \ + long endout = (long) out + 8; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD1 ", #0xaa" "\n\t" \ + "vmov.i8 " #QD2 ", #0xbb" "\n\t" \ + "mov " #RN ", %0\n\t" \ + "vstmdb " #RN "!, {" #QD1 "}\n\t" \ + "vstmdb " #RN "!, {" #QD2 "}\n\t" \ + "mov %0, " #RN "\n\t" \ + : \ + : "r" (endout), "r" (mem) \ + : #QD1, #QD2, "memory", #RN \ + ); \ + printf("vstmdb " #RN "!, " #QD2 "; vstmdb " #RN "!, " #QD2 \ + " :: Result 0x%08x 0x%08x 0x%08x 0x%08x\n", \ + out[0], out[1], out[2], out[3]); \ +} + +#define TESTINSN_VLDMIAnoWB(instruction, RN, QD) \ +{ \ + unsigned int in[2] = {0xaa0, 0xbb1}; \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "mov " #RN ", %0\n\t" \ + instruction "\n\t" \ + "mov " #RN ", %1\n\t" \ + "vstmia " #RN ", {" #QD "}\n\t" \ + : \ + : "r" (in), "r" (out), "r" (mem) \ + : #QD, "memory", #RN \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x\n", \ + instruction, out[0], out[1], out[2], out[3]); \ +} + +#define TESTINSN_VLDMIAWB(RN, QD1, QD2) \ +{ \ + unsigned int in[4] = {0xaa0, 0xbb1, 0xcc2, 0xdd3}; \ + unsigned int out[4]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD1 ", #0x55" "\n\t" \ + "vmov.i8 " #QD2 ", #0x55" "\n\t" \ + "mov " #RN ", %0\n\t" \ + "vldmia " #RN "!, {" #QD1 "}\n\t" \ + "vldmia " #RN "!, {" #QD2 "}\n\t" \ + "mov " #RN ", %1\n\t" \ + "vstmia " #RN "!, {" #QD1 "}\n\t" \ + "vstmia " #RN "!, {" #QD2 "}\n\t" \ + : \ + : "r" (in), "r" (out), "r" (mem) \ + : #QD1, #QD2, "memory", #RN \ + ); \ + printf("vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x%08x 0x%08x 0x%08x 0x%08x\n", \ + out[0], out[1], out[2], out[3]); \ +} + +#define TESTINSN_VLDMDB(RN, QD1, QD2) \ +{ \ + unsigned int in[4] = {0xaa0, 0xbb1, 0xcc2, 0xdd3}; \ + unsigned int out[4]; \ + long endin = (long) in + 16; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD1 ", #0x55" "\n\t" \ + "vmov.i8 " #QD2 ", #0x55" "\n\t" \ + "mov " #RN ", %0\n\t" \ + "vldmdb " #RN "!, {" #QD1 "}\n\t" \ + "vldmdb " #RN "!, {" #QD2 "}\n\t" \ + "mov " #RN ", %1\n\t" \ + "vstmia " #RN "!, {" #QD1 "}\n\t" \ + "vstmia " #RN "!, {" #QD2 "}\n\t" \ + : \ + : "r" (endin), "r" (out), "r" (mem) \ + : #QD1, #QD2, "memory", #RN \ + ); \ + printf("vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x%08x 0x%08x 0x%08x 0x%08x\n", \ + out[0], out[1], out[2], out[3]); \ +} + +#define TESTINSN_VLDR(instruction, dD, rN, rNval, offset) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #dD ", #0x55\n\t" \ + "mov " #rN ", %1\n\t" \ + instruction ", #" #offset "]\n\t" \ + "vstmia %0, {" #dD "}\n\t" \ + : \ + : "r" (out), "r" (rNval) \ + : #dD, "memory" \ + ); \ + printf("%s :: dD 0x%08x 0x%08x rN 0x%08x\n", \ + instruction, out[1], out[0], rNval); \ +} + + +#define TESTINSN_vpush_vpop_f32(S1, Sval1, S2, Sval2, S3, Sval3, S4, S5, S6) \ +{ \ + unsigned int out[6]; \ +\ + __asm__ volatile( \ + "vmov "#S4", %4\n\t" \ + "vmov "#S5", %4\n\t" \ + "vmov "#S6", %4\n\t" \ + "vmov "#S1", %1\n\t" \ + "vmov "#S2", %2\n\t" \ + "vmov "#S3", %3\n\t" \ + "vpush {"#S1", "#S2"}\n\t" \ + "vpush {"#S3"}\n\t" \ + "vpop {"#S4"}\n\t" \ + "vpop {"#S5", "#S6"}\n\t" \ + "mov r4, %0\n\t" \ + "vstmia %0!, {"#S1"}\n\t" \ + "vstmia %0!, {"#S2"}\n\t" \ + "vstmia %0!, {"#S3"}\n\t" \ + "vstmia %0!, {"#S4"}\n\t" \ + "vstmia %0!, {"#S5"}\n\t" \ + "vstmia %0!, {"#S6"}\n\t" \ + "mov %0, r4\n\t" \ + : \ + : "r" (out), "r" (Sval1), "r" (Sval2), "r" (Sval3), "r" (0x55555555) \ + : #S1, #S2, #S3, #S4, #S5, #S6, "r4", "memory" \ + ); \ + printf(#S1" 0x%08x "#S2" 0x%08x "#S3" 0x%08x "#S4" 0x%08x "\ + #S5" 0x%08x "#S6" 0x%08x\n", out[0], out[1],\ + out[2], out[3], out[4], out[5]); \ +} + +#define TESTINSN_vpush_vpop_f64(D1, Dval10, Dval11, D2, Dval20, Dval21, D3, D4) \ +{ \ + unsigned int out[8]; \ +\ + __asm__ volatile( \ + "vmov "#D3", %4, %4\n\t" \ + "vmov "#D4", %4, %4\n\t" \ + "vmov "#D1", %1, %2\n\t" \ + "vmov "#D2", %3, %4\n\t" \ + "vpush {"#D1", "#D2"}\n\t" \ + "vpop {"#D3", "#D4"}\n\t" \ + "mov r4, %0\n\t" \ + "vstmia %0!, {"#D1"}\n\t" \ + "vstmia %0!, {"#D2"}\n\t" \ + "vstmia %0!, {"#D3"}\n\t" \ + "vstmia %0!, {"#D4"}\n\t" \ + "mov %0, r4\n\t" \ + : \ + : "r" (out), "r" (Dval10), "r" (Dval11), "r" (Dval20), "r" (Dval21), "r" (0x55555555) \ + : #D1, #D2, #D3, #D4, "r4", "memory" \ + ); \ + printf(#D1" 0x%08x %08x "#D2" 0x%08x %08x "#D3" 0x%08x %08x "#D4" 0x%08x %08x\n",\ + out[0],out[1], out[2],out[3], out[4],out[5], out[6],out[7]); \ +} + +#define TESTINSN_VSTn(instruction, QD1, QD2, QD3, QD4) \ +{ \ + unsigned int out[8]; \ +\ + memset(out, 0x55, 8 * (sizeof(unsigned int)));\ + __asm__ volatile( \ + "mov r4, %1\n\t" \ + "vldmia %1!, {" #QD1 "}\n\t" \ + "vldmia %1!, {" #QD2 "}\n\t" \ + "vldmia %1!, {" #QD3 "}\n\t" \ + "vldmia %1!, {" #QD4 "}\n\t" \ + "mov %1, r4\n\t" \ + instruction ", [%0]\n\t" \ + : \ + : "r" (out), "r" (mem) \ + : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \ + ); \ + printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\ + "0x%08x 0x%08x 0x%08x 0x%08x\n", \ + instruction, out[0], out[1], out[2], out[3], out[4],\ + out[5], out[6], out[7]); \ +} + +#define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vmov.i8 " #QD ", #0x55" "\n\t" \ + "vdup." #QMtype " " #QM ", %1\n\t" \ + "vdup." #QNtype " " #QN ", %2\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval), "r" (QNval) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \ + " Qn (" #QNtype ")0x%08x\n", \ + instruction, out[1], out[0], QMval, QNval); \ +} + +#define TESTINSN_bin_f64(instruction, QD, QM, QMtype, QMval0, QMval1, QN, QNtype, QNval0, QNval1) \ +{ \ + unsigned int out[2]; \ +\ + __asm__ volatile( \ + "vdup.i32 " #QD ", %5\n\t" \ + "vmov " #QM ", %1, %2 \n\t" \ + "vmov " #QN ", %3, %4 \n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #QD "}\n\t" \ + : \ + : "r" (out), "r" (QMval0), "r" (QMval1), "r" (QNval0), "r" (QNval1), "r"(0x3f800000) \ + : #QD, #QM, #QN, "memory" \ + ); \ + printf("%s :: Qd 0x%08x 0x%08x Qm 0x%08x %08x" \ + " Qn 0x%08x %08x\n", \ + instruction, out[1], out[0], QMval1, QMval0, QNval1, QNval0); \ +} + +#define TESTINSN_bin_f32(instruction, SD, SM, SMtype, SMval, SN, SNtype, SNval) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov.f32 " #SM ", %1\n\t" \ + "vmov.f32 " #SN ", %2\n\t" \ + "vmov.f32 " #SD ", %3\n\t" \ + instruction "\n\t" \ + "vstmia %0, {" #SD "}\n\t" \ + : \ + : "r" (out), "r" (SMval), "r" (SNval), "r" (0xaaaaaaaa) \ + : #SD, #SM, #SN, "memory" \ + ); \ + printf("%s :: Sd 0x%08x Sm (" #SMtype ")0x%08x" \ + " Sn (" #SNtype ")0x%08x\n", \ + instruction, out[0], SMval, SNval); \ +} + +#define TESTINSN_cmp_f64(instruction, DD, DDval0, DDval1, DM, DMval0, DMval1) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #DD ", %1, %2\n\t" \ + "vmov " #DM ", %3, %4\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + instruction "\n\t" \ + MOVE_to_R4_from_FPSCR \ + "str r4, [%0]\n\t" \ + : \ + : "r" (out), "r" (DDval0), "r" (DDval1),"r" (DMval0), "r" (DMval1) \ + : #DD, #DM, "r4", "memory" \ + ); \ + printf("%s :: FPSCR 0x%08x Dd 0x%08x %08x" \ + " Dm 0x%08x %08x\n", \ + instruction, out[0] & 0xffffff60, DDval1, DDval0, DMval1, DMval0); \ +} + +#define TESTINSN_cmp_f32(instruction, SD, SDval, SM, SMval) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #SD ", %1\n\t" \ + "vmov " #SM ", %2\n\t" \ + "mov r4, #0\n\t" \ + MOVE_to_FPSCR_from_R4 \ + instruction "\n\t" \ + MOVE_to_R4_from_FPSCR \ + "str r4, [%0]\n\t" \ + : \ + : "r" (out), "r" (SDval),"r" (SMval) \ + : #SD, #SM, "r4", "memory" \ + ); \ + printf("%s :: FPSCR 0x%01x Sd 0x%08x" \ + " Sm 0x%08x\n", \ + instruction, (out[0] & 0xf0000000) >> 28, SDval, SMval); \ +} + +#define TESTINSN_cmpz_f32(instruction, SD, SDval) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #SD ", %1\n\t" \ + instruction ", #0\n\t" \ + MOVE_to_R4_from_FPSCR \ + "vmov " #SD ", r4\n\t" \ + "vstmia %0, {" #SD "}\n\t" \ + : \ + : "r" (out), "r" (SDval)\ + : #SD, "r4", "memory" \ + ); \ + printf("%s :: FPSCR 0x%08x Sd 0x%08x\n", \ + instruction, out[0] & 0xffffff60, SDval); \ +} + +#define TESTINSN_cmpz_f64(instruction, DD, DDval0, DDval1) \ +{ \ + unsigned int out[1]; \ +\ + __asm__ volatile( \ + "vmov " #DD ", %1, %2\n\t" \ + instruction ", #0\n\t" \ + MOVE_to_R4_from_FPSCR \ + "str r4, [%0]\n\t" \ + : \ + : "r" (out), "r" (DDval0), "r" (DDval1) \ + : #DD, "r4", "memory" \ + ); \ + printf("%s :: FPSCR 0x%08x Dd 0x%08x %08x\n", \ + instruction, out[0] & 0xffffff60, DDval1, DDval0); \ +} + +static void do_vldm_vstm_check(void) +{ + int i; + const char *format = "\t0x%08x\n"; + unsigned int data[] = { + 0x1a1b1c1d, 0x2a2b2c2d, 0x3a3b3c3d, 0x4a4b4c4d, + 0x5a5b5c5d, 0x6a6b6c6d, 0x7a7b7c7d, 0x8a8b8c8d, + 0x9a9b9c9d, 0xaaabacad, 0xbabbbcbd, 0xcacbcccd, + 0xdadbdcdd, 0xeaebeced, 0xfafbfcfd, 0x0a0b0c0d + }; + unsigned int res; + printf("do_vldm_vstm_check:\n"); + __asm__ volatile( + "mov r1, %0\n\t" + "vldmia r1!, {s0, s1, s2, s3}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, s2\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, s3\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, s0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "add r1, %0, #32\n\t" + "vldmdb r1!, {s5, s6}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, s5\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, s6\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "add r1, %0, #4\n\t" + "vldmia r1, {s0, s1, s2, s3}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, s2\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, s3\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, s0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "add r1, %0, #48\n\t" + "vldmia r1!, {d30, d31}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, r5, d30\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "mov r1, r5\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, r5, d31\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "mov r1, r5\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "add r1, %0, #44\n\t" + "vldmia r1, {d30, d31}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, r5, d30\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "mov r1, r5\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, r5, d31\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "mov r1, r5\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "add r1, %0, #40\n\t" + "vldmdb r1!, {d30, d31}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, r5, d30\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "mov r1, r5\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "vmov r1, r5, d31\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + "mov r0, %1\n\t" + "mov r1, r5\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "mov r0, #0x55\n\t" + "vmov s0, r0\n\t" + "mov r0, #0x56\n\t" + "vmov s1, r0\n\t" + "mov r0, #0x57\n\t" + "vmov s2, r0\n\t" + "mov r0, #0x58\n\t" + "vmov s3, r0\n\t" + "add r1, %0, #0\n\t" + "vstmia r1!, {s0, s1, s2, s3}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "mov r0, #0x65\n\t" + "vmov s16, r0\n\t" + "mov r0, #0x66\n\t" + "vmov s17, r0\n\t" + "add r1, %0, #16\n\t" + "vstmia r1, {s16, s17}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "mov r0, #0x75\n\t" + "vmov s16, r0\n\t" + "mov r0, #0x76\n\t" + "vmov s17, r0\n\t" + "add r1, %0, #32\n\t" + "vstmdb r1!, {s16, s17}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "mov r0, #0x42\n\t" + "mov r1, #0x43\n\t" + "vmov d30, r0, r1\n\t" + "mov r0, #0x40\n\t" + "mov r1, #0x41\n\t" + "vmov d31, r0, r1\n\t" + "mov r0, #0x57\n\t" + "add r1, %0, #32\n\t" + "vstmia r1!, {d30, d31}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "mov r0, #0x32\n\t" + "mov r1, #0x33\n\t" + "vmov d10, r0, r1\n\t" + "mov r0, #0x57\n\t" + "add r1, %0, #48\n\t" + "vstmia r1, {d10}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" +/* --- */ + "mov r0, #0x22\n\t" + "mov r1, #0x23\n\t" + "vmov d10, r0, r1\n\t" + "mov r0, #0x57\n\t" + "add r1, %0, #64\n\t" + "vstmdb r1!, {d10}\n\t" + "mov r0, %1\n\t" + "sub r1, r1, %0\n\t" + "mov r3, r1\n\t" + "bl printf\n\t" + : + : "r" (data), "r" (format), "r"(&res) + : "r0", "r1", "r2", "r3", "r5", "r12", "r14", "memory", + "s0", "s1", "s2", "s3", "s5", "s6", "s16", "s17", + "d10", "d30", "d31" + ); + printf("data:\n"); + for (i = 0; i < 16; i++) { + printf("\t0x%08x\n", data[i]); + } +} + +int main(int argc, char **argv) +{ + do_vldm_vstm_check(); + + printf("---- VMOV (ARM core register to scalar) ----\n"); + TESTINSN_core_to_scalar("vmov.32 d0[0], r5", d0, r5, f2u(13)); + TESTINSN_core_to_scalar("vmov.32 d1[1], r6", d1, r6, 0x12); + TESTINSN_core_to_scalar("vmov.32 d20[0], r5", d20, r5, f2u(NAN)); + TESTINSN_core_to_scalar("vmov.32 d29[1], r6", d29, r6, f2u(172)); + TESTINSN_core_to_scalar("vmov.32 d30[0], r5", d30, r5, f2u(INFINITY)); + TESTINSN_core_to_scalar("vmov.32 d11[1], r6", d11, r6, f2u(-INFINITY)); + TESTINSN_core_to_scalar("vmov.32 d18[0], r5", d11, r5, f2u(653)); + TESTINSN_core_to_scalar("vmov.32 d9[1], r6", d9, r6, 12); + TESTINSN_core_to_scalar("vmov.16 d0[0], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.16 d14[1], r5", d14, r5, f2u(NAN)); + TESTINSN_core_to_scalar("vmov.16 d28[2], r6", d28, r6, 14); + TESTINSN_core_to_scalar("vmov.16 d30[3], r1", d30, r1, 17); + TESTINSN_core_to_scalar("vmov.16 d0[0], r5", d0, r5, f2u(INFINITY)); + TESTINSN_core_to_scalar("vmov.16 d7[1], r5", d7, r5, f2u(-INFINITY)); + TESTINSN_core_to_scalar("vmov.16 d21[2], r6", d21, r6, 14); + TESTINSN_core_to_scalar("vmov.16 d17[3], r1", d17, r1, 17); + TESTINSN_core_to_scalar("vmov.8 d0[0], r5", d0, r5, 13); + TESTINSN_core_to_scalar("vmov.8 d10[1], r5", d10, r5, f2u(NAN)); + TESTINSN_core_to_scalar("vmov.8 d20[2], r5", d20, r5, f2u(INFINITY)); + TESTINSN_core_to_scalar("vmov.8 d30[3], r5", d30, r5, f2u(-INFINITY)); + TESTINSN_core_to_scalar("vmov.8 d13[4], r5", d13, r5, 213); + TESTINSN_core_to_scalar("vmov.8 d17[5], r5", d17, r5, 1343); + TESTINSN_core_to_scalar("vmov.8 d24[6], r5", d24, r5, 111); + TESTINSN_core_to_scalar("vmov.8 d29[7], r5", d29, r5, 173); + + printf("---- VMOV (scalar to ARM core register) ----\n"); + TESTINSN_scalar_to_core("vmov.32 r5, d0[0]", r5, d0, i32, f2u(NAN)); + TESTINSN_scalar_to_core("vmov.32 r6, d5[1]", r6, d5, i32, f2u(INFINITY)); + TESTINSN_scalar_to_core("vmov.32 r4, d10[0]", r4, d10, i32, f2u(-INFINITY)); + TESTINSN_scalar_to_core("vmov.32 r5, d15[1]", r5, d15, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.32 r9, d20[0]", r9, d20, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.32 r8, d25[1]", r8, d25, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.32 r0, d30[0]", r0, d30, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.32 r2, d19[1]", r2, d19, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r5, d31[0]", r5, d31, i32, f2u(NAN)); + TESTINSN_scalar_to_core("vmov.u16 r3, d30[1]", r3, d30, i32, f2u(INFINITY)); + TESTINSN_scalar_to_core("vmov.u16 r6, d21[2]", r6, d21, i32, f2u(-INFINITY)); + TESTINSN_scalar_to_core("vmov.u16 r9, d26[3]", r9, d26, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r12, d11[0]", r12, d11, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r0, d10[1]", r0, d10, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r6, d1[2]", r6, d1, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u16 r8, d5[3]", r8, d5, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r2, d4[0]", r2, d4, i32, f2u(NAN)); + TESTINSN_scalar_to_core("vmov.u8 r6, d14[1]", r6, d14, i32, f2u(INFINITY)); + TESTINSN_scalar_to_core("vmov.u8 r9, d24[2]", r9, d24, i32, f2u(-INFINITY)); + TESTINSN_scalar_to_core("vmov.u8 r8, d31[3]", r8, d31, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r10, d29[4]", r10, d29, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r3, d19[5]", r3, d19, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r12, d12[6]", r12, d12, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.u8 r10, d18[4]", r10, d18, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s16 r5, d31[0]", r5, d31, i32, f2u(NAN)); + TESTINSN_scalar_to_core("vmov.s16 r3, d30[1]", r3, d30, i32, f2u(INFINITY)); + TESTINSN_scalar_to_core("vmov.s16 r6, d21[2]", r6, d21, i32, f2u(-INFINITY)); + TESTINSN_scalar_to_core("vmov.s16 r9, d26[3]", r9, d26, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s16 r4, d11[0]", r4, d11, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s16 r0, d10[1]", r0, d10, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s16 r6, d1[2]", r6, d1, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s16 r8, d5[3]", r8, d5, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s8 r2, d4[0]", r2, d4, i32, f2u(NAN)); + TESTINSN_scalar_to_core("vmov.s8 r6, d14[1]", r6, d14, i32, f2u(INFINITY)); + TESTINSN_scalar_to_core("vmov.s8 r9, d24[2]", r9, d24, i32, f2u(-INFINITY)); + TESTINSN_scalar_to_core("vmov.s8 r8, d31[3]", r8, d31, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s8 r6, d29[4]", r6, d29, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s8 r3, d19[5]", r3, d19, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s8 r12, d12[6]", r12, d12, i32, 0x11223344); + TESTINSN_scalar_to_core("vmov.s8 r10, d18[7]", r10, d18, i32, 0x11223344); + + printf("---- VMLA (fp) ----\n"); + TESTINSN_bin_f64("vmla.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmla.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmla.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); + TESTINSN_bin_f64("vmla.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vmla.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmla.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vmla.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vmla.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vmla.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vmla.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vmla.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vmla.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vmla.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vmla.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vmla.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vmla.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vmla.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vmla.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vmla.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vmla.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vmla.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vmla.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vmla.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vmla.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vmla.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); + TESTINSN_bin_f32("vmla.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); + TESTINSN_bin_f32("vmla.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); + TESTINSN_bin_f32("vmla.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vmla.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); + TESTINSN_bin_f32("vmla.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vmla.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vmla.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vmla.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vmla.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vmla.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vmla.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vmla.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vmla.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vmla.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vmla.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vmla.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vmla.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vmla.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); + TESTINSN_bin_f32("vmla.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vmla.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vmla.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vmla.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vmla.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VNMLA (fp) ----\n"); + TESTINSN_bin_f64("vnmla.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmla.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmla.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); + TESTINSN_bin_f64("vnmla.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vnmla.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmla.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vnmla.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vnmla.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vnmla.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vnmla.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vnmla.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vnmla.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vnmla.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vnmla.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vnmla.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vnmla.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vnmla.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vnmla.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vnmla.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vnmla.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vnmla.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vnmla.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vnmla.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vnmla.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vnmla.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmla.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmla.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); + TESTINSN_bin_f32("vnmla.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vnmla.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmla.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vnmla.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vnmla.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vnmla.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vnmla.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vnmla.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vnmla.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vnmla.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vnmla.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vnmla.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vnmla.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vnmla.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vnmla.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vnmla.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752.)); + TESTINSN_bin_f32("vnmla.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vnmla.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vnmla.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vnmla.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vnmla.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VMLS (fp) ----\n"); + TESTINSN_bin_f64("vmls.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmls.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmls.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); + TESTINSN_bin_f64("vmls.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vmls.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmls.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vmls.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vmls.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vmls.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vmls.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vmls.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vmls.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vmls.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vmls.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vmls.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vmls.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vmls.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vmls.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vmls.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vmls.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vmls.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vmls.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vmls.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vmls.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vmls.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); + TESTINSN_bin_f32("vmls.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); + TESTINSN_bin_f32("vmls.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); + TESTINSN_bin_f32("vmls.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vmls.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); + TESTINSN_bin_f32("vmls.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vmls.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vmls.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vmls.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vmls.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vmls.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vmls.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vmls.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vmls.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vmls.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vmls.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vmls.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vmls.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vmls.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); + TESTINSN_bin_f32("vmls.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vmls.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vmls.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vmls.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vmls.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VNMLS (fp) ----\n"); + TESTINSN_bin_f64("vnmls.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmls.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmls.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); + TESTINSN_bin_f64("vnmls.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vnmls.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmls.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vnmls.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vnmls.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vnmls.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vnmls.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vnmls.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vnmls.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vnmls.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vnmls.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vnmls.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vnmls.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vnmls.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vnmls.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vnmls.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vnmls.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vnmls.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vnmls.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vnmls.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vnmls.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vnmls.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmls.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmls.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); + TESTINSN_bin_f32("vnmls.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vnmls.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmls.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vnmls.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vnmls.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vnmls.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vnmls.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vnmls.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vnmls.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vnmls.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vnmls.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vnmls.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vnmls.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vnmls.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vnmls.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vnmls.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); + TESTINSN_bin_f32("vnmls.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vnmls.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vnmls.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vnmls.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vnmls.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VMUL (fp) ----\n"); + TESTINSN_bin_f64("vmul.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmul.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmul.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); + TESTINSN_bin_f64("vmul.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vmul.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vmul.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vmul.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vmul.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vmul.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vmul.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vmul.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vmul.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vmul.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vmul.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vmul.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vmul.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vmul.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vmul.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vmul.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vmul.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vmul.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vmul.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vmul.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vmul.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vmul.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); + TESTINSN_bin_f32("vmul.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); + TESTINSN_bin_f32("vmul.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); + TESTINSN_bin_f32("vmul.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vmul.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); + TESTINSN_bin_f32("vmul.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vmul.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vmul.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vmul.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vmul.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vmul.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vmul.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vmul.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vmul.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vmul.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vmul.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vmul.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vmul.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vmul.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); + TESTINSN_bin_f32("vmul.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vmul.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vmul.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vmul.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vmul.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VNMUL (fp) ----\n"); + TESTINSN_bin_f64("vnmul.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmul.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmul.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); + TESTINSN_bin_f64("vnmul.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vnmul.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vnmul.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vnmul.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vnmul.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vnmul.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vnmul.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vnmul.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vnmul.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vnmul.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vnmul.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vnmul.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vnmul.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vnmul.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vnmul.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vnmul.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vnmul.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vnmul.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vnmul.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vnmul.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vnmul.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vnmul.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmul.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmul.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); + TESTINSN_bin_f32("vnmul.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vnmul.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); + TESTINSN_bin_f32("vnmul.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vnmul.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vnmul.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vnmul.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vnmul.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vnmul.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vnmul.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vnmul.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vnmul.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vnmul.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vnmul.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vnmul.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vnmul.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vnmul.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); + TESTINSN_bin_f32("vnmul.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vnmul.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vnmul.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vnmul.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vnmul.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VADD (fp) ----\n"); + TESTINSN_bin_f64("vadd.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vadd.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vadd.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); + TESTINSN_bin_f64("vadd.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vadd.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vadd.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vadd.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vadd.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vadd.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vadd.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vadd.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vadd.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vadd.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vadd.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vadd.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vadd.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vadd.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vadd.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vadd.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vadd.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vadd.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vadd.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vadd.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vadd.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vadd.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); + TESTINSN_bin_f32("vadd.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); + TESTINSN_bin_f32("vadd.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); + TESTINSN_bin_f32("vadd.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vadd.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); + TESTINSN_bin_f32("vadd.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vadd.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vadd.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vadd.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vadd.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vadd.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vadd.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vadd.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vadd.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vadd.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vadd.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vadd.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vadd.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vadd.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); + TESTINSN_bin_f32("vadd.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vadd.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vadd.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vadd.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vadd.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VSUB (fp) ----\n"); + TESTINSN_bin_f64("vsub.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vsub.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vsub.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); + TESTINSN_bin_f64("vsub.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vsub.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_bin_f64("vsub.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vsub.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vsub.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vsub.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vsub.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vsub.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vsub.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vsub.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vsub.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vsub.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vsub.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vsub.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vsub.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vsub.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vsub.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vsub.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vsub.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vsub.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vsub.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vsub.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); + TESTINSN_bin_f32("vsub.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); + TESTINSN_bin_f32("vsub.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); + TESTINSN_bin_f32("vsub.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vsub.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); + TESTINSN_bin_f32("vsub.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vsub.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vsub.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vsub.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vsub.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vsub.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vsub.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vsub.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vsub.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vsub.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vsub.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vsub.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vsub.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vsub.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); + TESTINSN_bin_f32("vsub.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vsub.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vsub.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vsub.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vsub.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VDIV (fp) ----\n"); + TESTINSN_bin_f64("vdiv.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); + TESTINSN_bin_f64("vdiv.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vdiv.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); + TESTINSN_bin_f64("vdiv.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); + TESTINSN_bin_f64("vdiv.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); + TESTINSN_bin_f64("vdiv.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); + TESTINSN_bin_f64("vdiv.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); + TESTINSN_bin_f64("vdiv.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); + TESTINSN_bin_f64("vdiv.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); + TESTINSN_bin_f64("vdiv.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); + TESTINSN_bin_f64("vdiv.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); + TESTINSN_bin_f64("vdiv.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); + TESTINSN_bin_f64("vdiv.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); + TESTINSN_bin_f64("vdiv.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); + TESTINSN_bin_f64("vdiv.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); + TESTINSN_bin_f64("vdiv.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); + TESTINSN_bin_f64("vdiv.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_bin_f64("vdiv.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f64("vdiv.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); + TESTINSN_bin_f32("vdiv.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); + TESTINSN_bin_f32("vdiv.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); + TESTINSN_bin_f32("vdiv.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); + TESTINSN_bin_f32("vdiv.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); + TESTINSN_bin_f32("vdiv.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); + TESTINSN_bin_f32("vdiv.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); + TESTINSN_bin_f32("vdiv.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); + TESTINSN_bin_f32("vdiv.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); + TESTINSN_bin_f32("vdiv.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); + TESTINSN_bin_f32("vdiv.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); + TESTINSN_bin_f32("vdiv.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); + TESTINSN_bin_f32("vdiv.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); + TESTINSN_bin_f32("vdiv.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); + TESTINSN_bin_f32("vdiv.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); + TESTINSN_bin_f32("vdiv.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); + TESTINSN_bin_f32("vdiv.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); + TESTINSN_bin_f32("vdiv.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); + TESTINSN_bin_f32("vdiv.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); + TESTINSN_bin_f32("vdiv.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); + + printf("---- VABS ----\n"); + TESTINSN_un_f64("vabs.f64 d15, d4", d15, d4, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_f64("vabs.f64 d31, d4", d31, d4, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_f64("vabs.f64 d25, d25", d25, d24, i32, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_un_f64("vabs.f64 d18, d17", d18, d17, i32, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_un_f64("vabs.f64 d30, d1", d30, d1, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_f64("vabs.f64 d8, d27", d8, d27, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_f64("vabs.f64 d20, d1", d20, d1, i32, f2u0(76543.001002), f2u1(76543.001002)); + TESTINSN_un_f64("vabs.f64 d28, d7", d28, d7, i32, f2u0(-4856.234), f2u1(-4856.234)); + TESTINSN_un_f64("vabs.f64 d2, d19", d2, d19, i32,f2u0(87.098217), f2u1(87.098217)); + TESTINSN_un_f64("vabs.f64 d8, d7", d8, d7, i32, f2u0(-122156.2), f2u1(-122156.2)); + TESTINSN_un_f32("vabs.f32 s15, s4", s15, s4, i32, f2u(NAN)); + TESTINSN_un_f32("vabs.f32 s31, s4", s31, s4, i32, f2u(NAN)); + TESTINSN_un_f32("vabs.f32 s25, s25", s25, s24, i32, f2u(INFINITY)); + TESTINSN_un_f32("vabs.f32 s18, s17", s18, s17, i32, f2u(INFINITY)); + TESTINSN_un_f32("vabs.f32 s30, s1", s30, s1, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vabs.f32 s8, s27", s8, s27, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vabs.f32 s20, s1", s20, s1, i32, f2u(76543.001002)); + TESTINSN_un_f32("vabs.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); + TESTINSN_un_f32("vabs.f32 s2, s19", s2, s19, i32,f2u(87.098217)); + TESTINSN_un_f32("vabs.f32 s8, s7", s8, s7, i32, f2u(-122156.2)); + + printf("---- VNEG ----\n"); + TESTINSN_un_f64("vneg.f64 d15, d4", d15, d4, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_f64("vneg.f64 d31, d4", d31, d4, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_f64("vneg.f64 d25, d25", d25, d24, i32, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_un_f64("vneg.f64 d18, d17", d18, d17, i32, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_un_f64("vneg.f64 d30, d1", d30, d1, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_f64("vneg.f64 d8, d27", d8, d27, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_f64("vneg.f64 d20, d1", d20, d1, i32, f2u0(76543.001002), f2u1(76543.001002)); + TESTINSN_un_f64("vneg.f64 d28, d7", d28, d7, i32, f2u0(-4856.234), f2u1(-4856.234)); + TESTINSN_un_f64("vneg.f64 d2, d19", d2, d19, i32,f2u0(87.098217), f2u1(87.098217)); + TESTINSN_un_f64("vneg.f64 d8, d7", d8, d7, i32, f2u0(-122156.2), f2u1(-122156.2)); + TESTINSN_un_f32("vneg.f32 s15, s4", s15, s4, i32, f2u(NAN)); + TESTINSN_un_f32("vneg.f32 s31, s4", s31, s4, i32, f2u(NAN)); + TESTINSN_un_f32("vneg.f32 s25, s25", s25, s24, i32, f2u(INFINITY)); + TESTINSN_un_f32("vneg.f32 s18, s17", s18, s17, i32, f2u(INFINITY)); + TESTINSN_un_f32("vneg.f32 s30, s1", s30, s1, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vneg.f32 s8, s27", s8, s27, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vneg.f32 s20, s1", s20, s1, i32, f2u(76543.001002)); + TESTINSN_un_f32("vneg.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); + TESTINSN_un_f32("vneg.f32 s2, s19", s2, s19, i32,f2u(87.098217)); + TESTINSN_un_f32("vneg.f32 s8, s7", s8, s7, i32, f2u(-122156.2)); + + printf("---- VMOV (register) ----\n"); + TESTINSN_un_f64("vmov.f64 d15, d4", d15, d4, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_f64("vmov.f64 d31, d4", d31, d4, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_f64("vmov.f64 d25, d25", d25, d24, i32, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_un_f64("vmov.f64 d18, d17", d18, d17, i32, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_un_f64("vmov.f64 d30, d1", d30, d1, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_f64("vmov.f64 d8, d27", d8, d27, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_f64("vmov.f64 d20, d1", d20, d1, i32, f2u0(76543.001002), f2u1(76543.001002)); + TESTINSN_un_f64("vmov.f64 d28, d7", d28, d7, i32, f2u0(-4856.234), f2u1(-4856.234)); + TESTINSN_un_f64("vmov.f64 d2, d19", d2, d19, i32,f2u0(87.098217), f2u1(87.098217)); + TESTINSN_un_f64("vmov.f64 d8, d7", d8, d7, i32, f2u0(-122156.2), f2u1(-122156.2)); + TESTINSN_un_f32("vmov.f32 s15, s4", s15, s4, i32, f2u(NAN)); + TESTINSN_un_f32("vmov.f32 s31, s4", s31, s4, i32, f2u(NAN)); + TESTINSN_un_f32("vmov.f32 s25, s25", s25, s24, i32, f2u(INFINITY)); + TESTINSN_un_f32("vmov.f32 s18, s17", s18, s17, i32, f2u(INFINITY)); + TESTINSN_un_f32("vmov.f32 s30, s1", s30, s1, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vmov.f32 s8, s27", s8, s27, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vmov.f32 s20, s1", s20, s1, i32, f2u(76543.001002)); + TESTINSN_un_f32("vmov.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); + TESTINSN_un_f32("vmov.f32 s2, s19", s2, s19, i32,f2u(87.098217)); + TESTINSN_un_f32("vmov.f32 s8, s7", s8, s7, i32, f2u(-122156.2)); + + printf("---- VSQRT ----\n"); + TESTINSN_un_f64("vsqrt.f64 d15, d4", d15, d4, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_f64("vsqrt.f64 d31, d4", d31, d4, i32, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_f64("vsqrt.f64 d25, d25", d25, d24, i32, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_un_f64("vsqrt.f64 d18, d17", d18, d17, i32, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_un_f64("vsqrt.f64 d30, d1", d30, d1, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_f64("vsqrt.f64 d8, d27", d8, d27, i32, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_f64("vsqrt.f64 d20, d1", d20, d1, i32, f2u0(76543.001002), f2u1(76543.001002)); + TESTINSN_un_f64("vsqrt.f64 d28, d7", d28, d7, i32, f2u0(-4856.234), f2u1(-4856.234)); + TESTINSN_un_f64("vsqrt.f64 d2, d19", d2, d19, i32,f2u0(87.098217), f2u1(87.098217)); + TESTINSN_un_f64("vsqrt.f64 d8, d7", d8, d7, i32, f2u0(-122156.2), f2u1(-122156.2)); + TESTINSN_un_f32("vsqrt.f32 s15, s4", s15, s4, i32, f2u(NAN)); + TESTINSN_un_f32("vsqrt.f32 s31, s4", s31, s4, i32, f2u(NAN)); + TESTINSN_un_f32("vsqrt.f32 s25, s25", s25, s24, i32, f2u(INFINITY)); + TESTINSN_un_f32("vsqrt.f32 s18, s17", s18, s17, i32, f2u(INFINITY)); + TESTINSN_un_f32("vsqrt.f32 s30, s1", s30, s1, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vsqrt.f32 s8, s27", s8, s27, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vsqrt.f32 s20, s1", s20, s1, i32, f2u(76543.001002)); + TESTINSN_un_f32("vsqrt.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); + TESTINSN_un_f32("vsqrt.f32 s2, s19", s2, s19, i32,f2u(87.098217)); + TESTINSN_un_f32("vsqrt.f32 s8, s7", s8, s7, i32, f2u(-122156.2)); + + printf("---- VCVT (integer <-> fp) ----\n"); + TESTINSN_un_f32("vcvt.u32.f32 s0, s1", s0, s1, i32, f2u(3.2)); + TESTINSN_un_f32("vcvt.u32.f32 s10, s11", s10, s11, i32, f2u(3e22)); + TESTINSN_un_f32("vcvt.u32.f32 s15, s4", s15, s4, i32, f2u(3e9)); + TESTINSN_un_f32("vcvt.u32.f32 s25, s24", s25, s24, i32, f2u(-0.5)); + TESTINSN_un_f32("vcvt.u32.f32 s19, s21", s19, s21, i32, f2u(-7.1)); + TESTINSN_un_f32("vcvt.u32.f32 s12, s8", s12, s8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un_f32("vcvt.u32.f32 s12, s18", s12, s18, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un_f32("vcvt.u32.f32 s30, s1", s30, s1, i32, f2u(0.0)); + TESTINSN_un_f32("vcvt.u32.f32 s11, s1", s11, s1, i32, f2u(INFINITY)); + TESTINSN_un_f32("vcvt.u32.f32 s21, s12", s21, s12, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vcvt.u32.f32 s20, s11", s20, s11, i32, f2u(NAN)); + TESTINSN_un_f32("vcvt.s32.f32 s29, s13", s29, s13, i32, f2u(NAN)); + TESTINSN_un_f32("vcvt.s32.f32 s9, s19", s9, s19, i32, f2u(0.0)); + TESTINSN_un_f32("vcvt.s32.f32 s0, s17", s0, s17, i32, f2u(INFINITY)); + TESTINSN_un_f32("vcvt.s32.f32 s0, s1", s0, s1, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vcvt.s32.f32 s30, s11", s30, s11, i32, f2u(3.2)); + TESTINSN_un_f32("vcvt.s32.f32 s20, s21", s20, s21, i32, f2u(3e22)); + TESTINSN_un_f32("vcvt.s32.f32 s15, s14", s15, s14, i32, f2u(3e9)); + TESTINSN_un_f32("vcvt.s32.f32 s15, s24", s15, s24, i32, f2u(-0.5)); + TESTINSN_un_f32("vcvt.s32.f32 s15, s29", s15, s29, i32, f2u(-7.1)); + TESTINSN_un_f32("vcvt.s32.f32 s12, s31", s12, s31, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un_f32("vcvt.s32.f32 s1, s8", s1, s8, i32, f2u(-8.0 + 1.0/1024.0)); + + TESTINSN_un_f32("vcvt.f32.u32 s30, s1", s30, s1, i32, f2u(7)); + TESTINSN_un_f32("vcvt.f32.u32 s10, s17", s10, s17, i32, f2u(1 << 31)); + TESTINSN_un_f32("vcvt.f32.u32 s20, s1", s20, s1, i32, f2u((1U << 31) + 1)); + TESTINSN_un_f32("vcvt.f32.u32 s24, s26", s24, s26, i32, f2u((1U << 31) - 1)); + TESTINSN_un_f32("vcvt.f32.u32 s0, s14", s0, s14, i32, f2u(0x30a0bcef)); + TESTINSN_un_f32("vcvt.f32.u32 s11, s1", s11, s1, i32, f2u(INFINITY)); + TESTINSN_un_f32("vcvt.f32.u32 s21, s12", s21, s12, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vcvt.f32.u32 s29, s13", s29, s13, i32, f2u(NAN)); + TESTINSN_un_f32("vcvt.f32.s32 s0, s1", s0, s1, i32, f2u(7)); + TESTINSN_un_f32("vcvt.f32.s32 s30, s31", s30, s31, i32, f2u(1 << 31)); + TESTINSN_un_f32("vcvt.f32.s32 s0, s12", s0, s12, i32, f2u((1U << 31) + 1)); + TESTINSN_un_f32("vcvt.f32.s32 s10, s16", s10, s16, i32, f2u((1U << 31) - 1)); + TESTINSN_un_f32("vcvt.f32.s32 s1, s8", s1, s8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un_f32("vcvt.f32.s32 s29, s13", s29, s13, i32, f2u(NAN)); + TESTINSN_un_f32("vcvt.f32.s32 s9, s19", s9, s19, i32, f2u(0.0)); + TESTINSN_un_f32("vcvt.f32.s32 s0, s17", s0, s17, i32, f2u(INFINITY)); + TESTINSN_un_f32("vcvt.f32.s32 s0, s1", s0, s1, i32, f2u(-INFINITY)); + + TESTINSN_cvt_i32_f64("vcvt.u32.f64 s0, d1", s0, d1, f2u0(3.2), f2u1(3.2)); + TESTINSN_cvt_i32_f64("vcvt.u32.f64 s13, d26", s13, d26, f2u0(234.54), f2u1(234.54)); + TESTINSN_cvt_i32_f64("vcvt.u32.f64 s29, d30", s29, d30, f2u0(46245.345), f2u1(46245.345)); + TESTINSN_cvt_i32_f64("vcvt.u32.f64 s30, d21", s30, d21, f2u0(-8.0 + 1.0/1024.0), f2u1(-8.0 + 1.0/1024.0)); + TESTINSN_cvt_i32_f64("vcvt.u32.f64 s11, d8", s11, d8, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cvt_i32_f64("vcvt.u32.f64 s8, d12", s8, d12, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cvt_i32_f64("vcvt.u32.f64 s19, d7", s19, d7, f2u0(NAN), f2u1(NAN)); + TESTINSN_cvt_i32_f64("vcvt.u32.f64 s16, d16", s16, d16, f2u0(76.67), f2u1(76.67)); + TESTINSN_cvt_i32_f64("vcvt.s32.f64 s0, d1", s0, d1, f2u0(3.2), f2u1(3.2)); + TESTINSN_cvt_i32_f64("vcvt.s32.f64 s13, d26", s13, d26, f2u0(234.54), f2u1(234.54)); + TESTINSN_cvt_i32_f64("vcvt.s32.f64 s29, d30", s29, d30, f2u0(46245.345), f2u1(46245.345)); + TESTINSN_cvt_i32_f64("vcvt.s32.f64 s30, d21", s30, d21, f2u0(-8.0 + 1.0/1024.0), f2u1(-8.0 + 1.0/1024.0)); + TESTINSN_cvt_i32_f64("vcvt.s32.f64 s11, d8", s11, d8, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cvt_i32_f64("vcvt.s32.f64 s8, d12", s8, d12, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cvt_i32_f64("vcvt.s32.f64 s19, d7", s19, d7, f2u0(NAN), f2u1(NAN)); + TESTINSN_cvt_i32_f64("vcvt.s32.f64 s16, d16", s16, d16, f2u0(76.67), f2u1(76.67)); + + TESTINSN_cvt_f64_i32("vcvt.f64.u32 d0, s1", d0, s1, f2u(3.2)); + TESTINSN_cvt_f64_i32("vcvt.f64.u32 d30, s21", d30, s21, f2u(-656.42)); + TESTINSN_cvt_f64_i32("vcvt.f64.u32 d16, s12", d16, s12, f2u(870.024)); + TESTINSN_cvt_f64_i32("vcvt.f64.u32 d29, s7", d29, s7, f2u(-2543.4506)); + TESTINSN_cvt_f64_i32("vcvt.f64.u32 d12, s28", d12, s28, f2u(5.00003245)); + TESTINSN_cvt_f64_i32("vcvt.f64.u32 d7, s5", d7, s5, f2u(-INFINITY)); + TESTINSN_cvt_f64_i32("vcvt.f64.u32 d21, s20", d21, s20, f2u(INFINITY)); + TESTINSN_cvt_f64_i32("vcvt.f64.u32 d11, s11", d11, s11, f2u(NAN)); + TESTINSN_cvt_f64_i32("vcvt.f64.s32 d0, s1", d0, s1, f2u(3.2)); + TESTINSN_cvt_f64_i32("vcvt.f64.s32 d30, s21", d30, s21, f2u(-656.42)); + TESTINSN_cvt_f64_i32("vcvt.f64.s32 d16, s12", d16, s12, f2u(870.024)); + TESTINSN_cvt_f64_i32("vcvt.f64.s32 d29, s7", d29, s7, f2u(-2543.4506)); + TESTINSN_cvt_f64_i32("vcvt.f64.s32 d12, s28", d12, s28, f2u(5.00003245)); + TESTINSN_cvt_f64_i32("vcvt.f64.s32 d7, s5", d7, s5, f2u(-INFINITY)); + TESTINSN_cvt_f64_i32("vcvt.f64.s32 d21, s20", d21, s20, f2u(INFINITY)); + TESTINSN_cvt_f64_i32("vcvt.f64.s32 d11, s11", d11, s11, f2u(NAN)); + +/* printf("---- VCVT (fixed <-> fp) ----\n"); + TESTINSN_un_f32("vcvt.u32.f32 s0, s0, #3", s0, s0, i32, f2u(3.2)); + TESTINSN_un_f32("vcvt.u32.f32 s11, s11, #1", s11, s11, i32, f2u(3e22)); + TESTINSN_un_f32("vcvt.u32.f32 s15, s15, #32", s15, s15, i32, f2u(3e9)); + TESTINSN_un_f32("vcvt.u32.f32 s4, s4, #7", s4, s4, i32, f2u(-0.5)); + TESTINSN_un_f32("vcvt.u32.f32 s6, s6, #4", s6, s6, i32, f2u(-7.1)); + TESTINSN_un_f32("vcvt.u32.f32 s12, s12, #3", s12, s12, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un_f32("vcvt.u32.f32 s8, s8, #3", s8, s8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un_f32("vcvt.u32.f32 s30, s30, #3", s30, s30, i32, f2u(NAN)); + TESTINSN_un_f32("vcvt.u32.f32 s20, s20, #3", s20, s20, i32, f2u(0.0)); + TESTINSN_un_f32("vcvt.u32.f32 s13, s13, #6", s13, s13, i32, f2u(INFINITY)); + TESTINSN_un_f32("vcvt.u32.f32 s16, s16, #3", s16, s16, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vcvt.s32.f32 s1, s1, #5", s1, s1, i32, f2u(3.2)); + TESTINSN_un_f32("vcvt.s32.f32 s21, s21, #1", s21, s21, i32, f2u(3e22)); + TESTINSN_un_f32("vcvt.s32.f32 s17, s17, #8", s17, s17, i32, f2u(3e9)); + TESTINSN_un_f32("vcvt.s32.f32 s27, s27, #2", s27, s27, i32, f2u(-0.5)); + TESTINSN_un_f32("vcvt.s32.f32 s15, s15, #1", s15, s15, i32, f2u(-7.1)); + TESTINSN_un_f32("vcvt.s32.f32 s8, s8, #2", s8, s8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un_f32("vcvt.s32.f32 s31, s31, #2", s31, s31, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un_f32("vcvt.s32.f32 s10, s10, #3", s10, s10, i32, f2u(0.0)); + TESTINSN_un_f32("vcvt.s32.f32 s13, s13, #9", s13, s13, i32, f2u(INFINITY)); + TESTINSN_un_f32("vcvt.s32.f32 s22, s22, #3", s22, s22, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vcvt.s32.f32 s1, s1, #7", s1, s1, i32, f2u(NAN)); + + TESTINSN_un_f32("vcvt.f32.u32 s0, s0, #3", s0, s0, i32, f2u(3.2)); + TESTINSN_un_f32("vcvt.f32.u32 s11, s11, #1", s11, s11, i32, f2u(3e22)); + TESTINSN_un_f32("vcvt.f32.u32 s15, s15, #32", s15, s15, i32, f2u(3e9)); + TESTINSN_un_f32("vcvt.f32.u32 s4, s4, #7", s4, s4, i32, f2u(-0.5)); + TESTINSN_un_f32("vcvt.f32.u32 s6, s6, #4", s6, s6, i32, f2u(-7.1)); + TESTINSN_un_f32("vcvt.f32.u32 s12, s12, #3", s12, s12, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un_f32("vcvt.f32.u32 s8, s8, #3", s8, s8, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un_f32("vcvt.f32.u32 s30, s30, #3", s30, s30, i32, f2u(NAN)); + TESTINSN_un_f32("vcvt.f32.u32 s20, s20, #3", s20, s20, i32, f2u(0.0)); + TESTINSN_un_f32("vcvt.f32.u32 s13, s13, #6", s13, s13, i32, f2u(INFINITY)); + TESTINSN_un_f32("vcvt.f32.u32 s16, s16, #3", s16, s16, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vcvt.f32.s32 s1, s1, #5", s1, s1, i32, f2u(3.2)); + TESTINSN_un_f32("vcvt.f32.s32 s21, s21, #1", s21, s21, i32, f2u(3e22)); + TESTINSN_un_f32("vcvt.f32.s32 s17, s17, #8", s17, s17, i32, f2u(3e9)); + TESTINSN_un_f32("vcvt.f32.s32 s27, s27, #2", s27, s27, i32, f2u(-0.5)); + TESTINSN_un_f32("vcvt.f32.s32 s15, s15, #1", s15, s15, i32, f2u(-7.1)); + TESTINSN_un_f32("vcvt.f32.s32 s8, s8, #2", s8, s8, i32, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un_f32("vcvt.f32.s32 s31, s31, #2", s31, s31, i32, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un_f32("vcvt.f32.s32 s10, s10, #3", s10, s10, i32, f2u(0.0)); + TESTINSN_un_f32("vcvt.f32.s32 s13, s13, #9", s13, s13, i32, f2u(INFINITY)); + TESTINSN_un_f32("vcvt.f32.s32 s22, s22, #3", s22, s22, i32, f2u(-INFINITY)); + TESTINSN_un_f32("vcvt.f32.s32 s1, s1, #7", s1, s1, i32, f2u(NAN)); + */ + + printf("---- VCVT (single <-> double) ----\n"); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d0, s1", d0, s1, f2u(3.2)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d29, s21", d29, s21, f2u(234.65)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d16, s30", d16, s30, f2u(-700.63)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d11, s7", d11, s7, f2u(8.0 - 1.0/1024.0)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d30, s3", d30, s3, f2u(-8.0 + 1.0/1024.0)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d7, s19", d7, s19, f2u(12.43303)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d2, s11", d2, s11, f2u(65.4235)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d9, s21", d9, s21, f2u(NAN)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d17, s29", d17, s29, f2u(-INFINITY)); + TESTINSN_un_cvt_ds("vcvt.f64.f32 d19, s0", d19, s0, f2u(INFINITY)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s0, d1", s0, d1, f2u0(3.2), f2u1(3.2)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s29, d21", s29, d21, f2u0(234.65), f2u1(234.65)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s16, d30", s16, d30, f2u0(-700.63), f2u1(-700.63)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s11, d7", s11, d7, f2u0(8.0 - 1.0/1024.0), f2u1(8.0 - 1.0/1024.0)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s30, d3", s30, d3, f2u0(-8.0 + 1.0/1024.0), f2u1(-8.0 + 1.0/1024.0)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s7, d19", s7, d19, f2u0(12.43303), f2u1(12.43303)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s2, d11", s2, d11, f2u0(65.4235), f2u1(65.4235)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s9, d21", s9, d21, f2u0(NAN), f2u1(NAN)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s17, d29", s17, d29, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_un_cvt_sd("vcvt.f32.f64 s19, d0", s19, d0, f2u0(INFINITY), f2u1(INFINITY)); + + printf("---- VCMP ----\n"); + TESTINSN_cmp_f64("vcmp.f64 d0, d19", d0, f2u0(-3.4567), f2u1(-3.4567), d19, f2u0(-2.6245), f2u1(-2.6245)); + TESTINSN_cmp_f64("vcmp.f64 d11, d16", d11, f2u0(23475.45), f2u1(23475.45), d16, f2u0(3425.5), f2u1(3425.5)); + TESTINSN_cmp_f64("vcmp.f64 d21, d30", d21, f2u0(-4524.5), f2u1(-4524.5), d30, f2u0(-452345.5), f2u1(-452345.5)); + TESTINSN_cmp_f64("vcmp.f64 d7, d28", d7, f2u0(425.5), f2u1(425.5), d28, f2u0(-456.3), f2u1(-456.3)); + TESTINSN_cmp_f64("vcmp.f64 d29, d3", d29, f2u0(INFINITY), f2u1(INFINITY), d3, f2u0(34562.45), f2u1(34562.45)); + TESTINSN_cmp_f64("vcmp.f64 d3, d22", d3, f2u0(2.0), f2u1(2.0), d22, f2u0(2.0), f2u1(2.0)); + TESTINSN_cmp_f64("vcmp.f64 d3, d22", d3, f2u0(12.023), f2u1(12.023), d22, f2u0(12.023), f2u1(12.023)); + TESTINSN_cmp_f64("vcmp.f64 d3, d22", d3, f2u0(0.0), f2u1(0.0), d22, f2u0(0.0), f2u1(0.0)); + TESTINSN_cmp_f64("vcmp.f64 d9, d2", d9, f2u0(INFINITY), f2u1(INFINITY), d2, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cmp_f64("vcmp.f64 d30, d15", d30, f2u0(-INFINITY), f2u1(-INFINITY), d15, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cmp_f64("vcmp.f64 d0, d19", d0, f2u0(-3.4567), f2u1(-3.4567), d19, f2u0(-2.6245), f2u1(-2.6245)); + TESTINSN_cmp_f64("vcmp.f64 d11, d16", d11, f2u0(-5463.7), f2u1(-5463.7), d16, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cmp_f64("vcmp.f64 d21, d30", d21, f2u0(-INFINITY), f2u1(-INFINITY), d30, f2u0(86.7), f2u1(86.7)); + TESTINSN_cmp_f64("vcmp.f64 d7, d28", d7, f2u0(INFINITY), f2u1(INFINITY), d28, f2u0(-8567.456), f2u1(-8567.456)); + TESTINSN_cmp_f64("vcmp.f64 d29, d3", d29, f2u0(-524.4), f2u1(-524.4), d3, f2u0(654.5), f2u1(654.5)); + TESTINSN_cmp_f64("vcmp.f64 d3, d22", d3, f2u0(NAN), f2u1(NAN), d22, f2u0(-6.46524), f2u1(-6.46524)); + TESTINSN_cmp_f64("vcmp.f64 d9, d2", d9, f2u0(56.563), f2u1(56.563), d2, f2u0(56.56), f2u1(56.56)); + TESTINSN_cmp_f64("vcmp.f64 d30, d15", d30, f2u0(5365.60001), f2u1(5365.60001), d15, f2u0(56763.5), f2u1(56763.5)); + TESTINSN_cmp_f64("vcmpe.f64 d0, d19", d0, f2u0(-3.4567), f2u1(-3.4567), d19, f2u0(-2.6245), f2u1(-2.6245)); + TESTINSN_cmp_f64("vcmpe.f64 d11, d16", d11, f2u0(23475.45), f2u1(23475.45), d16, f2u0(3425.5), f2u1(3425.5)); + TESTINSN_cmp_f64("vcmpe.f64 d11, d16", d11, f2u0(23475.45), f2u1(23475.45), d16, f2u0(NAN), f2u1(NAN)); + TESTINSN_cmp_f64("vcmpe.f64 d21, d30", d21, f2u0(-4524.5), f2u1(-4524.5), d30, f2u0(-452345.5), f2u1(-452345.5)); + TESTINSN_cmp_f64("vcmpe.f64 d7, d28", d7, f2u0(425.5), f2u1(425.5), d28, f2u0(-456.3), f2u1(-456.3)); + TESTINSN_cmp_f64("vcmpe.f64 d29, d3", d29, f2u0(INFINITY), f2u1(INFINITY), d3, f2u0(34562.45), f2u1(34562.45)); + TESTINSN_cmp_f64("vcmpe.f64 d3, d22", d3, f2u0(2.0), f2u1(2.0), d22, f2u0(2.0), f2u1(2.0)); + TESTINSN_cmp_f64("vcmpe.f64 d9, d2", d9, f2u0(INFINITY), f2u1(INFINITY), d2, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cmp_f64("vcmpe.f64 d30, d15", d30, f2u0(-INFINITY), f2u1(-INFINITY), d15, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cmp_f64("vcmpe.f64 d0, d19", d0, f2u0(-3.4567), f2u1(-3.4567), d19, f2u0(-2.6245), f2u1(-2.6245)); + TESTINSN_cmp_f64("vcmpe.f64 d11, d16", d11, f2u0(-5463.7), f2u1(-5463.7), d16, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cmp_f64("vcmpe.f64 d21, d30", d21, f2u0(-INFINITY), f2u1(-INFINITY), d30, f2u0(86.7), f2u1(86.7)); + TESTINSN_cmp_f64("vcmpe.f64 d7, d28", d7, f2u0(INFINITY), f2u1(INFINITY), d28, f2u0(-8567.456), f2u1(-8567.456)); + TESTINSN_cmp_f64("vcmpe.f64 d29, d3", d29, f2u0(-524.4), f2u1(-524.4), d3, f2u0(654.5), f2u1(654.5)); + TESTINSN_cmp_f64("vcmpe.f64 d3, d22", d3, f2u0(4624.5), f2u1(4624.5), d22, f2u0(-6.46524), f2u1(-6.46524)); + TESTINSN_cmp_f64("vcmpe.f64 d9, d2", d9, f2u0(56.563), f2u1(56.563), d2, f2u0(56.56), f2u1(56.56)); + TESTINSN_cmp_f64("vcmpe.f64 d30, d15", d30, f2u0(5365.60001), f2u1(5365.60001), d15, f2u0(56763.5), f2u1(56763.5)); + + TESTINSN_cmp_f32("vcmp.f32 s0, s19", s0, f2u(-3.4567), s19, f2u(-2.6245)); + TESTINSN_cmp_f32("vcmp.f32 s11, s16", s11, f2u(23475.45), s16, f2u(3425.5)); + TESTINSN_cmp_f32("vcmp.f32 s3, s22", s3, f2u(2.0), s22, f2u(2.0)); + TESTINSN_cmp_f32("vcmp.f32 s0, s19", s0, f2u(-3.4567), s19, f2u(-2.6245)); + TESTINSN_cmp_f32("vcmp.f32 s11, s16", s11, f2u(23475.45), s16, f2u(3425.5)); + TESTINSN_cmp_f32("vcmp.f32 s21, s30", s21, f2u(-4524.5), s30, f2u(-452345.5)); + TESTINSN_cmp_f32("vcmp.f32 s7, s28", s7, f2u(425.5), s28, f2u(-456.3)); + TESTINSN_cmp_f32("vcmp.f32 s29, s3", s29, f2u(INFINITY), s3, f2u(34562.45)); + TESTINSN_cmp_f32("vcmp.f32 s3, s22", s3, f2u(12.023), s22, f2u(12.023)); + TESTINSN_cmp_f32("vcmp.f32 s3, s22", s3, f2u(0.0), s22, f2u(0.0)); + TESTINSN_cmp_f32("vcmp.f32 s9, s2", s9, f2u(INFINITY), s2, f2u(INFINITY)); + TESTINSN_cmp_f32("vcmp.f32 s30, s15", s30, f2u(-INFINITY),s15, f2u(-INFINITY)); + TESTINSN_cmp_f32("vcmp.f32 s0, s19", s0, f2u(-3.4567), s19, f2u(-2.6245)); + TESTINSN_cmp_f32("vcmp.f32 s11, s16", s11, f2u(-5463.7), s16, f2u(-INFINITY)); + TESTINSN_cmp_f32("vcmp.f32 s21, s30", s21, f2u(-INFINITY),s30, f2u(86.7)); + TESTINSN_cmp_f32("vcmp.f32 s7, s28", s7, f2u(INFINITY), s28, f2u(-8567.456)); + TESTINSN_cmp_f32("vcmp.f32 s29, s3", s29, f2u(-524.4), s3, f2u(654.5)); + TESTINSN_cmp_f32("vcmp.f32 s3, s22", s3, f2u(NAN), s22, f2u(-6.46524)); + TESTINSN_cmp_f32("vcmp.f32 s9, s2", s9, f2u(56.563), s2, f2u(56.56)); + TESTINSN_cmp_f32("vcmp.f32 s30, s15", s30, f2u(5365.60001), s15, f2u(56763.5)); + TESTINSN_cmp_f32("vcmpe.f32 s0, s19", s0, f2u(-3.4567), s19, f2u(-2.6245)); + TESTINSN_cmp_f32("vcmpe.f32 s11, s16", s11, f2u(23475.45), s16, f2u(3425.5)); + TESTINSN_cmp_f32("vcmpe.f32 s11, s16", s11, f2u(23475.45), s16, f2u(NAN)); + TESTINSN_cmp_f32("vcmpe.f32 s21, s30", s21, f2u(-4524.5), s30, f2u(-452345.5)); + TESTINSN_cmp_f32("vcmpe.f32 s7, s28", s7, f2u(425.5), s28, f2u(-456.3)); + TESTINSN_cmp_f32("vcmpe.f32 s29, s3", s29, f2u(INFINITY), s3, f2u(34562.45)); + TESTINSN_cmp_f32("vcmpe.f32 s3, s22", s3, f2u(2.0), s22, f2u(2.0)); + TESTINSN_cmp_f32("vcmpe.f32 s9, s2", s9, f2u(INFINITY), s2, f2u(INFINITY)); + TESTINSN_cmp_f32("vcmpe.f32 s30, s15", s30, f2u(-INFINITY), s15, f2u(-INFINITY)); + TESTINSN_cmp_f32("vcmpe.f32 s0, s19", s0, f2u(-3.4567), s19, f2u(-2.6245)); + TESTINSN_cmp_f32("vcmpe.f32 s11, s16", s11, f2u(-5463.7), s16, f2u(-INFINITY)); + TESTINSN_cmp_f32("vcmpe.f32 s21, s30", s21, f2u(-INFINITY), s30, f2u(86.7)); + TESTINSN_cmp_f32("vcmpe.f32 s7, s28", s7, f2u(INFINITY), s28, f2u(-8567.456)); + TESTINSN_cmp_f32("vcmpe.f32 s29, s3", s29, f2u(-524.4), s3, f2u(654.5)); + TESTINSN_cmp_f32("vcmpe.f32 s3, s22", s3, f2u(4624.5), s22, f2u(-6.46524)); + TESTINSN_cmp_f32("vcmpe.f32 s9, s2", s9, f2u(56.563), s2, f2u(56.56)); + TESTINSN_cmp_f32("vcmpe.f32 s9, s2", s9, f2u(0.0), s2, f2u(56.56)); + TESTINSN_cmp_f32("vcmpe.f32 s9, s2", s9, f2u(10.0), s2, f2u(0.0)); + TESTINSN_cmp_f32("vcmpe.f32 s9, s2", s9, f2u(0.0), s2, f2u(0.0)); + TESTINSN_cmp_f32("vcmpe.f32 s9, s2", s9, f2u(0.0), s2, f2u(0.0)); + + printf("---- VCMP (zero) ----\n"); + TESTINSN_cmpz_f64("vcmp.f64 d0", d0, f2u0(-3.4567), f2u1(-3.4567)); + TESTINSN_cmpz_f64("vcmp.f64 d11", d11, f2u0(23475.45), f2u1(23475.45)); + TESTINSN_cmpz_f64("vcmp.f64 d21", d21, f2u0(-4524.5), f2u1(-4524.5)); + TESTINSN_cmpz_f64("vcmp.f64 d7", d7, f2u0(425.5), f2u1(425.5)); + TESTINSN_cmpz_f64("vcmp.f64 d29", d29, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cmpz_f64("vcmp.f64 d3", d3, f2u0(2.0), f2u1(2.0)); + TESTINSN_cmpz_f64("vcmp.f64 d3", d3, f2u0(0.0), f2u1(0.0)); + TESTINSN_cmpz_f64("vcmp.f64 d9", d9, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cmpz_f64("vcmp.f64 d30", d30, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cmpz_f64("vcmp.f64 d0", d0, f2u0(-3.4567), f2u1(-3.4567)); + TESTINSN_cmpz_f64("vcmp.f64 d11", d11, f2u0(-5463.7), f2u1(-5463.7)); + TESTINSN_cmpz_f64("vcmp.f64 d21", d21, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cmpz_f64("vcmp.f64 d7", d7, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cmpz_f64("vcmp.f64 d29", d29, f2u0(-524.4), f2u1(-524.4)); + TESTINSN_cmpz_f64("vcmp.f64 d3", d3, f2u0(4624.5), f2u1(4624.5)); + TESTINSN_cmpz_f64("vcmp.f64 d9", d9, f2u0(NAN), f2u1(NAN)); + TESTINSN_cmpz_f64("vcmp.f64 d30", d30, f2u0(5365.60001), f2u1(5365.60001)); + + TESTINSN_cmpz_f64("vcmpe.f64 d0", d0, f2u0(-3.4567), f2u1(-3.4567)); + TESTINSN_cmpz_f64("vcmpe.f64 d11", d11, f2u0(23475.45), f2u1(23475.45)); + TESTINSN_cmpz_f64("vcmpe.f64 d21", d21, f2u0(-4524.5), f2u1(-4524.5)); + TESTINSN_cmpz_f64("vcmpe.f64 d7", d7, f2u0(425.5), f2u1(425.5)); + TESTINSN_cmpz_f64("vcmpe.f64 d29", d29, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cmpz_f64("vcmpe.f64 d3", d3, f2u0(2.0), f2u1(2.0)); + TESTINSN_cmpz_f64("vcmpe.f64 d3", d3, f2u0(0.0), f2u1(0.0)); + TESTINSN_cmpz_f64("vcmpe.f64 d9", d9, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cmpz_f64("vcmpe.f64 d30", d30, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cmpz_f64("vcmpe.f64 d0", d0, f2u0(-3.4567), f2u1(-3.4567)); + TESTINSN_cmpz_f64("vcmpe.f64 d11", d11, f2u0(-5463.7), f2u1(-5463.7)); + TESTINSN_cmpz_f64("vcmpe.f64 d21", d21, f2u0(-INFINITY), f2u1(-INFINITY)); + TESTINSN_cmpz_f64("vcmpe.f64 d7", d7, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_cmpz_f64("vcmpe.f64 d29", d29, f2u0(-524.4), f2u1(-524.4)); + TESTINSN_cmpz_f64("vcmpe.f64 d3", d3, f2u0(4624.5), f2u1(4624.5)); + TESTINSN_cmpz_f64("vcmpe.f64 d9", d9, f2u0(NAN), f2u1(NAN)); + TESTINSN_cmpz_f64("vcmpe.f64 d30", d30, f2u0(5365.60001), f2u1(5365.60001)); + + TESTINSN_cmpz_f32("vcmp.f32 s0", s0, f2u(-3.4567)); + TESTINSN_cmpz_f32("vcmp.f32 s11", s11, f2u(23475.45)); + TESTINSN_cmpz_f32("vcmp.f32 s21", s21, f2u(-4524.5)); + TESTINSN_cmpz_f32("vcmp.f32 s7", s7, f2u(425.5)); + TESTINSN_cmpz_f32("vcmp.f32 s29", s29, f2u(INFINITY)); + TESTINSN_cmpz_f32("vcmp.f32 s3", s3, f2u(2.0)); + TESTINSN_cmpz_f32("vcmp.f32 s3", s3, f2u(0.0)); + TESTINSN_cmpz_f32("vcmp.f32 s9", s9, f2u(INFINITY)); + TESTINSN_cmpz_f32("vcmp.f32 s30", s30, f2u(-INFINITY)); + TESTINSN_cmpz_f32("vcmp.f32 s0", s0, f2u(-3.4567)); + TESTINSN_cmpz_f32("vcmp.f32 s11", s11, f2u(-5463.7)); + TESTINSN_cmpz_f32("vcmp.f32 s21", s21, f2u(-INFINITY)); + TESTINSN_cmpz_f32("vcmp.f32 s7", s7, f2u(INFINITY)); + TESTINSN_cmpz_f32("vcmp.f32 s29", s29, f2u(-524.4)); + TESTINSN_cmpz_f32("vcmp.f32 s3", s3, f2u(4624.5)); + TESTINSN_cmpz_f32("vcmp.f32 s9", s9, f2u(NAN)); + TESTINSN_cmpz_f32("vcmp.f32 s30", s30, f2u(5365.60001)); + TESTINSN_cmpz_f32("vcmpe.f32 s0", s0, f2u(-3.4567)); + TESTINSN_cmpz_f32("vcmpe.f32 s11", s11, f2u(23475.45)); + TESTINSN_cmpz_f32("vcmpe.f32 s21", s21, f2u(-4524.5)); + TESTINSN_cmpz_f32("vcmpe.f32 s7", s7, f2u(425.5)); + TESTINSN_cmpz_f32("vcmpe.f32 s29", s29, f2u(INFINITY)); + TESTINSN_cmpz_f32("vcmpe.f32 s3", s3, f2u(2.0)); + TESTINSN_cmpz_f32("vcmpe.f32 s3", s3, f2u(0.0)); + TESTINSN_cmpz_f32("vcmpe.f32 s9", s9, f2u(INFINITY)); + TESTINSN_cmpz_f32("vcmpe.f32 s30", s30, f2u(-INFINITY)); + TESTINSN_cmpz_f32("vcmpe.f32 s0", s0, f2u(-3.4567)); + TESTINSN_cmpz_f32("vcmpe.f32 s11", s11, f2u(-5463.7)); + TESTINSN_cmpz_f32("vcmpe.f32 s21", s21, f2u(-INFINITY)); + TESTINSN_cmpz_f32("vcmpe.f32 s7", s7, f2u(INFINITY)); + TESTINSN_cmpz_f32("vcmpe.f32 s29", s29, f2u(-524.4)); + TESTINSN_cmpz_f32("vcmpe.f32 s3", s3, f2u(4624.5)); + TESTINSN_cmpz_f32("vcmpe.f32 s9", s9, f2u(NAN)); + TESTINSN_cmpz_f32("vcmpe.f32 s30", s30, f2u(5365.60001)); + + int numbers[8] ={ 0xaa0, 0xbb1, 0xcc2, 0xdd3, 0x11a, 0x22b, 0x33c, 0x44d }; + + printf("---- VLDR ----\n"); + TESTINSN_vldr_f64("vldr d9, [r6, #+4]", d9, r6, (long) numbers + 8, 4); + TESTINSN_vldr_f64("vldr d16, [r9, #-4]", d16, r9, (long) numbers + 8, -4); + TESTINSN_vldr_f64("vldr d30, [r12]", d30, r12, (long) numbers + 8, 0); + TESTINSN_vldr_f64("vldr d22, [r9, #+8]", d22, r9, (long) numbers + 8, 8); + TESTINSN_vldr_f64("vldr d29, [r2, #-8]", d29, r2, (long) numbers + 8, -8); + TESTINSN_vldr_f64("vldr d8, [r8, #+8]", d8, r8, (long) numbers + 8, 8); + TESTINSN_vldr_f64("vldr d11, [r12, #-4]", d11, r12, (long) numbers + 8, -4); + TESTINSN_vldr_f64("vldr d18, [r3]", d18, r3, (long) numbers + 8, 0); + TESTINSN_vldr_f64("vldr d5, [r10, #+8]", d5, r10, (long) numbers + 8, 8); + TESTINSN_vldr_f64("vldr d17, [r10]", d17, r10, (long) numbers + 8, 0); + TESTINSN_vldr_f64("vldr d9, [r9, #-4]", d9, r9, (long) numbers + 8, -4); + TESTINSN_vldr_f64("vldr d29, [r4, #-8]", d29, r4, (long) numbers + 8, -8); + TESTINSN_vldr_f64("vldr d21, [r6, #+4]", d21, r6, (long) numbers + 8, 4); + TESTINSN_vldr_f64("vldr d8, [r4]", d8, r4, (long) numbers + 8, 0); + TESTINSN_vldr_f64("vldr d19, [r0, #-8]", d19, r0, (long) numbers + 8, -8); + TESTINSN_vldr_f64("vldr d10, [r3, #+4]", d10, r3, (long) numbers + 8, 4); + TESTINSN_vldr_f32("vldr s10, [r3, #+4]", s10, r3, (long) numbers + 8, 4); + TESTINSN_vldr_f32("vldr s9, [r6, #+4]", s9, r6, (long) numbers + 8, 4); + TESTINSN_vldr_f32("vldr s16, [r9, #-4]", s16, r9, (long) numbers + 8, -4); + TESTINSN_vldr_f32("vldr s30, [r12]", s30, r12, (long) numbers + 8, 0); + TESTINSN_vldr_f32("vldr s22, [r9, #+8]", s22, r9, (long) numbers + 8, 8); + TESTINSN_vldr_f32("vldr s29, [r2, #-8]", s29, r2, (long) numbers + 8, -8); + TESTINSN_vldr_f32("vldr s8, [r8, #+8]", s8, r8, (long) numbers + 8, 8); + TESTINSN_vldr_f32("vldr s11, [r12, #-4]", s11, r12, (long) numbers + 8, -4); + TESTINSN_vldr_f32("vldr s18, [r3]", s18, r3, (long) numbers + 8, 0); + TESTINSN_vldr_f32("vldr s5, [r10, #+8]", s5, r10, (long) numbers + 8, 8); + TESTINSN_vldr_f32("vldr s17, [r10]", s17, r10, (long) numbers + 8, 0); + TESTINSN_vldr_f32("vldr s9, [r9, #-4]", s9, r9, (long) numbers + 8, -4); + TESTINSN_vldr_f32("vldr s29, [r4, #-8]", s29, r4, (long) numbers + 8, -8); + TESTINSN_vldr_f32("vldr s21, [r6, #+4]", s21, r6, (long) numbers + 8, 4); + TESTINSN_vldr_f32("vldr s8, [r4]", s8, r4, (long) numbers + 8, 0); + TESTINSN_vldr_f32("vldr s19, [r0, #-8]", s19, r0, (long) numbers + 8, -8); + TESTINSN_vldr_f32("vldr s10, [r3, #+4]", s10, r3, (long) numbers + 8, 4); + + printf("---- VLDM (Increment After, writeback) ----\n"); + TESTINSN_VLDMIAWB(r6, d17, d7); + TESTINSN_VLDMIAWB(r4, d11, d23); + TESTINSN_VLDMIAWB(r9, d29, d12); + TESTINSN_VLDMIAWB(r9, d0, d30); + TESTINSN_VLDMIAWB(r12, d8, d24); + TESTINSN_VLDMIAWB(r3, d27, d13); + TESTINSN_VLDMIAWB(r10, d20, d30); + TESTINSN_VLDMIAWB(r0, d0, d1); + TESTINSN_VLDMIAWB(r8, d15, d19); + TESTINSN_VLDMIAWB(r3, d31, d30); + TESTINSN_VLDMIAWB(r10, d6, d23); + TESTINSN_VLDMIAWB(r8, d8, d16); + TESTINSN_VLDMIAWB(r9, d13, d11); + TESTINSN_VLDMIAWB(r1, d3, d8); + TESTINSN_VLDMIAWB(r2, d4, d8); + TESTINSN_VLDMIAWB(r3, d9, d27); + + printf("---- VSTR ----\n"); + TESTINSN_vstr64("vstr d9, [r6, #+4]", d9, 0xa0, r6, (long) numbers + 8, 4); + TESTINSN_vstr64("vstr d16, [r9, #-4]", d16, 0xb1, r9, (long) numbers + 8, -4); + TESTINSN_vstr64("vstr d30, [r12]", d30, 0xc2, r12, (long) numbers + 8, 0); + TESTINSN_vstr64("vstr d22, [r9, #+8]", d22, 0xd4, r9, (long) numbers + 8, 8); + TESTINSN_vstr64("vstr d29, [r2, #-8]", d29, 0x00, r2, (long) numbers + 8, -8); + TESTINSN_vstr64("vstr d8, [r8, #+8]", d8, 0x11, r8, (long) numbers + 8, 8); + TESTINSN_vstr64("vstr d11, [r12, #-4]", d11, 0x22, r12, (long) numbers + 8, -4); + TESTINSN_vstr64("vstr d18, [r3]", d18, 0x33, r3, (long) numbers + 8, 0); + TESTINSN_vstr64("vstr d5, [r10, #+8]", d5, 0x99, r10, (long) numbers + 8, 8); + TESTINSN_vstr64("vstr d17, [r10]", d17, 0x77, r10, (long) numbers + 8, 0); + TESTINSN_vstr64("vstr d9, [r9, #-4]", d9, 0xee, r9, (long) numbers + 8, -4); + TESTINSN_vstr64("vstr d29, [r4, #-8]", d29, 0xff, r4, (long) numbers + 8, -8); + TESTINSN_vstr64("vstr d10, [r3, #+4]", d10, 0xbc, r3, (long) numbers + 8, 4); + TESTINSN_vstr64("vstr d21, [r6, #+4]", d21, 0x48, r6, (long) numbers + 8, 4); + TESTINSN_vstr64("vstr d8, [r4]", d8, 0x1f, r4, (long) numbers + 8, 0); + TESTINSN_vstr64("vstr d19, [r0, #-8]", d19, 0xf9, r0, (long) numbers + 8, -8); + TESTINSN_vstr32("vstr s9, [r6, #+4]", s9, r6, (long) numbers + 8, 4); + TESTINSN_vstr32("vstr s21, [r9, #-4]", s21, r9, (long) numbers + 8, -4); + TESTINSN_vstr32("vstr s4, [r3, #+8]", s4, r3, (long) numbers + 8, 8); + TESTINSN_vstr32("vstr s19, [r4, #-8]", s19, r4, (long) numbers + 8, -8); + TESTINSN_vstr32("vstr s29, [r8]", s29, r8, (long) numbers + 8, 0); + TESTINSN_vstr32("vstr s8, [r12]", s8, r12, (long) numbers + 8, 0); + TESTINSN_vstr32("vstr s16, [r0, #+4]", s16, r0, (long) numbers + 8, 4); + TESTINSN_vstr32("vstr s0, [r8, #-4]", s0, r8, (long) numbers + 8, -4); + TESTINSN_vstr32("vstr s3, [r9, #+8]", s3, r9, (long) numbers + 8, 8); + TESTINSN_vstr32("vstr s9, [r10, #-8]", s9, r10, (long) numbers + 8, -8); + TESTINSN_vstr32("vstr s11, [r2]", s11, r2, (long) numbers + 8, 0); + TESTINSN_vstr32("vstr s30, [r0]", s30, r0, (long) numbers + 8, 0); + + printf("---- VSTM (Increment After, no writeback) ----\n"); + TESTINSN_VSTMIAnoWB("vstmia r6, {d21}", r6, d21, 0xab); + TESTINSN_VSTMIAnoWB("vstmia r1, {d1}", r1, d1, 0x13); + TESTINSN_VSTMIAnoWB("vstmia r9, {d2}", r9, d2, 0x78); + TESTINSN_VSTMIAnoWB("vstmia r4, {d30}", r4, d30, 0x0); + TESTINSN_VSTMIAnoWB("vstmia r12, {d23}", r12, d23, 0xb9); + TESTINSN_VSTMIAnoWB("vstmia r6, {d16}", r6, d16, 0xa6); + TESTINSN_VSTMIAnoWB("vstmia r6, {d8}", r6, d8, 0x7f); + TESTINSN_VSTMIAnoWB("vstmia r6, {d27}", r6, d27, 0xff); + TESTINSN_VSTMIAnoWB("vstmia r5, {d11}", r5, d11, 0x32); + TESTINSN_VSTMIAnoWB("vstmia r6, {d4}", r6, d4, 0x10); + TESTINSN_VSTMIAnoWB("vstmia r10, {d9}", r10, d9, 0x4f); + TESTINSN_VSTMIAnoWB("vstmia r9, {d29}", r9, d29, 0x97); + TESTINSN_VSTMIAnoWB("vstmia r10, {d17}", r10, d17, 0xaa); + TESTINSN_VSTMIAnoWB("vstmia r5, {d5}", r5, d5, 0x2b); + TESTINSN_VSTMIAnoWB("vstmia r9, {d7}", r9, d7, 0x7b); + TESTINSN_VSTMIAnoWB("vstmia r3, {d16}", r3, d16, 0x11); + TESTINSN_VSTMIAnoWB32("vstmia r6, {s21}", r6, s21, 0xab); + TESTINSN_VSTMIAnoWB32("vstmia r1, {s1}", r1, s1, 0x13); + TESTINSN_VSTMIAnoWB32("vstmia r9, {s2}", r9, s2, 0x78); + TESTINSN_VSTMIAnoWB32("vstmia r4, {s30}", r4, s30, 0x0); + TESTINSN_VSTMIAnoWB32("vstmia r12, {s23}", r12, s23, 0xb9); + TESTINSN_VSTMIAnoWB32("vstmia r6, {s16}", r6, s16, 0xa613451d); + TESTINSN_VSTMIAnoWB32("vstmia r6, {s8}", r6, s8, 0x7f); + TESTINSN_VSTMIAnoWB32("vstmia r6, {s27}", r6, s27, f2u(-INFINITY)); + TESTINSN_VSTMIAnoWB32("vstmia r5, {s11}", r5, s11, f2u(NAN)); + TESTINSN_VSTMIAnoWB32("vstmia r6, {s4}", r6, s4, 0x10ccb); + TESTINSN_VSTMIAnoWB32("vstmia r10, {s9}", r10, s9, 0x4f543); + TESTINSN_VSTMIAnoWB32("vstmia r9, {s29}", r9, s29, 0x97001a); + TESTINSN_VSTMIAnoWB32("vstmia r10, {s17}", r10, s17, 0xaa45f); + TESTINSN_VSTMIAnoWB32("vstmia r5, {s5}", r5, s5, f2u(NAN)); + TESTINSN_VSTMIAnoWB32("vstmia r9, {s7}", r9, s7, f2u(-INFINITY)); + TESTINSN_VSTMIAnoWB32("vstmia r3, {s16}", r3, s16, f2u(INFINITY)); + + printf("---- VSTM (Increment After, writeback) ----\n"); + TESTINSN_VSTMIAWB(r6, d21, d2); + TESTINSN_VSTMIAWB(r1, d1, d5); + TESTINSN_VSTMIAWB(r9, d2, d17); + TESTINSN_VSTMIAWB(r4, d30, d21); + TESTINSN_VSTMIAWB(r12, d23, d29); + TESTINSN_VSTMIAWB(r6, d16, d30); + TESTINSN_VSTMIAWB(r6, d8, d12); + TESTINSN_VSTMIAWB(r6, d27, d24); + TESTINSN_VSTMIAWB(r5, d11, d13); + TESTINSN_VSTMIAWB(r6, d4, d31); + TESTINSN_VSTMIAWB(r10, d9, d27); + TESTINSN_VSTMIAWB(r9, d29, d17); + TESTINSN_VSTMIAWB(r10, d17, d7); + TESTINSN_VSTMIAWB(r5, d5, d8); + TESTINSN_VSTMIAWB(r9, d7, d16); + TESTINSN_VSTMIAWB(r3, d16, d21); + TESTINSN_VSTMIAWB32(r6, s21, s2); + TESTINSN_VSTMIAWB32(r12, s23, s21); + TESTINSN_VSTMIAWB32(r3, s3, s3); + TESTINSN_VSTMIAWB32(r10, s19, s5); + TESTINSN_VSTMIAWB32(r2, s3, s12); + TESTINSN_VSTMIAWB32(r8, s7, s10); + TESTINSN_VSTMIAWB32(r4, s30, s13); + TESTINSN_VSTMIAWB32(r6, s17, s17); + TESTINSN_VSTMIAWB32(r9, s11, s21); + TESTINSN_VSTMIAWB32(r9, s8, s30); + TESTINSN_VSTMIAWB32(r3, s12, s9); + TESTINSN_VSTMIAWB32(r6, s6, s11); + TESTINSN_VSTMIAWB32(r8, s17, s12); + TESTINSN_VSTMIAWB32(r9, s12, s12); + TESTINSN_VSTMIAWB32(r4, s11, s11); + + printf("---- VLDM (Decrement Before) ----\n"); + TESTINSN_VLDMDB(r4, d11, d23); + TESTINSN_VLDMDB(r9, d29, d12); + TESTINSN_VLDMDB(r9, d0, d30); + TESTINSN_VLDMDB(r12, d8, d24); + TESTINSN_VLDMDB(r3, d27, d13); + TESTINSN_VLDMDB(r6, d17, d7); + TESTINSN_VLDMDB(r10, d20, d30); + TESTINSN_VLDMDB(r0, d0, d1); + TESTINSN_VLDMDB(r8, d15, d19); + TESTINSN_VLDMDB(r3, d31, d30); + TESTINSN_VLDMDB(r10, d6, d23); + TESTINSN_VLDMDB(r8, d8, d16); + TESTINSN_VLDMDB(r9, d13, d11); + TESTINSN_VLDMDB(r1, d3, d8); + TESTINSN_VLDMDB(r2, d4, d8); + TESTINSN_VLDMDB(r3, d9, d27); + + printf("----- VMOV (immediate) -----\n"); + TESTINSN_vmovf32_imm("vmov s0", s0, 0xbe880000); + TESTINSN_vmovf32_imm("vmov s1", s1, 0x3fa80000); + TESTINSN_vmovf32_imm("vmov s2", s2, 0xbf080000); + TESTINSN_vmovf32_imm("vmov s5", s5, 0x3eb80000); + TESTINSN_vmovf32_imm("vmov s7", s7, 0xbff80000); + TESTINSN_vmovf32_imm("vmov s10", s10, 0xbe280000); + TESTINSN_vmovf32_imm("vmov s12", s12, 0x40000000); + TESTINSN_vmovf32_imm("vmov s13", s13, 0x3e880000); + TESTINSN_vmovf32_imm("vmov s14", s14, 0xbee80000); + TESTINSN_vmovf32_imm("vmov s15", s15, 0xc0b80000); + + printf("----- VMOV (ARM core register and single register) -----\n"); + TESTINSN_vmov_core_single("vmov r12, s12", r12, s12, 0x4000aad); + TESTINSN_vmov_core_single("vmov r2, s5", r2, s5, 0xab45e7); + TESTINSN_vmov_core_single("vmov r5, s15", r5, s15, 0x00add12); + TESTINSN_vmov_core_single("vmov r8, s11", r8, s11, 0x876450ff); + TESTINSN_vmov_core_single("vmov r9, s5", r9, s5, 0xffff); + TESTINSN_vmov_core_single("vmov r10, s9", r10, s9, 0x87d34f); + TESTINSN_vmov_core_single("vmov r9, s10", r9, s10, 0x00ffff); + TESTINSN_vmov_core_single("vmov r6, s8", r6, s8, 0xad4f8); + TESTINSN_vmov_core_single("vmov r4, s14", r4, s14, 0x920b8cf); + TESTINSN_vmov_core_single("vmov r3, s7", r3, s7, f2u(NAN)); + TESTINSN_vmov_core_single("vmov r2, s0", r2, s0, f2u(-INFINITY)); + TESTINSN_vmov_core_single("vmov r0, s1", r0, s1, f2u(INFINITY)); + TESTINSN_vmov_single_core("vmov s2, r9", s2, r9, 0x9465a); + TESTINSN_vmov_single_core("vmov s14, r0", s14, r0, 0xd0b87a); + TESTINSN_vmov_single_core("vmov s4, r2", s4, r2, 0x452bbc8); + TESTINSN_vmov_single_core("vmov s7, r8", s7, r8, 0xa7cb3d); + TESTINSN_vmov_single_core("vmov s9, r4", s9, r4, 0xdd8ec); + TESTINSN_vmov_single_core("vmov s10, r12", s10, r12, 0x8a7b6e); + TESTINSN_vmov_single_core("vmov s13, r9", s13, r9, 0x4b00a); + TESTINSN_vmov_single_core("vmov s3, r3", s3, r3, 0x0023455); + TESTINSN_vmov_single_core("vmov s5, r5", s5, r5, f2u(INFINITY)); + TESTINSN_vmov_single_core("vmov s8, r6", s8, r6, f2u(-INFINITY)); + TESTINSN_vmov_single_core("vmov s4, r0", s4, r0, 0x000acb45); + TESTINSN_vmov_single_core("vmov s0, r6", s0, r6, f2u(NAN)); + + printf("----- VMOV (ARM two core registers and two single registers) -----\n"); + TESTINSN_vmov_2single_2core("vmov s0, s1, r6, r9", s0, s1, r6, r9, 0x43252acc, 0xabcc4); + TESTINSN_vmov_2single_2core("vmov s0, s1, r9, r9", s0, s1, r9, r9, 0x43252acc, 0xabcc4); + TESTINSN_vmov_2single_2core("vmov s30, s31, r9, r1", s30, s31, r9, r1, 0xaa2e2acc, 0x00337); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(NAN), f2u(NAN)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(NAN), f2u(INFINITY)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(NAN), f2u(-INFINITY)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(NAN), f2u(0)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(INFINITY), f2u(NAN)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(INFINITY), f2u(INFINITY)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(INFINITY), f2u(-INFINITY)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(INFINITY), f2u(0)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(-INFINITY), f2u(NAN)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(-INFINITY), f2u(INFINITY)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(-INFINITY), f2u(-INFINITY)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(-INFINITY), f2u(0)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(0), f2u(NAN)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(0), f2u(INFINITY)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(0), f2u(-INFINITY)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(0), f2u(0)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(NAN) + 1, f2u(NAN)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(NAN) + 1, f2u(0)); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(NAN), f2u(NAN) - 1); + TESTINSN_vmov_2single_2core("vmov s20, s21, r10, r9", s20, s21, r10, r9, f2u(0), f2u(NAN) - 1); + TESTINSN_vmov_2core_2single("vmov r12, r9, s12, s13", r12, r9, s12, s13, 0x4000aad, 0xaffff); + TESTINSN_vmov_2core_2single("vmov r0, r9, s12, s13", r0, r9, s12, s13, 0x40ee56d, 0x123ff); + TESTINSN_vmov_2core_2single("vmov r12, r9, s12, s13", r12, r9, s12, s13, 0x4000aad, 0xaffff); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(NAN), f2u(NAN)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(NAN), f2u(INFINITY)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(NAN), f2u(-INFINITY)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(NAN), f2u(0)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(INFINITY), f2u(NAN)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(INFINITY), f2u(INFINITY)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(INFINITY), f2u(-INFINITY)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(INFINITY), f2u(0)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(-INFINITY), f2u(NAN)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(-INFINITY), f2u(INFINITY)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(-INFINITY), f2u(-INFINITY)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(-INFINITY), f2u(0)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(0), f2u(NAN)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(0), f2u(INFINITY)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(0), f2u(-INFINITY)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(0), f2u(0)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(NAN) + 1, f2u(NAN)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(NAN) + 1, f2u(0)); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(NAN), f2u(NAN) - 1); + TESTINSN_vmov_2core_2single("vmov r10, r9, s20, s21", r10, r9, s20, s21, f2u(0), f2u(NAN) - 1); + + printf("----- VMOV (ARM two core registers and double register) -----\n"); + TESTINSN_vmov_double_2core("vmov d3, r6, r9", d3, r6, r9, 0x43252acc, 0x45bbd); + TESTINSN_vmov_double_2core("vmov d4, r10, r2", d4, r10, r2, 0x1243b4, 0x237ffb); + TESTINSN_vmov_double_2core("vmov d21, r1, r6", d21, r1, r6, 0x30cc4, 0x314c043); + TESTINSN_vmov_double_2core("vmov d30, r9, r9", d30, r9, r9, 0x08ddf, 0x87bbca); + TESTINSN_vmov_double_2core("vmov d29, r3, r5", d29, r3, r5, 0xaaa0, 0xbbb1); + TESTINSN_vmov_double_2core("vmov d16, r8, r8", d16, r8, r8, 0xaa455bb, 0x13434); + TESTINSN_vmov_double_2core("vmov d17, r12, r9", d17, r12, r9, 0x004003, 0x452bbc1); + TESTINSN_vmov_double_2core("vmov d9, r9, r0", d9, r9, r0, 0x134c, 0x41ffb6); + TESTINSN_vmov_double_2core("vmov d7, r0, r6", d7, r0, r6, 0x35425dcc, 0x0876c43); + TESTINSN_vmov_double_2core("vmov d13, r3, r9", d13, r3, r9, f2u0(NAN), f2u1(NAN)); + TESTINSN_vmov_double_2core("vmov d19, r6, r5", d19, r6, r5, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_vmov_double_2core("vmov d0, r2, r6", d0, r2, r6, f2u0(-INFINITY), f2u1(-INFINITY)); + + TESTINSN_vmov_2core_double("vmov r3, r6, d9", r3, r6, d9, 0x43252acc, 0x45bbd); + TESTINSN_vmov_2core_double("vmov r4, r10, d2", r4, r10, d2, 0x1243b4, 0x237ffb); + TESTINSN_vmov_2core_double("vmov r2, r1, d6", r2, r1, d6, 0x30cc4, 0x314c043); + TESTINSN_vmov_2core_double("vmov r0, r9, d11", r0, r9, d11, 0x08ddf, 0x87bbca); + TESTINSN_vmov_2core_double("vmov r9, r3, d5", r9, r3, d5, 0xaaa0, 0xbbb1); + TESTINSN_vmov_2core_double("vmov r10, r8, d8", r10, r8, d8, 0xaa455bb, 0x13434); + TESTINSN_vmov_2core_double("vmov r9, r12, d11", r9, r12, d11, 0x004003, 0x452bbc1); + + // ARM ARM says this is UNDEFINED, hence we don't decode it + //TESTINSN_vmov_2core_double("vmov r9, r9, d0", r9, r9, d0, 0x134c, 0x41ffb6); + + TESTINSN_vmov_2core_double("vmov r6, r0, d7", r6, r0, d7, 0x35425dcc, 0x0876c43); + TESTINSN_vmov_2core_double("vmov r12, r3, d11", r12, r3, d11, f2u0(NAN), f2u1(NAN)); + TESTINSN_vmov_2core_double("vmov r1, r6, d5", r1, r6, d5, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_vmov_2core_double("vmov r0, r2, d7", r0, r2, d7, f2u0(-INFINITY), f2u1(-INFINITY)); + + TESTINSN_vmov_2core_double("vmov r2, r9, d0", r2, r9, d0, f2u0(INFINITY), f2u1(INFINITY)); + TESTINSN_vmov_2core_double("vmov r6, r9, d10", r6, r9, d10, 0x14534c, 0x41ffb6); + TESTINSN_vmov_2core_double("vmov r0, r9, d20", r0, r9, d20, f2u0(NAN), f2u1(NAN)); + + printf("----- VPUSH, VPOP -----\n"); + TESTINSN_vpush_vpop_f32(s3, 0x00aaaaaa, s4, 0x00bbbbbb, s5, 0x00cccccc, s0, s1, s2); + TESTINSN_vpush_vpop_f32(s1, 0x000134f4, s2, 0x0870ccb3, s3, 0x00aba0f1, s9, s10, s11); + TESTINSN_vpush_vpop_f32(s3, 0x00dddddd, s4, 0x00eeeeee, s5, 0x00ffffff, s0, s1, s2); + TESTINSN_vpush_vpop_f32(s11, 0x13454c, s12, 0x341, s13, 0xaac45f, s6, s7, s8); + TESTINSN_vpush_vpop_f32(s21, 0x0, s22, f2u(NAN), s23, f2u(INFINITY), s23, s24, s25); + TESTINSN_vpush_vpop_f32(s12, 0xffffff, s13, 0xf542dd4, s14, f2u(-INFINITY), s11, s12, s13); + TESTINSN_vpush_vpop_f32(s25, 0x45cd, s26, 0xa3ccb5, s27, 0xbbcaf, s0, s1, s2); + TESTINSN_vpush_vpop_f32(s1, f2u(NAN), s2, 0xaaca3, s3, 0x876008, s6, s7, s8); + TESTINSN_vpush_vpop_f32(s9, 0x2f43, s10, f2u(INFINITY), s11, 0x3cc66a, s9, s10, s11); + TESTINSN_vpush_vpop_f32(s10, f2u(INFINITY), s11, 0x134cc5, s12, f2u(NAN), s2, s3, s4); + TESTINSN_vpush_vpop_f32(s7, 0xcc006d, s8, 0x1308c, s9, 0xabbc45, s21, s22, s23); + TESTINSN_vpush_vpop_f32(s19, f2u(-INFINITY), s20, 0x452146, s21, 0x388bbc, s4, s5, s6); + TESTINSN_vpush_vpop_f32(s16, 0x542aa, s17, 0xaddcd5, s18, 0x87acc, s18, s19, s20); + TESTINSN_vpush_vpop_f32(s22, 0x5ccb708, s23, 0x52345c, s24, 0x98745c, s12, s13, s14); + TESTINSN_vpush_vpop_f32(s24, 0x99234f, s25, 0x1aac, s26, 0x3746c, s28, s29, s30); + TESTINSN_vpush_vpop_f32(s13, 0x134ccc, s14, 0x6bb43, s15, 0x834aa, s0, s1, s2); + TESTINSN_vpush_vpop_f64(d3, 0x00aaaaaa, 0xaac3, d4, 0x00bbbbbb, 0x34ccb, d0, d1); + TESTINSN_vpush_vpop_f64(d1, 0x000134f4, 0x341531, d2, 0x0870ccb3, 0x4576bbc, d9, d10); + TESTINSN_vpush_vpop_f64(d3, 0x00dddddd, 0x13451cc, d4, 0x00eeeeee, 0x123ddc8, d0, d1); + TESTINSN_vpush_vpop_f64(d11, 0x13454c, 0x541bbc3, d12, 0x341, 0xccb5, d6, d7); + TESTINSN_vpush_vpop_f64(d21, 0x0, 0x123c33, d22, f2u0(NAN), f2u1(NAN), d23, d24); + TESTINSN_vpush_vpop_f64(d12, 0xffffff, 0x1940c, d13, 0xf542dd4, 0x788ffc, d11, d12); + TESTINSN_vpush_vpop_f64(d25, 0x45cd, 0x1309c, d26, 0xa3ccb5, 0x4588b, d0, d1); + TESTINSN_vpush_vpop_f64(d1, f2u0(NAN), f2u1(NAN), d2, 0xaaca3, 0x1120a, d6, d7); + TESTINSN_vpush_vpop_f64(d9, 0x2f43, 0x19ff9, d10, f2u0(INFINITY), f2u1(INFINITY), d9, d10); + TESTINSN_vpush_vpop_f64(d10, f2u0(INFINITY), f2u1(INFINITY), d11, 0x134cc5, 0x78cbbd, d2, d3); + TESTINSN_vpush_vpop_f64(d7, 0xcc006d, 0x28354, d8, 0x1308c, 0x1993bc, d21, d22); + TESTINSN_vpush_vpop_f64(d19, f2u0(-INFINITY), f2u1(-INFINITY), d20, 0x452146, 0x138476c, d4, d5); + TESTINSN_vpush_vpop_f64(d16, 0x542aa, 0x12dd4, d17, 0xaddcd5, 0x399cb, d18, d19); + TESTINSN_vpush_vpop_f64(d22, 0x5ccb708, 0x8009c, d23, 0x52345c, 0x29902c, d12, d13); + TESTINSN_vpush_vpop_f64(d24, 0x99234f, 0x3457ff, d25, 0x1aac, 0x1002cba, d28, d29); + TESTINSN_vpush_vpop_f64(d13, 0x134ccc, 0xfaa309, d14, 0x6bb43, 0x199cb, d0, d1); + + return 0; +} diff --git a/none/tests/arm/vfp.stderr.exp b/none/tests/arm/vfp.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/arm/vfp.stdout.exp b/none/tests/arm/vfp.stdout.exp new file mode 100644 index 0000000..1f6be32 --- /dev/null +++ b/none/tests/arm/vfp.stdout.exp @@ -0,0 +1,1220 @@ +do_vldm_vstm_check: + 0x00000010 + 0x3a3b3c3d + 0x4a4b4c4d + 0x1a1b1c1d + 0x00000018 + 0x7a7b7c7d + 0x8a8b8c8d + 0x00000004 + 0x4a4b4c4d + 0x5a5b5c5d + 0x2a2b2c2d + 0x00000040 + 0xdadbdcdd + 0xeaebeced + 0xfafbfcfd + 0x0a0b0c0d + 0x0000002c + 0xcacbcccd + 0xdadbdcdd + 0xeaebeced + 0xfafbfcfd + 0x00000018 + 0x7a7b7c7d + 0x8a8b8c8d + 0x9a9b9c9d + 0xaaabacad + 0x00000010 + 0x00000010 + 0x00000018 + 0x00000030 + 0x00000030 + 0x00000038 +data: + 0x00000055 + 0x00000056 + 0x00000057 + 0x00000058 + 0x00000065 + 0x00000066 + 0x00000075 + 0x00000076 + 0x00000042 + 0x00000043 + 0x00000040 + 0x00000041 + 0x00000032 + 0x00000033 + 0x00000022 + 0x00000023 +---- VMOV (ARM core register to scalar) ---- +vmov.32 d0[0], r5 :: Dd 0x55555555 0x41500000 Dm 0x41500000 +vmov.32 d1[1], r6 :: Dd 0x00000012 0x55555555 Dm 0x00000012 +vmov.32 d20[0], r5 :: Dd 0x55555555 0x7fc00000 Dm 0x7fc00000 +vmov.32 d29[1], r6 :: Dd 0x432c0000 0x55555555 Dm 0x432c0000 +vmov.32 d30[0], r5 :: Dd 0x55555555 0x7f800000 Dm 0x7f800000 +vmov.32 d11[1], r6 :: Dd 0xff800000 0x55555555 Dm 0xff800000 +vmov.32 d18[0], r5 :: Dd 0x55555555 0x55555555 Dm 0x44234000 +vmov.32 d9[1], r6 :: Dd 0x0000000c 0x55555555 Dm 0x0000000c +vmov.16 d0[0], r5 :: Dd 0x55555555 0x5555000d Dm 0x0000000d +vmov.16 d14[1], r5 :: Dd 0x55555555 0x00005555 Dm 0x7fc00000 +vmov.16 d28[2], r6 :: Dd 0x5555000e 0x55555555 Dm 0x0000000e +vmov.16 d30[3], r1 :: Dd 0x00115555 0x55555555 Dm 0x00000011 +vmov.16 d0[0], r5 :: Dd 0x55555555 0x55550000 Dm 0x7f800000 +vmov.16 d7[1], r5 :: Dd 0x55555555 0x00005555 Dm 0xff800000 +vmov.16 d21[2], r6 :: Dd 0x5555000e 0x55555555 Dm 0x0000000e +vmov.16 d17[3], r1 :: Dd 0x00115555 0x55555555 Dm 0x00000011 +vmov.8 d0[0], r5 :: Dd 0x55555555 0x5555550d Dm 0x0000000d +vmov.8 d10[1], r5 :: Dd 0x55555555 0x55550055 Dm 0x7fc00000 +vmov.8 d20[2], r5 :: Dd 0x55555555 0x55005555 Dm 0x7f800000 +vmov.8 d30[3], r5 :: Dd 0x55555555 0x00555555 Dm 0xff800000 +vmov.8 d13[4], r5 :: Dd 0x555555d5 0x55555555 Dm 0x000000d5 +vmov.8 d17[5], r5 :: Dd 0x55553f55 0x55555555 Dm 0x0000053f +vmov.8 d24[6], r5 :: Dd 0x556f5555 0x55555555 Dm 0x0000006f +vmov.8 d29[7], r5 :: Dd 0xad555555 0x55555555 Dm 0x000000ad +---- VMOV (scalar to ARM core register) ---- +vmov.32 r5, d0[0] :: Rd 0x7fc00000 Qm (i32)0x7fc00000 +vmov.32 r6, d5[1] :: Rd 0x7f800000 Qm (i32)0x7f800000 +vmov.32 r4, d10[0] :: Rd 0xff800000 Qm (i32)0xff800000 +vmov.32 r5, d15[1] :: Rd 0x11223344 Qm (i32)0x11223344 +vmov.32 r9, d20[0] :: Rd 0x11223344 Qm (i32)0x11223344 +vmov.32 r8, d25[1] :: Rd 0x11223344 Qm (i32)0x11223344 +vmov.32 r0, d30[0] :: Rd 0x11223344 Qm (i32)0x11223344 +vmov.32 r2, d19[1] :: Rd 0x11223344 Qm (i32)0x11223344 +vmov.u16 r5, d31[0] :: Rd 0x00000000 Qm (i32)0x7fc00000 +vmov.u16 r3, d30[1] :: Rd 0x00007f80 Qm (i32)0x7f800000 +vmov.u16 r6, d21[2] :: Rd 0x00000000 Qm (i32)0xff800000 +vmov.u16 r9, d26[3] :: Rd 0x00001122 Qm (i32)0x11223344 +vmov.u16 r12, d11[0] :: Rd 0x00003344 Qm (i32)0x11223344 +vmov.u16 r0, d10[1] :: Rd 0x00001122 Qm (i32)0x11223344 +vmov.u16 r6, d1[2] :: Rd 0x00003344 Qm (i32)0x11223344 +vmov.u16 r8, d5[3] :: Rd 0x00001122 Qm (i32)0x11223344 +vmov.u8 r2, d4[0] :: Rd 0x00000000 Qm (i32)0x7fc00000 +vmov.u8 r6, d14[1] :: Rd 0x00000000 Qm (i32)0x7f800000 +vmov.u8 r9, d24[2] :: Rd 0x00000080 Qm (i32)0xff800000 +vmov.u8 r8, d31[3] :: Rd 0x00000011 Qm (i32)0x11223344 +vmov.u8 r10, d29[4] :: Rd 0x00000044 Qm (i32)0x11223344 +vmov.u8 r3, d19[5] :: Rd 0x00000033 Qm (i32)0x11223344 +vmov.u8 r12, d12[6] :: Rd 0x00000022 Qm (i32)0x11223344 +vmov.u8 r10, d18[4] :: Rd 0x00000044 Qm (i32)0x11223344 +vmov.s16 r5, d31[0] :: Rd 0x00000000 Qm (i32)0x7fc00000 +vmov.s16 r3, d30[1] :: Rd 0x00007f80 Qm (i32)0x7f800000 +vmov.s16 r6, d21[2] :: Rd 0x00000000 Qm (i32)0xff800000 +vmov.s16 r9, d26[3] :: Rd 0x00001122 Qm (i32)0x11223344 +vmov.s16 r4, d11[0] :: Rd 0x00003344 Qm (i32)0x11223344 +vmov.s16 r0, d10[1] :: Rd 0x00001122 Qm (i32)0x11223344 +vmov.s16 r6, d1[2] :: Rd 0x00003344 Qm (i32)0x11223344 +vmov.s16 r8, d5[3] :: Rd 0x00001122 Qm (i32)0x11223344 +vmov.s8 r2, d4[0] :: Rd 0x00000000 Qm (i32)0x7fc00000 +vmov.s8 r6, d14[1] :: Rd 0x00000000 Qm (i32)0x7f800000 +vmov.s8 r9, d24[2] :: Rd 0xffffff80 Qm (i32)0xff800000 +vmov.s8 r8, d31[3] :: Rd 0x00000011 Qm (i32)0x11223344 +vmov.s8 r6, d29[4] :: Rd 0x00000044 Qm (i32)0x11223344 +vmov.s8 r3, d19[5] :: Rd 0x00000033 Qm (i32)0x11223344 +vmov.s8 r12, d12[6] :: Rd 0x00000022 Qm (i32)0x11223344 +vmov.s8 r10, d18[7] :: Rd 0x00000011 Qm (i32)0x11223344 +---- VMLA (fp) ---- +vmla.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 +vmla.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 +vmla.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 +vmla.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 +vmla.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 +vmla.f64 d20, d25, d22 :: Qd 0xc0906794 0x842f8549 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vmla.f64 d23, d24, d25 :: Qd 0xc1bbe864 0x1f579999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vmla.f64 d20, d31, d12 :: Qd 0xc1e0a1cf 0xd2abe8f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vmla.f64 d19, d25, d27 :: Qd 0x41d860c7 0xf71a1999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vmla.f64 d30, d15, d2 :: Qd 0x420524a9 0x817febf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vmla.f64 d23, d24, d5 :: Qd 0x40df8c00 0x800001fc Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vmla.f64 d10, d11, d2 :: Qd 0x41895139 0x98100000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vmla.f64 d29, d15, d7 :: Qd 0x41b65928 0xd6020000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vmla.f64 d30, d11, d12 :: Qd 0x41df20a6 0xd7bd2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vmla.f64 d27, d21, d6 :: Qd 0x3fb763ef 0x4799be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vmla.f64 d30, d31, d2 :: Qd 0x4111fc58 0x08000020 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vmla.f64 d13, d24, d5 :: Qd 0x4132771c 0x6866666e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vmla.f64 d10, d11, d2 :: Qd 0x40e9f35f 0xb4bc6b7d Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vmla.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vmla.f64 d0, d11, d12 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vmla.f64 d27, d21, d16 :: Qd 0xc0aa0043 0x17cbec9d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vmla.f64 d0, d5, d2 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vmla.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vmla.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vmla.f32 s0, s11, s12 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 +vmla.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 +vmla.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 +vmla.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 +vmla.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 +vmla.f32 s20, s25, s22 :: Sd 0xc4833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vmla.f32 s23, s24, s25 :: Sd 0xcddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vmla.f32 s20, s31, s12 :: Sd 0xcf050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vmla.f32 s19, s25, s27 :: Sd 0x4ec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vmla.f32 s30, s15, s2 :: Sd 0x5029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vmla.f32 s23, s24, s5 :: Sd 0x46fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vmla.f32 s10, s11, s2 :: Sd 0x4c4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000 +vmla.f32 s29, s15, s7 :: Sd 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vmla.f32 s30, s11, s12 :: Sd 0x4ef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vmla.f32 s27, s21, s6 :: Sd 0x3dab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vmla.f32 s30, s31, s2 :: Sd 0x488fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vmla.f32 s13, s24, s5 :: Sd 0x4993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vmla.f32 s10, s11, s2 :: Sd 0x474f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vmla.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vmla.f32 s0, s11, s12 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vmla.f32 s27, s21, s16 :: Sd 0xc5500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vmla.f32 s0, s5, s2 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vmla.f32 s20, s13, s15 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vmla.f32 s10, s23, s15 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VNMLA (fp) ---- +vnmla.f64 d0, d11, d12 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 +vnmla.f64 d7, d1, d6 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 +vnmla.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 +vnmla.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 +vnmla.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 +vnmla.f64 d20, d25, d22 :: Qd 0x409067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vnmla.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vnmla.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vnmla.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vnmla.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817fcbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vnmla.f64 d23, d24, d5 :: Qd 0xc0df8bff 0x7ffffe04 Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vnmla.f64 d10, d11, d2 :: Qd 0xc1895139 0x97f00000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vnmla.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd5fe0000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vnmla.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bc2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vnmla.f64 d27, d21, d6 :: Qd 0xbfb363ef 0x37b9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vnmla.f64 d30, d31, d2 :: Qd 0xc111fc57 0xf7ffffe0 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vnmla.f64 d13, d24, d5 :: Qd 0xc132771c 0x6466665e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vnmla.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0x34bc6981 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vnmla.f64 d29, d25, d7 :: Qd 0x7ff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vnmla.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vnmla.f64 d27, d21, d16 :: Qd 0x40aa004b 0x17cc0c5d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vnmla.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vnmla.f64 d20, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vnmla.f64 d10, d23, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vnmla.f32 s0, s11, s12 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 +vnmla.f32 s7, s1, s6 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 +vnmla.f32 s0, s5, s2 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 +vnmla.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 +vnmla.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 +vnmla.f32 s20, s25, s22 :: Sd 0x44833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vnmla.f32 s23, s24, s25 :: Sd 0x4ddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vnmla.f32 s20, s31, s12 :: Sd 0x4f050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vnmla.f32 s19, s25, s27 :: Sd 0xcec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vnmla.f32 s30, s15, s2 :: Sd 0xd029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vnmla.f32 s23, s24, s5 :: Sd 0xc6fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vnmla.f32 s10, s11, s2 :: Sd 0xcc4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000 +vnmla.f32 s29, s15, s7 :: Sd 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vnmla.f32 s30, s11, s12 :: Sd 0xcef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vnmla.f32 s27, s21, s6 :: Sd 0xbdab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vnmla.f32 s30, s31, s2 :: Sd 0xc88fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vnmla.f32 s13, s24, s5 :: Sd 0xc993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vnmla.f32 s10, s11, s2 :: Sd 0xc74f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vnmla.f32 s29, s25, s7 :: Sd 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vnmla.f32 s0, s11, s12 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vnmla.f32 s27, s21, s16 :: Sd 0x45500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vnmla.f32 s0, s5, s2 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vnmla.f32 s20, s13, s15 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vnmla.f32 s10, s23, s15 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VMLS (fp) ---- +vmls.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 +vmls.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 +vmls.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 +vmls.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 +vmls.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 +vmls.f64 d20, d25, d22 :: Qd 0xc09067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vmls.f64 d23, d24, d25 :: Qd 0xc1bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vmls.f64 d20, d31, d12 :: Qd 0xc1e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vmls.f64 d19, d25, d27 :: Qd 0x41d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vmls.f64 d30, d15, d2 :: Qd 0x420524a9 0x817fcbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vmls.f64 d23, d24, d5 :: Qd 0x40df8bff 0x7ffffe04 Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vmls.f64 d10, d11, d2 :: Qd 0x41895139 0x97f00000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vmls.f64 d29, d15, d7 :: Qd 0x41b65928 0xd5fe0000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vmls.f64 d30, d11, d12 :: Qd 0x41df20a6 0xd7bc2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vmls.f64 d27, d21, d6 :: Qd 0x3fb363ef 0x37b9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vmls.f64 d30, d31, d2 :: Qd 0x4111fc57 0xf7ffffe0 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vmls.f64 d13, d24, d5 :: Qd 0x4132771c 0x6466665e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vmls.f64 d10, d11, d2 :: Qd 0x40e9f35f 0x34bc6981 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vmls.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vmls.f64 d0, d11, d12 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vmls.f64 d27, d21, d16 :: Qd 0xc0aa004b 0x17cc0c5d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vmls.f64 d0, d5, d2 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vmls.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vmls.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vmls.f32 s0, s11, s12 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 +vmls.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 +vmls.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 +vmls.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 +vmls.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 +vmls.f32 s20, s25, s22 :: Sd 0xc4833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vmls.f32 s23, s24, s25 :: Sd 0xcddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vmls.f32 s20, s31, s12 :: Sd 0xcf050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vmls.f32 s19, s25, s27 :: Sd 0x4ec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vmls.f32 s30, s15, s2 :: Sd 0x5029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vmls.f32 s23, s24, s5 :: Sd 0x46fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vmls.f32 s10, s11, s2 :: Sd 0x4c4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000 +vmls.f32 s29, s15, s7 :: Sd 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vmls.f32 s30, s11, s12 :: Sd 0x4ef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vmls.f32 s27, s21, s6 :: Sd 0x3dab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vmls.f32 s30, s31, s2 :: Sd 0x488fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vmls.f32 s13, s24, s5 :: Sd 0x4993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vmls.f32 s10, s11, s2 :: Sd 0x474f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vmls.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vmls.f32 s0, s11, s12 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vmls.f32 s27, s21, s16 :: Sd 0xc5500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vmls.f32 s0, s5, s2 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vmls.f32 s20, s13, s15 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vmls.f32 s10, s23, s15 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VNMLS (fp) ---- +vnmls.f64 d0, d11, d12 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 +vnmls.f64 d7, d1, d6 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 +vnmls.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 +vnmls.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 +vnmls.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 +vnmls.f64 d20, d25, d22 :: Qd 0x40906794 0x842f8549 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vnmls.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f579999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vnmls.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2abe8f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vnmls.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf71a1999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vnmls.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817febf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vnmls.f64 d23, d24, d5 :: Qd 0xc0df8c00 0x800001fc Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vnmls.f64 d10, d11, d2 :: Qd 0xc1895139 0x98100000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vnmls.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd6020000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vnmls.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bd2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vnmls.f64 d27, d21, d6 :: Qd 0xbfb763ef 0x4799be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vnmls.f64 d30, d31, d2 :: Qd 0xc111fc58 0x08000020 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vnmls.f64 d13, d24, d5 :: Qd 0xc132771c 0x6866666e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vnmls.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0xb4bc6b7d Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vnmls.f64 d29, d25, d7 :: Qd 0x7ff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vnmls.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vnmls.f64 d27, d21, d16 :: Qd 0x40aa0043 0x17cbec9d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vnmls.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vnmls.f64 d20, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vnmls.f64 d10, d23, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vnmls.f32 s0, s11, s12 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 +vnmls.f32 s7, s1, s6 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 +vnmls.f32 s0, s5, s2 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 +vnmls.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 +vnmls.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 +vnmls.f32 s20, s25, s22 :: Sd 0x44833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vnmls.f32 s23, s24, s25 :: Sd 0x4ddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vnmls.f32 s20, s31, s12 :: Sd 0x4f050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vnmls.f32 s19, s25, s27 :: Sd 0xcec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vnmls.f32 s30, s15, s2 :: Sd 0xd029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vnmls.f32 s23, s24, s5 :: Sd 0xc6fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vnmls.f32 s10, s11, s2 :: Sd 0xcc4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000 +vnmls.f32 s29, s15, s7 :: Sd 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vnmls.f32 s30, s11, s12 :: Sd 0xcef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vnmls.f32 s27, s21, s6 :: Sd 0xbdab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vnmls.f32 s30, s31, s2 :: Sd 0xc88fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vnmls.f32 s13, s24, s5 :: Sd 0xc993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vnmls.f32 s10, s11, s2 :: Sd 0xc74f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vnmls.f32 s29, s25, s7 :: Sd 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vnmls.f32 s0, s11, s12 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vnmls.f32 s27, s21, s16 :: Sd 0x45500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vnmls.f32 s0, s5, s2 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vnmls.f32 s20, s13, s15 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vnmls.f32 s10, s23, s15 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VMUL (fp) ---- +vmul.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 +vmul.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 +vmul.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 +vmul.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 +vmul.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 +vmul.f64 d20, d25, d22 :: Qd 0xc090679c 0x842fa509 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vmul.f64 d23, d24, d25 :: Qd 0xc1bbe864 0x1f599999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vmul.f64 d20, d31, d12 :: Qd 0xc1e0a1cf 0xd2ac28f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vmul.f64 d19, d25, d27 :: Qd 0x41d860c7 0xf7199999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vmul.f64 d30, d15, d2 :: Qd 0x420524a9 0x817fdbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vmul.f64 d23, d24, d5 :: Qd 0x40df8c00 0x00000000 Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vmul.f64 d10, d11, d2 :: Qd 0x41895139 0x98000000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vmul.f64 d29, d15, d7 :: Qd 0x41b65928 0xd6000000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vmul.f64 d30, d11, d12 :: Qd 0x41df20a6 0xd7bcacb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vmul.f64 d27, d21, d6 :: Qd 0x3fb563ef 0x3fa9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vmul.f64 d30, d31, d2 :: Qd 0x4111fc58 0x00000000 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vmul.f64 d13, d24, d5 :: Qd 0x4132771c 0x66666666 Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vmul.f64 d10, d11, d2 :: Qd 0x40e9f35f 0x74bc6a7f Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vmul.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vmul.f64 d0, d11, d12 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vmul.f64 d27, d21, d16 :: Qd 0xc0aa0047 0x17cbfc7d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vmul.f64 d0, d5, d2 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vmul.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vmul.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vmul.f32 s0, s11, s12 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 +vmul.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 +vmul.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 +vmul.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 +vmul.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 +vmul.f32 s20, s25, s22 :: Sd 0xc4833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vmul.f32 s23, s24, s25 :: Sd 0xcddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vmul.f32 s20, s31, s12 :: Sd 0xcf050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vmul.f32 s19, s25, s27 :: Sd 0x4ec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vmul.f32 s30, s15, s2 :: Sd 0x5029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vmul.f32 s23, s24, s5 :: Sd 0x46fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vmul.f32 s10, s11, s2 :: Sd 0x4c4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000 +vmul.f32 s29, s15, s7 :: Sd 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vmul.f32 s30, s11, s12 :: Sd 0x4ef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vmul.f32 s27, s21, s6 :: Sd 0x3dab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vmul.f32 s30, s31, s2 :: Sd 0x488fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vmul.f32 s13, s24, s5 :: Sd 0x4993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vmul.f32 s10, s11, s2 :: Sd 0x474f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vmul.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vmul.f32 s0, s11, s12 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vmul.f32 s27, s21, s16 :: Sd 0xc5500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vmul.f32 s0, s5, s2 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vmul.f32 s20, s13, s15 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vmul.f32 s10, s23, s15 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VNMUL (fp) ---- +vnmul.f64 d0, d11, d12 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 +vnmul.f64 d7, d1, d6 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 +vnmul.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 +vnmul.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 +vnmul.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 +vnmul.f64 d20, d25, d22 :: Qd 0x4090679c 0x842fa509 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vnmul.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f599999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vnmul.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2ac28f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vnmul.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf7199999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vnmul.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817fdbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vnmul.f64 d23, d24, d5 :: Qd 0xc0df8c00 0x00000000 Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vnmul.f64 d10, d11, d2 :: Qd 0xc1895139 0x98000000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vnmul.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd6000000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vnmul.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bcacb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vnmul.f64 d27, d21, d6 :: Qd 0xbfb563ef 0x3fa9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vnmul.f64 d30, d31, d2 :: Qd 0xc111fc58 0x00000000 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vnmul.f64 d13, d24, d5 :: Qd 0xc132771c 0x66666666 Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vnmul.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0x74bc6a7f Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vnmul.f64 d29, d25, d7 :: Qd 0x7ff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vnmul.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vnmul.f64 d27, d21, d16 :: Qd 0x40aa0047 0x17cbfc7d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vnmul.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vnmul.f64 d20, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vnmul.f64 d10, d23, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vnmul.f32 s0, s11, s12 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 +vnmul.f32 s7, s1, s6 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 +vnmul.f32 s0, s5, s2 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 +vnmul.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 +vnmul.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 +vnmul.f32 s20, s25, s22 :: Sd 0x44833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vnmul.f32 s23, s24, s25 :: Sd 0x4ddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vnmul.f32 s20, s31, s12 :: Sd 0x4f050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vnmul.f32 s19, s25, s27 :: Sd 0xcec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vnmul.f32 s30, s15, s2 :: Sd 0xd029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vnmul.f32 s23, s24, s5 :: Sd 0xc6fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vnmul.f32 s10, s11, s2 :: Sd 0xcc4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000 +vnmul.f32 s29, s15, s7 :: Sd 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vnmul.f32 s30, s11, s12 :: Sd 0xcef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vnmul.f32 s27, s21, s6 :: Sd 0xbdab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vnmul.f32 s30, s31, s2 :: Sd 0xc88fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vnmul.f32 s13, s24, s5 :: Sd 0xc993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vnmul.f32 s10, s11, s2 :: Sd 0xc74f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vnmul.f32 s29, s25, s7 :: Sd 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vnmul.f32 s0, s11, s12 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vnmul.f32 s27, s21, s16 :: Sd 0x45500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vnmul.f32 s0, s5, s2 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vnmul.f32 s20, s13, s15 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vnmul.f32 s10, s23, s15 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VADD (fp) ---- +vadd.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 +vadd.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 +vadd.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 +vadd.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 +vadd.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 +vadd.f64 d20, d25, d22 :: Qd 0xc0368758 0xe219652c Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vadd.f64 d23, d24, d25 :: Qd 0xc1152639 0xe6666666 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vadd.f64 d20, d31, d12 :: Qd 0x40a7310c 0x49ba5e30 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vadd.f64 d19, d25, d27 :: Qd 0x40fb924c 0x28f5c28f Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vadd.f64 d30, d15, d2 :: Qd 0xc111f558 0x00000000 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vadd.f64 d23, d24, d5 :: Qd 0x40956800 0x00000000 Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vadd.f64 d10, d11, d2 :: Qd 0x40e85680 0x00000000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vadd.f64 d29, d15, d7 :: Qd 0x413abcd7 0x00000000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vadd.f64 d30, d11, d12 :: Qd 0x411616ea 0x46a7ef9e Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vadd.f64 d27, d21, d6 :: Qd 0x4041005f 0x99c38b04 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vadd.f64 d30, d31, d2 :: Qd 0x40a65a00 0x00000000 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vadd.f64 d13, d24, d5 :: Qd 0x40a1a533 0x33333333 Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vadd.f64 d10, d11, d2 :: Qd 0x4082a4b2 0x2d0e5604 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vadd.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vadd.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vadd.f64 d27, d21, d16 :: Qd 0x407c0f45 0x2cfb0ace Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vadd.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vadd.f64 d20, d13, d15 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vadd.f64 d10, d23, d15 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vadd.f32 s0, s11, s12 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 +vadd.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 +vadd.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 +vadd.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 +vadd.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 +vadd.f32 s20, s25, s22 :: Sd 0xc1b43ac6 Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vadd.f32 s23, s24, s25 :: Sd 0xc8a931cf Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vadd.f32 s20, s31, s12 :: Sd 0x45398860 Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vadd.f32 s19, s25, s27 :: Sd 0x47dc9261 Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vadd.f32 s30, s15, s2 :: Sd 0xc88faac0 Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vadd.f32 s23, s24, s5 :: Sd 0x44ab4000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vadd.f32 s10, s11, s2 :: Sd 0x4742b400 Sm (i32)0x473e7300 Sn (i32)0x44882000 +vadd.f32 s29, s15, s7 :: Sd 0x49d5e6b8 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vadd.f32 s30, s11, s12 :: Sd 0x48b0b752 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vadd.f32 s27, s21, s6 :: Sd 0x420802fd Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vadd.f32 s30, s31, s2 :: Sd 0x4532d000 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vadd.f32 s13, s24, s5 :: Sd 0x450d299a Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vadd.f32 s10, s11, s2 :: Sd 0x44152592 Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vadd.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vadd.f32 s0, s11, s12 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vadd.f32 s27, s21, s16 :: Sd 0x43e07a2a Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vadd.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vadd.f32 s20, s13, s15 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vadd.f32 s10, s23, s15 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VSUB (fp) ---- +vsub.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 +vsub.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 +vsub.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 +vsub.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 +vsub.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 +vsub.f64 d20, d25, d22 :: Qd 0x405126f4 0xf0d844d0 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vsub.f64 d23, d24, d25 :: Qd 0xc1155049 0xe6666666 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vsub.f64 d20, d31, d12 :: Qd 0x40f714d7 0x9db22d0e Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vsub.f64 d19, d25, d27 :: Qd 0x40f33d2c 0x28f5c28f Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vsub.f64 d30, d15, d2 :: Qd 0x4108c47c 0x28f5c290 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vsub.f64 d23, d24, d5 :: Qd 0xc094a800 0x00000000 Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vsub.f64 d10, d11, d2 :: Qd 0x40e74640 0x00000000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vsub.f64 d29, d15, d7 :: Qd 0xc13abb2b 0x00000000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vsub.f64 d30, d11, d12 :: Qd 0x41155f92 0x34395810 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vsub.f64 d27, d21, d6 :: Qd 0x4040ffbe 0x8bc169c2 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vsub.f64 d30, d31, d2 :: Qd 0x40a4ae00 0x00000000 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vsub.f64 d13, d24, d5 :: Qd 0xc07fe999 0x99999998 Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vsub.f64 d10, d11, d2 :: Qd 0x4077a964 0x5a1cac08 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vsub.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vsub.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vsub.f64 d27, d21, d16 :: Qd 0x407cf8b2 0x46031990 Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vsub.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vsub.f64 d20, d13, d15 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vsub.f64 d10, d23, d15 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vsub.f32 s0, s11, s12 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 +vsub.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 +vsub.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 +vsub.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 +vsub.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 +vsub.f32 s20, s25, s22 :: Sd 0x428937a8 Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vsub.f32 s23, s24, s25 :: Sd 0xc8aa824f Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vsub.f32 s20, s31, s12 :: Sd 0x47b8a6bd Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vsub.f32 s19, s25, s27 :: Sd 0x4799e961 Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vsub.f32 s30, s15, s2 :: Sd 0x484623e2 Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vsub.f32 s23, s24, s5 :: Sd 0xc4a54000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vsub.f32 s10, s11, s2 :: Sd 0x473a3200 Sm (i32)0x473e7300 Sn (i32)0x44882000 +vsub.f32 s29, s15, s7 :: Sd 0xc9d5d958 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vsub.f32 s30, s11, s12 :: Sd 0x48aafc92 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vsub.f32 s27, s21, s6 :: Sd 0x4207fdf5 Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vsub.f32 s30, s31, s2 :: Sd 0x45257000 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vsub.f32 s13, s24, s5 :: Sd 0xc3ff4ccc Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vsub.f32 s10, s11, s2 :: Sd 0x43bd4b23 Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vsub.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vsub.f32 s0, s11, s12 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vsub.f32 s27, s21, s16 :: Sd 0x43e7c592 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vsub.f32 s0, s5, s2 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vsub.f32 s20, s13, s15 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vsub.f32 s10, s23, s15 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VDIV (fp) ---- +vdiv.f64 d20, d25, d22 :: Qd 0xbfe02df5 0x76d6419a Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b +vdiv.f64 d23, d24, d25 :: Qd 0xc07026fe 0xc863346b Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 +vdiv.f64 d20, d31, d12 :: Qd 0xbff1098f 0x758c5d80 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d +vdiv.f64 d19, d25, d27 :: Qd 0x401678a0 0x9bfa11ab Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 +vdiv.f64 d30, d15, d2 :: Qd 0x3fc7844e 0x96972113 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 +vdiv.f64 d23, d24, d5 :: Qd 0x3f92422f 0xedbdd012 Qm 0x40380000 00000000 Qn 0x40950800 00000000 +vdiv.f64 d10, d11, d2 :: Qd 0x4046629d 0x80967330 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 +vdiv.f64 d29, d15, d7 :: Qd 0x3f200264 0x3ec040af Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 +vdiv.f64 d30, d11, d12 :: Qd 0x404e57db 0x6cbb9f42 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa +vdiv.f64 d27, d21, d6 :: Qd 0x40cb05b1 0x59d8ef97 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd +vdiv.f64 d30, d31, d2 :: Qd 0x4039bd02 0x647c6945 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 +vdiv.f64 d13, d24, d5 :: Qd 0x3fe43307 0xa78c550d Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 +vdiv.f64 d10, d11, d2 :: Qd 0x4011e4a2 0x43006502 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 +vdiv.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 +vdiv.f64 d0, d11, d12 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f +vdiv.f64 d27, d21, d16 :: Qd 0xc04f45f0 0x7ea9eeda Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 +vdiv.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 +vdiv.f64 d20, d13, d15 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 +vdiv.f64 d10, d23, d15 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 +vdiv.f32 s20, s25, s22 :: Sd 0xbf016fac Sm (i32)0x41b851ec Sn (i32)0xc2364659 +vdiv.f32 s23, s24, s25 :: Sd 0xc38137f6 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 +vdiv.f32 s20, s31, s12 :: Sd 0xbf884c7c Sm (i32)0x473e7300 Sn (i32)0xc732da7a +vdiv.f32 s19, s25, s27 :: Sd 0x40b3c505 Sm (i32)0x47bb3de1 Sn (i32)0x46855200 +vdiv.f32 s30, s15, s2 :: Sd 0x3e3c2274 Sm (i32)0xc732633d Sn (i32)0xc872bcb1 +vdiv.f32 s23, s24, s5 :: Sd 0x3c92117f Sm (i32)0x41c00000 Sn (i32)0x44a84000 +vdiv.f32 s10, s11, s2 :: Sd 0x423314ec Sm (i32)0x473e7300 Sn (i32)0x44882000 +vdiv.f32 s29, s15, s7 :: Sd 0x39001322 Sm (i32)0x43560000 Sn (i32)0x49d5e008 +vdiv.f32 s30, s11, s12 :: Sd 0x4272bedc Sm (i32)0x48add9f2 Sn (i32)0x45b75812 +vdiv.f32 s27, s21, s6 :: Sd 0x46582d8c Sm (i32)0x42080079 Sn (i32)0x3b210e02 +vdiv.f32 s30, s31, s2 :: Sd 0x41cde813 Sm (i32)0x452c2000 Sn (i32)0x42d60000 +vdiv.f32 s13, s24, s5 :: Sd 0x3f21983d Sm (i32)0x445a8000 Sn (i32)0x44ad1333 +vdiv.f32 s10, s11, s2 :: Sd 0x408f2512 Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 +vdiv.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 +vdiv.f32 s0, s11, s12 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 +vdiv.f32 s27, s21, s16 :: Sd 0xc27a2f84 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 +vdiv.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0xff800000 +vdiv.f32 s20, s13, s15 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x00000000 +vdiv.f32 s10, s23, s15 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0x00000000 +---- VABS ---- +vabs.f64 d15, d4 :: Dd 0x7ff80000 0x00000000 Dm (i32)0x7ff80000 00000000 +vabs.f64 d31, d4 :: Dd 0x7ff80000 0x00000000 Dm (i32)0x7ff80000 00000000 +vabs.f64 d25, d25 :: Dd 0x55555555 0x55555555 Dm (i32)0x7ff00000 00000000 +vabs.f64 d18, d17 :: Dd 0x7ff00000 0x00000000 Dm (i32)0x7ff00000 00000000 +vabs.f64 d30, d1 :: Dd 0x7ff00000 0x00000000 Dm (i32)0xfff00000 00000000 +vabs.f64 d8, d27 :: Dd 0x7ff00000 0x00000000 Dm (i32)0xfff00000 00000000 +vabs.f64 d20, d1 :: Dd 0x40f2aff0 0x041aac54 Dm (i32)0x40f2aff0 041aac54 +vabs.f64 d28, d7 :: Dd 0x40b2f83b 0xe76c8b44 Dm (i32)0xc0b2f83b e76c8b44 +vabs.f64 d2, d19 :: Dd 0x4055c649 0x2ff4ba52 Dm (i32)0x4055c649 2ff4ba52 +vabs.f64 d8, d7 :: Dd 0x40fdd2c3 0x33333333 Dm (i32)0xc0fdd2c3 33333333 +vabs.f32 s15, s4 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 +vabs.f32 s31, s4 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 +vabs.f32 s25, s25 :: Sd 0x7fffaaaa Sm (i32)0x7f800000 +vabs.f32 s18, s17 :: Sd 0x7f800000 Sm (i32)0x7f800000 +vabs.f32 s30, s1 :: Sd 0x7f800000 Sm (i32)0xff800000 +vabs.f32 s8, s27 :: Sd 0x7f800000 Sm (i32)0xff800000 +vabs.f32 s20, s1 :: Sd 0x47957f80 Sm (i32)0x47957f80 +vabs.f32 s28, s7 :: Sd 0x4597c1df Sm (i32)0xc597c1df +vabs.f32 s2, s19 :: Sd 0x42ae3249 Sm (i32)0x42ae3249 +vabs.f32 s8, s7 :: Sd 0x47ee961a Sm (i32)0xc7ee961a +---- VNEG ---- +vneg.f64 d15, d4 :: Dd 0xfff80000 0x00000000 Dm (i32)0x7ff80000 00000000 +vneg.f64 d31, d4 :: Dd 0xfff80000 0x00000000 Dm (i32)0x7ff80000 00000000 +vneg.f64 d25, d25 :: Dd 0xd5555555 0x55555555 Dm (i32)0x7ff00000 00000000 +vneg.f64 d18, d17 :: Dd 0xfff00000 0x00000000 Dm (i32)0x7ff00000 00000000 +vneg.f64 d30, d1 :: Dd 0x7ff00000 0x00000000 Dm (i32)0xfff00000 00000000 +vneg.f64 d8, d27 :: Dd 0x7ff00000 0x00000000 Dm (i32)0xfff00000 00000000 +vneg.f64 d20, d1 :: Dd 0xc0f2aff0 0x041aac54 Dm (i32)0x40f2aff0 041aac54 +vneg.f64 d28, d7 :: Dd 0x40b2f83b 0xe76c8b44 Dm (i32)0xc0b2f83b e76c8b44 +vneg.f64 d2, d19 :: Dd 0xc055c649 0x2ff4ba52 Dm (i32)0x4055c649 2ff4ba52 +vneg.f64 d8, d7 :: Dd 0x40fdd2c3 0x33333333 Dm (i32)0xc0fdd2c3 33333333 +vneg.f32 s15, s4 :: Sd 0xffc00000 Sm (i32)0x7fc00000 +vneg.f32 s31, s4 :: Sd 0xffc00000 Sm (i32)0x7fc00000 +vneg.f32 s25, s25 :: Sd 0x7fffaaaa Sm (i32)0x7f800000 +vneg.f32 s18, s17 :: Sd 0xff800000 Sm (i32)0x7f800000 +vneg.f32 s30, s1 :: Sd 0x7f800000 Sm (i32)0xff800000 +vneg.f32 s8, s27 :: Sd 0x7f800000 Sm (i32)0xff800000 +vneg.f32 s20, s1 :: Sd 0xc7957f80 Sm (i32)0x47957f80 +vneg.f32 s28, s7 :: Sd 0x4597c1df Sm (i32)0xc597c1df +vneg.f32 s2, s19 :: Sd 0xc2ae3249 Sm (i32)0x42ae3249 +vneg.f32 s8, s7 :: Sd 0x47ee961a Sm (i32)0xc7ee961a +---- VMOV (register) ---- +vmov.f64 d15, d4 :: Dd 0x7ff80000 0x00000000 Dm (i32)0x7ff80000 00000000 +vmov.f64 d31, d4 :: Dd 0x7ff80000 0x00000000 Dm (i32)0x7ff80000 00000000 +vmov.f64 d25, d25 :: Dd 0x55555555 0x55555555 Dm (i32)0x7ff00000 00000000 +vmov.f64 d18, d17 :: Dd 0x7ff00000 0x00000000 Dm (i32)0x7ff00000 00000000 +vmov.f64 d30, d1 :: Dd 0xfff00000 0x00000000 Dm (i32)0xfff00000 00000000 +vmov.f64 d8, d27 :: Dd 0xfff00000 0x00000000 Dm (i32)0xfff00000 00000000 +vmov.f64 d20, d1 :: Dd 0x40f2aff0 0x041aac54 Dm (i32)0x40f2aff0 041aac54 +vmov.f64 d28, d7 :: Dd 0xc0b2f83b 0xe76c8b44 Dm (i32)0xc0b2f83b e76c8b44 +vmov.f64 d2, d19 :: Dd 0x4055c649 0x2ff4ba52 Dm (i32)0x4055c649 2ff4ba52 +vmov.f64 d8, d7 :: Dd 0xc0fdd2c3 0x33333333 Dm (i32)0xc0fdd2c3 33333333 +vmov.f32 s15, s4 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 +vmov.f32 s31, s4 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 +vmov.f32 s25, s25 :: Sd 0xffffaaaa Sm (i32)0x7f800000 +vmov.f32 s18, s17 :: Sd 0x7f800000 Sm (i32)0x7f800000 +vmov.f32 s30, s1 :: Sd 0xff800000 Sm (i32)0xff800000 +vmov.f32 s8, s27 :: Sd 0xff800000 Sm (i32)0xff800000 +vmov.f32 s20, s1 :: Sd 0x47957f80 Sm (i32)0x47957f80 +vmov.f32 s28, s7 :: Sd 0xc597c1df Sm (i32)0xc597c1df +vmov.f32 s2, s19 :: Sd 0x42ae3249 Sm (i32)0x42ae3249 +vmov.f32 s8, s7 :: Sd 0xc7ee961a Sm (i32)0xc7ee961a +---- VSQRT ---- +vsqrt.f64 d15, d4 :: Dd 0x7ff80000 0x00000000 Dm (i32)0x7ff80000 00000000 +vsqrt.f64 d31, d4 :: Dd 0x7ff80000 0x00000000 Dm (i32)0x7ff80000 00000000 +vsqrt.f64 d25, d25 :: Dd 0x4aa279a7 0x4590331c Dm (i32)0x7ff00000 00000000 +vsqrt.f64 d18, d17 :: Dd 0x7ff00000 0x00000000 Dm (i32)0x7ff00000 00000000 +vsqrt.f64 d30, d1 :: Dd 0x7ff80000 0x00000000 Dm (i32)0xfff00000 00000000 +vsqrt.f64 d8, d27 :: Dd 0x7ff80000 0x00000000 Dm (i32)0xfff00000 00000000 +vsqrt.f64 d20, d1 :: Dd 0x40714a9f 0xfb4e5577 Dm (i32)0x40f2aff0 041aac54 +vsqrt.f64 d28, d7 :: Dd 0x7ff80000 0x00000000 Dm (i32)0xc0b2f83b e76c8b44 +vsqrt.f64 d2, d19 :: Dd 0x4022aa50 0x1fe2a179 Dm (i32)0x4055c649 2ff4ba52 +vsqrt.f64 d8, d7 :: Dd 0x7ff80000 0x00000000 Dm (i32)0xc0fdd2c3 33333333 +vsqrt.f32 s15, s4 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 +vsqrt.f32 s31, s4 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 +vsqrt.f32 s25, s25 :: Sd 0xffffaaaa Sm (i32)0x7f800000 +vsqrt.f32 s18, s17 :: Sd 0x7f800000 Sm (i32)0x7f800000 +vsqrt.f32 s30, s1 :: Sd 0x7fc00000 Sm (i32)0xff800000 +vsqrt.f32 s8, s27 :: Sd 0x7fc00000 Sm (i32)0xff800000 +vsqrt.f32 s20, s1 :: Sd 0x438a5500 Sm (i32)0x47957f80 +vsqrt.f32 s28, s7 :: Sd 0x7fc00000 Sm (i32)0xc597c1df +vsqrt.f32 s2, s19 :: Sd 0x41155281 Sm (i32)0x42ae3249 +vsqrt.f32 s8, s7 :: Sd 0x7fc00000 Sm (i32)0xc7ee961a +---- VCVT (integer <-> fp) ---- +vcvt.u32.f32 s0, s1 :: Sd 0x00000003 Sm (i32)0x404ccccd +vcvt.u32.f32 s10, s11 :: Sd 0xffffffff Sm (i32)0x64cb49b4 +vcvt.u32.f32 s15, s4 :: Sd 0xb2d05e00 Sm (i32)0x4f32d05e +vcvt.u32.f32 s25, s24 :: Sd 0x00000000 Sm (i32)0xbf000000 +vcvt.u32.f32 s19, s21 :: Sd 0x00000000 Sm (i32)0xc0e33333 +vcvt.u32.f32 s12, s8 :: Sd 0x00000008 Sm (i32)0x40fff800 +vcvt.u32.f32 s12, s18 :: Sd 0x00000000 Sm (i32)0xc0fff800 +vcvt.u32.f32 s30, s1 :: Sd 0x00000000 Sm (i32)0x00000000 +vcvt.u32.f32 s11, s1 :: Sd 0xffffffff Sm (i32)0x7f800000 +vcvt.u32.f32 s21, s12 :: Sd 0x00000000 Sm (i32)0xff800000 +vcvt.u32.f32 s20, s11 :: Sd 0x00000000 Sm (i32)0x7fc00000 +vcvt.s32.f32 s29, s13 :: Sd 0x00000000 Sm (i32)0x7fc00000 +vcvt.s32.f32 s9, s19 :: Sd 0x00000000 Sm (i32)0x00000000 +vcvt.s32.f32 s0, s17 :: Sd 0x7fffffff Sm (i32)0x7f800000 +vcvt.s32.f32 s0, s1 :: Sd 0x80000000 Sm (i32)0xff800000 +vcvt.s32.f32 s30, s11 :: Sd 0x00000003 Sm (i32)0x404ccccd +vcvt.s32.f32 s20, s21 :: Sd 0x7fffffff Sm (i32)0x64cb49b4 +vcvt.s32.f32 s15, s14 :: Sd 0x7fffffff Sm (i32)0x4f32d05e +vcvt.s32.f32 s15, s24 :: Sd 0x00000000 Sm (i32)0xbf000000 +vcvt.s32.f32 s15, s29 :: Sd 0xfffffff9 Sm (i32)0xc0e33333 +vcvt.s32.f32 s12, s31 :: Sd 0x00000008 Sm (i32)0x40fff800 +vcvt.s32.f32 s1, s8 :: Sd 0xfffffff8 Sm (i32)0xc0fff800 +vcvt.f32.u32 s30, s1 :: Sd 0x4e81c000 Sm (i32)0x40e00000 +vcvt.f32.u32 s10, s17 :: Sd 0x4f4f0000 Sm (i32)0xcf000000 +vcvt.f32.u32 s20, s1 :: Sd 0x4e9e0000 Sm (i32)0x4f000000 +vcvt.f32.u32 s24, s26 :: Sd 0x4e9e0000 Sm (i32)0x4f000000 +vcvt.f32.u32 s0, s14 :: Sd 0x4e9c8506 Sm (i32)0x4e4282f4 +vcvt.f32.u32 s11, s1 :: Sd 0x4eff0000 Sm (i32)0x7f800000 +vcvt.f32.u32 s21, s12 :: Sd 0x4f7f8000 Sm (i32)0xff800000 +vcvt.f32.u32 s29, s13 :: Sd 0x4eff8000 Sm (i32)0x7fc00000 +vcvt.f32.s32 s0, s1 :: Sd 0x4e81c000 Sm (i32)0x40e00000 +vcvt.f32.s32 s30, s31 :: Sd 0xce440000 Sm (i32)0xcf000000 +vcvt.f32.s32 s0, s12 :: Sd 0x4e9e0000 Sm (i32)0x4f000000 +vcvt.f32.s32 s10, s16 :: Sd 0x4e9e0000 Sm (i32)0x4f000000 +vcvt.f32.s32 s1, s8 :: Sd 0xce7c0020 Sm (i32)0xc0fff800 +vcvt.f32.s32 s29, s13 :: Sd 0x4eff8000 Sm (i32)0x7fc00000 +vcvt.f32.s32 s9, s19 :: Sd 0x00000000 Sm (i32)0x00000000 +vcvt.f32.s32 s0, s17 :: Sd 0x4eff0000 Sm (i32)0x7f800000 +vcvt.f32.s32 s0, s1 :: Sd 0xcb000000 Sm (i32)0xff800000 +vcvt.u32.f64 s0, d1 :: Sd 0x00000003 Dm 0x40099999 9999999a +vcvt.u32.f64 s13, d26 :: Sd 0x000000eb Dm 0x406d5147 ae147ae1 +vcvt.u32.f64 s29, d30 :: Sd 0x0000b4a5 Dm 0x40e694ab 0a3d70a4 +vcvt.u32.f64 s30, d21 :: Sd 0x00000000 Dm 0xc01fff00 00000000 +vcvt.u32.f64 s11, d8 :: Sd 0xffffffff Dm 0x7ff00000 00000000 +vcvt.u32.f64 s8, d12 :: Sd 0x00000000 Dm 0xfff00000 00000000 +vcvt.u32.f64 s19, d7 :: Sd 0x00000000 Dm 0x7ff80000 00000000 +vcvt.u32.f64 s16, d16 :: Sd 0x0000004d Dm 0x40532ae1 47ae147b +vcvt.s32.f64 s0, d1 :: Sd 0x00000003 Dm 0x40099999 9999999a +vcvt.s32.f64 s13, d26 :: Sd 0x000000eb Dm 0x406d5147 ae147ae1 +vcvt.s32.f64 s29, d30 :: Sd 0x0000b4a5 Dm 0x40e694ab 0a3d70a4 +vcvt.s32.f64 s30, d21 :: Sd 0xfffffff8 Dm 0xc01fff00 00000000 +vcvt.s32.f64 s11, d8 :: Sd 0x7fffffff Dm 0x7ff00000 00000000 +vcvt.s32.f64 s8, d12 :: Sd 0x80000000 Dm 0xfff00000 00000000 +vcvt.s32.f64 s19, d7 :: Sd 0x00000000 Dm 0x7ff80000 00000000 +vcvt.s32.f64 s16, d16 :: Sd 0x0000004d Dm 0x40532ae1 47ae147b +vcvt.f64.u32 d0, s1 :: Dd 0xfe000000 41efffff Sm 0x404ccccd +vcvt.f64.u32 d30, s21 :: Dd 0x5c200000 41e88483 Sm 0xc4241ae1 +vcvt.f64.u32 d16, s12 :: Dd 0x62400000 41d11660 Sm 0x44598189 +vcvt.f64.u32 d29, s7 :: Dd 0xe6c00000 41e8a3de Sm 0xc51ef736 +vcvt.f64.u32 d12, s28 :: Dd 0x11000000 41d02800 Sm 0x40a00044 +vcvt.f64.u32 d7, s5 :: Dd 0x00000000 41eff000 Sm 0xff800000 +vcvt.f64.u32 d21, s20 :: Dd 0x00000000 41dfe000 Sm 0x7f800000 +vcvt.f64.u32 d11, s11 :: Dd 0x00000000 41dff000 Sm 0x7fc00000 +vcvt.f64.s32 d0, s1 :: Dd 0x00000000 c0300000 Sm 0x404ccccd +vcvt.f64.s32 d30, s21 :: Dd 0x8f800000 c1cdedf2 Sm 0xc4241ae1 +vcvt.f64.s32 d16, s12 :: Dd 0x62400000 41d11660 Sm 0x44598189 +vcvt.f64.s32 d29, s7 :: Dd 0x65000000 c1cd7084 Sm 0xc51ef736 +vcvt.f64.s32 d12, s28 :: Dd 0x11000000 41d02800 Sm 0x40a00044 +vcvt.f64.s32 d7, s5 :: Dd 0x00000000 c1600000 Sm 0xff800000 +vcvt.f64.s32 d21, s20 :: Dd 0x00000000 41dfe000 Sm 0x7f800000 +vcvt.f64.s32 d11, s11 :: Dd 0x00000000 41dff000 Sm 0x7fc00000 +---- VCVT (single <-> double) ---- +vcvt.f64.f32 d0, s1 :: Dd 0xfffff555 0x40000000 Sm 0x404ccccd +vcvt.f64.f32 d29, s21 :: Dd 0x406d54cc 0xc0000000 Sm 0x436aa666 +vcvt.f64.f32 d16, s30 :: Dd 0xc085e50a 0x40000000 Sm 0xc42f2852 +vcvt.f64.f32 d11, s7 :: Dd 0x401fff00 0x00000000 Sm 0x40fff800 +vcvt.f64.f32 d30, s3 :: Dd 0xc01fff00 0x00000000 Sm 0xc0fff800 +vcvt.f64.f32 d7, s19 :: Dd 0x4028ddb6 0x20000000 Sm 0x4146edb1 +vcvt.f64.f32 d2, s11 :: Dd 0x40505b1a 0xa0000000 Sm 0x4282d8d5 +vcvt.f64.f32 d9, s21 :: Dd 0x7ff80000 0x00000000 Sm 0x7fc00000 +vcvt.f64.f32 d17, s29 :: Dd 0xfff00000 0x00000000 Sm 0xff800000 +vcvt.f64.f32 d19, s0 :: Dd 0x7ff00000 0x00000000 Sm 0x7f800000 +vcvt.f32.f64 s0, d1 :: Sd 0x404ccccd Dm 0x40099999 9999999a +vcvt.f32.f64 s29, d21 :: Sd 0x436aa666 Dm 0x406d54cc cccccccd +vcvt.f32.f64 s16, d30 :: Sd 0xc42f2852 Dm 0xc085e50a 3d70a3d7 +vcvt.f32.f64 s11, d7 :: Sd 0x40fff800 Dm 0x401fff00 00000000 +vcvt.f32.f64 s30, d3 :: Sd 0xc0fff800 Dm 0xc01fff00 00000000 +vcvt.f32.f64 s7, d19 :: Sd 0x4146edb1 Dm 0x4028ddb6 1bb05faf +vcvt.f32.f64 s2, d11 :: Sd 0x4282d8d5 Dm 0x40505b1a 9fbe76c9 +vcvt.f32.f64 s9, d21 :: Sd 0x7fc00000 Dm 0x7ff80000 00000000 +vcvt.f32.f64 s17, d29 :: Sd 0xff800000 Dm 0xfff00000 00000000 +vcvt.f32.f64 s19, d0 :: Sd 0x7f800000 Dm 0x7ff00000 00000000 +---- VCMP ---- +vcmp.f64 d0, d19 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 Dm 0xc004fef9 db22d0e5 +vcmp.f64 d11, d16 :: FPSCR 0x20000000 Dd 0x40d6ecdc cccccccd Dm 0x40aac300 00000000 +vcmp.f64 d21, d30 :: FPSCR 0x20000000 Dd 0xc0b1ac80 00000000 Dm 0xc11b9be6 00000000 +vcmp.f64 d7, d28 :: FPSCR 0x20000000 Dd 0x407a9800 00000000 Dm 0xc07c84cc cccccccd +vcmp.f64 d29, d3 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 Dm 0x40e0e04e 66666666 +vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40000000 00000000 Dm 0x40000000 00000000 +vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40280bc6 a7ef9db2 Dm 0x40280bc6 a7ef9db2 +vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x00000000 00000000 Dm 0x00000000 00000000 +vcmp.f64 d9, d2 :: FPSCR 0x60000000 Dd 0x7ff00000 00000000 Dm 0x7ff00000 00000000 +vcmp.f64 d30, d15 :: FPSCR 0x60000000 Dd 0xfff00000 00000000 Dm 0xfff00000 00000000 +vcmp.f64 d0, d19 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 Dm 0xc004fef9 db22d0e5 +vcmp.f64 d11, d16 :: FPSCR 0x20000000 Dd 0xc0b557b3 33333333 Dm 0xfff00000 00000000 +vcmp.f64 d21, d30 :: FPSCR 0x80000000 Dd 0xfff00000 00000000 Dm 0x4055accc cccccccd +vcmp.f64 d7, d28 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 Dm 0xc0c0bbba 5e353f7d +vcmp.f64 d29, d3 :: FPSCR 0x80000000 Dd 0xc0806333 33333333 Dm 0x40847400 00000000 +vcmp.f64 d3, d22 :: FPSCR 0x30000000 Dd 0x7ff80000 00000000 Dm 0xc019dc67 dfe32a06 +vcmp.f64 d9, d2 :: FPSCR 0x20000000 Dd 0x404c4810 624dd2f2 Dm 0x404c47ae 147ae148 +vcmp.f64 d30, d15 :: FPSCR 0x80000000 Dd 0x40b4f599 9a415f46 Dm 0x40ebb770 00000000 +vcmpe.f64 d0, d19 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 Dm 0xc004fef9 db22d0e5 +vcmpe.f64 d11, d16 :: FPSCR 0x20000000 Dd 0x40d6ecdc cccccccd Dm 0x40aac300 00000000 +vcmpe.f64 d11, d16 :: FPSCR 0x30000000 Dd 0x40d6ecdc cccccccd Dm 0x7ff80000 00000000 +vcmpe.f64 d21, d30 :: FPSCR 0x20000000 Dd 0xc0b1ac80 00000000 Dm 0xc11b9be6 00000000 +vcmpe.f64 d7, d28 :: FPSCR 0x20000000 Dd 0x407a9800 00000000 Dm 0xc07c84cc cccccccd +vcmpe.f64 d29, d3 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 Dm 0x40e0e04e 66666666 +vcmpe.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40000000 00000000 Dm 0x40000000 00000000 +vcmpe.f64 d9, d2 :: FPSCR 0x60000000 Dd 0x7ff00000 00000000 Dm 0x7ff00000 00000000 +vcmpe.f64 d30, d15 :: FPSCR 0x60000000 Dd 0xfff00000 00000000 Dm 0xfff00000 00000000 +vcmpe.f64 d0, d19 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 Dm 0xc004fef9 db22d0e5 +vcmpe.f64 d11, d16 :: FPSCR 0x20000000 Dd 0xc0b557b3 33333333 Dm 0xfff00000 00000000 +vcmpe.f64 d21, d30 :: FPSCR 0x80000000 Dd 0xfff00000 00000000 Dm 0x4055accc cccccccd +vcmpe.f64 d7, d28 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 Dm 0xc0c0bbba 5e353f7d +vcmpe.f64 d29, d3 :: FPSCR 0x80000000 Dd 0xc0806333 33333333 Dm 0x40847400 00000000 +vcmpe.f64 d3, d22 :: FPSCR 0x20000000 Dd 0x40b21080 00000000 Dm 0xc019dc67 dfe32a06 +vcmpe.f64 d9, d2 :: FPSCR 0x20000000 Dd 0x404c4810 624dd2f2 Dm 0x404c47ae 147ae148 +vcmpe.f64 d30, d15 :: FPSCR 0x80000000 Dd 0x40b4f599 9a415f46 Dm 0x40ebb770 00000000 +vcmp.f32 s0, s19 :: FPSCR 0x8 Sd 0xc05d3a93 Sm 0xc027f7cf +vcmp.f32 s11, s16 :: FPSCR 0x2 Sd 0x46b766e6 Sm 0x45561800 +vcmp.f32 s3, s22 :: FPSCR 0x6 Sd 0x40000000 Sm 0x40000000 +vcmp.f32 s0, s19 :: FPSCR 0x8 Sd 0xc05d3a93 Sm 0xc027f7cf +vcmp.f32 s11, s16 :: FPSCR 0x2 Sd 0x46b766e6 Sm 0x45561800 +vcmp.f32 s21, s30 :: FPSCR 0x2 Sd 0xc58d6400 Sm 0xc8dcdf30 +vcmp.f32 s7, s28 :: FPSCR 0x2 Sd 0x43d4c000 Sm 0xc3e42666 +vcmp.f32 s29, s3 :: FPSCR 0x2 Sd 0x7f800000 Sm 0x47070273 +vcmp.f32 s3, s22 :: FPSCR 0x6 Sd 0x41405e35 Sm 0x41405e35 +vcmp.f32 s3, s22 :: FPSCR 0x6 Sd 0x00000000 Sm 0x00000000 +vcmp.f32 s9, s2 :: FPSCR 0x6 Sd 0x7f800000 Sm 0x7f800000 +vcmp.f32 s30, s15 :: FPSCR 0x6 Sd 0xff800000 Sm 0xff800000 +vcmp.f32 s0, s19 :: FPSCR 0x8 Sd 0xc05d3a93 Sm 0xc027f7cf +vcmp.f32 s11, s16 :: FPSCR 0x2 Sd 0xc5aabd9a Sm 0xff800000 +vcmp.f32 s21, s30 :: FPSCR 0x8 Sd 0xff800000 Sm 0x42ad6666 +vcmp.f32 s7, s28 :: FPSCR 0x2 Sd 0x7f800000 Sm 0xc605ddd3 +vcmp.f32 s29, s3 :: FPSCR 0x8 Sd 0xc403199a Sm 0x4423a000 +vcmp.f32 s3, s22 :: FPSCR 0x3 Sd 0x7fc00000 Sm 0xc0cee33f +vcmp.f32 s9, s2 :: FPSCR 0x2 Sd 0x42624083 Sm 0x42623d71 +vcmp.f32 s30, s15 :: FPSCR 0x8 Sd 0x45a7accd Sm 0x475dbb80 +vcmpe.f32 s0, s19 :: FPSCR 0x8 Sd 0xc05d3a93 Sm 0xc027f7cf +vcmpe.f32 s11, s16 :: FPSCR 0x2 Sd 0x46b766e6 Sm 0x45561800 +vcmpe.f32 s11, s16 :: FPSCR 0x3 Sd 0x46b766e6 Sm 0x7fc00000 +vcmpe.f32 s21, s30 :: FPSCR 0x2 Sd 0xc58d6400 Sm 0xc8dcdf30 +vcmpe.f32 s7, s28 :: FPSCR 0x2 Sd 0x43d4c000 Sm 0xc3e42666 +vcmpe.f32 s29, s3 :: FPSCR 0x2 Sd 0x7f800000 Sm 0x47070273 +vcmpe.f32 s3, s22 :: FPSCR 0x6 Sd 0x40000000 Sm 0x40000000 +vcmpe.f32 s9, s2 :: FPSCR 0x6 Sd 0x7f800000 Sm 0x7f800000 +vcmpe.f32 s30, s15 :: FPSCR 0x6 Sd 0xff800000 Sm 0xff800000 +vcmpe.f32 s0, s19 :: FPSCR 0x8 Sd 0xc05d3a93 Sm 0xc027f7cf +vcmpe.f32 s11, s16 :: FPSCR 0x2 Sd 0xc5aabd9a Sm 0xff800000 +vcmpe.f32 s21, s30 :: FPSCR 0x8 Sd 0xff800000 Sm 0x42ad6666 +vcmpe.f32 s7, s28 :: FPSCR 0x2 Sd 0x7f800000 Sm 0xc605ddd3 +vcmpe.f32 s29, s3 :: FPSCR 0x8 Sd 0xc403199a Sm 0x4423a000 +vcmpe.f32 s3, s22 :: FPSCR 0x2 Sd 0x45908400 Sm 0xc0cee33f +vcmpe.f32 s9, s2 :: FPSCR 0x2 Sd 0x42624083 Sm 0x42623d71 +vcmpe.f32 s9, s2 :: FPSCR 0x8 Sd 0x00000000 Sm 0x42623d71 +vcmpe.f32 s9, s2 :: FPSCR 0x2 Sd 0x41200000 Sm 0x00000000 +vcmpe.f32 s9, s2 :: FPSCR 0x6 Sd 0x00000000 Sm 0x00000000 +vcmpe.f32 s9, s2 :: FPSCR 0x6 Sd 0x00000000 Sm 0x00000000 +---- VCMP (zero) ---- +vcmp.f64 d0 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 +vcmp.f64 d11 :: FPSCR 0x20000000 Dd 0x40d6ecdc cccccccd +vcmp.f64 d21 :: FPSCR 0x80000000 Dd 0xc0b1ac80 00000000 +vcmp.f64 d7 :: FPSCR 0x20000000 Dd 0x407a9800 00000000 +vcmp.f64 d29 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 +vcmp.f64 d3 :: FPSCR 0x20000000 Dd 0x40000000 00000000 +vcmp.f64 d3 :: FPSCR 0x60000000 Dd 0x00000000 00000000 +vcmp.f64 d9 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 +vcmp.f64 d30 :: FPSCR 0x80000000 Dd 0xfff00000 00000000 +vcmp.f64 d0 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 +vcmp.f64 d11 :: FPSCR 0x80000000 Dd 0xc0b557b3 33333333 +vcmp.f64 d21 :: FPSCR 0x80000000 Dd 0xfff00000 00000000 +vcmp.f64 d7 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 +vcmp.f64 d29 :: FPSCR 0x80000000 Dd 0xc0806333 33333333 +vcmp.f64 d3 :: FPSCR 0x20000000 Dd 0x40b21080 00000000 +vcmp.f64 d9 :: FPSCR 0x30000000 Dd 0x7ff80000 00000000 +vcmp.f64 d30 :: FPSCR 0x20000000 Dd 0x40b4f599 9a415f46 +vcmpe.f64 d0 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 +vcmpe.f64 d11 :: FPSCR 0x20000000 Dd 0x40d6ecdc cccccccd +vcmpe.f64 d21 :: FPSCR 0x80000000 Dd 0xc0b1ac80 00000000 +vcmpe.f64 d7 :: FPSCR 0x20000000 Dd 0x407a9800 00000000 +vcmpe.f64 d29 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 +vcmpe.f64 d3 :: FPSCR 0x20000000 Dd 0x40000000 00000000 +vcmpe.f64 d3 :: FPSCR 0x60000000 Dd 0x00000000 00000000 +vcmpe.f64 d9 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 +vcmpe.f64 d30 :: FPSCR 0x80000000 Dd 0xfff00000 00000000 +vcmpe.f64 d0 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 +vcmpe.f64 d11 :: FPSCR 0x80000000 Dd 0xc0b557b3 33333333 +vcmpe.f64 d21 :: FPSCR 0x80000000 Dd 0xfff00000 00000000 +vcmpe.f64 d7 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 +vcmpe.f64 d29 :: FPSCR 0x80000000 Dd 0xc0806333 33333333 +vcmpe.f64 d3 :: FPSCR 0x20000000 Dd 0x40b21080 00000000 +vcmpe.f64 d9 :: FPSCR 0x30000000 Dd 0x7ff80000 00000000 +vcmpe.f64 d30 :: FPSCR 0x20000000 Dd 0x40b4f599 9a415f46 +vcmp.f32 s0 :: FPSCR 0x80000000 Sd 0xc05d3a93 +vcmp.f32 s11 :: FPSCR 0x20000000 Sd 0x46b766e6 +vcmp.f32 s21 :: FPSCR 0x80000000 Sd 0xc58d6400 +vcmp.f32 s7 :: FPSCR 0x20000000 Sd 0x43d4c000 +vcmp.f32 s29 :: FPSCR 0x20000000 Sd 0x7f800000 +vcmp.f32 s3 :: FPSCR 0x20000000 Sd 0x40000000 +vcmp.f32 s3 :: FPSCR 0x60000000 Sd 0x00000000 +vcmp.f32 s9 :: FPSCR 0x20000000 Sd 0x7f800000 +vcmp.f32 s30 :: FPSCR 0x80000000 Sd 0xff800000 +vcmp.f32 s0 :: FPSCR 0x80000000 Sd 0xc05d3a93 +vcmp.f32 s11 :: FPSCR 0x80000000 Sd 0xc5aabd9a +vcmp.f32 s21 :: FPSCR 0x80000000 Sd 0xff800000 +vcmp.f32 s7 :: FPSCR 0x20000000 Sd 0x7f800000 +vcmp.f32 s29 :: FPSCR 0x80000000 Sd 0xc403199a +vcmp.f32 s3 :: FPSCR 0x20000000 Sd 0x45908400 +vcmp.f32 s9 :: FPSCR 0x30000000 Sd 0x7fc00000 +vcmp.f32 s30 :: FPSCR 0x20000000 Sd 0x45a7accd +vcmpe.f32 s0 :: FPSCR 0x80000000 Sd 0xc05d3a93 +vcmpe.f32 s11 :: FPSCR 0x20000000 Sd 0x46b766e6 +vcmpe.f32 s21 :: FPSCR 0x80000000 Sd 0xc58d6400 +vcmpe.f32 s7 :: FPSCR 0x20000000 Sd 0x43d4c000 +vcmpe.f32 s29 :: FPSCR 0x20000000 Sd 0x7f800000 +vcmpe.f32 s3 :: FPSCR 0x20000000 Sd 0x40000000 +vcmpe.f32 s3 :: FPSCR 0x60000000 Sd 0x00000000 +vcmpe.f32 s9 :: FPSCR 0x20000000 Sd 0x7f800000 +vcmpe.f32 s30 :: FPSCR 0x80000000 Sd 0xff800000 +vcmpe.f32 s0 :: FPSCR 0x80000000 Sd 0xc05d3a93 +vcmpe.f32 s11 :: FPSCR 0x80000000 Sd 0xc5aabd9a +vcmpe.f32 s21 :: FPSCR 0x80000000 Sd 0xff800000 +vcmpe.f32 s7 :: FPSCR 0x20000000 Sd 0x7f800000 +vcmpe.f32 s29 :: FPSCR 0x80000000 Sd 0xc403199a +vcmpe.f32 s3 :: FPSCR 0x20000000 Sd 0x45908400 +vcmpe.f32 s9 :: FPSCR 0x30000000 Sd 0x7fc00000 +vcmpe.f32 s30 :: FPSCR 0x20000000 Sd 0x45a7accd +---- VLDR ---- +vldr d9, [r6, #+4] :: Dd 0x0000011a 0x00000dd3 *(int*) (Rn + shift) 0x0dd3 +vldr d16, [r9, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1 +vldr d30, [r12] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 +vldr d22, [r9, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a +vldr d29, [r2, #-8] :: Dd 0x00000bb1 0x00000aa0 *(int*) (Rn + shift) 0x0aa0 +vldr d8, [r8, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a +vldr d11, [r12, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1 +vldr d18, [r3] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 +vldr d5, [r10, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a +vldr d17, [r10] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 +vldr d9, [r9, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1 +vldr d29, [r4, #-8] :: Dd 0x00000bb1 0x00000aa0 *(int*) (Rn + shift) 0x0aa0 +vldr d21, [r6, #+4] :: Dd 0x0000011a 0x00000dd3 *(int*) (Rn + shift) 0x0dd3 +vldr d8, [r4] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 +vldr d19, [r0, #-8] :: Dd 0x00000bb1 0x00000aa0 *(int*) (Rn + shift) 0x0aa0 +vldr d10, [r3, #+4] :: Dd 0x0000011a 0x00000dd3 *(int*) (Rn + shift) 0x0dd3 +vldr s10, [r3, #+4] :: Sd 0x00000dd3 *(int*) (Rn + shift) 0x0dd3 +vldr s9, [r6, #+4] :: Sd 0x00000dd3 *(int*) (Rn + shift) 0x0dd3 +vldr s16, [r9, #-4] :: Sd 0x00000bb1 *(int*) (Rn + shift) 0x0bb1 +vldr s30, [r12] :: Sd 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 +vldr s22, [r9, #+8] :: Sd 0x0000011a *(int*) (Rn + shift) 0x011a +vldr s29, [r2, #-8] :: Sd 0x00000aa0 *(int*) (Rn + shift) 0x0aa0 +vldr s8, [r8, #+8] :: Sd 0x0000011a *(int*) (Rn + shift) 0x011a +vldr s11, [r12, #-4] :: Sd 0x00000bb1 *(int*) (Rn + shift) 0x0bb1 +vldr s18, [r3] :: Sd 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 +vldr s5, [r10, #+8] :: Sd 0x0000011a *(int*) (Rn + shift) 0x011a +vldr s17, [r10] :: Sd 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 +vldr s9, [r9, #-4] :: Sd 0x00000bb1 *(int*) (Rn + shift) 0x0bb1 +vldr s29, [r4, #-8] :: Sd 0x00000aa0 *(int*) (Rn + shift) 0x0aa0 +vldr s21, [r6, #+4] :: Sd 0x00000dd3 *(int*) (Rn + shift) 0x0dd3 +vldr s8, [r4] :: Sd 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 +vldr s19, [r0, #-8] :: Sd 0x00000aa0 *(int*) (Rn + shift) 0x0aa0 +vldr s10, [r3, #+4] :: Sd 0x00000dd3 *(int*) (Rn + shift) 0x0dd3 +---- VLDM (Increment After, writeback) ---- +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 +---- VSTR ---- +vstr d9, [r6, #+4] :: Dd 0xa0a0a0a0 0xa0a0a0a0 *(int*) (Rm + shift) 0xa0a0a0a0 +vstr d16, [r9, #-4] :: Dd 0xb1b1b1b1 0xb1b1b1b1 *(int*) (Rm + shift) 0xb1b1b1b1 +vstr d30, [r12] :: Dd 0xc2c2c2c2 0xc2c2c2c2 *(int*) (Rm + shift) 0xc2c2c2c2 +vstr d22, [r9, #+8] :: Dd 0xd4d4d4d4 0xd4d4d4d4 *(int*) (Rm + shift) 0xd4d4d4d4 +vstr d29, [r2, #-8] :: Dd 0x00000000 0x00000000 *(int*) (Rm + shift) 0x0000 +vstr d8, [r8, #+8] :: Dd 0x11111111 0x11111111 *(int*) (Rm + shift) 0x11111111 +vstr d11, [r12, #-4] :: Dd 0x22222222 0x22222222 *(int*) (Rm + shift) 0x22222222 +vstr d18, [r3] :: Dd 0x33333333 0x33333333 *(int*) (Rm + shift) 0x33333333 +vstr d5, [r10, #+8] :: Dd 0x99999999 0x99999999 *(int*) (Rm + shift) 0x99999999 +vstr d17, [r10] :: Dd 0x77777777 0x77777777 *(int*) (Rm + shift) 0x77777777 +vstr d9, [r9, #-4] :: Dd 0xeeeeeeee 0xeeeeeeee *(int*) (Rm + shift) 0xeeeeeeee +vstr d29, [r4, #-8] :: Dd 0xffffffff 0xffffffff *(int*) (Rm + shift) 0xffffffff +vstr d10, [r3, #+4] :: Dd 0xbcbcbcbc 0xbcbcbcbc *(int*) (Rm + shift) 0xbcbcbcbc +vstr d21, [r6, #+4] :: Dd 0x48484848 0x48484848 *(int*) (Rm + shift) 0x48484848 +vstr d8, [r4] :: Dd 0x1f1f1f1f 0x1f1f1f1f *(int*) (Rm + shift) 0x1f1f1f1f +vstr d19, [r0, #-8] :: Dd 0xf9f9f9f9 0xf9f9f9f9 *(int*) (Rm + shift) 0xf9f9f9f9 +vstr s9, [r6, #+4] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s21, [r9, #-4] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s4, [r3, #+8] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s19, [r4, #-8] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s29, [r8] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s8, [r12] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s16, [r0, #+4] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s0, [r8, #-4] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s3, [r9, #+8] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s9, [r10, #-8] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s11, [r2] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +vstr s30, [r0] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000 +---- VSTM (Increment After, no writeback) ---- +vstmia r6, {d21} :: Result 0xabababab 0xabababab +vstmia r1, {d1} :: Result 0x13131313 0x13131313 +vstmia r9, {d2} :: Result 0x78787878 0x78787878 +vstmia r4, {d30} :: Result 0x00000000 0x00000000 +vstmia r12, {d23} :: Result 0xb9b9b9b9 0xb9b9b9b9 +vstmia r6, {d16} :: Result 0xa6a6a6a6 0xa6a6a6a6 +vstmia r6, {d8} :: Result 0x7f7f7f7f 0x7f7f7f7f +vstmia r6, {d27} :: Result 0xffffffff 0xffffffff +vstmia r5, {d11} :: Result 0x32323232 0x32323232 +vstmia r6, {d4} :: Result 0x10101010 0x10101010 +vstmia r10, {d9} :: Result 0x4f4f4f4f 0x4f4f4f4f +vstmia r9, {d29} :: Result 0x97979797 0x97979797 +vstmia r10, {d17} :: Result 0xaaaaaaaa 0xaaaaaaaa +vstmia r5, {d5} :: Result 0x2b2b2b2b 0x2b2b2b2b +vstmia r9, {d7} :: Result 0x7b7b7b7b 0x7b7b7b7b +vstmia r3, {d16} :: Result 0x11111111 0x11111111 +vstmia r6, {s21} :: Result 0x000000ab +vstmia r1, {s1} :: Result 0x00000013 +vstmia r9, {s2} :: Result 0x00000078 +vstmia r4, {s30} :: Result 0x00000000 +vstmia r12, {s23} :: Result 0x000000b9 +vstmia r6, {s16} :: Result 0xa613451d +vstmia r6, {s8} :: Result 0x0000007f +vstmia r6, {s27} :: Result 0xff800000 +vstmia r5, {s11} :: Result 0x7fc00000 +vstmia r6, {s4} :: Result 0x00010ccb +vstmia r10, {s9} :: Result 0x0004f543 +vstmia r9, {s29} :: Result 0x0097001a +vstmia r10, {s17} :: Result 0x000aa45f +vstmia r5, {s5} :: Result 0x7fc00000 +vstmia r9, {s7} :: Result 0xff800000 +vstmia r3, {s16} :: Result 0x7f800000 +---- VSTM (Increment After, writeback) ---- +vstmia r6!, d21; vstmia r6!, d2 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r1!, d1; vstmia r1!, d5 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r9!, d2; vstmia r9!, d17 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r4!, d30; vstmia r4!, d21 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r12!, d23; vstmia r12!, d29 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r6!, d16; vstmia r6!, d30 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r6!, d8; vstmia r6!, d12 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r6!, d27; vstmia r6!, d24 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r5!, d11; vstmia r5!, d13 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r6!, d4; vstmia r6!, d31 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r10!, d9; vstmia r10!, d27 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r9!, d29; vstmia r9!, d17 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r10!, d17; vstmia r10!, d7 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r5!, d5; vstmia r5!, d8 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r9!, d7; vstmia r9!, d16 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r3!, d16; vstmia r3!, d21 :: Result 0xa0a0a0a0 0xa0a0a0a0 0xb1b1b1b1 0xb1b1b1b1 +vstmia r6!, s21; vstmia r6!, s2 :: Result 0xbff80000 0x3fa80000 +vstmia r12!, s23; vstmia r12!, s21 :: Result 0xbff80000 0x3fa80000 +vstmia r3!, s3; vstmia r3!, s3 :: Result 0x3fa80000 0x3fa80000 +vstmia r10!, s19; vstmia r10!, s5 :: Result 0xbff80000 0x3fa80000 +vstmia r2!, s3; vstmia r2!, s12 :: Result 0xbff80000 0x3fa80000 +vstmia r8!, s7; vstmia r8!, s10 :: Result 0xbff80000 0x3fa80000 +vstmia r4!, s30; vstmia r4!, s13 :: Result 0xbff80000 0x3fa80000 +vstmia r6!, s17; vstmia r6!, s17 :: Result 0x3fa80000 0x3fa80000 +vstmia r9!, s11; vstmia r9!, s21 :: Result 0xbff80000 0x3fa80000 +vstmia r9!, s8; vstmia r9!, s30 :: Result 0xbff80000 0x3fa80000 +vstmia r3!, s12; vstmia r3!, s9 :: Result 0xbff80000 0x3fa80000 +vstmia r6!, s6; vstmia r6!, s11 :: Result 0xbff80000 0x3fa80000 +vstmia r8!, s17; vstmia r8!, s12 :: Result 0xbff80000 0x3fa80000 +vstmia r9!, s12; vstmia r9!, s12 :: Result 0x3fa80000 0x3fa80000 +vstmia r4!, s11; vstmia r4!, s11 :: Result 0x3fa80000 0x3fa80000 +---- VLDM (Decrement Before) ---- +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x00000cc2 0x00000dd3 0x00000aa0 0x00000bb1 +----- VMOV (immediate) ----- +vmov s0, #0xbe880000 :: Sd 0xbe880000 +vmov s1, #0x3fa80000 :: Sd 0x3fa80000 +vmov s2, #0xbf080000 :: Sd 0xbf080000 +vmov s5, #0x3eb80000 :: Sd 0x3eb80000 +vmov s7, #0xbff80000 :: Sd 0xbff80000 +vmov s10, #0xbe280000 :: Sd 0xbe280000 +vmov s12, #0x40000000 :: Sd 0x40000000 +vmov s13, #0x3e880000 :: Sd 0x3e880000 +vmov s14, #0xbee80000 :: Sd 0xbee80000 +vmov s15, #0xc0b80000 :: Sd 0xc0b80000 +----- VMOV (ARM core register and single register) ----- +s12 0x04000aad vmov r12, s12 :: r12 0x04000aad +s5 0x00ab45e7 vmov r2, s5 :: r2 0x00ab45e7 +s15 0x000add12 vmov r5, s15 :: r5 0x000add12 +s11 0x876450ff vmov r8, s11 :: r8 0x876450ff +s5 0x0000ffff vmov r9, s5 :: r9 0x0000ffff +s9 0x0087d34f vmov r10, s9 :: r10 0x0087d34f +s10 0x0000ffff vmov r9, s10 :: r9 0x0000ffff +s8 0x000ad4f8 vmov r6, s8 :: r6 0x000ad4f8 +s14 0x0920b8cf vmov r4, s14 :: r4 0x0920b8cf +s7 0x7fc00000 vmov r3, s7 :: r3 0x7fc00000 +s0 0xff800000 vmov r2, s0 :: r2 0xff800000 +s1 0x7f800000 vmov r0, s1 :: r0 0x7f800000 +r9 0x0009465a vmov s2, r9 :: s2 0x0009465a +r0 0x00d0b87a vmov s14, r0 :: s14 0x00d0b87a +r2 0x0452bbc8 vmov s4, r2 :: s4 0x0452bbc8 +r8 0x00a7cb3d vmov s7, r8 :: s7 0x00a7cb3d +r4 0x000dd8ec vmov s9, r4 :: s9 0x000dd8ec +r12 0x008a7b6e vmov s10, r12 :: s10 0x008a7b6e +r9 0x0004b00a vmov s13, r9 :: s13 0x0004b00a +r3 0x00023455 vmov s3, r3 :: s3 0x00023455 +r5 0x7f800000 vmov s5, r5 :: s5 0x7f800000 +r6 0xff800000 vmov s8, r6 :: s8 0xff800000 +r0 0x000acb45 vmov s4, r0 :: s4 0x000acb45 +r6 0x7fc00000 vmov s0, r6 :: s0 0x7fc00000 +----- VMOV (ARM two core registers and two single registers) ----- + r6 0x43252acc r9 0x000abcc4 +vmov s0, s1, r6, r9 :: s0 0x43252acc s1 0x000abcc4 + r9 0x43252acc r9 0x000abcc4 +vmov s0, s1, r9, r9 :: s0 0x000abcc4 s1 0x000abcc4 + r9 0xaa2e2acc r1 0x00000337 +vmov s30, s31, r9, r1 :: s30 0xaa2e2acc s31 0x00000337 + r10 0x7fc00000 r9 0x7fc00000 +vmov s20, s21, r10, r9 :: s20 0x7fc00000 s21 0x7fc00000 + r10 0x7fc00000 r9 0x7f800000 +vmov s20, s21, r10, r9 :: s20 0x7fc00000 s21 0x7f800000 + r10 0x7fc00000 r9 0xff800000 +vmov s20, s21, r10, r9 :: s20 0x7fc00000 s21 0xff800000 + r10 0x7fc00000 r9 0x00000000 +vmov s20, s21, r10, r9 :: s20 0x7fc00000 s21 0x00000000 + r10 0x7f800000 r9 0x7fc00000 +vmov s20, s21, r10, r9 :: s20 0x7f800000 s21 0x7fc00000 + r10 0x7f800000 r9 0x7f800000 +vmov s20, s21, r10, r9 :: s20 0x7f800000 s21 0x7f800000 + r10 0x7f800000 r9 0xff800000 +vmov s20, s21, r10, r9 :: s20 0x7f800000 s21 0xff800000 + r10 0x7f800000 r9 0x00000000 +vmov s20, s21, r10, r9 :: s20 0x7f800000 s21 0x00000000 + r10 0xff800000 r9 0x7fc00000 +vmov s20, s21, r10, r9 :: s20 0xff800000 s21 0x7fc00000 + r10 0xff800000 r9 0x7f800000 +vmov s20, s21, r10, r9 :: s20 0xff800000 s21 0x7f800000 + r10 0xff800000 r9 0xff800000 +vmov s20, s21, r10, r9 :: s20 0xff800000 s21 0xff800000 + r10 0xff800000 r9 0x00000000 +vmov s20, s21, r10, r9 :: s20 0xff800000 s21 0x00000000 + r10 0x00000000 r9 0x7fc00000 +vmov s20, s21, r10, r9 :: s20 0x00000000 s21 0x7fc00000 + r10 0x00000000 r9 0x7f800000 +vmov s20, s21, r10, r9 :: s20 0x00000000 s21 0x7f800000 + r10 0x00000000 r9 0xff800000 +vmov s20, s21, r10, r9 :: s20 0x00000000 s21 0xff800000 + r10 0x00000000 r9 0x00000000 +vmov s20, s21, r10, r9 :: s20 0x00000000 s21 0x00000000 + r10 0x7fc00001 r9 0x7fc00000 +vmov s20, s21, r10, r9 :: s20 0x7fc00001 s21 0x7fc00000 + r10 0x7fc00001 r9 0x00000000 +vmov s20, s21, r10, r9 :: s20 0x7fc00001 s21 0x00000000 + r10 0x7fc00000 r9 0x7fbfffff +vmov s20, s21, r10, r9 :: s20 0x7fc00000 s21 0x7fbfffff + r10 0x00000000 r9 0x7fbfffff +vmov s20, s21, r10, r9 :: s20 0x00000000 s21 0x7fbfffff + s12 0x04000aad s13 0x000affff +vmov r12, r9, s12, s13 :: r12 0x04000aad r9 0x000affff + s12 0x040ee56d s13 0x000123ff +vmov r0, r9, s12, s13 :: r0 0x040ee56d r9 0x000123ff + s12 0x04000aad s13 0x000affff +vmov r12, r9, s12, s13 :: r12 0x04000aad r9 0x000affff + s20 0x7fc00000 s21 0x7fc00000 +vmov r10, r9, s20, s21 :: r10 0x7fc00000 r9 0x7fc00000 + s20 0x7fc00000 s21 0x7f800000 +vmov r10, r9, s20, s21 :: r10 0x7fc00000 r9 0x7f800000 + s20 0x7fc00000 s21 0xff800000 +vmov r10, r9, s20, s21 :: r10 0x7fc00000 r9 0xff800000 + s20 0x7fc00000 s21 0x00000000 +vmov r10, r9, s20, s21 :: r10 0x7fc00000 r9 0x00000000 + s20 0x7f800000 s21 0x7fc00000 +vmov r10, r9, s20, s21 :: r10 0x7f800000 r9 0x7fc00000 + s20 0x7f800000 s21 0x7f800000 +vmov r10, r9, s20, s21 :: r10 0x7f800000 r9 0x7f800000 + s20 0x7f800000 s21 0xff800000 +vmov r10, r9, s20, s21 :: r10 0x7f800000 r9 0xff800000 + s20 0x7f800000 s21 0x00000000 +vmov r10, r9, s20, s21 :: r10 0x7f800000 r9 0x00000000 + s20 0xff800000 s21 0x7fc00000 +vmov r10, r9, s20, s21 :: r10 0xff800000 r9 0x7fc00000 + s20 0xff800000 s21 0x7f800000 +vmov r10, r9, s20, s21 :: r10 0xff800000 r9 0x7f800000 + s20 0xff800000 s21 0xff800000 +vmov r10, r9, s20, s21 :: r10 0xff800000 r9 0xff800000 + s20 0xff800000 s21 0x00000000 +vmov r10, r9, s20, s21 :: r10 0xff800000 r9 0x00000000 + s20 0x00000000 s21 0x7fc00000 +vmov r10, r9, s20, s21 :: r10 0x00000000 r9 0x7fc00000 + s20 0x00000000 s21 0x7f800000 +vmov r10, r9, s20, s21 :: r10 0x00000000 r9 0x7f800000 + s20 0x00000000 s21 0xff800000 +vmov r10, r9, s20, s21 :: r10 0x00000000 r9 0xff800000 + s20 0x00000000 s21 0x00000000 +vmov r10, r9, s20, s21 :: r10 0x00000000 r9 0x00000000 + s20 0x7fc00001 s21 0x7fc00000 +vmov r10, r9, s20, s21 :: r10 0x7fc00001 r9 0x7fc00000 + s20 0x7fc00001 s21 0x00000000 +vmov r10, r9, s20, s21 :: r10 0x7fc00001 r9 0x00000000 + s20 0x7fc00000 s21 0x7fbfffff +vmov r10, r9, s20, s21 :: r10 0x7fc00000 r9 0x7fbfffff + s20 0x00000000 s21 0x7fbfffff +vmov r10, r9, s20, s21 :: r10 0x00000000 r9 0x7fbfffff +----- VMOV (ARM two core registers and double register) ----- +r6 0x43252acc r9 0x00045bbd vmov d3, r6, r9 :: d3 0x43252acc 0x00045bbd +r10 0x001243b4 r2 0x00237ffb vmov d4, r10, r2 :: d4 0x001243b4 0x00237ffb +r1 0x00030cc4 r6 0x0314c043 vmov d21, r1, r6 :: d21 0x00030cc4 0x0314c043 +r9 0x00008ddf r9 0x0087bbca vmov d30, r9, r9 :: d30 0x0087bbca 0x0087bbca +r3 0x0000aaa0 r5 0x0000bbb1 vmov d29, r3, r5 :: d29 0x0000aaa0 0x0000bbb1 +r8 0x0aa455bb r8 0x00013434 vmov d16, r8, r8 :: d16 0x00013434 0x00013434 +r12 0x00004003 r9 0x0452bbc1 vmov d17, r12, r9 :: d17 0x00004003 0x0452bbc1 +r9 0x0000134c r0 0x0041ffb6 vmov d9, r9, r0 :: d9 0x0000134c 0x0041ffb6 +r0 0x35425dcc r6 0x00876c43 vmov d7, r0, r6 :: d7 0x35425dcc 0x00876c43 +r3 0x00000000 r9 0x7ff80000 vmov d13, r3, r9 :: d13 0x00000000 0x7ff80000 +r6 0x00000000 r5 0x7ff00000 vmov d19, r6, r5 :: d19 0x00000000 0x7ff00000 +r2 0x00000000 r6 0xfff00000 vmov d0, r2, r6 :: d0 0x00000000 0xfff00000 +d9 0x43252acc 0x00045bbd vmov r3, r6, d9 :: r3 0x43252acc r6 0x00045bbd +d2 0x001243b4 0x00237ffb vmov r4, r10, d2 :: r4 0x001243b4 r10 0x00237ffb +d6 0x00030cc4 0x0314c043 vmov r2, r1, d6 :: r2 0x00030cc4 r1 0x0314c043 +d11 0x00008ddf 0x0087bbca vmov r0, r9, d11 :: r0 0x00008ddf r9 0x0087bbca +d5 0x0000aaa0 0x0000bbb1 vmov r9, r3, d5 :: r9 0x0000aaa0 r3 0x0000bbb1 +d8 0x0aa455bb 0x00013434 vmov r10, r8, d8 :: r10 0x0aa455bb r8 0x00013434 +d11 0x00004003 0x0452bbc1 vmov r9, r12, d11 :: r9 0x00004003 r12 0x0452bbc1 +d7 0x35425dcc 0x00876c43 vmov r6, r0, d7 :: r6 0x35425dcc r0 0x00876c43 +d11 0x00000000 0x7ff80000 vmov r12, r3, d11 :: r12 0x00000000 r3 0x7ff80000 +d5 0x00000000 0x7ff00000 vmov r1, r6, d5 :: r1 0x00000000 r6 0x7ff00000 +d7 0x00000000 0xfff00000 vmov r0, r2, d7 :: r0 0x00000000 r2 0xfff00000 +d0 0x00000000 0x7ff00000 vmov r2, r9, d0 :: r2 0x00000000 r9 0x7ff00000 +d10 0x0014534c 0x0041ffb6 vmov r6, r9, d10 :: r6 0x0014534c r9 0x0041ffb6 +d20 0x00000000 0x7ff80000 vmov r0, r9, d20 :: r0 0x00000000 r9 0x7ff80000 +----- VPUSH, VPOP ----- +s3 0x00aaaaaa s4 0x00bbbbbb s5 0x00cccccc s0 0x00cccccc s1 0x00aaaaaa s2 0x00bbbbbb +s1 0x000134f4 s2 0x0870ccb3 s3 0x00aba0f1 s9 0x00aba0f1 s10 0x000134f4 s11 0x0870ccb3 +s3 0x00dddddd s4 0x00eeeeee s5 0x00ffffff s0 0x00ffffff s1 0x00dddddd s2 0x00eeeeee +s11 0x0013454c s12 0x00000341 s13 0x00aac45f s6 0x00aac45f s7 0x0013454c s8 0x00000341 +s21 0x00000000 s22 0x7fc00000 s23 0x7f800000 s23 0x7f800000 s24 0x00000000 s25 0x7fc00000 +s12 0x00ffffff s13 0x0f542dd4 s14 0xff800000 s11 0xff800000 s12 0x00ffffff s13 0x0f542dd4 +s25 0x000045cd s26 0x00a3ccb5 s27 0x000bbcaf s0 0x000bbcaf s1 0x000045cd s2 0x00a3ccb5 +s1 0x7fc00000 s2 0x000aaca3 s3 0x00876008 s6 0x00876008 s7 0x7fc00000 s8 0x000aaca3 +s9 0x003cc66a s10 0x00002f43 s11 0x7f800000 s9 0x003cc66a s10 0x00002f43 s11 0x7f800000 +s10 0x7f800000 s11 0x00134cc5 s12 0x7fc00000 s2 0x7fc00000 s3 0x7f800000 s4 0x00134cc5 +s7 0x00cc006d s8 0x0001308c s9 0x00abbc45 s21 0x00abbc45 s22 0x00cc006d s23 0x0001308c +s19 0xff800000 s20 0x00452146 s21 0x00388bbc s4 0x00388bbc s5 0xff800000 s6 0x00452146 +s16 0x000542aa s17 0x00addcd5 s18 0x00087acc s18 0x00087acc s19 0x000542aa s20 0x00addcd5 +s22 0x05ccb708 s23 0x0052345c s24 0x0098745c s12 0x0098745c s13 0x05ccb708 s14 0x0052345c +s24 0x0099234f s25 0x00001aac s26 0x0003746c s28 0x0003746c s29 0x0099234f s30 0x00001aac +s13 0x00134ccc s14 0x0006bb43 s15 0x000834aa s0 0x000834aa s1 0x00134ccc s2 0x0006bb43 +d3 0x00aaaaaa 0000aac3 d4 0x00bbbbbb 00034ccb d0 0x00aaaaaa 0000aac3 d1 0x00bbbbbb 00034ccb +d1 0x000134f4 00341531 d2 0x0870ccb3 04576bbc d9 0x000134f4 00341531 d10 0x0870ccb3 04576bbc +d3 0x00dddddd 013451cc d4 0x00eeeeee 0123ddc8 d0 0x00dddddd 013451cc d1 0x00eeeeee 0123ddc8 +d11 0x0013454c 0541bbc3 d12 0x00000341 0000ccb5 d6 0x0013454c 0541bbc3 d7 0x00000341 0000ccb5 +d21 0x00000000 00123c33 d22 0x00000000 7ff80000 d23 0x00000000 00123c33 d24 0x00000000 7ff80000 +d12 0x0f542dd4 00788ffc d13 0x0f542dd4 00788ffc d11 0x00ffffff 0001940c d12 0x0f542dd4 00788ffc +d25 0x000045cd 0001309c d26 0x00a3ccb5 0004588b d0 0x000045cd 0001309c d1 0x00a3ccb5 0004588b +d1 0x00000000 7ff80000 d2 0x000aaca3 0001120a d6 0x00000000 7ff80000 d7 0x000aaca3 0001120a +d9 0x00002f43 00019ff9 d10 0x00000000 7ff00000 d9 0x00002f43 00019ff9 d10 0x00000000 7ff00000 +d10 0x00000000 7ff00000 d11 0x00134cc5 0078cbbd d2 0x00000000 7ff00000 d3 0x00134cc5 0078cbbd +d7 0x00cc006d 00028354 d8 0x0001308c 001993bc d21 0x00cc006d 00028354 d22 0x0001308c 001993bc +d19 0x00000000 fff00000 d20 0x00452146 0138476c d4 0x00000000 fff00000 d5 0x00452146 0138476c +d16 0x000542aa 00012dd4 d17 0x00addcd5 000399cb d18 0x000542aa 00012dd4 d19 0x00addcd5 000399cb +d22 0x05ccb708 0008009c d23 0x0052345c 0029902c d12 0x05ccb708 0008009c d13 0x0052345c 0029902c +d24 0x0099234f 003457ff d25 0x00001aac 01002cba d28 0x0099234f 003457ff d29 0x00001aac 01002cba +d13 0x00134ccc 00faa309 d14 0x0006bb43 000199cb d0 0x00134ccc 00faa309 d1 0x0006bb43 000199cb diff --git a/none/tests/arm/vfp.vgtest b/none/tests/arm/vfp.vgtest new file mode 100644 index 0000000..fd3e759 --- /dev/null +++ b/none/tests/arm/vfp.vgtest @@ -0,0 +1,2 @@ +prog: vfp +vgopts: -q diff --git a/none/tests/cmdline1.stdout.exp b/none/tests/cmdline1.stdout.exp index 0fab2a2..9c6d5fe 100644 --- a/none/tests/cmdline1.stdout.exp +++ b/none/tests/cmdline1.stdout.exp @@ -10,6 +10,8 @@ usage: valgrind [options] prog-and-args -q --quiet run silently; only print error msgs -v --verbose be more verbose -- show misc extra info --trace-children=no|yes Valgrind-ise child processes (follow execve)? [no] + --trace-children-skip=patt1,patt2,... specifies a list of executables + that --trace-children=yes should not trace into --child-silent-after-fork=no|yes omit child output between fork & exec? [no] --track-fds=no|yes track open file descriptors? [no] --time-stamp=no|yes add timestamps to log messages? [no] @@ -31,7 +33,7 @@ usage: valgrind [options] prog-and-args --suppressions= suppress errors described in --gen-suppressions=no|yes|all print suppressions for errors? [no] --db-attach=no|yes start debugger when errors detected? [no] - --db-command= command to start debugger [/usr/bin/gdb -nw %f %p] + --db-command= command to start debugger [... -nw %f %p] --input-fd= file descriptor for input [0=stdin] --dsymutil=no|yes run dsymutil on Mac OS X when helpful? [no] --max-stackframe= assume stack switch for SP changes larger @@ -43,27 +45,36 @@ usage: valgrind [options] prog-and-args --alignment= set minimum alignment of heap allocations [...] uncommon user options for all Valgrind tools: + --fullpath-after= (with nothing after the '=') + show full source paths in call stacks + --fullpath-after=string like --fullpath-after=, but only show the + part of the path after 'string'. Allows removal + of path prefixes. Use this flag multiple times + to specify a set of prefixes to remove. --smc-check=none|stack|all checks for self-modifying code: none, only for code found in stacks, or all [stack] --read-var-info=yes|no read debug info on stack and global variables and use it to print better error messages in tools that make use of it (Memcheck, Helgrind, - DRD) + DRD) [no] --run-libc-freeres=no|yes free up glibc memory at exit on Linux? [yes] --sim-hints=hint1,hint2,... known hints: lax-ioctls, enable-outer [none] --kernel-variant=variant1,variant2,... known variants: bproc [none] handle non-standard kernel variants --show-emwarns=no|yes show warnings about emulation limits? [no] + --require-text-symbol=:sonamepattern:symbolpattern abort run if the + stated shared object doesn't have the stated + text symbol. Patterns can contain ? and *. user options for Nulgrind: (none) Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc - Nulgrind is Copyright (C) 2002-2009, and GNU GPL'd, by Nicholas Nethercote. - Valgrind is Copyright (C) 2000-2009, and GNU GPL'd, by Julian Seward et al. - LibVEX is Copyright (C) 2004-2009, and GNU GPL'd, by OpenWorks LLP. + Nulgrind is Copyright (C) 2002-2010, and GNU GPL'd, by Nicholas Nethercote. + Valgrind is Copyright (C) 2000-2010, and GNU GPL'd, by Julian Seward et al. + LibVEX is Copyright (C) 2004-2010, and GNU GPL'd, by OpenWorks LLP et al. Bug reports, feedback, admiration, abuse, etc, to: www.valgrind.org. diff --git a/none/tests/cmdline2.stdout.exp b/none/tests/cmdline2.stdout.exp index cb7e515..d27316f 100644 --- a/none/tests/cmdline2.stdout.exp +++ b/none/tests/cmdline2.stdout.exp @@ -10,6 +10,8 @@ usage: valgrind [options] prog-and-args -q --quiet run silently; only print error msgs -v --verbose be more verbose -- show misc extra info --trace-children=no|yes Valgrind-ise child processes (follow execve)? [no] + --trace-children-skip=patt1,patt2,... specifies a list of executables + that --trace-children=yes should not trace into --child-silent-after-fork=no|yes omit child output between fork & exec? [no] --track-fds=no|yes track open file descriptors? [no] --time-stamp=no|yes add timestamps to log messages? [no] @@ -31,7 +33,7 @@ usage: valgrind [options] prog-and-args --suppressions= suppress errors described in --gen-suppressions=no|yes|all print suppressions for errors? [no] --db-attach=no|yes start debugger when errors detected? [no] - --db-command= command to start debugger [/usr/bin/gdb -nw %f %p] + --db-command= command to start debugger [... -nw %f %p] --input-fd= file descriptor for input [0=stdin] --dsymutil=no|yes run dsymutil on Mac OS X when helpful? [no] --max-stackframe= assume stack switch for SP changes larger @@ -43,25 +45,34 @@ usage: valgrind [options] prog-and-args --alignment= set minimum alignment of heap allocations [...] uncommon user options for all Valgrind tools: + --fullpath-after= (with nothing after the '=') + show full source paths in call stacks + --fullpath-after=string like --fullpath-after=, but only show the + part of the path after 'string'. Allows removal + of path prefixes. Use this flag multiple times + to specify a set of prefixes to remove. --smc-check=none|stack|all checks for self-modifying code: none, only for code found in stacks, or all [stack] --read-var-info=yes|no read debug info on stack and global variables and use it to print better error messages in tools that make use of it (Memcheck, Helgrind, - DRD) + DRD) [no] --run-libc-freeres=no|yes free up glibc memory at exit on Linux? [yes] --sim-hints=hint1,hint2,... known hints: lax-ioctls, enable-outer [none] --kernel-variant=variant1,variant2,... known variants: bproc [none] handle non-standard kernel variants --show-emwarns=no|yes show warnings about emulation limits? [no] + --require-text-symbol=:sonamepattern:symbolpattern abort run if the + stated shared object doesn't have the stated + text symbol. Patterns can contain ? and *. user options for Nulgrind: (none) debugging options for all Valgrind tools: - --stats=no|yes show tool and core statistics [no] -d show verbose debugging output + --stats=no|yes show tool and core statistics [no] --sanity-level= level of sanity checking to do [1] --trace-flags= show generated code? (X = 0|1) [00000000] --profile-flags= ditto, but for profiling (X = 0|1) [00000000] @@ -88,6 +99,7 @@ usage: valgrind [options] prog-and-args --vex-iropt-unroll-thresh=<0..400> [120] --vex-guest-max-insns=<1..100> [50] --vex-guest-chase-thresh=<0..99> [10] + --vex-guest-chase-cond=no|yes [no] --trace-flags and --profile-flags values (omit the middle space): 1000 0000 show conversion into IR 0100 0000 show after initial opt @@ -111,9 +123,9 @@ usage: valgrind [options] prog-and-args Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc - Nulgrind is Copyright (C) 2002-2009, and GNU GPL'd, by Nicholas Nethercote. - Valgrind is Copyright (C) 2000-2009, and GNU GPL'd, by Julian Seward et al. - LibVEX is Copyright (C) 2004-2009, and GNU GPL'd, by OpenWorks LLP. + Nulgrind is Copyright (C) 2002-2010, and GNU GPL'd, by Nicholas Nethercote. + Valgrind is Copyright (C) 2000-2010, and GNU GPL'd, by Julian Seward et al. + LibVEX is Copyright (C) 2004-2010, and GNU GPL'd, by OpenWorks LLP et al. Bug reports, feedback, admiration, abuse, etc, to: www.valgrind.org. diff --git a/none/tests/cmdline4.stderr.exp b/none/tests/cmdline4.stderr.exp index 1f88235..f9b9ba6 100644 --- a/none/tests/cmdline4.stderr.exp +++ b/none/tests/cmdline4.stderr.exp @@ -1,2 +1,2 @@ -valgrind: Bad option '--bad-bad-option'; aborting. -valgrind: Use --help for more information. +valgrind: Bad option: --bad-bad-option +valgrind: Use --help for more information or consult the user manual. diff --git a/none/tests/faultstatus.c b/none/tests/faultstatus.c index 8769565..af0f892 100644 --- a/none/tests/faultstatus.c +++ b/none/tests/faultstatus.c @@ -9,16 +9,24 @@ #include "tests/sys_mman.h" #include -/* - * Division by zero triggers a SIGFPE on x86 and x86_64, - * but not on the PowerPC architecture. +/* Division by zero triggers a SIGFPE on x86 and x86_64, + but not on the PowerPC architecture. + + On ARM-Linux, we do get a SIGFPE, but not from the faulting of a + division instruction (there isn't any such thing) but rather + because the process exits via tgkill, sending itself a SIGFPE. + Hence we get a SIGFPE but the SI_CODE is different from that on + x86/amd64-linux. */ #if defined(__powerpc__) -#define DIVISION_BY_ZERO_TRIGGERS_FPE 0 -#define DIVISION_BY_ZERO_SI_CODE SI_TKILL +# define DIVISION_BY_ZERO_TRIGGERS_FPE 0 +# define DIVISION_BY_ZERO_SI_CODE SI_TKILL +#elif defined(__arm__) +# define DIVISION_BY_ZERO_TRIGGERS_FPE 1 +# define DIVISION_BY_ZERO_SI_CODE SI_TKILL #else -#define DIVISION_BY_ZERO_TRIGGERS_FPE 1 -#define DIVISION_BY_ZERO_SI_CODE FPE_INTDIV +# define DIVISION_BY_ZERO_TRIGGERS_FPE 1 +# define DIVISION_BY_ZERO_SI_CODE FPE_INTDIV #endif diff --git a/none/tests/filter_cmdline1 b/none/tests/filter_cmdline1 index e6b58ae..a301000 100755 --- a/none/tests/filter_cmdline1 +++ b/none/tests/filter_cmdline1 @@ -1,4 +1,5 @@ #! /bin/sh -perl -p -e 's/(set minimum alignment of heap allocations) \[(8|16)\]/$1 [...]/' +sed -e 's/\(set minimum alignment of heap allocations\) \[[0-9]*\]/\1 [...]/' \ + -e 's/\(command to start debugger\) \[.* -nw %f %p\]/\1 [... -nw %f %p]/' diff --git a/none/tests/ppc32/Makefile.am b/none/tests/ppc32/Makefile.am index 1f564fb..d3da324 100644 --- a/none/tests/ppc32/Makefile.am +++ b/none/tests/ppc32/Makefile.am @@ -21,18 +21,28 @@ EXTRA_DIST = \ testVMX.stderr.exp testVMX.stdout.exp testVMX.vgtest \ twi.stderr.exp twi.stdout.exp twi.vgtest \ tw.stderr.exp tw.stdout.exp tw.vgtest \ - xlc_dbl_u32.stderr.exp xlc_dbl_u32.stdout.exp xlc_dbl_u32.vgtest + xlc_dbl_u32.stderr.exp xlc_dbl_u32.stdout.exp xlc_dbl_u32.vgtest \ + power5+_round.stderr.exp power5+_round.stdout.exp power5+_round.vgtest \ + power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest check_PROGRAMS = \ bug129390-ppc32 \ bug139050-ppc32 \ ldstrev lsw jm-insns mftocrf mcrfs round test_fx test_gx \ - testVMX twi tw xlc_dbl_u32 + testVMX twi tw xlc_dbl_u32 power5+_round power6_bcmp AM_CFLAGS += @FLAG_M32@ AM_CXXFLAGS += @FLAG_M32@ AM_CCASFLAGS += @FLAG_M32@ -jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec @FLAG_M32@ +if HAS_ALTIVEC +ALTIVEC_FLAG = -DHAS_ALTIVEC +else +ALTIVEC_FLAG = +endif + +jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \ + @FLAG_M32@ $(ALTIVEC_FLAG) + testVMX_CFLAGS = $(AM_CFLAGS) -O -g -Wall -maltivec -mabi=altivec -DALTIVEC \ -DGCC_COMPILER @FLAG_M32@ diff --git a/none/tests/ppc32/bug129390-ppc32.vgtest b/none/tests/ppc32/bug129390-ppc32.vgtest index a4fb6ba..d7d05b3 100644 --- a/none/tests/ppc32/bug129390-ppc32.vgtest +++ b/none/tests/ppc32/bug129390-ppc32.vgtest @@ -1,2 +1,3 @@ +prereq: ../../../tests/check_vmx_cap prog: bug129390-ppc32 vgopts: -q diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c index 16adc73..2986b41 100644 --- a/none/tests/ppc32/jm-insns.c +++ b/none/tests/ppc32/jm-insns.c @@ -167,15 +167,32 @@ case I chased). #include #include "tests/sys_mman.h" +#include "tests/malloc.h" // memalign16 + +#define STATIC_ASSERT(e) sizeof(struct { int:-!(e); }) /* Something of the same size as void*, so can be safely be coerced - to/from a pointer type. Also same size as the host's gp registers. */ + * to/from a pointer type. Also same size as the host's gp registers. + * According to the AltiVec section of the GCC manual, the syntax does + * not allow the use of a typedef name as a type specifier in conjunction + * with the vector keyword, so typedefs uint[32|64]_t are #undef'ed here + * and redefined using #define. + */ +#undef uint32_t +#undef uint64_t +#define uint32_t unsigned int +#define uint64_t unsigned long long + #ifndef __powerpc64__ typedef uint32_t HWord_t; #else typedef uint64_t HWord_t; -#endif // #ifndef __powerpc64__ +#endif /* __powerpc64__ */ +enum { + compile_time_test1 = STATIC_ASSERT(sizeof(uint32_t) == 4), + compile_time_test2 = STATIC_ASSERT(sizeof(uint64_t) == 8), +}; #define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7" @@ -210,17 +227,17 @@ typedef uint64_t HWord_t; /* XXXX these must all be callee-save regs! */ -register double f14 __asm__ ("f14"); -register double f15 __asm__ ("f15"); -register double f16 __asm__ ("f16"); -register double f17 __asm__ ("f17"); +register double f14 __asm__ ("fr14"); +register double f15 __asm__ ("fr15"); +register double f16 __asm__ ("fr16"); +register double f17 __asm__ ("fr17"); register HWord_t r14 __asm__ ("r14"); register HWord_t r15 __asm__ ("r15"); register HWord_t r16 __asm__ ("r16"); register HWord_t r17 __asm__ ("r17"); -#include "config.h" -#if defined (HAVE_ALTIVEC_H) +#include "config.h" // HAS_ALTIVEC +#if defined (HAS_ALTIVEC) # include #endif #include diff --git a/none/tests/ppc32/jm-vmx.vgtest b/none/tests/ppc32/jm-vmx.vgtest index 0f32c0d..183536b 100644 --- a/none/tests/ppc32/jm-vmx.vgtest +++ b/none/tests/ppc32/jm-vmx.vgtest @@ -1 +1,2 @@ +prereq: ../../../tests/check_vmx_cap prog: jm-insns -a diff --git a/none/tests/ppc32/power5+_round.c b/none/tests/ppc32/power5+_round.c new file mode 100644 index 0000000..d6f6bc3 --- /dev/null +++ b/none/tests/ppc32/power5+_round.c @@ -0,0 +1,168 @@ +/* Copyright (C) 2007 IBM + + Author: Pete Eberlein eberlein@us.ibm.com + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + + + +#include +#include +#include + +#define POS_NORMAL 0x4000 +#define NEG_NORMAL 0x8000 +#define POS_INF 0x5000 +#define NEG_INF 0x9000 +#define POS_ZERO 0x2000 +#define NEG_ZERO 0x12000 +#define POS_DENORMAL 0x14000 +#define NEG_DENORMAL 0x18000 +#define NAN 0x11000 +#define FPRF_MASK 0x1F000 + + +int main(int argc, char *argv[]) +{ + + double inf, neg0, nan; + union { + double d; + struct { + unsigned int dummy, dummy2:15, fprf:17; + }; + } fpscr; + + inf = strtod("inf", NULL); + neg0 = strtod("-0", NULL); + nan = strtod("nan", NULL); + + + /* This set is disabled until fprf is implemented. */ + if (0) { + double set[] = { inf, 1.5, 0, neg0, -1.5, -inf, nan }; + int i, j, fprf; + for (i = 0; i < 7; ++i) { + for (j = 0; j < 7; ++j) { + asm("fcmpu 1, %1, %2\n\t" "mffs %0\n":"=f"(fpscr.d) + : "f"(set[i]), "f"(set[j]) + ); + + if (i == 6 || j == 6) { + fprf = 0x1000; // Unordered + } else if (i == j || (i == 2 && j == 3) || (i == 3 && j == 2)) { + fprf = 0x2000; // Equal + } else if (i < j) { + fprf = 0x4000; // Greater Than + } else if (i > j) { + fprf = 0x8000; // Less Than + } + + printf("fcmpu\t%.1f\t%.1f\t%x\t%s\n", set[i], set[j], + fpscr.fprf, fpscr.fprf == fprf ? "PASS" : "FAIL"); + } + } + } + + { + double set[] = { inf, 1.9, 1.1, 0, neg0, -1.1, -1.9, -inf, nan }; + double frin[] = { inf, 2.0, 1.0, 0, neg0, -1.0, -2.0, -inf, nan }; + double friz[] = { inf, 1.0, 1.0, 0, neg0, -1.0, -1.0, -inf, nan }; + double frip[] = { inf, 2.0, 2.0, 0, neg0, -1.0, -1.0, -inf, nan }; + double frim[] = { inf, 1.0, 1.0, 0, neg0, -2.0, -2.0, -inf, nan }; + int fprf[] = { POS_INF, POS_NORMAL, POS_NORMAL, POS_ZERO, NEG_ZERO, + NEG_NORMAL, NEG_NORMAL, NEG_INF, NAN + }; + double set2[] = { 0.9, 0.1, -0.1, -0.9, 1e-40, -1e-40 }; + double frin2[] = { 1.0, 0.0, -0.0, -1.0, 0.0, -0.0 }; + int frin2rf[] = + { POS_NORMAL, POS_ZERO, NEG_ZERO, NEG_NORMAL, POS_ZERO, + NEG_ZERO }; + double friz2[] = { 0.0, 0.0, -0.0, -0.0, 0.0, -0.0 }; + int friz2rf[] = + { POS_ZERO, POS_ZERO, NEG_ZERO, NEG_ZERO, POS_ZERO, NEG_ZERO }; + double frip2[] = { 1.0, 1.0, -0.0, -0.0, 1.0, -0.0 }; + int frip2rf[] = + { POS_NORMAL, POS_NORMAL, NEG_ZERO, NEG_ZERO, POS_NORMAL, + NEG_ZERO }; + double frim2[] = { 0.0, 0.0, -1.0, -1.0, 0.0, -1.0 }; + int frim2rf[] = + { POS_ZERO, POS_ZERO, NEG_NORMAL, NEG_NORMAL, POS_ZERO, + NEG_NORMAL }; + double ret; + int i; + +#define DO_TEST(op,in,out,rf) for (i=0; i +#include +#include + +#define CMPB(result,a,b) \ + asm __volatile ("cmpb %0, %1, %2\n" : "=r"(result) : "r"(a), "r"(b)) + + +int main(int argc, char *argv[]) +{ + int i, j, k; + long mask; + for (i = 1; i < 16; i++) { + mask = 0; + if (i & 1) + mask += 0xff; + if (i & 2) + mask += 0xff00; + if (i & 4) + mask += 0xff0000; + if (i & 8) + mask += 0xff000000; + + for (j = 0; j < 256; j++) + for (k = 0; k < 256; k++) + if (j != k) { + + long a, b, result; + a = (mask & (j * 0x1010101)) + ((~mask) & (k * 0x1010101)); + b = j * 0x1010101; + CMPB(result, a, b); + if (result != mask) { + printf("%llx %llx %llx %llx\n", + (unsigned long long) mask, (unsigned long long) a, + (unsigned long long) b, + (unsigned long long) result); + exit(1); + } + } + + } + + return 0; +} diff --git a/none/tests/ppc32/power6_bcmp.stderr.exp b/none/tests/ppc32/power6_bcmp.stderr.exp new file mode 100644 index 0000000..139597f --- /dev/null +++ b/none/tests/ppc32/power6_bcmp.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc32/power6_bcmp.stdout.exp b/none/tests/ppc32/power6_bcmp.stdout.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/ppc32/power6_bcmp.vgtest b/none/tests/ppc32/power6_bcmp.vgtest new file mode 100644 index 0000000..28146c0 --- /dev/null +++ b/none/tests/ppc32/power6_bcmp.vgtest @@ -0,0 +1 @@ +prog: power6_bcmp diff --git a/none/tests/ppc32/testVMX.vgtest b/none/tests/ppc32/testVMX.vgtest index 7c51503..81c59f2 100644 --- a/none/tests/ppc32/testVMX.vgtest +++ b/none/tests/ppc32/testVMX.vgtest @@ -1 +1,2 @@ +prereq: ../../../tests/check_vmx_cap prog: testVMX diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 5d8b08d..fdd515a 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -11,13 +11,23 @@ EXTRA_DIST = \ std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp \ round.stderr.exp round.stdout.exp round.vgtest \ twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \ - tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest + tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \ + power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \ + power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest check_PROGRAMS = \ - jm-insns lsw round std_reg_imm twi_tdi tw_td + jm-insns lsw round std_reg_imm twi_tdi tw_td power6_bcmp power6_mf_gpr AM_CFLAGS += @FLAG_M64@ AM_CXXFLAGS += @FLAG_M64@ AM_CCASFLAGS += @FLAG_M64@ -jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec @FLAG_M64@ +if HAS_ALTIVEC +ALTIVEC_FLAG = -DHAS_ALTIVEC +else +ALTIVEC_FLAG = +endif + +jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \ + @FLAG_M64@ $(ALTIVEC_FLAG) + diff --git a/none/tests/ppc64/jm-insns.c b/none/tests/ppc64/jm-insns.c index 16adc73..2986b41 100644 --- a/none/tests/ppc64/jm-insns.c +++ b/none/tests/ppc64/jm-insns.c @@ -167,15 +167,32 @@ case I chased). #include #include "tests/sys_mman.h" +#include "tests/malloc.h" // memalign16 + +#define STATIC_ASSERT(e) sizeof(struct { int:-!(e); }) /* Something of the same size as void*, so can be safely be coerced - to/from a pointer type. Also same size as the host's gp registers. */ + * to/from a pointer type. Also same size as the host's gp registers. + * According to the AltiVec section of the GCC manual, the syntax does + * not allow the use of a typedef name as a type specifier in conjunction + * with the vector keyword, so typedefs uint[32|64]_t are #undef'ed here + * and redefined using #define. + */ +#undef uint32_t +#undef uint64_t +#define uint32_t unsigned int +#define uint64_t unsigned long long + #ifndef __powerpc64__ typedef uint32_t HWord_t; #else typedef uint64_t HWord_t; -#endif // #ifndef __powerpc64__ +#endif /* __powerpc64__ */ +enum { + compile_time_test1 = STATIC_ASSERT(sizeof(uint32_t) == 4), + compile_time_test2 = STATIC_ASSERT(sizeof(uint64_t) == 8), +}; #define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7" @@ -210,17 +227,17 @@ typedef uint64_t HWord_t; /* XXXX these must all be callee-save regs! */ -register double f14 __asm__ ("f14"); -register double f15 __asm__ ("f15"); -register double f16 __asm__ ("f16"); -register double f17 __asm__ ("f17"); +register double f14 __asm__ ("fr14"); +register double f15 __asm__ ("fr15"); +register double f16 __asm__ ("fr16"); +register double f17 __asm__ ("fr17"); register HWord_t r14 __asm__ ("r14"); register HWord_t r15 __asm__ ("r15"); register HWord_t r16 __asm__ ("r16"); register HWord_t r17 __asm__ ("r17"); -#include "config.h" -#if defined (HAVE_ALTIVEC_H) +#include "config.h" // HAS_ALTIVEC +#if defined (HAS_ALTIVEC) # include #endif #include diff --git a/none/tests/ppc64/jm-vmx.vgtest b/none/tests/ppc64/jm-vmx.vgtest index 0f32c0d..183536b 100644 --- a/none/tests/ppc64/jm-vmx.vgtest +++ b/none/tests/ppc64/jm-vmx.vgtest @@ -1 +1,2 @@ +prereq: ../../../tests/check_vmx_cap prog: jm-insns -a diff --git a/none/tests/ppc64/power6_bcmp.c b/none/tests/ppc64/power6_bcmp.c new file mode 100644 index 0000000..3137743 --- /dev/null +++ b/none/tests/ppc64/power6_bcmp.c @@ -0,0 +1,73 @@ +/* Copyright (C) 2007 IBM + + Author: Pete Eberlein eberlein@us.ibm.com + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + + +#include +#include +#include + +#define CMPB(result,a,b) \ + asm ("cmpb %0, %1, %2\n" : "=r"(result) : "r"(a), "r"(b)) + + +int main(int argc, char *argv[]) +{ + int i, j, k; + unsigned long mask; + for (i = 1; i < 256; i++) { + mask = 0; + if (i & 1) + mask += 0xff; + if (i & 2) + mask += 0xff00; + if (i & 4) + mask += 0xff0000; + if (i & 8) + mask += 0xff000000; + if (i & 16) + mask += 0xff00000000; + if (i & 32) + mask += 0xff0000000000; + if (i & 64) + mask += 0xff000000000000; + if (i & 128) + mask += 0xff00000000000000; + + for (j = 0; j < 256; j++) + for (k = 0; k < 256; k++) + if (j != k) { + + unsigned long a, b, result; + a = (mask & (j * 0x101010101010101)) + + ((~mask) & (k * 0x101010101010101)); + b = j * 0x101010101010101; + CMPB(result, a, b); + if (result != mask) { + printf("%8lx %8lx %8lx %8lx\n", mask, a, b, result); + exit(1); + } + } + + } + + return 0; +} diff --git a/none/tests/ppc64/power6_bcmp.stderr.exp b/none/tests/ppc64/power6_bcmp.stderr.exp new file mode 100644 index 0000000..139597f --- /dev/null +++ b/none/tests/ppc64/power6_bcmp.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/power6_bcmp.stdout.exp b/none/tests/ppc64/power6_bcmp.stdout.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/ppc64/power6_bcmp.vgtest b/none/tests/ppc64/power6_bcmp.vgtest new file mode 100644 index 0000000..28146c0 --- /dev/null +++ b/none/tests/ppc64/power6_bcmp.vgtest @@ -0,0 +1 @@ +prog: power6_bcmp diff --git a/none/tests/ppc64/power6_mf_gpr.c b/none/tests/ppc64/power6_mf_gpr.c new file mode 100644 index 0000000..ba4bf4d --- /dev/null +++ b/none/tests/ppc64/power6_mf_gpr.c @@ -0,0 +1,49 @@ +/* Copyright (C) 2007 IBM + + Author: Pete Eberlein eberlein@us.ibm.com + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307, USA. + + The GNU General Public License is contained in the file COPYING. +*/ + +#include +#include + + + +int main(int argc, char *argv[]) +{ + + long i; + double f; + + i = 0; + f = 100.0; + + printf("%lx %f\n", i, f); + + asm("mftgpr %0, %1\n": "=r"(i):"f"(f)); + + f = 0.0; + printf("%lx %f\n", i, f); + + asm("mffgpr %0, %1\n": "=f"(f):"r"(i)); + + printf("%lx %f\n", i, f); + + return 0; +} diff --git a/none/tests/ppc64/power6_mf_gpr.stderr.exp b/none/tests/ppc64/power6_mf_gpr.stderr.exp new file mode 100644 index 0000000..139597f --- /dev/null +++ b/none/tests/ppc64/power6_mf_gpr.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/power6_mf_gpr.stdout.exp b/none/tests/ppc64/power6_mf_gpr.stdout.exp new file mode 100644 index 0000000..7bc827d --- /dev/null +++ b/none/tests/ppc64/power6_mf_gpr.stdout.exp @@ -0,0 +1,3 @@ +0 100.000000 +4059000000000000 0.000000 +4059000000000000 100.000000 diff --git a/none/tests/ppc64/power6_mf_gpr.vgtest b/none/tests/ppc64/power6_mf_gpr.vgtest new file mode 100644 index 0000000..5868fe6 --- /dev/null +++ b/none/tests/ppc64/power6_mf_gpr.vgtest @@ -0,0 +1 @@ +prog: power6_mf_gpr diff --git a/none/tests/procfs-cmdline-exe.c b/none/tests/procfs-cmdline-exe.c new file mode 100644 index 0000000..9f550e5 --- /dev/null +++ b/none/tests/procfs-cmdline-exe.c @@ -0,0 +1,115 @@ +/* + * Read /proc/self/cmdline and /proc/self/exe such that it can be tested + * whether Valgrind intercepts the system calls that access these pseudo-files + * properly on Linux and whether Valgrind does not modify the behavior of + * accessing these files on other operating systems. + */ + +#define _ATFILE_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../config.h" + +static void test_cmdline(const char* const cwd, const char* const label, + const char* const path) +{ + int fd, n; + char ch; + + fprintf(stderr, "%s:\n", label); + fd = open(path, 0); + if (fd >= 0) + { + while ((n = read(fd, &ch, 1)) > 0) + { + if (ch == '\\') + fprintf(stderr, "\\\\"); + else if (ch == 0) + fprintf(stderr, "\\0"); + else if (isprint((unsigned)ch)) + fprintf(stderr, "%c", ch); + else + fprintf(stderr, "\\0%o", ch); + } + fprintf(stderr, "\n"); + close(fd); + } + else + perror("open()"); +} + +static void test_readlink(const char* const cwd, const char* const label, + const char* const path) +{ + char buf[512]; + const char* p; + int n; + + if ((n = readlink(path, buf, sizeof(buf) - 1)) >= 0) + { + buf[n] = 0; + p = buf; + if (strncmp(buf, cwd, strlen(cwd)) == 0) + p += strlen(cwd); + fprintf(stderr, "Result of readlink(\"%s\"): %s\n", label, p); + } + else + perror("readlink"); +} + +static void test_readlinkat(const char* const cwd, const char* const label, + const char* const path) +{ +#if HAVE_READLINKAT + char buf[512]; + const char* p; + int n; + + if ((n = readlinkat(AT_FDCWD, path, buf, sizeof(buf) - 1)) >= 0) + { + buf[n] = 0; + p = buf; + if (strncmp(buf, cwd, strlen(cwd)) == 0) + p += strlen(cwd); + fprintf(stderr, "Result of readlinkat(\"%s\"): %s\n", label, p); + } + else + perror("readlinkat"); +#else + errno = ENOSYS; + perror("readlinkat"); +#endif +} + +int main(int argc, char** argv) +{ + char cwd[512]; + char path[512]; + + cwd[0] = 0; + if (! getcwd(cwd, sizeof(cwd))) + perror("getcwd"); + strcat(cwd, "/"); + + snprintf(path, sizeof(path), "/proc/%d/cmdline", getpid()); + + test_cmdline(cwd, "/proc/self/cmdline", "/proc/self/cmdline"); + test_cmdline(cwd, "/proc//cmdline", path); + + snprintf(path, sizeof(path), "/proc/%d/exe", getpid()); + + test_readlink(cwd, "/proc/self/exe", "/proc/self/exe"); + test_readlink(cwd, "/proc//exe", path); + + test_readlinkat(cwd, "/proc/self/exe", "/proc/self/exe"); + test_readlinkat(cwd, "/proc//exe", path); + + return 0; +} diff --git a/none/tests/procfs-linux.stderr.exp-with-readlinkat b/none/tests/procfs-linux.stderr.exp-with-readlinkat new file mode 100644 index 0000000..6314262 --- /dev/null +++ b/none/tests/procfs-linux.stderr.exp-with-readlinkat @@ -0,0 +1,10 @@ + +/proc/self/cmdline: +./procfs-cmdline-exe\0arg1\0arg 2\0arg3\0 +/proc//cmdline: +./procfs-cmdline-exe\0arg1\0arg 2\0arg3\0 +Result of readlink("/proc/self/exe"): procfs-cmdline-exe +Result of readlink("/proc//exe"): procfs-cmdline-exe +Result of readlinkat("/proc/self/exe"): procfs-cmdline-exe +Result of readlinkat("/proc//exe"): procfs-cmdline-exe + diff --git a/none/tests/procfs-linux.stderr.exp-without-readlinkat b/none/tests/procfs-linux.stderr.exp-without-readlinkat new file mode 100644 index 0000000..25fd8e6 --- /dev/null +++ b/none/tests/procfs-linux.stderr.exp-without-readlinkat @@ -0,0 +1,10 @@ + +/proc/self/cmdline: +./procfs-cmdline-exe\0arg1\0arg 2\0arg3\0 +/proc//cmdline: +./procfs-cmdline-exe\0arg1\0arg 2\0arg3\0 +Result of readlink("/proc/self/exe"): procfs-cmdline-exe +Result of readlink("/proc//exe"): procfs-cmdline-exe +readlinkat: Function not implemented +readlinkat: Function not implemented + diff --git a/none/tests/procfs-linux.vgtest b/none/tests/procfs-linux.vgtest new file mode 100644 index 0000000..ea8a8e9 --- /dev/null +++ b/none/tests/procfs-linux.vgtest @@ -0,0 +1,4 @@ +prereq: [ $(uname) = Linux ] +prog: procfs-cmdline-exe +args: arg1 "arg 2" arg3 +stderr_filter: filter_stderr diff --git a/none/tests/procfs-non-linux.stderr.exp b/none/tests/procfs-non-linux.stderr.exp new file mode 100644 index 0000000..ec92dfa --- /dev/null +++ b/none/tests/procfs-non-linux.stderr.exp @@ -0,0 +1,10 @@ + +/proc/self/cmdline: +open(): No such file or directory +/proc//cmdline: +open(): No such file or directory +readlink: No such file or directory +readlink: No such file or directory +readlinkat: Function not implemented +readlinkat: Function not implemented + diff --git a/none/tests/procfs-non-linux.vgtest b/none/tests/procfs-non-linux.vgtest new file mode 100644 index 0000000..61bf349 --- /dev/null +++ b/none/tests/procfs-non-linux.vgtest @@ -0,0 +1,3 @@ +prereq: [ $(uname) != Linux ] +prog: procfs-cmdline-exe +stderr_filter: filter_stderr diff --git a/none/tests/require-text-symbol-1.stderr.exp b/none/tests/require-text-symbol-1.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/require-text-symbol-1.vgtest b/none/tests/require-text-symbol-1.vgtest new file mode 100644 index 0000000..fca0092 --- /dev/null +++ b/none/tests/require-text-symbol-1.vgtest @@ -0,0 +1,2 @@ +prog: require-text-symbol +vgopts: -q "--require-text-symbol=:*libc.so*:strl?n" diff --git a/none/tests/require-text-symbol-2.stderr.exp-libcso6 b/none/tests/require-text-symbol-2.stderr.exp-libcso6 new file mode 100644 index 0000000..0d66f2d --- /dev/null +++ b/none/tests/require-text-symbol-2.stderr.exp-libcso6 @@ -0,0 +1,9 @@ + +valgrind: Fatal error at when loading library with soname +valgrind: libc.so.6 +valgrind: Cannot find any text symbol with a name that matches the pattern +valgrind: doesntexist +valgrind: as required by a --require-text-symbol= specification. + +valgrind: Cannot continue -- exiting now. + diff --git a/none/tests/require-text-symbol-2.vgtest b/none/tests/require-text-symbol-2.vgtest new file mode 100644 index 0000000..48b553b --- /dev/null +++ b/none/tests/require-text-symbol-2.vgtest @@ -0,0 +1,2 @@ +prog: require-text-symbol +vgopts: -q "--require-text-symbol=:*libc.so*:doesntexist" diff --git a/none/tests/require-text-symbol.c b/none/tests/require-text-symbol.c new file mode 100644 index 0000000..15b827c --- /dev/null +++ b/none/tests/require-text-symbol.c @@ -0,0 +1,8 @@ + +/* Doesn't do anything. The point of this is to test for the presence + of a couple of symbols in libc.so. See the .vgtest files. */ + +int main ( void ) +{ + return 0; +} diff --git a/none/tests/valgrind_cpp_test.cpp b/none/tests/valgrind_cpp_test.cpp new file mode 100644 index 0000000..f4edade --- /dev/null +++ b/none/tests/valgrind_cpp_test.cpp @@ -0,0 +1,47 @@ +// Test program to verify whether the Valgrind header files compile fine +// with a C++ compiler. + + +#include +#include +#include "pub_tool_basics.h" +#include "pub_tool_libcassert.h" +#include "pub_tool_libcbase.h" +#include "pub_tool_mallocfree.h" +#include "pub_tool_libcprint.h" +#include "pub_tool_libcfile.h" +#include "pub_tool_libcproc.h" +#include "pub_tool_vki.h" +#include "pub_tool_threadstate.h" +#include "pub_tool_errormgr.h" +#include "pub_tool_options.h" +#include "pub_tool_machine.h" +#include "pub_tool_debuginfo.h" +#include "pub_tool_seqmatch.h" +#include "pub_tool_tooliface.h" +#include "pub_tool_options.h" + +#if defined(VGO_darwin) +int CheckSys() +{ + return SysRes_MACH; +} +#endif + +void CheckAssert(int x) +{ + tl_assert(x); + tl_assert2(x, "fail"); +} + +int main(int argc, char** argv) +{ + fprintf(stderr, "Compilation succeeded.\n"); + return 0; +} + +void VG_(assert_fail)(Bool isCore, const Char* expr, const Char* file, + Int line, const Char* fn, const HChar* format, ... ) +{ + abort(); +} diff --git a/none/tests/x86/Makefile.am b/none/tests/x86/Makefile.am index 47d6a34..0fa2194 100644 --- a/none/tests/x86/Makefile.am +++ b/none/tests/x86/Makefile.am @@ -17,6 +17,9 @@ endif # Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS, # to avoid packaging screwups if 'make dist' is run on a machine # which failed the BUILD_SSE3_TESTS test in configure.in. + +## FIXME: move lzcnt32 to SSE4 conditionalisation, when that happens. + EXTRA_DIST = \ badseg.stderr.exp badseg.stdout.exp badseg.vgtest \ bt_everything.stderr.exp bt_everything.stdout.exp bt_everything.vgtest \ @@ -46,6 +49,7 @@ EXTRA_DIST = \ jcxz.stdout.exp jcxz.stderr.exp jcxz.vgtest \ lahf.stdout.exp lahf.stderr.exp lahf.vgtest \ looper.stderr.exp looper.stdout.exp looper.vgtest \ + lzcnt32.stderr.exp lzcnt32.stdout.exp lzcnt32.vgtest \ movx.stderr.exp movx.stdout.exp movx.vgtest \ pushpopseg.stderr.exp pushpopseg.stdout.exp pushpopseg.vgtest \ sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \ @@ -53,7 +57,8 @@ EXTRA_DIST = \ ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \ ssse3_misaligned.vgtest ssse3_misaligned.c \ x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \ - yield.stderr.exp yield.stdout.exp yield.disabled + yield.stderr.exp yield.stdout.exp yield.disabled \ + xadd.stdout.exp xadd.stderr.exp xadd.vgtest check_PROGRAMS = \ badseg \ @@ -84,10 +89,14 @@ check_PROGRAMS = \ sbbmisc \ smc1 \ x86locked \ - yield + yield \ + xadd if BUILD_SSSE3_TESTS check_PROGRAMS += ssse3_misaligned endif +if BUILD_LZCNT_TESTS + check_PROGRAMS += lzcnt32 +endif AM_CFLAGS += @FLAG_M32@ $(FLAG_MMMX) $(FLAG_MSSE) diff --git a/none/tests/x86/fxtract.stdout.exp b/none/tests/x86/fxtract.stdout.exp index 4508fd6..b82f306 100644 --- a/none/tests/x86/fxtract.stdout.exp +++ b/none/tests/x86/fxtract.stdout.exp @@ -40,7 +40,7 @@ 2.7049662808e+02 -> 1.0566274534 8.0000000000 0.0000000000e+00 -> 0.0000000000 -inf inf -> inf inf - nan -> nan nan + -nan -> -nan -nan 7.2124891681e-308 -> 1.6207302828 -1021.0000000000 5.7982756057e-308 -> 1.3029400313 -1021.0000000000 4.3840620434e-308 -> 1.9702995595 -1022.0000000000 diff --git a/none/tests/x86/lzcnt32.c b/none/tests/x86/lzcnt32.c new file mode 100644 index 0000000..107a25d --- /dev/null +++ b/none/tests/x86/lzcnt32.c @@ -0,0 +1,66 @@ + +#include + +typedef unsigned long long int ULong; +typedef unsigned int UInt; + +__attribute__((noinline)) +void do_lzcnt32 ( /*OUT*/UInt* flags, /*OUT*/UInt* res, UInt arg ) +{ + UInt block[3] = { arg, 0, 0 }; + __asm__ __volatile__( + "movl $0x55555555, %%esi" "\n\t" + "lzcntl 0(%0), %%esi" "\n\t" + "movl %%esi, 4(%0)" "\n\t" + "pushfl" "\n\t" + "popl %%esi" "\n\t" + "movl %%esi, 8(%0)" "\n" + : : "r"(&block[0]) : "esi","cc","memory" + ); + *res = block[1]; + *flags = block[2] & 0x8d5; +} + +__attribute__((noinline)) +void do_lzcnt16 ( /*OUT*/UInt* flags, /*OUT*/UInt* res, UInt arg ) +{ + UInt block[3] = { arg, 0, 0 }; + __asm__ __volatile__( + "movl $0x55555555, %%esi" "\n\t" + "lzcntw 0(%0), %%si" "\n\t" + "movl %%esi, 4(%0)" "\n\t" + "pushfl" "\n\t" + "popl %%esi" "\n\t" + "movl %%esi, 8(%0)" "\n" + : : "r"(&block[0]) : "esi","cc","memory" + ); + *res = block[1]; + *flags = block[2] & 0x8d5; +} + +int main ( void ) +{ + UInt w; + + w = 0xFEDC1928; + while (1) { + UInt res; + UInt flags; + do_lzcnt32(&flags, &res, w); + printf("lzcntl %08x -> %08x %04x\n", w, res, flags); + if (w == 0) break; + w = ((w >> 2) | (w >> 1)) + (w / 17); + } + + w = 0xFEDC1928; + while (1) { + UInt res; + UInt flags; + do_lzcnt16(&flags, &res, w); + printf("lzcntw %08x -> %08x %04x\n", w, res, flags); + if (w == 0) break; + w = ((w >> 2) | (w >> 1)) + (w / 17); + } + + return 0; +} diff --git a/none/tests/x86/lzcnt32.stderr.exp b/none/tests/x86/lzcnt32.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/x86/lzcnt32.stdout.exp b/none/tests/x86/lzcnt32.stdout.exp new file mode 100644 index 0000000..41773d3 --- /dev/null +++ b/none/tests/x86/lzcnt32.stdout.exp @@ -0,0 +1,122 @@ +lzcntl fedc1928 -> 00000000 0040 +lzcntl 8efcf23a -> 00000000 0040 +lzcntl 7068b90b -> 00000001 0000 +lzcntl 42db3e5e -> 00000001 0000 +lzcntl 35eea72d -> 00000002 0000 +lzcntl 232c23d2 -> 00000002 0000 +lzcntl 1bf0c1be -> 00000003 0000 +lzcntl 11a13119 -> 00000003 0000 +lzcntl 0e025829 -> 00000004 0000 +lzcntl 0854b43e -> 00000004 0000 +lzcntl 06bcf322 -> 00000005 0000 +lzcntl 0464f58f -> 00000005 0000 +lzcntl 037dac76 -> 00000006 0000 +lzcntl 023490eb -> 00000006 0000 +lzcntl 01c0a232 -> 00000007 0000 +lzcntl 010add81 -> 00000007 0000 +lzcntl 00d7b28d -> 00000008 0000 +lzcntl 008cae0d -> 00000008 0000 +lzcntl 006fc600 -> 00000009 0000 +lzcntl 004686ad -> 00000009 0000 +lzcntl 00380a09 -> 0000000a 0000 +lzcntl 00215368 -> 0000000a 0000 +lzcntl 001af3d6 -> 0000000b 0000 +lzcntl 001193de -> 0000000b 0000 +lzcntl 000df6b1 -> 0000000c 0000 +lzcntl 0008d242 -> 0000000c 0000 +lzcntl 00070287 -> 0000000d 0000 +lzcntl 00042b72 -> 0000000d 0000 +lzcntl 00035ec7 -> 0000000e 0000 +lzcntl 000232b3 -> 0000000e 0000 +lzcntl 0001bf16 -> 0000000f 0000 +lzcntl 00011a1b -> 0000000f 0000 +lzcntl 0000e027 -> 00000010 0000 +lzcntl 0000854a -> 00000010 0000 +lzcntl 00006bce -> 00000011 0000 +lzcntl 0000464e -> 00000011 0000 +lzcntl 000037d9 -> 00000012 0000 +lzcntl 00002347 -> 00000012 0000 +lzcntl 00001c06 -> 00000013 0000 +lzcntl 000010a9 -> 00000013 0000 +lzcntl 00000d78 -> 00000014 0000 +lzcntl 000008c8 -> 00000014 0000 +lzcntl 000006fa -> 00000015 0000 +lzcntl 00000468 -> 00000015 0000 +lzcntl 00000380 -> 00000016 0000 +lzcntl 00000214 -> 00000016 0000 +lzcntl 000001ae -> 00000017 0000 +lzcntl 00000118 -> 00000017 0000 +lzcntl 000000de -> 00000018 0000 +lzcntl 0000008c -> 00000018 0000 +lzcntl 0000006f -> 00000019 0000 +lzcntl 00000045 -> 00000019 0000 +lzcntl 00000037 -> 0000001a 0000 +lzcntl 00000022 -> 0000001a 0000 +lzcntl 0000001b -> 0000001b 0000 +lzcntl 00000010 -> 0000001b 0000 +lzcntl 0000000c -> 0000001c 0000 +lzcntl 00000007 -> 0000001d 0000 +lzcntl 00000003 -> 0000001e 0000 +lzcntl 00000001 -> 0000001f 0000 +lzcntl 00000000 -> 00000020 0001 +lzcntw fedc1928 -> 55550003 0000 +lzcntw 8efcf23a -> 55550000 0040 +lzcntw 7068b90b -> 55550000 0040 +lzcntw 42db3e5e -> 55550002 0000 +lzcntw 35eea72d -> 55550000 0040 +lzcntw 232c23d2 -> 55550002 0000 +lzcntw 1bf0c1be -> 55550000 0040 +lzcntw 11a13119 -> 55550002 0000 +lzcntw 0e025829 -> 55550001 0000 +lzcntw 0854b43e -> 55550000 0040 +lzcntw 06bcf322 -> 55550000 0040 +lzcntw 0464f58f -> 55550000 0040 +lzcntw 037dac76 -> 55550000 0040 +lzcntw 023490eb -> 55550000 0040 +lzcntw 01c0a232 -> 55550000 0040 +lzcntw 010add81 -> 55550000 0040 +lzcntw 00d7b28d -> 55550000 0040 +lzcntw 008cae0d -> 55550000 0040 +lzcntw 006fc600 -> 55550000 0040 +lzcntw 004686ad -> 55550000 0040 +lzcntw 00380a09 -> 55550004 0000 +lzcntw 00215368 -> 55550001 0000 +lzcntw 001af3d6 -> 55550000 0040 +lzcntw 001193de -> 55550000 0040 +lzcntw 000df6b1 -> 55550000 0040 +lzcntw 0008d242 -> 55550000 0040 +lzcntw 00070287 -> 55550006 0000 +lzcntw 00042b72 -> 55550002 0000 +lzcntw 00035ec7 -> 55550001 0000 +lzcntw 000232b3 -> 55550002 0000 +lzcntw 0001bf16 -> 55550000 0040 +lzcntw 00011a1b -> 55550003 0000 +lzcntw 0000e027 -> 55550000 0040 +lzcntw 0000854a -> 55550000 0040 +lzcntw 00006bce -> 55550001 0000 +lzcntw 0000464e -> 55550001 0000 +lzcntw 000037d9 -> 55550002 0000 +lzcntw 00002347 -> 55550002 0000 +lzcntw 00001c06 -> 55550003 0000 +lzcntw 000010a9 -> 55550003 0000 +lzcntw 00000d78 -> 55550004 0000 +lzcntw 000008c8 -> 55550004 0000 +lzcntw 000006fa -> 55550005 0000 +lzcntw 00000468 -> 55550005 0000 +lzcntw 00000380 -> 55550006 0000 +lzcntw 00000214 -> 55550006 0000 +lzcntw 000001ae -> 55550007 0000 +lzcntw 00000118 -> 55550007 0000 +lzcntw 000000de -> 55550008 0000 +lzcntw 0000008c -> 55550008 0000 +lzcntw 0000006f -> 55550009 0000 +lzcntw 00000045 -> 55550009 0000 +lzcntw 00000037 -> 5555000a 0000 +lzcntw 00000022 -> 5555000a 0000 +lzcntw 0000001b -> 5555000b 0000 +lzcntw 00000010 -> 5555000b 0000 +lzcntw 0000000c -> 5555000c 0000 +lzcntw 00000007 -> 5555000d 0000 +lzcntw 00000003 -> 5555000e 0000 +lzcntw 00000001 -> 5555000f 0000 +lzcntw 00000000 -> 55550010 0001 diff --git a/none/tests/x86/lzcnt32.vgtest b/none/tests/x86/lzcnt32.vgtest new file mode 100644 index 0000000..d1e95be --- /dev/null +++ b/none/tests/x86/lzcnt32.vgtest @@ -0,0 +1,3 @@ +prog: lzcnt32 +prereq: ../../../tests/x86_amd64_features x86-lzcnt +vgopts: -q diff --git a/none/tests/x86/sbbmisc.c b/none/tests/x86/sbbmisc.c index 20340f9..322d6e1 100644 --- a/none/tests/x86/sbbmisc.c +++ b/none/tests/x86/sbbmisc.c @@ -140,7 +140,58 @@ VG_SYM(adc_eb_gb_2) ":\n" "\tret\n" ); +extern void adc_ib_al ( void ); +asm("\n" +VG_SYM(adc_ib_al) ":\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tclc\n" +"\tadcb $5, %al\n" +"\tmovb %al, " VG_SYM(out_b1) "\n" + +"\tmovb " VG_SYM(in_b) ", %al\n" +"\tstc\n" +"\tadcb $5, %al\n" +"\tmovb %al, " VG_SYM(out_b2) "\n" +"\tret\n" +); + + +extern void adc_iw_ax ( void ); +asm("\n" +VG_SYM(adc_iw_ax) ":\n" + +"\tmovw " VG_SYM(in_w) ", %ax\n" +"\tclc\n" +"\tadcw $555, %ax\n" +"\tmovw %ax, " VG_SYM(out_w1) "\n" + +"\tmovw " VG_SYM(in_w) ", %ax\n" +"\tstc\n" +"\tadcw $555, %ax\n" +"\tmovw %ax, " VG_SYM(out_w2) "\n" + +"\tret\n" +); + + +extern void adc_il_eax ( void ); +asm("\n" +VG_SYM(adc_il_eax) ":\n" + +"\tmovl " VG_SYM(in_l) ", %eax\n" +"\tclc\n" +"\tadcl $555666, %eax\n" +"\tmovl %eax, " VG_SYM(out_l1) "\n" + +"\tmovl " VG_SYM(in_l) ", %eax\n" +"\tstc\n" +"\tadcl $555666, %eax\n" +"\tmovl %eax, " VG_SYM(out_l2) "\n" + +"\tret\n" +); int main ( void ) @@ -177,5 +228,17 @@ int main ( void ) adc_eb_gb_2(); printf("r7 = %d %d\n", (int)out_b1, (int)out_b2); + in_b = 99; + adc_ib_al(); + printf("r8 = %d %d\n", (int)out_b1, (int)out_b2); + + in_w = 49999; + adc_iw_ax(); + printf("r9 = %d %d\n", (int)out_w1, (int)out_w2); + + in_l = 0xF0000000; + adc_il_eax(); + printf("r10 = %d %d\n", (int)out_l1, (int)out_l2); + return 0; } diff --git a/none/tests/x86/sbbmisc.stdout.exp b/none/tests/x86/sbbmisc.stdout.exp index 6c616b0..2945cc3 100644 --- a/none/tests/x86/sbbmisc.stdout.exp +++ b/none/tests/x86/sbbmisc.stdout.exp @@ -5,3 +5,6 @@ r4 = 11 10 r5 = -11 -12 r6 = -69 -68 r7 = -113 -112 +r8 = 104 105 +r9 = -14982 -14981 +r10 = -267879790 -267879789 diff --git a/none/tests/x86/xadd.c b/none/tests/x86/xadd.c new file mode 100644 index 0000000..38d4f20 --- /dev/null +++ b/none/tests/x86/xadd.c @@ -0,0 +1,51 @@ + +#include "config.h" +#include +#include + +/* Simple test program, no race. + Tests the 'xadd' exchange-and-add instruction with {r,r} operands, which is rarely generated by compilers. */ + +#undef PLAT_x86_linux +#undef PLAT_amd64_linux +#undef PLAT_ppc32_linux +#undef PLAT_ppc64_linux +#undef PLAT_ppc32_aix5 +#undef PLAT_ppc64_aix5 + +#if !defined(_AIX) && defined(__i386__) +# define PLAT_x86_linux 1 +#elif !defined(_AIX) && defined(__x86_64__) +# define PLAT_amd64_linux 1 +#endif + + +#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) +# define XADD_R_R(_addr,_lval) \ + __asm__ __volatile__( \ + "xadd %1, %0" \ + : /*out*/ "=r"(_lval),"=r"(_addr) \ + : /*in*/ "0"(_lval),"1"(_addr) \ + : "flags" \ + ) +#else +# error "Unsupported architecture" +#endif + +int main ( void ) +{ + long d = 20, s = 2; + long xadd_r_r_res; +#define XADD_R_R_RES 42 + + XADD_R_R(s, d); + xadd_r_r_res = s + d; + assert(xadd_r_r_res == XADD_R_R_RES); + + if (xadd_r_r_res == XADD_R_R_RES) + printf("success\n"); + else + printf("failure\n"); + + return xadd_r_r_res; +} diff --git a/none/tests/x86/xadd.stderr.exp b/none/tests/x86/xadd.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/x86/xadd.stdout.exp b/none/tests/x86/xadd.stdout.exp new file mode 100644 index 0000000..2e9ba47 --- /dev/null +++ b/none/tests/x86/xadd.stdout.exp @@ -0,0 +1 @@ +success diff --git a/none/tests/x86/xadd.vgtest b/none/tests/x86/xadd.vgtest new file mode 100644 index 0000000..2cb1bee --- /dev/null +++ b/none/tests/x86/xadd.vgtest @@ -0,0 +1,2 @@ +prog: xadd +vgopts: -q diff --git a/perf/tinycc.c b/perf/tinycc.c index 782b3ff..ff25b55 100644 --- a/perf/tinycc.c +++ b/perf/tinycc.c @@ -21284,7 +21284,7 @@ static int64_t getclock_us(void) void help(void) { - printf("tcc version " TCC_VERSION " - Tiny C Compiler - Copyright (C) 2001-2009 Fabrice Bellard\n" + printf("tcc version " TCC_VERSION " - Tiny C Compiler - Copyright (C) 2001-2010 Fabrice Bellard\n" "usage: tcc [-v] [-c] [-o outfile] [-Bdir] [-bench] [-Idir] [-Dsym[=val]] [-Usym]\n" " [-Wwarn] [-g] [-b] [-bt N] [-Ldir] [-llib] [-shared] [-static]\n" " [infile1 infile2...] [-run infile args...]\n" diff --git a/tests/Makefile.am b/tests/Makefile.am index 44e2636..fe31489 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -2,6 +2,7 @@ include $(top_srcdir)/Makefile.tool-tests.am dist_noinst_SCRIPTS = \ + check_vmx_cap \ filter_addresses \ filter_discards \ filter_libc \ diff --git a/tests/arch_test.c b/tests/arch_test.c index 68053a1..8c28bc5 100644 --- a/tests/arch_test.c +++ b/tests/arch_test.c @@ -27,6 +27,7 @@ char* all_archs[] = { "amd64", "ppc32", "ppc64", + "arm", NULL }; @@ -55,6 +56,9 @@ static Bool go(char* arch) if ( 0 == strcmp( arch, "ppc32" ) ) return True; } +#elif defined(VGP_arm_linux) + if ( 0 == strcmp( arch, "arm" ) ) return True; + #else # error Unknown platform #endif // VGP_* diff --git a/tests/check_vmx_cap b/tests/check_vmx_cap new file mode 100755 index 0000000..12e5f68 --- /dev/null +++ b/tests/check_vmx_cap @@ -0,0 +1,11 @@ +#!/bin/sh + +# We use this script to check whether or not the processor supports VMX (aka "Altivec"). + +LD_SHOW_AUXV=1 /bin/true | grep altivec > /dev/null 2>&1 +if [ "$?" -ne "0" ]; then + exit 1 +else + exit 0 +fi + diff --git a/tests/filter_stderr_basic b/tests/filter_stderr_basic index 7586958..1537713 100755 --- a/tests/filter_stderr_basic +++ b/tests/filter_stderr_basic @@ -9,8 +9,8 @@ dir=`dirname $0` -# Remove ==pid== and --pid-- and ++pid++ and **pid** strings -perl -p -e 's/(==|--|\+\+|\*\*)[0-9]{1,7}\1 //' | +# Remove ==pid== and --pid-- and **pid** strings +perl -p -e 's/(==|--|\*\*)[0-9]{1,7}\1 //' | # Remove any --pid:0: strings (debuglog level zero output) sed "/^--[0-9]\{1,7\}:0:*/d" | diff --git a/tests/platform_test b/tests/platform_test index 4d57901..22b58d9 100644 --- a/tests/platform_test +++ b/tests/platform_test @@ -12,6 +12,7 @@ all_platforms= all_platforms="$all_platforms x86-linux amd64-linux ppc32-linux ppc64-linux" +all_platforms="$all_platforms arm-linux" all_platforms="$all_platforms ppc32-aix5 ppc64-aix5" all_platforms="$all_platforms x86-darwin amd64-darwin" diff --git a/tests/vg_regtest.in b/tests/vg_regtest.in index 15c53f1..adf3b9a 100755 --- a/tests/vg_regtest.in +++ b/tests/vg_regtest.in @@ -217,7 +217,9 @@ sub read_vgtest_file($) if ($line =~ /^\s*#/ || $line =~ /^\s*$/) { next; } elsif ($line =~ /^\s*vgopts:\s*(.*)$/) { - $vgopts = $vgopts . " " . $1; # Nb: Make sure there's a space! + my $addvgopts = $1; + $addvgopts =~ s/\${PWD}/$ENV{PWD}/g; + $vgopts = $vgopts . " " . $addvgopts; # Nb: Make sure there's a space! } elsif ($line =~ /^\s*prog:\s*(.*)$/) { $prog = validate_program(".", $1, 0, 0); } elsif ($line =~ /^\s*args:\s*(.*)$/) { diff --git a/tests/x86_amd64_features.c b/tests/x86_amd64_features.c index aaa2a55..faad7ae 100644 --- a/tests/x86_amd64_features.c +++ b/tests/x86_amd64_features.c @@ -29,9 +29,23 @@ static void cpuid ( unsigned int n, : "0" (n) /* input */ ); } + +static Bool vendorStringEquals ( char* str ) +{ + char vstr[13]; + unsigned int a, b, c, d; + cpuid(0, &a, &b, &c, &d); + memcpy(&vstr[0], &b, 4); + memcpy(&vstr[4], &d, 4); + memcpy(&vstr[8], &c, 4); + vstr[12] = 0; + return 0 == strcmp(vstr, str); +} + static Bool go(char* cpu) { unsigned int level = 0, cmask = 0, dmask = 0, a, b, c, d; + Bool require_amd = False; if ( strcmp( cpu, "x86-fpu" ) == 0 ) { level = 1; @@ -57,16 +71,27 @@ static Bool go(char* cpu) } else if ( strcmp( cpu, "x86-ssse3" ) == 0 ) { level = 1; cmask = 1 << 9; + } else if ( strcmp( cpu, "x86-lzcnt" ) == 0 ) { + level = 0x80000001; + cmask = 1 << 5; + require_amd = True; #if defined(VGA_amd64) } else if ( strcmp( cpu, "amd64-sse3" ) == 0 ) { level = 1; cmask = 1 << 0; + } else if ( strcmp( cpu, "amd64-pclmulqdq" ) == 0 ) { + level = 1; + cmask = 1 << 1; } else if ( strcmp( cpu, "amd64-ssse3" ) == 0 ) { level = 1; cmask = 1 << 9; } else if ( strcmp( cpu, "amd64-cx16" ) == 0 ) { level = 1; cmask = 1 << 13; + } else if ( strcmp( cpu, "amd64-lzcnt" ) == 0 ) { + level = 0x80000001; + cmask = 1 << 5; + require_amd = True; #endif } else { return 2; // Unrecognised feature. @@ -75,6 +100,10 @@ static Bool go(char* cpu) assert( !(cmask != 0 && dmask != 0) ); assert( !(cmask == 0 && dmask == 0) ); + if (require_amd && !vendorStringEquals("AuthenticAMD")) + return 1; // Feature not present + // regardless of what that feature actually is + cpuid( level & 0x80000000, &a, &b, &c, &d ); if ( a >= level ) { diff --git a/valgrind.pc.in b/valgrind.pc.in index 34a2407..34b3bd1 100644 --- a/valgrind.pc.in +++ b/valgrind.pc.in @@ -11,6 +11,6 @@ Name: Valgrind Description: A dynamic binary instrumentation framework Version: @VERSION@ Requires: -Libs: -L${libdir}/valgrind/@VGCONF_ARCH_PRI@-@VGCONF_OS@ -lcoregrind -lvex -lgcc +Libs: -L${libdir}/valgrind -lcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@ -lvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@ -lgcc Cflags: -I${includedir} diff --git a/vg-in-place b/vg-in-place old mode 100644 new mode 100755 diff --git a/xfree-4.supp b/xfree-4.supp index 94d3dbf..ca566ea 100644 --- a/xfree-4.supp +++ b/xfree-4.supp @@ -33,97 +33,97 @@ Memcheck:Param write(buf) fun:*libc_write - obj:/usr/X11R6/lib*/libX11.so.6.2 + obj:/usr/*lib*/libX11.so* fun:*X11TransWrite } { libX11.so.6.2/libX11.so.6.2/libX11.so.6.2(Cond) Memcheck:Cond - obj:/usr/X11R6/lib*/libX11.so.6.2 - obj:/usr/X11R6/lib*/libX11.so.6.2 - obj:/usr/X11R6/lib*/libX11.so.6.2 + obj:/usr/*lib*/libX11.so* + obj:/usr/*lib*/libX11.so* + obj:/usr/*lib*/libX11.so* } { libXt.so.6.2/libXt.so.6.2/libXt.so.6.2(Cond) Memcheck:Cond - obj:/usr/X11R6/lib*/libXt.so.6.0 - obj:/usr/X11R6/lib*/libXt.so.6.0 - obj:/usr/X11R6/lib*/libXt.so.6.0 + obj:/usr/*lib*/libXt.so* + obj:/usr/*lib*/libXt.so* + obj:/usr/*lib*/libXt.so* } { libXaw.so.7.0/libXaw.so.7.0/libXaw.so.7.0(Cond) Memcheck:Cond - obj:/usr/X11R6/lib*/libXaw.so.7.0 - obj:/usr/X11R6/lib*/libXaw.so.7.0 - obj:/usr/X11R6/lib*/libXaw.so.7.0 + obj:/usr/*lib*/libXaw.so* + obj:/usr/*lib*/libXaw.so* + obj:/usr/*lib*/libXaw.so* } { libXmu.so.6.2/libXmu.so.6.2/libXmu.so.6.2(Cond) Memcheck:Cond - obj:/usr/X11R6/lib*/libXmu.so.6.2 - obj:/usr/X11R6/lib*/libXmu.so.6.2 - obj:/usr/X11R6/lib*/libXmu.so.6.2 + obj:/usr/*lib*/libXmu.so* + obj:/usr/*lib*/libXmu.so* + obj:/usr/*lib*/libXmu.so* } { libXt.so.6.0/libXt.so.6.0/libXaw.so.7.0(Cond) Memcheck:Cond - obj:/usr/X11R6/lib*/libXt.so.6.0 - obj:/usr/X11R6/lib*/libXt.so.6.0 - obj:/usr/X11R6/lib*/libXaw.so.7.0 + obj:/usr/*lib*/libXt.so* + obj:/usr/*lib*/libXt.so* + obj:/usr/*lib*/libXaw.so* } { libXaw.so.7.0/libXaw.so.7.0/libXt.so.6.0(Value4) Memcheck:Value4 - obj:/usr/X11R6/lib*/libXaw.so.7.0 - obj:/usr/X11R6/lib*/libXaw.so.7.0 - obj:/usr/X11R6/lib*/libXt.so.6.0 + obj:/usr/*lib*/libXaw.so* + obj:/usr/*lib*/libXaw.so* + obj:/usr/*lib*/libXt.so* } { libXaw.so.7.0/libXaw.so.7.0/libXt.so.6.0(Cond) Memcheck:Cond - obj:/usr/X11R6/lib*/libXaw.so.7.0 - obj:/usr/X11R6/lib*/libXaw.so.7.0 - obj:/usr/X11R6/lib*/libXt.so.6.0 + obj:/usr/*lib*/libXaw.so* + obj:/usr/*lib*/libXaw.so* + obj:/usr/*lib*/libXt.so* } { libX11.so.6.2/libX11.so.6.2/libXaw.so.7.0(Cond) Memcheck:Cond - obj:/usr/X11R6/lib*/libX11.so.6.2 - obj:/usr/X11R6/lib*/libX11.so.6.2 - obj:/usr/X11R6/lib*/libXaw.so.7.0 + obj:/usr/*lib*/libX11.so* + obj:/usr/*lib*/libX11.so* + obj:/usr/*lib*/libXaw.so* } { libX11.so.6.2/libX11.so.6.2/libXaw.so.7.0(Addr4) Memcheck:Addr4 - obj:/usr/X11R6/lib*/libX11.so.6.2 - obj:/usr/X11R6/lib*/libX11.so.6.2 - obj:/usr/X11R6/lib*/libXaw.so.7.0 + obj:/usr/*lib*/libX11.so* + obj:/usr/*lib*/libX11.so* + obj:/usr/*lib*/libXaw.so* } { libX11.so.6.2/libXaw.so.7.0/libXaw.so.7.0(Cond) Memcheck:Cond - obj:/usr/X11R6/lib*/libX11.so.6.2 - obj:/usr/X11R6/lib*/libXaw.so.7.0 - obj:/usr/X11R6/lib*/libXaw.so.7.0 + obj:/usr/*lib*/libX11.so* + obj:/usr/*lib*/libXaw.so* + obj:/usr/*lib*/libXaw.so* } { libXpm.so.4.11/libXpm.so.4.11/libXpm.so.4.11 Memcheck:Cond - obj:/usr/X11R6/lib*/libXpm.so.4.11 - obj:/usr/X11R6/lib*/libXpm.so.4.11 - obj:/usr/X11R6/lib*/libXpm.so.4.11 + obj:/usr/*lib*/libXpm.so.4.11 + obj:/usr/*lib*/libXpm.so.4.11 + obj:/usr/*lib*/libXpm.so.4.11 } { @@ -175,7 +175,7 @@ write(buf) fun:* fun:_X11TransWrite - obj:/usr/X11R6/lib*/libX11.so.6.2 + obj:/usr/*lib*/libX11.so* } { @@ -184,7 +184,7 @@ write(buf) fun:write fun:_X11TransWrite - obj:/usr/X11R6/lib*/libX11.so.6.2 + obj:/usr/*lib*/libX11.so* } { @@ -202,7 +202,7 @@ Memcheck:Param writev(vector[...]) fun:writev - obj:/usr/X11R6/lib*/libX11.so.6.2 + obj:/usr/*lib*/libX11.so* fun:_X11TransWritev fun:_XSend } @@ -213,7 +213,7 @@ writev(vector[...]) fun:do_writev fun:writev - obj:/usr/X11R6/lib*/libX11.so.6.2 + obj:/usr/*lib*/libX11.so* fun:_X11TransWritev fun:_XSend } @@ -287,6 +287,24 @@ obj:/usr/X11*/lib*/libX11.so* } +# Inlined strlen in libX11 on Ubuntu 9.10 amd64, unfortunately. +# Invalid read of size 4 +# at 0x9B5CCE6: ??? (in /usr/lib/libX11.so.6.2.0) +# by 0x9B5D011: XGetAtomName (in /usr/lib/libX11.so.6.2.0) +# by 0x86407C3: gdk_x11_xatom_to_atom_for_display +# (in /usr/lib/libgdk-x11-2.0.so.0.1800.3) +# by 0x8636817: ??? (in /usr/lib/libgdk-x11-2.0.so.0.1800.3) +# Address 0x1a558e1c is 28 bytes inside a block of size 30 alloc'd +# at 0x4C2552D: malloc (vg_replace_malloc.c:236) +# by 0x9B642C0: _XUpdateAtomCache (in /usr/lib/libX11.so.6.2.0) +# by 0x9B647F1: ??? (in /usr/lib/libX11.so.6.2.0) +# by 0x9B81818: ??? (in /usr/lib/libX11.so.6.2.0) +{ + libX11.so.6.2.0/libX11.so.6.2.0(Addr4) + Memcheck:Addr4 + obj:/usr/*lib*/libX11.so* + obj:/usr/*lib*/libX11.so* +} ##----------------------------------------------------------------------## # Completely inappropriate place, but ...