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GD32F130xxxx clock support #98
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Sure, we can update the SPL. The way these macros are structured in the code, the first activated macro is effect. So in the above example, let's say //#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000)
#define __SYSTEM_CLOCK_48M_PLL_IRC8M_DIV2 (uint32_t)(48000000)
#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) Then 48M_PLL_IRC8M_DIV2 will actually take effect. That was already discovered in some other issue. Meaning that, after the update, you should be able to use build_flags = __SYSTEM_CLOCK_48M_PLL_IRC8M_DIV2=48000000 in the Note that getting easier better clock selection is tracked in #19. |
Thanks for the super-fast reply! The issue is much more than a macro, though. If you follow the new code (attached below as a ZIP), you will see that if that #define in turns executes the following code, which is not present in the SPL in your repository
and
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Yeah the above with "previous definition ovverides last one" is actually wrong here due to the way it's structured differently than what I was working on previously (CommunityGD32Cores/gd32-pio-spl-package#4). The SPL is updated now in 86e0ac7. The default clock source is unmodified with 72MHz PLL from HXTAL. However, I added a build_flags =
-D __PIO_DONT_SET_CLOCK_SOURCE__
-D __SYSTEM_CLOCK_48M_PLL_IRC8M_DIV2=48000000 in the I've tested that to be working on my GD32F130C8. To update, use a PlatformIO core CLI and execute
Per |
Oh, wow, this is great! I really like the PIO_DONT_SET_CLOCK_SOURCE override, thanks again for the amazing turnaround and addressing this. Should I close the issue or will you? Not sure about your project preferences... |
Have you tested this to be working already on your board? Well something is still wrong.. Updating the F1x0 SPL to the newest version.. ..killed all CAN SPL code? F170 and F190 series chips have "CAN" written in their datasheet in the versions I'm looking at. What in the world is going there, I need to investigate this for a moment. |
ARE THEY SERIOUS? They just deleted the datasheets for F170 and F190 that we have a backup copy of.. https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/tree/main/GD32F1x0 Okay, so I guess these chips are not made anymore, noone ever bought them, and they just kill support for it, no backwards compatibility? Crazy, I'll have to write an email about this to Gigadevice. In any case, the underlying problem in this issue should be solved per above. I'll wait for you to test on real hardware to confirm the workings. |
I think we were also confused about inserted adc desappearing from some of the documents but still being in some of the spl examples. Maybe it's a mistake? |
What @Candas1 is referring to, is that in previous GD32F130 reference manuals there was documentation about the inserted ADC functionality (same as the STM32F103 injected mode), but it has been removed completely in newer doc revisions. It's still present in the SPL, but the latest SPL is much older than the latest reference manual. My guess is that GigaDevice discovered issues with the inserted ADC functionality and removed support for it, but didn't update the SPL yet. Or didn't want to guarantee functionality, but it's still in the SPL for people who used it @maxgerhardt if you have a contact in GigaDevice, would be good to ask them about the inserted ADC functionality (registers below have been removed from the documentation V 3.6 https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230209/GD32F1x0_User_Manual_EN_Rev3.6.pdf) #define ADC_ISQ REG32(ADC + 0x00000038U) /*!< ADC inserted sequence register / In the new SPL readme, it's interesting to see the supported chip versions
7 and 9 appeared in 2016, deprecated in the SPL in 2022 |
I didn't immediately find a technical support address but |
Wow. |
Hi, My code is running only if I add this in platformio.ini now
Is it the expected behavior ? Thanks in advance. |
@Candas1 so it was running fine before the update (which was using external crystal + PLL) but now it won't run in the default settings? |
Yes. So now if I run the same program while commenting the build flags, the program is running slower, I am receiving data properly, but the firmware on the other side doesn't like the data I am sending. (SystemCoreClock = 72000000) |
Woops, in the previous version, the clock was actually set from 72MHz from INTERNAL RC + PLL. ArduinoCore-GD32/system/GD32F1x0_firmware/CMSIS/GD/GD32F1x0/Source/system_gd32f1x0.c Lines 45 to 49 in b03bd51
Now the default (no build_flags set) is 72MHz from external crystal. Meaning if your board doesn't have one, the startup of the clock will fail and it'll likely keep its reset clock of 8MHz. Can you quickly manually go into the file (in PlatformIO: We will fix this shortly. |
Or rather, if you don't want to hack around in files, it's commited in 8465b99 now. The defaults should work for internal clock + 72MHz now. |
Oh wow so fast. |
Great, then with the new default being the old default and the possibility of changing the clock source arbitrarily per build flags, I'm considering this done :) |
Thanks a lot |
Hello, I'm working on the SimpleFOC port together with @Candas1 (#95)
The split boards used in many hoverboards use a GD32F130 (C8T6, C6T6 or K6), running at 48MHz and without a crystal oscillator. The SPL files in this repository don't seem to have the proper initialization code for that clock, e.g.
ArduinoCore-GD32/system/GD32F1x0_firmware/CMSIS/GD/GD32F1x0/Source/system_gd32f1x0.c
Line 49 in 2cb8305
I downloaded the latest SPL for the GD32F1x0 processors, version 3.3.4, and the system_gd32f1x0.c file is different and includes the proper #defines and code to initialize the clock at 48MHz using the internal oscillator
Do you plan to update the SPL? if not, what is the best way to use a custom system_gd32f1x0.c file?
Latest SPL for GD32F1x0 is here https://www.gd32mcu.com/download/down/document_id/288/path_type/1
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