From cd758eb9600a1492792923055163d1967c0fcd5b Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Wed, 11 Oct 2017 12:21:02 +0200 Subject: [PATCH] Finished application layer --- application/application.vhd | 95 +++++++++++++ application/application_test.vhd | 102 ++++++++++++++ application/debouncer/debouncer.vhd | 63 +++++++++ application/debouncer/debouncer_test.vhd | 96 +++++++++++++ application/edgedetector/edgedetector.vhd | 69 ++++++++++ .../edgedetector/edgedetector_test.vhd | 95 +++++++++++++ application/segdecoder/segdecoder_test.vhd | 58 ++++++++ application/segdecoder/segedecoder.vhd | 58 ++++++++ application/updowncounter/updowncounter.vhd | 60 ++++++++ .../updowncounter/updowncounter_test.vhd | 100 ++++++++++++++ binToSegDisplay.vhd | 67 --------- binToSegDisplay_test.vhd | 92 ------------- debounce.vhd | 76 ----------- debounce_test.vhd | 128 ------------------ 14 files changed, 796 insertions(+), 363 deletions(-) create mode 100644 application/application.vhd create mode 100644 application/application_test.vhd create mode 100644 application/debouncer/debouncer.vhd create mode 100644 application/debouncer/debouncer_test.vhd create mode 100644 application/edgedetector/edgedetector.vhd create mode 100644 application/edgedetector/edgedetector_test.vhd create mode 100644 application/segdecoder/segdecoder_test.vhd create mode 100644 application/segdecoder/segedecoder.vhd create mode 100644 application/updowncounter/updowncounter.vhd create mode 100644 application/updowncounter/updowncounter_test.vhd delete mode 100644 binToSegDisplay.vhd delete mode 100644 binToSegDisplay_test.vhd delete mode 100644 debounce.vhd delete mode 100644 debounce_test.vhd diff --git a/application/application.vhd b/application/application.vhd new file mode 100644 index 0000000..5542e38 --- /dev/null +++ b/application/application.vhd @@ -0,0 +1,95 @@ +--******************************* +--* TITLE: Application (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 01/10/2017 * +--******************************* +--*************** +--* DESCRIPTION * +--*************** +--1)Purpose: +-- Application layer API. +--2)Principle: +-- Provide an API as application layer +--3)Ingangen: +-- cha, rst, clk, clk_en +--4)Uitgangen: +-- output, display_b +--********************** +--* LIBRARIES & ENTITY * +--********************** +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +ENTITY application IS + PORT + ( + clk : IN std_logic; + clk_en : IN std_logic; + rst : IN std_logic; + up : IN std_logic; + down : IN std_logic; + output : OUT std_logic_vector(3 DOWNTO 0); + display_b : OUT std_logic_vector(6 DOWNTO 0) + ); +END application; +ARCHITECTURE behavior OF application IS + SIGNAL counter_output : std_logic_vector(3 DOWNTO 0); + SIGNAL btn_up_deb_s : std_logic; + SIGNAL btn_down_deb_s : std_logic; + SIGNAL btn_up_edg_s : std_logic; + SIGNAL btn_down_edg_s : std_logic; +BEGIN + output <= counter_output; + decoder : ENTITY work.decoder(behavior) + PORT MAP + ( + bin => counter_output, + disp_b => display_b + ); + edge1 : ENTITY work.edgedetector(behavior) + PORT MAP + ( + data => btn_up_deb_s, + puls => btn_up_edg_s, + clk => clk, + clk_en => clk_en, + rst => rst + ); + edge2 : ENTITY work.edgedetector(behavior) + PORT MAP + ( + data => btn_down_deb_s, + puls => btn_down_edg_s, + clk => clk, + clk_en => clk_en, + rst => rst + ); + debounce1 : ENTITY work.debouncer(behavior) + PORT MAP + ( + clk => clk, + clk_en => clk_en, + rst => rst, + cha => up, + syncha => btn_up_deb_s + ); + debounce2 : ENTITY work.debouncer(behavior) + PORT MAP + ( + clk => clk, + clk_en => clk_en, + rst => rst, + cha => down, + syncha => btn_down_deb_s + ); + counter : ENTITY work.counter(behavior) + PORT MAP + ( + clk => clk, + clk_en => clk_en, + rst => rst, + up => btn_up_edg_s, + down => btn_down_edg_s, + output => counter_output + ); +END behavior; diff --git a/application/application_test.vhd b/application/application_test.vhd new file mode 100644 index 0000000..0023c23 --- /dev/null +++ b/application/application_test.vhd @@ -0,0 +1,102 @@ +--****************************************************************************** +--* TITLE: Application TESTBENCH (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 01/10/2017 * +--****************************************************************************** +--******************** +--* DESCRIPTION * +--******************** +--1)Purpose: +-- TESTBENCH: Application layer API. +--2)Principle: +-- Provide an API as application layer +--3)Ingangen: +-- cha, rst, clk, clk_en +--4)Uitgangen: +-- output, display_b +--*************************** +--* LIBRARIES & ENTITY * +--*************************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.std_logic_arith.ALL; +ENTITY application_test IS +END application_test; +--************************************************** +--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * +--************************************************** +ARCHITECTURE structural OF application_test IS + --initialize signals & constants + CONSTANT period : TIME := 100 ns; + CONSTANT delay : TIME := 10 ns; + SIGNAL end_of_sim : BOOLEAN := false; + SIGNAL clk : std_logic := '0'; + SIGNAL clk_en : std_logic := '1'; + SIGNAL rst : std_logic := '0'; + SIGNAL up : std_logic := '0'; + SIGNAL down : std_logic := '0'; + SIGNAL output : std_logic_vector(3 DOWNTO 0); + SIGNAL display_b : std_logic_vector(6 DOWNTO 0); +BEGIN +--*********** +--* MAPPING * +--*********** +uut : ENTITY work.application(behavior) + PORT MAP + ( + clk => clk, + clk_en => clk_en, + rst => rst, + up => up, + down => down, + output => output, + display_b => display_b + ); +-- Only for synchronous components +clock : PROCESS +BEGIN + clk <= '0'; + WAIT FOR period/2; + LOOP + clk <= '0'; + WAIT FOR period/2; + clk <= '1'; + WAIT FOR period/2; + EXIT WHEN end_of_sim; + END LOOP; + WAIT; + END PROCESS clock; +-- Testbench +tb : PROCESS + -- Reset procedure to initialize the component + PROCEDURE reset IS + BEGIN + rst <= '1'; + WAIT FOR period * 2; + rst <= '0'; + WAIT FOR period; + END reset; + -- Test data procedure + PROCEDURE test (CONSTANT testdata : IN std_logic_vector(1 DOWNTO 0)) IS + BEGIN + up <= testdata(0); + down <= testdata(1); + WAIT FOR period * 5; + END test; +BEGIN + -- Reset at startup + reset; + -- Test data + test("01"); -- up=1, down=0 + test("00"); -- nothing + test("11"); -- nothing + test("10"); -- up=0, down=1 + test("00"); + clk_en <= '0'; -- disable clock + test("10"); + end_of_sim <= true; + WAIT; +END PROCESS; +END; \ No newline at end of file diff --git a/application/debouncer/debouncer.vhd b/application/debouncer/debouncer.vhd new file mode 100644 index 0000000..30f9ed7 --- /dev/null +++ b/application/debouncer/debouncer.vhd @@ -0,0 +1,63 @@ +--******************************* +--* TITLE: Debouncer (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 28/09/2017 * +--******************************* +--*************** +--* DESCRIPTION * +--*************** +--1)Purpose: +-- Debouncing the input buttons. +--2)Principle: +-- When detecting 4 clock cycles the same input, data is valid. +--3)Ingangen: +-- cha, rst, clk +--4)Uitgangen: +-- syncha +--********************** +--* LIBRARIES & ENTITY * +--********************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +ENTITY debouncer IS + PORT + ( + cha, clk, clk_en, rst : IN std_logic; + syncha : OUT std_logic + ); +END debouncer; +--********************************************* +--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * +--********************************************* +ARCHITECTURE behavior OF debouncer IS + SIGNAL reg : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL reg_next : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL sh_ldb : std_logic; +BEGIN +-- output of the shiftreg asigned to syncha (signal -> output) +syncha <= reg(0); +-- exor +sh_ldb <= reg(0) XOR cha; +-- 2-Process: synchronous part +sync_debouncer : PROCESS (clk) +BEGIN + IF (rising_edge(clk) AND clk_en = '1') THEN + IF (rst = '1') THEN -- reset line high, go to initial state + reg <= (OTHERS => '0'); + ELSE -- normal operation + reg <= reg_next; + END IF; + END IF; +END PROCESS sync_debouncer; +-- 2-Process: combinatoric part +comb_debouncer : PROCESS (reg, sh_ldb, cha) +BEGIN + IF (sh_ldb = '1') THEN + reg_next <= cha & reg(3 DOWNTO 1); + ELSE + reg_next <= (OTHERS => reg(0)); + END IF; +END PROCESS comb_debouncer; +END behavior; diff --git a/application/debouncer/debouncer_test.vhd b/application/debouncer/debouncer_test.vhd new file mode 100644 index 0000000..4fe4153 --- /dev/null +++ b/application/debouncer/debouncer_test.vhd @@ -0,0 +1,96 @@ +--****************************************************************************** +--* TITLE: Debouncer TESTBENCH (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 01/10/2017 * +--****************************************************************************** +--******************** +--* DESCRIPTION * +--******************** +--1)Purpose: +-- TESTBENCH: Debouncing the input buttons. +--2)Principle: +-- When detecting 4 clock cycles the same input, data is valid. +--3)Ingangen: +-- cha, rst, clk +--4)Uitgangen: +-- syncha +--*************************** +--* LIBRARIES & ENTITY * +--*************************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.std_logic_arith.ALL; +ENTITY debouncer_test IS +END debouncer_test; +--************************************************** +--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * +--************************************************** +ARCHITECTURE structural OF debouncer_test IS + --initialize signals & constants + CONSTANT period : TIME := 100 ns; + CONSTANT delay : TIME := 10 ns; + SIGNAL end_of_sim : BOOLEAN := false; + SIGNAL clk : std_logic; + SIGNAL clk_en : std_logic := '1'; + SIGNAL rst : std_logic; + SIGNAL cha : std_logic; + SIGNAL syncha : std_logic; +BEGIN +--*********** +--* MAPPING * +--*********** +-- Connect ports to signals (PORT => SIGNAL) +uut : ENTITY work.debouncer(behavior) + PORT MAP + ( + clk => clk, + clk_en => clk_en, + rst => rst, + cha => cha, + syncha => syncha + ); + +-- Only for synchronous components +clock : PROCESS +BEGIN + clk <= '0'; + WAIT FOR period/2; + LOOP + clk <= '0'; + WAIT FOR period/2; + clk <= '1'; + WAIT FOR period/2; + EXIT WHEN end_of_sim; + END LOOP; + WAIT; +END PROCESS clock; +-- Testbench +tb : PROCESS + -- Reset procedure to initialize the component + PROCEDURE reset IS + BEGIN + rst <= '1'; + WAIT FOR period * 2; + rst <= '0'; + WAIT FOR period; + END reset; + -- Test data procedure + PROCEDURE test (CONSTANT testdata : IN std_logic) IS + BEGIN + cha <= testdata; + WAIT FOR period * 4; + END test; +BEGIN + -- Reset at startup + reset; + -- Test data + test('0'); + test('1'); + test('0'); + test('1'); + end_of_sim <= true; + WAIT; +END PROCESS; +END; diff --git a/application/edgedetector/edgedetector.vhd b/application/edgedetector/edgedetector.vhd new file mode 100644 index 0000000..919fec1 --- /dev/null +++ b/application/edgedetector/edgedetector.vhd @@ -0,0 +1,69 @@ +--****************************************************************************** +--* TITLE: Edgedetector FSM (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 05/10/2017 * +--****************************************************************************** +--******************** +--* DESCRIPTION * +--******************** +--1)Purpose: +-- Check if a signal goes from LOW to HIGH +--2)Principle: +-- Moore FSM +--3)Inputs: +-- data, clk, clk_en, rst +--4)Outputs: +-- puls +--*************************** +--* LIBRARIES & ENTITY * +--*************************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +ENTITY edgedetector IS + PORT + ( + data, clk, clk_en, rst : IN std_logic; + puls : OUT std_logic + ); +END edgedetector; +--************************************************** +--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * +--************************************************** +ARCHITECTURE behavior OF edgedetector IS + TYPE state IS (s0, s1, s2); + SIGNAL present_state, next_state : state; +BEGIN +-- 2-Process: synchronous part +sync_moore : PROCESS (clk) +BEGIN + IF (rising_edge(clk) AND clk_en = '1') THEN + IF (rst = '1') THEN -- reset line high, go to initial state + present_state <= s0; + ELSE -- normal operation + present_state <= next_state; + END IF; + END IF; +END PROCESS sync_moore; +-- 2-Process: combinatoric part +comb_moore : PROCESS (present_state, data) +BEGIN + CASE present_state IS + WHEN s0 => puls <= '0'; -- Initial state + IF (data = '1') THEN -- data high, send puls + next_state <= s1; + ELSE + next_state <= s0; + END IF; + WHEN s1 => puls <= '1'; -- Send puls out (high) + next_state <= s2; + WHEN s2 => puls <= '0'; -- After 1 CLK cycle, puls low + IF (data = '0') THEN -- data low, go to initial state + next_state <= s0; + ELSE + next_state <= s2; + END IF; + END CASE; +END PROCESS comb_moore; +END behavior; \ No newline at end of file diff --git a/application/edgedetector/edgedetector_test.vhd b/application/edgedetector/edgedetector_test.vhd new file mode 100644 index 0000000..8a115e6 --- /dev/null +++ b/application/edgedetector/edgedetector_test.vhd @@ -0,0 +1,95 @@ +--****************************************************************************** +--* TITLE: Edgedetector FSM TESTBENCH (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 05/10/2017 * +--****************************************************************************** +--******************** +--* DESCRIPTION * +--******************** +--1)Purpose: +-- Check if a signal goes from LOW to HIGH +--2)Principle: +-- Moore FSM +--3)Inputs: +-- data, clk, clk_en, rst +--4)Outputs: +-- puls +--*************************** +--* LIBRARIES & ENTITY * +--*************************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +ENTITY edgedetector_test IS +END edgedetector_test; +--************************************************** +--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * +--************************************************** +ARCHITECTURE structural OF edgedetector_test IS + --initialize signals & constants + CONSTANT period : TIME := 100 ns; + CONSTANT delay : TIME := 10 ns; + SIGNAL end_of_sim : BOOLEAN := false; + SIGNAL data : std_logic; + SIGNAL clk : std_logic; + SIGNAL clk_en : std_logic := '1'; + SIGNAL rst : std_logic; + SIGNAL puls : std_logic; +BEGIN +--*********** +--* MAPPING * +--*********** +-- Connect ports to signals (PORT => SIGNAL) +uut : ENTITY work.edgedetector(behavior) + PORT MAP + ( + data => data, + puls => puls, + clk => clk, + clk_en => clk_en, + rst => rst + ); + +-- Only for synchronous components +clock : PROCESS + BEGIN + clk <= '0'; + WAIT FOR period/2; + LOOP + clk <= '0'; + WAIT FOR period/2; + clk <= '1'; + WAIT FOR period/2; + EXIT WHEN end_of_sim; + END LOOP; + WAIT; +END PROCESS clock; +-- Testbench +PROCESS + -- Reset procedure to initialize the component + PROCEDURE reset IS + BEGIN + rst <= '1'; + WAIT FOR period * 2; + rst <= '0'; + WAIT FOR period; + END reset; + -- Test data procedure + PROCEDURE test (CONSTANT testdata : IN std_logic) IS + BEGIN + data <= testdata; + WAIT FOR period * 4; + END test; +BEGIN + -- Reset at startup + reset; + -- Test data + test('0'); + test('1'); + test('0'); + test('1'); + end_of_sim <= true; + WAIT; +END PROCESS; +END structural; diff --git a/application/segdecoder/segdecoder_test.vhd b/application/segdecoder/segdecoder_test.vhd new file mode 100644 index 0000000..a953214 --- /dev/null +++ b/application/segdecoder/segdecoder_test.vhd @@ -0,0 +1,58 @@ +--****************************************************************************** +--* TITLE: Binary-To-7-Segment-Display decoder TESTBENCH (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 01/10/2017 * +--****************************************************************************** +--******************** +--* DESCRIPTION * +--******************** +--1)Purpose: +-- TESTBENCH: Convert a 4 bit STD_LOGIC_VECTOR to a 7 segment display output (active low) +--2)Principle: +-- Switch statement converts the binary data to HEX values which are understand by the 7 segment display +--3)Inputs: +-- bin +--4)Outputs: +-- disp_b +--*************************** +--* LIBRARIES & ENTITY * +--*************************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.std_logic_arith.ALL; +ENTITY decoder_test IS +END decoder_test; +ARCHITECTURE structural OF decoder_test IS + --************************************************** + --* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * + --************************************************** + -- Initialize signals & constants + CONSTANT period : TIME := 100 ns; + CONSTANT delay : TIME := 10 ns; + SIGNAL end_of_sim : BOOLEAN := false; + SIGNAL bin : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL disp_b : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); +BEGIN +--*********** +--* MAPPING * +--*********** +uut : ENTITY work.decoder(behavior) + PORT MAP + ( + bin => bin, + disp_b => disp_b + ); + +-- Testbench +tb : PROCESS +BEGIN + FOR i IN 0 TO 15 LOOP + bin <= CONV_STD_LOGIC_VECTOR(i, 4); + WAIT FOR period; + END LOOP; + end_of_sim <= true; + WAIT; +END PROCESS; +END; diff --git a/application/segdecoder/segedecoder.vhd b/application/segdecoder/segedecoder.vhd new file mode 100644 index 0000000..8591249 --- /dev/null +++ b/application/segdecoder/segedecoder.vhd @@ -0,0 +1,58 @@ +--******************************************************* +--* TITLE: Binary-To-7-Segment-Display decoder (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 01/10/2017 * +--******************************************************* +--*************** +--* DESCRIPTION * +--*************** +--1)Purpose: +-- Convert a 4 bit STD_LOGIC_VECTOR to a 7 segment display output (active low) +--2)Principle: +-- Switch statement converts the binary data to HEX values which are understand by the 7 segment display +--3)Inputs: +-- bin +--4)Outputs: +-- disp_b +--********************** +--* LIBRARIES & ENTITY * +--********************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +ENTITY decoder IS + PORT + ( + bin : IN std_logic_vector(3 DOWNTO 0); + disp_b : OUT std_logic_vector(6 DOWNTO 0) + ); +END decoder; +--********************************************* +--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * +--********************************************* +ARCHITECTURE behavior OF decoder IS +BEGIN +decode : PROCESS (bin) +BEGIN + CASE bin IS + WHEN "0000" => disp_b <= "0000001"; -- '0' + WHEN "0001" => disp_b <= "1001111"; -- '1' + WHEN "0010" => disp_b <= "0010010"; -- '2' + WHEN "0011" => disp_b <= "0000110"; -- '3' + WHEN "0100" => disp_b <= "1001100"; -- '4' + WHEN "0101" => disp_b <= "0100100"; -- '5' + WHEN "0110" => disp_b <= "0100000"; -- '6' + WHEN "0111" => disp_b <= "0001111"; -- '7' + WHEN "1000" => disp_b <= "0000000"; -- '8' + WHEN "1001" => disp_b <= "0000100"; -- '9' + WHEN "1010" => disp_b <= "0000010"; -- 'A' + WHEN "1011" => disp_b <= "1100000"; -- 'B' + WHEN "1100" => disp_b <= "0110001"; -- 'C' + WHEN "1101" => disp_b <= "1000010"; -- 'D' + WHEN "1110" => disp_b <= "0010000"; -- 'E' + WHEN "1111" => disp_b <= "0111000"; -- 'F' + WHEN OTHERS => disp_b <= "0000000"; + END CASE; +END PROCESS decode; +END behavior; diff --git a/application/updowncounter/updowncounter.vhd b/application/updowncounter/updowncounter.vhd new file mode 100644 index 0000000..b943a77 --- /dev/null +++ b/application/updowncounter/updowncounter.vhd @@ -0,0 +1,60 @@ +--******************************* +--* TITLE: Counter (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 01/10/2017 * +--******************************* +--* DESCRIPTION * +--*************** +--1)Purpose: +-- Counting up/down +--2)Principle: +-- When up or down input is high, count +--3)Ingangen: +-- up, down, rst, clk, clk_en +--4)Uitgangen: +-- output +--********************** +--* LIBRARIES & ENTITY * +--********************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +ENTITY counter IS + PORT + ( + clk, clk_en, rst, up, down : IN std_logic; + output : OUT std_logic_vector(3 DOWNTO 0) + ); + SIGNAL n_count : std_logic_vector(3 DOWNTO 0); + SIGNAL p_count : std_logic_vector(3 DOWNTO 0); +END; +--********************************************* +--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * +--********************************************* +ARCHITECTURE behavior OF counter IS +BEGIN + output <= p_count; + -- 2-Process: synchronous part + count_sync : PROCESS (clk) + BEGIN + IF (rising_edge(clk) AND clk_en = '1') THEN + IF (rst = '1') THEN -- rst line high, go to initial state + p_count <= (OTHERS => '0'); + ELSE -- normal operation + p_count <= n_count; + END IF; + END IF; + END PROCESS count_sync; + -- 2-Process: combinatoric part + count_comb : PROCESS (p_count, up, down) + BEGIN + IF up = '1' AND down = '0' THEN -- count up + n_count <= p_count + 1; + ELSIF down = '1' AND up = '0' THEN -- count down + n_count <= p_count - 1; + ELSE + n_count <= p_count; -- halt + END IF; + END PROCESS count_comb; +END behavior; \ No newline at end of file diff --git a/application/updowncounter/updowncounter_test.vhd b/application/updowncounter/updowncounter_test.vhd new file mode 100644 index 0000000..6de8dac --- /dev/null +++ b/application/updowncounter/updowncounter_test.vhd @@ -0,0 +1,100 @@ +--*************************************** +--* TITLE: Counter TESTBENCH (sender) * +--* TYPE: Component * +--* AUTHOR: Dylan Van Assche * +--* DATE: 01/10/2017 * +--*************************************** +--*************** +--* DESCRIPTION * +--*************** +--1)Purpose: +-- TESTBENCH: Counting up/down +--2)Principle: +-- When up or down input is high, count +--3)Ingangen: +-- up, down, rst, clk, clk_en +--4)Uitgangen: +-- output +--********************** +--* LIBRARIES & ENTITY * +--********************** +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.std_logic_arith.ALL; +ENTITY counter_test IS +END counter_test; +--********************************************* +--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * +--********************************************* +ARCHITECTURE structural OF counter_test IS + --initialize signals & constants + CONSTANT period : TIME := 100 ns; + CONSTANT delay : TIME := 10 ns; + SIGNAL end_of_sim : BOOLEAN := false; + SIGNAL clk : std_logic := '0'; + SIGNAL clk_en : std_logic := '1'; + SIGNAL rst : std_logic := '0'; + SIGNAL up : std_logic := '0'; + SIGNAL down : std_logic := '0'; + SIGNAL output : std_logic_vector(3 DOWNTO 0); +BEGIN +--*********** +--* MAPPING * +--*********** +uut : ENTITY work.counter(behavior) + PORT MAP + ( + clk => clk, + clk_en => clk_en, + rst => rst, + up => up, + down => down, + output => output + ); +-- Only for synchronous components +clock : PROCESS +BEGIN + clk <= '0'; + WAIT FOR period/2; + LOOP + clk <= '0'; + WAIT FOR period/2; + clk <= '1'; + WAIT FOR period/2; + EXIT WHEN end_of_sim; + END LOOP; + WAIT; +END PROCESS clock; +-- Testbench +tb : PROCESS + -- Reset procedure to initialize the component + PROCEDURE reset IS + BEGIN + rst <= '1'; + WAIT FOR period * 2; + rst <= '0'; + WAIT FOR period; + END reset; + -- Test data procedure + PROCEDURE test (CONSTANT testdata : IN std_logic_vector(1 DOWNTO 0)) IS + BEGIN + up <= testdata(0); + down <= testdata(1); + WAIT FOR period * 5; + END test; +BEGIN + -- Reset at startup + reset; + -- Test data + test("01"); -- up=1, down=0 + test("00"); -- nothing + test("11"); -- nothing + test("10"); -- up=0, down=1 + test("00"); + clk_en <= '0'; -- disable clock + test("10"); + end_of_sim <= true; + WAIT; +END PROCESS; +END; diff --git a/binToSegDisplay.vhd b/binToSegDisplay.vhd deleted file mode 100644 index c57c7ce..0000000 --- a/binToSegDisplay.vhd +++ /dev/null @@ -1,67 +0,0 @@ ---****************************************************************************** ---* TITLE: Binary-To-7-Segment-Display decoder (sender) * ---* TYPE: Component * ---* AUTHOR: Dylan Van Assche * ---* DATE: 01/10/2017 * ---****************************************************************************** - ---******************** ---* DESCRIPTION * ---******************** ---1)Purpose: --- Convert a 4 bit STD_LOGIC_VECTOR to a 7 segment display output (active low) ---2)Principle: --- Switch statement converts the binary data to HEX values which are understand by the 7 segment display ---3)Inputs: --- bin ---4)Outputs: --- disp_b - ---*************************** ---* LIBRARIES & ENTITY * ---*************************** -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.ALL; - -ENTITY decoder IS - PORT ( - bin : IN std_logic_vector(3 DOWNTO 0); - disp_b : OUT std_logic_vector(6 DOWNTO 0) - ); -END decoder; - ---************************************************** ---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * ---************************************************** - -ARCHITECTURE behavior OF decoder IS -BEGIN - ---******************* ---* STATEMENTS * ---******************* - -decode : PROCESS(bin) - BEGIN - CASE bin IS - WHEN "0000" => disp_b <= "0000001"; -- '0' - WHEN "0001" => disp_b <= "1001111"; -- '1' - WHEN "0010" => disp_b <= "0010010"; -- '2' - WHEN "0011" => disp_b <= "0000110"; -- '3' - WHEN "0100" => disp_b <= "1001100"; -- '4' - WHEN "0101" => disp_b <= "0100100"; -- '5' - WHEN "0110" => disp_b <= "0100000"; -- '6' - WHEN "0111" => disp_b <= "0001111"; -- '7' - WHEN "1000" => disp_b <= "0000000"; -- '8' - WHEN "1001" => disp_b <= "0000100"; -- '9' - WHEN "1010" => disp_b <= "0000010"; -- 'A' - WHEN "1011" => disp_b <= "1100000"; -- 'B' - WHEN "1100" => disp_b <= "0110001"; -- 'C' - WHEN "1101" => disp_b <= "1000010"; -- 'D' - WHEN "1110" => disp_b <= "0010000"; -- 'E' - WHEN "1111" => disp_b <= "0111000"; -- 'F' - WHEN OTHERS => disp_b <= "0000000"; - END CASE; -END PROCESS decode; -END behavior; \ No newline at end of file diff --git a/binToSegDisplay_test.vhd b/binToSegDisplay_test.vhd deleted file mode 100644 index 43f7726..0000000 --- a/binToSegDisplay_test.vhd +++ /dev/null @@ -1,92 +0,0 @@ ---****************************************************************************** ---* TITLE: Binary-To-7-Segment-Display decoder TESTBENCH (sender) * ---* TYPE: Component * ---* AUTHOR: Dylan Van Assche * ---* DATE: 01/10/2017 * ---****************************************************************************** - ---******************** ---* DESCRIPTION * ---******************** ---1)Purpose: --- TESTBENCH: Convert a 4 bit STD_LOGIC_VECTOR to a 7 segment display output (active low) ---2)Principle: --- Switch statement converts the binary data to HEX values which are understand by the 7 segment display ---3)Inputs: --- bin ---4)Outputs: --- disp_b - ---*************************** ---* LIBRARIES & ENTITY * ---*************************** -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.ALL; -USE ieee.std_logic_arith.ALL; - - -ENTITY decoder_test IS -END decoder_test; - -ARCHITECTURE structural OF decoder_test IS - -COMPONENT decoder -PORT ( - bin: IN std_logic_vector(3 DOWNTO 0); - disp_b: OUT std_logic_vector(6 DOWNTO 0) - ); -END COMPONENT; - ---************************************************** ---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * ---************************************************** -FOR uut : decoder USE ENTITY work.decoder(behavior); - --- Initialize signals & constants -CONSTANT period : time := 100 ns; -CONSTANT delay : time := 10 ns; -SIGNAL end_of_sim : boolean := false; - -SIGNAL bin: std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); -SIGNAL disp_b: std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); - -BEGIN - ---**************** ---* MAPPING * ---**************** -uut: decoder PORT MAP( - bin => bin, - disp_b => disp_b -); - ---******************* ---* STATEMENTS * ---******************* --- Only for synchronous components ---clock : PROCESS ---BEGIN --- clk <= '0'; --- WAIT FOR period/2; --- LOOP --- clk <= '0'; --- WAIT FOR period/2; --- clk <= '1'; --- WAIT FOR period/2; --- EXIT WHEN end_of_sim; --- END LOOP; --- WAIT; ---END PROCESS clock; - --- Testbench -tb : PROCESS -BEGIN - FOR i IN 0 TO 15 LOOP - bin <= CONV_STD_LOGIC_VECTOR(i,4); - WAIT FOR period; - END LOOP; - end_of_sim <= true; - WAIT; -END PROCESS; -END; \ No newline at end of file diff --git a/debounce.vhd b/debounce.vhd deleted file mode 100644 index c6da8e0..0000000 --- a/debounce.vhd +++ /dev/null @@ -1,76 +0,0 @@ ---****************************************************************************** ---* TITLE: Debouncer (sender) * ---* TYPE: Component * ---* AUTHOR: Dylan Van Assche * ---* DATE: 28/09/2017 * ---****************************************************************************** - ---******************** ---* DESCRIPTION * ---******************** ---1)Purpose: --- Debouncing the input buttons. ---2)Principle: --- When detecting 4 clock cycles the same input, data is valid. ---3)Ingangen: --- cha, rst, clk ---4)Uitgangen: --- syncha - ---*************************** ---* LIBRARIES & ENTITY * ---*************************** -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.ALL; - -ENTITY debouncer IS -PORT ( - cha, clk, clk_en, rst: IN std_logic; - syncha : OUT std_logic -); -END debouncer; - ---************************************************** ---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * ---************************************************** - -ARCHITECTURE behavior OF debouncer IS - SIGNAL reg: std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); - SIGNAL reg_next: std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); - SIGNAL sh_ldb: std_logic; -BEGIN - ---******************* ---* STATEMENTS * ---******************* - ---output of the shiftreg asigned to syncha (signal -> output) -syncha <= reg(0); - ---exor -sh_ldb <= reg(0) XOR cha; - - --- 2-Process: synchronous part -sync_debouncer : PROCESS(clk) -BEGIN - IF (rising_edge(clk) AND clk_en = '1') THEN - IF (rst = '1') THEN -- reset line high, go to initial state - reg <= (OTHERS => '0'); - ELSE -- normal operation - reg <= reg_next; - END IF; - END IF; -END PROCESS sync_debouncer; - --- 2-Process: combinatoric part -comb_debouncer : PROCESS(reg, sh_ldb, cha) -BEGIN - IF(sh_ldb = '1') THEN - reg_next <= cha & reg(3 DOWNTO 1); - ELSE - reg_next <= (OTHERS => reg(0)); - END IF; -END PROCESS comb_debouncer; -END behavior; diff --git a/debounce_test.vhd b/debounce_test.vhd deleted file mode 100644 index 211a581..0000000 --- a/debounce_test.vhd +++ /dev/null @@ -1,128 +0,0 @@ ---****************************************************************************** ---* TITLE: Debouncer TESTBENCH (sender) * ---* TYPE: Component * ---* AUTHOR: Dylan Van Assche * ---* DATE: 01/10/2017 * ---****************************************************************************** - ---******************** ---* DESCRIPTION * ---******************** ---1)Purpose: --- TESTBENCH: Debouncing the input buttons. ---2)Principle: --- When detecting 4 clock cycles the same input, data is valid. ---3)Ingangen: --- cha, rst, clk ---4)Uitgangen: --- syncha - ---*************************** ---* LIBRARIES & ENTITY * ---*************************** -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.ALL; -USE ieee.std_logic_arith.ALL; - - -ENTITY debouncer_test IS -END debouncer_test; - -ARCHITECTURE structural OF debouncer_test IS - -COMPONENT debouncer -PORT ( - cha, clk, clk_en, rst: IN std_logic; - syncha : OUT std_logic -); -END COMPONENT; - ---************************************************** ---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS * ---************************************************** -FOR uut : debouncer USE ENTITY work.debouncer(behavior); - ---initialize signals & constants -CONSTANT period : time := 100 ns; -CONSTANT delay : time := 10 ns; -SIGNAL end_of_sim : boolean := false; - -SIGNAL clk: std_logic := '0'; -SIGNAL clk_en: std_logic := '0'; -SIGNAL rst: std_logic := '0'; -SIGNAL cha: std_logic := '0'; -SIGNAL syncha: std_logic := '0'; - -BEGIN - ---**************** ---* MAPPING * ---**************** -uut: debouncer PORT MAP( - clk => clk, - clk_en => clk_en, - rst => rst, - cha => cha, - syncha => syncha -); - ---******************* ---* STATEMENTS * ---******************* --- Only for synchronous components -clock : PROCESS -BEGIN - clk <= '0'; - WAIT FOR period/2; - LOOP - clk <= '0'; - WAIT FOR period/2; - clk <= '1'; - WAIT FOR period/2; - EXIT WHEN end_of_sim; - END LOOP; - WAIT; -END PROCESS clock; - --- Testbench -tb : PROCESS -BEGIN - -- 4 CLK cycles '0': expected result '0' - clk_en <= '1'; - cha <= '0'; - WAIT FOR period*4; - - -- 4 CLK cycles '1': expected result '1' - clk_en <= '1'; - cha <= '1'; - WAIT FOR period*4; - - -- 1 CLK cycle '0': expected result '0' - clk_en <= '1'; - cha <= '0'; - WAIT FOR period; - - -- 3 CLK cycles '1': expected result '0' - clk_en <= '1'; - cha <= '0'; - WAIT FOR period*3; - - -- 10 CLK cycles '0': expected result '0' - clk_en <= '1'; - cha <= '0'; - WAIT FOR period*10; - - -- 5 CLK cycles '1': expected result '0' - clk_en <= '0'; - cha <= '1'; - WAIT FOR period*5; - - -- 2 CLK cycles '0': expected result '0' - cha <= '0'; - WAIT FOR period*2; - - end_of_sim <= true; - WAIT; -END PROCESS; -END; \ No newline at end of file