First to create FPGA image to N310 failed

[mioway]

Issue Description

WARNING: [Synth 8-3331] design mig_7series_v4_2_ddr_w_upsizer has unconnected port cmd_offset[3]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ddr_w_upsizer has unconnected port cmd_offset[2]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ddr_w_upsizer has unconnected port cmd_offset[1]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ddr_w_upsizer has unconnected port cmd_offset[0]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ddr_w_upsizer has unconnected port cmd_step[5]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ddr_w_upsizer has unconnected port S_AXI_WUSER[0]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ddr_a_upsizer has unconnected port S_AXI_AUSER[0]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ui_rd_data has unconnected port ecc_multiple[7]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ui_rd_data has unconnected port ecc_multiple[6]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ui_rd_data has unconnected port ecc_multiple[5]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ui_rd_data has unconnected port ecc_multiple[4]
WARNING: [Synth 8-3331] design mig_7series_v4_2_ui_rd_data has unconnected port ecc_multiple[3]
[00:00:38] Current task: Synthesis +++ Current Phase: Starting
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/linux-02/user/uhd-UHD-4.0/fpga/usrp3/top/n3xx/build-ip/xc7z035ffg900-2/ddr3_32bit/ddr3_32bit/user_design/constraints/ddr3_32bit.xdc:545]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/linux-02/user/uhd-UHD-4.0/fpga/usrp3/top/n3xx/build-ip/xc7z035ffg900-2/ddr3_32bit/ddr3_32bit/user_design/constraints/ddr3_32bit.xdc:552]
[00:01:16] Current task: Synthesis +++ Current Phase: Handling Custom Attributes
[00:01:16] Current task: Synthesis +++ Current Phase: RTL Component Statistics
[00:01:17] Current task: Synthesis +++ Current Phase: RTL Hierarchical Component Statistics
[00:02:33] Current task: Synthesis +++ Current Phase: Part Resource Summary
[00:02:33] Current task: Synthesis +++ Current Phase: Finished
[00:02:33] Process terminated. Status: Failure

========================================================
Warnings: 317
Critical Warnings: 0
Errors: 0

[00:02:35] Current task: Synthesis +++ Current Phase: FinishedBUILDER: Releasing IP location: /home/linux-02/user/uhd-UHD-4.0/fpga/usrp3/top/n3xx/build-ip/xc7z035ffg900-2/ddr3_32bit
/home/linux-02/user/uhd-UHD-4.0/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc:15: recipe for target '/home/linux-02/user/uhd-UHD-4.0/fpga/usrp3/top/n3xx/build-ip/xc7z035ffg900-2/ddr3_32bit/ddr3_32bit.xci' failed
make[1]: *** [/home/linux-02/user/uhd-UHD-4.0/fpga/usrp3/top/n3xx/build-ip/xc7z035ffg900-2/ddr3_32bit/ddr3_32bit.xci] Error 1
make[1]: Leaving directory '/home/linux-02/user/uhd-UHD-4.0/fpga/usrp3/top/n3xx'
Makefile:128: recipe for target 'N300_HA' failed
make: *** [N300_HA] Error 2

Setup Details

Expected Behavior

Actual Behaviour

Steps to reproduce the problem

Additional Information

linux version: ubuntu18.04
vivado version :2019.1

[mbr0wn]

Hi @mioway, it's not clear if there's a bug or a local build issue (your logs don't contain any errors). I'm going to close this, as this bug tracker is for bugs, and not for support requests. Try the mailing list instead. This is our boilerplate page for support requests: https://www.ettus.com/support/