Double assign on wires

[Pasca133]

Hey,
I am currently using icestudio for "writing" verilog code but I need the design unoptimized by the synthesis. So I exported the verilog file and the constraint file and imported them into icecube2, added " /* synthesis syn_keep=1 */" to all the wires so nothing gets optimized in the synthesis but then the synthesis failed.
I recognized that icestudio makes double assign on wires, which is fine if the synthesis is run normally but its, in my mind, certainly not what you want ideally.
For example I had following lines:
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;

the synthesis fails because of double input to a single input wire. Took me a few minutes to find it.
Also it would be great if there were any settings to check a box for a non optimized synthesis so it wouldn't be so much work to edit all these lines in the verilog file.