vivado_19848.backup.log

#-----------------------------------------------------------
# Vivado v2022.1 (64-bit)
# SW Build 3526262 on Mon Apr 18 15:48:16 MDT 2022
# IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
# Start of session at: Mon Apr 29 21:56:49 2024
# Process ID: 19848
# Current directory: E:/Accelerator/Accelerator_100M
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent5656 E:\Accelerator\Accelerator_100M\Accelerator.xpr
# Log file: E:/Accelerator/Accelerator_100M/vivado.log
# Journal file: E:/Accelerator/Accelerator_100M\vivado.jou
# Running On: DESKTOP-JO2RAF5, OS: Windows, CPU Frequency: 2496 MHz, CPU Physical cores: 4, Host memory: 17041 MB
#-----------------------------------------------------------
start_gui
open_project E:/Accelerator/Accelerator_100M/Accelerator.xpr
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at F:/Xilinx/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory 'E:/Accelerator/ip_repo/Accelerator_Control_1.0'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'F:/Xilinx/Vivado/2022.1/data/ip'.
open_project: Time (s): cpu = 00:00:31 ; elapsed = 00:00:17 . Memory (MB): peak = 1746.750 ; gain = 0.000
update_compile_order -fileset sources_1
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
CRITICAL WARNING: [HDL 9-1206] Syntax error near ')' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v:4]
update_compile_order -fileset sources_1
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Reading block design file <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd>...
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_data_fifo:2.1 - s00_data_fifo
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_1
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_result
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_picture_window
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_weight
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_weight_full
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - RESULT_DATA_FIFO1
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - WEIGHT_FULLCON_FIFO
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - WEIGHT_CONV_ACT_FULLCON_FIFO
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - INACT_DATA_FIFO
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - PICTURE_DATA_FIFO
Adding component instance block -- xilinx.com:module_ref:Windows_Data_Convert_v1_0:1.0 - Windows_Data_Convert_0
Adding component instance block -- xilinx.com:module_ref:CNN_Control:1.0 - CNN_Control_1
Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - axi_intc_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Successfully read diagram <Accelerator_block_design> from block design file <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd>
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
upgrade_ip: Time (s): cpu = 00:00:16 ; elapsed = 00:00:12 . Memory (MB): peak = 1746.750 ; gain = 0.000
update_module_reference: Time (s): cpu = 00:00:16 ; elapsed = 00:00:12 . Memory (MB): peak = 1746.750 ; gain = 0.000
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
startgroup
set_property -dict [list CONFIG.KERNEL_SIZE {5}] [get_bd_cells CNN_ACCELERATOR/Windows_Data_Convert_0]
endgroup
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
update_compile_order -fileset sources_1
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
startgroup
set_property -dict [list CONFIG.CONV_KERNEL_SIZE {5} CONFIG.CONV_KERNEL_NUM {12} CONFIG.POOL_KERNEL_SIZE {2} CONFIG.FULLCON_OUTPUT_SIZE {10}] [get_bd_cells CNN_ACCELERATOR/CNN_Control_1]
endgroup
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
WARNING: [IP_Flow 19-4706] Upgraded port 'result_tdata' width 384 differs from original width 160
WARNING: [IP_Flow 19-4706] Upgraded port 'result_tkeep' width 48 differs from original width 20
WARNING: [IP_Flow 19-4706] Upgraded port 'result_tstrb' width 48 differs from original width 20
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'Accelerator_block_design_CNN_Control_1_0'. These changes may impact your design.
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'Accelerator_block_design_CNN_Control_1_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
startgroup
endgroup
startgroup
set_property -dict [list CONFIG.TDATA_NUM_BYTES {48}] [get_bd_cells CNN_ACCELERATOR/RESULT_DATA_FIFO1]
endgroup
startgroup
set_property -dict [list CONFIG.RESULT_NUM {8} CONFIG.CONV_KERNEL_NUM {8} CONFIG.FULLCON_OUTPUT_SIZE {8}] [get_bd_cells CNN_ACCELERATOR/CNN_Control_1]
endgroup
startgroup
set_property -dict [list CONFIG.TDATA_NUM_BYTES {32}] [get_bd_cells CNN_ACCELERATOR/RESULT_DATA_FIFO1]
endgroup
startgroup
set_property -dict [list CONFIG.TDATA_NUM_BYTES {25}] [get_bd_cells CNN_ACCELERATOR/INACT_DATA_FIFO]
endgroup
startgroup
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_cells CNN_ACCELERATOR/WEIGHT_CONV_ACT_FULLCON_FIFO]
endgroup
startgroup
set_property -dict [list CONFIG.TDATA_NUM_BYTES {8}] [get_bd_cells CNN_ACCELERATOR/WEIGHT_FULLCON_FIFO]
endgroup
startgroup
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] [get_bd_cells axi_dma_weight_full]
endgroup
startgroup
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] [get_bd_cells axi_dma_weight]
endgroup
set_property CONFIG.FREQ_HZ 50000000 [get_bd_intf_pins /CNN_ACCELERATOR/CNN_Control_1/image]
set_property CONFIG.FREQ_HZ 50000000 [get_bd_intf_pins /CNN_ACCELERATOR/CNN_Control_1/weight]
set_property CONFIG.FREQ_HZ 50000000 [get_bd_intf_pins /CNN_ACCELERATOR/CNN_Control_1/weightfc]
validate_bd_design
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to any ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. 
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_S_AXI_ACLK_FREQ_MHZ(100.0) on '/axi_intc_0' with propagated value(50.0). Command ignored
WARNING: [xilinx.com:ip:axi_intc:4.1-7] /axi_intc_0: Interrupts type manual value (0xFFFFFFFF) does not match computed value (0xFFFFFFF0). Please review the manual value or consider using Auto instead.
validate_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1845.566 ; gain = 14.559
set_property -dict [list CONFIG.TDATA_NUM_BYTES {32}] [get_ips fifo_result]
generate_target all [get_files  E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/fifo_result/fifo_result.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_result'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_result'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_result'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_result'...
catch { config_ip_cache -export [get_ips -all fifo_result] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP fifo_result, cache-ID = 8152b3865422d742; cache size = 1297.775 MB.
export_ip_user_files -of_objects [get_files E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/fifo_result/fifo_result.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/fifo_result/fifo_result.xci]
INFO: [Vivado 12-3453] The given sub-design is up-to-date, no action was taken.  If a run is still desired, use the '-force' option for the file:'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/fifo_result/fifo_result.xci'
export_simulation -of_objects [get_files E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/fifo_result/fifo_result.xci] -directory E:/Accelerator/Accelerator_100M/Accelerator.ip_user_files/sim_scripts -ip_user_files_dir E:/Accelerator/Accelerator_100M/Accelerator.ip_user_files -ipstatic_source_dir E:/Accelerator/Accelerator_100M/Accelerator.ip_user_files/ipstatic -lib_map_path [list {modelsim=E:/Accelerator/Accelerator_100M/Accelerator.cache/compile_simlib/modelsim} {questa=E:/Accelerator/Accelerator_100M/Accelerator.cache/compile_simlib/questa} {riviera=E:/Accelerator/Accelerator_100M/Accelerator.cache/compile_simlib/riviera} {activehdl=E:/Accelerator/Accelerator_100M/Accelerator.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
save_bd_design
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
INFO: [Vivado 12-5457] ref source:E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci
generate_target Simulation [get_files E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci]
INFO: [IP_Flow 19-1706] Not generating 'Simulation' target for IP 'div_gen_0'. Target already exists and is up to date.
launch_simulation
Command: launch_simulation 
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'F:/Xilinx/Vivado/2022.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'F:/Xilinx/Vivado/2022.1/data/xsim/xsim.ini' copied to run dir:'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'CNN_Accelerator_system_Test' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:585]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:606]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:611]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:615]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:633]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:639]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:643]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:651]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:656]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:659]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:665]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:669]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:675]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
ERROR: [VRFC 10-2989] 'Data_width' is not declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v:34]
ERROR: [VRFC 10-8530] module 'Relu' is ignored due to previous errors [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v:21]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1907.898 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '5' seconds
INFO: [USF-XSim-99] Step results log file:'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim/xvlog.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1907.898 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
INFO: [Vivado 12-5457] ref source:E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci
generate_target Simulation [get_files E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci]
INFO: [IP_Flow 19-1706] Not generating 'Simulation' target for IP 'div_gen_0'. Target already exists and is up to date.
launch_simulation
Command: launch_simulation 
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'F:/Xilinx/Vivado/2022.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'F:/Xilinx/Vivado/2022.1/data/xsim/xsim.ini' copied to run dir:'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'CNN_Accelerator_system_Test' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:585]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:606]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:611]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:615]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:633]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:639]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:643]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:651]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:656]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:659]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:665]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:669]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:675]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 1971.363 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '10' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 's_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:163]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:166]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:167]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 'm_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:169]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 64 differs from formal bit length 128 for port 'weight_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:321]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 128 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=3,DATA_HORIZ...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=16)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1971.363 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '16' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "CNN_Accelerator_system_Test_behav -key {Behavioral:sim_1:Functional:CNN_Accelerator_system_Test} -tclbatch {CNN_Accelerator_system_Test.tcl} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/window_tb/window_tb_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/cnn/CNN_Accelerator_tb_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/conv/conv_tb_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/window_tb/windows_data_axi_test_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/CNN_System_tb/CNN_Accelerator_system_Test_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/relu_tb/Relu_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/window_tb/window_tb_behav.wcfg
WARNING: Simulation object /conv_tb/convtb/clk was not found in the design.
WARNING: Simulation object /conv_tb/convtb/rstn was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/\Vertical[3].Horizontal[0].wire_outWtPs  was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/\Vertical[3].Horizontal[1].wire_outWtPs  was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/\Vertical[3].Horizontal[2].wire_outWtPs  was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/\Vertical[3].Horizontal[3].wire_outWtPs  was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/reg_outWtPs[3] was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Sum_valid was not found in the design.
WARNING: Simulation object /conv_tb/convtb/io_outSum was not found in the design.
WARNING: Simulation object /conv_tb/convtb/start was not found in the design.
WARNING: Simulation object /conv_tb/convtb/state was not found in the design.
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/cnn/CNN_Accelerator_tb_behav.wcfg
WARNING: Simulation object /pool_tb/clk was not found in the design.
WARNING: Simulation object /pool_tb/rst_n was not found in the design.
WARNING: Simulation object /pool_tb/io_Max_MeanValid was not found in the design.
WARNING: Simulation object /pool_tb/io_inAct_0 was not found in the design.
WARNING: Simulation object /pool_tb/io_inAct_1 was not found in the design.
WARNING: Simulation object /pool_tb/io_inAct_2 was not found in the design.
WARNING: Simulation object /pool_tb/io_inAct_3 was not found in the design.
WARNING: Simulation object /pool_tb/io_outSum_0 was not found in the design.
WARNING: Simulation object /pool_tb/valid was not found in the design.
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/conv/conv_tb_behav.wcfg
WARNING: Simulation object /conv_tb/clk was not found in the design.
WARNING: Simulation object /conv_tb/rst_n was not found in the design.
WARNING: Simulation object /conv_tb/io_inAct_0 was not found in the design.
WARNING: Simulation object /conv_tb/io_inAct_1 was not found in the design.
WARNING: Simulation object /conv_tb/io_inAct_2 was not found in the design.
WARNING: Simulation object /conv_tb/io_inAct_3 was not found in the design.
WARNING: Simulation object /conv_tb/io_inWeight_0 was not found in the design.
WARNING: Simulation object /conv_tb/io_inWeight_1 was not found in the design.
WARNING: Simulation object /conv_tb/io_inWeight_2 was not found in the design.
WARNING: Simulation object /conv_tb/io_inWeight_3 was not found in the design.
WARNING: Simulation object /conv_tb/io_outSum_0 was not found in the design.
WARNING: Simulation object /conv_tb/io_outSum_1 was not found in the design.
WARNING: Simulation object /conv_tb/io_outSum_2 was not found in the design.
WARNING: Simulation object /conv_tb/io_outSum_3 was not found in the design.
WARNING: Simulation object /conv_tb/Sum_valid was not found in the design.
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/window_tb/windows_data_axi_test_behav.wcfg
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_aclk was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_aresetn was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tready was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tdata was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tstrb was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tlast was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tvalid was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_aclk was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_aresetn was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tvalid was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tdata was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tstrb was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tkeep was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tlast was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tready was not found in the design.
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/CNN_System_tb/CNN_Accelerator_system_Test_behav.wcfg
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/relu_tb/Relu_tb_behav.wcfg
WARNING: Simulation object /Relu_tb/relu_inst/din was not found in the design.
WARNING: Simulation object /Relu_tb/relu_inst/ivalid was not found in the design.
WARNING: Simulation object /Relu_tb/relu_inst/ovalid was not found in the design.
WARNING: Simulation object /Relu_tb/relu_inst/dout was not found in the design.
source CNN_Accelerator_system_Test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_127  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_182  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_659  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_716  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_773  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weightfc read over
weight read over
xsim: Time (s): cpu = 00:00:18 ; elapsed = 00:00:07 . Memory (MB): peak = 2382.676 ; gain = 411.312
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CNN_Accelerator_system_Test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 2382.676 ; gain = 411.312
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Start_Control}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_State}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Act}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Weight}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Act_Ready}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Weight_Ready}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Refresh}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Outsum}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Outsum_Valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/FULLCON_Finish}} 
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/clk}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/rstn}} 
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/result_tready}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/result_tvalid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/result_tlast}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/result_tdata}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/cnn_done}} 
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'F:/Xilinx/Vivado/2022.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'F:/Xilinx/Vivado/2022.1/data/xsim/xsim.ini' copied to run dir:'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'CNN_Accelerator_system_Test' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:585]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:606]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:611]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:615]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:633]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:639]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:643]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:651]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:656]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:659]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:665]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:669]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:675]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:11 . Memory (MB): peak = 2382.676 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:15 . Memory (MB): peak = 2382.676 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 's_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:163]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:166]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:167]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 'm_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:169]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 64 differs from formal bit length 128 for port 'weight_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:321]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 128 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=3,DATA_HORIZ...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=16)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 2382.676 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '13' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:14 . Memory (MB): peak = 2382.676 ; gain = 0.000
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_127  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_182  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_659  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_716  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_773  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weightfc read over
weight read over
relaunch_sim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:32 . Memory (MB): peak = 2382.676 ; gain = 0.000
run all
weight read over
weight read over
weight read over
weight read over
weight read over
weight read over
weight read over
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:585]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:606]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:611]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:615]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:633]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:639]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:643]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:651]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:656]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:659]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:665]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:669]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:675]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:11 . Memory (MB): peak = 2384.207 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:15 . Memory (MB): peak = 2384.207 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 's_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:163]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:166]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:167]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 'm_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:169]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 'image_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:314]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=3,DATA_HORIZ...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2384.207 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '13' seconds
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 2384.207 ; gain = 0.000
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_127  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_182  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_740  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_797  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_854  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weightfc read over
weight read over
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:32 . Memory (MB): peak = 2384.207 ; gain = 0.000
run all
weight read over
weight read over
weight read over
weight read over
weight read over
weight read over
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-8956] extra semicolon is not allowed here in this dialect; use SystemVerilog mode instead [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:570]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:614]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:650]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:655]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:658]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:664]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:668]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:672]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:674]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2391.379 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 2391.379 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 's_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:163]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:166]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:167]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 'm_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:169]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 'image_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:314]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=3,DATA_HORIZ...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:14 . Memory (MB): peak = 2404.711 ; gain = 13.332
INFO: [USF-XSim-69] 'elaborate' step finished in '13' seconds
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:15 . Memory (MB): peak = 2404.711 ; gain = 13.332
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_127  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_182  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_740  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_797  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_854  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:32 . Memory (MB): peak = 2404.711 ; gain = 13.332
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_State}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Act}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Weight}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Start_Control}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Load_Act}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Image_Ready}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Weight_Ready}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Refresh}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Outsum}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Outsum_Valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_Finish}} 
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_In_Valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_Act}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_Only_Act}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_Valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_Only_Valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_Refresh}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_Outsum}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_Outsum_Valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/RELU_Finish}} 
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-8956] extra semicolon is not allowed here in this dialect; use SystemVerilog mode instead [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:570]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:614]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:650]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:655]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:658]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:664]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:668]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:672]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:674]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2404.711 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 2404.711 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 's_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:163]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:166]
WARNING: [VRFC 10-3091] actual bit length 9 differs from formal bit length 25 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:167]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 'm_axis_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:169]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 72 differs from formal bit length 200 for port 'image_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:314]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=3,DATA_HORIZ...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 2404.711 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '13' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:14 . Memory (MB): peak = 2404.711 ; gain = 0.000
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_127  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_182  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_740  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_797  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_854  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:28 . Memory (MB): peak = 2404.711 ; gain = 0.000
run all
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-8956] extra semicolon is not allowed here in this dialect; use SystemVerilog mode instead [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:570]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:614]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:650]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:655]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:658]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:664]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:668]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:672]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:674]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2407.406 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 2407.406 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 2419.617 ; gain = 12.211
INFO: [USF-XSim-69] 'elaborate' step finished in '16' seconds
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:17 . Memory (MB): peak = 2419.617 ; gain = 12.211
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2419.617 ; gain = 12.211
run all
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-8956] extra semicolon is not allowed here in this dialect; use SystemVerilog mode instead [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:570]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:614]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:650]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:655]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:658]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:664]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:668]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:672]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:674]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:13 . Memory (MB): peak = 2436.371 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '13' seconds
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:18 . Memory (MB): peak = 2436.371 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 2444.223 ; gain = 7.852
INFO: [USF-XSim-69] 'elaborate' step finished in '15' seconds
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2444.223 ; gain = 7.852
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:36 . Memory (MB): peak = 2444.223 ; gain = 7.852
run all
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:582]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:603]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:608]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:613]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:630]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:636]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:640]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:649]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:654]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:657]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:663]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:667]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:671]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:11 . Memory (MB): peak = 2457.160 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 2457.160 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:15 . Memory (MB): peak = 2457.160 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '15' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 2457.160 ; gain = 0.000
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 2482.926 ; gain = 25.766
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_00/Sum_valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_00/reg_Sum_valid}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_00/reg_Sum_valid1}} 
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:582]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:603]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:608]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:613]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:630]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:636]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:640]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:649]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:654]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:657]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:663]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:667]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:671]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:11 . Memory (MB): peak = 2482.926 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 2482.926 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:16 . Memory (MB): peak = 2482.926 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '15' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 2482.926 ; gain = 0.000
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 2510.352 ; gain = 27.426
run all
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_00/act_done}} 
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_00/state}} 
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_00/wait_pipeline_acttransfer_counter}} {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_00/wait_pipeline_outtransfer_counter}} 
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:582]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:603]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:608]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:613]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:630]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:636]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:640]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:649]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:654]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:657]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:663]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:667]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:671]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2514.137 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 2514.137 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:15 . Memory (MB): peak = 2514.137 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '15' seconds
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:16 . Memory (MB): peak = 2514.137 ; gain = 0.000
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 2538.809 ; gain = 24.672
run all
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/image_tlast}} 
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/CNN_Accelerator_00/CONV_State}} 
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:582]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:603]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:608]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:613]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:630]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:636]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:640]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:649]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:654]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:657]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:663]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:667]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:671]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 2553.480 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '13' seconds
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:14 . Memory (MB): peak = 2553.480 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 2565.758 ; gain = 12.277
INFO: [USF-XSim-69] 'elaborate' step finished in '16' seconds
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:17 . Memory (MB): peak = 2565.758 ; gain = 12.277
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:32 . Memory (MB): peak = 2565.758 ; gain = 12.277
run all
current_wave_config {Relu_tb_behav.wcfg}
Relu_tb_behav.wcfg
add_wave {{/CNN_Accelerator_system_Test/test_aix_windows/m00_axis_tdata}} {{/CNN_Accelerator_system_Test/test_aix_windows/m00_axis_tstrb}} {{/CNN_Accelerator_system_Test/test_aix_windows/m00_axis_tkeep}} {{/CNN_Accelerator_system_Test/test_aix_windows/m00_axis_tlast}} {{/CNN_Accelerator_system_Test/test_aix_windows/m00_axis_tready}} 
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 2599.004 ; gain = 24.668
run all
set_property -dict [list CONFIG.FIFO_DEPTH {1024}] [get_ips axis_data_fifo_0]
generate_target all [get_files  E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/axis_data_fifo_0/axis_data_fifo_0.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axis_data_fifo_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axis_data_fifo_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axis_data_fifo_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axis_data_fifo_0'...
catch { config_ip_cache -export [get_ips -all axis_data_fifo_0] }
export_ip_user_files -of_objects [get_files E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/axis_data_fifo_0/axis_data_fifo_0.xci] -no_script -sync -force -quiet
reset_run axis_data_fifo_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory E:/Accelerator/Accelerator_100M/Accelerator.runs/axis_data_fifo_0_synth_1

launch_runs axis_data_fifo_0_synth_1 -jobs 8
[Mon Apr 29 23:36:26 2024] Launched axis_data_fifo_0_synth_1...
Run output will be captured here: E:/Accelerator/Accelerator_100M/Accelerator.runs/axis_data_fifo_0_synth_1/runme.log
export_simulation -of_objects [get_files E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/axis_data_fifo_0/axis_data_fifo_0.xci] -directory E:/Accelerator/Accelerator_100M/Accelerator.ip_user_files/sim_scripts -ip_user_files_dir E:/Accelerator/Accelerator_100M/Accelerator.ip_user_files -ipstatic_source_dir E:/Accelerator/Accelerator_100M/Accelerator.ip_user_files/ipstatic -lib_map_path [list {modelsim=E:/Accelerator/Accelerator_100M/Accelerator.cache/compile_simlib/modelsim} {questa=E:/Accelerator/Accelerator_100M/Accelerator.cache/compile_simlib/questa} {riviera=E:/Accelerator/Accelerator_100M/Accelerator.cache/compile_simlib/riviera} {activehdl=E:/Accelerator/Accelerator_100M/Accelerator.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim/simulate.log"
INFO: [Common 17-17] undo 'relaunch_sim'
INFO: [Common 17-17] undo 'relaunch_sim'
ERROR: [Common 17-69] Command failed: boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim/simulate.log"
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim/simulate.log"
INFO: [Common 17-17] undo 'relaunch_sim'
INFO: [Common 17-17] undo 'relaunch_sim'
ERROR: [Common 17-69] Command failed: boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim/simulate.log"
save_wave_config {E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/relu_tb/Relu_tb_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
INFO: [Vivado 12-5457] ref source:E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci
generate_target Simulation [get_files E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci]
INFO: [IP_Flow 19-1706] Not generating 'Simulation' target for IP 'div_gen_0'. Target already exists and is up to date.
launch_simulation
Command: launch_simulation 
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'F:/Xilinx/Vivado/2022.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'F:/Xilinx/Vivado/2022.1/data/xsim/xsim.ini' copied to run dir:'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'CNN_Accelerator_system_Test' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:582]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:603]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:608]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:613]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:630]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:636]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:640]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:649]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:654]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:657]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:663]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:667]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:671]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2668.484 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '12' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=1024,TD...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 2668.484 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '15' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "CNN_Accelerator_system_Test_behav -key {Behavioral:sim_1:Functional:CNN_Accelerator_system_Test} -tclbatch {CNN_Accelerator_system_Test.tcl} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/window_tb/window_tb_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/cnn/CNN_Accelerator_tb_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/conv/conv_tb_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/window_tb/windows_data_axi_test_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/CNN_System_tb/CNN_Accelerator_system_Test_behav.wcfg} -view {E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/relu_tb/Relu_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/window_tb/window_tb_behav.wcfg
WARNING: Simulation object /conv_tb/convtb/clk was not found in the design.
WARNING: Simulation object /conv_tb/convtb/rstn was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/\Vertical[3].Horizontal[0].wire_outWtPs  was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/\Vertical[3].Horizontal[1].wire_outWtPs  was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/\Vertical[3].Horizontal[2].wire_outWtPs  was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/\Vertical[3].Horizontal[3].wire_outWtPs  was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Conv_Array_0/reg_outWtPs[3] was not found in the design.
WARNING: Simulation object /conv_tb/convtb/Sum_valid was not found in the design.
WARNING: Simulation object /conv_tb/convtb/io_outSum was not found in the design.
WARNING: Simulation object /conv_tb/convtb/start was not found in the design.
WARNING: Simulation object /conv_tb/convtb/state was not found in the design.
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/cnn/CNN_Accelerator_tb_behav.wcfg
WARNING: Simulation object /pool_tb/clk was not found in the design.
WARNING: Simulation object /pool_tb/rst_n was not found in the design.
WARNING: Simulation object /pool_tb/io_Max_MeanValid was not found in the design.
WARNING: Simulation object /pool_tb/io_inAct_0 was not found in the design.
WARNING: Simulation object /pool_tb/io_inAct_1 was not found in the design.
WARNING: Simulation object /pool_tb/io_inAct_2 was not found in the design.
WARNING: Simulation object /pool_tb/io_inAct_3 was not found in the design.
WARNING: Simulation object /pool_tb/io_outSum_0 was not found in the design.
WARNING: Simulation object /pool_tb/valid was not found in the design.
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/conv/conv_tb_behav.wcfg
WARNING: Simulation object /conv_tb/clk was not found in the design.
WARNING: Simulation object /conv_tb/rst_n was not found in the design.
WARNING: Simulation object /conv_tb/io_inAct_0 was not found in the design.
WARNING: Simulation object /conv_tb/io_inAct_1 was not found in the design.
WARNING: Simulation object /conv_tb/io_inAct_2 was not found in the design.
WARNING: Simulation object /conv_tb/io_inAct_3 was not found in the design.
WARNING: Simulation object /conv_tb/io_inWeight_0 was not found in the design.
WARNING: Simulation object /conv_tb/io_inWeight_1 was not found in the design.
WARNING: Simulation object /conv_tb/io_inWeight_2 was not found in the design.
WARNING: Simulation object /conv_tb/io_inWeight_3 was not found in the design.
WARNING: Simulation object /conv_tb/io_outSum_0 was not found in the design.
WARNING: Simulation object /conv_tb/io_outSum_1 was not found in the design.
WARNING: Simulation object /conv_tb/io_outSum_2 was not found in the design.
WARNING: Simulation object /conv_tb/io_outSum_3 was not found in the design.
WARNING: Simulation object /conv_tb/Sum_valid was not found in the design.
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/behav/window_tb/windows_data_axi_test_behav.wcfg
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_aclk was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_aresetn was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tready was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tdata was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tstrb was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tlast was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/s00_axis_tvalid was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_aclk was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_aresetn was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tvalid was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tdata was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tstrb was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tkeep was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tlast was not found in the design.
WARNING: Simulation object /axis_windows_tb/test_aix_windows/m00_axis_tready was not found in the design.
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/imports/CNN_System_tb/CNN_Accelerator_system_Test_behav.wcfg
open_wave_config E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/relu_tb/Relu_tb_behav.wcfg
source CNN_Accelerator_system_Test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
xsim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2668.484 ; gain = 0.000
INFO: [USF-XSim-96] XSim completed. Design snapshot 'CNN_Accelerator_system_Test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:18 ; elapsed = 00:00:45 . Memory (MB): peak = 2668.484 ; gain = 0.000
run all
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:351]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:355]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:358]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:362]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:373]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:377]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:379]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:385]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:388]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:394]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:398]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:401]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:440]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:446]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:456]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:463]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:467]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:469]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:472]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:489]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:493]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:496]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:505]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:508]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:510]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:513]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:522]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:526]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:528]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:582]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:603]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:608]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:613]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:630]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:636]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:640]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:649]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:654]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:657]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:663]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:667]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:671]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:673]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2668.484 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '13' seconds
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 2668.484 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:417]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=1024,TD...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 2668.484 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '15' seconds
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2668.484 ; gain = 0.000
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
weight read over
relaunch_sim: Time (s): cpu = 00:00:07 ; elapsed = 00:00:36 . Memory (MB): peak = 2668.484 ; gain = 0.000
run all
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:348]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:353]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:357]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:360]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:364]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:374]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:378]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:380]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:386]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:389]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:395]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:399]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:402]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:442]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:447]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:457]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:465]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:468]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:470]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:473]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:490]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:494]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:497]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:506]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:509]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:511]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:514]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:523]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:527]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:529]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:614]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:650]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:655]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:658]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:664]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:668]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:672]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:674]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2672.398 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2672.398 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:418]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=1024,TD...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 2677.273 ; gain = 4.875
INFO: [USF-XSim-69] 'elaborate' step finished in '16' seconds
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 2677.273 ; gain = 4.875
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
relaunch_sim: Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2677.273 ; gain = 4.875
run all
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_12 -L processing_system7_vip_v1_0_14 -L xilinx_vip -prj CNN_Accelerator_system_Test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_result/sim/fifo_result.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_result
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weightfc/sim/fifo_weightfc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weightfc
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/fifo_weight/sim/fifo_weight.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_weight
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/picture_fifo_0/sim/picture_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module picture_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/ip/axis_data_fifo_0/sim/axis_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axis_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator
WARNING: [VRFC 10-2938] 'CONV_Load_Act' is already implicitly declared on line 197 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:302]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:149]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:154]
WARNING: [VRFC 10-3380] identifier 'CONV_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:157]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:167]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:171]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:173]
WARNING: [VRFC 10-3380] identifier 'CONV_State' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:197]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:208]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:210]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:211]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:212]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:226]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:236]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:237]
WARNING: [VRFC 10-3380] identifier 'CONV_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:241]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:242]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:251]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:259]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:263]
WARNING: [VRFC 10-3380] identifier 'CONV_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:264]
WARNING: [VRFC 10-3380] identifier 'CONV_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:268]
WARNING: [VRFC 10-3380] identifier 'CONV_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:269]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:289]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:293]
WARNING: [VRFC 10-3380] identifier 'CONV_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:295]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:310]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:312]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:345]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:346]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:347]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:348]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:352]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:353]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:356]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:357]
WARNING: [VRFC 10-3380] identifier 'RELU_Only_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:359]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:360]
WARNING: [VRFC 10-3380] identifier 'RELU_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:363]
WARNING: [VRFC 10-3380] identifier 'RELU_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:364]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:374]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:378]
WARNING: [VRFC 10-3380] identifier 'RELU_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:380]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:386]
WARNING: [VRFC 10-3380] identifier 'RELU_In_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:389]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:395]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:399]
WARNING: [VRFC 10-3380] identifier 'RELU_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:402]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:441]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:442]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:447]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:457]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:464]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:465]
WARNING: [VRFC 10-3380] identifier 'POOL_Image_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:468]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:470]
WARNING: [VRFC 10-3380] identifier 'POOL_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:473]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:490]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:494]
WARNING: [VRFC 10-3380] identifier 'POOL_Max_MeanValid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:497]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:506]
WARNING: [VRFC 10-3380] identifier 'POOL_Start_Control' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:509]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:511]
WARNING: [VRFC 10-3380] identifier 'POOL_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:514]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:523]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:527]
WARNING: [VRFC 10-3380] identifier 'POOL_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:529]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:583]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:584]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:604]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:605]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:609]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight_Ready' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:610]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Finish' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:614]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:631]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:632]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:637]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:638]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Act' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:641]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Weight' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:642]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:650]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:655]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:658]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:664]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:668]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:672]
WARNING: [VRFC 10-3380] identifier 'FULLCON_Refresh' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:674]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Conv_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Conv_SystolicArray
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/FullCon_PE_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FullCon_PE_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pool_PE.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pool_PE
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_Array_Control
WARNING: [VRFC 10-3380] identifier 'Pool_out_valid' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_Array_Control.v:67]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Pooling_SystolicArray
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Pooling_SystolicArray.v:59]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/Relu_Array_Control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Relu_Array_Control
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_M00_AXIS
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_M00_AXIS.v:66]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S00_AXIS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S00_AXIS
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/Windows_Data_Convert_v1_0_S01_AXI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Windows_Data_Convert_v1_0_S01_AXI
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module windows
WARNING: [VRFC 10-2938] 'divider_out_valid' is already implicitly declared on line 112 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:115]
WARNING: [VRFC 10-8332] begin/end is required for generate-for in this mode of Verilog [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/imports/window_ip/windows.v:167]
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module CNN_Accelerator_system_Test
WARNING: [VRFC 10-2938] 'mlast' is already implicitly declared on line 145 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:150]
WARNING: [VRFC 10-2938] 'mready' is already implicitly declared on line 146 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:151]
WARNING: [VRFC 10-2938] 'mvalid' is already implicitly declared on line 141 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:152]
WARNING: [VRFC 10-2938] 'mstrb' is already implicitly declared on line 143 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:153]
WARNING: [VRFC 10-2938] 'mkeep' is already implicitly declared on line 144 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:154]
WARNING: [VRFC 10-2938] 'moutdata' is already implicitly declared on line 142 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:155]
WARNING: [VRFC 10-2938] 'plast' is already implicitly declared on line 135 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:179]
WARNING: [VRFC 10-2938] 'pready' is already implicitly declared on line 132 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:180]
WARNING: [VRFC 10-2938] 'pvalid' is already implicitly declared on line 136 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:181]
WARNING: [VRFC 10-3248] data object 'mstrb' is already declared [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-9364] second declaration of 'mstrb' is ignored [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:183]
WARNING: [VRFC 10-2938] 'pdata' is already implicitly declared on line 133 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:184]
WARNING: [VRFC 10-2938] 'm1_axis_tdata' is already implicitly declared on line 321 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:349]
WARNING: [VRFC 10-2938] 'm1_axis_tlast' is already implicitly declared on line 319 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:350]
WARNING: [VRFC 10-2938] 'm1_axis_tready' is already implicitly declared on line 320 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:351]
WARNING: [VRFC 10-2938] 'm1_axis_tvalid' is already implicitly declared on line 318 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:352]
WARNING: [VRFC 10-2938] 'm2_axis_tdata' is already implicitly declared on line 328 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:461]
WARNING: [VRFC 10-2938] 'm2_axis_tlast' is already implicitly declared on line 326 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:462]
WARNING: [VRFC 10-2938] 'm2_axis_tready' is already implicitly declared on line 327 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:463]
WARNING: [VRFC 10-2938] 'm2_axis_tvalid' is already implicitly declared on line 325 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:464]
WARNING: [VRFC 10-2938] 's3_axis_tdata' is already implicitly declared on line 334 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:538]
WARNING: [VRFC 10-2938] 's3_axis_tlast' is already implicitly declared on line 337 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:539]
WARNING: [VRFC 10-2938] 's3_axis_tready' is already implicitly declared on line 332 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:540]
WARNING: [VRFC 10-2938] 's3_axis_tvalid' is already implicitly declared on line 333 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:541]
WARNING: [VRFC 10-2938] 's3_axis_tstrb' is already implicitly declared on line 336 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:542]
WARNING: [VRFC 10-2938] 's3_axis_tkeep' is already implicitly declared on line 335 [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:543]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:205]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:238]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:248]
WARNING: [VRFC 10-3380] identifier 'fp_2' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:259]
WARNING: [VRFC 10-3380] identifier 'fp_1' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:376]
WARNING: [VRFC 10-3380] identifier 'fp_3' is used before its declaration [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:377]
"xvhdl --incr --relax -prj CNN_Accelerator_system_Test_vhdl.prj"
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 2687.840 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2687.840 ; gain = 0.000
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'CNN_Accelerator_system_Test'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Accelerator/Accelerator_100M/Accelerator.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: F:/Xilinx/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_8 -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_0_20 -L xbip_dsp48_mult_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L div_gen_v5_1_19 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot CNN_Accelerator_system_Test_behav xil_defaultlib.CNN_Accelerator_system_Test xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-2861] module 'Relu_Array_Control' does not have a parameter named Data_width [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/new/CNN_Accelerator.v:418]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:304]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Conv_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:305]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:306]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'Pool_Kernel_Num' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:307]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Input_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:308]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'FULLCON_Output_Size' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:309]
WARNING: [VRFC 10-3091] actual bit length 80 differs from formal bit length 64 for port 'weightfc_tdata' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:328]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:335]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 'result_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:336]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tstrb' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:558]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 32 for port 's_axis_tkeep' [E:/Accelerator/Accelerator_100M/Accelerator.srcs/sim_1/new/CNN_Accelerator_system_Test.v:559]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package div_gen_v5_1_19.div_gen_v5_1_19_viv_comp
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package ieee.math_real
Compiling package axi_utils_v2_0_6.global_util_pkg
Compiling package axi_utils_v2_0_6.axi_utils_comps
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package xbip_bram18k_v3_0_6.xbip_bram18k_v3_0_6_pkg
Compiling package div_gen_v5_1_19.div_gen_pkg
Compiling package ieee.std_logic_signed
Compiling package unisim.vcomponents
Compiling package div_gen_v5_1_19.pkg_addsub
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S01_AX...
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_registered=1)(1,0)(1,...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=8,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_ainit_val="00000001",...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=8)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_ain...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=7)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=6)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=5)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=4)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=3)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_width=2)...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(1,1)(1,1)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_sinit_va...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture rtl of entity div_gen_v5_1_19.c_addsub_lut6 [\c_addsub_lut6(c_width=9,c_add_m...]
Compiling architecture synth of entity div_gen_v5_1_19.c_addsub_viv [\c_addsub_viv(c_a_width=9,c_b_wi...]
Compiling architecture virtex of entity div_gen_v5_1_19.addsubreg_v [\addsubreg_v(c_bus_width=9,c_has...]
Compiling architecture virtex of entity div_gen_v5_1_19.dividervdc_v [\dividervdc_v(bus_num=8,bus_div=...]
Compiling architecture synth of entity div_gen_v5_1_19.c_twos_comp_viv [\c_twos_comp_viv(c_width=9,c_ain...]
Compiling architecture virtex of entity div_gen_v5_1_19.cmp2s_v [\cmp2s_v(c_bus_width=9)(1,0)(1,0...]
Compiling architecture synth of entity div_gen_v5_1_19.bip_sdivider_synth [\bip_sdivider_synth(c_xdevicefam...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_synth [\div_gen_synth(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_latency=...]
Compiling architecture synth of entity div_gen_v5_1_19.div_gen_v5_1_19_viv [\div_gen_v5_1_19_viv(c_xdevicefa...]
Compiling architecture xilinx of entity div_gen_v5_1_19.div_gen_v5_1_19 [\div_gen_v5_1_19(c_xdevicefamily...]
Compiling architecture div_gen_0_arch of entity xil_defaultlib.div_gen_0 [div_gen_0_default]
Compiling module xil_defaultlib.windows(KERNEL_SIZE=5,STRIDE=2)
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_S00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0_M00_AX...
Compiling module xil_defaultlib.Windows_Data_Convert_v1_0(KERNEL...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=1...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=1024,TD...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.axis_data_fifo_0
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=9...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=2...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=256,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.picture_fifo_0
Compiling module xil_defaultlib.Conv_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.Conv_SystolicArray(CONV_KERNEL_S...
Compiling module xil_defaultlib.Conv_Array_Control(PARA_WIDTH=8,...
Compiling module xil_defaultlib.Relu
Compiling module xil_defaultlib.Relu_Array_Control(Relu_Num=8)
Compiling module xil_defaultlib.Pool_PE
Compiling module xil_defaultlib.Pooling_SystolicArray(DATA_WIDTH...
Compiling module xil_defaultlib.Pooling_Array_Control(POOL_KERNE...
Compiling module xil_defaultlib.FullCon_PE(DATA_WIDTH=8)
Compiling module xil_defaultlib.FullCon_PE_Control(DATA_WIDTH=8,...
Compiling module xil_defaultlib.CNN_Accelerator(RESULT_NUM=8,CON...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weight
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_weightfc
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=5...
Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=512,TDA...
Compiling module axis_data_fifo_v2_0_8.axis_data_fifo_v2_0_8_top(C_FAMI...
Compiling module xil_defaultlib.fifo_result
Compiling module xil_defaultlib.CNN_Accelerator_system_Test
Compiling module xil_defaultlib.glbl
Built simulation snapshot CNN_Accelerator_system_Test_behav
run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2706.055 ; gain = 18.215
INFO: [USF-XSim-69] 'elaborate' step finished in '16' seconds
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:18 . Memory (MB): peak = 2706.055 ; gain = 18.215
Time resolution is 1 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_act/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_261  Scope: CNN_Accelerator_system_Test.fifo_act.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_316  Scope: CNN_Accelerator_system_Test.fifo0.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weight_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_874  Scope: CNN_Accelerator_system_Test.fifo_weight_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_weightfc_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_931  Scope: CNN_Accelerator_system_Test.fifo_weightfc_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps  Iteration: 0  Process: /CNN_Accelerator_system_Test/fifo_result_1/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial299_988  Scope: CNN_Accelerator_system_Test.fifo_result_1.inst.\gen_fifo.xpm_fifo_axis_inst .xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc  File: F:/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 493
relaunch_sim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:36 . Memory (MB): peak = 2706.055 ; gain = 18.215
run all
close_sim
INFO: [Simtcl 6-16] Simulation closed
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
update_module_reference {Accelerator_block_design_Windows_Data_Convert_0_5 Windows_data_Test_Windows_Data_Convert_0_1}
INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's01_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's01_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's01_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'm00_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's01_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'm00_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm00_axis'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axis'.
INFO: [IP_Flow 19-4728] Bus Interface 's01_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's01_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm00_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm00_axis_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axis_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's01_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's01_axi_aresetn'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_Windows_Data_Convert_0_5 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
Reading block design file <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Windows_data_Test/Windows_data_Test.bd>...
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_0
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_1
WARNING: [BD 41-1282] Ignoring parameter HAS_BURST
WARNING: [BD 41-1281] Parameter HAS_BURST is not defined on /axi_dma_1/M_AXIS_MM2S. Setting parameter on /axi_dma_1/M_AXIS_MM2S failed
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_1
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - INACT_DATA_FIFO
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_outw
INFO: [xilinx.com:ip:ila:6.2-6] /ila_outw: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - Picture
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_0
INFO: [xilinx.com:ip:ila:6.2-6] /ila_0: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:module_ref:Windows_Data_Convert_v1_0:1.0 - Windows_Data_Convert_0
Successfully read diagram <Windows_data_Test> from block design file <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Windows_data_Test/Windows_data_Test.bd>
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Windows_data_Test/Windows_data_Test.bd'
INFO: [IP_Flow 19-3420] Updated Windows_data_Test_Windows_Data_Convert_0_1 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Windows_data_Test\Windows_data_Test.bd> 
upgrade_ip: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2782.664 ; gain = 19.863
update_module_reference: Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2782.664 ; gain = 19.863
close_bd_design [get_bd_designs Windows_data_Test]
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Windows_data_Test/ui/bd_22a3e04b.ui> 
update_module_reference {Accelerator_block_design_Windows_Data_Convert_0_5 Windows_data_Test_Windows_Data_Convert_0_1}
INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's01_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axis_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's01_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's01_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'm00_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axis_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's01_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'm00_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm00_axis'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axis'.
INFO: [IP_Flow 19-4728] Bus Interface 's01_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's01_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm00_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm00_axis_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axis_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's01_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's01_axi_aresetn'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_Windows_Data_Convert_0_5 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Reading block design file <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Windows_data_Test/Windows_data_Test.bd>...
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_0
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - axi_dma_1
WARNING: [BD 41-1282] Ignoring parameter HAS_BURST
WARNING: [BD 41-1281] Parameter HAS_BURST is not defined on /axi_dma_1/M_AXIS_MM2S. Setting parameter on /axi_dma_1/M_AXIS_MM2S failed
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_1
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - INACT_DATA_FIFO
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_outw
INFO: [xilinx.com:ip:ila:6.2-6] /ila_outw: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - Picture
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_0
INFO: [xilinx.com:ip:ila:6.2-6] /ila_0: Xilinx recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:module_ref:Windows_Data_Convert_v1_0:1.0 - Windows_Data_Convert_0
Successfully read diagram <Windows_data_Test> from block design file <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Windows_data_Test/Windows_data_Test.bd>
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Windows_data_Test/Windows_data_Test.bd'
INFO: [IP_Flow 19-3420] Updated Windows_data_Test_Windows_Data_Convert_0_1 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Windows_data_Test\Windows_data_Test.bd> 
upgrade_ip: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2798.348 ; gain = 0.000
update_module_reference: Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2798.348 ; gain = 0.000
current_bd_design [get_bd_designs Accelerator_block_design]
current_bd_design [get_bd_designs Windows_data_Test]
close_bd_design [get_bd_designs Windows_data_Test]
validate_bd_design
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to any ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. 
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_S_AXI_ACLK_FREQ_MHZ(100.0) on '/axi_intc_0' with propagated value(50.0). Command ignored
WARNING: [xilinx.com:ip:axi_intc:4.1-7] /axi_intc_0: Interrupts type manual value (0xFFFFFFFF) does not match computed value (0xFFFFFFF0). Please review the manual value or consider using Auto instead.
validate_bd_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2845.113 ; gain = 0.000
save_bd_design
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
reset_run synth_1
INFO: [Project 1-1161] Replacing file E:/Accelerator/Accelerator/Accelerator.srcs/utils_1/imports/synth_1/Conv_SystolicArray.dcp with file E:/Accelerator/Accelerator_100M/Accelerator.runs/synth_1/Accelerator_block_design_wrapper.dcp
reset_run Accelerator_block_design_axi_dma_0_2_synth_1
reset_run Accelerator_block_design_axi_dma_0_3_synth_1
reset_run Accelerator_block_design_axis_data_fifo_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci' is already up-to-date
INFO: [BD 41-1662] The design 'Accelerator_block_design.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
Verilog Output written to : e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/synth/Accelerator_block_design.v
Verilog Output written to : e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/sim/Accelerator_block_design.v
Verilog Output written to : e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/hdl/Accelerator_block_design_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_dma_weight .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_dma_weight_full .
INFO: [BD 41-1029] Generation completed for the IP Integrator block CNN_ACCELERATOR/WEIGHT_FULLCON_FIFO .
INFO: [BD 41-1029] Generation completed for the IP Integrator block CNN_ACCELERATOR/WEIGHT_CONV_ACT_FULLCON_FIFO .
INFO: [BD 41-1029] Generation completed for the IP Integrator block CNN_ACCELERATOR/INACT_DATA_FIFO .
INFO: [BD 41-1029] Generation completed for the IP Integrator block CNN_ACCELERATOR/Windows_Data_Convert_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block CNN_ACCELERATOR/CNN_Control_1 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_s00_data_fifo_0/Accelerator_block_design_s00_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/s00_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_ds_1/Accelerator_block_design_auto_ds_1_ooc.xdc'
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_us_0/Accelerator_block_design_auto_us_0_ooc.xdc'
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s01_couplers/auto_us .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_ds_0/Accelerator_block_design_auto_ds_0_ooc.xdc'
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_pc_0/Accelerator_block_design_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_pc_1/Accelerator_block_design_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_1/s00_couplers/auto_pc .
Exporting to file e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/hw_handoff/Accelerator_block_design.hwh
Generated Hardware Definition File e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/synth/Accelerator_block_design.hwdef
WARNING: [BD 41-2265] Clock pin for protocol instance pin image could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /CNN_ACCELERATOR/CNN_Control_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin result could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /CNN_ACCELERATOR/CNN_Control_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin weight could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /CNN_ACCELERATOR/CNN_Control_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin weightfc could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /CNN_ACCELERATOR/CNN_Control_1
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_ds_0, cache-ID = 54b9edd7788406d3; cache size = 1298.411 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_axis_data_fifo_1_0, cache-ID = d6278f979518fa0f; cache size = 1298.411 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_ds_1, cache-ID = 80d89f872afb5bf6; cache size = 1298.411 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_pc_0, cache-ID = 81e16e67b40e7abf; cache size = 1298.411 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_pc_1, cache-ID = e724e0b0bf1cf8c4; cache size = 1298.411 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_us_0, cache-ID = 38046c7b7941a505; cache size = 1298.411 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_s00_data_fifo_0, cache-ID = d8271c2434b30b6f; cache size = 1298.411 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_axis_data_fifo_0_0, cache-ID = b1315624fbca5560; cache size = 1298.411 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_axis_data_fifo_0_1, cache-ID = d6278f979518fa0f; cache size = 1298.411 MB.
config_ip_cache: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 3009.129 ; gain = 0.000
[Mon Apr 29 23:54:11 2024] Launched Accelerator_block_design_axi_dma_0_2_synth_1, Accelerator_block_design_axi_dma_0_3_synth_1, Accelerator_block_design_Windows_Data_Convert_0_5_synth_1, Accelerator_block_design_CNN_Control_1_0_synth_1, synth_1...
Run output will be captured here:
Accelerator_block_design_axi_dma_0_2_synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/Accelerator_block_design_axi_dma_0_2_synth_1/runme.log
Accelerator_block_design_axi_dma_0_3_synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/Accelerator_block_design_axi_dma_0_3_synth_1/runme.log
Accelerator_block_design_Windows_Data_Convert_0_5_synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/Accelerator_block_design_Windows_Data_Convert_0_5_synth_1/runme.log
Accelerator_block_design_CNN_Control_1_0_synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/Accelerator_block_design_CNN_Control_1_0_synth_1/runme.log
synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/synth_1/runme.log
[Mon Apr 29 23:54:12 2024] Launched impl_1...
Run output will be captured here: E:/Accelerator/Accelerator_100M/Accelerator.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:13 ; elapsed = 00:00:35 . Memory (MB): peak = 3018.980 ; gain = 173.867
update_module_reference Accelerator_block_design_CNN_Control_1_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'image' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'result' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weight' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'weightfc' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'.
WARNING: [IP_Flow 19-3158] Bus Interface 'image': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'result': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weight': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 'weightfc': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/AXI4-LITE_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_package_rtl/CNN_Control'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/CNN_Control/CNN_Control_1.0'.
WARNING: [IP_Flow 19-2207] Repository 'e:/Accelerator/ip_repo/myip_1.0' already exists; ignoring attempt to add it again.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/Accelerator/IP_design/Windows_Data_Convert_1.0'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'e:/Accelerator/ip_repo/Accelerator_Control_1.0'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'f:/Digital_IC_design/dpu_ip'.
Upgrading 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/Accelerator_block_design.bd'
INFO: [IP_Flow 19-3420] Updated Accelerator_block_design_CNN_Control_1_0 to use current project options
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci' is already up-to-date
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to any ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. 
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_S_AXI_ACLK_FREQ_MHZ(100.0) on '/axi_intc_0' with propagated value(50.0). Command ignored
WARNING: [xilinx.com:ip:axi_intc:4.1-7] /axi_intc_0: Interrupts type manual value (0xFFFFFFFF) does not match computed value (0xFFFFFFF0). Please review the manual value or consider using Auto instead.
Wrote  : <E:\Accelerator\Accelerator_100M\Accelerator.srcs\sources_1\bd\Accelerator_block_design\Accelerator_block_design.bd> 
Wrote  : <E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/bd/Accelerator_block_design/ui/bd_ab2a7024.ui> 
Verilog Output written to : e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/synth/Accelerator_block_design.v
Verilog Output written to : e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/sim/Accelerator_block_design.v
Verilog Output written to : e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/hdl/Accelerator_block_design_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block CNN_ACCELERATOR/CNN_Control_1 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_s00_data_fifo_0/Accelerator_block_design_s00_data_fifo_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/s00_data_fifo .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_ds_1/Accelerator_block_design_auto_ds_1_ooc.xdc'
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_us_0/Accelerator_block_design_auto_us_0_ooc.xdc'
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s01_couplers/auto_us .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_ds_0/Accelerator_block_design_auto_ds_0_ooc.xdc'
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_pc_0/Accelerator_block_design_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/ip/Accelerator_block_design_auto_pc_1/Accelerator_block_design_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_1/s00_couplers/auto_pc .
Exporting to file e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/hw_handoff/Accelerator_block_design.hwh
Generated Hardware Definition File e:/Accelerator/Accelerator_100M/Accelerator.gen/sources_1/bd/Accelerator_block_design/synth/Accelerator_block_design.hwdef
WARNING: [BD 41-2265] Clock pin for protocol instance pin image could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /CNN_ACCELERATOR/CNN_Control_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin result could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /CNN_ACCELERATOR/CNN_Control_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin weight could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /CNN_ACCELERATOR/CNN_Control_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin weightfc could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /CNN_ACCELERATOR/CNN_Control_1
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_ds_0, cache-ID = 54b9edd7788406d3; cache size = 1300.638 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_ds_1, cache-ID = 80d89f872afb5bf6; cache size = 1300.638 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_pc_0, cache-ID = 81e16e67b40e7abf; cache size = 1300.638 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_pc_1, cache-ID = e724e0b0bf1cf8c4; cache size = 1300.638 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_auto_us_0, cache-ID = 38046c7b7941a505; cache size = 1300.638 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Accelerator_block_design_s00_data_fifo_0, cache-ID = d8271c2434b30b6f; cache size = 1300.638 MB.
[Tue Apr 30 00:03:37 2024] Launched Accelerator_block_design_CNN_Control_1_0_synth_1, synth_1...
Run output will be captured here:
Accelerator_block_design_CNN_Control_1_0_synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/Accelerator_block_design_CNN_Control_1_0_synth_1/runme.log
synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/synth_1/runme.log
[Tue Apr 30 00:03:37 2024] Launched impl_1...
Run output will be captured here: E:/Accelerator/Accelerator_100M/Accelerator.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:01:01 ; elapsed = 00:01:14 . Memory (MB): peak = 3068.430 ; gain = 28.281
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 8
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'E:/Accelerator/Accelerator_100M/Accelerator.srcs/sources_1/ip/div_gen_0/div_gen_0.xci' is already up-to-date
[Tue Apr 30 00:05:41 2024] Launched Accelerator_block_design_CNN_Control_1_0_synth_1, synth_1...
Run output will be captured here:
Accelerator_block_design_CNN_Control_1_0_synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/Accelerator_block_design_CNN_Control_1_0_synth_1/runme.log
synth_1: E:/Accelerator/Accelerator_100M/Accelerator.runs/synth_1/runme.log
[Tue Apr 30 00:05:41 2024] Launched impl_1...
Run output will be captured here: E:/Accelerator/Accelerator_100M/Accelerator.runs/impl_1/runme.log
exit
INFO: [Common 17-206] Exiting Vivado at Tue Apr 30 00:24:58 2024...