Add support for the use of regfiles in swregs #719
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AndreMerendeira
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Currently the hardware is not generated if log2items != 0 (register array in successive addresses) From the inside of the core, these register files can be read in two ways :
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arturum1
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Sep 12, 2024
If user sets a write register with 'log2n_items' > 0, then csrs.py will generate the regfile inside the csrs module. All registers from regfile can be read in parallel. A port signal is created for each register in the regfile. Example, if we create a CSR, named 'reg', with 'log2n_items' = 2, then the following port signals will be available in the csrs module: reg_0_wr reg_1_wr reg_2_wr reg_3_wr If the user creates a CSR with `autoreg = False`, then the regfile is not generated. The csrs module continues to generate a single port for this regfile, since the signals come from the CPU, and the CPU can only address one register at a time. If the user creates a CSR of type "R" (read register), then the regfile is not generated. This is because read registers should always be implemented by user logic. The csrs module only generates wires to read from the user logic's regfile. Note 1: If we have `autoreg = True`, and type "RW", then the csrs module will generate the regfile for the write part, but will continue to have normal wires for the read part. Note 2: The user logic can find out which register from the regfile is being addressed by using the `iob` output port of the csrs module. (The `iob` output port is always available to user logic, even if csr_if is set to another interface). Related to issues: IObundle#33 IObundle/iob-soc#719
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